indent_size = 8
file_type_emacs = makefile
-[*.{c,h}]
+[*.{c,h,c.inc,h.inc}]
indent_style = space
indent_size = 4
+file_type_emacs = c
[*.sh]
indent_style = space
/ui/shader/texture-blit-frag.h
/ui/shader/texture-blit-vert.h
/ui/shader/texture-blit-flip-vert.h
-/ui/input-keymap-*.c
+/ui/input-keymap-*.c.inc
*-timestamp
/*-softmmu
/*-darwin-user
trace-dtrace-root.dtrace
trace-ust-all.h
trace-ust-all.c
-/target/arm/decode-sve.inc.c
+/target/arm/decode-sve.c.inc
KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv
KEYCODEMAP_FILES = \
- ui/input-keymap-atset1-to-qcode.c \
- ui/input-keymap-linux-to-qcode.c \
- ui/input-keymap-qcode-to-atset1.c \
- ui/input-keymap-qcode-to-atset2.c \
- ui/input-keymap-qcode-to-atset3.c \
- ui/input-keymap-qcode-to-linux.c \
- ui/input-keymap-qcode-to-qnum.c \
- ui/input-keymap-qcode-to-sun.c \
- ui/input-keymap-qnum-to-qcode.c \
- ui/input-keymap-usb-to-qcode.c \
- ui/input-keymap-win32-to-qcode.c \
- ui/input-keymap-x11-to-qcode.c \
- ui/input-keymap-xorgevdev-to-qcode.c \
- ui/input-keymap-xorgkbd-to-qcode.c \
- ui/input-keymap-xorgxquartz-to-qcode.c \
- ui/input-keymap-xorgxwin-to-qcode.c \
- ui/input-keymap-osx-to-qcode.c \
+ ui/input-keymap-atset1-to-qcode.c.inc \
+ ui/input-keymap-linux-to-qcode.c.inc \
+ ui/input-keymap-qcode-to-atset1.c.inc \
+ ui/input-keymap-qcode-to-atset2.c.inc \
+ ui/input-keymap-qcode-to-atset3.c.inc \
+ ui/input-keymap-qcode-to-linux.c.inc \
+ ui/input-keymap-qcode-to-qnum.c.inc \
+ ui/input-keymap-qcode-to-sun.c.inc \
+ ui/input-keymap-qnum-to-qcode.c.inc \
+ ui/input-keymap-usb-to-qcode.c.inc \
+ ui/input-keymap-win32-to-qcode.c.inc \
+ ui/input-keymap-x11-to-qcode.c.inc \
+ ui/input-keymap-xorgevdev-to-qcode.c.inc \
+ ui/input-keymap-xorgkbd-to-qcode.c.inc \
+ ui/input-keymap-xorgxquartz-to-qcode.c.inc \
+ ui/input-keymap-xorgxwin-to-qcode.c.inc \
+ ui/input-keymap-osx-to-qcode.c.inc \
$(NULL)
generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES)
-ui/input-keymap-%.c: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs
+ui/input-keymap-%.c.inc: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs
$(call quiet-command,\
stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \
test -e $(KEYCODEMAP_GEN) && \
--- /dev/null
+/*
+ * Common Atomic Helper Functions
+ *
+ * This file should be included before the various instantiations of
+ * the atomic_template.h helpers.
+ *
+ * Copyright (c) 2019 Linaro
+ * Written by Alex Bennée <alex.bennee@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+static inline
+void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ CPUState *cpu = env_cpu(env);
+
+ trace_guest_mem_before_exec(cpu, addr, info);
+ trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
+}
+
+static inline void
+atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
+}
+
+static inline
+void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+}
+++ /dev/null
-/*
- * Common Atomic Helper Functions
- *
- * This file should be included before the various instantiations of
- * the atomic_template.h helpers.
- *
- * Copyright (c) 2019 Linaro
- * Written by Alex Bennée <alex.bennee@linaro.org>
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-static inline
-void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info)
-{
- CPUState *cpu = env_cpu(env);
-
- trace_guest_mem_before_exec(cpu, addr, info);
- trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
-}
-
-static inline void
-atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info)
-{
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
-}
-
-static inline
-void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info)
-{
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
-}
-
-static inline
-void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info)
-{
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
-}
-
-static inline
-void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info)
-{
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
-}
-
-static inline
-void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info)
-{
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
-}
#define ATOMIC_MMU_CLEANUP
#define ATOMIC_MMU_IDX get_mmuidx(oi)
-#include "atomic_common.inc.c"
+#include "atomic_common.c.inc"
#define DATA_SIZE 1
#include "atomic_template.h"
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
#define EXTRA_ARGS
-#include "atomic_common.inc.c"
+#include "atomic_common.c.inc"
#define DATA_SIZE 1
#include "atomic_template.h"
# (most common languages first
#
filetype code \.c$ # C
-filetype code \.inc.c$ # C
+filetype code \.c.inc$ # C
filetype code \.C$ # C++
filetype code \.cpp$ # C++
filetype code \.c\+\+$ # C++
#define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
#define RCU_READ_LOCK(...) rcu_read_lock()
#define RCU_READ_UNLOCK(...) rcu_read_unlock()
-#include "memory_ldst.inc.c"
+#include "memory_ldst.c.inc"
int64_t address_space_cache_init(MemoryRegionCache *cache,
AddressSpace *as,
#define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
#define RCU_READ_LOCK() ((void)0)
#define RCU_READ_UNLOCK() ((void)0)
-#include "memory_ldst.inc.c"
+#include "memory_ldst.c.inc"
/* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
--- /dev/null
+/*
+ * QEMU float support
+ *
+ * The code in this source file is derived from release 2a of the SoftFloat
+ * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
+ * some later contributions) are provided under that license, as detailed below.
+ * It has subsequently been modified by contributors to the QEMU Project,
+ * so some portions are provided under:
+ * the SoftFloat-2a license
+ * the BSD license
+ * GPL-v2-or-later
+ *
+ * Any future contributions to this file after December 1st 2014 will be
+ * taken to be licensed under the Softfloat-2a license unless specifically
+ * indicated otherwise.
+ */
+
+/*
+===============================================================================
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2a.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
+has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
+TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
+PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
+AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) they include prominent notice that the work is derivative, and (2) they
+include prominent notice akin to these four paragraphs for those parts of
+this code that are retained.
+
+===============================================================================
+*/
+
+/* BSD licensing:
+ * Copyright (c) 2006, Fabrice Bellard
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Portions of this work are licensed under the terms of the GNU GPL,
+ * version 2 or later. See the COPYING file in the top-level directory.
+ */
+
+/* Define for architectures which deviate from IEEE in not supporting
+ * signaling NaNs (so all NaNs are treated as quiet).
+ */
+#if defined(TARGET_XTENSA)
+#define NO_SIGNALING_NANS 1
+#endif
+
+/* Define how the architecture discriminates signaling NaNs.
+ * This done with the most significant bit of the fraction.
+ * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
+ * the msb must be zero. MIPS is (so far) unique in supporting both the
+ * 2008 revision and backward compatibility with their original choice.
+ * Thus for MIPS we must make the choice at runtime.
+ */
+static inline bool snan_bit_is_one(float_status *status)
+{
+#if defined(TARGET_MIPS)
+ return status->snan_bit_is_one;
+#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4)
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| For the deconstructed floating-point with fraction FRAC, return true
+| if the fraction represents a signalling NaN; otherwise false.
+*----------------------------------------------------------------------------*/
+
+static bool parts_is_snan_frac(uint64_t frac, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return false;
+#else
+ bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
+ return msb == snan_bit_is_one(status);
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated deconstructed floating-point NaN.
+*----------------------------------------------------------------------------*/
+
+static FloatParts parts_default_nan(float_status *status)
+{
+ bool sign = 0;
+ uint64_t frac;
+
+#if defined(TARGET_SPARC) || defined(TARGET_M68K)
+ /* !snan_bit_is_one, set all bits */
+ frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
+ || defined(TARGET_MICROBLAZE)
+ /* !snan_bit_is_one, set sign and msb */
+ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
+ sign = 1;
+#elif defined(TARGET_HPPA)
+ /* snan_bit_is_one, set msb-1. */
+ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
+#else
+ /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
+ * S390, SH4, TriCore, and Xtensa. I cannot find documentation
+ * for Unicore32; the choice from the original commit is unchanged.
+ * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
+ * do not have floating-point.
+ */
+ if (snan_bit_is_one(status)) {
+ /* set all bits other than msb */
+ frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
+ } else {
+ /* set msb */
+ frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
+ }
+#endif
+
+ return (FloatParts) {
+ .cls = float_class_qnan,
+ .sign = sign,
+ .exp = INT_MAX,
+ .frac = frac
+ };
+}
+
+/*----------------------------------------------------------------------------
+| Returns a quiet NaN from a signalling NaN for the deconstructed
+| floating-point parts.
+*----------------------------------------------------------------------------*/
+
+static FloatParts parts_silence_nan(FloatParts a, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ g_assert_not_reached();
+#elif defined(TARGET_HPPA)
+ a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
+ a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
+#else
+ if (snan_bit_is_one(status)) {
+ return parts_default_nan(status);
+ } else {
+ a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
+ }
+#endif
+ a.cls = float_class_qnan;
+ return a;
+}
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated extended double-precision NaN.
+*----------------------------------------------------------------------------*/
+floatx80 floatx80_default_nan(float_status *status)
+{
+ floatx80 r;
+
+ /* None of the targets that have snan_bit_is_one use floatx80. */
+ assert(!snan_bit_is_one(status));
+#if defined(TARGET_M68K)
+ r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
+ r.high = 0x7FFF;
+#else
+ /* X86 */
+ r.low = UINT64_C(0xC000000000000000);
+ r.high = 0xFFFF;
+#endif
+ return r;
+}
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated extended double-precision inf.
+*----------------------------------------------------------------------------*/
+
+#define floatx80_infinity_high 0x7FFF
+#if defined(TARGET_M68K)
+#define floatx80_infinity_low UINT64_C(0x0000000000000000)
+#else
+#define floatx80_infinity_low UINT64_C(0x8000000000000000)
+#endif
+
+const floatx80 floatx80_infinity
+ = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'. Floating-point traps can be
+| defined here if desired. It is currently not possible for such a trap
+| to substitute a result value. If traps are not implemented, this routine
+| should be simply `float_exception_flags |= flags;'.
+*----------------------------------------------------------------------------*/
+
+void float_raise(uint8_t flags, float_status *status)
+{
+ status->float_exception_flags |= flags;
+}
+
+/*----------------------------------------------------------------------------
+| Internal canonical NaN format.
+*----------------------------------------------------------------------------*/
+typedef struct {
+ bool sign;
+ uint64_t high, low;
+} commonNaNT;
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float16_is_quiet_nan(float16 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return float16_is_any_nan(a_);
+#else
+ uint16_t a = float16_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ } else {
+ return ((a >> 9) & 0x3F) == 0x3F;
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float16_is_signaling_nan(float16 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return 0;
+#else
+ uint16_t a = float16_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((a >> 9) & 0x3F) == 0x3F;
+ } else {
+ return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float32_is_quiet_nan(float32 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return float32_is_any_nan(a_);
+#else
+ uint32_t a = float32_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
+ } else {
+ return ((uint32_t)(a << 1) >= 0xFF800000);
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float32_is_signaling_nan(float32 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return 0;
+#else
+ uint32_t a = float32_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((uint32_t)(a << 1) >= 0xFF800000);
+ } else {
+ return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the single-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
+{
+ commonNaNT z;
+
+ if (float32_is_signaling_nan(a, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ z.sign = float32_val(a) >> 31;
+ z.low = 0;
+ z.high = ((uint64_t)float32_val(a)) << 41;
+ return z;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the single-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
+{
+ uint32_t mantissa = a.high >> 41;
+
+ if (status->default_nan_mode) {
+ return float32_default_nan(status);
+ }
+
+ if (mantissa) {
+ return make_float32(
+ (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
+ } else {
+ return float32_default_nan(status);
+ }
+}
+
+/*----------------------------------------------------------------------------
+| Select which NaN to propagate for a two-input operation.
+| IEEE754 doesn't specify all the details of this, so the
+| algorithm is target-specific.
+| The routine is passed various bits of information about the
+| two NaNs and should return 0 to select NaN a and 1 for NaN b.
+| Note that signalling NaNs are always squashed to quiet NaNs
+| by the caller, by calling floatXX_silence_nan() before
+| returning them.
+|
+| aIsLargerSignificand is only valid if both a and b are NaNs
+| of some kind, and is true if a has the larger significand,
+| or if both a and b have the same significand but a is
+| positive but b is negative. It is only needed for the x87
+| tie-break rule.
+*----------------------------------------------------------------------------*/
+
+static int pickNaN(FloatClass a_cls, FloatClass b_cls,
+ bool aIsLargerSignificand)
+{
+#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
+ /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
+ * the first of:
+ * 1. A if it is signaling
+ * 2. B if it is signaling
+ * 3. A (quiet)
+ * 4. B (quiet)
+ * A signaling NaN is always quietened before returning it.
+ */
+ /* According to MIPS specifications, if one of the two operands is
+ * a sNaN, a new qNaN has to be generated. This is done in
+ * floatXX_silence_nan(). For qNaN inputs the specifications
+ * says: "When possible, this QNaN result is one of the operand QNaN
+ * values." In practice it seems that most implementations choose
+ * the first operand if both operands are qNaN. In short this gives
+ * the following rules:
+ * 1. A if it is signaling
+ * 2. B if it is signaling
+ * 3. A (quiet)
+ * 4. B (quiet)
+ * A signaling NaN is always silenced before returning it.
+ */
+ if (is_snan(a_cls)) {
+ return 0;
+ } else if (is_snan(b_cls)) {
+ return 1;
+ } else if (is_qnan(a_cls)) {
+ return 0;
+ } else {
+ return 1;
+ }
+#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K)
+ /* PowerPC propagation rules:
+ * 1. A if it sNaN or qNaN
+ * 2. B if it sNaN or qNaN
+ * A signaling NaN is always silenced before returning it.
+ */
+ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
+ * 3.4 FLOATING-POINT INSTRUCTION DETAILS
+ * If either operand, but not both operands, of an operation is a
+ * nonsignaling NaN, then that NaN is returned as the result. If both
+ * operands are nonsignaling NaNs, then the destination operand
+ * nonsignaling NaN is returned as the result.
+ * If either operand to an operation is a signaling NaN (SNaN), then the
+ * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
+ * is set in the FPCR ENABLE byte, then the exception is taken and the
+ * destination is not modified. If the SNaN exception enable bit is not
+ * set, setting the SNaN bit in the operand to a one converts the SNaN to
+ * a nonsignaling NaN. The operation then continues as described in the
+ * preceding paragraph for nonsignaling NaNs.
+ */
+ if (is_nan(a_cls)) {
+ return 0;
+ } else {
+ return 1;
+ }
+#else
+ /* This implements x87 NaN propagation rules:
+ * SNaN + QNaN => return the QNaN
+ * two SNaNs => return the one with the larger significand, silenced
+ * two QNaNs => return the one with the larger significand
+ * SNaN and a non-NaN => return the SNaN, silenced
+ * QNaN and a non-NaN => return the QNaN
+ *
+ * If we get down to comparing significands and they are the same,
+ * return the NaN with the positive sign bit (if any).
+ */
+ if (is_snan(a_cls)) {
+ if (is_snan(b_cls)) {
+ return aIsLargerSignificand ? 0 : 1;
+ }
+ return is_qnan(b_cls) ? 1 : 0;
+ } else if (is_qnan(a_cls)) {
+ if (is_snan(b_cls) || !is_qnan(b_cls)) {
+ return 0;
+ } else {
+ return aIsLargerSignificand ? 0 : 1;
+ }
+ } else {
+ return 1;
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Select which NaN to propagate for a three-input operation.
+| For the moment we assume that no CPU needs the 'larger significand'
+| information.
+| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
+*----------------------------------------------------------------------------*/
+static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
+ bool infzero, float_status *status)
+{
+#if defined(TARGET_ARM)
+ /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
+ * the default NaN
+ */
+ if (infzero && is_qnan(c_cls)) {
+ float_raise(float_flag_invalid, status);
+ return 3;
+ }
+
+ /* This looks different from the ARM ARM pseudocode, because the ARM ARM
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
+ */
+ if (is_snan(c_cls)) {
+ return 2;
+ } else if (is_snan(a_cls)) {
+ return 0;
+ } else if (is_snan(b_cls)) {
+ return 1;
+ } else if (is_qnan(c_cls)) {
+ return 2;
+ } else if (is_qnan(a_cls)) {
+ return 0;
+ } else {
+ return 1;
+ }
+#elif defined(TARGET_MIPS)
+ if (snan_bit_is_one(status)) {
+ /*
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
+ * case sets InvalidOp and returns the default NaN
+ */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return 3;
+ }
+ /* Prefer sNaN over qNaN, in the a, b, c order. */
+ if (is_snan(a_cls)) {
+ return 0;
+ } else if (is_snan(b_cls)) {
+ return 1;
+ } else if (is_snan(c_cls)) {
+ return 2;
+ } else if (is_qnan(a_cls)) {
+ return 0;
+ } else if (is_qnan(b_cls)) {
+ return 1;
+ } else {
+ return 2;
+ }
+ } else {
+ /*
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
+ * case sets InvalidOp and returns the input value 'c'
+ */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return 2;
+ }
+ /* Prefer sNaN over qNaN, in the c, a, b order. */
+ if (is_snan(c_cls)) {
+ return 2;
+ } else if (is_snan(a_cls)) {
+ return 0;
+ } else if (is_snan(b_cls)) {
+ return 1;
+ } else if (is_qnan(c_cls)) {
+ return 2;
+ } else if (is_qnan(a_cls)) {
+ return 0;
+ } else {
+ return 1;
+ }
+ }
+#elif defined(TARGET_PPC)
+ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
+ * to return an input NaN if we have one (ie c) rather than generating
+ * a default NaN
+ */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return 2;
+ }
+
+ /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
+ */
+ if (is_nan(a_cls)) {
+ return 0;
+ } else if (is_nan(c_cls)) {
+ return 2;
+ } else {
+ return 1;
+ }
+#else
+ /* A default implementation: prefer a to b to c.
+ * This is unlikely to actually match any real implementation.
+ */
+ if (is_nan(a_cls)) {
+ return 0;
+ } else if (is_nan(b_cls)) {
+ return 1;
+ } else {
+ return 2;
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Takes two single-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
+{
+ bool aIsLargerSignificand;
+ uint32_t av, bv;
+ FloatClass a_cls, b_cls;
+
+ /* This is not complete, but is good enough for pickNaN. */
+ a_cls = (!float32_is_any_nan(a)
+ ? float_class_normal
+ : float32_is_signaling_nan(a, status)
+ ? float_class_snan
+ : float_class_qnan);
+ b_cls = (!float32_is_any_nan(b)
+ ? float_class_normal
+ : float32_is_signaling_nan(b, status)
+ ? float_class_snan
+ : float_class_qnan);
+
+ av = float32_val(a);
+ bv = float32_val(b);
+
+ if (is_snan(a_cls) || is_snan(b_cls)) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return float32_default_nan(status);
+ }
+
+ if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
+ aIsLargerSignificand = 0;
+ } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (av < bv) ? 1 : 0;
+ }
+
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
+ if (is_snan(b_cls)) {
+ return float32_silence_nan(b, status);
+ }
+ return b;
+ } else {
+ if (is_snan(a_cls)) {
+ return float32_silence_nan(a, status);
+ }
+ return a;
+ }
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float64_is_quiet_nan(float64 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return float64_is_any_nan(a_);
+#else
+ uint64_t a = float64_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 51) & 0xFFF) == 0xFFE)
+ && (a & 0x0007FFFFFFFFFFFFULL);
+ } else {
+ return ((a << 1) >= 0xFFF0000000000000ULL);
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float64_is_signaling_nan(float64 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return 0;
+#else
+ uint64_t a = float64_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((a << 1) >= 0xFFF0000000000000ULL);
+ } else {
+ return (((a >> 51) & 0xFFF) == 0xFFE)
+ && (a & UINT64_C(0x0007FFFFFFFFFFFF));
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the double-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
+{
+ commonNaNT z;
+
+ if (float64_is_signaling_nan(a, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ z.sign = float64_val(a) >> 63;
+ z.low = 0;
+ z.high = float64_val(a) << 12;
+ return z;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the double-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
+{
+ uint64_t mantissa = a.high >> 12;
+
+ if (status->default_nan_mode) {
+ return float64_default_nan(status);
+ }
+
+ if (mantissa) {
+ return make_float64(
+ (((uint64_t) a.sign) << 63)
+ | UINT64_C(0x7FF0000000000000)
+ | (a.high >> 12));
+ } else {
+ return float64_default_nan(status);
+ }
+}
+
+/*----------------------------------------------------------------------------
+| Takes two double-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
+{
+ bool aIsLargerSignificand;
+ uint64_t av, bv;
+ FloatClass a_cls, b_cls;
+
+ /* This is not complete, but is good enough for pickNaN. */
+ a_cls = (!float64_is_any_nan(a)
+ ? float_class_normal
+ : float64_is_signaling_nan(a, status)
+ ? float_class_snan
+ : float_class_qnan);
+ b_cls = (!float64_is_any_nan(b)
+ ? float_class_normal
+ : float64_is_signaling_nan(b, status)
+ ? float_class_snan
+ : float_class_qnan);
+
+ av = float64_val(a);
+ bv = float64_val(b);
+
+ if (is_snan(a_cls) || is_snan(b_cls)) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return float64_default_nan(status);
+ }
+
+ if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
+ aIsLargerSignificand = 0;
+ } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (av < bv) ? 1 : 0;
+ }
+
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
+ if (is_snan(b_cls)) {
+ return float64_silence_nan(b, status);
+ }
+ return b;
+ } else {
+ if (is_snan(a_cls)) {
+ return float64_silence_nan(a, status);
+ }
+ return a;
+ }
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the extended double-precision floating-point value `a' is a
+| quiet NaN; otherwise returns 0. This slightly differs from the same
+| function for other types as floatx80 has an explicit bit.
+*----------------------------------------------------------------------------*/
+
+int floatx80_is_quiet_nan(floatx80 a, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return floatx80_is_any_nan(a);
+#else
+ if (snan_bit_is_one(status)) {
+ uint64_t aLow;
+
+ aLow = a.low & ~0x4000000000000000ULL;
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (aLow << 1)
+ && (a.low == aLow);
+ } else {
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the extended double-precision floating-point value `a' is a
+| signaling NaN; otherwise returns 0. This slightly differs from the same
+| function for other types as floatx80 has an explicit bit.
+*----------------------------------------------------------------------------*/
+
+int floatx80_is_signaling_nan(floatx80 a, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return 0;
+#else
+ if (snan_bit_is_one(status)) {
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && ((a.low << 1) >= 0x8000000000000000ULL);
+ } else {
+ uint64_t aLow;
+
+ aLow = a.low & ~UINT64_C(0x4000000000000000);
+ return ((a.high & 0x7FFF) == 0x7FFF)
+ && (uint64_t)(aLow << 1)
+ && (a.low == aLow);
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns a quiet NaN from a signalling NaN for the extended double-precision
+| floating point value `a'.
+*----------------------------------------------------------------------------*/
+
+floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
+{
+ /* None of the targets that have snan_bit_is_one use floatx80. */
+ assert(!snan_bit_is_one(status));
+ a.low |= UINT64_C(0xC000000000000000);
+ return a;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the extended double-precision floating-
+| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
+{
+ floatx80 dflt;
+ commonNaNT z;
+
+ if (floatx80_is_signaling_nan(a, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ if (a.low >> 63) {
+ z.sign = a.high >> 15;
+ z.low = 0;
+ z.high = a.low << 1;
+ } else {
+ dflt = floatx80_default_nan(status);
+ z.sign = dflt.high >> 15;
+ z.low = 0;
+ z.high = dflt.low << 1;
+ }
+ return z;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the extended
+| double-precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
+{
+ floatx80 z;
+
+ if (status->default_nan_mode) {
+ return floatx80_default_nan(status);
+ }
+
+ if (a.high >> 1) {
+ z.low = UINT64_C(0x8000000000000000) | a.high >> 1;
+ z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
+ } else {
+ z = floatx80_default_nan(status);
+ }
+ return z;
+}
+
+/*----------------------------------------------------------------------------
+| Takes two extended double-precision floating-point values `a' and `b', one
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
+| `b' is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
+{
+ bool aIsLargerSignificand;
+ FloatClass a_cls, b_cls;
+
+ /* This is not complete, but is good enough for pickNaN. */
+ a_cls = (!floatx80_is_any_nan(a)
+ ? float_class_normal
+ : floatx80_is_signaling_nan(a, status)
+ ? float_class_snan
+ : float_class_qnan);
+ b_cls = (!floatx80_is_any_nan(b)
+ ? float_class_normal
+ : floatx80_is_signaling_nan(b, status)
+ ? float_class_snan
+ : float_class_qnan);
+
+ if (is_snan(a_cls) || is_snan(b_cls)) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return floatx80_default_nan(status);
+ }
+
+ if (a.low < b.low) {
+ aIsLargerSignificand = 0;
+ } else if (b.low < a.low) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
+ }
+
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
+ if (is_snan(b_cls)) {
+ return floatx80_silence_nan(b, status);
+ }
+ return b;
+ } else {
+ if (is_snan(a_cls)) {
+ return floatx80_silence_nan(a, status);
+ }
+ return a;
+ }
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float128_is_quiet_nan(float128 a, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return float128_is_any_nan(a);
+#else
+ if (snan_bit_is_one(status)) {
+ return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
+ && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
+ } else {
+ return ((a.high << 1) >= 0xFFFF000000000000ULL)
+ && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the quadruple-precision floating-point value `a' is a
+| signaling NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float128_is_signaling_nan(float128 a, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return 0;
+#else
+ if (snan_bit_is_one(status)) {
+ return ((a.high << 1) >= 0xFFFF000000000000ULL)
+ && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
+ } else {
+ return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
+ && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns a quiet NaN from a signalling NaN for the quadruple-precision
+| floating point value `a'.
+*----------------------------------------------------------------------------*/
+
+float128 float128_silence_nan(float128 a, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ g_assert_not_reached();
+#else
+ if (snan_bit_is_one(status)) {
+ return float128_default_nan(status);
+ } else {
+ a.high |= UINT64_C(0x0000800000000000);
+ return a;
+ }
+#endif
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the quadruple-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
+{
+ commonNaNT z;
+
+ if (float128_is_signaling_nan(a, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ z.sign = a.high >> 63;
+ shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
+ return z;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the quadruple-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
+{
+ float128 z;
+
+ if (status->default_nan_mode) {
+ return float128_default_nan(status);
+ }
+
+ shift128Right(a.high, a.low, 16, &z.high, &z.low);
+ z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000);
+ return z;
+}
+
+/*----------------------------------------------------------------------------
+| Takes two quadruple-precision floating-point values `a' and `b', one of
+| which is a NaN, and returns the appropriate NaN result. If either `a' or
+| `b' is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float128 propagateFloat128NaN(float128 a, float128 b,
+ float_status *status)
+{
+ bool aIsLargerSignificand;
+ FloatClass a_cls, b_cls;
+
+ /* This is not complete, but is good enough for pickNaN. */
+ a_cls = (!float128_is_any_nan(a)
+ ? float_class_normal
+ : float128_is_signaling_nan(a, status)
+ ? float_class_snan
+ : float_class_qnan);
+ b_cls = (!float128_is_any_nan(b)
+ ? float_class_normal
+ : float128_is_signaling_nan(b, status)
+ ? float_class_snan
+ : float_class_qnan);
+
+ if (is_snan(a_cls) || is_snan(b_cls)) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return float128_default_nan(status);
+ }
+
+ if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
+ aIsLargerSignificand = 0;
+ } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
+ }
+
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
+ if (is_snan(b_cls)) {
+ return float128_silence_nan(b, status);
+ }
+ return b;
+ } else {
+ if (is_snan(a_cls)) {
+ return float128_silence_nan(a, status);
+ }
+ return a;
+ }
+}
+++ /dev/null
-/*
- * QEMU float support
- *
- * The code in this source file is derived from release 2a of the SoftFloat
- * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
- * some later contributions) are provided under that license, as detailed below.
- * It has subsequently been modified by contributors to the QEMU Project,
- * so some portions are provided under:
- * the SoftFloat-2a license
- * the BSD license
- * GPL-v2-or-later
- *
- * Any future contributions to this file after December 1st 2014 will be
- * taken to be licensed under the Softfloat-2a license unless specifically
- * indicated otherwise.
- */
-
-/*
-===============================================================================
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 2a.
-
-Written by John R. Hauser. This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704. Funding was partially provided by the
-National Science Foundation under grant MIP-9311980. The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek. More information
-is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
-has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
-TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
-PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
-AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) they include prominent notice that the work is derivative, and (2) they
-include prominent notice akin to these four paragraphs for those parts of
-this code that are retained.
-
-===============================================================================
-*/
-
-/* BSD licensing:
- * Copyright (c) 2006, Fabrice Bellard
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- * may be used to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* Portions of this work are licensed under the terms of the GNU GPL,
- * version 2 or later. See the COPYING file in the top-level directory.
- */
-
-/* Define for architectures which deviate from IEEE in not supporting
- * signaling NaNs (so all NaNs are treated as quiet).
- */
-#if defined(TARGET_XTENSA)
-#define NO_SIGNALING_NANS 1
-#endif
-
-/* Define how the architecture discriminates signaling NaNs.
- * This done with the most significant bit of the fraction.
- * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
- * the msb must be zero. MIPS is (so far) unique in supporting both the
- * 2008 revision and backward compatibility with their original choice.
- * Thus for MIPS we must make the choice at runtime.
- */
-static inline bool snan_bit_is_one(float_status *status)
-{
-#if defined(TARGET_MIPS)
- return status->snan_bit_is_one;
-#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4)
- return 1;
-#else
- return 0;
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| For the deconstructed floating-point with fraction FRAC, return true
-| if the fraction represents a signalling NaN; otherwise false.
-*----------------------------------------------------------------------------*/
-
-static bool parts_is_snan_frac(uint64_t frac, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return false;
-#else
- bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
- return msb == snan_bit_is_one(status);
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated deconstructed floating-point NaN.
-*----------------------------------------------------------------------------*/
-
-static FloatParts parts_default_nan(float_status *status)
-{
- bool sign = 0;
- uint64_t frac;
-
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
- /* !snan_bit_is_one, set all bits */
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
- || defined(TARGET_MICROBLAZE)
- /* !snan_bit_is_one, set sign and msb */
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
- sign = 1;
-#elif defined(TARGET_HPPA)
- /* snan_bit_is_one, set msb-1. */
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
-#else
- /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
- * S390, SH4, TriCore, and Xtensa. I cannot find documentation
- * for Unicore32; the choice from the original commit is unchanged.
- * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
- * do not have floating-point.
- */
- if (snan_bit_is_one(status)) {
- /* set all bits other than msb */
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
- } else {
- /* set msb */
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
- }
-#endif
-
- return (FloatParts) {
- .cls = float_class_qnan,
- .sign = sign,
- .exp = INT_MAX,
- .frac = frac
- };
-}
-
-/*----------------------------------------------------------------------------
-| Returns a quiet NaN from a signalling NaN for the deconstructed
-| floating-point parts.
-*----------------------------------------------------------------------------*/
-
-static FloatParts parts_silence_nan(FloatParts a, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- g_assert_not_reached();
-#elif defined(TARGET_HPPA)
- a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
- a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
-#else
- if (snan_bit_is_one(status)) {
- return parts_default_nan(status);
- } else {
- a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
- }
-#endif
- a.cls = float_class_qnan;
- return a;
-}
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated extended double-precision NaN.
-*----------------------------------------------------------------------------*/
-floatx80 floatx80_default_nan(float_status *status)
-{
- floatx80 r;
-
- /* None of the targets that have snan_bit_is_one use floatx80. */
- assert(!snan_bit_is_one(status));
-#if defined(TARGET_M68K)
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
- r.high = 0x7FFF;
-#else
- /* X86 */
- r.low = UINT64_C(0xC000000000000000);
- r.high = 0xFFFF;
-#endif
- return r;
-}
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated extended double-precision inf.
-*----------------------------------------------------------------------------*/
-
-#define floatx80_infinity_high 0x7FFF
-#if defined(TARGET_M68K)
-#define floatx80_infinity_low UINT64_C(0x0000000000000000)
-#else
-#define floatx80_infinity_low UINT64_C(0x8000000000000000)
-#endif
-
-const floatx80 floatx80_infinity
- = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
-
-/*----------------------------------------------------------------------------
-| Raises the exceptions specified by `flags'. Floating-point traps can be
-| defined here if desired. It is currently not possible for such a trap
-| to substitute a result value. If traps are not implemented, this routine
-| should be simply `float_exception_flags |= flags;'.
-*----------------------------------------------------------------------------*/
-
-void float_raise(uint8_t flags, float_status *status)
-{
- status->float_exception_flags |= flags;
-}
-
-/*----------------------------------------------------------------------------
-| Internal canonical NaN format.
-*----------------------------------------------------------------------------*/
-typedef struct {
- bool sign;
- uint64_t high, low;
-} commonNaNT;
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the half-precision floating-point value `a' is a quiet
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float16_is_quiet_nan(float16 a_, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return float16_is_any_nan(a_);
-#else
- uint16_t a = float16_val(a_);
- if (snan_bit_is_one(status)) {
- return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
- } else {
- return ((a >> 9) & 0x3F) == 0x3F;
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the half-precision floating-point value `a' is a signaling
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float16_is_signaling_nan(float16 a_, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- uint16_t a = float16_val(a_);
- if (snan_bit_is_one(status)) {
- return ((a >> 9) & 0x3F) == 0x3F;
- } else {
- return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the single-precision floating-point value `a' is a quiet
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float32_is_quiet_nan(float32 a_, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return float32_is_any_nan(a_);
-#else
- uint32_t a = float32_val(a_);
- if (snan_bit_is_one(status)) {
- return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
- } else {
- return ((uint32_t)(a << 1) >= 0xFF800000);
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the single-precision floating-point value `a' is a signaling
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float32_is_signaling_nan(float32 a_, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- uint32_t a = float32_val(a_);
- if (snan_bit_is_one(status)) {
- return ((uint32_t)(a << 1) >= 0xFF800000);
- } else {
- return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the single-precision floating-point NaN
-| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
-{
- commonNaNT z;
-
- if (float32_is_signaling_nan(a, status)) {
- float_raise(float_flag_invalid, status);
- }
- z.sign = float32_val(a) >> 31;
- z.low = 0;
- z.high = ((uint64_t)float32_val(a)) << 41;
- return z;
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the single-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
-{
- uint32_t mantissa = a.high >> 41;
-
- if (status->default_nan_mode) {
- return float32_default_nan(status);
- }
-
- if (mantissa) {
- return make_float32(
- (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
- } else {
- return float32_default_nan(status);
- }
-}
-
-/*----------------------------------------------------------------------------
-| Select which NaN to propagate for a two-input operation.
-| IEEE754 doesn't specify all the details of this, so the
-| algorithm is target-specific.
-| The routine is passed various bits of information about the
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
-| Note that signalling NaNs are always squashed to quiet NaNs
-| by the caller, by calling floatXX_silence_nan() before
-| returning them.
-|
-| aIsLargerSignificand is only valid if both a and b are NaNs
-| of some kind, and is true if a has the larger significand,
-| or if both a and b have the same significand but a is
-| positive but b is negative. It is only needed for the x87
-| tie-break rule.
-*----------------------------------------------------------------------------*/
-
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
- bool aIsLargerSignificand)
-{
-#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
- /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
- * the first of:
- * 1. A if it is signaling
- * 2. B if it is signaling
- * 3. A (quiet)
- * 4. B (quiet)
- * A signaling NaN is always quietened before returning it.
- */
- /* According to MIPS specifications, if one of the two operands is
- * a sNaN, a new qNaN has to be generated. This is done in
- * floatXX_silence_nan(). For qNaN inputs the specifications
- * says: "When possible, this QNaN result is one of the operand QNaN
- * values." In practice it seems that most implementations choose
- * the first operand if both operands are qNaN. In short this gives
- * the following rules:
- * 1. A if it is signaling
- * 2. B if it is signaling
- * 3. A (quiet)
- * 4. B (quiet)
- * A signaling NaN is always silenced before returning it.
- */
- if (is_snan(a_cls)) {
- return 0;
- } else if (is_snan(b_cls)) {
- return 1;
- } else if (is_qnan(a_cls)) {
- return 0;
- } else {
- return 1;
- }
-#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K)
- /* PowerPC propagation rules:
- * 1. A if it sNaN or qNaN
- * 2. B if it sNaN or qNaN
- * A signaling NaN is always silenced before returning it.
- */
- /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
- * 3.4 FLOATING-POINT INSTRUCTION DETAILS
- * If either operand, but not both operands, of an operation is a
- * nonsignaling NaN, then that NaN is returned as the result. If both
- * operands are nonsignaling NaNs, then the destination operand
- * nonsignaling NaN is returned as the result.
- * If either operand to an operation is a signaling NaN (SNaN), then the
- * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
- * is set in the FPCR ENABLE byte, then the exception is taken and the
- * destination is not modified. If the SNaN exception enable bit is not
- * set, setting the SNaN bit in the operand to a one converts the SNaN to
- * a nonsignaling NaN. The operation then continues as described in the
- * preceding paragraph for nonsignaling NaNs.
- */
- if (is_nan(a_cls)) {
- return 0;
- } else {
- return 1;
- }
-#else
- /* This implements x87 NaN propagation rules:
- * SNaN + QNaN => return the QNaN
- * two SNaNs => return the one with the larger significand, silenced
- * two QNaNs => return the one with the larger significand
- * SNaN and a non-NaN => return the SNaN, silenced
- * QNaN and a non-NaN => return the QNaN
- *
- * If we get down to comparing significands and they are the same,
- * return the NaN with the positive sign bit (if any).
- */
- if (is_snan(a_cls)) {
- if (is_snan(b_cls)) {
- return aIsLargerSignificand ? 0 : 1;
- }
- return is_qnan(b_cls) ? 1 : 0;
- } else if (is_qnan(a_cls)) {
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
- return 0;
- } else {
- return aIsLargerSignificand ? 0 : 1;
- }
- } else {
- return 1;
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Select which NaN to propagate for a three-input operation.
-| For the moment we assume that no CPU needs the 'larger significand'
-| information.
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
-*----------------------------------------------------------------------------*/
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
- bool infzero, float_status *status)
-{
-#if defined(TARGET_ARM)
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
- * the default NaN
- */
- if (infzero && is_qnan(c_cls)) {
- float_raise(float_flag_invalid, status);
- return 3;
- }
-
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
- */
- if (is_snan(c_cls)) {
- return 2;
- } else if (is_snan(a_cls)) {
- return 0;
- } else if (is_snan(b_cls)) {
- return 1;
- } else if (is_qnan(c_cls)) {
- return 2;
- } else if (is_qnan(a_cls)) {
- return 0;
- } else {
- return 1;
- }
-#elif defined(TARGET_MIPS)
- if (snan_bit_is_one(status)) {
- /*
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
- * case sets InvalidOp and returns the default NaN
- */
- if (infzero) {
- float_raise(float_flag_invalid, status);
- return 3;
- }
- /* Prefer sNaN over qNaN, in the a, b, c order. */
- if (is_snan(a_cls)) {
- return 0;
- } else if (is_snan(b_cls)) {
- return 1;
- } else if (is_snan(c_cls)) {
- return 2;
- } else if (is_qnan(a_cls)) {
- return 0;
- } else if (is_qnan(b_cls)) {
- return 1;
- } else {
- return 2;
- }
- } else {
- /*
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
- * case sets InvalidOp and returns the input value 'c'
- */
- if (infzero) {
- float_raise(float_flag_invalid, status);
- return 2;
- }
- /* Prefer sNaN over qNaN, in the c, a, b order. */
- if (is_snan(c_cls)) {
- return 2;
- } else if (is_snan(a_cls)) {
- return 0;
- } else if (is_snan(b_cls)) {
- return 1;
- } else if (is_qnan(c_cls)) {
- return 2;
- } else if (is_qnan(a_cls)) {
- return 0;
- } else {
- return 1;
- }
- }
-#elif defined(TARGET_PPC)
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
- * to return an input NaN if we have one (ie c) rather than generating
- * a default NaN
- */
- if (infzero) {
- float_raise(float_flag_invalid, status);
- return 2;
- }
-
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
- */
- if (is_nan(a_cls)) {
- return 0;
- } else if (is_nan(c_cls)) {
- return 2;
- } else {
- return 1;
- }
-#else
- /* A default implementation: prefer a to b to c.
- * This is unlikely to actually match any real implementation.
- */
- if (is_nan(a_cls)) {
- return 0;
- } else if (is_nan(b_cls)) {
- return 1;
- } else {
- return 2;
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Takes two single-precision floating-point values `a' and `b', one of which
-| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
-| signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
-{
- bool aIsLargerSignificand;
- uint32_t av, bv;
- FloatClass a_cls, b_cls;
-
- /* This is not complete, but is good enough for pickNaN. */
- a_cls = (!float32_is_any_nan(a)
- ? float_class_normal
- : float32_is_signaling_nan(a, status)
- ? float_class_snan
- : float_class_qnan);
- b_cls = (!float32_is_any_nan(b)
- ? float_class_normal
- : float32_is_signaling_nan(b, status)
- ? float_class_snan
- : float_class_qnan);
-
- av = float32_val(a);
- bv = float32_val(b);
-
- if (is_snan(a_cls) || is_snan(b_cls)) {
- float_raise(float_flag_invalid, status);
- }
-
- if (status->default_nan_mode) {
- return float32_default_nan(status);
- }
-
- if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
- aIsLargerSignificand = 0;
- } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
- aIsLargerSignificand = 1;
- } else {
- aIsLargerSignificand = (av < bv) ? 1 : 0;
- }
-
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
- if (is_snan(b_cls)) {
- return float32_silence_nan(b, status);
- }
- return b;
- } else {
- if (is_snan(a_cls)) {
- return float32_silence_nan(a, status);
- }
- return a;
- }
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the double-precision floating-point value `a' is a quiet
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float64_is_quiet_nan(float64 a_, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return float64_is_any_nan(a_);
-#else
- uint64_t a = float64_val(a_);
- if (snan_bit_is_one(status)) {
- return (((a >> 51) & 0xFFF) == 0xFFE)
- && (a & 0x0007FFFFFFFFFFFFULL);
- } else {
- return ((a << 1) >= 0xFFF0000000000000ULL);
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the double-precision floating-point value `a' is a signaling
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float64_is_signaling_nan(float64 a_, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- uint64_t a = float64_val(a_);
- if (snan_bit_is_one(status)) {
- return ((a << 1) >= 0xFFF0000000000000ULL);
- } else {
- return (((a >> 51) & 0xFFF) == 0xFFE)
- && (a & UINT64_C(0x0007FFFFFFFFFFFF));
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the double-precision floating-point NaN
-| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
-{
- commonNaNT z;
-
- if (float64_is_signaling_nan(a, status)) {
- float_raise(float_flag_invalid, status);
- }
- z.sign = float64_val(a) >> 63;
- z.low = 0;
- z.high = float64_val(a) << 12;
- return z;
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the double-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
-{
- uint64_t mantissa = a.high >> 12;
-
- if (status->default_nan_mode) {
- return float64_default_nan(status);
- }
-
- if (mantissa) {
- return make_float64(
- (((uint64_t) a.sign) << 63)
- | UINT64_C(0x7FF0000000000000)
- | (a.high >> 12));
- } else {
- return float64_default_nan(status);
- }
-}
-
-/*----------------------------------------------------------------------------
-| Takes two double-precision floating-point values `a' and `b', one of which
-| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
-| signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
-{
- bool aIsLargerSignificand;
- uint64_t av, bv;
- FloatClass a_cls, b_cls;
-
- /* This is not complete, but is good enough for pickNaN. */
- a_cls = (!float64_is_any_nan(a)
- ? float_class_normal
- : float64_is_signaling_nan(a, status)
- ? float_class_snan
- : float_class_qnan);
- b_cls = (!float64_is_any_nan(b)
- ? float_class_normal
- : float64_is_signaling_nan(b, status)
- ? float_class_snan
- : float_class_qnan);
-
- av = float64_val(a);
- bv = float64_val(b);
-
- if (is_snan(a_cls) || is_snan(b_cls)) {
- float_raise(float_flag_invalid, status);
- }
-
- if (status->default_nan_mode) {
- return float64_default_nan(status);
- }
-
- if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
- aIsLargerSignificand = 0;
- } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
- aIsLargerSignificand = 1;
- } else {
- aIsLargerSignificand = (av < bv) ? 1 : 0;
- }
-
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
- if (is_snan(b_cls)) {
- return float64_silence_nan(b, status);
- }
- return b;
- } else {
- if (is_snan(a_cls)) {
- return float64_silence_nan(a, status);
- }
- return a;
- }
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is a
-| quiet NaN; otherwise returns 0. This slightly differs from the same
-| function for other types as floatx80 has an explicit bit.
-*----------------------------------------------------------------------------*/
-
-int floatx80_is_quiet_nan(floatx80 a, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return floatx80_is_any_nan(a);
-#else
- if (snan_bit_is_one(status)) {
- uint64_t aLow;
-
- aLow = a.low & ~0x4000000000000000ULL;
- return ((a.high & 0x7FFF) == 0x7FFF)
- && (aLow << 1)
- && (a.low == aLow);
- } else {
- return ((a.high & 0x7FFF) == 0x7FFF)
- && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is a
-| signaling NaN; otherwise returns 0. This slightly differs from the same
-| function for other types as floatx80 has an explicit bit.
-*----------------------------------------------------------------------------*/
-
-int floatx80_is_signaling_nan(floatx80 a, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- if (snan_bit_is_one(status)) {
- return ((a.high & 0x7FFF) == 0x7FFF)
- && ((a.low << 1) >= 0x8000000000000000ULL);
- } else {
- uint64_t aLow;
-
- aLow = a.low & ~UINT64_C(0x4000000000000000);
- return ((a.high & 0x7FFF) == 0x7FFF)
- && (uint64_t)(aLow << 1)
- && (a.low == aLow);
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns a quiet NaN from a signalling NaN for the extended double-precision
-| floating point value `a'.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
-{
- /* None of the targets that have snan_bit_is_one use floatx80. */
- assert(!snan_bit_is_one(status));
- a.low |= UINT64_C(0xC000000000000000);
- return a;
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
-| invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
-{
- floatx80 dflt;
- commonNaNT z;
-
- if (floatx80_is_signaling_nan(a, status)) {
- float_raise(float_flag_invalid, status);
- }
- if (a.low >> 63) {
- z.sign = a.high >> 15;
- z.low = 0;
- z.high = a.low << 1;
- } else {
- dflt = floatx80_default_nan(status);
- z.sign = dflt.high >> 15;
- z.low = 0;
- z.high = dflt.low << 1;
- }
- return z;
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the extended
-| double-precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
-{
- floatx80 z;
-
- if (status->default_nan_mode) {
- return floatx80_default_nan(status);
- }
-
- if (a.high >> 1) {
- z.low = UINT64_C(0x8000000000000000) | a.high >> 1;
- z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
- } else {
- z = floatx80_default_nan(status);
- }
- return z;
-}
-
-/*----------------------------------------------------------------------------
-| Takes two extended double-precision floating-point values `a' and `b', one
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
-| `b' is a signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
-{
- bool aIsLargerSignificand;
- FloatClass a_cls, b_cls;
-
- /* This is not complete, but is good enough for pickNaN. */
- a_cls = (!floatx80_is_any_nan(a)
- ? float_class_normal
- : floatx80_is_signaling_nan(a, status)
- ? float_class_snan
- : float_class_qnan);
- b_cls = (!floatx80_is_any_nan(b)
- ? float_class_normal
- : floatx80_is_signaling_nan(b, status)
- ? float_class_snan
- : float_class_qnan);
-
- if (is_snan(a_cls) || is_snan(b_cls)) {
- float_raise(float_flag_invalid, status);
- }
-
- if (status->default_nan_mode) {
- return floatx80_default_nan(status);
- }
-
- if (a.low < b.low) {
- aIsLargerSignificand = 0;
- } else if (b.low < a.low) {
- aIsLargerSignificand = 1;
- } else {
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
- }
-
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
- if (is_snan(b_cls)) {
- return floatx80_silence_nan(b, status);
- }
- return b;
- } else {
- if (is_snan(a_cls)) {
- return floatx80_silence_nan(a, status);
- }
- return a;
- }
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float128_is_quiet_nan(float128 a, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return float128_is_any_nan(a);
-#else
- if (snan_bit_is_one(status)) {
- return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
- && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
- } else {
- return ((a.high << 1) >= 0xFFFF000000000000ULL)
- && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is a
-| signaling NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-bool float128_is_signaling_nan(float128 a, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- return 0;
-#else
- if (snan_bit_is_one(status)) {
- return ((a.high << 1) >= 0xFFFF000000000000ULL)
- && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
- } else {
- return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
- && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns a quiet NaN from a signalling NaN for the quadruple-precision
-| floating point value `a'.
-*----------------------------------------------------------------------------*/
-
-float128 float128_silence_nan(float128 a, float_status *status)
-{
-#ifdef NO_SIGNALING_NANS
- g_assert_not_reached();
-#else
- if (snan_bit_is_one(status)) {
- return float128_default_nan(status);
- } else {
- a.high |= UINT64_C(0x0000800000000000);
- return a;
- }
-#endif
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point NaN
-| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
-{
- commonNaNT z;
-
- if (float128_is_signaling_nan(a, status)) {
- float_raise(float_flag_invalid, status);
- }
- z.sign = a.high >> 63;
- shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
- return z;
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the quadruple-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
-{
- float128 z;
-
- if (status->default_nan_mode) {
- return float128_default_nan(status);
- }
-
- shift128Right(a.high, a.low, 16, &z.high, &z.low);
- z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000);
- return z;
-}
-
-/*----------------------------------------------------------------------------
-| Takes two quadruple-precision floating-point values `a' and `b', one of
-| which is a NaN, and returns the appropriate NaN result. If either `a' or
-| `b' is a signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static float128 propagateFloat128NaN(float128 a, float128 b,
- float_status *status)
-{
- bool aIsLargerSignificand;
- FloatClass a_cls, b_cls;
-
- /* This is not complete, but is good enough for pickNaN. */
- a_cls = (!float128_is_any_nan(a)
- ? float_class_normal
- : float128_is_signaling_nan(a, status)
- ? float_class_snan
- : float_class_qnan);
- b_cls = (!float128_is_any_nan(b)
- ? float_class_normal
- : float128_is_signaling_nan(b, status)
- ? float_class_snan
- : float_class_qnan);
-
- if (is_snan(a_cls) || is_snan(b_cls)) {
- float_raise(float_flag_invalid, status);
- }
-
- if (status->default_nan_mode) {
- return float128_default_nan(status);
- }
-
- if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
- aIsLargerSignificand = 0;
- } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
- aIsLargerSignificand = 1;
- } else {
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
- }
-
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
- if (is_snan(b_cls)) {
- return float128_silence_nan(b, status);
- }
- return b;
- } else {
- if (is_snan(a_cls)) {
- return float128_silence_nan(a, status);
- }
- return a;
- }
-}
| are propagated from function inputs to output. These details are target-
| specific.
*----------------------------------------------------------------------------*/
-#include "softfloat-specialize.inc.c"
+#include "softfloat-specialize.c.inc"
/* Canonicalize EXP and FRAC, setting CLS. */
static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm,
/* Track which vCPU triggers events */
CPUState *cpu; /* *_trans */
- /* These structures are private to tcg-target.inc.c. */
+ /* These structures are private to tcg-target.c.inc. */
#ifdef TCG_TARGET_NEED_LDST_LABELS
QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
#endif
--- /dev/null
+/*
+ * Physical memory access templates
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2015 Linaro, Inc.
+ * Copyright (c) 2016 Red Hat, Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* warning: addr must be aligned */
+static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
+ enum device_endian endian)
+{
+ uint8_t *ptr;
+ uint64_t val;
+ MemoryRegion *mr;
+ hwaddr l = 4;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
+ if (l < 4 || !memory_access_is_direct(mr, false)) {
+ release_lock |= prepare_mmio_access(mr);
+
+ /* I/O case */
+ r = memory_region_dispatch_read(mr, addr1, &val,
+ MO_32 | devend_memop(endian), attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ switch (endian) {
+ case DEVICE_LITTLE_ENDIAN:
+ val = ldl_le_p(ptr);
+ break;
+ case DEVICE_BIG_ENDIAN:
+ val = ldl_be_p(ptr);
+ break;
+ default:
+ val = ldl_p(ptr);
+ break;
+ }
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+ return val;
+}
+
+uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_NATIVE_ENDIAN);
+}
+
+uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_LITTLE_ENDIAN);
+}
+
+uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_BIG_ENDIAN);
+}
+
+/* warning: addr must be aligned */
+static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
+ enum device_endian endian)
+{
+ uint8_t *ptr;
+ uint64_t val;
+ MemoryRegion *mr;
+ hwaddr l = 8;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
+ if (l < 8 || !memory_access_is_direct(mr, false)) {
+ release_lock |= prepare_mmio_access(mr);
+
+ /* I/O case */
+ r = memory_region_dispatch_read(mr, addr1, &val,
+ MO_64 | devend_memop(endian), attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ switch (endian) {
+ case DEVICE_LITTLE_ENDIAN:
+ val = ldq_le_p(ptr);
+ break;
+ case DEVICE_BIG_ENDIAN:
+ val = ldq_be_p(ptr);
+ break;
+ default:
+ val = ldq_p(ptr);
+ break;
+ }
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+ return val;
+}
+
+uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_NATIVE_ENDIAN);
+}
+
+uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_LITTLE_ENDIAN);
+}
+
+uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_BIG_ENDIAN);
+}
+
+uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ uint8_t *ptr;
+ uint64_t val;
+ MemoryRegion *mr;
+ hwaddr l = 1;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
+ if (!memory_access_is_direct(mr, false)) {
+ release_lock |= prepare_mmio_access(mr);
+
+ /* I/O case */
+ r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ val = ldub_p(ptr);
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+ return val;
+}
+
+/* warning: addr must be aligned */
+static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
+ enum device_endian endian)
+{
+ uint8_t *ptr;
+ uint64_t val;
+ MemoryRegion *mr;
+ hwaddr l = 2;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
+ if (l < 2 || !memory_access_is_direct(mr, false)) {
+ release_lock |= prepare_mmio_access(mr);
+
+ /* I/O case */
+ r = memory_region_dispatch_read(mr, addr1, &val,
+ MO_16 | devend_memop(endian), attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ switch (endian) {
+ case DEVICE_LITTLE_ENDIAN:
+ val = lduw_le_p(ptr);
+ break;
+ case DEVICE_BIG_ENDIAN:
+ val = lduw_be_p(ptr);
+ break;
+ default:
+ val = lduw_p(ptr);
+ break;
+ }
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+ return val;
+}
+
+uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_NATIVE_ENDIAN);
+}
+
+uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_LITTLE_ENDIAN);
+}
+
+uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
+ DEVICE_BIG_ENDIAN);
+}
+
+/* warning: addr must be aligned. The ram page is not masked as dirty
+ and the code inside is not invalidated. It is useful if the dirty
+ bits are used to track modified PTEs */
+void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ uint8_t *ptr;
+ MemoryRegion *mr;
+ hwaddr l = 4;
+ hwaddr addr1;
+ MemTxResult r;
+ uint8_t dirty_log_mask;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
+ if (l < 4 || !memory_access_is_direct(mr, true)) {
+ release_lock |= prepare_mmio_access(mr);
+
+ r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
+ } else {
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ stl_p(ptr, val);
+
+ dirty_log_mask = memory_region_get_dirty_log_mask(mr);
+ dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
+ cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
+ 4, dirty_log_mask);
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+}
+
+/* warning: addr must be aligned */
+static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs,
+ MemTxResult *result, enum device_endian endian)
+{
+ uint8_t *ptr;
+ MemoryRegion *mr;
+ hwaddr l = 4;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
+ if (l < 4 || !memory_access_is_direct(mr, true)) {
+ release_lock |= prepare_mmio_access(mr);
+ r = memory_region_dispatch_write(mr, addr1, val,
+ MO_32 | devend_memop(endian), attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ switch (endian) {
+ case DEVICE_LITTLE_ENDIAN:
+ stl_le_p(ptr, val);
+ break;
+ case DEVICE_BIG_ENDIAN:
+ stl_be_p(ptr, val);
+ break;
+ default:
+ stl_p(ptr, val);
+ break;
+ }
+ invalidate_and_set_dirty(mr, addr1, 4);
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+}
+
+void glue(address_space_stl, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
+ result, DEVICE_NATIVE_ENDIAN);
+}
+
+void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
+ result, DEVICE_LITTLE_ENDIAN);
+}
+
+void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
+ result, DEVICE_BIG_ENDIAN);
+}
+
+void glue(address_space_stb, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ uint8_t *ptr;
+ MemoryRegion *mr;
+ hwaddr l = 1;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
+ if (!memory_access_is_direct(mr, true)) {
+ release_lock |= prepare_mmio_access(mr);
+ r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ stb_p(ptr, val);
+ invalidate_and_set_dirty(mr, addr1, 1);
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+}
+
+/* warning: addr must be aligned */
+static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs,
+ MemTxResult *result, enum device_endian endian)
+{
+ uint8_t *ptr;
+ MemoryRegion *mr;
+ hwaddr l = 2;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
+ if (l < 2 || !memory_access_is_direct(mr, true)) {
+ release_lock |= prepare_mmio_access(mr);
+ r = memory_region_dispatch_write(mr, addr1, val,
+ MO_16 | devend_memop(endian), attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ switch (endian) {
+ case DEVICE_LITTLE_ENDIAN:
+ stw_le_p(ptr, val);
+ break;
+ case DEVICE_BIG_ENDIAN:
+ stw_be_p(ptr, val);
+ break;
+ default:
+ stw_p(ptr, val);
+ break;
+ }
+ invalidate_and_set_dirty(mr, addr1, 2);
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+}
+
+void glue(address_space_stw, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
+ DEVICE_NATIVE_ENDIAN);
+}
+
+void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
+ DEVICE_LITTLE_ENDIAN);
+}
+
+void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
+ DEVICE_BIG_ENDIAN);
+}
+
+static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint64_t val, MemTxAttrs attrs,
+ MemTxResult *result, enum device_endian endian)
+{
+ uint8_t *ptr;
+ MemoryRegion *mr;
+ hwaddr l = 8;
+ hwaddr addr1;
+ MemTxResult r;
+ bool release_lock = false;
+
+ RCU_READ_LOCK();
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
+ if (l < 8 || !memory_access_is_direct(mr, true)) {
+ release_lock |= prepare_mmio_access(mr);
+ r = memory_region_dispatch_write(mr, addr1, val,
+ MO_64 | devend_memop(endian), attrs);
+ } else {
+ /* RAM case */
+ ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
+ switch (endian) {
+ case DEVICE_LITTLE_ENDIAN:
+ stq_le_p(ptr, val);
+ break;
+ case DEVICE_BIG_ENDIAN:
+ stq_be_p(ptr, val);
+ break;
+ default:
+ stq_p(ptr, val);
+ break;
+ }
+ invalidate_and_set_dirty(mr, addr1, 8);
+ r = MEMTX_OK;
+ }
+ if (result) {
+ *result = r;
+ }
+ if (release_lock) {
+ qemu_mutex_unlock_iothread();
+ }
+ RCU_READ_UNLOCK();
+}
+
+void glue(address_space_stq, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
+ DEVICE_NATIVE_ENDIAN);
+}
+
+void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
+ DEVICE_LITTLE_ENDIAN);
+}
+
+void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
+ hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
+ DEVICE_BIG_ENDIAN);
+}
+
+#undef ARG1_DECL
+#undef ARG1
+#undef SUFFIX
+#undef TRANSLATE
+#undef RCU_READ_LOCK
+#undef RCU_READ_UNLOCK
+++ /dev/null
-/*
- * Physical memory access templates
- *
- * Copyright (c) 2003 Fabrice Bellard
- * Copyright (c) 2015 Linaro, Inc.
- * Copyright (c) 2016 Red Hat, Inc.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/* warning: addr must be aligned */
-static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
- enum device_endian endian)
-{
- uint8_t *ptr;
- uint64_t val;
- MemoryRegion *mr;
- hwaddr l = 4;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false, attrs);
- if (l < 4 || !memory_access_is_direct(mr, false)) {
- release_lock |= prepare_mmio_access(mr);
-
- /* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val,
- MO_32 | devend_memop(endian), attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- switch (endian) {
- case DEVICE_LITTLE_ENDIAN:
- val = ldl_le_p(ptr);
- break;
- case DEVICE_BIG_ENDIAN:
- val = ldl_be_p(ptr);
- break;
- default:
- val = ldl_p(ptr);
- break;
- }
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
- return val;
-}
-
-uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_NATIVE_ENDIAN);
-}
-
-uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_LITTLE_ENDIAN);
-}
-
-uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_BIG_ENDIAN);
-}
-
-/* warning: addr must be aligned */
-static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
- enum device_endian endian)
-{
- uint8_t *ptr;
- uint64_t val;
- MemoryRegion *mr;
- hwaddr l = 8;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false, attrs);
- if (l < 8 || !memory_access_is_direct(mr, false)) {
- release_lock |= prepare_mmio_access(mr);
-
- /* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val,
- MO_64 | devend_memop(endian), attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- switch (endian) {
- case DEVICE_LITTLE_ENDIAN:
- val = ldq_le_p(ptr);
- break;
- case DEVICE_BIG_ENDIAN:
- val = ldq_be_p(ptr);
- break;
- default:
- val = ldq_p(ptr);
- break;
- }
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
- return val;
-}
-
-uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_NATIVE_ENDIAN);
-}
-
-uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_LITTLE_ENDIAN);
-}
-
-uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_BIG_ENDIAN);
-}
-
-uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- uint8_t *ptr;
- uint64_t val;
- MemoryRegion *mr;
- hwaddr l = 1;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false, attrs);
- if (!memory_access_is_direct(mr, false)) {
- release_lock |= prepare_mmio_access(mr);
-
- /* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- val = ldub_p(ptr);
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
- return val;
-}
-
-/* warning: addr must be aligned */
-static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
- enum device_endian endian)
-{
- uint8_t *ptr;
- uint64_t val;
- MemoryRegion *mr;
- hwaddr l = 2;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false, attrs);
- if (l < 2 || !memory_access_is_direct(mr, false)) {
- release_lock |= prepare_mmio_access(mr);
-
- /* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val,
- MO_16 | devend_memop(endian), attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- switch (endian) {
- case DEVICE_LITTLE_ENDIAN:
- val = lduw_le_p(ptr);
- break;
- case DEVICE_BIG_ENDIAN:
- val = lduw_be_p(ptr);
- break;
- default:
- val = lduw_p(ptr);
- break;
- }
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
- return val;
-}
-
-uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_NATIVE_ENDIAN);
-}
-
-uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_LITTLE_ENDIAN);
-}
-
-uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
- DEVICE_BIG_ENDIAN);
-}
-
-/* warning: addr must be aligned. The ram page is not masked as dirty
- and the code inside is not invalidated. It is useful if the dirty
- bits are used to track modified PTEs */
-void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- uint8_t *ptr;
- MemoryRegion *mr;
- hwaddr l = 4;
- hwaddr addr1;
- MemTxResult r;
- uint8_t dirty_log_mask;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true, attrs);
- if (l < 4 || !memory_access_is_direct(mr, true)) {
- release_lock |= prepare_mmio_access(mr);
-
- r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
- } else {
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- stl_p(ptr, val);
-
- dirty_log_mask = memory_region_get_dirty_log_mask(mr);
- dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
- cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
- 4, dirty_log_mask);
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
-}
-
-/* warning: addr must be aligned */
-static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs,
- MemTxResult *result, enum device_endian endian)
-{
- uint8_t *ptr;
- MemoryRegion *mr;
- hwaddr l = 4;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true, attrs);
- if (l < 4 || !memory_access_is_direct(mr, true)) {
- release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val,
- MO_32 | devend_memop(endian), attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- switch (endian) {
- case DEVICE_LITTLE_ENDIAN:
- stl_le_p(ptr, val);
- break;
- case DEVICE_BIG_ENDIAN:
- stl_be_p(ptr, val);
- break;
- default:
- stl_p(ptr, val);
- break;
- }
- invalidate_and_set_dirty(mr, addr1, 4);
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
-}
-
-void glue(address_space_stl, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
- result, DEVICE_NATIVE_ENDIAN);
-}
-
-void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
- result, DEVICE_LITTLE_ENDIAN);
-}
-
-void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
- result, DEVICE_BIG_ENDIAN);
-}
-
-void glue(address_space_stb, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- uint8_t *ptr;
- MemoryRegion *mr;
- hwaddr l = 1;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true, attrs);
- if (!memory_access_is_direct(mr, true)) {
- release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- stb_p(ptr, val);
- invalidate_and_set_dirty(mr, addr1, 1);
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
-}
-
-/* warning: addr must be aligned */
-static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs,
- MemTxResult *result, enum device_endian endian)
-{
- uint8_t *ptr;
- MemoryRegion *mr;
- hwaddr l = 2;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true, attrs);
- if (l < 2 || !memory_access_is_direct(mr, true)) {
- release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val,
- MO_16 | devend_memop(endian), attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- switch (endian) {
- case DEVICE_LITTLE_ENDIAN:
- stw_le_p(ptr, val);
- break;
- case DEVICE_BIG_ENDIAN:
- stw_be_p(ptr, val);
- break;
- default:
- stw_p(ptr, val);
- break;
- }
- invalidate_and_set_dirty(mr, addr1, 2);
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
-}
-
-void glue(address_space_stw, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_NATIVE_ENDIAN);
-}
-
-void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_LITTLE_ENDIAN);
-}
-
-void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_BIG_ENDIAN);
-}
-
-static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint64_t val, MemTxAttrs attrs,
- MemTxResult *result, enum device_endian endian)
-{
- uint8_t *ptr;
- MemoryRegion *mr;
- hwaddr l = 8;
- hwaddr addr1;
- MemTxResult r;
- bool release_lock = false;
-
- RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true, attrs);
- if (l < 8 || !memory_access_is_direct(mr, true)) {
- release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val,
- MO_64 | devend_memop(endian), attrs);
- } else {
- /* RAM case */
- ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
- switch (endian) {
- case DEVICE_LITTLE_ENDIAN:
- stq_le_p(ptr, val);
- break;
- case DEVICE_BIG_ENDIAN:
- stq_be_p(ptr, val);
- break;
- default:
- stq_p(ptr, val);
- break;
- }
- invalidate_and_set_dirty(mr, addr1, 8);
- r = MEMTX_OK;
- }
- if (result) {
- *result = r;
- }
- if (release_lock) {
- qemu_mutex_unlock_iothread();
- }
- RCU_READ_UNLOCK();
-}
-
-void glue(address_space_stq, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_NATIVE_ENDIAN);
-}
-
-void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_LITTLE_ENDIAN);
-}
-
-void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
- DEVICE_BIG_ENDIAN);
-}
-
-#undef ARG1_DECL
-#undef ARG1
-#undef SUFFIX
-#undef TRANSLATE
-#undef RCU_READ_LOCK
-#undef RCU_READ_UNLOCK
for f in "$@"; do
case "$f" in
- *.inc.c)
+ *.c.inc)
# These aren't standalone C source files
echo "SKIPPING $f (not a standalone source file)"
continue
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
-target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
+target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
+target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
+target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
+target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
+target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
+target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
+target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
+target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
+target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
+target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
-target/arm/translate-sve.o: target/arm/decode-sve.inc.c
-target/arm/translate.o: target/arm/decode-neon-shared.inc.c
-target/arm/translate.o: target/arm/decode-neon-dp.inc.c
-target/arm/translate.o: target/arm/decode-neon-ls.inc.c
-target/arm/translate.o: target/arm/decode-vfp.inc.c
-target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
-target/arm/translate.o: target/arm/decode-a32.inc.c
-target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
-target/arm/translate.o: target/arm/decode-t32.inc.c
-target/arm/translate.o: target/arm/decode-t16.inc.c
+target/arm/translate-sve.o: target/arm/decode-sve.c.inc
+target/arm/translate.o: target/arm/decode-neon-shared.c.inc
+target/arm/translate.o: target/arm/decode-neon-dp.c.inc
+target/arm/translate.o: target/arm/decode-neon-ls.c.inc
+target/arm/translate.o: target/arm/decode-vfp.c.inc
+target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc
+target/arm/translate.o: target/arm/decode-a32.c.inc
+target/arm/translate.o: target/arm/decode-a32-uncond.c.inc
+target/arm/translate.o: target/arm/decode-t32.c.inc
+target/arm/translate.o: target/arm/decode-t16.c.inc
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
--- /dev/null
+/*
+ * ARM translation: AArch32 Neon instructions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2005-2007 CodeSourcery
+ * Copyright (c) 2007 OpenedHand, Ltd.
+ * Copyright (c) 2020 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file is intended to be included from translate.c; it uses
+ * some macros and definitions provided by that file.
+ * It might be possible to convert it to a standalone .c file eventually.
+ */
+
+static inline int plus1(DisasContext *s, int x)
+{
+ return x + 1;
+}
+
+static inline int rsub_64(DisasContext *s, int x)
+{
+ return 64 - x;
+}
+
+static inline int rsub_32(DisasContext *s, int x)
+{
+ return 32 - x;
+}
+static inline int rsub_16(DisasContext *s, int x)
+{
+ return 16 - x;
+}
+static inline int rsub_8(DisasContext *s, int x)
+{
+ return 8 - x;
+}
+
+/* Include the generated Neon decoder */
+#include "decode-neon-dp.c.inc"
+#include "decode-neon-ls.c.inc"
+#include "decode-neon-shared.c.inc"
+
+/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
+ * where 0 is the least significant end of the register.
+ */
+static inline long
+neon_element_offset(int reg, int element, MemOp size)
+{
+ int element_size = 1 << size;
+ int ofs = element * element_size;
+#ifdef HOST_WORDS_BIGENDIAN
+ /* Calculate the offset assuming fully little-endian,
+ * then XOR to account for the order of the 8-byte units.
+ */
+ if (element_size < 8) {
+ ofs ^= 8 - element_size;
+ }
+#endif
+ return neon_reg_offset(reg, 0) + ofs;
+}
+
+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
+{
+ long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
+
+ switch (mop) {
+ case MO_UB:
+ tcg_gen_ld8u_i32(var, cpu_env, offset);
+ break;
+ case MO_UW:
+ tcg_gen_ld16u_i32(var, cpu_env, offset);
+ break;
+ case MO_UL:
+ tcg_gen_ld_i32(var, cpu_env, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
+{
+ long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
+
+ switch (mop) {
+ case MO_UB:
+ tcg_gen_ld8u_i64(var, cpu_env, offset);
+ break;
+ case MO_UW:
+ tcg_gen_ld16u_i64(var, cpu_env, offset);
+ break;
+ case MO_UL:
+ tcg_gen_ld32u_i64(var, cpu_env, offset);
+ break;
+ case MO_Q:
+ tcg_gen_ld_i64(var, cpu_env, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
+{
+ long offset = neon_element_offset(reg, ele, size);
+
+ switch (size) {
+ case MO_8:
+ tcg_gen_st8_i32(var, cpu_env, offset);
+ break;
+ case MO_16:
+ tcg_gen_st16_i32(var, cpu_env, offset);
+ break;
+ case MO_32:
+ tcg_gen_st_i32(var, cpu_env, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
+{
+ long offset = neon_element_offset(reg, ele, size);
+
+ switch (size) {
+ case MO_8:
+ tcg_gen_st8_i64(var, cpu_env, offset);
+ break;
+ case MO_16:
+ tcg_gen_st16_i64(var, cpu_env, offset);
+ break;
+ case MO_32:
+ tcg_gen_st32_i64(var, cpu_env, offset);
+ break;
+ case MO_64:
+ tcg_gen_st_i64(var, cpu_env, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
+{
+ int opr_sz;
+ TCGv_ptr fpst;
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+ if (!dc_isar_feature(aa32_vcma, s)
+ || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz = (1 + a->q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->vm),
+ fpst, opr_sz, opr_sz, a->rot,
+ fn_gvec_ptr);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
+{
+ int opr_sz;
+ TCGv_ptr fpst;
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+ if (!dc_isar_feature(aa32_vcma, s)
+ || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz = (1 + a->q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->vm),
+ fpst, opr_sz, opr_sz, a->rot,
+ fn_gvec_ptr);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
+{
+ int opr_sz;
+ gen_helper_gvec_3 *fn_gvec;
+
+ if (!dc_isar_feature(aa32_dp, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz = (1 + a->q) * 8;
+ fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->vm),
+ opr_sz, opr_sz, 0, fn_gvec);
+ return true;
+}
+
+static bool trans_VFML(DisasContext *s, arg_VFML *a)
+{
+ int opr_sz;
+
+ if (!dc_isar_feature(aa32_fhm, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz = (1 + a->q) * 8;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(a->q, a->vn),
+ vfp_reg_offset(a->q, a->vm),
+ cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
+ gen_helper_gvec_fmlal_a32);
+ return true;
+}
+
+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
+{
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
+ int opr_sz;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_vcma, s)) {
+ return false;
+ }
+ if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd | a->vn) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
+ : gen_helper_gvec_fcmlah_idx);
+ opr_sz = (1 + a->q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->vm),
+ fpst, opr_sz, opr_sz,
+ (a->index << 2) | a->rot, fn_gvec_ptr);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
+{
+ gen_helper_gvec_3 *fn_gvec;
+ int opr_sz;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_dp, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd | a->vn) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
+ opr_sz = (1 + a->q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->rm),
+ opr_sz, opr_sz, a->index, fn_gvec);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
+{
+ int opr_sz;
+
+ if (!dc_isar_feature(aa32_fhm, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
+ return false;
+ }
+
+ if (a->vd & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz = (1 + a->q) * 8;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(a->q, a->vn),
+ vfp_reg_offset(a->q, a->rm),
+ cpu_env, opr_sz, opr_sz,
+ (a->index << 2) | a->s, /* is_2 == 0 */
+ gen_helper_gvec_fmlal_idx_a32);
+ return true;
+}
+
+static struct {
+ int nregs;
+ int interleave;
+ int spacing;
+} const neon_ls_element_type[11] = {
+ {1, 4, 1},
+ {1, 4, 2},
+ {4, 1, 1},
+ {2, 2, 2},
+ {1, 3, 1},
+ {1, 3, 2},
+ {3, 1, 1},
+ {1, 1, 1},
+ {1, 2, 1},
+ {1, 2, 2},
+ {2, 1, 1}
+};
+
+static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
+ int stride)
+{
+ if (rm != 15) {
+ TCGv_i32 base;
+
+ base = load_reg(s, rn);
+ if (rm == 13) {
+ tcg_gen_addi_i32(base, base, stride);
+ } else {
+ TCGv_i32 index;
+ index = load_reg(s, rm);
+ tcg_gen_add_i32(base, base, index);
+ tcg_temp_free_i32(index);
+ }
+ store_reg(s, rn, base);
+ }
+}
+
+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
+{
+ /* Neon load/store multiple structures */
+ int nregs, interleave, spacing, reg, n;
+ MemOp endian = s->be_data;
+ int mmu_idx = get_mem_index(s);
+ int size = a->size;
+ TCGv_i64 tmp64;
+ TCGv_i32 addr, tmp;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+ if (a->itype > 10) {
+ return false;
+ }
+ /* Catch UNDEF cases for bad values of align field */
+ switch (a->itype & 0xc) {
+ case 4:
+ if (a->align >= 2) {
+ return false;
+ }
+ break;
+ case 8:
+ if (a->align == 3) {
+ return false;
+ }
+ break;
+ default:
+ break;
+ }
+ nregs = neon_ls_element_type[a->itype].nregs;
+ interleave = neon_ls_element_type[a->itype].interleave;
+ spacing = neon_ls_element_type[a->itype].spacing;
+ if (size == 3 && (interleave | spacing) != 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /* For our purposes, bytes are always little-endian. */
+ if (size == 0) {
+ endian = MO_LE;
+ }
+ /*
+ * Consecutive little-endian elements from a single register
+ * can be promoted to a larger little-endian operation.
+ */
+ if (interleave == 1 && endian == MO_LE) {
+ size = 3;
+ }
+ tmp64 = tcg_temp_new_i64();
+ addr = tcg_temp_new_i32();
+ tmp = tcg_const_i32(1 << size);
+ load_reg_var(s, addr, a->rn);
+ for (reg = 0; reg < nregs; reg++) {
+ for (n = 0; n < 8 >> size; n++) {
+ int xs;
+ for (xs = 0; xs < interleave; xs++) {
+ int tt = a->vd + reg + spacing * xs;
+
+ if (a->l) {
+ gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+ neon_store_element64(tt, n, size, tmp64);
+ } else {
+ neon_load_element64(tmp64, tt, n, size);
+ gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+ }
+ tcg_gen_add_i32(addr, addr, tmp);
+ }
+ }
+ }
+ tcg_temp_free_i32(addr);
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i64(tmp64);
+
+ gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
+ return true;
+}
+
+static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
+{
+ /* Neon load single structure to all lanes */
+ int reg, stride, vec_size;
+ int vd = a->vd;
+ int size = a->size;
+ int nregs = a->n + 1;
+ TCGv_i32 addr, tmp;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (size == 3) {
+ if (nregs != 4 || a->a == 0) {
+ return false;
+ }
+ /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */
+ size = 2;
+ }
+ if (nregs == 1 && a->a == 1 && size == 0) {
+ return false;
+ }
+ if (nregs == 3 && a->a == 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /*
+ * VLD1 to all lanes: T bit indicates how many Dregs to write.
+ * VLD2/3/4 to all lanes: T bit indicates register stride.
+ */
+ stride = a->t ? 2 : 1;
+ vec_size = nregs == 1 ? stride * 8 : 8;
+
+ tmp = tcg_temp_new_i32();
+ addr = tcg_temp_new_i32();
+ load_reg_var(s, addr, a->rn);
+ for (reg = 0; reg < nregs; reg++) {
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ s->be_data | size);
+ if ((vd & 1) && vec_size == 16) {
+ /*
+ * We cannot write 16 bytes at once because the
+ * destination is unaligned.
+ */
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
+ 8, 8, tmp);
+ tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
+ neon_reg_offset(vd, 0), 8, 8);
+ } else {
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
+ vec_size, vec_size, tmp);
+ }
+ tcg_gen_addi_i32(addr, addr, 1 << size);
+ vd += stride;
+ }
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(addr);
+
+ gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs);
+
+ return true;
+}
+
+static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
+{
+ /* Neon load/store single structure to one lane */
+ int reg;
+ int nregs = a->n + 1;
+ int vd = a->vd;
+ TCGv_i32 addr, tmp;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ /* Catch the UNDEF cases. This is unavoidably a bit messy. */
+ switch (nregs) {
+ case 1:
+ if (((a->align & (1 << a->size)) != 0) ||
+ (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+ return false;
+ }
+ break;
+ case 3:
+ if ((a->align & 1) != 0) {
+ return false;
+ }
+ /* fall through */
+ case 2:
+ if (a->size == 2 && (a->align & 2) != 0) {
+ return false;
+ }
+ break;
+ case 4:
+ if ((a->size == 2) && ((a->align & 3) == 3)) {
+ return false;
+ }
+ break;
+ default:
+ abort();
+ }
+ if ((vd + a->stride * (nregs - 1)) > 31) {
+ /*
+ * Attempts to write off the end of the register file are
+ * UNPREDICTABLE; we choose to UNDEF because otherwise we would
+ * access off the end of the array that holds the register data.
+ */
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i32();
+ addr = tcg_temp_new_i32();
+ load_reg_var(s, addr, a->rn);
+ /*
+ * TODO: if we implemented alignment exceptions, we should check
+ * addr against the alignment encoded in a->align here.
+ */
+ for (reg = 0; reg < nregs; reg++) {
+ if (a->l) {
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ s->be_data | a->size);
+ neon_store_element(vd, a->reg_idx, a->size, tmp);
+ } else { /* Store */
+ neon_load_element(tmp, vd, a->reg_idx, a->size);
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
+ s->be_data | a->size);
+ }
+ vd += a->stride;
+ tcg_gen_addi_i32(addr, addr, 1 << a->size);
+ }
+ tcg_temp_free_i32(addr);
+ tcg_temp_free_i32(tmp);
+
+ gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
+
+ return true;
+}
+
+static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
+{
+ int vec_size = a->q ? 16 : 8;
+ int rd_ofs = neon_reg_offset(a->vd, 0);
+ int rn_ofs = neon_reg_offset(a->vn, 0);
+ int rm_ofs = neon_reg_offset(a->vm, 0);
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
+ return true;
+}
+
+#define DO_3SAME(INSN, FUNC) \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ return do_3same(s, a, FUNC); \
+ }
+
+DO_3SAME(VADD, tcg_gen_gvec_add)
+DO_3SAME(VSUB, tcg_gen_gvec_sub)
+DO_3SAME(VAND, tcg_gen_gvec_and)
+DO_3SAME(VBIC, tcg_gen_gvec_andc)
+DO_3SAME(VORR, tcg_gen_gvec_or)
+DO_3SAME(VORN, tcg_gen_gvec_orc)
+DO_3SAME(VEOR, tcg_gen_gvec_xor)
+DO_3SAME(VSHL_S, gen_gvec_sshl)
+DO_3SAME(VSHL_U, gen_gvec_ushl)
+DO_3SAME(VQADD_S, gen_gvec_sqadd_qc)
+DO_3SAME(VQADD_U, gen_gvec_uqadd_qc)
+DO_3SAME(VQSUB_S, gen_gvec_sqsub_qc)
+DO_3SAME(VQSUB_U, gen_gvec_uqsub_qc)
+
+/* These insns are all gvec_bitsel but with the inputs in various orders. */
+#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \
+ } \
+ DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
+DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
+DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
+
+#define DO_3SAME_NO_SZ_3(INSN, FUNC) \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size == 3) { \
+ return false; \
+ } \
+ return do_3same(s, a, FUNC); \
+ }
+
+DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
+DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
+DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
+DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
+DO_3SAME_NO_SZ_3(VMLA, gen_gvec_mla)
+DO_3SAME_NO_SZ_3(VMLS, gen_gvec_mls)
+DO_3SAME_NO_SZ_3(VTST, gen_gvec_cmtst)
+DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd)
+DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba)
+DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd)
+DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba)
+
+#define DO_3SAME_CMP(INSN, COND) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
+ } \
+ DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
+
+DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
+DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
+DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
+DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
+DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
+
+#define WRAP_OOL_FN(WRAPNAME, FUNC) \
+ static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \
+ uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \
+ { \
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
+ }
+
+WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
+
+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
+{
+ if (a->size != 0) {
+ return false;
+ }
+ return do_3same(s, a, gen_VMUL_p_3s);
+}
+
+#define DO_VQRDMLAH(INSN, FUNC) \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (!dc_isar_feature(aa32_rdm, s)) { \
+ return false; \
+ } \
+ if (a->size != 1 && a->size != 2) { \
+ return false; \
+ } \
+ return do_3same(s, a, FUNC); \
+ }
+
+DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
+DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
+
+#define DO_SHA1(NAME, FUNC) \
+ WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
+ static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (!dc_isar_feature(aa32_sha1, s)) { \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##NAME##_3s); \
+ }
+
+DO_SHA1(SHA1C, gen_helper_crypto_sha1c)
+DO_SHA1(SHA1P, gen_helper_crypto_sha1p)
+DO_SHA1(SHA1M, gen_helper_crypto_sha1m)
+DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0)
+
+#define DO_SHA2(NAME, FUNC) \
+ WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
+ static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (!dc_isar_feature(aa32_sha2, s)) { \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##NAME##_3s); \
+ }
+
+DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
+DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
+DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
+
+#define DO_3SAME_64(INSN, FUNC) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ static const GVecGen3 op = { .fni8 = FUNC }; \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &op); \
+ } \
+ DO_3SAME(INSN, gen_##INSN##_3s)
+
+#define DO_3SAME_64_ENV(INSN, FUNC) \
+ static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \
+ { \
+ FUNC(d, cpu_env, n, m); \
+ } \
+ DO_3SAME_64(INSN, gen_##INSN##_elt)
+
+DO_3SAME_64(VRSHL_S64, gen_helper_neon_rshl_s64)
+DO_3SAME_64(VRSHL_U64, gen_helper_neon_rshl_u64)
+DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64)
+DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64)
+DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64)
+DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
+
+#define DO_3SAME_32(INSN, FUNC) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ static const GVecGen3 ops[4] = { \
+ { .fni4 = gen_helper_neon_##FUNC##8 }, \
+ { .fni4 = gen_helper_neon_##FUNC##16 }, \
+ { .fni4 = gen_helper_neon_##FUNC##32 }, \
+ { 0 }, \
+ }; \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \
+ } \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size > 2) { \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##INSN##_3s); \
+ }
+
+/*
+ * Some helper functions need to be passed the cpu_env. In order
+ * to use those with the gvec APIs like tcg_gen_gvec_3() we need
+ * to create wrapper functions whose prototype is a NeonGenTwoOpFn()
+ * and which call a NeonGenTwoOpEnvFn().
+ */
+#define WRAP_ENV_FN(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \
+ { \
+ FUNC(d, cpu_env, n, m); \
+ }
+
+#define DO_3SAME_32_ENV(INSN, FUNC) \
+ WRAP_ENV_FN(gen_##INSN##_tramp8, gen_helper_neon_##FUNC##8); \
+ WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##16); \
+ WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##32); \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ static const GVecGen3 ops[4] = { \
+ { .fni4 = gen_##INSN##_tramp8 }, \
+ { .fni4 = gen_##INSN##_tramp16 }, \
+ { .fni4 = gen_##INSN##_tramp32 }, \
+ { 0 }, \
+ }; \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \
+ } \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size > 2) { \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##INSN##_3s); \
+ }
+
+DO_3SAME_32(VHADD_S, hadd_s)
+DO_3SAME_32(VHADD_U, hadd_u)
+DO_3SAME_32(VHSUB_S, hsub_s)
+DO_3SAME_32(VHSUB_U, hsub_u)
+DO_3SAME_32(VRHADD_S, rhadd_s)
+DO_3SAME_32(VRHADD_U, rhadd_u)
+DO_3SAME_32(VRSHL_S, rshl_s)
+DO_3SAME_32(VRSHL_U, rshl_u)
+
+DO_3SAME_32_ENV(VQSHL_S, qshl_s)
+DO_3SAME_32_ENV(VQSHL_U, qshl_u)
+DO_3SAME_32_ENV(VQRSHL_S, qrshl_s)
+DO_3SAME_32_ENV(VQRSHL_U, qrshl_u)
+
+static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
+{
+ /* Operations handled pairwise 32 bits at a time */
+ TCGv_i32 tmp, tmp2, tmp3;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size == 3) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ assert(a->q == 0); /* enforced by decode patterns */
+
+ /*
+ * Note that we have to be careful not to clobber the source operands
+ * in the "vm == vd" case by storing the result of the first pass too
+ * early. Since Q is 0 there are always just two passes, so instead
+ * of a complicated loop over each pass we just unroll.
+ */
+ tmp = neon_load_reg(a->vn, 0);
+ tmp2 = neon_load_reg(a->vn, 1);
+ fn(tmp, tmp, tmp2);
+ tcg_temp_free_i32(tmp2);
+
+ tmp3 = neon_load_reg(a->vm, 0);
+ tmp2 = neon_load_reg(a->vm, 1);
+ fn(tmp3, tmp3, tmp2);
+ tcg_temp_free_i32(tmp2);
+
+ neon_store_reg(a->vd, 0, tmp);
+ neon_store_reg(a->vd, 1, tmp3);
+ return true;
+}
+
+#define DO_3SAME_PAIR(INSN, func) \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ static NeonGenTwoOpFn * const fns[] = { \
+ gen_helper_neon_##func##8, \
+ gen_helper_neon_##func##16, \
+ gen_helper_neon_##func##32, \
+ }; \
+ if (a->size > 2) { \
+ return false; \
+ } \
+ return do_3same_pair(s, a, fns[a->size]); \
+ }
+
+/* 32-bit pairwise ops end up the same as the elementwise versions. */
+#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32
+#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
+#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
+#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
+#define gen_helper_neon_padd_u32 tcg_gen_add_i32
+
+DO_3SAME_PAIR(VPMAX_S, pmax_s)
+DO_3SAME_PAIR(VPMIN_S, pmin_s)
+DO_3SAME_PAIR(VPMAX_U, pmax_u)
+DO_3SAME_PAIR(VPMIN_U, pmin_u)
+DO_3SAME_PAIR(VPADD, padd_u)
+
+#define DO_3SAME_VQDMULH(INSN, FUNC) \
+ WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \
+ WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ static const GVecGen3 ops[2] = { \
+ { .fni4 = gen_##INSN##_tramp16 }, \
+ { .fni4 = gen_##INSN##_tramp32 }, \
+ }; \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \
+ } \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size != 1 && a->size != 2) { \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##INSN##_3s); \
+ }
+
+DO_3SAME_VQDMULH(VQDMULH, qdmulh)
+DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
+
+static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn,
+ bool reads_vd)
+{
+ /*
+ * FP operations handled elementwise 32 bits at a time.
+ * If reads_vd is true then the old value of Vd will be
+ * loaded before calling the callback function. This is
+ * used for multiply-accumulate type operations.
+ */
+ TCGv_i32 tmp, tmp2;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ tmp = neon_load_reg(a->vn, pass);
+ tmp2 = neon_load_reg(a->vm, pass);
+ if (reads_vd) {
+ TCGv_i32 tmp_rd = neon_load_reg(a->vd, pass);
+ fn(tmp_rd, tmp, tmp2, fpstatus);
+ neon_store_reg(a->vd, pass, tmp_rd);
+ tcg_temp_free_i32(tmp);
+ } else {
+ fn(tmp, tmp, tmp2, fpstatus);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ tcg_temp_free_i32(tmp2);
+ }
+ tcg_temp_free_ptr(fpstatus);
+ return true;
+}
+
+/*
+ * For all the functions using this macro, size == 1 means fp16,
+ * which is an architecture extension we don't implement yet.
+ */
+#define DO_3S_FP_GVEC(INSN,FUNC) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ TCGv_ptr fpst = get_fpstatus_ptr(1); \
+ tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \
+ oprsz, maxsz, 0, FUNC); \
+ tcg_temp_free_ptr(fpst); \
+ } \
+ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size != 0) { \
+ /* TODO fp16 support */ \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##INSN##_3s); \
+ }
+
+
+DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)
+DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)
+DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)
+DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s)
+
+/*
+ * For all the functions using this macro, size == 1 means fp16,
+ * which is an architecture extension we don't implement yet.
+ */
+#define DO_3S_FP(INSN,FUNC,READS_VD) \
+ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size != 0) { \
+ /* TODO fp16 support */ \
+ return false; \
+ } \
+ return do_3same_fp(s, a, FUNC, READS_VD); \
+ }
+
+DO_3S_FP(VCEQ, gen_helper_neon_ceq_f32, false)
+DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false)
+DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false)
+DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false)
+DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false)
+DO_3S_FP(VMAX, gen_helper_vfp_maxs, false)
+DO_3S_FP(VMIN, gen_helper_vfp_mins, false)
+
+static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
+ TCGv_ptr fpstatus)
+{
+ gen_helper_vfp_muls(vn, vn, vm, fpstatus);
+ gen_helper_vfp_adds(vd, vd, vn, fpstatus);
+}
+
+static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
+ TCGv_ptr fpstatus)
+{
+ gen_helper_vfp_muls(vn, vn, vm, fpstatus);
+ gen_helper_vfp_subs(vd, vd, vn, fpstatus);
+}
+
+DO_3S_FP(VMLA, gen_VMLA_fp_3s, true)
+DO_3S_FP(VMLS, gen_VMLS_fp_3s, true)
+
+static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+
+ if (a->size != 0) {
+ /* TODO fp16 support */
+ return false;
+ }
+
+ return do_3same_fp(s, a, gen_helper_vfp_maxnums, false);
+}
+
+static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+
+ if (a->size != 0) {
+ /* TODO fp16 support */
+ return false;
+ }
+
+ return do_3same_fp(s, a, gen_helper_vfp_minnums, false);
+}
+
+WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32)
+
+static void gen_VRECPS_fp_3s(unsigned vece, uint32_t rd_ofs,
+ uint32_t rn_ofs, uint32_t rm_ofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp };
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);
+}
+
+static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a)
+{
+ if (a->size != 0) {
+ /* TODO fp16 support */
+ return false;
+ }
+
+ return do_3same(s, a, gen_VRECPS_fp_3s);
+}
+
+WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32)
+
+static void gen_VRSQRTS_fp_3s(unsigned vece, uint32_t rd_ofs,
+ uint32_t rn_ofs, uint32_t rm_ofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 ops = { .fni4 = gen_VRSQRTS_tramp };
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);
+}
+
+static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a)
+{
+ if (a->size != 0) {
+ /* TODO fp16 support */
+ return false;
+ }
+
+ return do_3same(s, a, gen_VRSQRTS_fp_3s);
+}
+
+static void gen_VFMA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
+ TCGv_ptr fpstatus)
+{
+ gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus);
+}
+
+static bool trans_VFMA_fp_3s(DisasContext *s, arg_3same *a)
+{
+ if (!dc_isar_feature(aa32_simdfmac, s)) {
+ return false;
+ }
+
+ if (a->size != 0) {
+ /* TODO fp16 support */
+ return false;
+ }
+
+ return do_3same_fp(s, a, gen_VFMA_fp_3s, true);
+}
+
+static void gen_VFMS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
+ TCGv_ptr fpstatus)
+{
+ gen_helper_vfp_negs(vn, vn);
+ gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus);
+}
+
+static bool trans_VFMS_fp_3s(DisasContext *s, arg_3same *a)
+{
+ if (!dc_isar_feature(aa32_simdfmac, s)) {
+ return false;
+ }
+
+ if (a->size != 0) {
+ /* TODO fp16 support */
+ return false;
+ }
+
+ return do_3same_fp(s, a, gen_VFMS_fp_3s, true);
+}
+
+static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
+{
+ /* FP operations handled pairwise 32 bits at a time */
+ TCGv_i32 tmp, tmp2, tmp3;
+ TCGv_ptr fpstatus;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ assert(a->q == 0); /* enforced by decode patterns */
+
+ /*
+ * Note that we have to be careful not to clobber the source operands
+ * in the "vm == vd" case by storing the result of the first pass too
+ * early. Since Q is 0 there are always just two passes, so instead
+ * of a complicated loop over each pass we just unroll.
+ */
+ fpstatus = get_fpstatus_ptr(1);
+ tmp = neon_load_reg(a->vn, 0);
+ tmp2 = neon_load_reg(a->vn, 1);
+ fn(tmp, tmp, tmp2, fpstatus);
+ tcg_temp_free_i32(tmp2);
+
+ tmp3 = neon_load_reg(a->vm, 0);
+ tmp2 = neon_load_reg(a->vm, 1);
+ fn(tmp3, tmp3, tmp2, fpstatus);
+ tcg_temp_free_i32(tmp2);
+ tcg_temp_free_ptr(fpstatus);
+
+ neon_store_reg(a->vd, 0, tmp);
+ neon_store_reg(a->vd, 1, tmp3);
+ return true;
+}
+
+/*
+ * For all the functions using this macro, size == 1 means fp16,
+ * which is an architecture extension we don't implement yet.
+ */
+#define DO_3S_FP_PAIR(INSN,FUNC) \
+ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size != 0) { \
+ /* TODO fp16 support */ \
+ return false; \
+ } \
+ return do_3same_fp_pair(s, a, FUNC); \
+ }
+
+DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
+DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
+DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
+
+static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
+{
+ /* Handle a 2-reg-shift insn which can be vectorized. */
+ int vec_size = a->q ? 16 : 8;
+ int rd_ofs = neon_reg_offset(a->vd, 0);
+ int rm_ofs = neon_reg_offset(a->vm, 0);
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
+ return true;
+}
+
+#define DO_2SH(INSN, FUNC) \
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
+ { \
+ return do_vector_2sh(s, a, FUNC); \
+ } \
+
+DO_2SH(VSHL, tcg_gen_gvec_shli)
+DO_2SH(VSLI, gen_gvec_sli)
+DO_2SH(VSRI, gen_gvec_sri)
+DO_2SH(VSRA_S, gen_gvec_ssra)
+DO_2SH(VSRA_U, gen_gvec_usra)
+DO_2SH(VRSHR_S, gen_gvec_srshr)
+DO_2SH(VRSHR_U, gen_gvec_urshr)
+DO_2SH(VRSRA_S, gen_gvec_srsra)
+DO_2SH(VRSRA_U, gen_gvec_ursra)
+
+static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+ /* Signed shift out of range results in all-sign-bits */
+ a->shift = MIN(a->shift, (8 << a->size) - 1);
+ return do_vector_2sh(s, a, tcg_gen_gvec_sari);
+}
+
+static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
+ int64_t shift, uint32_t oprsz, uint32_t maxsz)
+{
+ tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
+}
+
+static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+ /* Shift out of range is architecturally valid and results in zero. */
+ if (a->shift >= (8 << a->size)) {
+ return do_vector_2sh(s, a, gen_zero_rd_2sh);
+ } else {
+ return do_vector_2sh(s, a, tcg_gen_gvec_shri);
+ }
+}
+
+static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
+ NeonGenTwo64OpEnvFn *fn)
+{
+ /*
+ * 2-reg-and-shift operations, size == 3 case, where the
+ * function needs to be passed cpu_env.
+ */
+ TCGv_i64 constimm;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /*
+ * To avoid excessive duplication of ops we implement shift
+ * by immediate using the variable shift operations.
+ */
+ constimm = tcg_const_i64(dup_const(a->size, a->shift));
+
+ for (pass = 0; pass < a->q + 1; pass++) {
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ neon_load_reg64(tmp, a->vm + pass);
+ fn(tmp, cpu_env, tmp, constimm);
+ neon_store_reg64(tmp, a->vd + pass);
+ tcg_temp_free_i64(tmp);
+ }
+ tcg_temp_free_i64(constimm);
+ return true;
+}
+
+static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
+ NeonGenTwoOpEnvFn *fn)
+{
+ /*
+ * 2-reg-and-shift operations, size < 3 case, where the
+ * helper needs to be passed cpu_env.
+ */
+ TCGv_i32 constimm;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /*
+ * To avoid excessive duplication of ops we implement shift
+ * by immediate using the variable shift operations.
+ */
+ constimm = tcg_const_i32(dup_const(a->size, a->shift));
+
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+ fn(tmp, cpu_env, tmp, constimm);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ tcg_temp_free_i32(constimm);
+ return true;
+}
+
+#define DO_2SHIFT_ENV(INSN, FUNC) \
+ static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \
+ { \
+ return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \
+ } \
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
+ { \
+ static NeonGenTwoOpEnvFn * const fns[] = { \
+ gen_helper_neon_##FUNC##8, \
+ gen_helper_neon_##FUNC##16, \
+ gen_helper_neon_##FUNC##32, \
+ }; \
+ assert(a->size < ARRAY_SIZE(fns)); \
+ return do_2shift_env_32(s, a, fns[a->size]); \
+ }
+
+DO_2SHIFT_ENV(VQSHLU, qshlu_s)
+DO_2SHIFT_ENV(VQSHL_U, qshl_u)
+DO_2SHIFT_ENV(VQSHL_S, qshl_s)
+
+static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
+ NeonGenTwo64OpFn *shiftfn,
+ NeonGenNarrowEnvFn *narrowfn)
+{
+ /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
+ TCGv_i64 constimm, rm1, rm2;
+ TCGv_i32 rd;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vm & 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /*
+ * This is always a right shift, and the shiftfn is always a
+ * left-shift helper, which thus needs the negated shift count.
+ */
+ constimm = tcg_const_i64(-a->shift);
+ rm1 = tcg_temp_new_i64();
+ rm2 = tcg_temp_new_i64();
+
+ /* Load both inputs first to avoid potential overwrite if rm == rd */
+ neon_load_reg64(rm1, a->vm);
+ neon_load_reg64(rm2, a->vm + 1);
+
+ shiftfn(rm1, rm1, constimm);
+ rd = tcg_temp_new_i32();
+ narrowfn(rd, cpu_env, rm1);
+ neon_store_reg(a->vd, 0, rd);
+
+ shiftfn(rm2, rm2, constimm);
+ rd = tcg_temp_new_i32();
+ narrowfn(rd, cpu_env, rm2);
+ neon_store_reg(a->vd, 1, rd);
+
+ tcg_temp_free_i64(rm1);
+ tcg_temp_free_i64(rm2);
+ tcg_temp_free_i64(constimm);
+
+ return true;
+}
+
+static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
+ NeonGenTwoOpFn *shiftfn,
+ NeonGenNarrowEnvFn *narrowfn)
+{
+ /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
+ TCGv_i32 constimm, rm1, rm2, rm3, rm4;
+ TCGv_i64 rtmp;
+ uint32_t imm;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vm & 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /*
+ * This is always a right shift, and the shiftfn is always a
+ * left-shift helper, which thus needs the negated shift count
+ * duplicated into each lane of the immediate value.
+ */
+ if (a->size == 1) {
+ imm = (uint16_t)(-a->shift);
+ imm |= imm << 16;
+ } else {
+ /* size == 2 */
+ imm = -a->shift;
+ }
+ constimm = tcg_const_i32(imm);
+
+ /* Load all inputs first to avoid potential overwrite */
+ rm1 = neon_load_reg(a->vm, 0);
+ rm2 = neon_load_reg(a->vm, 1);
+ rm3 = neon_load_reg(a->vm + 1, 0);
+ rm4 = neon_load_reg(a->vm + 1, 1);
+ rtmp = tcg_temp_new_i64();
+
+ shiftfn(rm1, rm1, constimm);
+ shiftfn(rm2, rm2, constimm);
+
+ tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
+ tcg_temp_free_i32(rm2);
+
+ narrowfn(rm1, cpu_env, rtmp);
+ neon_store_reg(a->vd, 0, rm1);
+
+ shiftfn(rm3, rm3, constimm);
+ shiftfn(rm4, rm4, constimm);
+ tcg_temp_free_i32(constimm);
+
+ tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
+ tcg_temp_free_i32(rm4);
+
+ narrowfn(rm3, cpu_env, rtmp);
+ tcg_temp_free_i64(rtmp);
+ neon_store_reg(a->vd, 1, rm3);
+ return true;
+}
+
+#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
+ { \
+ return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \
+ }
+#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
+ { \
+ return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \
+ }
+
+static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+ tcg_gen_extrl_i64_i32(dest, src);
+}
+
+static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+ gen_helper_neon_narrow_u16(dest, src);
+}
+
+static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
+{
+ gen_helper_neon_narrow_u8(dest, src);
+}
+
+DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
+DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
+DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
+
+DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
+DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
+DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
+
+DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
+DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
+DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
+
+DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
+DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
+DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
+DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
+
+DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
+
+static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
+ NeonGenWidenFn *widenfn, bool u)
+{
+ TCGv_i64 tmp;
+ TCGv_i32 rm0, rm1;
+ uint64_t widen_mask = 0;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /*
+ * This is a widen-and-shift operation. The shift is always less
+ * than the width of the source type, so after widening the input
+ * vector we can simply shift the whole 64-bit widened register,
+ * and then clear the potential overflow bits resulting from left
+ * bits of the narrow input appearing as right bits of the left
+ * neighbour narrow input. Calculate a mask of bits to clear.
+ */
+ if ((a->shift != 0) && (a->size < 2 || u)) {
+ int esize = 8 << a->size;
+ widen_mask = MAKE_64BIT_MASK(0, esize);
+ widen_mask >>= esize - a->shift;
+ widen_mask = dup_const(a->size + 1, widen_mask);
+ }
+
+ rm0 = neon_load_reg(a->vm, 0);
+ rm1 = neon_load_reg(a->vm, 1);
+ tmp = tcg_temp_new_i64();
+
+ widenfn(tmp, rm0);
+ tcg_temp_free_i32(rm0);
+ if (a->shift != 0) {
+ tcg_gen_shli_i64(tmp, tmp, a->shift);
+ tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
+ }
+ neon_store_reg64(tmp, a->vd);
+
+ widenfn(tmp, rm1);
+ tcg_temp_free_i32(rm1);
+ if (a->shift != 0) {
+ tcg_gen_shli_i64(tmp, tmp, a->shift);
+ tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
+ }
+ neon_store_reg64(tmp, a->vd + 1);
+ tcg_temp_free_i64(tmp);
+ return true;
+}
+
+static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+ static NeonGenWidenFn * const widenfn[] = {
+ gen_helper_neon_widen_s8,
+ gen_helper_neon_widen_s16,
+ tcg_gen_ext_i32_i64,
+ };
+ return do_vshll_2sh(s, a, widenfn[a->size], false);
+}
+
+static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
+{
+ static NeonGenWidenFn * const widenfn[] = {
+ gen_helper_neon_widen_u8,
+ gen_helper_neon_widen_u16,
+ tcg_gen_extu_i32_i64,
+ };
+ return do_vshll_2sh(s, a, widenfn[a->size], true);
+}
+
+static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
+ NeonGenTwoSingleOpFn *fn)
+{
+ /* FP operations in 2-reg-and-shift group */
+ TCGv_i32 tmp, shiftv;
+ TCGv_ptr fpstatus;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpstatus = get_fpstatus_ptr(1);
+ shiftv = tcg_const_i32(a->shift);
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ tmp = neon_load_reg(a->vm, pass);
+ fn(tmp, tmp, shiftv, fpstatus);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ tcg_temp_free_ptr(fpstatus);
+ tcg_temp_free_i32(shiftv);
+ return true;
+}
+
+#define DO_FP_2SH(INSN, FUNC) \
+ static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
+ { \
+ return do_fp_2sh(s, a, FUNC); \
+ }
+
+DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
+DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
+DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
+DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
+
+static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+ /*
+ * Expand the encoded constant.
+ * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
+ * We choose to not special-case this and will behave as if a
+ * valid constant encoding of 0 had been given.
+ * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
+ */
+ switch (cmode) {
+ case 0: case 1:
+ /* no-op */
+ break;
+ case 2: case 3:
+ imm <<= 8;
+ break;
+ case 4: case 5:
+ imm <<= 16;
+ break;
+ case 6: case 7:
+ imm <<= 24;
+ break;
+ case 8: case 9:
+ imm |= imm << 16;
+ break;
+ case 10: case 11:
+ imm = (imm << 8) | (imm << 24);
+ break;
+ case 12:
+ imm = (imm << 8) | 0xff;
+ break;
+ case 13:
+ imm = (imm << 16) | 0xffff;
+ break;
+ case 14:
+ if (op) {
+ /*
+ * This is the only case where the top and bottom 32 bits
+ * of the encoded constant differ.
+ */
+ uint64_t imm64 = 0;
+ int n;
+
+ for (n = 0; n < 8; n++) {
+ if (imm & (1 << n)) {
+ imm64 |= (0xffULL << (n * 8));
+ }
+ }
+ return imm64;
+ }
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
+ break;
+ case 15:
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+ break;
+ }
+ if (op) {
+ imm = ~imm;
+ }
+ return dup_const(MO_32, imm);
+}
+
+static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
+ GVecGen2iFn *fn)
+{
+ uint64_t imm;
+ int reg_ofs, vec_size;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ reg_ofs = neon_reg_offset(a->vd, 0);
+ vec_size = a->q ? 16 : 8;
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
+
+ fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size);
+ return true;
+}
+
+static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c);
+}
+
+static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
+{
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
+ GVecGen2iFn *fn;
+
+ if ((a->cmode & 1) && a->cmode < 12) {
+ /* for op=1, the imm will be inverted, so BIC becomes AND. */
+ fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori;
+ } else {
+ /* There is one unallocated cmode/op combination in this space */
+ if (a->cmode == 15 && a->op == 1) {
+ return false;
+ }
+ fn = gen_VMOV_1r;
+ }
+ return do_1reg_imm(s, a, fn);
+}
+
+static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
+ NeonGenWidenFn *widenfn,
+ NeonGenTwo64OpFn *opfn,
+ bool src1_wide)
+{
+ /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
+ TCGv_i64 rn0_64, rn1_64, rm_64;
+ TCGv_i32 rm;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!widenfn || !opfn) {
+ /* size == 3 case, which is an entirely different insn group */
+ return false;
+ }
+
+ if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rn0_64 = tcg_temp_new_i64();
+ rn1_64 = tcg_temp_new_i64();
+ rm_64 = tcg_temp_new_i64();
+
+ if (src1_wide) {
+ neon_load_reg64(rn0_64, a->vn);
+ } else {
+ TCGv_i32 tmp = neon_load_reg(a->vn, 0);
+ widenfn(rn0_64, tmp);
+ tcg_temp_free_i32(tmp);
+ }
+ rm = neon_load_reg(a->vm, 0);
+
+ widenfn(rm_64, rm);
+ tcg_temp_free_i32(rm);
+ opfn(rn0_64, rn0_64, rm_64);
+
+ /*
+ * Load second pass inputs before storing the first pass result, to
+ * avoid incorrect results if a narrow input overlaps with the result.
+ */
+ if (src1_wide) {
+ neon_load_reg64(rn1_64, a->vn + 1);
+ } else {
+ TCGv_i32 tmp = neon_load_reg(a->vn, 1);
+ widenfn(rn1_64, tmp);
+ tcg_temp_free_i32(tmp);
+ }
+ rm = neon_load_reg(a->vm, 1);
+
+ neon_store_reg64(rn0_64, a->vd);
+
+ widenfn(rm_64, rm);
+ tcg_temp_free_i32(rm);
+ opfn(rn1_64, rn1_64, rm_64);
+ neon_store_reg64(rn1_64, a->vd + 1);
+
+ tcg_temp_free_i64(rn0_64);
+ tcg_temp_free_i64(rn1_64);
+ tcg_temp_free_i64(rm_64);
+
+ return true;
+}
+
+#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \
+ static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
+ { \
+ static NeonGenWidenFn * const widenfn[] = { \
+ gen_helper_neon_widen_##S##8, \
+ gen_helper_neon_widen_##S##16, \
+ tcg_gen_##EXT##_i32_i64, \
+ NULL, \
+ }; \
+ static NeonGenTwo64OpFn * const addfn[] = { \
+ gen_helper_neon_##OP##l_u16, \
+ gen_helper_neon_##OP##l_u32, \
+ tcg_gen_##OP##_i64, \
+ NULL, \
+ }; \
+ return do_prewiden_3d(s, a, widenfn[a->size], \
+ addfn[a->size], SRC1WIDE); \
+ }
+
+DO_PREWIDEN(VADDL_S, s, ext, add, false)
+DO_PREWIDEN(VADDL_U, u, extu, add, false)
+DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
+DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
+DO_PREWIDEN(VADDW_S, s, ext, add, true)
+DO_PREWIDEN(VADDW_U, u, extu, add, true)
+DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
+DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
+
+static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
+ NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
+{
+ /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */
+ TCGv_i64 rn_64, rm_64;
+ TCGv_i32 rd0, rd1;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!opfn || !narrowfn) {
+ /* size == 3 case, which is an entirely different insn group */
+ return false;
+ }
+
+ if ((a->vn | a->vm) & 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rn_64 = tcg_temp_new_i64();
+ rm_64 = tcg_temp_new_i64();
+ rd0 = tcg_temp_new_i32();
+ rd1 = tcg_temp_new_i32();
+
+ neon_load_reg64(rn_64, a->vn);
+ neon_load_reg64(rm_64, a->vm);
+
+ opfn(rn_64, rn_64, rm_64);
+
+ narrowfn(rd0, rn_64);
+
+ neon_load_reg64(rn_64, a->vn + 1);
+ neon_load_reg64(rm_64, a->vm + 1);
+
+ opfn(rn_64, rn_64, rm_64);
+
+ narrowfn(rd1, rn_64);
+
+ neon_store_reg(a->vd, 0, rd0);
+ neon_store_reg(a->vd, 1, rd1);
+
+ tcg_temp_free_i64(rn_64);
+ tcg_temp_free_i64(rm_64);
+
+ return true;
+}
+
+#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \
+ static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
+ { \
+ static NeonGenTwo64OpFn * const addfn[] = { \
+ gen_helper_neon_##OP##l_u16, \
+ gen_helper_neon_##OP##l_u32, \
+ tcg_gen_##OP##_i64, \
+ NULL, \
+ }; \
+ static NeonGenNarrowFn * const narrowfn[] = { \
+ gen_helper_neon_##NARROWTYPE##_high_u8, \
+ gen_helper_neon_##NARROWTYPE##_high_u16, \
+ EXTOP, \
+ NULL, \
+ }; \
+ return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \
+ }
+
+static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn)
+{
+ tcg_gen_addi_i64(rn, rn, 1u << 31);
+ tcg_gen_extrh_i64_i32(rd, rn);
+}
+
+DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32)
+DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32)
+DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32)
+DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32)
+
+static bool do_long_3d(DisasContext *s, arg_3diff *a,
+ NeonGenTwoOpWidenFn *opfn,
+ NeonGenTwo64OpFn *accfn)
+{
+ /*
+ * 3-regs different lengths, long operations.
+ * These perform an operation on two inputs that returns a double-width
+ * result, and then possibly perform an accumulation operation of
+ * that result into the double-width destination.
+ */
+ TCGv_i64 rd0, rd1, tmp;
+ TCGv_i32 rn, rm;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!opfn) {
+ /* size == 3 case, which is an entirely different insn group */
+ return false;
+ }
+
+ if (a->vd & 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rd0 = tcg_temp_new_i64();
+ rd1 = tcg_temp_new_i64();
+
+ rn = neon_load_reg(a->vn, 0);
+ rm = neon_load_reg(a->vm, 0);
+ opfn(rd0, rn, rm);
+ tcg_temp_free_i32(rn);
+ tcg_temp_free_i32(rm);
+
+ rn = neon_load_reg(a->vn, 1);
+ rm = neon_load_reg(a->vm, 1);
+ opfn(rd1, rn, rm);
+ tcg_temp_free_i32(rn);
+ tcg_temp_free_i32(rm);
+
+ /* Don't store results until after all loads: they might overlap */
+ if (accfn) {
+ tmp = tcg_temp_new_i64();
+ neon_load_reg64(tmp, a->vd);
+ accfn(tmp, tmp, rd0);
+ neon_store_reg64(tmp, a->vd);
+ neon_load_reg64(tmp, a->vd + 1);
+ accfn(tmp, tmp, rd1);
+ neon_store_reg64(tmp, a->vd + 1);
+ tcg_temp_free_i64(tmp);
+ } else {
+ neon_store_reg64(rd0, a->vd);
+ neon_store_reg64(rd1, a->vd + 1);
+ }
+
+ tcg_temp_free_i64(rd0);
+ tcg_temp_free_i64(rd1);
+
+ return true;
+}
+
+static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ gen_helper_neon_abdl_s16,
+ gen_helper_neon_abdl_s32,
+ gen_helper_neon_abdl_s64,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ gen_helper_neon_abdl_u16,
+ gen_helper_neon_abdl_u32,
+ gen_helper_neon_abdl_u64,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ gen_helper_neon_abdl_s16,
+ gen_helper_neon_abdl_s32,
+ gen_helper_neon_abdl_s64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const addfn[] = {
+ gen_helper_neon_addl_u16,
+ gen_helper_neon_addl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], addfn[a->size]);
+}
+
+static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ gen_helper_neon_abdl_u16,
+ gen_helper_neon_abdl_u32,
+ gen_helper_neon_abdl_u64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const addfn[] = {
+ gen_helper_neon_addl_u16,
+ gen_helper_neon_addl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], addfn[a->size]);
+}
+
+static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ TCGv_i32 lo = tcg_temp_new_i32();
+ TCGv_i32 hi = tcg_temp_new_i32();
+
+ tcg_gen_muls2_i32(lo, hi, rn, rm);
+ tcg_gen_concat_i32_i64(rd, lo, hi);
+
+ tcg_temp_free_i32(lo);
+ tcg_temp_free_i32(hi);
+}
+
+static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ TCGv_i32 lo = tcg_temp_new_i32();
+ TCGv_i32 hi = tcg_temp_new_i32();
+
+ tcg_gen_mulu2_i32(lo, hi, rn, rm);
+ tcg_gen_concat_i32_i64(rd, lo, hi);
+
+ tcg_temp_free_i32(lo);
+ tcg_temp_free_i32(hi);
+}
+
+static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ gen_helper_neon_mull_s8,
+ gen_helper_neon_mull_s16,
+ gen_mull_s32,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ gen_helper_neon_mull_u8,
+ gen_helper_neon_mull_u16,
+ gen_mull_u32,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], NULL);
+}
+
+#define DO_VMLAL(INSN,MULL,ACC) \
+ static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
+ { \
+ static NeonGenTwoOpWidenFn * const opfn[] = { \
+ gen_helper_neon_##MULL##8, \
+ gen_helper_neon_##MULL##16, \
+ gen_##MULL##32, \
+ NULL, \
+ }; \
+ static NeonGenTwo64OpFn * const accfn[] = { \
+ gen_helper_neon_##ACC##l_u16, \
+ gen_helper_neon_##ACC##l_u32, \
+ tcg_gen_##ACC##_i64, \
+ NULL, \
+ }; \
+ return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \
+ }
+
+DO_VMLAL(VMLAL_S,mull_s,add)
+DO_VMLAL(VMLAL_U,mull_u,add)
+DO_VMLAL(VMLSL_S,mull_s,sub)
+DO_VMLAL(VMLSL_U,mull_u,sub)
+
+static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ gen_helper_neon_mull_s16(rd, rn, rm);
+ gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd);
+}
+
+static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
+{
+ gen_mull_s32(rd, rn, rm);
+ gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd);
+}
+
+static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_VQDMULL_16,
+ gen_VQDMULL_32,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], NULL);
+}
+
+static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
+}
+
+static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
+}
+
+static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_VQDMULL_16,
+ gen_VQDMULL_32,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const accfn[] = {
+ NULL,
+ gen_VQDMLAL_acc_16,
+ gen_VQDMLAL_acc_32,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ gen_helper_neon_negl_u32(rm, rm);
+ gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
+}
+
+static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_neg_i64(rm, rm);
+ gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
+}
+
+static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_VQDMULL_16,
+ gen_VQDMULL_32,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const accfn[] = {
+ NULL,
+ gen_VQDMLSL_acc_16,
+ gen_VQDMLSL_acc_32,
+ NULL,
+ };
+
+ return do_long_3d(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
+{
+ gen_helper_gvec_3 *fn_gvec;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & 1) {
+ return false;
+ }
+
+ switch (a->size) {
+ case 0:
+ fn_gvec = gen_helper_neon_pmull_h;
+ break;
+ case 2:
+ if (!dc_isar_feature(aa32_pmull, s)) {
+ return false;
+ }
+ fn_gvec = gen_helper_gvec_pmull_q;
+ break;
+ default:
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
+ neon_reg_offset(a->vn, 0),
+ neon_reg_offset(a->vm, 0),
+ 16, 16, 0, fn_gvec);
+ return true;
+}
+
+static void gen_neon_dup_low16(TCGv_i32 var)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_ext16u_i32(var, var);
+ tcg_gen_shli_i32(tmp, var, 16);
+ tcg_gen_or_i32(var, var, tmp);
+ tcg_temp_free_i32(tmp);
+}
+
+static void gen_neon_dup_high16(TCGv_i32 var)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_andi_i32(var, var, 0xffff0000);
+ tcg_gen_shri_i32(tmp, var, 16);
+ tcg_gen_or_i32(var, var, tmp);
+ tcg_temp_free_i32(tmp);
+}
+
+static inline TCGv_i32 neon_get_scalar(int size, int reg)
+{
+ TCGv_i32 tmp;
+ if (size == 1) {
+ tmp = neon_load_reg(reg & 7, reg >> 4);
+ if (reg & 8) {
+ gen_neon_dup_high16(tmp);
+ } else {
+ gen_neon_dup_low16(tmp);
+ }
+ } else {
+ tmp = neon_load_reg(reg & 15, reg >> 4);
+ }
+ return tmp;
+}
+
+static bool do_2scalar(DisasContext *s, arg_2scalar *a,
+ NeonGenTwoOpFn *opfn, NeonGenTwoOpFn *accfn)
+{
+ /*
+ * Two registers and a scalar: perform an operation between
+ * the input elements and the scalar, and then possibly
+ * perform an accumulation operation of that result into the
+ * destination.
+ */
+ TCGv_i32 scalar;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!opfn) {
+ /* Bad size (including size == 3, which is a different insn group) */
+ return false;
+ }
+
+ if (a->q && ((a->vd | a->vn) & 1)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ scalar = neon_get_scalar(a->size, a->vm);
+
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 tmp = neon_load_reg(a->vn, pass);
+ opfn(tmp, tmp, scalar);
+ if (accfn) {
+ TCGv_i32 rd = neon_load_reg(a->vd, pass);
+ accfn(tmp, rd, tmp);
+ tcg_temp_free_i32(rd);
+ }
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ tcg_temp_free_i32(scalar);
+ return true;
+}
+
+static bool trans_VMUL_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ gen_helper_neon_mul_u16,
+ tcg_gen_mul_i32,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VMLA_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ gen_helper_neon_mul_u16,
+ tcg_gen_mul_i32,
+ NULL,
+ };
+ static NeonGenTwoOpFn * const accfn[] = {
+ NULL,
+ gen_helper_neon_add_u16,
+ tcg_gen_add_i32,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ gen_helper_neon_mul_u16,
+ tcg_gen_mul_i32,
+ NULL,
+ };
+ static NeonGenTwoOpFn * const accfn[] = {
+ NULL,
+ gen_helper_neon_sub_u16,
+ tcg_gen_sub_i32,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
+}
+
+/*
+ * Rather than have a float-specific version of do_2scalar just for
+ * three insns, we wrap a NeonGenTwoSingleOpFn to turn it into
+ * a NeonGenTwoOpFn.
+ */
+#define WRAP_FP_FN(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \
+ { \
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1); \
+ FUNC(rd, rn, rm, fpstatus); \
+ tcg_temp_free_ptr(fpstatus); \
+ }
+
+WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls)
+WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds)
+WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs)
+
+static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_mul,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_mul,
+ NULL,
+ };
+ static NeonGenTwoOpFn * const accfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_add,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_mul,
+ NULL,
+ };
+ static NeonGenTwoOpFn * const accfn[] = {
+ NULL,
+ NULL, /* TODO: fp16 support */
+ gen_VMUL_F_sub,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
+}
+
+WRAP_ENV_FN(gen_VQDMULH_16, gen_helper_neon_qdmulh_s16)
+WRAP_ENV_FN(gen_VQDMULH_32, gen_helper_neon_qdmulh_s32)
+WRAP_ENV_FN(gen_VQRDMULH_16, gen_helper_neon_qrdmulh_s16)
+WRAP_ENV_FN(gen_VQRDMULH_32, gen_helper_neon_qrdmulh_s32)
+
+static bool trans_VQDMULH_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ gen_VQDMULH_16,
+ gen_VQDMULH_32,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpFn * const opfn[] = {
+ NULL,
+ gen_VQRDMULH_16,
+ gen_VQRDMULH_32,
+ NULL,
+ };
+
+ return do_2scalar(s, a, opfn[a->size], NULL);
+}
+
+static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
+ NeonGenThreeOpEnvFn *opfn)
+{
+ /*
+ * VQRDMLAH/VQRDMLSH: this is like do_2scalar, but the opfn
+ * performs a kind of fused op-then-accumulate using a helper
+ * function that takes all of rd, rn and the scalar at once.
+ */
+ TCGv_i32 scalar;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_rdm, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!opfn) {
+ /* Bad size (including size == 3, which is a different insn group) */
+ return false;
+ }
+
+ if (a->q && ((a->vd | a->vn) & 1)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ scalar = neon_get_scalar(a->size, a->vm);
+
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 rn = neon_load_reg(a->vn, pass);
+ TCGv_i32 rd = neon_load_reg(a->vd, pass);
+ opfn(rd, cpu_env, rn, scalar, rd);
+ tcg_temp_free_i32(rn);
+ neon_store_reg(a->vd, pass, rd);
+ }
+ tcg_temp_free_i32(scalar);
+
+ return true;
+}
+
+static bool trans_VQRDMLAH_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenThreeOpEnvFn *opfn[] = {
+ NULL,
+ gen_helper_neon_qrdmlah_s16,
+ gen_helper_neon_qrdmlah_s32,
+ NULL,
+ };
+ return do_vqrdmlah_2sc(s, a, opfn[a->size]);
+}
+
+static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenThreeOpEnvFn *opfn[] = {
+ NULL,
+ gen_helper_neon_qrdmlsh_s16,
+ gen_helper_neon_qrdmlsh_s32,
+ NULL,
+ };
+ return do_vqrdmlah_2sc(s, a, opfn[a->size]);
+}
+
+static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
+ NeonGenTwoOpWidenFn *opfn,
+ NeonGenTwo64OpFn *accfn)
+{
+ /*
+ * Two registers and a scalar, long operations: perform an
+ * operation on the input elements and the scalar which produces
+ * a double-width result, and then possibly perform an accumulation
+ * operation of that result into the destination.
+ */
+ TCGv_i32 scalar, rn;
+ TCGv_i64 rn0_64, rn1_64;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!opfn) {
+ /* Bad size (including size == 3, which is a different insn group) */
+ return false;
+ }
+
+ if (a->vd & 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ scalar = neon_get_scalar(a->size, a->vm);
+
+ /* Load all inputs before writing any outputs, in case of overlap */
+ rn = neon_load_reg(a->vn, 0);
+ rn0_64 = tcg_temp_new_i64();
+ opfn(rn0_64, rn, scalar);
+ tcg_temp_free_i32(rn);
+
+ rn = neon_load_reg(a->vn, 1);
+ rn1_64 = tcg_temp_new_i64();
+ opfn(rn1_64, rn, scalar);
+ tcg_temp_free_i32(rn);
+ tcg_temp_free_i32(scalar);
+
+ if (accfn) {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ neon_load_reg64(t64, a->vd);
+ accfn(t64, t64, rn0_64);
+ neon_store_reg64(t64, a->vd);
+ neon_load_reg64(t64, a->vd + 1);
+ accfn(t64, t64, rn1_64);
+ neon_store_reg64(t64, a->vd + 1);
+ tcg_temp_free_i64(t64);
+ } else {
+ neon_store_reg64(rn0_64, a->vd);
+ neon_store_reg64(rn1_64, a->vd + 1);
+ }
+ tcg_temp_free_i64(rn0_64);
+ tcg_temp_free_i64(rn1_64);
+ return true;
+}
+
+static bool trans_VMULL_S_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_helper_neon_mull_s16,
+ gen_mull_s32,
+ NULL,
+ };
+
+ return do_2scalar_long(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_helper_neon_mull_u16,
+ gen_mull_u32,
+ NULL,
+ };
+
+ return do_2scalar_long(s, a, opfn[a->size], NULL);
+}
+
+#define DO_VMLAL_2SC(INSN, MULL, ACC) \
+ static bool trans_##INSN##_2sc(DisasContext *s, arg_2scalar *a) \
+ { \
+ static NeonGenTwoOpWidenFn * const opfn[] = { \
+ NULL, \
+ gen_helper_neon_##MULL##16, \
+ gen_##MULL##32, \
+ NULL, \
+ }; \
+ static NeonGenTwo64OpFn * const accfn[] = { \
+ NULL, \
+ gen_helper_neon_##ACC##l_u32, \
+ tcg_gen_##ACC##_i64, \
+ NULL, \
+ }; \
+ return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); \
+ }
+
+DO_VMLAL_2SC(VMLAL_S, mull_s, add)
+DO_VMLAL_2SC(VMLAL_U, mull_u, add)
+DO_VMLAL_2SC(VMLSL_S, mull_s, sub)
+DO_VMLAL_2SC(VMLSL_U, mull_u, sub)
+
+static bool trans_VQDMULL_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_VQDMULL_16,
+ gen_VQDMULL_32,
+ NULL,
+ };
+
+ return do_2scalar_long(s, a, opfn[a->size], NULL);
+}
+
+static bool trans_VQDMLAL_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_VQDMULL_16,
+ gen_VQDMULL_32,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const accfn[] = {
+ NULL,
+ gen_VQDMLAL_acc_16,
+ gen_VQDMLAL_acc_32,
+ NULL,
+ };
+
+ return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a)
+{
+ static NeonGenTwoOpWidenFn * const opfn[] = {
+ NULL,
+ gen_VQDMULL_16,
+ gen_VQDMULL_32,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const accfn[] = {
+ NULL,
+ gen_VQDMLSL_acc_16,
+ gen_VQDMLSL_acc_32,
+ NULL,
+ };
+
+ return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]);
+}
+
+static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (a->imm > 7 && !a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (!a->q) {
+ /* Extract 64 bits from <Vm:Vn> */
+ TCGv_i64 left, right, dest;
+
+ left = tcg_temp_new_i64();
+ right = tcg_temp_new_i64();
+ dest = tcg_temp_new_i64();
+
+ neon_load_reg64(right, a->vn);
+ neon_load_reg64(left, a->vm);
+ tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
+ neon_store_reg64(dest, a->vd);
+
+ tcg_temp_free_i64(left);
+ tcg_temp_free_i64(right);
+ tcg_temp_free_i64(dest);
+ } else {
+ /* Extract 128 bits from <Vm+1:Vm:Vn+1:Vn> */
+ TCGv_i64 left, middle, right, destleft, destright;
+
+ left = tcg_temp_new_i64();
+ middle = tcg_temp_new_i64();
+ right = tcg_temp_new_i64();
+ destleft = tcg_temp_new_i64();
+ destright = tcg_temp_new_i64();
+
+ if (a->imm < 8) {
+ neon_load_reg64(right, a->vn);
+ neon_load_reg64(middle, a->vn + 1);
+ tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
+ neon_load_reg64(left, a->vm);
+ tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
+ } else {
+ neon_load_reg64(right, a->vn + 1);
+ neon_load_reg64(middle, a->vm);
+ tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
+ neon_load_reg64(left, a->vm + 1);
+ tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
+ }
+
+ neon_store_reg64(destright, a->vd);
+ neon_store_reg64(destleft, a->vd + 1);
+
+ tcg_temp_free_i64(destright);
+ tcg_temp_free_i64(destleft);
+ tcg_temp_free_i64(right);
+ tcg_temp_free_i64(middle);
+ tcg_temp_free_i64(left);
+ }
+ return true;
+}
+
+static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
+{
+ int n;
+ TCGv_i32 tmp, tmp2, tmp3, tmp4;
+ TCGv_ptr ptr1;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ n = a->len + 1;
+ if ((a->vn + n) > 32) {
+ /*
+ * This is UNPREDICTABLE; we choose to UNDEF to avoid the
+ * helper function running off the end of the register file.
+ */
+ return false;
+ }
+ n <<= 3;
+ if (a->op) {
+ tmp = neon_load_reg(a->vd, 0);
+ } else {
+ tmp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(tmp, 0);
+ }
+ tmp2 = neon_load_reg(a->vm, 0);
+ ptr1 = vfp_reg_ptr(true, a->vn);
+ tmp4 = tcg_const_i32(n);
+ gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
+ tcg_temp_free_i32(tmp);
+ if (a->op) {
+ tmp = neon_load_reg(a->vd, 1);
+ } else {
+ tmp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(tmp, 0);
+ }
+ tmp3 = neon_load_reg(a->vm, 1);
+ gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
+ tcg_temp_free_i32(tmp4);
+ tcg_temp_free_ptr(ptr1);
+ neon_store_reg(a->vd, 0, tmp2);
+ neon_store_reg(a->vd, 1, tmp3);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
+ neon_element_offset(a->vm, a->index, a->size),
+ a->q ? 16 : 8, a->q ? 16 : 8);
+ return true;
+}
+
+static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
+{
+ int pass, half;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (a->size == 3) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
+ TCGv_i32 tmp[2];
+
+ for (half = 0; half < 2; half++) {
+ tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
+ switch (a->size) {
+ case 0:
+ tcg_gen_bswap32_i32(tmp[half], tmp[half]);
+ break;
+ case 1:
+ gen_swap_half(tmp[half], tmp[half]);
+ break;
+ case 2:
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ neon_store_reg(a->vd, pass * 2, tmp[1]);
+ neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
+ }
+ return true;
+}
+
+static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
+ NeonGenWidenFn *widenfn,
+ NeonGenTwo64OpFn *opfn,
+ NeonGenTwo64OpFn *accfn)
+{
+ /*
+ * Pairwise long operations: widen both halves of the pair,
+ * combine the pairs with the opfn, and then possibly accumulate
+ * into the destination with the accfn.
+ */
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!widenfn) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ for (pass = 0; pass < a->q + 1; pass++) {
+ TCGv_i32 tmp;
+ TCGv_i64 rm0_64, rm1_64, rd_64;
+
+ rm0_64 = tcg_temp_new_i64();
+ rm1_64 = tcg_temp_new_i64();
+ rd_64 = tcg_temp_new_i64();
+ tmp = neon_load_reg(a->vm, pass * 2);
+ widenfn(rm0_64, tmp);
+ tcg_temp_free_i32(tmp);
+ tmp = neon_load_reg(a->vm, pass * 2 + 1);
+ widenfn(rm1_64, tmp);
+ tcg_temp_free_i32(tmp);
+ opfn(rd_64, rm0_64, rm1_64);
+ tcg_temp_free_i64(rm0_64);
+ tcg_temp_free_i64(rm1_64);
+
+ if (accfn) {
+ TCGv_i64 tmp64 = tcg_temp_new_i64();
+ neon_load_reg64(tmp64, a->vd + pass);
+ accfn(rd_64, tmp64, rd_64);
+ tcg_temp_free_i64(tmp64);
+ }
+ neon_store_reg64(rd_64, a->vd + pass);
+ tcg_temp_free_i64(rd_64);
+ }
+ return true;
+}
+
+static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenWidenFn * const widenfn[] = {
+ gen_helper_neon_widen_s8,
+ gen_helper_neon_widen_s16,
+ tcg_gen_ext_i32_i64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const opfn[] = {
+ gen_helper_neon_paddl_u16,
+ gen_helper_neon_paddl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
+}
+
+static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenWidenFn * const widenfn[] = {
+ gen_helper_neon_widen_u8,
+ gen_helper_neon_widen_u16,
+ tcg_gen_extu_i32_i64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const opfn[] = {
+ gen_helper_neon_paddl_u16,
+ gen_helper_neon_paddl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
+}
+
+static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenWidenFn * const widenfn[] = {
+ gen_helper_neon_widen_s8,
+ gen_helper_neon_widen_s16,
+ tcg_gen_ext_i32_i64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const opfn[] = {
+ gen_helper_neon_paddl_u16,
+ gen_helper_neon_paddl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const accfn[] = {
+ gen_helper_neon_addl_u16,
+ gen_helper_neon_addl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
+ accfn[a->size]);
+}
+
+static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenWidenFn * const widenfn[] = {
+ gen_helper_neon_widen_u8,
+ gen_helper_neon_widen_u16,
+ tcg_gen_extu_i32_i64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const opfn[] = {
+ gen_helper_neon_paddl_u16,
+ gen_helper_neon_paddl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+ static NeonGenTwo64OpFn * const accfn[] = {
+ gen_helper_neon_addl_u16,
+ gen_helper_neon_addl_u32,
+ tcg_gen_add_i64,
+ NULL,
+ };
+
+ return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
+ accfn[a->size]);
+}
+
+typedef void ZipFn(TCGv_ptr, TCGv_ptr);
+
+static bool do_zip_uzp(DisasContext *s, arg_2misc *a,
+ ZipFn *fn)
+{
+ TCGv_ptr pd, pm;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!fn) {
+ /* Bad size or size/q combination */
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ pd = vfp_reg_ptr(true, a->vd);
+ pm = vfp_reg_ptr(true, a->vm);
+ fn(pd, pm);
+ tcg_temp_free_ptr(pd);
+ tcg_temp_free_ptr(pm);
+ return true;
+}
+
+static bool trans_VUZP(DisasContext *s, arg_2misc *a)
+{
+ static ZipFn * const fn[2][4] = {
+ {
+ gen_helper_neon_unzip8,
+ gen_helper_neon_unzip16,
+ NULL,
+ NULL,
+ }, {
+ gen_helper_neon_qunzip8,
+ gen_helper_neon_qunzip16,
+ gen_helper_neon_qunzip32,
+ NULL,
+ }
+ };
+ return do_zip_uzp(s, a, fn[a->q][a->size]);
+}
+
+static bool trans_VZIP(DisasContext *s, arg_2misc *a)
+{
+ static ZipFn * const fn[2][4] = {
+ {
+ gen_helper_neon_zip8,
+ gen_helper_neon_zip16,
+ NULL,
+ NULL,
+ }, {
+ gen_helper_neon_qzip8,
+ gen_helper_neon_qzip16,
+ gen_helper_neon_qzip32,
+ NULL,
+ }
+ };
+ return do_zip_uzp(s, a, fn[a->q][a->size]);
+}
+
+static bool do_vmovn(DisasContext *s, arg_2misc *a,
+ NeonGenNarrowEnvFn *narrowfn)
+{
+ TCGv_i64 rm;
+ TCGv_i32 rd0, rd1;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vm & 1) {
+ return false;
+ }
+
+ if (!narrowfn) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rm = tcg_temp_new_i64();
+ rd0 = tcg_temp_new_i32();
+ rd1 = tcg_temp_new_i32();
+
+ neon_load_reg64(rm, a->vm);
+ narrowfn(rd0, cpu_env, rm);
+ neon_load_reg64(rm, a->vm + 1);
+ narrowfn(rd1, cpu_env, rm);
+ neon_store_reg(a->vd, 0, rd0);
+ neon_store_reg(a->vd, 1, rd1);
+ tcg_temp_free_i64(rm);
+ return true;
+}
+
+#define DO_VMOVN(INSN, FUNC) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ static NeonGenNarrowEnvFn * const narrowfn[] = { \
+ FUNC##8, \
+ FUNC##16, \
+ FUNC##32, \
+ NULL, \
+ }; \
+ return do_vmovn(s, a, narrowfn[a->size]); \
+ }
+
+DO_VMOVN(VMOVN, gen_neon_narrow_u)
+DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat)
+DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s)
+DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u)
+
+static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
+{
+ TCGv_i32 rm0, rm1;
+ TCGv_i64 rd;
+ static NeonGenWidenFn * const widenfns[] = {
+ gen_helper_neon_widen_u8,
+ gen_helper_neon_widen_u16,
+ tcg_gen_extu_i32_i64,
+ NULL,
+ };
+ NeonGenWidenFn *widenfn = widenfns[a->size];
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & 1) {
+ return false;
+ }
+
+ if (!widenfn) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rd = tcg_temp_new_i64();
+
+ rm0 = neon_load_reg(a->vm, 0);
+ rm1 = neon_load_reg(a->vm, 1);
+
+ widenfn(rd, rm0);
+ tcg_gen_shli_i64(rd, rd, 8 << a->size);
+ neon_store_reg64(rd, a->vd);
+ widenfn(rd, rm1);
+ tcg_gen_shli_i64(rd, rd, 8 << a->size);
+ neon_store_reg64(rd, a->vd + 1);
+
+ tcg_temp_free_i64(rd);
+ tcg_temp_free_i32(rm0);
+ tcg_temp_free_i32(rm1);
+ return true;
+}
+
+static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 ahp, tmp, tmp2, tmp3;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
+ !dc_isar_feature(aa32_fp16_spconv, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vm & 1) || (a->size != 1)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(true);
+ ahp = get_ahp_flag();
+ tmp = neon_load_reg(a->vm, 0);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
+ tmp2 = neon_load_reg(a->vm, 1);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
+ tcg_gen_shli_i32(tmp2, tmp2, 16);
+ tcg_gen_or_i32(tmp2, tmp2, tmp);
+ tcg_temp_free_i32(tmp);
+ tmp = neon_load_reg(a->vm, 2);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
+ tmp3 = neon_load_reg(a->vm, 3);
+ neon_store_reg(a->vd, 0, tmp2);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
+ tcg_gen_shli_i32(tmp3, tmp3, 16);
+ tcg_gen_or_i32(tmp3, tmp3, tmp);
+ neon_store_reg(a->vd, 1, tmp3);
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(ahp);
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 ahp, tmp, tmp2, tmp3;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
+ !dc_isar_feature(aa32_fp16_spconv, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd & 1) || (a->size != 1)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(true);
+ ahp = get_ahp_flag();
+ tmp3 = tcg_temp_new_i32();
+ tmp = neon_load_reg(a->vm, 0);
+ tmp2 = neon_load_reg(a->vm, 1);
+ tcg_gen_ext16u_i32(tmp3, tmp);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
+ neon_store_reg(a->vd, 0, tmp3);
+ tcg_gen_shri_i32(tmp, tmp, 16);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
+ neon_store_reg(a->vd, 1, tmp);
+ tmp3 = tcg_temp_new_i32();
+ tcg_gen_ext16u_i32(tmp3, tmp2);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
+ neon_store_reg(a->vd, 2, tmp3);
+ tcg_gen_shri_i32(tmp2, tmp2, 16);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
+ neon_store_reg(a->vd, 3, tmp2);
+ tcg_temp_free_i32(ahp);
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
+{
+ int vec_size = a->q ? 16 : 8;
+ int rd_ofs = neon_reg_offset(a->vd, 0);
+ int rm_ofs = neon_reg_offset(a->vm, 0);
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size == 3) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size);
+
+ return true;
+}
+
+#define DO_2MISC_VEC(INSN, FN) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ return do_2misc_vec(s, a, FN); \
+ }
+
+DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg)
+DO_2MISC_VEC(VABS, tcg_gen_gvec_abs)
+DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0)
+DO_2MISC_VEC(VCGT0, gen_gvec_cgt0)
+DO_2MISC_VEC(VCLE0, gen_gvec_cle0)
+DO_2MISC_VEC(VCGE0, gen_gvec_cge0)
+DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
+
+static bool trans_VMVN(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 0) {
+ return false;
+ }
+ return do_2misc_vec(s, a, tcg_gen_gvec_not);
+}
+
+#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
+ static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rm_ofs, uint32_t oprsz, \
+ uint32_t maxsz) \
+ { \
+ tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \
+ DATA, FUNC); \
+ }
+
+#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \
+ static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rm_ofs, uint32_t oprsz, \
+ uint32_t maxsz) \
+ { \
+ tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \
+ }
+
+WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0)
+WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1)
+WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0)
+WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1)
+WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0)
+WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0)
+WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0)
+
+#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \
+ return false; \
+ } \
+ return do_2misc_vec(s, a, gen_##INSN); \
+ }
+
+DO_2M_CRYPTO(AESE, aa32_aes, 0)
+DO_2M_CRYPTO(AESD, aa32_aes, 0)
+DO_2M_CRYPTO(AESMC, aa32_aes, 0)
+DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
+DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
+DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
+DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
+
+static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
+{
+ int pass;
+
+ /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!fn) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+ fn(tmp, tmp);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+
+ return true;
+}
+
+static bool trans_VREV32(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenOneOpFn * const fn[] = {
+ tcg_gen_bswap32_i32,
+ gen_swap_half,
+ NULL,
+ NULL,
+ };
+ return do_2misc(s, a, fn[a->size]);
+}
+
+static bool trans_VREV16(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 0) {
+ return false;
+ }
+ return do_2misc(s, a, gen_rev16);
+}
+
+static bool trans_VCLS(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenOneOpFn * const fn[] = {
+ gen_helper_neon_cls_s8,
+ gen_helper_neon_cls_s16,
+ gen_helper_neon_cls_s32,
+ NULL,
+ };
+ return do_2misc(s, a, fn[a->size]);
+}
+
+static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm)
+{
+ tcg_gen_clzi_i32(rd, rm, 32);
+}
+
+static bool trans_VCLZ(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenOneOpFn * const fn[] = {
+ gen_helper_neon_clz_u8,
+ gen_helper_neon_clz_u16,
+ do_VCLZ_32,
+ NULL,
+ };
+ return do_2misc(s, a, fn[a->size]);
+}
+
+static bool trans_VCNT(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 0) {
+ return false;
+ }
+ return do_2misc(s, a, gen_helper_neon_cnt_u8);
+}
+
+static bool trans_VABS_F(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 2) {
+ return false;
+ }
+ /* TODO: FP16 : size == 1 */
+ return do_2misc(s, a, gen_helper_vfp_abss);
+}
+
+static bool trans_VNEG_F(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 2) {
+ return false;
+ }
+ /* TODO: FP16 : size == 1 */
+ return do_2misc(s, a, gen_helper_vfp_negs);
+}
+
+static bool trans_VRECPE(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 2) {
+ return false;
+ }
+ return do_2misc(s, a, gen_helper_recpe_u32);
+}
+
+static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 2) {
+ return false;
+ }
+ return do_2misc(s, a, gen_helper_rsqrte_u32);
+}
+
+#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \
+ { \
+ FUNC(d, cpu_env, m); \
+ }
+
+WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)
+WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16)
+WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32)
+WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8)
+WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16)
+WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32)
+
+static bool trans_VQABS(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenOneOpFn * const fn[] = {
+ gen_VQABS_s8,
+ gen_VQABS_s16,
+ gen_VQABS_s32,
+ NULL,
+ };
+ return do_2misc(s, a, fn[a->size]);
+}
+
+static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
+{
+ static NeonGenOneOpFn * const fn[] = {
+ gen_VQNEG_s8,
+ gen_VQNEG_s16,
+ gen_VQNEG_s32,
+ NULL,
+ };
+ return do_2misc(s, a, fn[a->size]);
+}
+
+static bool do_2misc_fp(DisasContext *s, arg_2misc *a,
+ NeonGenOneSingleOpFn *fn)
+{
+ int pass;
+ TCGv_ptr fpst;
+
+ /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size != 2) {
+ /* TODO: FP16 will be the size == 1 case */
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(1);
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+ fn(tmp, tmp, fpst);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+#define DO_2MISC_FP(INSN, FUNC) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ return do_2misc_fp(s, a, FUNC); \
+ }
+
+DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32)
+DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32)
+DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos)
+DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos)
+DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs)
+DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs)
+
+static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ return do_2misc_fp(s, a, gen_helper_rints_exact);
+}
+
+#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
+ { \
+ TCGv_i32 zero = tcg_const_i32(0); \
+ FUNC(d, m, zero, fpst); \
+ tcg_temp_free_i32(zero); \
+ }
+#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \
+ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
+ { \
+ TCGv_i32 zero = tcg_const_i32(0); \
+ FUNC(d, zero, m, fpst); \
+ tcg_temp_free_i32(zero); \
+ }
+
+#define DO_FP_CMP0(INSN, FUNC, REV) \
+ WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ return do_2misc_fp(s, a, gen_##INSN); \
+ }
+
+DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD)
+DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
+DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
+DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
+DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
+
+static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode)
+{
+ /*
+ * Handle a VRINT* operation by iterating 32 bits at a time,
+ * with a specified rounding mode in operation.
+ */
+ int pass;
+ TCGv_ptr fpst;
+ TCGv_i32 tcg_rmode;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size != 2) {
+ /* TODO: FP16 will be the size == 1 case */
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(1);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+ gen_helper_rints(tmp, tmp, fpst);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ tcg_temp_free_i32(tcg_rmode);
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+#define DO_VRINT(INSN, RMODE) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ return do_vrint(s, a, RMODE); \
+ }
+
+DO_VRINT(VRINTN, FPROUNDING_TIEEVEN)
+DO_VRINT(VRINTA, FPROUNDING_TIEAWAY)
+DO_VRINT(VRINTZ, FPROUNDING_ZERO)
+DO_VRINT(VRINTM, FPROUNDING_NEGINF)
+DO_VRINT(VRINTP, FPROUNDING_POSINF)
+
+static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed)
+{
+ /*
+ * Handle a VCVT* operation by iterating 32 bits at a time,
+ * with a specified rounding mode in operation.
+ */
+ int pass;
+ TCGv_ptr fpst;
+ TCGv_i32 tcg_rmode, tcg_shift;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size != 2) {
+ /* TODO: FP16 will be the size == 1 case */
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(1);
+ tcg_shift = tcg_const_i32(0);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+ if (is_signed) {
+ gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst);
+ } else {
+ gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst);
+ }
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ tcg_temp_free_i32(tcg_rmode);
+ tcg_temp_free_i32(tcg_shift);
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+#define DO_VCVT(INSN, RMODE, SIGNED) \
+ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
+ { \
+ return do_vcvt(s, a, RMODE, SIGNED); \
+ }
+
+DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false)
+DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true)
+DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false)
+DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true)
+DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
+DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
+DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
+DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
+
+static bool trans_VSWP(DisasContext *s, arg_2misc *a)
+{
+ TCGv_i64 rm, rd;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (a->size != 0) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ rm = tcg_temp_new_i64();
+ rd = tcg_temp_new_i64();
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
+ neon_load_reg64(rm, a->vm + pass);
+ neon_load_reg64(rd, a->vd + pass);
+ neon_store_reg64(rm, a->vd + pass);
+ neon_store_reg64(rd, a->vm + pass);
+ }
+ tcg_temp_free_i64(rm);
+ tcg_temp_free_i64(rd);
+
+ return true;
+}
+static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
+{
+ TCGv_i32 rd, tmp;
+
+ rd = tcg_temp_new_i32();
+ tmp = tcg_temp_new_i32();
+
+ tcg_gen_shli_i32(rd, t0, 8);
+ tcg_gen_andi_i32(rd, rd, 0xff00ff00);
+ tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
+ tcg_gen_or_i32(rd, rd, tmp);
+
+ tcg_gen_shri_i32(t1, t1, 8);
+ tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
+ tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
+ tcg_gen_or_i32(t1, t1, tmp);
+ tcg_gen_mov_i32(t0, rd);
+
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(rd);
+}
+
+static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
+{
+ TCGv_i32 rd, tmp;
+
+ rd = tcg_temp_new_i32();
+ tmp = tcg_temp_new_i32();
+
+ tcg_gen_shli_i32(rd, t0, 16);
+ tcg_gen_andi_i32(tmp, t1, 0xffff);
+ tcg_gen_or_i32(rd, rd, tmp);
+ tcg_gen_shri_i32(t1, t1, 16);
+ tcg_gen_andi_i32(tmp, t0, 0xffff0000);
+ tcg_gen_or_i32(t1, t1, tmp);
+ tcg_gen_mov_i32(t0, rd);
+
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(rd);
+}
+
+static bool trans_VTRN(DisasContext *s, arg_2misc *a)
+{
+ TCGv_i32 tmp, tmp2;
+ int pass;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vd | a->vm) & a->q) {
+ return false;
+ }
+
+ if (a->size == 3) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (a->size == 2) {
+ for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
+ tmp = neon_load_reg(a->vm, pass);
+ tmp2 = neon_load_reg(a->vd, pass + 1);
+ neon_store_reg(a->vm, pass, tmp2);
+ neon_store_reg(a->vd, pass + 1, tmp);
+ }
+ } else {
+ for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+ tmp = neon_load_reg(a->vm, pass);
+ tmp2 = neon_load_reg(a->vd, pass);
+ if (a->size == 0) {
+ gen_neon_trn_u8(tmp, tmp2);
+ } else {
+ gen_neon_trn_u16(tmp, tmp2);
+ }
+ neon_store_reg(a->vm, pass, tmp2);
+ neon_store_reg(a->vd, pass, tmp);
+ }
+ }
+ return true;
+}
+++ /dev/null
-/*
- * ARM translation: AArch32 Neon instructions
- *
- * Copyright (c) 2003 Fabrice Bellard
- * Copyright (c) 2005-2007 CodeSourcery
- * Copyright (c) 2007 OpenedHand, Ltd.
- * Copyright (c) 2020 Linaro, Ltd.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * This file is intended to be included from translate.c; it uses
- * some macros and definitions provided by that file.
- * It might be possible to convert it to a standalone .c file eventually.
- */
-
-static inline int plus1(DisasContext *s, int x)
-{
- return x + 1;
-}
-
-static inline int rsub_64(DisasContext *s, int x)
-{
- return 64 - x;
-}
-
-static inline int rsub_32(DisasContext *s, int x)
-{
- return 32 - x;
-}
-static inline int rsub_16(DisasContext *s, int x)
-{
- return 16 - x;
-}
-static inline int rsub_8(DisasContext *s, int x)
-{
- return 8 - x;
-}
-
-/* Include the generated Neon decoder */
-#include "decode-neon-dp.inc.c"
-#include "decode-neon-ls.inc.c"
-#include "decode-neon-shared.inc.c"
-
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
- * where 0 is the least significant end of the register.
- */
-static inline long
-neon_element_offset(int reg, int element, MemOp size)
-{
- int element_size = 1 << size;
- int ofs = element * element_size;
-#ifdef HOST_WORDS_BIGENDIAN
- /* Calculate the offset assuming fully little-endian,
- * then XOR to account for the order of the 8-byte units.
- */
- if (element_size < 8) {
- ofs ^= 8 - element_size;
- }
-#endif
- return neon_reg_offset(reg, 0) + ofs;
-}
-
-static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
-{
- long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
-
- switch (mop) {
- case MO_UB:
- tcg_gen_ld8u_i32(var, cpu_env, offset);
- break;
- case MO_UW:
- tcg_gen_ld16u_i32(var, cpu_env, offset);
- break;
- case MO_UL:
- tcg_gen_ld_i32(var, cpu_env, offset);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)
-{
- long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
-
- switch (mop) {
- case MO_UB:
- tcg_gen_ld8u_i64(var, cpu_env, offset);
- break;
- case MO_UW:
- tcg_gen_ld16u_i64(var, cpu_env, offset);
- break;
- case MO_UL:
- tcg_gen_ld32u_i64(var, cpu_env, offset);
- break;
- case MO_Q:
- tcg_gen_ld_i64(var, cpu_env, offset);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)
-{
- long offset = neon_element_offset(reg, ele, size);
-
- switch (size) {
- case MO_8:
- tcg_gen_st8_i32(var, cpu_env, offset);
- break;
- case MO_16:
- tcg_gen_st16_i32(var, cpu_env, offset);
- break;
- case MO_32:
- tcg_gen_st_i32(var, cpu_env, offset);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
-{
- long offset = neon_element_offset(reg, ele, size);
-
- switch (size) {
- case MO_8:
- tcg_gen_st8_i64(var, cpu_env, offset);
- break;
- case MO_16:
- tcg_gen_st16_i64(var, cpu_env, offset);
- break;
- case MO_32:
- tcg_gen_st32_i64(var, cpu_env, offset);
- break;
- case MO_64:
- tcg_gen_st_i64(var, cpu_env, offset);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
-{
- int opr_sz;
- TCGv_ptr fpst;
- gen_helper_gvec_3_ptr *fn_gvec_ptr;
-
- if (!dc_isar_feature(aa32_vcma, s)
- || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- opr_sz = (1 + a->q) * 8;
- fpst = get_fpstatus_ptr(1);
- fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->vm),
- fpst, opr_sz, opr_sz, a->rot,
- fn_gvec_ptr);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
-{
- int opr_sz;
- TCGv_ptr fpst;
- gen_helper_gvec_3_ptr *fn_gvec_ptr;
-
- if (!dc_isar_feature(aa32_vcma, s)
- || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- opr_sz = (1 + a->q) * 8;
- fpst = get_fpstatus_ptr(1);
- fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->vm),
- fpst, opr_sz, opr_sz, a->rot,
- fn_gvec_ptr);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
-{
- int opr_sz;
- gen_helper_gvec_3 *fn_gvec;
-
- if (!dc_isar_feature(aa32_dp, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- opr_sz = (1 + a->q) * 8;
- fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->vm),
- opr_sz, opr_sz, 0, fn_gvec);
- return true;
-}
-
-static bool trans_VFML(DisasContext *s, arg_VFML *a)
-{
- int opr_sz;
-
- if (!dc_isar_feature(aa32_fhm, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- (a->vd & 0x10)) {
- return false;
- }
-
- if (a->vd & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- opr_sz = (1 + a->q) * 8;
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(a->q, a->vn),
- vfp_reg_offset(a->q, a->vm),
- cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
- gen_helper_gvec_fmlal_a32);
- return true;
-}
-
-static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
-{
- gen_helper_gvec_3_ptr *fn_gvec_ptr;
- int opr_sz;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_vcma, s)) {
- return false;
- }
- if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vn) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
- : gen_helper_gvec_fcmlah_idx);
- opr_sz = (1 + a->q) * 8;
- fpst = get_fpstatus_ptr(1);
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->vm),
- fpst, opr_sz, opr_sz,
- (a->index << 2) | a->rot, fn_gvec_ptr);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
-{
- gen_helper_gvec_3 *fn_gvec;
- int opr_sz;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_dp, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vn) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
- opr_sz = (1 + a->q) * 8;
- fpst = get_fpstatus_ptr(1);
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->rm),
- opr_sz, opr_sz, a->index, fn_gvec);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
-{
- int opr_sz;
-
- if (!dc_isar_feature(aa32_fhm, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
- return false;
- }
-
- if (a->vd & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- opr_sz = (1 + a->q) * 8;
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(a->q, a->vn),
- vfp_reg_offset(a->q, a->rm),
- cpu_env, opr_sz, opr_sz,
- (a->index << 2) | a->s, /* is_2 == 0 */
- gen_helper_gvec_fmlal_idx_a32);
- return true;
-}
-
-static struct {
- int nregs;
- int interleave;
- int spacing;
-} const neon_ls_element_type[11] = {
- {1, 4, 1},
- {1, 4, 2},
- {4, 1, 1},
- {2, 2, 2},
- {1, 3, 1},
- {1, 3, 2},
- {3, 1, 1},
- {1, 1, 1},
- {1, 2, 1},
- {1, 2, 2},
- {2, 1, 1}
-};
-
-static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
- int stride)
-{
- if (rm != 15) {
- TCGv_i32 base;
-
- base = load_reg(s, rn);
- if (rm == 13) {
- tcg_gen_addi_i32(base, base, stride);
- } else {
- TCGv_i32 index;
- index = load_reg(s, rm);
- tcg_gen_add_i32(base, base, index);
- tcg_temp_free_i32(index);
- }
- store_reg(s, rn, base);
- }
-}
-
-static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
-{
- /* Neon load/store multiple structures */
- int nregs, interleave, spacing, reg, n;
- MemOp endian = s->be_data;
- int mmu_idx = get_mem_index(s);
- int size = a->size;
- TCGv_i64 tmp64;
- TCGv_i32 addr, tmp;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
- if (a->itype > 10) {
- return false;
- }
- /* Catch UNDEF cases for bad values of align field */
- switch (a->itype & 0xc) {
- case 4:
- if (a->align >= 2) {
- return false;
- }
- break;
- case 8:
- if (a->align == 3) {
- return false;
- }
- break;
- default:
- break;
- }
- nregs = neon_ls_element_type[a->itype].nregs;
- interleave = neon_ls_element_type[a->itype].interleave;
- spacing = neon_ls_element_type[a->itype].spacing;
- if (size == 3 && (interleave | spacing) != 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /* For our purposes, bytes are always little-endian. */
- if (size == 0) {
- endian = MO_LE;
- }
- /*
- * Consecutive little-endian elements from a single register
- * can be promoted to a larger little-endian operation.
- */
- if (interleave == 1 && endian == MO_LE) {
- size = 3;
- }
- tmp64 = tcg_temp_new_i64();
- addr = tcg_temp_new_i32();
- tmp = tcg_const_i32(1 << size);
- load_reg_var(s, addr, a->rn);
- for (reg = 0; reg < nregs; reg++) {
- for (n = 0; n < 8 >> size; n++) {
- int xs;
- for (xs = 0; xs < interleave; xs++) {
- int tt = a->vd + reg + spacing * xs;
-
- if (a->l) {
- gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
- neon_store_element64(tt, n, size, tmp64);
- } else {
- neon_load_element64(tmp64, tt, n, size);
- gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
- }
- tcg_gen_add_i32(addr, addr, tmp);
- }
- }
- }
- tcg_temp_free_i32(addr);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i64(tmp64);
-
- gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
- return true;
-}
-
-static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
-{
- /* Neon load single structure to all lanes */
- int reg, stride, vec_size;
- int vd = a->vd;
- int size = a->size;
- int nregs = a->n + 1;
- TCGv_i32 addr, tmp;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (size == 3) {
- if (nregs != 4 || a->a == 0) {
- return false;
- }
- /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */
- size = 2;
- }
- if (nregs == 1 && a->a == 1 && size == 0) {
- return false;
- }
- if (nregs == 3 && a->a == 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /*
- * VLD1 to all lanes: T bit indicates how many Dregs to write.
- * VLD2/3/4 to all lanes: T bit indicates register stride.
- */
- stride = a->t ? 2 : 1;
- vec_size = nregs == 1 ? stride * 8 : 8;
-
- tmp = tcg_temp_new_i32();
- addr = tcg_temp_new_i32();
- load_reg_var(s, addr, a->rn);
- for (reg = 0; reg < nregs; reg++) {
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
- s->be_data | size);
- if ((vd & 1) && vec_size == 16) {
- /*
- * We cannot write 16 bytes at once because the
- * destination is unaligned.
- */
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
- 8, 8, tmp);
- tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
- neon_reg_offset(vd, 0), 8, 8);
- } else {
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
- vec_size, vec_size, tmp);
- }
- tcg_gen_addi_i32(addr, addr, 1 << size);
- vd += stride;
- }
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(addr);
-
- gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs);
-
- return true;
-}
-
-static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
-{
- /* Neon load/store single structure to one lane */
- int reg;
- int nregs = a->n + 1;
- int vd = a->vd;
- TCGv_i32 addr, tmp;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- /* Catch the UNDEF cases. This is unavoidably a bit messy. */
- switch (nregs) {
- case 1:
- if (((a->align & (1 << a->size)) != 0) ||
- (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
- return false;
- }
- break;
- case 3:
- if ((a->align & 1) != 0) {
- return false;
- }
- /* fall through */
- case 2:
- if (a->size == 2 && (a->align & 2) != 0) {
- return false;
- }
- break;
- case 4:
- if ((a->size == 2) && ((a->align & 3) == 3)) {
- return false;
- }
- break;
- default:
- abort();
- }
- if ((vd + a->stride * (nregs - 1)) > 31) {
- /*
- * Attempts to write off the end of the register file are
- * UNPREDICTABLE; we choose to UNDEF because otherwise we would
- * access off the end of the array that holds the register data.
- */
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i32();
- addr = tcg_temp_new_i32();
- load_reg_var(s, addr, a->rn);
- /*
- * TODO: if we implemented alignment exceptions, we should check
- * addr against the alignment encoded in a->align here.
- */
- for (reg = 0; reg < nregs; reg++) {
- if (a->l) {
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
- s->be_data | a->size);
- neon_store_element(vd, a->reg_idx, a->size, tmp);
- } else { /* Store */
- neon_load_element(tmp, vd, a->reg_idx, a->size);
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
- s->be_data | a->size);
- }
- vd += a->stride;
- tcg_gen_addi_i32(addr, addr, 1 << a->size);
- }
- tcg_temp_free_i32(addr);
- tcg_temp_free_i32(tmp);
-
- gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
-
- return true;
-}
-
-static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
-{
- int vec_size = a->q ? 16 : 8;
- int rd_ofs = neon_reg_offset(a->vd, 0);
- int rn_ofs = neon_reg_offset(a->vn, 0);
- int rm_ofs = neon_reg_offset(a->vm, 0);
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
- return true;
-}
-
-#define DO_3SAME(INSN, FUNC) \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- return do_3same(s, a, FUNC); \
- }
-
-DO_3SAME(VADD, tcg_gen_gvec_add)
-DO_3SAME(VSUB, tcg_gen_gvec_sub)
-DO_3SAME(VAND, tcg_gen_gvec_and)
-DO_3SAME(VBIC, tcg_gen_gvec_andc)
-DO_3SAME(VORR, tcg_gen_gvec_or)
-DO_3SAME(VORN, tcg_gen_gvec_orc)
-DO_3SAME(VEOR, tcg_gen_gvec_xor)
-DO_3SAME(VSHL_S, gen_gvec_sshl)
-DO_3SAME(VSHL_U, gen_gvec_ushl)
-DO_3SAME(VQADD_S, gen_gvec_sqadd_qc)
-DO_3SAME(VQADD_U, gen_gvec_uqadd_qc)
-DO_3SAME(VQSUB_S, gen_gvec_sqsub_qc)
-DO_3SAME(VQSUB_U, gen_gvec_uqsub_qc)
-
-/* These insns are all gvec_bitsel but with the inputs in various orders. */
-#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \
- } \
- DO_3SAME(INSN, gen_##INSN##_3s)
-
-DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
-DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
-DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
-
-#define DO_3SAME_NO_SZ_3(INSN, FUNC) \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size == 3) { \
- return false; \
- } \
- return do_3same(s, a, FUNC); \
- }
-
-DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
-DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
-DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
-DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
-DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
-DO_3SAME_NO_SZ_3(VMLA, gen_gvec_mla)
-DO_3SAME_NO_SZ_3(VMLS, gen_gvec_mls)
-DO_3SAME_NO_SZ_3(VTST, gen_gvec_cmtst)
-DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd)
-DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba)
-DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd)
-DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba)
-
-#define DO_3SAME_CMP(INSN, COND) \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
- } \
- DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
-
-DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
-DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
-DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
-DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
-DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
-
-#define WRAP_OOL_FN(WRAPNAME, FUNC) \
- static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \
- uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \
- { \
- tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
- }
-
-WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b)
-
-static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
-{
- if (a->size != 0) {
- return false;
- }
- return do_3same(s, a, gen_VMUL_p_3s);
-}
-
-#define DO_VQRDMLAH(INSN, FUNC) \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (!dc_isar_feature(aa32_rdm, s)) { \
- return false; \
- } \
- if (a->size != 1 && a->size != 2) { \
- return false; \
- } \
- return do_3same(s, a, FUNC); \
- }
-
-DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
-DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
-
-#define DO_SHA1(NAME, FUNC) \
- WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
- static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (!dc_isar_feature(aa32_sha1, s)) { \
- return false; \
- } \
- return do_3same(s, a, gen_##NAME##_3s); \
- }
-
-DO_SHA1(SHA1C, gen_helper_crypto_sha1c)
-DO_SHA1(SHA1P, gen_helper_crypto_sha1p)
-DO_SHA1(SHA1M, gen_helper_crypto_sha1m)
-DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0)
-
-#define DO_SHA2(NAME, FUNC) \
- WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \
- static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (!dc_isar_feature(aa32_sha2, s)) { \
- return false; \
- } \
- return do_3same(s, a, gen_##NAME##_3s); \
- }
-
-DO_SHA2(SHA256H, gen_helper_crypto_sha256h)
-DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2)
-DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
-
-#define DO_3SAME_64(INSN, FUNC) \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- static const GVecGen3 op = { .fni8 = FUNC }; \
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &op); \
- } \
- DO_3SAME(INSN, gen_##INSN##_3s)
-
-#define DO_3SAME_64_ENV(INSN, FUNC) \
- static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \
- { \
- FUNC(d, cpu_env, n, m); \
- } \
- DO_3SAME_64(INSN, gen_##INSN##_elt)
-
-DO_3SAME_64(VRSHL_S64, gen_helper_neon_rshl_s64)
-DO_3SAME_64(VRSHL_U64, gen_helper_neon_rshl_u64)
-DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64)
-DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64)
-DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64)
-DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
-
-#define DO_3SAME_32(INSN, FUNC) \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- static const GVecGen3 ops[4] = { \
- { .fni4 = gen_helper_neon_##FUNC##8 }, \
- { .fni4 = gen_helper_neon_##FUNC##16 }, \
- { .fni4 = gen_helper_neon_##FUNC##32 }, \
- { 0 }, \
- }; \
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \
- } \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size > 2) { \
- return false; \
- } \
- return do_3same(s, a, gen_##INSN##_3s); \
- }
-
-/*
- * Some helper functions need to be passed the cpu_env. In order
- * to use those with the gvec APIs like tcg_gen_gvec_3() we need
- * to create wrapper functions whose prototype is a NeonGenTwoOpFn()
- * and which call a NeonGenTwoOpEnvFn().
- */
-#define WRAP_ENV_FN(WRAPNAME, FUNC) \
- static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \
- { \
- FUNC(d, cpu_env, n, m); \
- }
-
-#define DO_3SAME_32_ENV(INSN, FUNC) \
- WRAP_ENV_FN(gen_##INSN##_tramp8, gen_helper_neon_##FUNC##8); \
- WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##16); \
- WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##32); \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- static const GVecGen3 ops[4] = { \
- { .fni4 = gen_##INSN##_tramp8 }, \
- { .fni4 = gen_##INSN##_tramp16 }, \
- { .fni4 = gen_##INSN##_tramp32 }, \
- { 0 }, \
- }; \
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \
- } \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size > 2) { \
- return false; \
- } \
- return do_3same(s, a, gen_##INSN##_3s); \
- }
-
-DO_3SAME_32(VHADD_S, hadd_s)
-DO_3SAME_32(VHADD_U, hadd_u)
-DO_3SAME_32(VHSUB_S, hsub_s)
-DO_3SAME_32(VHSUB_U, hsub_u)
-DO_3SAME_32(VRHADD_S, rhadd_s)
-DO_3SAME_32(VRHADD_U, rhadd_u)
-DO_3SAME_32(VRSHL_S, rshl_s)
-DO_3SAME_32(VRSHL_U, rshl_u)
-
-DO_3SAME_32_ENV(VQSHL_S, qshl_s)
-DO_3SAME_32_ENV(VQSHL_U, qshl_u)
-DO_3SAME_32_ENV(VQRSHL_S, qrshl_s)
-DO_3SAME_32_ENV(VQRSHL_U, qrshl_u)
-
-static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
-{
- /* Operations handled pairwise 32 bits at a time */
- TCGv_i32 tmp, tmp2, tmp3;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->size == 3) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- assert(a->q == 0); /* enforced by decode patterns */
-
- /*
- * Note that we have to be careful not to clobber the source operands
- * in the "vm == vd" case by storing the result of the first pass too
- * early. Since Q is 0 there are always just two passes, so instead
- * of a complicated loop over each pass we just unroll.
- */
- tmp = neon_load_reg(a->vn, 0);
- tmp2 = neon_load_reg(a->vn, 1);
- fn(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
-
- tmp3 = neon_load_reg(a->vm, 0);
- tmp2 = neon_load_reg(a->vm, 1);
- fn(tmp3, tmp3, tmp2);
- tcg_temp_free_i32(tmp2);
-
- neon_store_reg(a->vd, 0, tmp);
- neon_store_reg(a->vd, 1, tmp3);
- return true;
-}
-
-#define DO_3SAME_PAIR(INSN, func) \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- static NeonGenTwoOpFn * const fns[] = { \
- gen_helper_neon_##func##8, \
- gen_helper_neon_##func##16, \
- gen_helper_neon_##func##32, \
- }; \
- if (a->size > 2) { \
- return false; \
- } \
- return do_3same_pair(s, a, fns[a->size]); \
- }
-
-/* 32-bit pairwise ops end up the same as the elementwise versions. */
-#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32
-#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
-#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
-#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
-#define gen_helper_neon_padd_u32 tcg_gen_add_i32
-
-DO_3SAME_PAIR(VPMAX_S, pmax_s)
-DO_3SAME_PAIR(VPMIN_S, pmin_s)
-DO_3SAME_PAIR(VPMAX_U, pmax_u)
-DO_3SAME_PAIR(VPMIN_U, pmin_u)
-DO_3SAME_PAIR(VPADD, padd_u)
-
-#define DO_3SAME_VQDMULH(INSN, FUNC) \
- WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \
- WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- static const GVecGen3 ops[2] = { \
- { .fni4 = gen_##INSN##_tramp16 }, \
- { .fni4 = gen_##INSN##_tramp32 }, \
- }; \
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \
- } \
- static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size != 1 && a->size != 2) { \
- return false; \
- } \
- return do_3same(s, a, gen_##INSN##_3s); \
- }
-
-DO_3SAME_VQDMULH(VQDMULH, qdmulh)
-DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
-
-static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn,
- bool reads_vd)
-{
- /*
- * FP operations handled elementwise 32 bits at a time.
- * If reads_vd is true then the old value of Vd will be
- * loaded before calling the callback function. This is
- * used for multiply-accumulate type operations.
- */
- TCGv_i32 tmp, tmp2;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- tmp = neon_load_reg(a->vn, pass);
- tmp2 = neon_load_reg(a->vm, pass);
- if (reads_vd) {
- TCGv_i32 tmp_rd = neon_load_reg(a->vd, pass);
- fn(tmp_rd, tmp, tmp2, fpstatus);
- neon_store_reg(a->vd, pass, tmp_rd);
- tcg_temp_free_i32(tmp);
- } else {
- fn(tmp, tmp, tmp2, fpstatus);
- neon_store_reg(a->vd, pass, tmp);
- }
- tcg_temp_free_i32(tmp2);
- }
- tcg_temp_free_ptr(fpstatus);
- return true;
-}
-
-/*
- * For all the functions using this macro, size == 1 means fp16,
- * which is an architecture extension we don't implement yet.
- */
-#define DO_3S_FP_GVEC(INSN,FUNC) \
- static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
- uint32_t rn_ofs, uint32_t rm_ofs, \
- uint32_t oprsz, uint32_t maxsz) \
- { \
- TCGv_ptr fpst = get_fpstatus_ptr(1); \
- tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \
- oprsz, maxsz, 0, FUNC); \
- tcg_temp_free_ptr(fpst); \
- } \
- static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size != 0) { \
- /* TODO fp16 support */ \
- return false; \
- } \
- return do_3same(s, a, gen_##INSN##_3s); \
- }
-
-
-DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)
-DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)
-DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)
-DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s)
-
-/*
- * For all the functions using this macro, size == 1 means fp16,
- * which is an architecture extension we don't implement yet.
- */
-#define DO_3S_FP(INSN,FUNC,READS_VD) \
- static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size != 0) { \
- /* TODO fp16 support */ \
- return false; \
- } \
- return do_3same_fp(s, a, FUNC, READS_VD); \
- }
-
-DO_3S_FP(VCEQ, gen_helper_neon_ceq_f32, false)
-DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false)
-DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false)
-DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false)
-DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false)
-DO_3S_FP(VMAX, gen_helper_vfp_maxs, false)
-DO_3S_FP(VMIN, gen_helper_vfp_mins, false)
-
-static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
- TCGv_ptr fpstatus)
-{
- gen_helper_vfp_muls(vn, vn, vm, fpstatus);
- gen_helper_vfp_adds(vd, vd, vn, fpstatus);
-}
-
-static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
- TCGv_ptr fpstatus)
-{
- gen_helper_vfp_muls(vn, vn, vm, fpstatus);
- gen_helper_vfp_subs(vd, vd, vn, fpstatus);
-}
-
-DO_3S_FP(VMLA, gen_VMLA_fp_3s, true)
-DO_3S_FP(VMLS, gen_VMLS_fp_3s, true)
-
-static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a)
-{
- if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
-
- if (a->size != 0) {
- /* TODO fp16 support */
- return false;
- }
-
- return do_3same_fp(s, a, gen_helper_vfp_maxnums, false);
-}
-
-static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)
-{
- if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
-
- if (a->size != 0) {
- /* TODO fp16 support */
- return false;
- }
-
- return do_3same_fp(s, a, gen_helper_vfp_minnums, false);
-}
-
-WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32)
-
-static void gen_VRECPS_fp_3s(unsigned vece, uint32_t rd_ofs,
- uint32_t rn_ofs, uint32_t rm_ofs,
- uint32_t oprsz, uint32_t maxsz)
-{
- static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp };
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);
-}
-
-static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a)
-{
- if (a->size != 0) {
- /* TODO fp16 support */
- return false;
- }
-
- return do_3same(s, a, gen_VRECPS_fp_3s);
-}
-
-WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32)
-
-static void gen_VRSQRTS_fp_3s(unsigned vece, uint32_t rd_ofs,
- uint32_t rn_ofs, uint32_t rm_ofs,
- uint32_t oprsz, uint32_t maxsz)
-{
- static const GVecGen3 ops = { .fni4 = gen_VRSQRTS_tramp };
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);
-}
-
-static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a)
-{
- if (a->size != 0) {
- /* TODO fp16 support */
- return false;
- }
-
- return do_3same(s, a, gen_VRSQRTS_fp_3s);
-}
-
-static void gen_VFMA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
- TCGv_ptr fpstatus)
-{
- gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus);
-}
-
-static bool trans_VFMA_fp_3s(DisasContext *s, arg_3same *a)
-{
- if (!dc_isar_feature(aa32_simdfmac, s)) {
- return false;
- }
-
- if (a->size != 0) {
- /* TODO fp16 support */
- return false;
- }
-
- return do_3same_fp(s, a, gen_VFMA_fp_3s, true);
-}
-
-static void gen_VFMS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
- TCGv_ptr fpstatus)
-{
- gen_helper_vfp_negs(vn, vn);
- gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus);
-}
-
-static bool trans_VFMS_fp_3s(DisasContext *s, arg_3same *a)
-{
- if (!dc_isar_feature(aa32_simdfmac, s)) {
- return false;
- }
-
- if (a->size != 0) {
- /* TODO fp16 support */
- return false;
- }
-
- return do_3same_fp(s, a, gen_VFMS_fp_3s, true);
-}
-
-static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
-{
- /* FP operations handled pairwise 32 bits at a time */
- TCGv_i32 tmp, tmp2, tmp3;
- TCGv_ptr fpstatus;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- assert(a->q == 0); /* enforced by decode patterns */
-
- /*
- * Note that we have to be careful not to clobber the source operands
- * in the "vm == vd" case by storing the result of the first pass too
- * early. Since Q is 0 there are always just two passes, so instead
- * of a complicated loop over each pass we just unroll.
- */
- fpstatus = get_fpstatus_ptr(1);
- tmp = neon_load_reg(a->vn, 0);
- tmp2 = neon_load_reg(a->vn, 1);
- fn(tmp, tmp, tmp2, fpstatus);
- tcg_temp_free_i32(tmp2);
-
- tmp3 = neon_load_reg(a->vm, 0);
- tmp2 = neon_load_reg(a->vm, 1);
- fn(tmp3, tmp3, tmp2, fpstatus);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_ptr(fpstatus);
-
- neon_store_reg(a->vd, 0, tmp);
- neon_store_reg(a->vd, 1, tmp3);
- return true;
-}
-
-/*
- * For all the functions using this macro, size == 1 means fp16,
- * which is an architecture extension we don't implement yet.
- */
-#define DO_3S_FP_PAIR(INSN,FUNC) \
- static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
- { \
- if (a->size != 0) { \
- /* TODO fp16 support */ \
- return false; \
- } \
- return do_3same_fp_pair(s, a, FUNC); \
- }
-
-DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
-DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
-DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
-
-static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
-{
- /* Handle a 2-reg-shift insn which can be vectorized. */
- int vec_size = a->q ? 16 : 8;
- int rd_ofs = neon_reg_offset(a->vd, 0);
- int rm_ofs = neon_reg_offset(a->vm, 0);
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
- return true;
-}
-
-#define DO_2SH(INSN, FUNC) \
- static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
- { \
- return do_vector_2sh(s, a, FUNC); \
- } \
-
-DO_2SH(VSHL, tcg_gen_gvec_shli)
-DO_2SH(VSLI, gen_gvec_sli)
-DO_2SH(VSRI, gen_gvec_sri)
-DO_2SH(VSRA_S, gen_gvec_ssra)
-DO_2SH(VSRA_U, gen_gvec_usra)
-DO_2SH(VRSHR_S, gen_gvec_srshr)
-DO_2SH(VRSHR_U, gen_gvec_urshr)
-DO_2SH(VRSRA_S, gen_gvec_srsra)
-DO_2SH(VRSRA_U, gen_gvec_ursra)
-
-static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
-{
- /* Signed shift out of range results in all-sign-bits */
- a->shift = MIN(a->shift, (8 << a->size) - 1);
- return do_vector_2sh(s, a, tcg_gen_gvec_sari);
-}
-
-static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
- int64_t shift, uint32_t oprsz, uint32_t maxsz)
-{
- tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0);
-}
-
-static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a)
-{
- /* Shift out of range is architecturally valid and results in zero. */
- if (a->shift >= (8 << a->size)) {
- return do_vector_2sh(s, a, gen_zero_rd_2sh);
- } else {
- return do_vector_2sh(s, a, tcg_gen_gvec_shri);
- }
-}
-
-static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
- NeonGenTwo64OpEnvFn *fn)
-{
- /*
- * 2-reg-and-shift operations, size == 3 case, where the
- * function needs to be passed cpu_env.
- */
- TCGv_i64 constimm;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /*
- * To avoid excessive duplication of ops we implement shift
- * by immediate using the variable shift operations.
- */
- constimm = tcg_const_i64(dup_const(a->size, a->shift));
-
- for (pass = 0; pass < a->q + 1; pass++) {
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- neon_load_reg64(tmp, a->vm + pass);
- fn(tmp, cpu_env, tmp, constimm);
- neon_store_reg64(tmp, a->vd + pass);
- tcg_temp_free_i64(tmp);
- }
- tcg_temp_free_i64(constimm);
- return true;
-}
-
-static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
- NeonGenTwoOpEnvFn *fn)
-{
- /*
- * 2-reg-and-shift operations, size < 3 case, where the
- * helper needs to be passed cpu_env.
- */
- TCGv_i32 constimm;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /*
- * To avoid excessive duplication of ops we implement shift
- * by immediate using the variable shift operations.
- */
- constimm = tcg_const_i32(dup_const(a->size, a->shift));
-
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
- fn(tmp, cpu_env, tmp, constimm);
- neon_store_reg(a->vd, pass, tmp);
- }
- tcg_temp_free_i32(constimm);
- return true;
-}
-
-#define DO_2SHIFT_ENV(INSN, FUNC) \
- static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \
- { \
- return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \
- } \
- static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
- { \
- static NeonGenTwoOpEnvFn * const fns[] = { \
- gen_helper_neon_##FUNC##8, \
- gen_helper_neon_##FUNC##16, \
- gen_helper_neon_##FUNC##32, \
- }; \
- assert(a->size < ARRAY_SIZE(fns)); \
- return do_2shift_env_32(s, a, fns[a->size]); \
- }
-
-DO_2SHIFT_ENV(VQSHLU, qshlu_s)
-DO_2SHIFT_ENV(VQSHL_U, qshl_u)
-DO_2SHIFT_ENV(VQSHL_S, qshl_s)
-
-static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
- NeonGenTwo64OpFn *shiftfn,
- NeonGenNarrowEnvFn *narrowfn)
-{
- /* 2-reg-and-shift narrowing-shift operations, size == 3 case */
- TCGv_i64 constimm, rm1, rm2;
- TCGv_i32 rd;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vm & 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /*
- * This is always a right shift, and the shiftfn is always a
- * left-shift helper, which thus needs the negated shift count.
- */
- constimm = tcg_const_i64(-a->shift);
- rm1 = tcg_temp_new_i64();
- rm2 = tcg_temp_new_i64();
-
- /* Load both inputs first to avoid potential overwrite if rm == rd */
- neon_load_reg64(rm1, a->vm);
- neon_load_reg64(rm2, a->vm + 1);
-
- shiftfn(rm1, rm1, constimm);
- rd = tcg_temp_new_i32();
- narrowfn(rd, cpu_env, rm1);
- neon_store_reg(a->vd, 0, rd);
-
- shiftfn(rm2, rm2, constimm);
- rd = tcg_temp_new_i32();
- narrowfn(rd, cpu_env, rm2);
- neon_store_reg(a->vd, 1, rd);
-
- tcg_temp_free_i64(rm1);
- tcg_temp_free_i64(rm2);
- tcg_temp_free_i64(constimm);
-
- return true;
-}
-
-static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
- NeonGenTwoOpFn *shiftfn,
- NeonGenNarrowEnvFn *narrowfn)
-{
- /* 2-reg-and-shift narrowing-shift operations, size < 3 case */
- TCGv_i32 constimm, rm1, rm2, rm3, rm4;
- TCGv_i64 rtmp;
- uint32_t imm;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vm & 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /*
- * This is always a right shift, and the shiftfn is always a
- * left-shift helper, which thus needs the negated shift count
- * duplicated into each lane of the immediate value.
- */
- if (a->size == 1) {
- imm = (uint16_t)(-a->shift);
- imm |= imm << 16;
- } else {
- /* size == 2 */
- imm = -a->shift;
- }
- constimm = tcg_const_i32(imm);
-
- /* Load all inputs first to avoid potential overwrite */
- rm1 = neon_load_reg(a->vm, 0);
- rm2 = neon_load_reg(a->vm, 1);
- rm3 = neon_load_reg(a->vm + 1, 0);
- rm4 = neon_load_reg(a->vm + 1, 1);
- rtmp = tcg_temp_new_i64();
-
- shiftfn(rm1, rm1, constimm);
- shiftfn(rm2, rm2, constimm);
-
- tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
- tcg_temp_free_i32(rm2);
-
- narrowfn(rm1, cpu_env, rtmp);
- neon_store_reg(a->vd, 0, rm1);
-
- shiftfn(rm3, rm3, constimm);
- shiftfn(rm4, rm4, constimm);
- tcg_temp_free_i32(constimm);
-
- tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
- tcg_temp_free_i32(rm4);
-
- narrowfn(rm3, cpu_env, rtmp);
- tcg_temp_free_i64(rtmp);
- neon_store_reg(a->vd, 1, rm3);
- return true;
-}
-
-#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \
- static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
- { \
- return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \
- }
-#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \
- static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
- { \
- return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \
- }
-
-static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
-{
- tcg_gen_extrl_i64_i32(dest, src);
-}
-
-static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
-{
- gen_helper_neon_narrow_u16(dest, src);
-}
-
-static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src)
-{
- gen_helper_neon_narrow_u8(dest, src);
-}
-
-DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32)
-DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16)
-DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8)
-
-DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32)
-DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16)
-DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8)
-
-DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32)
-DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16)
-DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8)
-
-DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
-DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
-DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
-DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
-DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
-DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
-
-DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32)
-DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16)
-DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
-
-DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
-DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
-DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
-
-DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32)
-DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16)
-DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
-
-static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
- NeonGenWidenFn *widenfn, bool u)
-{
- TCGv_i64 tmp;
- TCGv_i32 rm0, rm1;
- uint64_t widen_mask = 0;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vd & 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /*
- * This is a widen-and-shift operation. The shift is always less
- * than the width of the source type, so after widening the input
- * vector we can simply shift the whole 64-bit widened register,
- * and then clear the potential overflow bits resulting from left
- * bits of the narrow input appearing as right bits of the left
- * neighbour narrow input. Calculate a mask of bits to clear.
- */
- if ((a->shift != 0) && (a->size < 2 || u)) {
- int esize = 8 << a->size;
- widen_mask = MAKE_64BIT_MASK(0, esize);
- widen_mask >>= esize - a->shift;
- widen_mask = dup_const(a->size + 1, widen_mask);
- }
-
- rm0 = neon_load_reg(a->vm, 0);
- rm1 = neon_load_reg(a->vm, 1);
- tmp = tcg_temp_new_i64();
-
- widenfn(tmp, rm0);
- tcg_temp_free_i32(rm0);
- if (a->shift != 0) {
- tcg_gen_shli_i64(tmp, tmp, a->shift);
- tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
- }
- neon_store_reg64(tmp, a->vd);
-
- widenfn(tmp, rm1);
- tcg_temp_free_i32(rm1);
- if (a->shift != 0) {
- tcg_gen_shli_i64(tmp, tmp, a->shift);
- tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
- }
- neon_store_reg64(tmp, a->vd + 1);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
-static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_s8,
- gen_helper_neon_widen_s16,
- tcg_gen_ext_i32_i64,
- };
- return do_vshll_2sh(s, a, widenfn[a->size], false);
-}
-
-static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- };
- return do_vshll_2sh(s, a, widenfn[a->size], true);
-}
-
-static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
- NeonGenTwoSingleOpFn *fn)
-{
- /* FP operations in 2-reg-and-shift group */
- TCGv_i32 tmp, shiftv;
- TCGv_ptr fpstatus;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpstatus = get_fpstatus_ptr(1);
- shiftv = tcg_const_i32(a->shift);
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- tmp = neon_load_reg(a->vm, pass);
- fn(tmp, tmp, shiftv, fpstatus);
- neon_store_reg(a->vd, pass, tmp);
- }
- tcg_temp_free_ptr(fpstatus);
- tcg_temp_free_i32(shiftv);
- return true;
-}
-
-#define DO_FP_2SH(INSN, FUNC) \
- static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
- { \
- return do_fp_2sh(s, a, FUNC); \
- }
-
-DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
-DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
-DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
-DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
-
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
- /*
- * Expand the encoded constant.
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
- * We choose to not special-case this and will behave as if a
- * valid constant encoding of 0 had been given.
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
- */
- switch (cmode) {
- case 0: case 1:
- /* no-op */
- break;
- case 2: case 3:
- imm <<= 8;
- break;
- case 4: case 5:
- imm <<= 16;
- break;
- case 6: case 7:
- imm <<= 24;
- break;
- case 8: case 9:
- imm |= imm << 16;
- break;
- case 10: case 11:
- imm = (imm << 8) | (imm << 24);
- break;
- case 12:
- imm = (imm << 8) | 0xff;
- break;
- case 13:
- imm = (imm << 16) | 0xffff;
- break;
- case 14:
- if (op) {
- /*
- * This is the only case where the top and bottom 32 bits
- * of the encoded constant differ.
- */
- uint64_t imm64 = 0;
- int n;
-
- for (n = 0; n < 8; n++) {
- if (imm & (1 << n)) {
- imm64 |= (0xffULL << (n * 8));
- }
- }
- return imm64;
- }
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
- break;
- case 15:
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
- break;
- }
- if (op) {
- imm = ~imm;
- }
- return dup_const(MO_32, imm);
-}
-
-static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
- GVecGen2iFn *fn)
-{
- uint64_t imm;
- int reg_ofs, vec_size;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (a->vd & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- reg_ofs = neon_reg_offset(a->vd, 0);
- vec_size = a->q ? 16 : 8;
- imm = asimd_imm_const(a->imm, a->cmode, a->op);
-
- fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size);
- return true;
-}
-
-static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz)
-{
- tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c);
-}
-
-static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
-{
- /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
- GVecGen2iFn *fn;
-
- if ((a->cmode & 1) && a->cmode < 12) {
- /* for op=1, the imm will be inverted, so BIC becomes AND. */
- fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori;
- } else {
- /* There is one unallocated cmode/op combination in this space */
- if (a->cmode == 15 && a->op == 1) {
- return false;
- }
- fn = gen_VMOV_1r;
- }
- return do_1reg_imm(s, a, fn);
-}
-
-static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
- NeonGenWidenFn *widenfn,
- NeonGenTwo64OpFn *opfn,
- bool src1_wide)
-{
- /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
- TCGv_i64 rn0_64, rn1_64, rm_64;
- TCGv_i32 rm;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!widenfn || !opfn) {
- /* size == 3 case, which is an entirely different insn group */
- return false;
- }
-
- if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- rn0_64 = tcg_temp_new_i64();
- rn1_64 = tcg_temp_new_i64();
- rm_64 = tcg_temp_new_i64();
-
- if (src1_wide) {
- neon_load_reg64(rn0_64, a->vn);
- } else {
- TCGv_i32 tmp = neon_load_reg(a->vn, 0);
- widenfn(rn0_64, tmp);
- tcg_temp_free_i32(tmp);
- }
- rm = neon_load_reg(a->vm, 0);
-
- widenfn(rm_64, rm);
- tcg_temp_free_i32(rm);
- opfn(rn0_64, rn0_64, rm_64);
-
- /*
- * Load second pass inputs before storing the first pass result, to
- * avoid incorrect results if a narrow input overlaps with the result.
- */
- if (src1_wide) {
- neon_load_reg64(rn1_64, a->vn + 1);
- } else {
- TCGv_i32 tmp = neon_load_reg(a->vn, 1);
- widenfn(rn1_64, tmp);
- tcg_temp_free_i32(tmp);
- }
- rm = neon_load_reg(a->vm, 1);
-
- neon_store_reg64(rn0_64, a->vd);
-
- widenfn(rm_64, rm);
- tcg_temp_free_i32(rm);
- opfn(rn1_64, rn1_64, rm_64);
- neon_store_reg64(rn1_64, a->vd + 1);
-
- tcg_temp_free_i64(rn0_64);
- tcg_temp_free_i64(rn1_64);
- tcg_temp_free_i64(rm_64);
-
- return true;
-}
-
-#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \
- static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
- { \
- static NeonGenWidenFn * const widenfn[] = { \
- gen_helper_neon_widen_##S##8, \
- gen_helper_neon_widen_##S##16, \
- tcg_gen_##EXT##_i32_i64, \
- NULL, \
- }; \
- static NeonGenTwo64OpFn * const addfn[] = { \
- gen_helper_neon_##OP##l_u16, \
- gen_helper_neon_##OP##l_u32, \
- tcg_gen_##OP##_i64, \
- NULL, \
- }; \
- return do_prewiden_3d(s, a, widenfn[a->size], \
- addfn[a->size], SRC1WIDE); \
- }
-
-DO_PREWIDEN(VADDL_S, s, ext, add, false)
-DO_PREWIDEN(VADDL_U, u, extu, add, false)
-DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
-DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
-DO_PREWIDEN(VADDW_S, s, ext, add, true)
-DO_PREWIDEN(VADDW_U, u, extu, add, true)
-DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
-DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
-
-static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
- NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
-{
- /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */
- TCGv_i64 rn_64, rm_64;
- TCGv_i32 rd0, rd1;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!opfn || !narrowfn) {
- /* size == 3 case, which is an entirely different insn group */
- return false;
- }
-
- if ((a->vn | a->vm) & 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- rn_64 = tcg_temp_new_i64();
- rm_64 = tcg_temp_new_i64();
- rd0 = tcg_temp_new_i32();
- rd1 = tcg_temp_new_i32();
-
- neon_load_reg64(rn_64, a->vn);
- neon_load_reg64(rm_64, a->vm);
-
- opfn(rn_64, rn_64, rm_64);
-
- narrowfn(rd0, rn_64);
-
- neon_load_reg64(rn_64, a->vn + 1);
- neon_load_reg64(rm_64, a->vm + 1);
-
- opfn(rn_64, rn_64, rm_64);
-
- narrowfn(rd1, rn_64);
-
- neon_store_reg(a->vd, 0, rd0);
- neon_store_reg(a->vd, 1, rd1);
-
- tcg_temp_free_i64(rn_64);
- tcg_temp_free_i64(rm_64);
-
- return true;
-}
-
-#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \
- static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
- { \
- static NeonGenTwo64OpFn * const addfn[] = { \
- gen_helper_neon_##OP##l_u16, \
- gen_helper_neon_##OP##l_u32, \
- tcg_gen_##OP##_i64, \
- NULL, \
- }; \
- static NeonGenNarrowFn * const narrowfn[] = { \
- gen_helper_neon_##NARROWTYPE##_high_u8, \
- gen_helper_neon_##NARROWTYPE##_high_u16, \
- EXTOP, \
- NULL, \
- }; \
- return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \
- }
-
-static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn)
-{
- tcg_gen_addi_i64(rn, rn, 1u << 31);
- tcg_gen_extrh_i64_i32(rd, rn);
-}
-
-DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32)
-DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32)
-DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32)
-DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32)
-
-static bool do_long_3d(DisasContext *s, arg_3diff *a,
- NeonGenTwoOpWidenFn *opfn,
- NeonGenTwo64OpFn *accfn)
-{
- /*
- * 3-regs different lengths, long operations.
- * These perform an operation on two inputs that returns a double-width
- * result, and then possibly perform an accumulation operation of
- * that result into the double-width destination.
- */
- TCGv_i64 rd0, rd1, tmp;
- TCGv_i32 rn, rm;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!opfn) {
- /* size == 3 case, which is an entirely different insn group */
- return false;
- }
-
- if (a->vd & 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- rd0 = tcg_temp_new_i64();
- rd1 = tcg_temp_new_i64();
-
- rn = neon_load_reg(a->vn, 0);
- rm = neon_load_reg(a->vm, 0);
- opfn(rd0, rn, rm);
- tcg_temp_free_i32(rn);
- tcg_temp_free_i32(rm);
-
- rn = neon_load_reg(a->vn, 1);
- rm = neon_load_reg(a->vm, 1);
- opfn(rd1, rn, rm);
- tcg_temp_free_i32(rn);
- tcg_temp_free_i32(rm);
-
- /* Don't store results until after all loads: they might overlap */
- if (accfn) {
- tmp = tcg_temp_new_i64();
- neon_load_reg64(tmp, a->vd);
- accfn(tmp, tmp, rd0);
- neon_store_reg64(tmp, a->vd);
- neon_load_reg64(tmp, a->vd + 1);
- accfn(tmp, tmp, rd1);
- neon_store_reg64(tmp, a->vd + 1);
- tcg_temp_free_i64(tmp);
- } else {
- neon_store_reg64(rd0, a->vd);
- neon_store_reg64(rd1, a->vd + 1);
- }
-
- tcg_temp_free_i64(rd0);
- tcg_temp_free_i64(rd1);
-
- return true;
-}
-
-static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- gen_helper_neon_abdl_s16,
- gen_helper_neon_abdl_s32,
- gen_helper_neon_abdl_s64,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- gen_helper_neon_abdl_u16,
- gen_helper_neon_abdl_u32,
- gen_helper_neon_abdl_u64,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- gen_helper_neon_abdl_s16,
- gen_helper_neon_abdl_s32,
- gen_helper_neon_abdl_s64,
- NULL,
- };
- static NeonGenTwo64OpFn * const addfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], addfn[a->size]);
-}
-
-static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- gen_helper_neon_abdl_u16,
- gen_helper_neon_abdl_u32,
- gen_helper_neon_abdl_u64,
- NULL,
- };
- static NeonGenTwo64OpFn * const addfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], addfn[a->size]);
-}
-
-static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
-{
- TCGv_i32 lo = tcg_temp_new_i32();
- TCGv_i32 hi = tcg_temp_new_i32();
-
- tcg_gen_muls2_i32(lo, hi, rn, rm);
- tcg_gen_concat_i32_i64(rd, lo, hi);
-
- tcg_temp_free_i32(lo);
- tcg_temp_free_i32(hi);
-}
-
-static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
-{
- TCGv_i32 lo = tcg_temp_new_i32();
- TCGv_i32 hi = tcg_temp_new_i32();
-
- tcg_gen_mulu2_i32(lo, hi, rn, rm);
- tcg_gen_concat_i32_i64(rd, lo, hi);
-
- tcg_temp_free_i32(lo);
- tcg_temp_free_i32(hi);
-}
-
-static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- gen_helper_neon_mull_s8,
- gen_helper_neon_mull_s16,
- gen_mull_s32,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- gen_helper_neon_mull_u8,
- gen_helper_neon_mull_u16,
- gen_mull_u32,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], NULL);
-}
-
-#define DO_VMLAL(INSN,MULL,ACC) \
- static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
- { \
- static NeonGenTwoOpWidenFn * const opfn[] = { \
- gen_helper_neon_##MULL##8, \
- gen_helper_neon_##MULL##16, \
- gen_##MULL##32, \
- NULL, \
- }; \
- static NeonGenTwo64OpFn * const accfn[] = { \
- gen_helper_neon_##ACC##l_u16, \
- gen_helper_neon_##ACC##l_u32, \
- tcg_gen_##ACC##_i64, \
- NULL, \
- }; \
- return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \
- }
-
-DO_VMLAL(VMLAL_S,mull_s,add)
-DO_VMLAL(VMLAL_U,mull_u,add)
-DO_VMLAL(VMLSL_S,mull_s,sub)
-DO_VMLAL(VMLSL_U,mull_u,sub)
-
-static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
-{
- gen_helper_neon_mull_s16(rd, rn, rm);
- gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd);
-}
-
-static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
-{
- gen_mull_s32(rd, rn, rm);
- gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd);
-}
-
-static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_VQDMULL_16,
- gen_VQDMULL_32,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], NULL);
-}
-
-static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
-{
- gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
-}
-
-static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
-{
- gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
-}
-
-static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_VQDMULL_16,
- gen_VQDMULL_32,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- NULL,
- gen_VQDMLAL_acc_16,
- gen_VQDMLAL_acc_32,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], accfn[a->size]);
-}
-
-static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
-{
- gen_helper_neon_negl_u32(rm, rm);
- gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
-}
-
-static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
-{
- tcg_gen_neg_i64(rm, rm);
- gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
-}
-
-static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_VQDMULL_16,
- gen_VQDMULL_32,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- NULL,
- gen_VQDMLSL_acc_16,
- gen_VQDMLSL_acc_32,
- NULL,
- };
-
- return do_long_3d(s, a, opfn[a->size], accfn[a->size]);
-}
-
-static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
-{
- gen_helper_gvec_3 *fn_gvec;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vd & 1) {
- return false;
- }
-
- switch (a->size) {
- case 0:
- fn_gvec = gen_helper_neon_pmull_h;
- break;
- case 2:
- if (!dc_isar_feature(aa32_pmull, s)) {
- return false;
- }
- fn_gvec = gen_helper_gvec_pmull_q;
- break;
- default:
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
- neon_reg_offset(a->vn, 0),
- neon_reg_offset(a->vm, 0),
- 16, 16, 0, fn_gvec);
- return true;
-}
-
-static void gen_neon_dup_low16(TCGv_i32 var)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_ext16u_i32(var, var);
- tcg_gen_shli_i32(tmp, var, 16);
- tcg_gen_or_i32(var, var, tmp);
- tcg_temp_free_i32(tmp);
-}
-
-static void gen_neon_dup_high16(TCGv_i32 var)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_andi_i32(var, var, 0xffff0000);
- tcg_gen_shri_i32(tmp, var, 16);
- tcg_gen_or_i32(var, var, tmp);
- tcg_temp_free_i32(tmp);
-}
-
-static inline TCGv_i32 neon_get_scalar(int size, int reg)
-{
- TCGv_i32 tmp;
- if (size == 1) {
- tmp = neon_load_reg(reg & 7, reg >> 4);
- if (reg & 8) {
- gen_neon_dup_high16(tmp);
- } else {
- gen_neon_dup_low16(tmp);
- }
- } else {
- tmp = neon_load_reg(reg & 15, reg >> 4);
- }
- return tmp;
-}
-
-static bool do_2scalar(DisasContext *s, arg_2scalar *a,
- NeonGenTwoOpFn *opfn, NeonGenTwoOpFn *accfn)
-{
- /*
- * Two registers and a scalar: perform an operation between
- * the input elements and the scalar, and then possibly
- * perform an accumulation operation of that result into the
- * destination.
- */
- TCGv_i32 scalar;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!opfn) {
- /* Bad size (including size == 3, which is a different insn group) */
- return false;
- }
-
- if (a->q && ((a->vd | a->vn) & 1)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- scalar = neon_get_scalar(a->size, a->vm);
-
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 tmp = neon_load_reg(a->vn, pass);
- opfn(tmp, tmp, scalar);
- if (accfn) {
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
- accfn(tmp, rd, tmp);
- tcg_temp_free_i32(rd);
- }
- neon_store_reg(a->vd, pass, tmp);
- }
- tcg_temp_free_i32(scalar);
- return true;
-}
-
-static bool trans_VMUL_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- gen_helper_neon_mul_u16,
- tcg_gen_mul_i32,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VMLA_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- gen_helper_neon_mul_u16,
- tcg_gen_mul_i32,
- NULL,
- };
- static NeonGenTwoOpFn * const accfn[] = {
- NULL,
- gen_helper_neon_add_u16,
- tcg_gen_add_i32,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
-}
-
-static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- gen_helper_neon_mul_u16,
- tcg_gen_mul_i32,
- NULL,
- };
- static NeonGenTwoOpFn * const accfn[] = {
- NULL,
- gen_helper_neon_sub_u16,
- tcg_gen_sub_i32,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
-}
-
-/*
- * Rather than have a float-specific version of do_2scalar just for
- * three insns, we wrap a NeonGenTwoSingleOpFn to turn it into
- * a NeonGenTwoOpFn.
- */
-#define WRAP_FP_FN(WRAPNAME, FUNC) \
- static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \
- { \
- TCGv_ptr fpstatus = get_fpstatus_ptr(1); \
- FUNC(rd, rn, rm, fpstatus); \
- tcg_temp_free_ptr(fpstatus); \
- }
-
-WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls)
-WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds)
-WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs)
-
-static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- NULL, /* TODO: fp16 support */
- gen_VMUL_F_mul,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- NULL, /* TODO: fp16 support */
- gen_VMUL_F_mul,
- NULL,
- };
- static NeonGenTwoOpFn * const accfn[] = {
- NULL,
- NULL, /* TODO: fp16 support */
- gen_VMUL_F_add,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
-}
-
-static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- NULL, /* TODO: fp16 support */
- gen_VMUL_F_mul,
- NULL,
- };
- static NeonGenTwoOpFn * const accfn[] = {
- NULL,
- NULL, /* TODO: fp16 support */
- gen_VMUL_F_sub,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], accfn[a->size]);
-}
-
-WRAP_ENV_FN(gen_VQDMULH_16, gen_helper_neon_qdmulh_s16)
-WRAP_ENV_FN(gen_VQDMULH_32, gen_helper_neon_qdmulh_s32)
-WRAP_ENV_FN(gen_VQRDMULH_16, gen_helper_neon_qrdmulh_s16)
-WRAP_ENV_FN(gen_VQRDMULH_32, gen_helper_neon_qrdmulh_s32)
-
-static bool trans_VQDMULH_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- gen_VQDMULH_16,
- gen_VQDMULH_32,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpFn * const opfn[] = {
- NULL,
- gen_VQRDMULH_16,
- gen_VQRDMULH_32,
- NULL,
- };
-
- return do_2scalar(s, a, opfn[a->size], NULL);
-}
-
-static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
- NeonGenThreeOpEnvFn *opfn)
-{
- /*
- * VQRDMLAH/VQRDMLSH: this is like do_2scalar, but the opfn
- * performs a kind of fused op-then-accumulate using a helper
- * function that takes all of rd, rn and the scalar at once.
- */
- TCGv_i32 scalar;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_rdm, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!opfn) {
- /* Bad size (including size == 3, which is a different insn group) */
- return false;
- }
-
- if (a->q && ((a->vd | a->vn) & 1)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- scalar = neon_get_scalar(a->size, a->vm);
-
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 rn = neon_load_reg(a->vn, pass);
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
- opfn(rd, cpu_env, rn, scalar, rd);
- tcg_temp_free_i32(rn);
- neon_store_reg(a->vd, pass, rd);
- }
- tcg_temp_free_i32(scalar);
-
- return true;
-}
-
-static bool trans_VQRDMLAH_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenThreeOpEnvFn *opfn[] = {
- NULL,
- gen_helper_neon_qrdmlah_s16,
- gen_helper_neon_qrdmlah_s32,
- NULL,
- };
- return do_vqrdmlah_2sc(s, a, opfn[a->size]);
-}
-
-static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenThreeOpEnvFn *opfn[] = {
- NULL,
- gen_helper_neon_qrdmlsh_s16,
- gen_helper_neon_qrdmlsh_s32,
- NULL,
- };
- return do_vqrdmlah_2sc(s, a, opfn[a->size]);
-}
-
-static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
- NeonGenTwoOpWidenFn *opfn,
- NeonGenTwo64OpFn *accfn)
-{
- /*
- * Two registers and a scalar, long operations: perform an
- * operation on the input elements and the scalar which produces
- * a double-width result, and then possibly perform an accumulation
- * operation of that result into the destination.
- */
- TCGv_i32 scalar, rn;
- TCGv_i64 rn0_64, rn1_64;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!opfn) {
- /* Bad size (including size == 3, which is a different insn group) */
- return false;
- }
-
- if (a->vd & 1) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- scalar = neon_get_scalar(a->size, a->vm);
-
- /* Load all inputs before writing any outputs, in case of overlap */
- rn = neon_load_reg(a->vn, 0);
- rn0_64 = tcg_temp_new_i64();
- opfn(rn0_64, rn, scalar);
- tcg_temp_free_i32(rn);
-
- rn = neon_load_reg(a->vn, 1);
- rn1_64 = tcg_temp_new_i64();
- opfn(rn1_64, rn, scalar);
- tcg_temp_free_i32(rn);
- tcg_temp_free_i32(scalar);
-
- if (accfn) {
- TCGv_i64 t64 = tcg_temp_new_i64();
- neon_load_reg64(t64, a->vd);
- accfn(t64, t64, rn0_64);
- neon_store_reg64(t64, a->vd);
- neon_load_reg64(t64, a->vd + 1);
- accfn(t64, t64, rn1_64);
- neon_store_reg64(t64, a->vd + 1);
- tcg_temp_free_i64(t64);
- } else {
- neon_store_reg64(rn0_64, a->vd);
- neon_store_reg64(rn1_64, a->vd + 1);
- }
- tcg_temp_free_i64(rn0_64);
- tcg_temp_free_i64(rn1_64);
- return true;
-}
-
-static bool trans_VMULL_S_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_helper_neon_mull_s16,
- gen_mull_s32,
- NULL,
- };
-
- return do_2scalar_long(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_helper_neon_mull_u16,
- gen_mull_u32,
- NULL,
- };
-
- return do_2scalar_long(s, a, opfn[a->size], NULL);
-}
-
-#define DO_VMLAL_2SC(INSN, MULL, ACC) \
- static bool trans_##INSN##_2sc(DisasContext *s, arg_2scalar *a) \
- { \
- static NeonGenTwoOpWidenFn * const opfn[] = { \
- NULL, \
- gen_helper_neon_##MULL##16, \
- gen_##MULL##32, \
- NULL, \
- }; \
- static NeonGenTwo64OpFn * const accfn[] = { \
- NULL, \
- gen_helper_neon_##ACC##l_u32, \
- tcg_gen_##ACC##_i64, \
- NULL, \
- }; \
- return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); \
- }
-
-DO_VMLAL_2SC(VMLAL_S, mull_s, add)
-DO_VMLAL_2SC(VMLAL_U, mull_u, add)
-DO_VMLAL_2SC(VMLSL_S, mull_s, sub)
-DO_VMLAL_2SC(VMLSL_U, mull_u, sub)
-
-static bool trans_VQDMULL_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_VQDMULL_16,
- gen_VQDMULL_32,
- NULL,
- };
-
- return do_2scalar_long(s, a, opfn[a->size], NULL);
-}
-
-static bool trans_VQDMLAL_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_VQDMULL_16,
- gen_VQDMULL_32,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- NULL,
- gen_VQDMLAL_acc_16,
- gen_VQDMLAL_acc_32,
- NULL,
- };
-
- return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]);
-}
-
-static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a)
-{
- static NeonGenTwoOpWidenFn * const opfn[] = {
- NULL,
- gen_VQDMULL_16,
- gen_VQDMULL_32,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- NULL,
- gen_VQDMLSL_acc_16,
- gen_VQDMLSL_acc_32,
- NULL,
- };
-
- return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]);
-}
-
-static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
-{
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (a->imm > 7 && !a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (!a->q) {
- /* Extract 64 bits from <Vm:Vn> */
- TCGv_i64 left, right, dest;
-
- left = tcg_temp_new_i64();
- right = tcg_temp_new_i64();
- dest = tcg_temp_new_i64();
-
- neon_load_reg64(right, a->vn);
- neon_load_reg64(left, a->vm);
- tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
- neon_store_reg64(dest, a->vd);
-
- tcg_temp_free_i64(left);
- tcg_temp_free_i64(right);
- tcg_temp_free_i64(dest);
- } else {
- /* Extract 128 bits from <Vm+1:Vm:Vn+1:Vn> */
- TCGv_i64 left, middle, right, destleft, destright;
-
- left = tcg_temp_new_i64();
- middle = tcg_temp_new_i64();
- right = tcg_temp_new_i64();
- destleft = tcg_temp_new_i64();
- destright = tcg_temp_new_i64();
-
- if (a->imm < 8) {
- neon_load_reg64(right, a->vn);
- neon_load_reg64(middle, a->vn + 1);
- tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
- neon_load_reg64(left, a->vm);
- tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
- } else {
- neon_load_reg64(right, a->vn + 1);
- neon_load_reg64(middle, a->vm);
- tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
- neon_load_reg64(left, a->vm + 1);
- tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
- }
-
- neon_store_reg64(destright, a->vd);
- neon_store_reg64(destleft, a->vd + 1);
-
- tcg_temp_free_i64(destright);
- tcg_temp_free_i64(destleft);
- tcg_temp_free_i64(right);
- tcg_temp_free_i64(middle);
- tcg_temp_free_i64(left);
- }
- return true;
-}
-
-static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
-{
- int n;
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
- TCGv_ptr ptr1;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- n = a->len + 1;
- if ((a->vn + n) > 32) {
- /*
- * This is UNPREDICTABLE; we choose to UNDEF to avoid the
- * helper function running off the end of the register file.
- */
- return false;
- }
- n <<= 3;
- if (a->op) {
- tmp = neon_load_reg(a->vd, 0);
- } else {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- }
- tmp2 = neon_load_reg(a->vm, 0);
- ptr1 = vfp_reg_ptr(true, a->vn);
- tmp4 = tcg_const_i32(n);
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
- tcg_temp_free_i32(tmp);
- if (a->op) {
- tmp = neon_load_reg(a->vd, 1);
- } else {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- }
- tmp3 = neon_load_reg(a->vm, 1);
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
- tcg_temp_free_i32(tmp4);
- tcg_temp_free_ptr(ptr1);
- neon_store_reg(a->vd, 0, tmp2);
- neon_store_reg(a->vd, 1, tmp3);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
-{
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vd & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
- neon_element_offset(a->vm, a->index, a->size),
- a->q ? 16 : 8, a->q ? 16 : 8);
- return true;
-}
-
-static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
-{
- int pass, half;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (a->size == 3) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
- TCGv_i32 tmp[2];
-
- for (half = 0; half < 2; half++) {
- tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
- switch (a->size) {
- case 0:
- tcg_gen_bswap32_i32(tmp[half], tmp[half]);
- break;
- case 1:
- gen_swap_half(tmp[half], tmp[half]);
- break;
- case 2:
- break;
- default:
- g_assert_not_reached();
- }
- }
- neon_store_reg(a->vd, pass * 2, tmp[1]);
- neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
- }
- return true;
-}
-
-static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
- NeonGenWidenFn *widenfn,
- NeonGenTwo64OpFn *opfn,
- NeonGenTwo64OpFn *accfn)
-{
- /*
- * Pairwise long operations: widen both halves of the pair,
- * combine the pairs with the opfn, and then possibly accumulate
- * into the destination with the accfn.
- */
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!widenfn) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- for (pass = 0; pass < a->q + 1; pass++) {
- TCGv_i32 tmp;
- TCGv_i64 rm0_64, rm1_64, rd_64;
-
- rm0_64 = tcg_temp_new_i64();
- rm1_64 = tcg_temp_new_i64();
- rd_64 = tcg_temp_new_i64();
- tmp = neon_load_reg(a->vm, pass * 2);
- widenfn(rm0_64, tmp);
- tcg_temp_free_i32(tmp);
- tmp = neon_load_reg(a->vm, pass * 2 + 1);
- widenfn(rm1_64, tmp);
- tcg_temp_free_i32(tmp);
- opfn(rd_64, rm0_64, rm1_64);
- tcg_temp_free_i64(rm0_64);
- tcg_temp_free_i64(rm1_64);
-
- if (accfn) {
- TCGv_i64 tmp64 = tcg_temp_new_i64();
- neon_load_reg64(tmp64, a->vd + pass);
- accfn(rd_64, tmp64, rd_64);
- tcg_temp_free_i64(tmp64);
- }
- neon_store_reg64(rd_64, a->vd + pass);
- tcg_temp_free_i64(rd_64);
- }
- return true;
-}
-
-static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_s8,
- gen_helper_neon_widen_s16,
- tcg_gen_ext_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
-}
-
-static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
-}
-
-static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_s8,
- gen_helper_neon_widen_s16,
- tcg_gen_ext_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
- accfn[a->size]);
-}
-
-static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
- accfn[a->size]);
-}
-
-typedef void ZipFn(TCGv_ptr, TCGv_ptr);
-
-static bool do_zip_uzp(DisasContext *s, arg_2misc *a,
- ZipFn *fn)
-{
- TCGv_ptr pd, pm;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!fn) {
- /* Bad size or size/q combination */
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- pd = vfp_reg_ptr(true, a->vd);
- pm = vfp_reg_ptr(true, a->vm);
- fn(pd, pm);
- tcg_temp_free_ptr(pd);
- tcg_temp_free_ptr(pm);
- return true;
-}
-
-static bool trans_VUZP(DisasContext *s, arg_2misc *a)
-{
- static ZipFn * const fn[2][4] = {
- {
- gen_helper_neon_unzip8,
- gen_helper_neon_unzip16,
- NULL,
- NULL,
- }, {
- gen_helper_neon_qunzip8,
- gen_helper_neon_qunzip16,
- gen_helper_neon_qunzip32,
- NULL,
- }
- };
- return do_zip_uzp(s, a, fn[a->q][a->size]);
-}
-
-static bool trans_VZIP(DisasContext *s, arg_2misc *a)
-{
- static ZipFn * const fn[2][4] = {
- {
- gen_helper_neon_zip8,
- gen_helper_neon_zip16,
- NULL,
- NULL,
- }, {
- gen_helper_neon_qzip8,
- gen_helper_neon_qzip16,
- gen_helper_neon_qzip32,
- NULL,
- }
- };
- return do_zip_uzp(s, a, fn[a->q][a->size]);
-}
-
-static bool do_vmovn(DisasContext *s, arg_2misc *a,
- NeonGenNarrowEnvFn *narrowfn)
-{
- TCGv_i64 rm;
- TCGv_i32 rd0, rd1;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vm & 1) {
- return false;
- }
-
- if (!narrowfn) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- rm = tcg_temp_new_i64();
- rd0 = tcg_temp_new_i32();
- rd1 = tcg_temp_new_i32();
-
- neon_load_reg64(rm, a->vm);
- narrowfn(rd0, cpu_env, rm);
- neon_load_reg64(rm, a->vm + 1);
- narrowfn(rd1, cpu_env, rm);
- neon_store_reg(a->vd, 0, rd0);
- neon_store_reg(a->vd, 1, rd1);
- tcg_temp_free_i64(rm);
- return true;
-}
-
-#define DO_VMOVN(INSN, FUNC) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- static NeonGenNarrowEnvFn * const narrowfn[] = { \
- FUNC##8, \
- FUNC##16, \
- FUNC##32, \
- NULL, \
- }; \
- return do_vmovn(s, a, narrowfn[a->size]); \
- }
-
-DO_VMOVN(VMOVN, gen_neon_narrow_u)
-DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat)
-DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s)
-DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u)
-
-static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
-{
- TCGv_i32 rm0, rm1;
- TCGv_i64 rd;
- static NeonGenWidenFn * const widenfns[] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- NULL,
- };
- NeonGenWidenFn *widenfn = widenfns[a->size];
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->vd & 1) {
- return false;
- }
-
- if (!widenfn) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- rd = tcg_temp_new_i64();
-
- rm0 = neon_load_reg(a->vm, 0);
- rm1 = neon_load_reg(a->vm, 1);
-
- widenfn(rd, rm0);
- tcg_gen_shli_i64(rd, rd, 8 << a->size);
- neon_store_reg64(rd, a->vd);
- widenfn(rd, rm1);
- tcg_gen_shli_i64(rd, rd, 8 << a->size);
- neon_store_reg64(rd, a->vd + 1);
-
- tcg_temp_free_i64(rd);
- tcg_temp_free_i32(rm0);
- tcg_temp_free_i32(rm1);
- return true;
-}
-
-static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 ahp, tmp, tmp2, tmp3;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
- !dc_isar_feature(aa32_fp16_spconv, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vm & 1) || (a->size != 1)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(true);
- ahp = get_ahp_flag();
- tmp = neon_load_reg(a->vm, 0);
- gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
- tmp2 = neon_load_reg(a->vm, 1);
- gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
- tcg_gen_shli_i32(tmp2, tmp2, 16);
- tcg_gen_or_i32(tmp2, tmp2, tmp);
- tcg_temp_free_i32(tmp);
- tmp = neon_load_reg(a->vm, 2);
- gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
- tmp3 = neon_load_reg(a->vm, 3);
- neon_store_reg(a->vd, 0, tmp2);
- gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
- tcg_gen_shli_i32(tmp3, tmp3, 16);
- tcg_gen_or_i32(tmp3, tmp3, tmp);
- neon_store_reg(a->vd, 1, tmp3);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(ahp);
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 ahp, tmp, tmp2, tmp3;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
- !dc_isar_feature(aa32_fp16_spconv, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd & 1) || (a->size != 1)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(true);
- ahp = get_ahp_flag();
- tmp3 = tcg_temp_new_i32();
- tmp = neon_load_reg(a->vm, 0);
- tmp2 = neon_load_reg(a->vm, 1);
- tcg_gen_ext16u_i32(tmp3, tmp);
- gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
- neon_store_reg(a->vd, 0, tmp3);
- tcg_gen_shri_i32(tmp, tmp, 16);
- gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
- neon_store_reg(a->vd, 1, tmp);
- tmp3 = tcg_temp_new_i32();
- tcg_gen_ext16u_i32(tmp3, tmp2);
- gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
- neon_store_reg(a->vd, 2, tmp3);
- tcg_gen_shri_i32(tmp2, tmp2, 16);
- gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
- neon_store_reg(a->vd, 3, tmp2);
- tcg_temp_free_i32(ahp);
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
-{
- int vec_size = a->q ? 16 : 8;
- int rd_ofs = neon_reg_offset(a->vd, 0);
- int rm_ofs = neon_reg_offset(a->vm, 0);
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->size == 3) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size);
-
- return true;
-}
-
-#define DO_2MISC_VEC(INSN, FN) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- return do_2misc_vec(s, a, FN); \
- }
-
-DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg)
-DO_2MISC_VEC(VABS, tcg_gen_gvec_abs)
-DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0)
-DO_2MISC_VEC(VCGT0, gen_gvec_cgt0)
-DO_2MISC_VEC(VCLE0, gen_gvec_cle0)
-DO_2MISC_VEC(VCGE0, gen_gvec_cge0)
-DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
-
-static bool trans_VMVN(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 0) {
- return false;
- }
- return do_2misc_vec(s, a, tcg_gen_gvec_not);
-}
-
-#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
- static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
- uint32_t rm_ofs, uint32_t oprsz, \
- uint32_t maxsz) \
- { \
- tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \
- DATA, FUNC); \
- }
-
-#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \
- static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
- uint32_t rm_ofs, uint32_t oprsz, \
- uint32_t maxsz) \
- { \
- tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \
- }
-
-WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0)
-WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1)
-WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0)
-WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1)
-WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0)
-WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0)
-WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0)
-
-#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \
- return false; \
- } \
- return do_2misc_vec(s, a, gen_##INSN); \
- }
-
-DO_2M_CRYPTO(AESE, aa32_aes, 0)
-DO_2M_CRYPTO(AESD, aa32_aes, 0)
-DO_2M_CRYPTO(AESMC, aa32_aes, 0)
-DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
-DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
-DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
-DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
-
-static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
-{
- int pass;
-
- /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (!fn) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
- fn(tmp, tmp);
- neon_store_reg(a->vd, pass, tmp);
- }
-
- return true;
-}
-
-static bool trans_VREV32(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- tcg_gen_bswap32_i32,
- gen_swap_half,
- NULL,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static bool trans_VREV16(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 0) {
- return false;
- }
- return do_2misc(s, a, gen_rev16);
-}
-
-static bool trans_VCLS(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- gen_helper_neon_cls_s8,
- gen_helper_neon_cls_s16,
- gen_helper_neon_cls_s32,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm)
-{
- tcg_gen_clzi_i32(rd, rm, 32);
-}
-
-static bool trans_VCLZ(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- gen_helper_neon_clz_u8,
- gen_helper_neon_clz_u16,
- do_VCLZ_32,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static bool trans_VCNT(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 0) {
- return false;
- }
- return do_2misc(s, a, gen_helper_neon_cnt_u8);
-}
-
-static bool trans_VABS_F(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 2) {
- return false;
- }
- /* TODO: FP16 : size == 1 */
- return do_2misc(s, a, gen_helper_vfp_abss);
-}
-
-static bool trans_VNEG_F(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 2) {
- return false;
- }
- /* TODO: FP16 : size == 1 */
- return do_2misc(s, a, gen_helper_vfp_negs);
-}
-
-static bool trans_VRECPE(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 2) {
- return false;
- }
- return do_2misc(s, a, gen_helper_recpe_u32);
-}
-
-static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 2) {
- return false;
- }
- return do_2misc(s, a, gen_helper_rsqrte_u32);
-}
-
-#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
- static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \
- { \
- FUNC(d, cpu_env, m); \
- }
-
-WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)
-WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16)
-WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32)
-WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8)
-WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16)
-WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32)
-
-static bool trans_VQABS(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- gen_VQABS_s8,
- gen_VQABS_s16,
- gen_VQABS_s32,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static bool trans_VQNEG(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- gen_VQNEG_s8,
- gen_VQNEG_s16,
- gen_VQNEG_s32,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static bool do_2misc_fp(DisasContext *s, arg_2misc *a,
- NeonGenOneSingleOpFn *fn)
-{
- int pass;
- TCGv_ptr fpst;
-
- /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->size != 2) {
- /* TODO: FP16 will be the size == 1 case */
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(1);
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
- fn(tmp, tmp, fpst);
- neon_store_reg(a->vd, pass, tmp);
- }
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-#define DO_2MISC_FP(INSN, FUNC) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- return do_2misc_fp(s, a, FUNC); \
- }
-
-DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32)
-DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32)
-DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos)
-DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos)
-DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs)
-DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs)
-
-static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
-{
- if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
- return do_2misc_fp(s, a, gen_helper_rints_exact);
-}
-
-#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \
- static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
- { \
- TCGv_i32 zero = tcg_const_i32(0); \
- FUNC(d, m, zero, fpst); \
- tcg_temp_free_i32(zero); \
- }
-#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \
- static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
- { \
- TCGv_i32 zero = tcg_const_i32(0); \
- FUNC(d, zero, m, fpst); \
- tcg_temp_free_i32(zero); \
- }
-
-#define DO_FP_CMP0(INSN, FUNC, REV) \
- WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- return do_2misc_fp(s, a, gen_##INSN); \
- }
-
-DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD)
-DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
-DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
-DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
-DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)
-
-static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode)
-{
- /*
- * Handle a VRINT* operation by iterating 32 bits at a time,
- * with a specified rounding mode in operation.
- */
- int pass;
- TCGv_ptr fpst;
- TCGv_i32 tcg_rmode;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
- !arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->size != 2) {
- /* TODO: FP16 will be the size == 1 case */
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(1);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
- gen_helper_rints(tmp, tmp, fpst);
- neon_store_reg(a->vd, pass, tmp);
- }
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
- tcg_temp_free_i32(tcg_rmode);
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-#define DO_VRINT(INSN, RMODE) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- return do_vrint(s, a, RMODE); \
- }
-
-DO_VRINT(VRINTN, FPROUNDING_TIEEVEN)
-DO_VRINT(VRINTA, FPROUNDING_TIEAWAY)
-DO_VRINT(VRINTZ, FPROUNDING_ZERO)
-DO_VRINT(VRINTM, FPROUNDING_NEGINF)
-DO_VRINT(VRINTP, FPROUNDING_POSINF)
-
-static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed)
-{
- /*
- * Handle a VCVT* operation by iterating 32 bits at a time,
- * with a specified rounding mode in operation.
- */
- int pass;
- TCGv_ptr fpst;
- TCGv_i32 tcg_rmode, tcg_shift;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
- !arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->size != 2) {
- /* TODO: FP16 will be the size == 1 case */
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(1);
- tcg_shift = tcg_const_i32(0);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
- if (is_signed) {
- gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst);
- } else {
- gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst);
- }
- neon_store_reg(a->vd, pass, tmp);
- }
- gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env);
- tcg_temp_free_i32(tcg_rmode);
- tcg_temp_free_i32(tcg_shift);
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-#define DO_VCVT(INSN, RMODE, SIGNED) \
- static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
- { \
- return do_vcvt(s, a, RMODE, SIGNED); \
- }
-
-DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false)
-DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true)
-DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false)
-DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true)
-DO_VCVT(VCVTPU, FPROUNDING_POSINF, false)
-DO_VCVT(VCVTPS, FPROUNDING_POSINF, true)
-DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false)
-DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true)
-
-static bool trans_VSWP(DisasContext *s, arg_2misc *a)
-{
- TCGv_i64 rm, rd;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (a->size != 0) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- rm = tcg_temp_new_i64();
- rd = tcg_temp_new_i64();
- for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
- neon_load_reg64(rm, a->vm + pass);
- neon_load_reg64(rd, a->vd + pass);
- neon_store_reg64(rm, a->vd + pass);
- neon_store_reg64(rd, a->vm + pass);
- }
- tcg_temp_free_i64(rm);
- tcg_temp_free_i64(rd);
-
- return true;
-}
-static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
-{
- TCGv_i32 rd, tmp;
-
- rd = tcg_temp_new_i32();
- tmp = tcg_temp_new_i32();
-
- tcg_gen_shli_i32(rd, t0, 8);
- tcg_gen_andi_i32(rd, rd, 0xff00ff00);
- tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
- tcg_gen_or_i32(rd, rd, tmp);
-
- tcg_gen_shri_i32(t1, t1, 8);
- tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
- tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
- tcg_gen_or_i32(t1, t1, tmp);
- tcg_gen_mov_i32(t0, rd);
-
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(rd);
-}
-
-static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
-{
- TCGv_i32 rd, tmp;
-
- rd = tcg_temp_new_i32();
- tmp = tcg_temp_new_i32();
-
- tcg_gen_shli_i32(rd, t0, 16);
- tcg_gen_andi_i32(tmp, t1, 0xffff);
- tcg_gen_or_i32(rd, rd, tmp);
- tcg_gen_shri_i32(t1, t1, 16);
- tcg_gen_andi_i32(tmp, t0, 0xffff0000);
- tcg_gen_or_i32(t1, t1, tmp);
- tcg_gen_mov_i32(t0, rd);
-
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(rd);
-}
-
-static bool trans_VTRN(DisasContext *s, arg_2misc *a)
-{
- TCGv_i32 tmp, tmp2;
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (a->size == 3) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (a->size == 2) {
- for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
- tmp = neon_load_reg(a->vm, pass);
- tmp2 = neon_load_reg(a->vd, pass + 1);
- neon_store_reg(a->vm, pass, tmp2);
- neon_store_reg(a->vd, pass + 1, tmp);
- }
- } else {
- for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
- tmp = neon_load_reg(a->vm, pass);
- tmp2 = neon_load_reg(a->vd, pass);
- if (a->size == 0) {
- gen_neon_trn_u8(tmp, tmp2);
- } else {
- gen_neon_trn_u16(tmp, tmp2);
- }
- neon_store_reg(a->vm, pass, tmp2);
- neon_store_reg(a->vd, pass, tmp);
- }
- }
- return true;
-}
* Include the generated decoder.
*/
-#include "decode-sve.inc.c"
+#include "decode-sve.c.inc"
/*
* Implement all of the translator functions referenced by the decoder.
--- /dev/null
+/*
+ * ARM translation: AArch32 VFP instructions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2005-2007 CodeSourcery
+ * Copyright (c) 2007 OpenedHand, Ltd.
+ * Copyright (c) 2019 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file is intended to be included from translate.c; it uses
+ * some macros and definitions provided by that file.
+ * It might be possible to convert it to a standalone .c file eventually.
+ */
+
+/* Include the generated VFP decoder */
+#include "decode-vfp.c.inc"
+#include "decode-vfp-uncond.c.inc"
+
+/*
+ * The imm8 encodes the sign bit, enough bits to represent an exponent in
+ * the range 01....1xx to 10....0xx, and the most significant 4 bits of
+ * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
+ */
+uint64_t vfp_expand_imm(int size, uint8_t imm8)
+{
+ uint64_t imm;
+
+ switch (size) {
+ case MO_64:
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
+ extract32(imm8, 0, 6);
+ imm <<= 48;
+ break;
+ case MO_32:
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
+ (extract32(imm8, 0, 6) << 3);
+ imm <<= 16;
+ break;
+ case MO_16:
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
+ (extract32(imm8, 0, 6) << 6);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return imm;
+}
+
+/*
+ * Return the offset of a 16-bit half of the specified VFP single-precision
+ * register. If top is true, returns the top 16 bits; otherwise the bottom
+ * 16 bits.
+ */
+static inline long vfp_f16_offset(unsigned reg, bool top)
+{
+ long offs = vfp_reg_offset(false, reg);
+#ifdef HOST_WORDS_BIGENDIAN
+ if (!top) {
+ offs += 2;
+ }
+#else
+ if (top) {
+ offs += 2;
+ }
+#endif
+ return offs;
+}
+
+/*
+ * Check that VFP access is enabled. If it is, do the necessary
+ * M-profile lazy-FP handling and then return true.
+ * If not, emit code to generate an appropriate exception and
+ * return false.
+ * The ignore_vfp_enabled argument specifies that we should ignore
+ * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
+ * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
+ */
+static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
+{
+ if (s->fp_excp_el) {
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
+ s->fp_excp_el);
+ } else {
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_fp_access_trap(1, 0xe, false),
+ s->fp_excp_el);
+ }
+ return false;
+ }
+
+ if (!s->vfp_enabled && !ignore_vfp_enabled) {
+ assert(!arm_dc_feature(s, ARM_FEATURE_M));
+ unallocated_encoding(s);
+ return false;
+ }
+
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ /* Handle M-profile lazy FP state mechanics */
+
+ /* Trigger lazy-state preservation if necessary */
+ if (s->v7m_lspact) {
+ /*
+ * Lazy state saving affects external memory and also the NVIC,
+ * so we must mark it as an IO operation for icount (and cause
+ * this to be the last insn in the TB).
+ */
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
+ gen_io_start();
+ }
+ gen_helper_v7m_preserve_fp_state(cpu_env);
+ /*
+ * If the preserve_fp_state helper doesn't throw an exception
+ * then it will clear LSPACT; we don't need to repeat this for
+ * any further FP insns in this TB.
+ */
+ s->v7m_lspact = false;
+ }
+
+ /* Update ownership of FP context: set FPCCR.S to match current state */
+ if (s->v8m_fpccr_s_wrong) {
+ TCGv_i32 tmp;
+
+ tmp = load_cpu_field(v7m.fpccr[M_REG_S]);
+ if (s->v8m_secure) {
+ tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK);
+ } else {
+ tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK);
+ }
+ store_cpu_field(tmp, v7m.fpccr[M_REG_S]);
+ /* Don't need to do this for any further FP insns in this TB */
+ s->v8m_fpccr_s_wrong = false;
+ }
+
+ if (s->v7m_new_fp_ctxt_needed) {
+ /*
+ * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
+ * and the FPSCR.
+ */
+ TCGv_i32 control, fpscr;
+ uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
+
+ fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ tcg_temp_free_i32(fpscr);
+ /*
+ * We don't need to arrange to end the TB, because the only
+ * parts of FPSCR which we cache in the TB flags are the VECLEN
+ * and VECSTRIDE, and those don't exist for M-profile.
+ */
+
+ if (s->v8m_secure) {
+ bits |= R_V7M_CONTROL_SFPA_MASK;
+ }
+ control = load_cpu_field(v7m.control[M_REG_S]);
+ tcg_gen_ori_i32(control, control, bits);
+ store_cpu_field(control, v7m.control[M_REG_S]);
+ /* Don't need to do this for any further FP insns in this TB */
+ s->v7m_new_fp_ctxt_needed = false;
+ }
+ }
+
+ return true;
+}
+
+/*
+ * The most usual kind of VFP access check, for everything except
+ * FMXR/FMRX to the always-available special registers.
+ */
+static bool vfp_access_check(DisasContext *s)
+{
+ return full_vfp_access_check(s, false);
+}
+
+static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
+{
+ uint32_t rd, rn, rm;
+ bool dp = a->dp;
+
+ if (!dc_isar_feature(aa32_vsel, s)) {
+ return false;
+ }
+
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
+ return false;
+ }
+
+ rd = a->vd;
+ rn = a->vn;
+ rm = a->vm;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (dp) {
+ TCGv_i64 frn, frm, dest;
+ TCGv_i64 tmp, zero, zf, nf, vf;
+
+ zero = tcg_const_i64(0);
+
+ frn = tcg_temp_new_i64();
+ frm = tcg_temp_new_i64();
+ dest = tcg_temp_new_i64();
+
+ zf = tcg_temp_new_i64();
+ nf = tcg_temp_new_i64();
+ vf = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(zf, cpu_ZF);
+ tcg_gen_ext_i32_i64(nf, cpu_NF);
+ tcg_gen_ext_i32_i64(vf, cpu_VF);
+
+ neon_load_reg64(frn, rn);
+ neon_load_reg64(frm, rm);
+ switch (a->cc) {
+ case 0: /* eq: Z */
+ tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
+ frn, frm);
+ break;
+ case 1: /* vs: V */
+ tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero,
+ frn, frm);
+ break;
+ case 2: /* ge: N == V -> N ^ V == 0 */
+ tmp = tcg_temp_new_i64();
+ tcg_gen_xor_i64(tmp, vf, nf);
+ tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
+ frn, frm);
+ tcg_temp_free_i64(tmp);
+ break;
+ case 3: /* gt: !Z && N == V */
+ tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero,
+ frn, frm);
+ tmp = tcg_temp_new_i64();
+ tcg_gen_xor_i64(tmp, vf, nf);
+ tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
+ dest, frm);
+ tcg_temp_free_i64(tmp);
+ break;
+ }
+ neon_store_reg64(dest, rd);
+ tcg_temp_free_i64(frn);
+ tcg_temp_free_i64(frm);
+ tcg_temp_free_i64(dest);
+
+ tcg_temp_free_i64(zf);
+ tcg_temp_free_i64(nf);
+ tcg_temp_free_i64(vf);
+
+ tcg_temp_free_i64(zero);
+ } else {
+ TCGv_i32 frn, frm, dest;
+ TCGv_i32 tmp, zero;
+
+ zero = tcg_const_i32(0);
+
+ frn = tcg_temp_new_i32();
+ frm = tcg_temp_new_i32();
+ dest = tcg_temp_new_i32();
+ neon_load_reg32(frn, rn);
+ neon_load_reg32(frm, rm);
+ switch (a->cc) {
+ case 0: /* eq: Z */
+ tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
+ frn, frm);
+ break;
+ case 1: /* vs: V */
+ tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero,
+ frn, frm);
+ break;
+ case 2: /* ge: N == V -> N ^ V == 0 */
+ tmp = tcg_temp_new_i32();
+ tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+ tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
+ frn, frm);
+ tcg_temp_free_i32(tmp);
+ break;
+ case 3: /* gt: !Z && N == V */
+ tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero,
+ frn, frm);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
+ tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
+ dest, frm);
+ tcg_temp_free_i32(tmp);
+ break;
+ }
+ neon_store_reg32(dest, rd);
+ tcg_temp_free_i32(frn);
+ tcg_temp_free_i32(frm);
+ tcg_temp_free_i32(dest);
+
+ tcg_temp_free_i32(zero);
+ }
+
+ return true;
+}
+
+/*
+ * Table for converting the most common AArch32 encoding of
+ * rounding mode to arm_fprounding order (which matches the
+ * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
+ */
+static const uint8_t fp_decode_rm[] = {
+ FPROUNDING_TIEAWAY,
+ FPROUNDING_TIEEVEN,
+ FPROUNDING_POSINF,
+ FPROUNDING_NEGINF,
+};
+
+static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
+{
+ uint32_t rd, rm;
+ bool dp = a->dp;
+ TCGv_ptr fpst;
+ TCGv_i32 tcg_rmode;
+ int rounding = fp_decode_rm[a->rm];
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vd) & 0x10)) {
+ return false;
+ }
+
+ rd = a->vd;
+ rm = a->vm;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(0);
+
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+
+ if (dp) {
+ TCGv_i64 tcg_op;
+ TCGv_i64 tcg_res;
+ tcg_op = tcg_temp_new_i64();
+ tcg_res = tcg_temp_new_i64();
+ neon_load_reg64(tcg_op, rm);
+ gen_helper_rintd(tcg_res, tcg_op, fpst);
+ neon_store_reg64(tcg_res, rd);
+ tcg_temp_free_i64(tcg_op);
+ tcg_temp_free_i64(tcg_res);
+ } else {
+ TCGv_i32 tcg_op;
+ TCGv_i32 tcg_res;
+ tcg_op = tcg_temp_new_i32();
+ tcg_res = tcg_temp_new_i32();
+ neon_load_reg32(tcg_op, rm);
+ gen_helper_rints(tcg_res, tcg_op, fpst);
+ neon_store_reg32(tcg_res, rd);
+ tcg_temp_free_i32(tcg_op);
+ tcg_temp_free_i32(tcg_res);
+ }
+
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_temp_free_i32(tcg_rmode);
+
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
+{
+ uint32_t rd, rm;
+ bool dp = a->dp;
+ TCGv_ptr fpst;
+ TCGv_i32 tcg_rmode, tcg_shift;
+ int rounding = fp_decode_rm[a->rm];
+ bool is_signed = a->op;
+
+ if (!dc_isar_feature(aa32_vcvt_dr, s)) {
+ return false;
+ }
+
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ rd = a->vd;
+ rm = a->vm;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(0);
+
+ tcg_shift = tcg_const_i32(0);
+
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+
+ if (dp) {
+ TCGv_i64 tcg_double, tcg_res;
+ TCGv_i32 tcg_tmp;
+ tcg_double = tcg_temp_new_i64();
+ tcg_res = tcg_temp_new_i64();
+ tcg_tmp = tcg_temp_new_i32();
+ neon_load_reg64(tcg_double, rm);
+ if (is_signed) {
+ gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
+ } else {
+ gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
+ }
+ tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
+ neon_store_reg32(tcg_tmp, rd);
+ tcg_temp_free_i32(tcg_tmp);
+ tcg_temp_free_i64(tcg_res);
+ tcg_temp_free_i64(tcg_double);
+ } else {
+ TCGv_i32 tcg_single, tcg_res;
+ tcg_single = tcg_temp_new_i32();
+ tcg_res = tcg_temp_new_i32();
+ neon_load_reg32(tcg_single, rm);
+ if (is_signed) {
+ gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
+ } else {
+ gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
+ }
+ neon_store_reg32(tcg_res, rd);
+ tcg_temp_free_i32(tcg_res);
+ tcg_temp_free_i32(tcg_single);
+ }
+
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_temp_free_i32(tcg_rmode);
+
+ tcg_temp_free_i32(tcg_shift);
+
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
+{
+ /* VMOV scalar to general purpose register */
+ TCGv_i32 tmp;
+ int pass;
+ uint32_t offset;
+
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
+ if (a->size == 2
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
+ return false;
+ }
+
+ offset = a->index << a->size;
+ pass = extract32(offset, 2, 1);
+ offset = extract32(offset, 0, 2) * 8;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = neon_load_reg(a->vn, pass);
+ switch (a->size) {
+ case 0:
+ if (offset) {
+ tcg_gen_shri_i32(tmp, tmp, offset);
+ }
+ if (a->u) {
+ gen_uxtb(tmp);
+ } else {
+ gen_sxtb(tmp);
+ }
+ break;
+ case 1:
+ if (a->u) {
+ if (offset) {
+ tcg_gen_shri_i32(tmp, tmp, 16);
+ } else {
+ gen_uxth(tmp);
+ }
+ } else {
+ if (offset) {
+ tcg_gen_sari_i32(tmp, tmp, 16);
+ } else {
+ gen_sxth(tmp);
+ }
+ }
+ break;
+ case 2:
+ break;
+ }
+ store_reg(s, a->rt, tmp);
+
+ return true;
+}
+
+static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
+{
+ /* VMOV general purpose register to scalar */
+ TCGv_i32 tmp, tmp2;
+ int pass;
+ uint32_t offset;
+
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
+ if (a->size == 2
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
+ return false;
+ }
+
+ offset = a->index << a->size;
+ pass = extract32(offset, 2, 1);
+ offset = extract32(offset, 0, 2) * 8;
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = load_reg(s, a->rt);
+ switch (a->size) {
+ case 0:
+ tmp2 = neon_load_reg(a->vn, pass);
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
+ tcg_temp_free_i32(tmp2);
+ break;
+ case 1:
+ tmp2 = neon_load_reg(a->vn, pass);
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
+ tcg_temp_free_i32(tmp2);
+ break;
+ case 2:
+ break;
+ }
+ neon_store_reg(a->vn, pass, tmp);
+
+ return true;
+}
+
+static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
+{
+ /* VDUP (general purpose register) */
+ TCGv_i32 tmp;
+ int size, vec_size;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
+ return false;
+ }
+
+ if (a->b && a->e) {
+ return false;
+ }
+
+ if (a->q && (a->vn & 1)) {
+ return false;
+ }
+
+ vec_size = a->q ? 16 : 8;
+ if (a->b) {
+ size = 0;
+ } else if (a->e) {
+ size = 1;
+ } else {
+ size = 2;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = load_reg(s, a->rt);
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
+ vec_size, vec_size, tmp);
+ tcg_temp_free_i32(tmp);
+
+ return true;
+}
+
+static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
+{
+ TCGv_i32 tmp;
+ bool ignore_vfp_enabled = false;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ /*
+ * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
+ * Accesses to R15 are UNPREDICTABLE; we choose to undef.
+ * (FPSCR -> r15 is a special case which writes to the PSR flags.)
+ */
+ if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
+ return false;
+ }
+ }
+
+ switch (a->reg) {
+ case ARM_VFP_FPSID:
+ /*
+ * VFPv2 allows access to FPSID from userspace; VFPv3 restricts
+ * all ID registers to privileged access only.
+ */
+ if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
+ return false;
+ }
+ ignore_vfp_enabled = true;
+ break;
+ case ARM_VFP_MVFR0:
+ case ARM_VFP_MVFR1:
+ if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
+ return false;
+ }
+ ignore_vfp_enabled = true;
+ break;
+ case ARM_VFP_MVFR2:
+ if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ ignore_vfp_enabled = true;
+ break;
+ case ARM_VFP_FPSCR:
+ break;
+ case ARM_VFP_FPEXC:
+ if (IS_USER(s)) {
+ return false;
+ }
+ ignore_vfp_enabled = true;
+ break;
+ case ARM_VFP_FPINST:
+ case ARM_VFP_FPINST2:
+ /* Not present in VFPv3 */
+ if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
+ return false;
+ }
+ break;
+ default:
+ return false;
+ }
+
+ if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
+ return true;
+ }
+
+ if (a->l) {
+ /* VMRS, move VFP special register to gp register */
+ switch (a->reg) {
+ case ARM_VFP_MVFR0:
+ case ARM_VFP_MVFR1:
+ case ARM_VFP_MVFR2:
+ case ARM_VFP_FPSID:
+ if (s->current_el == 1) {
+ TCGv_i32 tcg_reg, tcg_rt;
+
+ gen_set_condexec(s);
+ gen_set_pc_im(s, s->pc_curr);
+ tcg_reg = tcg_const_i32(a->reg);
+ tcg_rt = tcg_const_i32(a->rt);
+ gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg);
+ tcg_temp_free_i32(tcg_reg);
+ tcg_temp_free_i32(tcg_rt);
+ }
+ /* fall through */
+ case ARM_VFP_FPEXC:
+ case ARM_VFP_FPINST:
+ case ARM_VFP_FPINST2:
+ tmp = load_cpu_field(vfp.xregs[a->reg]);
+ break;
+ case ARM_VFP_FPSCR:
+ if (a->rt == 15) {
+ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+ tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+ } else {
+ tmp = tcg_temp_new_i32();
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (a->rt == 15) {
+ /* Set the 4 flag bits in the CPSR. */
+ gen_set_nzcv(tmp);
+ tcg_temp_free_i32(tmp);
+ } else {
+ store_reg(s, a->rt, tmp);
+ }
+ } else {
+ /* VMSR, move gp register to VFP special register */
+ switch (a->reg) {
+ case ARM_VFP_FPSID:
+ case ARM_VFP_MVFR0:
+ case ARM_VFP_MVFR1:
+ case ARM_VFP_MVFR2:
+ /* Writes are ignored. */
+ break;
+ case ARM_VFP_FPSCR:
+ tmp = load_reg(s, a->rt);
+ gen_helper_vfp_set_fpscr(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
+ gen_lookup_tb(s);
+ break;
+ case ARM_VFP_FPEXC:
+ /*
+ * TODO: VFP subarchitecture support.
+ * For now, keep the EN bit only
+ */
+ tmp = load_reg(s, a->rt);
+ tcg_gen_andi_i32(tmp, tmp, 1 << 30);
+ store_cpu_field(tmp, vfp.xregs[a->reg]);
+ gen_lookup_tb(s);
+ break;
+ case ARM_VFP_FPINST:
+ case ARM_VFP_FPINST2:
+ tmp = load_reg(s, a->rt);
+ store_cpu_field(tmp, vfp.xregs[a->reg]);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+
+ return true;
+}
+
+static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
+{
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (a->l) {
+ /* VFP to general purpose register */
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vn);
+ if (a->rt == 15) {
+ /* Set the 4 flag bits in the CPSR. */
+ gen_set_nzcv(tmp);
+ tcg_temp_free_i32(tmp);
+ } else {
+ store_reg(s, a->rt, tmp);
+ }
+ } else {
+ /* general purpose register to VFP */
+ tmp = load_reg(s, a->rt);
+ neon_store_reg32(tmp, a->vn);
+ tcg_temp_free_i32(tmp);
+ }
+
+ return true;
+}
+
+static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
+{
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ /*
+ * VMOV between two general-purpose registers and two single precision
+ * floating point registers
+ */
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (a->op) {
+ /* fpreg to gpreg */
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm);
+ store_reg(s, a->rt, tmp);
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm + 1);
+ store_reg(s, a->rt2, tmp);
+ } else {
+ /* gpreg to fpreg */
+ tmp = load_reg(s, a->rt);
+ neon_store_reg32(tmp, a->vm);
+ tcg_temp_free_i32(tmp);
+ tmp = load_reg(s, a->rt2);
+ neon_store_reg32(tmp, a->vm + 1);
+ tcg_temp_free_i32(tmp);
+ }
+
+ return true;
+}
+
+static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
+{
+ TCGv_i32 tmp;
+
+ /*
+ * VMOV between two general-purpose registers and one double precision
+ * floating point register. Note that this does not require support
+ * for double precision arithmetic.
+ */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (a->op) {
+ /* fpreg to gpreg */
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm * 2);
+ store_reg(s, a->rt, tmp);
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm * 2 + 1);
+ store_reg(s, a->rt2, tmp);
+ } else {
+ /* gpreg to fpreg */
+ tmp = load_reg(s, a->rt);
+ neon_store_reg32(tmp, a->vm * 2);
+ tcg_temp_free_i32(tmp);
+ tmp = load_reg(s, a->rt2);
+ neon_store_reg32(tmp, a->vm * 2 + 1);
+ tcg_temp_free_i32(tmp);
+ }
+
+ return true;
+}
+
+static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
+{
+ uint32_t offset;
+ TCGv_i32 addr, tmp;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ offset = a->imm << 2;
+ if (!a->u) {
+ offset = -offset;
+ }
+
+ /* For thumb, use of PC is UNPREDICTABLE. */
+ addr = add_reg_for_lit(s, a->rn, offset);
+ tmp = tcg_temp_new_i32();
+ if (a->l) {
+ gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ neon_store_reg32(tmp, a->vd);
+ } else {
+ neon_load_reg32(tmp, a->vd);
+ gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ }
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(addr);
+
+ return true;
+}
+
+static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
+{
+ uint32_t offset;
+ TCGv_i32 addr;
+ TCGv_i64 tmp;
+
+ /* Note that this does not require support for double arithmetic. */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ offset = a->imm << 2;
+ if (!a->u) {
+ offset = -offset;
+ }
+
+ /* For thumb, use of PC is UNPREDICTABLE. */
+ addr = add_reg_for_lit(s, a->rn, offset);
+ tmp = tcg_temp_new_i64();
+ if (a->l) {
+ gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ neon_store_reg64(tmp, a->vd);
+ } else {
+ neon_load_reg64(tmp, a->vd);
+ gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ }
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i32(addr);
+
+ return true;
+}
+
+static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
+{
+ uint32_t offset;
+ TCGv_i32 addr, tmp;
+ int i, n;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ n = a->imm;
+
+ if (n == 0 || (a->vd + n) > 32) {
+ /*
+ * UNPREDICTABLE cases for bad immediates: we choose to
+ * UNDEF to avoid generating huge numbers of TCG ops
+ */
+ return false;
+ }
+ if (a->rn == 15 && a->w) {
+ /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /* For thumb, use of PC is UNPREDICTABLE. */
+ addr = add_reg_for_lit(s, a->rn, 0);
+ if (a->p) {
+ /* pre-decrement */
+ tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
+ }
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ /*
+ * Here 'addr' is the lowest address we will store to,
+ * and is either the old SP (if post-increment) or
+ * the new SP (if pre-decrement). For post-increment
+ * where the old value is below the limit and the new
+ * value is above, it is UNKNOWN whether the limit check
+ * triggers; we choose to trigger.
+ */
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
+ offset = 4;
+ tmp = tcg_temp_new_i32();
+ for (i = 0; i < n; i++) {
+ if (a->l) {
+ /* load */
+ gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ neon_store_reg32(tmp, a->vd + i);
+ } else {
+ /* store */
+ neon_load_reg32(tmp, a->vd + i);
+ gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+ tcg_temp_free_i32(tmp);
+ if (a->w) {
+ /* writeback */
+ if (a->p) {
+ offset = -offset * n;
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+
+ return true;
+}
+
+static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
+{
+ uint32_t offset;
+ TCGv_i32 addr;
+ TCGv_i64 tmp;
+ int i, n;
+
+ /* Note that this does not require support for double arithmetic. */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ n = a->imm >> 1;
+
+ if (n == 0 || (a->vd + n) > 32 || n > 16) {
+ /*
+ * UNPREDICTABLE cases for bad immediates: we choose to
+ * UNDEF to avoid generating huge numbers of TCG ops
+ */
+ return false;
+ }
+ if (a->rn == 15 && a->w) {
+ /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /* For thumb, use of PC is UNPREDICTABLE. */
+ addr = add_reg_for_lit(s, a->rn, 0);
+ if (a->p) {
+ /* pre-decrement */
+ tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
+ }
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ /*
+ * Here 'addr' is the lowest address we will store to,
+ * and is either the old SP (if post-increment) or
+ * the new SP (if pre-decrement). For post-increment
+ * where the old value is below the limit and the new
+ * value is above, it is UNKNOWN whether the limit check
+ * triggers; we choose to trigger.
+ */
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
+ offset = 8;
+ tmp = tcg_temp_new_i64();
+ for (i = 0; i < n; i++) {
+ if (a->l) {
+ /* load */
+ gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ neon_store_reg64(tmp, a->vd + i);
+ } else {
+ /* store */
+ neon_load_reg64(tmp, a->vd + i);
+ gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+ tcg_temp_free_i64(tmp);
+ if (a->w) {
+ /* writeback */
+ if (a->p) {
+ offset = -offset * n;
+ } else if (a->imm & 1) {
+ offset = 4;
+ } else {
+ offset = 0;
+ }
+
+ if (offset != 0) {
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+
+ return true;
+}
+
+/*
+ * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
+ * The callback should emit code to write a value to vd. If
+ * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
+ * will contain the old value of the relevant VFP register;
+ * otherwise it must be written to only.
+ */
+typedef void VFPGen3OpSPFn(TCGv_i32 vd,
+ TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst);
+typedef void VFPGen3OpDPFn(TCGv_i64 vd,
+ TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst);
+
+/*
+ * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
+ * The callback should emit code to write a value to vd (which
+ * should be written to only).
+ */
+typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm);
+typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm);
+
+/*
+ * Return true if the specified S reg is in a scalar bank
+ * (ie if it is s0..s7)
+ */
+static inline bool vfp_sreg_is_scalar(int reg)
+{
+ return (reg & 0x18) == 0;
+}
+
+/*
+ * Return true if the specified D reg is in a scalar bank
+ * (ie if it is d0..d3 or d16..d19)
+ */
+static inline bool vfp_dreg_is_scalar(int reg)
+{
+ return (reg & 0xc) == 0;
+}
+
+/*
+ * Advance the S reg number forwards by delta within its bank
+ * (ie increment the low 3 bits but leave the rest the same)
+ */
+static inline int vfp_advance_sreg(int reg, int delta)
+{
+ return ((reg + delta) & 0x7) | (reg & ~0x7);
+}
+
+/*
+ * Advance the D reg number forwards by delta within its bank
+ * (ie increment the low 2 bits but leave the rest the same)
+ */
+static inline int vfp_advance_dreg(int reg, int delta)
+{
+ return ((reg + delta) & 0x3) | (reg & ~0x3);
+}
+
+/*
+ * Perform a 3-operand VFP data processing instruction. fn is the
+ * callback to do the actual operation; this function deals with the
+ * code to handle looping around for VFP vector processing.
+ */
+static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
+ int vd, int vn, int vm, bool reads_vd)
+{
+ uint32_t delta_m = 0;
+ uint32_t delta_d = 0;
+ int veclen = s->vec_len;
+ TCGv_i32 f0, f1, fd;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (veclen > 0) {
+ /* Figure out what type of vector operation this is. */
+ if (vfp_sreg_is_scalar(vd)) {
+ /* scalar */
+ veclen = 0;
+ } else {
+ delta_d = s->vec_stride + 1;
+
+ if (vfp_sreg_is_scalar(vm)) {
+ /* mixed scalar/vector */
+ delta_m = 0;
+ } else {
+ /* vector */
+ delta_m = delta_d;
+ }
+ }
+ }
+
+ f0 = tcg_temp_new_i32();
+ f1 = tcg_temp_new_i32();
+ fd = tcg_temp_new_i32();
+ fpst = get_fpstatus_ptr(0);
+
+ neon_load_reg32(f0, vn);
+ neon_load_reg32(f1, vm);
+
+ for (;;) {
+ if (reads_vd) {
+ neon_load_reg32(fd, vd);
+ }
+ fn(fd, f0, f1, fpst);
+ neon_store_reg32(fd, vd);
+
+ if (veclen == 0) {
+ break;
+ }
+
+ /* Set up the operands for the next iteration */
+ veclen--;
+ vd = vfp_advance_sreg(vd, delta_d);
+ vn = vfp_advance_sreg(vn, delta_d);
+ neon_load_reg32(f0, vn);
+ if (delta_m) {
+ vm = vfp_advance_sreg(vm, delta_m);
+ neon_load_reg32(f1, vm);
+ }
+ }
+
+ tcg_temp_free_i32(f0);
+ tcg_temp_free_i32(f1);
+ tcg_temp_free_i32(fd);
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
+ int vd, int vn, int vm, bool reads_vd)
+{
+ uint32_t delta_m = 0;
+ uint32_t delta_d = 0;
+ int veclen = s->vec_len;
+ TCGv_i64 f0, f1, fd;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (veclen > 0) {
+ /* Figure out what type of vector operation this is. */
+ if (vfp_dreg_is_scalar(vd)) {
+ /* scalar */
+ veclen = 0;
+ } else {
+ delta_d = (s->vec_stride >> 1) + 1;
+
+ if (vfp_dreg_is_scalar(vm)) {
+ /* mixed scalar/vector */
+ delta_m = 0;
+ } else {
+ /* vector */
+ delta_m = delta_d;
+ }
+ }
+ }
+
+ f0 = tcg_temp_new_i64();
+ f1 = tcg_temp_new_i64();
+ fd = tcg_temp_new_i64();
+ fpst = get_fpstatus_ptr(0);
+
+ neon_load_reg64(f0, vn);
+ neon_load_reg64(f1, vm);
+
+ for (;;) {
+ if (reads_vd) {
+ neon_load_reg64(fd, vd);
+ }
+ fn(fd, f0, f1, fpst);
+ neon_store_reg64(fd, vd);
+
+ if (veclen == 0) {
+ break;
+ }
+ /* Set up the operands for the next iteration */
+ veclen--;
+ vd = vfp_advance_dreg(vd, delta_d);
+ vn = vfp_advance_dreg(vn, delta_d);
+ neon_load_reg64(f0, vn);
+ if (delta_m) {
+ vm = vfp_advance_dreg(vm, delta_m);
+ neon_load_reg64(f1, vm);
+ }
+ }
+
+ tcg_temp_free_i64(f0);
+ tcg_temp_free_i64(f1);
+ tcg_temp_free_i64(fd);
+ tcg_temp_free_ptr(fpst);
+
+ return true;
+}
+
+static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
+{
+ uint32_t delta_m = 0;
+ uint32_t delta_d = 0;
+ int veclen = s->vec_len;
+ TCGv_i32 f0, fd;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (veclen > 0) {
+ /* Figure out what type of vector operation this is. */
+ if (vfp_sreg_is_scalar(vd)) {
+ /* scalar */
+ veclen = 0;
+ } else {
+ delta_d = s->vec_stride + 1;
+
+ if (vfp_sreg_is_scalar(vm)) {
+ /* mixed scalar/vector */
+ delta_m = 0;
+ } else {
+ /* vector */
+ delta_m = delta_d;
+ }
+ }
+ }
+
+ f0 = tcg_temp_new_i32();
+ fd = tcg_temp_new_i32();
+
+ neon_load_reg32(f0, vm);
+
+ for (;;) {
+ fn(fd, f0);
+ neon_store_reg32(fd, vd);
+
+ if (veclen == 0) {
+ break;
+ }
+
+ if (delta_m == 0) {
+ /* single source one-many */
+ while (veclen--) {
+ vd = vfp_advance_sreg(vd, delta_d);
+ neon_store_reg32(fd, vd);
+ }
+ break;
+ }
+
+ /* Set up the operands for the next iteration */
+ veclen--;
+ vd = vfp_advance_sreg(vd, delta_d);
+ vm = vfp_advance_sreg(vm, delta_m);
+ neon_load_reg32(f0, vm);
+ }
+
+ tcg_temp_free_i32(f0);
+ tcg_temp_free_i32(fd);
+
+ return true;
+}
+
+static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
+{
+ uint32_t delta_m = 0;
+ uint32_t delta_d = 0;
+ int veclen = s->vec_len;
+ TCGv_i64 f0, fd;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (veclen > 0) {
+ /* Figure out what type of vector operation this is. */
+ if (vfp_dreg_is_scalar(vd)) {
+ /* scalar */
+ veclen = 0;
+ } else {
+ delta_d = (s->vec_stride >> 1) + 1;
+
+ if (vfp_dreg_is_scalar(vm)) {
+ /* mixed scalar/vector */
+ delta_m = 0;
+ } else {
+ /* vector */
+ delta_m = delta_d;
+ }
+ }
+ }
+
+ f0 = tcg_temp_new_i64();
+ fd = tcg_temp_new_i64();
+
+ neon_load_reg64(f0, vm);
+
+ for (;;) {
+ fn(fd, f0);
+ neon_store_reg64(fd, vd);
+
+ if (veclen == 0) {
+ break;
+ }
+
+ if (delta_m == 0) {
+ /* single source one-many */
+ while (veclen--) {
+ vd = vfp_advance_dreg(vd, delta_d);
+ neon_store_reg64(fd, vd);
+ }
+ break;
+ }
+
+ /* Set up the operands for the next iteration */
+ veclen--;
+ vd = vfp_advance_dreg(vd, delta_d);
+ vd = vfp_advance_dreg(vm, delta_m);
+ neon_load_reg64(f0, vm);
+ }
+
+ tcg_temp_free_i64(f0);
+ tcg_temp_free_i64(fd);
+
+ return true;
+}
+
+static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
+{
+ /* Note that order of inputs to the add matters for NaNs */
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ gen_helper_vfp_muls(tmp, vn, vm, fpst);
+ gen_helper_vfp_adds(vd, vd, tmp, fpst);
+ tcg_temp_free_i32(tmp);
+}
+
+static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
+{
+ /* Note that order of inputs to the add matters for NaNs */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ gen_helper_vfp_muld(tmp, vn, vm, fpst);
+ gen_helper_vfp_addd(vd, vd, tmp, fpst);
+ tcg_temp_free_i64(tmp);
+}
+
+static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
+{
+ /*
+ * VMLS: vd = vd + -(vn * vm)
+ * Note that order of inputs to the add matters for NaNs.
+ */
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ gen_helper_vfp_muls(tmp, vn, vm, fpst);
+ gen_helper_vfp_negs(tmp, tmp);
+ gen_helper_vfp_adds(vd, vd, tmp, fpst);
+ tcg_temp_free_i32(tmp);
+}
+
+static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
+{
+ /*
+ * VMLS: vd = vd + -(vn * vm)
+ * Note that order of inputs to the add matters for NaNs.
+ */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ gen_helper_vfp_muld(tmp, vn, vm, fpst);
+ gen_helper_vfp_negd(tmp, tmp);
+ gen_helper_vfp_addd(vd, vd, tmp, fpst);
+ tcg_temp_free_i64(tmp);
+}
+
+static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
+{
+ /*
+ * VNMLS: -fd + (fn * fm)
+ * Note that it isn't valid to replace (-A + B) with (B - A) or similar
+ * plausible looking simplifications because this will give wrong results
+ * for NaNs.
+ */
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ gen_helper_vfp_muls(tmp, vn, vm, fpst);
+ gen_helper_vfp_negs(vd, vd);
+ gen_helper_vfp_adds(vd, vd, tmp, fpst);
+ tcg_temp_free_i32(tmp);
+}
+
+static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
+{
+ /*
+ * VNMLS: -fd + (fn * fm)
+ * Note that it isn't valid to replace (-A + B) with (B - A) or similar
+ * plausible looking simplifications because this will give wrong results
+ * for NaNs.
+ */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ gen_helper_vfp_muld(tmp, vn, vm, fpst);
+ gen_helper_vfp_negd(vd, vd);
+ gen_helper_vfp_addd(vd, vd, tmp, fpst);
+ tcg_temp_free_i64(tmp);
+}
+
+static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
+{
+ /* VNMLA: -fd + -(fn * fm) */
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ gen_helper_vfp_muls(tmp, vn, vm, fpst);
+ gen_helper_vfp_negs(tmp, tmp);
+ gen_helper_vfp_negs(vd, vd);
+ gen_helper_vfp_adds(vd, vd, tmp, fpst);
+ tcg_temp_free_i32(tmp);
+}
+
+static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true);
+}
+
+static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
+{
+ /* VNMLA: -fd + (fn * fm) */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ gen_helper_vfp_muld(tmp, vn, vm, fpst);
+ gen_helper_vfp_negd(tmp, tmp);
+ gen_helper_vfp_negd(vd, vd);
+ gen_helper_vfp_addd(vd, vd, tmp, fpst);
+ tcg_temp_free_i64(tmp);
+}
+
+static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
+}
+
+static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false);
+}
+
+static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
+{
+ /* VNMUL: -(fn * fm) */
+ gen_helper_vfp_muls(vd, vn, vm, fpst);
+ gen_helper_vfp_negs(vd, vd);
+}
+
+static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false);
+}
+
+static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
+{
+ /* VNMUL: -(fn * fm) */
+ gen_helper_vfp_muld(vd, vn, vm, fpst);
+ gen_helper_vfp_negd(vd, vd);
+}
+
+static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a)
+{
+ return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
+{
+ return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
+{
+ /*
+ * VFNMA : fd = muladd(-fd, fn, fm)
+ * VFNMS : fd = muladd(-fd, -fn, fm)
+ * VFMA : fd = muladd( fd, fn, fm)
+ * VFMS : fd = muladd( fd, -fn, fm)
+ *
+ * These are fused multiply-add, and must be done as one floating
+ * point operation with no rounding between the multiplication and
+ * addition steps. NB that doing the negations here as separate
+ * steps is correct : an input NaN should come out with its sign
+ * bit flipped if it is a negated-input.
+ */
+ TCGv_ptr fpst;
+ TCGv_i32 vn, vm, vd;
+
+ /*
+ * Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+ /*
+ * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
+ * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
+ */
+ if (s->vec_len != 0 || s->vec_stride != 0) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vn = tcg_temp_new_i32();
+ vm = tcg_temp_new_i32();
+ vd = tcg_temp_new_i32();
+
+ neon_load_reg32(vn, a->vn);
+ neon_load_reg32(vm, a->vm);
+ if (neg_n) {
+ /* VFNMS, VFMS */
+ gen_helper_vfp_negs(vn, vn);
+ }
+ neon_load_reg32(vd, a->vd);
+ if (neg_d) {
+ /* VFNMA, VFNMS */
+ gen_helper_vfp_negs(vd, vd);
+ }
+ fpst = get_fpstatus_ptr(0);
+ gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
+ neon_store_reg32(vd, a->vd);
+
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(vn);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_i32(vd);
+
+ return true;
+}
+
+static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a)
+{
+ return do_vfm_sp(s, a, false, false);
+}
+
+static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a)
+{
+ return do_vfm_sp(s, a, true, false);
+}
+
+static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a)
+{
+ return do_vfm_sp(s, a, false, true);
+}
+
+static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a)
+{
+ return do_vfm_sp(s, a, true, true);
+}
+
+static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
+{
+ /*
+ * VFNMA : fd = muladd(-fd, fn, fm)
+ * VFNMS : fd = muladd(-fd, -fn, fm)
+ * VFMA : fd = muladd( fd, fn, fm)
+ * VFMS : fd = muladd( fd, -fn, fm)
+ *
+ * These are fused multiply-add, and must be done as one floating
+ * point operation with no rounding between the multiplication and
+ * addition steps. NB that doing the negations here as separate
+ * steps is correct : an input NaN should come out with its sign
+ * bit flipped if it is a negated-input.
+ */
+ TCGv_ptr fpst;
+ TCGv_i64 vn, vm, vd;
+
+ /*
+ * Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+ /*
+ * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
+ * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
+ */
+ if (s->vec_len != 0 || s->vec_stride != 0) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vn = tcg_temp_new_i64();
+ vm = tcg_temp_new_i64();
+ vd = tcg_temp_new_i64();
+
+ neon_load_reg64(vn, a->vn);
+ neon_load_reg64(vm, a->vm);
+ if (neg_n) {
+ /* VFNMS, VFMS */
+ gen_helper_vfp_negd(vn, vn);
+ }
+ neon_load_reg64(vd, a->vd);
+ if (neg_d) {
+ /* VFNMA, VFNMS */
+ gen_helper_vfp_negd(vd, vd);
+ }
+ fpst = get_fpstatus_ptr(0);
+ gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
+ neon_store_reg64(vd, a->vd);
+
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i64(vn);
+ tcg_temp_free_i64(vm);
+ tcg_temp_free_i64(vd);
+
+ return true;
+}
+
+static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a)
+{
+ return do_vfm_dp(s, a, false, false);
+}
+
+static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a)
+{
+ return do_vfm_dp(s, a, true, false);
+}
+
+static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a)
+{
+ return do_vfm_dp(s, a, false, true);
+}
+
+static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a)
+{
+ return do_vfm_dp(s, a, true, true);
+}
+
+static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
+{
+ uint32_t delta_d = 0;
+ int veclen = s->vec_len;
+ TCGv_i32 fd;
+ uint32_t vd;
+
+ vd = a->vd;
+
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (veclen > 0) {
+ /* Figure out what type of vector operation this is. */
+ if (vfp_sreg_is_scalar(vd)) {
+ /* scalar */
+ veclen = 0;
+ } else {
+ delta_d = s->vec_stride + 1;
+ }
+ }
+
+ fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
+
+ for (;;) {
+ neon_store_reg32(fd, vd);
+
+ if (veclen == 0) {
+ break;
+ }
+
+ /* Set up the operands for the next iteration */
+ veclen--;
+ vd = vfp_advance_sreg(vd, delta_d);
+ }
+
+ tcg_temp_free_i32(fd);
+ return true;
+}
+
+static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
+{
+ uint32_t delta_d = 0;
+ int veclen = s->vec_len;
+ TCGv_i64 fd;
+ uint32_t vd;
+
+ vd = a->vd;
+
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ if (veclen > 0) {
+ /* Figure out what type of vector operation this is. */
+ if (vfp_dreg_is_scalar(vd)) {
+ /* scalar */
+ veclen = 0;
+ } else {
+ delta_d = (s->vec_stride >> 1) + 1;
+ }
+ }
+
+ fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
+
+ for (;;) {
+ neon_store_reg64(fd, vd);
+
+ if (veclen == 0) {
+ break;
+ }
+
+ /* Set up the operands for the next iteration */
+ veclen--;
+ vd = vfp_advance_dreg(vd, delta_d);
+ }
+
+ tcg_temp_free_i64(fd);
+ return true;
+}
+
+static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a)
+{
+ return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm);
+}
+
+static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a)
+{
+ return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm);
+}
+
+static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
+{
+ return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
+}
+
+static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a)
+{
+ return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
+}
+
+static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a)
+{
+ return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm);
+}
+
+static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
+{
+ return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
+}
+
+static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
+{
+ gen_helper_vfp_sqrts(vd, vm, cpu_env);
+}
+
+static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a)
+{
+ return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm);
+}
+
+static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
+{
+ gen_helper_vfp_sqrtd(vd, vm, cpu_env);
+}
+
+static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a)
+{
+ return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm);
+}
+
+static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
+{
+ TCGv_i32 vd, vm;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ /* Vm/M bits must be zero for the Z variant */
+ if (a->z && a->vm != 0) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vd = tcg_temp_new_i32();
+ vm = tcg_temp_new_i32();
+
+ neon_load_reg32(vd, a->vd);
+ if (a->z) {
+ tcg_gen_movi_i32(vm, 0);
+ } else {
+ neon_load_reg32(vm, a->vm);
+ }
+
+ if (a->e) {
+ gen_helper_vfp_cmpes(vd, vm, cpu_env);
+ } else {
+ gen_helper_vfp_cmps(vd, vm, cpu_env);
+ }
+
+ tcg_temp_free_i32(vd);
+ tcg_temp_free_i32(vm);
+
+ return true;
+}
+
+static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
+{
+ TCGv_i64 vd, vm;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* Vm/M bits must be zero for the Z variant */
+ if (a->z && a->vm != 0) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vd = tcg_temp_new_i64();
+ vm = tcg_temp_new_i64();
+
+ neon_load_reg64(vd, a->vd);
+ if (a->z) {
+ tcg_gen_movi_i64(vm, 0);
+ } else {
+ neon_load_reg64(vm, a->vm);
+ }
+
+ if (a->e) {
+ gen_helper_vfp_cmped(vd, vm, cpu_env);
+ } else {
+ gen_helper_vfp_cmpd(vd, vm, cpu_env);
+ }
+
+ tcg_temp_free_i64(vd);
+ tcg_temp_free_i64(vm);
+
+ return true;
+}
+
+static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 ahp_mode;
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_fp16_spconv, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(false);
+ ahp_mode = get_ahp_flag();
+ tmp = tcg_temp_new_i32();
+ /* The T bit tells us if we want the low or high 16 bits of Vm */
+ tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
+ gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
+ neon_store_reg32(tmp, a->vd);
+ tcg_temp_free_i32(ahp_mode);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 ahp_mode;
+ TCGv_i32 tmp;
+ TCGv_i64 vd;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(false);
+ ahp_mode = get_ahp_flag();
+ tmp = tcg_temp_new_i32();
+ /* The T bit tells us if we want the low or high 16 bits of Vm */
+ tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
+ vd = tcg_temp_new_i64();
+ gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
+ neon_store_reg64(vd, a->vd);
+ tcg_temp_free_i32(ahp_mode);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i64(vd);
+ return true;
+}
+
+static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 ahp_mode;
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_fp16_spconv, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(false);
+ ahp_mode = get_ahp_flag();
+ tmp = tcg_temp_new_i32();
+
+ neon_load_reg32(tmp, a->vm);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
+ tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
+ tcg_temp_free_i32(ahp_mode);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 ahp_mode;
+ TCGv_i32 tmp;
+ TCGv_i64 vm;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(false);
+ ahp_mode = get_ahp_flag();
+ tmp = tcg_temp_new_i32();
+ vm = tcg_temp_new_i64();
+
+ neon_load_reg64(vm, a->vm);
+ gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
+ tcg_temp_free_i64(vm);
+ tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
+ tcg_temp_free_i32(ahp_mode);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ gen_helper_rints(tmp, tmp, fpst);
+ neon_store_reg32(tmp, a->vd);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i64 tmp;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i64();
+ neon_load_reg64(tmp, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ gen_helper_rintd(tmp, tmp, fpst);
+ neon_store_reg64(tmp, a->vd);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i64(tmp);
+ return true;
+}
+
+static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 tmp;
+ TCGv_i32 tcg_rmode;
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ tcg_rmode = tcg_const_i32(float_round_to_zero);
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_helper_rints(tmp, tmp, fpst);
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ neon_store_reg32(tmp, a->vd);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tcg_rmode);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i64 tmp;
+ TCGv_i32 tcg_rmode;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i64();
+ neon_load_reg64(tmp, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ tcg_rmode = tcg_const_i32(float_round_to_zero);
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_helper_rintd(tmp, tmp, fpst);
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ neon_store_reg64(tmp, a->vd);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i32(tcg_rmode);
+ return true;
+}
+
+static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i32 tmp;
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i32();
+ neon_load_reg32(tmp, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ gen_helper_rints_exact(tmp, tmp, fpst);
+ neon_store_reg32(tmp, a->vd);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tmp);
+ return true;
+}
+
+static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
+{
+ TCGv_ptr fpst;
+ TCGv_i64 tmp;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_vrint, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i64();
+ neon_load_reg64(tmp, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ gen_helper_rintd_exact(tmp, tmp, fpst);
+ neon_store_reg64(tmp, a->vd);
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i64(tmp);
+ return true;
+}
+
+static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
+{
+ TCGv_i64 vd;
+ TCGv_i32 vm;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i32();
+ vd = tcg_temp_new_i64();
+ neon_load_reg32(vm, a->vm);
+ gen_helper_vfp_fcvtds(vd, vm, cpu_env);
+ neon_store_reg64(vd, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_i64(vd);
+ return true;
+}
+
+static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
+{
+ TCGv_i64 vm;
+ TCGv_i32 vd;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vd = tcg_temp_new_i32();
+ vm = tcg_temp_new_i64();
+ neon_load_reg64(vm, a->vm);
+ gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
+ neon_store_reg32(vd, a->vd);
+ tcg_temp_free_i32(vd);
+ tcg_temp_free_i64(vm);
+ return true;
+}
+
+static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
+{
+ TCGv_i32 vm;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i32();
+ neon_load_reg32(vm, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ if (a->s) {
+ /* i32 -> f32 */
+ gen_helper_vfp_sitos(vm, vm, fpst);
+ } else {
+ /* u32 -> f32 */
+ gen_helper_vfp_uitos(vm, vm, fpst);
+ }
+ neon_store_reg32(vm, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
+{
+ TCGv_i32 vm;
+ TCGv_i64 vd;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i32();
+ vd = tcg_temp_new_i64();
+ neon_load_reg32(vm, a->vm);
+ fpst = get_fpstatus_ptr(false);
+ if (a->s) {
+ /* i32 -> f64 */
+ gen_helper_vfp_sitod(vd, vm, fpst);
+ } else {
+ /* u32 -> f64 */
+ gen_helper_vfp_uitod(vd, vm, fpst);
+ }
+ neon_store_reg64(vd, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_i64(vd);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
+{
+ TCGv_i32 vd;
+ TCGv_i64 vm;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ if (!dc_isar_feature(aa32_jscvt, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ vm = tcg_temp_new_i64();
+ vd = tcg_temp_new_i32();
+ neon_load_reg64(vm, a->vm);
+ gen_helper_vjcvt(vd, vm, cpu_env);
+ neon_store_reg32(vd, a->vd);
+ tcg_temp_free_i64(vm);
+ tcg_temp_free_i32(vd);
+ return true;
+}
+
+static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
+{
+ TCGv_i32 vd, shift;
+ TCGv_ptr fpst;
+ int frac_bits;
+
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
+
+ vd = tcg_temp_new_i32();
+ neon_load_reg32(vd, a->vd);
+
+ fpst = get_fpstatus_ptr(false);
+ shift = tcg_const_i32(frac_bits);
+
+ /* Switch on op:U:sx bits */
+ switch (a->opc) {
+ case 0:
+ gen_helper_vfp_shtos(vd, vd, shift, fpst);
+ break;
+ case 1:
+ gen_helper_vfp_sltos(vd, vd, shift, fpst);
+ break;
+ case 2:
+ gen_helper_vfp_uhtos(vd, vd, shift, fpst);
+ break;
+ case 3:
+ gen_helper_vfp_ultos(vd, vd, shift, fpst);
+ break;
+ case 4:
+ gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst);
+ break;
+ case 5:
+ gen_helper_vfp_tosls_round_to_zero(vd, vd, shift, fpst);
+ break;
+ case 6:
+ gen_helper_vfp_touhs_round_to_zero(vd, vd, shift, fpst);
+ break;
+ case 7:
+ gen_helper_vfp_touls_round_to_zero(vd, vd, shift, fpst);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ neon_store_reg32(vd, a->vd);
+ tcg_temp_free_i32(vd);
+ tcg_temp_free_i32(shift);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
+{
+ TCGv_i64 vd;
+ TCGv_i32 shift;
+ TCGv_ptr fpst;
+ int frac_bits;
+
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
+
+ vd = tcg_temp_new_i64();
+ neon_load_reg64(vd, a->vd);
+
+ fpst = get_fpstatus_ptr(false);
+ shift = tcg_const_i32(frac_bits);
+
+ /* Switch on op:U:sx bits */
+ switch (a->opc) {
+ case 0:
+ gen_helper_vfp_shtod(vd, vd, shift, fpst);
+ break;
+ case 1:
+ gen_helper_vfp_sltod(vd, vd, shift, fpst);
+ break;
+ case 2:
+ gen_helper_vfp_uhtod(vd, vd, shift, fpst);
+ break;
+ case 3:
+ gen_helper_vfp_ultod(vd, vd, shift, fpst);
+ break;
+ case 4:
+ gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst);
+ break;
+ case 5:
+ gen_helper_vfp_tosld_round_to_zero(vd, vd, shift, fpst);
+ break;
+ case 6:
+ gen_helper_vfp_touhd_round_to_zero(vd, vd, shift, fpst);
+ break;
+ case 7:
+ gen_helper_vfp_tould_round_to_zero(vd, vd, shift, fpst);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ neon_store_reg64(vd, a->vd);
+ tcg_temp_free_i64(vd);
+ tcg_temp_free_i32(shift);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
+{
+ TCGv_i32 vm;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(false);
+ vm = tcg_temp_new_i32();
+ neon_load_reg32(vm, a->vm);
+
+ if (a->s) {
+ if (a->rz) {
+ gen_helper_vfp_tosizs(vm, vm, fpst);
+ } else {
+ gen_helper_vfp_tosis(vm, vm, fpst);
+ }
+ } else {
+ if (a->rz) {
+ gen_helper_vfp_touizs(vm, vm, fpst);
+ } else {
+ gen_helper_vfp_touis(vm, vm, fpst);
+ }
+ }
+ neon_store_reg32(vm, a->vd);
+ tcg_temp_free_i32(vm);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
+{
+ TCGv_i32 vd;
+ TCGv_i64 vm;
+ TCGv_ptr fpst;
+
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ fpst = get_fpstatus_ptr(false);
+ vm = tcg_temp_new_i64();
+ vd = tcg_temp_new_i32();
+ neon_load_reg64(vm, a->vm);
+
+ if (a->s) {
+ if (a->rz) {
+ gen_helper_vfp_tosizd(vd, vm, fpst);
+ } else {
+ gen_helper_vfp_tosid(vd, vm, fpst);
+ }
+ } else {
+ if (a->rz) {
+ gen_helper_vfp_touizd(vd, vm, fpst);
+ } else {
+ gen_helper_vfp_touid(vd, vm, fpst);
+ }
+ }
+ neon_store_reg32(vd, a->vd);
+ tcg_temp_free_i32(vd);
+ tcg_temp_free_i64(vm);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+/*
+ * Decode VLLDM and VLSTM are nonstandard because:
+ * * if there is no FPU then these insns must NOP in
+ * Secure state and UNDEF in Nonsecure state
+ * * if there is an FPU then these insns do not have
+ * the usual behaviour that vfp_access_check() provides of
+ * being controlled by CPACR/NSACR enable bits or the
+ * lazy-stacking logic.
+ */
+static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
+{
+ TCGv_i32 fptr;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ /* If not secure, UNDEF. */
+ if (!s->v8m_secure) {
+ return false;
+ }
+ /* If no fpu, NOP. */
+ if (!dc_isar_feature(aa32_vfp, s)) {
+ return true;
+ }
+
+ fptr = load_reg(s, a->rn);
+ if (a->l) {
+ gen_helper_v7m_vlldm(cpu_env, fptr);
+ } else {
+ gen_helper_v7m_vlstm(cpu_env, fptr);
+ }
+ tcg_temp_free_i32(fptr);
+
+ /* End the TB, because we have updated FP control bits */
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
+ return true;
+}
+++ /dev/null
-/*
- * ARM translation: AArch32 VFP instructions
- *
- * Copyright (c) 2003 Fabrice Bellard
- * Copyright (c) 2005-2007 CodeSourcery
- * Copyright (c) 2007 OpenedHand, Ltd.
- * Copyright (c) 2019 Linaro, Ltd.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * This file is intended to be included from translate.c; it uses
- * some macros and definitions provided by that file.
- * It might be possible to convert it to a standalone .c file eventually.
- */
-
-/* Include the generated VFP decoder */
-#include "decode-vfp.inc.c"
-#include "decode-vfp-uncond.inc.c"
-
-/*
- * The imm8 encodes the sign bit, enough bits to represent an exponent in
- * the range 01....1xx to 10....0xx, and the most significant 4 bits of
- * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
- */
-uint64_t vfp_expand_imm(int size, uint8_t imm8)
-{
- uint64_t imm;
-
- switch (size) {
- case MO_64:
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
- (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
- extract32(imm8, 0, 6);
- imm <<= 48;
- break;
- case MO_32:
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
- (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
- (extract32(imm8, 0, 6) << 3);
- imm <<= 16;
- break;
- case MO_16:
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
- (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
- (extract32(imm8, 0, 6) << 6);
- break;
- default:
- g_assert_not_reached();
- }
- return imm;
-}
-
-/*
- * Return the offset of a 16-bit half of the specified VFP single-precision
- * register. If top is true, returns the top 16 bits; otherwise the bottom
- * 16 bits.
- */
-static inline long vfp_f16_offset(unsigned reg, bool top)
-{
- long offs = vfp_reg_offset(false, reg);
-#ifdef HOST_WORDS_BIGENDIAN
- if (!top) {
- offs += 2;
- }
-#else
- if (top) {
- offs += 2;
- }
-#endif
- return offs;
-}
-
-/*
- * Check that VFP access is enabled. If it is, do the necessary
- * M-profile lazy-FP handling and then return true.
- * If not, emit code to generate an appropriate exception and
- * return false.
- * The ignore_vfp_enabled argument specifies that we should ignore
- * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
- * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
- */
-static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
-{
- if (s->fp_excp_el) {
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
- s->fp_excp_el);
- } else {
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_fp_access_trap(1, 0xe, false),
- s->fp_excp_el);
- }
- return false;
- }
-
- if (!s->vfp_enabled && !ignore_vfp_enabled) {
- assert(!arm_dc_feature(s, ARM_FEATURE_M));
- unallocated_encoding(s);
- return false;
- }
-
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- /* Handle M-profile lazy FP state mechanics */
-
- /* Trigger lazy-state preservation if necessary */
- if (s->v7m_lspact) {
- /*
- * Lazy state saving affects external memory and also the NVIC,
- * so we must mark it as an IO operation for icount (and cause
- * this to be the last insn in the TB).
- */
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
- s->base.is_jmp = DISAS_UPDATE_EXIT;
- gen_io_start();
- }
- gen_helper_v7m_preserve_fp_state(cpu_env);
- /*
- * If the preserve_fp_state helper doesn't throw an exception
- * then it will clear LSPACT; we don't need to repeat this for
- * any further FP insns in this TB.
- */
- s->v7m_lspact = false;
- }
-
- /* Update ownership of FP context: set FPCCR.S to match current state */
- if (s->v8m_fpccr_s_wrong) {
- TCGv_i32 tmp;
-
- tmp = load_cpu_field(v7m.fpccr[M_REG_S]);
- if (s->v8m_secure) {
- tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK);
- } else {
- tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK);
- }
- store_cpu_field(tmp, v7m.fpccr[M_REG_S]);
- /* Don't need to do this for any further FP insns in this TB */
- s->v8m_fpccr_s_wrong = false;
- }
-
- if (s->v7m_new_fp_ctxt_needed) {
- /*
- * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
- * and the FPSCR.
- */
- TCGv_i32 control, fpscr;
- uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
-
- fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
- gen_helper_vfp_set_fpscr(cpu_env, fpscr);
- tcg_temp_free_i32(fpscr);
- /*
- * We don't need to arrange to end the TB, because the only
- * parts of FPSCR which we cache in the TB flags are the VECLEN
- * and VECSTRIDE, and those don't exist for M-profile.
- */
-
- if (s->v8m_secure) {
- bits |= R_V7M_CONTROL_SFPA_MASK;
- }
- control = load_cpu_field(v7m.control[M_REG_S]);
- tcg_gen_ori_i32(control, control, bits);
- store_cpu_field(control, v7m.control[M_REG_S]);
- /* Don't need to do this for any further FP insns in this TB */
- s->v7m_new_fp_ctxt_needed = false;
- }
- }
-
- return true;
-}
-
-/*
- * The most usual kind of VFP access check, for everything except
- * FMXR/FMRX to the always-available special registers.
- */
-static bool vfp_access_check(DisasContext *s)
-{
- return full_vfp_access_check(s, false);
-}
-
-static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
-{
- uint32_t rd, rn, rm;
- bool dp = a->dp;
-
- if (!dc_isar_feature(aa32_vsel, s)) {
- return false;
- }
-
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
- return false;
- }
-
- rd = a->vd;
- rn = a->vn;
- rm = a->vm;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (dp) {
- TCGv_i64 frn, frm, dest;
- TCGv_i64 tmp, zero, zf, nf, vf;
-
- zero = tcg_const_i64(0);
-
- frn = tcg_temp_new_i64();
- frm = tcg_temp_new_i64();
- dest = tcg_temp_new_i64();
-
- zf = tcg_temp_new_i64();
- nf = tcg_temp_new_i64();
- vf = tcg_temp_new_i64();
-
- tcg_gen_extu_i32_i64(zf, cpu_ZF);
- tcg_gen_ext_i32_i64(nf, cpu_NF);
- tcg_gen_ext_i32_i64(vf, cpu_VF);
-
- neon_load_reg64(frn, rn);
- neon_load_reg64(frm, rm);
- switch (a->cc) {
- case 0: /* eq: Z */
- tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
- frn, frm);
- break;
- case 1: /* vs: V */
- tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero,
- frn, frm);
- break;
- case 2: /* ge: N == V -> N ^ V == 0 */
- tmp = tcg_temp_new_i64();
- tcg_gen_xor_i64(tmp, vf, nf);
- tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
- frn, frm);
- tcg_temp_free_i64(tmp);
- break;
- case 3: /* gt: !Z && N == V */
- tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero,
- frn, frm);
- tmp = tcg_temp_new_i64();
- tcg_gen_xor_i64(tmp, vf, nf);
- tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
- dest, frm);
- tcg_temp_free_i64(tmp);
- break;
- }
- neon_store_reg64(dest, rd);
- tcg_temp_free_i64(frn);
- tcg_temp_free_i64(frm);
- tcg_temp_free_i64(dest);
-
- tcg_temp_free_i64(zf);
- tcg_temp_free_i64(nf);
- tcg_temp_free_i64(vf);
-
- tcg_temp_free_i64(zero);
- } else {
- TCGv_i32 frn, frm, dest;
- TCGv_i32 tmp, zero;
-
- zero = tcg_const_i32(0);
-
- frn = tcg_temp_new_i32();
- frm = tcg_temp_new_i32();
- dest = tcg_temp_new_i32();
- neon_load_reg32(frn, rn);
- neon_load_reg32(frm, rm);
- switch (a->cc) {
- case 0: /* eq: Z */
- tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
- frn, frm);
- break;
- case 1: /* vs: V */
- tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero,
- frn, frm);
- break;
- case 2: /* ge: N == V -> N ^ V == 0 */
- tmp = tcg_temp_new_i32();
- tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
- tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
- frn, frm);
- tcg_temp_free_i32(tmp);
- break;
- case 3: /* gt: !Z && N == V */
- tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero,
- frn, frm);
- tmp = tcg_temp_new_i32();
- tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
- tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
- dest, frm);
- tcg_temp_free_i32(tmp);
- break;
- }
- neon_store_reg32(dest, rd);
- tcg_temp_free_i32(frn);
- tcg_temp_free_i32(frm);
- tcg_temp_free_i32(dest);
-
- tcg_temp_free_i32(zero);
- }
-
- return true;
-}
-
-/*
- * Table for converting the most common AArch32 encoding of
- * rounding mode to arm_fprounding order (which matches the
- * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
- */
-static const uint8_t fp_decode_rm[] = {
- FPROUNDING_TIEAWAY,
- FPROUNDING_TIEEVEN,
- FPROUNDING_POSINF,
- FPROUNDING_NEGINF,
-};
-
-static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
-{
- uint32_t rd, rm;
- bool dp = a->dp;
- TCGv_ptr fpst;
- TCGv_i32 tcg_rmode;
- int rounding = fp_decode_rm[a->rm];
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vd) & 0x10)) {
- return false;
- }
-
- rd = a->vd;
- rm = a->vm;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(0);
-
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-
- if (dp) {
- TCGv_i64 tcg_op;
- TCGv_i64 tcg_res;
- tcg_op = tcg_temp_new_i64();
- tcg_res = tcg_temp_new_i64();
- neon_load_reg64(tcg_op, rm);
- gen_helper_rintd(tcg_res, tcg_op, fpst);
- neon_store_reg64(tcg_res, rd);
- tcg_temp_free_i64(tcg_op);
- tcg_temp_free_i64(tcg_res);
- } else {
- TCGv_i32 tcg_op;
- TCGv_i32 tcg_res;
- tcg_op = tcg_temp_new_i32();
- tcg_res = tcg_temp_new_i32();
- neon_load_reg32(tcg_op, rm);
- gen_helper_rints(tcg_res, tcg_op, fpst);
- neon_store_reg32(tcg_res, rd);
- tcg_temp_free_i32(tcg_op);
- tcg_temp_free_i32(tcg_res);
- }
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
- tcg_temp_free_i32(tcg_rmode);
-
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
-{
- uint32_t rd, rm;
- bool dp = a->dp;
- TCGv_ptr fpst;
- TCGv_i32 tcg_rmode, tcg_shift;
- int rounding = fp_decode_rm[a->rm];
- bool is_signed = a->op;
-
- if (!dc_isar_feature(aa32_vcvt_dr, s)) {
- return false;
- }
-
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
- return false;
- }
-
- rd = a->vd;
- rm = a->vm;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(0);
-
- tcg_shift = tcg_const_i32(0);
-
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-
- if (dp) {
- TCGv_i64 tcg_double, tcg_res;
- TCGv_i32 tcg_tmp;
- tcg_double = tcg_temp_new_i64();
- tcg_res = tcg_temp_new_i64();
- tcg_tmp = tcg_temp_new_i32();
- neon_load_reg64(tcg_double, rm);
- if (is_signed) {
- gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
- } else {
- gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
- }
- tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
- neon_store_reg32(tcg_tmp, rd);
- tcg_temp_free_i32(tcg_tmp);
- tcg_temp_free_i64(tcg_res);
- tcg_temp_free_i64(tcg_double);
- } else {
- TCGv_i32 tcg_single, tcg_res;
- tcg_single = tcg_temp_new_i32();
- tcg_res = tcg_temp_new_i32();
- neon_load_reg32(tcg_single, rm);
- if (is_signed) {
- gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
- } else {
- gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
- }
- neon_store_reg32(tcg_res, rd);
- tcg_temp_free_i32(tcg_res);
- tcg_temp_free_i32(tcg_single);
- }
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
- tcg_temp_free_i32(tcg_rmode);
-
- tcg_temp_free_i32(tcg_shift);
-
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
-{
- /* VMOV scalar to general purpose register */
- TCGv_i32 tmp;
- int pass;
- uint32_t offset;
-
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
- if (a->size == 2
- ? !dc_isar_feature(aa32_fpsp_v2, s)
- : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
- return false;
- }
-
- offset = a->index << a->size;
- pass = extract32(offset, 2, 1);
- offset = extract32(offset, 0, 2) * 8;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = neon_load_reg(a->vn, pass);
- switch (a->size) {
- case 0:
- if (offset) {
- tcg_gen_shri_i32(tmp, tmp, offset);
- }
- if (a->u) {
- gen_uxtb(tmp);
- } else {
- gen_sxtb(tmp);
- }
- break;
- case 1:
- if (a->u) {
- if (offset) {
- tcg_gen_shri_i32(tmp, tmp, 16);
- } else {
- gen_uxth(tmp);
- }
- } else {
- if (offset) {
- tcg_gen_sari_i32(tmp, tmp, 16);
- } else {
- gen_sxth(tmp);
- }
- }
- break;
- case 2:
- break;
- }
- store_reg(s, a->rt, tmp);
-
- return true;
-}
-
-static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
-{
- /* VMOV general purpose register to scalar */
- TCGv_i32 tmp, tmp2;
- int pass;
- uint32_t offset;
-
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
- if (a->size == 2
- ? !dc_isar_feature(aa32_fpsp_v2, s)
- : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
- return false;
- }
-
- offset = a->index << a->size;
- pass = extract32(offset, 2, 1);
- offset = extract32(offset, 0, 2) * 8;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = load_reg(s, a->rt);
- switch (a->size) {
- case 0:
- tmp2 = neon_load_reg(a->vn, pass);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
- tcg_temp_free_i32(tmp2);
- break;
- case 1:
- tmp2 = neon_load_reg(a->vn, pass);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
- tcg_temp_free_i32(tmp2);
- break;
- case 2:
- break;
- }
- neon_store_reg(a->vn, pass, tmp);
-
- return true;
-}
-
-static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
-{
- /* VDUP (general purpose register) */
- TCGv_i32 tmp;
- int size, vec_size;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
- return false;
- }
-
- if (a->b && a->e) {
- return false;
- }
-
- if (a->q && (a->vn & 1)) {
- return false;
- }
-
- vec_size = a->q ? 16 : 8;
- if (a->b) {
- size = 0;
- } else if (a->e) {
- size = 1;
- } else {
- size = 2;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = load_reg(s, a->rt);
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
- vec_size, vec_size, tmp);
- tcg_temp_free_i32(tmp);
-
- return true;
-}
-
-static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
-{
- TCGv_i32 tmp;
- bool ignore_vfp_enabled = false;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
- /*
- * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
- * Accesses to R15 are UNPREDICTABLE; we choose to undef.
- * (FPSCR -> r15 is a special case which writes to the PSR flags.)
- */
- if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
- return false;
- }
- }
-
- switch (a->reg) {
- case ARM_VFP_FPSID:
- /*
- * VFPv2 allows access to FPSID from userspace; VFPv3 restricts
- * all ID registers to privileged access only.
- */
- if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
- return false;
- }
- ignore_vfp_enabled = true;
- break;
- case ARM_VFP_MVFR0:
- case ARM_VFP_MVFR1:
- if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
- return false;
- }
- ignore_vfp_enabled = true;
- break;
- case ARM_VFP_MVFR2:
- if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
- ignore_vfp_enabled = true;
- break;
- case ARM_VFP_FPSCR:
- break;
- case ARM_VFP_FPEXC:
- if (IS_USER(s)) {
- return false;
- }
- ignore_vfp_enabled = true;
- break;
- case ARM_VFP_FPINST:
- case ARM_VFP_FPINST2:
- /* Not present in VFPv3 */
- if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
- return false;
- }
- break;
- default:
- return false;
- }
-
- if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
- return true;
- }
-
- if (a->l) {
- /* VMRS, move VFP special register to gp register */
- switch (a->reg) {
- case ARM_VFP_MVFR0:
- case ARM_VFP_MVFR1:
- case ARM_VFP_MVFR2:
- case ARM_VFP_FPSID:
- if (s->current_el == 1) {
- TCGv_i32 tcg_reg, tcg_rt;
-
- gen_set_condexec(s);
- gen_set_pc_im(s, s->pc_curr);
- tcg_reg = tcg_const_i32(a->reg);
- tcg_rt = tcg_const_i32(a->rt);
- gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg);
- tcg_temp_free_i32(tcg_reg);
- tcg_temp_free_i32(tcg_rt);
- }
- /* fall through */
- case ARM_VFP_FPEXC:
- case ARM_VFP_FPINST:
- case ARM_VFP_FPINST2:
- tmp = load_cpu_field(vfp.xregs[a->reg]);
- break;
- case ARM_VFP_FPSCR:
- if (a->rt == 15) {
- tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
- } else {
- tmp = tcg_temp_new_i32();
- gen_helper_vfp_get_fpscr(tmp, cpu_env);
- }
- break;
- default:
- g_assert_not_reached();
- }
-
- if (a->rt == 15) {
- /* Set the 4 flag bits in the CPSR. */
- gen_set_nzcv(tmp);
- tcg_temp_free_i32(tmp);
- } else {
- store_reg(s, a->rt, tmp);
- }
- } else {
- /* VMSR, move gp register to VFP special register */
- switch (a->reg) {
- case ARM_VFP_FPSID:
- case ARM_VFP_MVFR0:
- case ARM_VFP_MVFR1:
- case ARM_VFP_MVFR2:
- /* Writes are ignored. */
- break;
- case ARM_VFP_FPSCR:
- tmp = load_reg(s, a->rt);
- gen_helper_vfp_set_fpscr(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
- gen_lookup_tb(s);
- break;
- case ARM_VFP_FPEXC:
- /*
- * TODO: VFP subarchitecture support.
- * For now, keep the EN bit only
- */
- tmp = load_reg(s, a->rt);
- tcg_gen_andi_i32(tmp, tmp, 1 << 30);
- store_cpu_field(tmp, vfp.xregs[a->reg]);
- gen_lookup_tb(s);
- break;
- case ARM_VFP_FPINST:
- case ARM_VFP_FPINST2:
- tmp = load_reg(s, a->rt);
- store_cpu_field(tmp, vfp.xregs[a->reg]);
- break;
- default:
- g_assert_not_reached();
- }
- }
-
- return true;
-}
-
-static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
-{
- TCGv_i32 tmp;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (a->l) {
- /* VFP to general purpose register */
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vn);
- if (a->rt == 15) {
- /* Set the 4 flag bits in the CPSR. */
- gen_set_nzcv(tmp);
- tcg_temp_free_i32(tmp);
- } else {
- store_reg(s, a->rt, tmp);
- }
- } else {
- /* general purpose register to VFP */
- tmp = load_reg(s, a->rt);
- neon_store_reg32(tmp, a->vn);
- tcg_temp_free_i32(tmp);
- }
-
- return true;
-}
-
-static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
-{
- TCGv_i32 tmp;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- /*
- * VMOV between two general-purpose registers and two single precision
- * floating point registers
- */
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (a->op) {
- /* fpreg to gpreg */
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm);
- store_reg(s, a->rt, tmp);
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm + 1);
- store_reg(s, a->rt2, tmp);
- } else {
- /* gpreg to fpreg */
- tmp = load_reg(s, a->rt);
- neon_store_reg32(tmp, a->vm);
- tcg_temp_free_i32(tmp);
- tmp = load_reg(s, a->rt2);
- neon_store_reg32(tmp, a->vm + 1);
- tcg_temp_free_i32(tmp);
- }
-
- return true;
-}
-
-static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
-{
- TCGv_i32 tmp;
-
- /*
- * VMOV between two general-purpose registers and one double precision
- * floating point register. Note that this does not require support
- * for double precision arithmetic.
- */
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (a->op) {
- /* fpreg to gpreg */
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm * 2);
- store_reg(s, a->rt, tmp);
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm * 2 + 1);
- store_reg(s, a->rt2, tmp);
- } else {
- /* gpreg to fpreg */
- tmp = load_reg(s, a->rt);
- neon_store_reg32(tmp, a->vm * 2);
- tcg_temp_free_i32(tmp);
- tmp = load_reg(s, a->rt2);
- neon_store_reg32(tmp, a->vm * 2 + 1);
- tcg_temp_free_i32(tmp);
- }
-
- return true;
-}
-
-static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
-{
- uint32_t offset;
- TCGv_i32 addr, tmp;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- offset = a->imm << 2;
- if (!a->u) {
- offset = -offset;
- }
-
- /* For thumb, use of PC is UNPREDICTABLE. */
- addr = add_reg_for_lit(s, a->rn, offset);
- tmp = tcg_temp_new_i32();
- if (a->l) {
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- neon_store_reg32(tmp, a->vd);
- } else {
- neon_load_reg32(tmp, a->vd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- }
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(addr);
-
- return true;
-}
-
-static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
-{
- uint32_t offset;
- TCGv_i32 addr;
- TCGv_i64 tmp;
-
- /* Note that this does not require support for double arithmetic. */
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- offset = a->imm << 2;
- if (!a->u) {
- offset = -offset;
- }
-
- /* For thumb, use of PC is UNPREDICTABLE. */
- addr = add_reg_for_lit(s, a->rn, offset);
- tmp = tcg_temp_new_i64();
- if (a->l) {
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
- neon_store_reg64(tmp, a->vd);
- } else {
- neon_load_reg64(tmp, a->vd);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
- }
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i32(addr);
-
- return true;
-}
-
-static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
-{
- uint32_t offset;
- TCGv_i32 addr, tmp;
- int i, n;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- n = a->imm;
-
- if (n == 0 || (a->vd + n) > 32) {
- /*
- * UNPREDICTABLE cases for bad immediates: we choose to
- * UNDEF to avoid generating huge numbers of TCG ops
- */
- return false;
- }
- if (a->rn == 15 && a->w) {
- /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /* For thumb, use of PC is UNPREDICTABLE. */
- addr = add_reg_for_lit(s, a->rn, 0);
- if (a->p) {
- /* pre-decrement */
- tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
- }
-
- if (s->v8m_stackcheck && a->rn == 13 && a->w) {
- /*
- * Here 'addr' is the lowest address we will store to,
- * and is either the old SP (if post-increment) or
- * the new SP (if pre-decrement). For post-increment
- * where the old value is below the limit and the new
- * value is above, it is UNKNOWN whether the limit check
- * triggers; we choose to trigger.
- */
- gen_helper_v8m_stackcheck(cpu_env, addr);
- }
-
- offset = 4;
- tmp = tcg_temp_new_i32();
- for (i = 0; i < n; i++) {
- if (a->l) {
- /* load */
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- neon_store_reg32(tmp, a->vd + i);
- } else {
- /* store */
- neon_load_reg32(tmp, a->vd + i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- }
- tcg_gen_addi_i32(addr, addr, offset);
- }
- tcg_temp_free_i32(tmp);
- if (a->w) {
- /* writeback */
- if (a->p) {
- offset = -offset * n;
- tcg_gen_addi_i32(addr, addr, offset);
- }
- store_reg(s, a->rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
-
- return true;
-}
-
-static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
-{
- uint32_t offset;
- TCGv_i32 addr;
- TCGv_i64 tmp;
- int i, n;
-
- /* Note that this does not require support for double arithmetic. */
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- n = a->imm >> 1;
-
- if (n == 0 || (a->vd + n) > 32 || n > 16) {
- /*
- * UNPREDICTABLE cases for bad immediates: we choose to
- * UNDEF to avoid generating huge numbers of TCG ops
- */
- return false;
- }
- if (a->rn == 15 && a->w) {
- /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /* For thumb, use of PC is UNPREDICTABLE. */
- addr = add_reg_for_lit(s, a->rn, 0);
- if (a->p) {
- /* pre-decrement */
- tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
- }
-
- if (s->v8m_stackcheck && a->rn == 13 && a->w) {
- /*
- * Here 'addr' is the lowest address we will store to,
- * and is either the old SP (if post-increment) or
- * the new SP (if pre-decrement). For post-increment
- * where the old value is below the limit and the new
- * value is above, it is UNKNOWN whether the limit check
- * triggers; we choose to trigger.
- */
- gen_helper_v8m_stackcheck(cpu_env, addr);
- }
-
- offset = 8;
- tmp = tcg_temp_new_i64();
- for (i = 0; i < n; i++) {
- if (a->l) {
- /* load */
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
- neon_store_reg64(tmp, a->vd + i);
- } else {
- /* store */
- neon_load_reg64(tmp, a->vd + i);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
- }
- tcg_gen_addi_i32(addr, addr, offset);
- }
- tcg_temp_free_i64(tmp);
- if (a->w) {
- /* writeback */
- if (a->p) {
- offset = -offset * n;
- } else if (a->imm & 1) {
- offset = 4;
- } else {
- offset = 0;
- }
-
- if (offset != 0) {
- tcg_gen_addi_i32(addr, addr, offset);
- }
- store_reg(s, a->rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
-
- return true;
-}
-
-/*
- * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
- * The callback should emit code to write a value to vd. If
- * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
- * will contain the old value of the relevant VFP register;
- * otherwise it must be written to only.
- */
-typedef void VFPGen3OpSPFn(TCGv_i32 vd,
- TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst);
-typedef void VFPGen3OpDPFn(TCGv_i64 vd,
- TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst);
-
-/*
- * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
- * The callback should emit code to write a value to vd (which
- * should be written to only).
- */
-typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm);
-typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm);
-
-/*
- * Return true if the specified S reg is in a scalar bank
- * (ie if it is s0..s7)
- */
-static inline bool vfp_sreg_is_scalar(int reg)
-{
- return (reg & 0x18) == 0;
-}
-
-/*
- * Return true if the specified D reg is in a scalar bank
- * (ie if it is d0..d3 or d16..d19)
- */
-static inline bool vfp_dreg_is_scalar(int reg)
-{
- return (reg & 0xc) == 0;
-}
-
-/*
- * Advance the S reg number forwards by delta within its bank
- * (ie increment the low 3 bits but leave the rest the same)
- */
-static inline int vfp_advance_sreg(int reg, int delta)
-{
- return ((reg + delta) & 0x7) | (reg & ~0x7);
-}
-
-/*
- * Advance the D reg number forwards by delta within its bank
- * (ie increment the low 2 bits but leave the rest the same)
- */
-static inline int vfp_advance_dreg(int reg, int delta)
-{
- return ((reg + delta) & 0x3) | (reg & ~0x3);
-}
-
-/*
- * Perform a 3-operand VFP data processing instruction. fn is the
- * callback to do the actual operation; this function deals with the
- * code to handle looping around for VFP vector processing.
- */
-static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
- int vd, int vn, int vm, bool reads_vd)
-{
- uint32_t delta_m = 0;
- uint32_t delta_d = 0;
- int veclen = s->vec_len;
- TCGv_i32 f0, f1, fd;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (veclen > 0) {
- /* Figure out what type of vector operation this is. */
- if (vfp_sreg_is_scalar(vd)) {
- /* scalar */
- veclen = 0;
- } else {
- delta_d = s->vec_stride + 1;
-
- if (vfp_sreg_is_scalar(vm)) {
- /* mixed scalar/vector */
- delta_m = 0;
- } else {
- /* vector */
- delta_m = delta_d;
- }
- }
- }
-
- f0 = tcg_temp_new_i32();
- f1 = tcg_temp_new_i32();
- fd = tcg_temp_new_i32();
- fpst = get_fpstatus_ptr(0);
-
- neon_load_reg32(f0, vn);
- neon_load_reg32(f1, vm);
-
- for (;;) {
- if (reads_vd) {
- neon_load_reg32(fd, vd);
- }
- fn(fd, f0, f1, fpst);
- neon_store_reg32(fd, vd);
-
- if (veclen == 0) {
- break;
- }
-
- /* Set up the operands for the next iteration */
- veclen--;
- vd = vfp_advance_sreg(vd, delta_d);
- vn = vfp_advance_sreg(vn, delta_d);
- neon_load_reg32(f0, vn);
- if (delta_m) {
- vm = vfp_advance_sreg(vm, delta_m);
- neon_load_reg32(f1, vm);
- }
- }
-
- tcg_temp_free_i32(f0);
- tcg_temp_free_i32(f1);
- tcg_temp_free_i32(fd);
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
- int vd, int vn, int vm, bool reads_vd)
-{
- uint32_t delta_m = 0;
- uint32_t delta_d = 0;
- int veclen = s->vec_len;
- TCGv_i64 f0, f1, fd;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (veclen > 0) {
- /* Figure out what type of vector operation this is. */
- if (vfp_dreg_is_scalar(vd)) {
- /* scalar */
- veclen = 0;
- } else {
- delta_d = (s->vec_stride >> 1) + 1;
-
- if (vfp_dreg_is_scalar(vm)) {
- /* mixed scalar/vector */
- delta_m = 0;
- } else {
- /* vector */
- delta_m = delta_d;
- }
- }
- }
-
- f0 = tcg_temp_new_i64();
- f1 = tcg_temp_new_i64();
- fd = tcg_temp_new_i64();
- fpst = get_fpstatus_ptr(0);
-
- neon_load_reg64(f0, vn);
- neon_load_reg64(f1, vm);
-
- for (;;) {
- if (reads_vd) {
- neon_load_reg64(fd, vd);
- }
- fn(fd, f0, f1, fpst);
- neon_store_reg64(fd, vd);
-
- if (veclen == 0) {
- break;
- }
- /* Set up the operands for the next iteration */
- veclen--;
- vd = vfp_advance_dreg(vd, delta_d);
- vn = vfp_advance_dreg(vn, delta_d);
- neon_load_reg64(f0, vn);
- if (delta_m) {
- vm = vfp_advance_dreg(vm, delta_m);
- neon_load_reg64(f1, vm);
- }
- }
-
- tcg_temp_free_i64(f0);
- tcg_temp_free_i64(f1);
- tcg_temp_free_i64(fd);
- tcg_temp_free_ptr(fpst);
-
- return true;
-}
-
-static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
-{
- uint32_t delta_m = 0;
- uint32_t delta_d = 0;
- int veclen = s->vec_len;
- TCGv_i32 f0, fd;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (veclen > 0) {
- /* Figure out what type of vector operation this is. */
- if (vfp_sreg_is_scalar(vd)) {
- /* scalar */
- veclen = 0;
- } else {
- delta_d = s->vec_stride + 1;
-
- if (vfp_sreg_is_scalar(vm)) {
- /* mixed scalar/vector */
- delta_m = 0;
- } else {
- /* vector */
- delta_m = delta_d;
- }
- }
- }
-
- f0 = tcg_temp_new_i32();
- fd = tcg_temp_new_i32();
-
- neon_load_reg32(f0, vm);
-
- for (;;) {
- fn(fd, f0);
- neon_store_reg32(fd, vd);
-
- if (veclen == 0) {
- break;
- }
-
- if (delta_m == 0) {
- /* single source one-many */
- while (veclen--) {
- vd = vfp_advance_sreg(vd, delta_d);
- neon_store_reg32(fd, vd);
- }
- break;
- }
-
- /* Set up the operands for the next iteration */
- veclen--;
- vd = vfp_advance_sreg(vd, delta_d);
- vm = vfp_advance_sreg(vm, delta_m);
- neon_load_reg32(f0, vm);
- }
-
- tcg_temp_free_i32(f0);
- tcg_temp_free_i32(fd);
-
- return true;
-}
-
-static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
-{
- uint32_t delta_m = 0;
- uint32_t delta_d = 0;
- int veclen = s->vec_len;
- TCGv_i64 f0, fd;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (veclen > 0) {
- /* Figure out what type of vector operation this is. */
- if (vfp_dreg_is_scalar(vd)) {
- /* scalar */
- veclen = 0;
- } else {
- delta_d = (s->vec_stride >> 1) + 1;
-
- if (vfp_dreg_is_scalar(vm)) {
- /* mixed scalar/vector */
- delta_m = 0;
- } else {
- /* vector */
- delta_m = delta_d;
- }
- }
- }
-
- f0 = tcg_temp_new_i64();
- fd = tcg_temp_new_i64();
-
- neon_load_reg64(f0, vm);
-
- for (;;) {
- fn(fd, f0);
- neon_store_reg64(fd, vd);
-
- if (veclen == 0) {
- break;
- }
-
- if (delta_m == 0) {
- /* single source one-many */
- while (veclen--) {
- vd = vfp_advance_dreg(vd, delta_d);
- neon_store_reg64(fd, vd);
- }
- break;
- }
-
- /* Set up the operands for the next iteration */
- veclen--;
- vd = vfp_advance_dreg(vd, delta_d);
- vd = vfp_advance_dreg(vm, delta_m);
- neon_load_reg64(f0, vm);
- }
-
- tcg_temp_free_i64(f0);
- tcg_temp_free_i64(fd);
-
- return true;
-}
-
-static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
-{
- /* Note that order of inputs to the add matters for NaNs */
- TCGv_i32 tmp = tcg_temp_new_i32();
-
- gen_helper_vfp_muls(tmp, vn, vm, fpst);
- gen_helper_vfp_adds(vd, vd, tmp, fpst);
- tcg_temp_free_i32(tmp);
-}
-
-static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a)
-{
- return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
-{
- /* Note that order of inputs to the add matters for NaNs */
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- gen_helper_vfp_muld(tmp, vn, vm, fpst);
- gen_helper_vfp_addd(vd, vd, tmp, fpst);
- tcg_temp_free_i64(tmp);
-}
-
-static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a)
-{
- return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
-{
- /*
- * VMLS: vd = vd + -(vn * vm)
- * Note that order of inputs to the add matters for NaNs.
- */
- TCGv_i32 tmp = tcg_temp_new_i32();
-
- gen_helper_vfp_muls(tmp, vn, vm, fpst);
- gen_helper_vfp_negs(tmp, tmp);
- gen_helper_vfp_adds(vd, vd, tmp, fpst);
- tcg_temp_free_i32(tmp);
-}
-
-static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a)
-{
- return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
-{
- /*
- * VMLS: vd = vd + -(vn * vm)
- * Note that order of inputs to the add matters for NaNs.
- */
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- gen_helper_vfp_muld(tmp, vn, vm, fpst);
- gen_helper_vfp_negd(tmp, tmp);
- gen_helper_vfp_addd(vd, vd, tmp, fpst);
- tcg_temp_free_i64(tmp);
-}
-
-static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a)
-{
- return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
-{
- /*
- * VNMLS: -fd + (fn * fm)
- * Note that it isn't valid to replace (-A + B) with (B - A) or similar
- * plausible looking simplifications because this will give wrong results
- * for NaNs.
- */
- TCGv_i32 tmp = tcg_temp_new_i32();
-
- gen_helper_vfp_muls(tmp, vn, vm, fpst);
- gen_helper_vfp_negs(vd, vd);
- gen_helper_vfp_adds(vd, vd, tmp, fpst);
- tcg_temp_free_i32(tmp);
-}
-
-static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a)
-{
- return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
-{
- /*
- * VNMLS: -fd + (fn * fm)
- * Note that it isn't valid to replace (-A + B) with (B - A) or similar
- * plausible looking simplifications because this will give wrong results
- * for NaNs.
- */
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- gen_helper_vfp_muld(tmp, vn, vm, fpst);
- gen_helper_vfp_negd(vd, vd);
- gen_helper_vfp_addd(vd, vd, tmp, fpst);
- tcg_temp_free_i64(tmp);
-}
-
-static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a)
-{
- return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
-{
- /* VNMLA: -fd + -(fn * fm) */
- TCGv_i32 tmp = tcg_temp_new_i32();
-
- gen_helper_vfp_muls(tmp, vn, vm, fpst);
- gen_helper_vfp_negs(tmp, tmp);
- gen_helper_vfp_negs(vd, vd);
- gen_helper_vfp_adds(vd, vd, tmp, fpst);
- tcg_temp_free_i32(tmp);
-}
-
-static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a)
-{
- return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true);
-}
-
-static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
-{
- /* VNMLA: -fd + (fn * fm) */
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- gen_helper_vfp_muld(tmp, vn, vm, fpst);
- gen_helper_vfp_negd(tmp, tmp);
- gen_helper_vfp_negd(vd, vd);
- gen_helper_vfp_addd(vd, vd, tmp, fpst);
- tcg_temp_free_i64(tmp);
-}
-
-static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a)
-{
- return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
-}
-
-static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a)
-{
- return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a)
-{
- return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false);
-}
-
-static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
-{
- /* VNMUL: -(fn * fm) */
- gen_helper_vfp_muls(vd, vn, vm, fpst);
- gen_helper_vfp_negs(vd, vd);
-}
-
-static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a)
-{
- return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false);
-}
-
-static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
-{
- /* VNMUL: -(fn * fm) */
- gen_helper_vfp_muld(vd, vn, vm, fpst);
- gen_helper_vfp_negd(vd, vd);
-}
-
-static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a)
-{
- return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a)
-{
- return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a)
-{
- return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a)
-{
- return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a)
-{
- return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a)
-{
- return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
-{
- return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
-{
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
- return false;
- }
- return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
- a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
-{
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
- return false;
- }
- return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
- a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
-{
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
- return false;
- }
- return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
- a->vd, a->vn, a->vm, false);
-}
-
-static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
-{
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
- return false;
- }
- return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
- a->vd, a->vn, a->vm, false);
-}
-
-static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
-{
- /*
- * VFNMA : fd = muladd(-fd, fn, fm)
- * VFNMS : fd = muladd(-fd, -fn, fm)
- * VFMA : fd = muladd( fd, fn, fm)
- * VFMS : fd = muladd( fd, -fn, fm)
- *
- * These are fused multiply-add, and must be done as one floating
- * point operation with no rounding between the multiplication and
- * addition steps. NB that doing the negations here as separate
- * steps is correct : an input NaN should come out with its sign
- * bit flipped if it is a negated-input.
- */
- TCGv_ptr fpst;
- TCGv_i32 vn, vm, vd;
-
- /*
- * Present in VFPv4 only.
- * Note that we can't rely on the SIMDFMAC check alone, because
- * in a Neon-no-VFP core that ID register field will be non-zero.
- */
- if (!dc_isar_feature(aa32_simdfmac, s) ||
- !dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
- /*
- * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
- * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
- */
- if (s->vec_len != 0 || s->vec_stride != 0) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vn = tcg_temp_new_i32();
- vm = tcg_temp_new_i32();
- vd = tcg_temp_new_i32();
-
- neon_load_reg32(vn, a->vn);
- neon_load_reg32(vm, a->vm);
- if (neg_n) {
- /* VFNMS, VFMS */
- gen_helper_vfp_negs(vn, vn);
- }
- neon_load_reg32(vd, a->vd);
- if (neg_d) {
- /* VFNMA, VFNMS */
- gen_helper_vfp_negs(vd, vd);
- }
- fpst = get_fpstatus_ptr(0);
- gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
- neon_store_reg32(vd, a->vd);
-
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(vn);
- tcg_temp_free_i32(vm);
- tcg_temp_free_i32(vd);
-
- return true;
-}
-
-static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a)
-{
- return do_vfm_sp(s, a, false, false);
-}
-
-static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a)
-{
- return do_vfm_sp(s, a, true, false);
-}
-
-static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a)
-{
- return do_vfm_sp(s, a, false, true);
-}
-
-static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a)
-{
- return do_vfm_sp(s, a, true, true);
-}
-
-static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
-{
- /*
- * VFNMA : fd = muladd(-fd, fn, fm)
- * VFNMS : fd = muladd(-fd, -fn, fm)
- * VFMA : fd = muladd( fd, fn, fm)
- * VFMS : fd = muladd( fd, -fn, fm)
- *
- * These are fused multiply-add, and must be done as one floating
- * point operation with no rounding between the multiplication and
- * addition steps. NB that doing the negations here as separate
- * steps is correct : an input NaN should come out with its sign
- * bit flipped if it is a negated-input.
- */
- TCGv_ptr fpst;
- TCGv_i64 vn, vm, vd;
-
- /*
- * Present in VFPv4 only.
- * Note that we can't rely on the SIMDFMAC check alone, because
- * in a Neon-no-VFP core that ID register field will be non-zero.
- */
- if (!dc_isar_feature(aa32_simdfmac, s) ||
- !dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
- /*
- * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
- * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
- */
- if (s->vec_len != 0 || s->vec_stride != 0) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vn = tcg_temp_new_i64();
- vm = tcg_temp_new_i64();
- vd = tcg_temp_new_i64();
-
- neon_load_reg64(vn, a->vn);
- neon_load_reg64(vm, a->vm);
- if (neg_n) {
- /* VFNMS, VFMS */
- gen_helper_vfp_negd(vn, vn);
- }
- neon_load_reg64(vd, a->vd);
- if (neg_d) {
- /* VFNMA, VFNMS */
- gen_helper_vfp_negd(vd, vd);
- }
- fpst = get_fpstatus_ptr(0);
- gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
- neon_store_reg64(vd, a->vd);
-
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i64(vn);
- tcg_temp_free_i64(vm);
- tcg_temp_free_i64(vd);
-
- return true;
-}
-
-static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a)
-{
- return do_vfm_dp(s, a, false, false);
-}
-
-static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a)
-{
- return do_vfm_dp(s, a, true, false);
-}
-
-static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a)
-{
- return do_vfm_dp(s, a, false, true);
-}
-
-static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a)
-{
- return do_vfm_dp(s, a, true, true);
-}
-
-static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
-{
- uint32_t delta_d = 0;
- int veclen = s->vec_len;
- TCGv_i32 fd;
- uint32_t vd;
-
- vd = a->vd;
-
- if (!dc_isar_feature(aa32_fpsp_v3, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (veclen > 0) {
- /* Figure out what type of vector operation this is. */
- if (vfp_sreg_is_scalar(vd)) {
- /* scalar */
- veclen = 0;
- } else {
- delta_d = s->vec_stride + 1;
- }
- }
-
- fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
-
- for (;;) {
- neon_store_reg32(fd, vd);
-
- if (veclen == 0) {
- break;
- }
-
- /* Set up the operands for the next iteration */
- veclen--;
- vd = vfp_advance_sreg(vd, delta_d);
- }
-
- tcg_temp_free_i32(fd);
- return true;
-}
-
-static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
-{
- uint32_t delta_d = 0;
- int veclen = s->vec_len;
- TCGv_i64 fd;
- uint32_t vd;
-
- vd = a->vd;
-
- if (!dc_isar_feature(aa32_fpdp_v3, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- if (veclen > 0) {
- /* Figure out what type of vector operation this is. */
- if (vfp_dreg_is_scalar(vd)) {
- /* scalar */
- veclen = 0;
- } else {
- delta_d = (s->vec_stride >> 1) + 1;
- }
- }
-
- fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
-
- for (;;) {
- neon_store_reg64(fd, vd);
-
- if (veclen == 0) {
- break;
- }
-
- /* Set up the operands for the next iteration */
- veclen--;
- vd = vfp_advance_dreg(vd, delta_d);
- }
-
- tcg_temp_free_i64(fd);
- return true;
-}
-
-static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a)
-{
- return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm);
-}
-
-static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a)
-{
- return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm);
-}
-
-static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
-{
- return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
-}
-
-static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a)
-{
- return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
-}
-
-static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a)
-{
- return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm);
-}
-
-static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
-{
- return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
-}
-
-static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
-{
- gen_helper_vfp_sqrts(vd, vm, cpu_env);
-}
-
-static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a)
-{
- return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm);
-}
-
-static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
-{
- gen_helper_vfp_sqrtd(vd, vm, cpu_env);
-}
-
-static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a)
-{
- return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm);
-}
-
-static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
-{
- TCGv_i32 vd, vm;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- /* Vm/M bits must be zero for the Z variant */
- if (a->z && a->vm != 0) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vd = tcg_temp_new_i32();
- vm = tcg_temp_new_i32();
-
- neon_load_reg32(vd, a->vd);
- if (a->z) {
- tcg_gen_movi_i32(vm, 0);
- } else {
- neon_load_reg32(vm, a->vm);
- }
-
- if (a->e) {
- gen_helper_vfp_cmpes(vd, vm, cpu_env);
- } else {
- gen_helper_vfp_cmps(vd, vm, cpu_env);
- }
-
- tcg_temp_free_i32(vd);
- tcg_temp_free_i32(vm);
-
- return true;
-}
-
-static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
-{
- TCGv_i64 vd, vm;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* Vm/M bits must be zero for the Z variant */
- if (a->z && a->vm != 0) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vd = tcg_temp_new_i64();
- vm = tcg_temp_new_i64();
-
- neon_load_reg64(vd, a->vd);
- if (a->z) {
- tcg_gen_movi_i64(vm, 0);
- } else {
- neon_load_reg64(vm, a->vm);
- }
-
- if (a->e) {
- gen_helper_vfp_cmped(vd, vm, cpu_env);
- } else {
- gen_helper_vfp_cmpd(vd, vm, cpu_env);
- }
-
- tcg_temp_free_i64(vd);
- tcg_temp_free_i64(vm);
-
- return true;
-}
-
-static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 ahp_mode;
- TCGv_i32 tmp;
-
- if (!dc_isar_feature(aa32_fp16_spconv, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(false);
- ahp_mode = get_ahp_flag();
- tmp = tcg_temp_new_i32();
- /* The T bit tells us if we want the low or high 16 bits of Vm */
- tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
- gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
- neon_store_reg32(tmp, a->vd);
- tcg_temp_free_i32(ahp_mode);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 ahp_mode;
- TCGv_i32 tmp;
- TCGv_i64 vd;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(false);
- ahp_mode = get_ahp_flag();
- tmp = tcg_temp_new_i32();
- /* The T bit tells us if we want the low or high 16 bits of Vm */
- tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
- vd = tcg_temp_new_i64();
- gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
- neon_store_reg64(vd, a->vd);
- tcg_temp_free_i32(ahp_mode);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i64(vd);
- return true;
-}
-
-static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 ahp_mode;
- TCGv_i32 tmp;
-
- if (!dc_isar_feature(aa32_fp16_spconv, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(false);
- ahp_mode = get_ahp_flag();
- tmp = tcg_temp_new_i32();
-
- neon_load_reg32(tmp, a->vm);
- gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
- tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
- tcg_temp_free_i32(ahp_mode);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 ahp_mode;
- TCGv_i32 tmp;
- TCGv_i64 vm;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(false);
- ahp_mode = get_ahp_flag();
- tmp = tcg_temp_new_i32();
- vm = tcg_temp_new_i64();
-
- neon_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
- tcg_temp_free_i64(vm);
- tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
- tcg_temp_free_i32(ahp_mode);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 tmp;
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm);
- fpst = get_fpstatus_ptr(false);
- gen_helper_rints(tmp, tmp, fpst);
- neon_store_reg32(tmp, a->vd);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
-{
- TCGv_ptr fpst;
- TCGv_i64 tmp;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i64();
- neon_load_reg64(tmp, a->vm);
- fpst = get_fpstatus_ptr(false);
- gen_helper_rintd(tmp, tmp, fpst);
- neon_store_reg64(tmp, a->vd);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
-static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 tmp;
- TCGv_i32 tcg_rmode;
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm);
- fpst = get_fpstatus_ptr(false);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
- gen_helper_rints(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
- neon_store_reg32(tmp, a->vd);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tcg_rmode);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
-{
- TCGv_ptr fpst;
- TCGv_i64 tmp;
- TCGv_i32 tcg_rmode;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i64();
- neon_load_reg64(tmp, a->vm);
- fpst = get_fpstatus_ptr(false);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
- gen_helper_rintd(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
- neon_store_reg64(tmp, a->vd);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i32(tcg_rmode);
- return true;
-}
-
-static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
-{
- TCGv_ptr fpst;
- TCGv_i32 tmp;
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i32();
- neon_load_reg32(tmp, a->vm);
- fpst = get_fpstatus_ptr(false);
- gen_helper_rints_exact(tmp, tmp, fpst);
- neon_store_reg32(tmp, a->vd);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i32(tmp);
- return true;
-}
-
-static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
-{
- TCGv_ptr fpst;
- TCGv_i64 tmp;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_vrint, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp = tcg_temp_new_i64();
- neon_load_reg64(tmp, a->vm);
- fpst = get_fpstatus_ptr(false);
- gen_helper_rintd_exact(tmp, tmp, fpst);
- neon_store_reg64(tmp, a->vd);
- tcg_temp_free_ptr(fpst);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
-static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
-{
- TCGv_i64 vd;
- TCGv_i32 vm;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vm = tcg_temp_new_i32();
- vd = tcg_temp_new_i64();
- neon_load_reg32(vm, a->vm);
- gen_helper_vfp_fcvtds(vd, vm, cpu_env);
- neon_store_reg64(vd, a->vd);
- tcg_temp_free_i32(vm);
- tcg_temp_free_i64(vd);
- return true;
-}
-
-static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
-{
- TCGv_i64 vm;
- TCGv_i32 vd;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vd = tcg_temp_new_i32();
- vm = tcg_temp_new_i64();
- neon_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
- neon_store_reg32(vd, a->vd);
- tcg_temp_free_i32(vd);
- tcg_temp_free_i64(vm);
- return true;
-}
-
-static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
-{
- TCGv_i32 vm;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vm = tcg_temp_new_i32();
- neon_load_reg32(vm, a->vm);
- fpst = get_fpstatus_ptr(false);
- if (a->s) {
- /* i32 -> f32 */
- gen_helper_vfp_sitos(vm, vm, fpst);
- } else {
- /* u32 -> f32 */
- gen_helper_vfp_uitos(vm, vm, fpst);
- }
- neon_store_reg32(vm, a->vd);
- tcg_temp_free_i32(vm);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
-{
- TCGv_i32 vm;
- TCGv_i64 vd;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vm = tcg_temp_new_i32();
- vd = tcg_temp_new_i64();
- neon_load_reg32(vm, a->vm);
- fpst = get_fpstatus_ptr(false);
- if (a->s) {
- /* i32 -> f64 */
- gen_helper_vfp_sitod(vd, vm, fpst);
- } else {
- /* u32 -> f64 */
- gen_helper_vfp_uitod(vd, vm, fpst);
- }
- neon_store_reg64(vd, a->vd);
- tcg_temp_free_i32(vm);
- tcg_temp_free_i64(vd);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
-{
- TCGv_i32 vd;
- TCGv_i64 vm;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!dc_isar_feature(aa32_jscvt, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- vm = tcg_temp_new_i64();
- vd = tcg_temp_new_i32();
- neon_load_reg64(vm, a->vm);
- gen_helper_vjcvt(vd, vm, cpu_env);
- neon_store_reg32(vd, a->vd);
- tcg_temp_free_i64(vm);
- tcg_temp_free_i32(vd);
- return true;
-}
-
-static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
-{
- TCGv_i32 vd, shift;
- TCGv_ptr fpst;
- int frac_bits;
-
- if (!dc_isar_feature(aa32_fpsp_v3, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
-
- vd = tcg_temp_new_i32();
- neon_load_reg32(vd, a->vd);
-
- fpst = get_fpstatus_ptr(false);
- shift = tcg_const_i32(frac_bits);
-
- /* Switch on op:U:sx bits */
- switch (a->opc) {
- case 0:
- gen_helper_vfp_shtos(vd, vd, shift, fpst);
- break;
- case 1:
- gen_helper_vfp_sltos(vd, vd, shift, fpst);
- break;
- case 2:
- gen_helper_vfp_uhtos(vd, vd, shift, fpst);
- break;
- case 3:
- gen_helper_vfp_ultos(vd, vd, shift, fpst);
- break;
- case 4:
- gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst);
- break;
- case 5:
- gen_helper_vfp_tosls_round_to_zero(vd, vd, shift, fpst);
- break;
- case 6:
- gen_helper_vfp_touhs_round_to_zero(vd, vd, shift, fpst);
- break;
- case 7:
- gen_helper_vfp_touls_round_to_zero(vd, vd, shift, fpst);
- break;
- default:
- g_assert_not_reached();
- }
-
- neon_store_reg32(vd, a->vd);
- tcg_temp_free_i32(vd);
- tcg_temp_free_i32(shift);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
-{
- TCGv_i64 vd;
- TCGv_i32 shift;
- TCGv_ptr fpst;
- int frac_bits;
-
- if (!dc_isar_feature(aa32_fpdp_v3, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
-
- vd = tcg_temp_new_i64();
- neon_load_reg64(vd, a->vd);
-
- fpst = get_fpstatus_ptr(false);
- shift = tcg_const_i32(frac_bits);
-
- /* Switch on op:U:sx bits */
- switch (a->opc) {
- case 0:
- gen_helper_vfp_shtod(vd, vd, shift, fpst);
- break;
- case 1:
- gen_helper_vfp_sltod(vd, vd, shift, fpst);
- break;
- case 2:
- gen_helper_vfp_uhtod(vd, vd, shift, fpst);
- break;
- case 3:
- gen_helper_vfp_ultod(vd, vd, shift, fpst);
- break;
- case 4:
- gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst);
- break;
- case 5:
- gen_helper_vfp_tosld_round_to_zero(vd, vd, shift, fpst);
- break;
- case 6:
- gen_helper_vfp_touhd_round_to_zero(vd, vd, shift, fpst);
- break;
- case 7:
- gen_helper_vfp_tould_round_to_zero(vd, vd, shift, fpst);
- break;
- default:
- g_assert_not_reached();
- }
-
- neon_store_reg64(vd, a->vd);
- tcg_temp_free_i64(vd);
- tcg_temp_free_i32(shift);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
-{
- TCGv_i32 vm;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(false);
- vm = tcg_temp_new_i32();
- neon_load_reg32(vm, a->vm);
-
- if (a->s) {
- if (a->rz) {
- gen_helper_vfp_tosizs(vm, vm, fpst);
- } else {
- gen_helper_vfp_tosis(vm, vm, fpst);
- }
- } else {
- if (a->rz) {
- gen_helper_vfp_touizs(vm, vm, fpst);
- } else {
- gen_helper_vfp_touis(vm, vm, fpst);
- }
- }
- neon_store_reg32(vm, a->vd);
- tcg_temp_free_i32(vm);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
-{
- TCGv_i32 vd;
- TCGv_i64 vm;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(false);
- vm = tcg_temp_new_i64();
- vd = tcg_temp_new_i32();
- neon_load_reg64(vm, a->vm);
-
- if (a->s) {
- if (a->rz) {
- gen_helper_vfp_tosizd(vd, vm, fpst);
- } else {
- gen_helper_vfp_tosid(vd, vm, fpst);
- }
- } else {
- if (a->rz) {
- gen_helper_vfp_touizd(vd, vm, fpst);
- } else {
- gen_helper_vfp_touid(vd, vm, fpst);
- }
- }
- neon_store_reg32(vd, a->vd);
- tcg_temp_free_i32(vd);
- tcg_temp_free_i64(vm);
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
-/*
- * Decode VLLDM and VLSTM are nonstandard because:
- * * if there is no FPU then these insns must NOP in
- * Secure state and UNDEF in Nonsecure state
- * * if there is an FPU then these insns do not have
- * the usual behaviour that vfp_access_check() provides of
- * being controlled by CPACR/NSACR enable bits or the
- * lazy-stacking logic.
- */
-static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
-{
- TCGv_i32 fptr;
-
- if (!arm_dc_feature(s, ARM_FEATURE_M) ||
- !arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
- /* If not secure, UNDEF. */
- if (!s->v8m_secure) {
- return false;
- }
- /* If no fpu, NOP. */
- if (!dc_isar_feature(aa32_vfp, s)) {
- return true;
- }
-
- fptr = load_reg(s, a->rn);
- if (a->l) {
- gen_helper_v7m_vlldm(cpu_env, fptr);
- } else {
- gen_helper_v7m_vlstm(cpu_env, fptr);
- }
- tcg_temp_free_i32(fptr);
-
- /* End the TB, because we have updated FP control bits */
- s->base.is_jmp = DISAS_UPDATE_EXIT;
- return true;
-}
#define ARM_CP_RW_BIT (1 << 20)
/* Include the VFP and Neon decoders */
-#include "translate-vfp.inc.c"
-#include "translate-neon.inc.c"
+#include "translate-vfp.c.inc"
+#include "translate-neon.c.inc"
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{
* Include the generated decoders.
*/
-#include "decode-a32.inc.c"
-#include "decode-a32-uncond.inc.c"
-#include "decode-t32.inc.c"
-#include "decode-t16.inc.c"
+#include "decode-a32.c.inc"
+#include "decode-a32-uncond.c.inc"
+#include "decode-t32.c.inc"
+#include "decode-t16.c.inc"
/* Helpers to swap operands for reverse-subtract. */
static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
decode-y = $(SRC_PATH)/target/avr/insn.decode
-target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE)
+target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
"GEN", $(TARGET_DIR)$@)
-target/avr/translate.o: target/avr/decode_insn.inc.c
+target/avr/translate.o: target/avr/decode_insn.c.inc
obj-y += translate.o cpu.o helper.o
obj-y += gdbstub.o
/* Include the auto-generated decoder. */
static bool decode_insn(DisasContext *ctx, uint16_t insn);
-#include "decode_insn.inc.c"
+#include "decode_insn.c.inc"
#define output(mnemonic, format, ...) \
(pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \
}
static bool decode_insn(DisasContext *ctx, uint16_t insn);
-#include "decode_insn.inc.c"
+#include "decode_insn.c.inc"
/*
* Arithmetic Instructions
return insn_len;
}
-#include "translate_v10.inc.c"
+#include "translate_v10.c.inc"
/*
* Delay slots on QEMU/CRIS.
--- /dev/null
+/*
+ * CRISv10 emulation for qemu: main translation routines.
+ *
+ * Copyright (c) 2010 AXIS Communications AB
+ * Written by Edgar E. Iglesias.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "crisv10-decode.h"
+
+static const char *regnames_v10[] =
+{
+ "$r0", "$r1", "$r2", "$r3",
+ "$r4", "$r5", "$r6", "$r7",
+ "$r8", "$r9", "$r10", "$r11",
+ "$r12", "$r13", "$sp", "$pc",
+};
+
+static const char *pregnames_v10[] =
+{
+ "$bz", "$vr", "$p2", "$p3",
+ "$wz", "$ccr", "$p6-prefix", "$mof",
+ "$dz", "$ibr", "$irp", "$srp",
+ "$bar", "$dccr", "$brp", "$usp",
+};
+
+/* We need this table to handle preg-moves with implicit width. */
+static int preg_sizes_v10[] = {
+ 1, /* bz. */
+ 1, /* vr. */
+ 1, /* pid. */
+ 1, /* srs. */
+ 2, /* wz. */
+ 2, 2, 4,
+ 4, 4, 4, 4,
+ 4, 4, 4, 4,
+};
+
+static inline int dec10_size(unsigned int size)
+{
+ size++;
+ if (size == 3)
+ size++;
+ return size;
+}
+
+static inline void cris_illegal_insn(DisasContext *dc)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc);
+ t_gen_raise_exception(EXCP_BREAK);
+}
+
+static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
+ unsigned int size, int mem_index)
+{
+ TCGLabel *l1 = gen_new_label();
+ TCGv taddr = tcg_temp_local_new();
+ TCGv tval = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
+ dc->postinc = 0;
+ cris_evaluate_flags(dc);
+
+ tcg_gen_mov_tl(taddr, addr);
+ tcg_gen_mov_tl(tval, val);
+
+ /* Store only if F flag isn't set */
+ tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ if (size == 1) {
+ tcg_gen_qemu_st8(tval, taddr, mem_index);
+ } else if (size == 2) {
+ tcg_gen_qemu_st16(tval, taddr, mem_index);
+ } else {
+ tcg_gen_qemu_st32(tval, taddr, mem_index);
+ }
+ gen_set_label(l1);
+ tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
+ tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
+ tcg_temp_free(t1);
+ tcg_temp_free(tval);
+ tcg_temp_free(taddr);
+}
+
+static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
+ unsigned int size)
+{
+ int mem_index = cpu_mmu_index(&dc->cpu->env, false);
+
+ /* If we get a fault on a delayslot we must keep the jmp state in
+ the cpu-state to be able to re-execute the jmp. */
+ if (dc->delayed_branch == 1) {
+ cris_store_direct_jmp(dc);
+ }
+
+ /* Conditional writes. We only support the kind were X is known
+ at translation time. */
+ if (dc->flagx_known && dc->flags_x) {
+ gen_store_v10_conditional(dc, addr, val, size, mem_index);
+ return;
+ }
+
+ if (size == 1) {
+ tcg_gen_qemu_st8(val, addr, mem_index);
+ } else if (size == 2) {
+ tcg_gen_qemu_st16(val, addr, mem_index);
+ } else {
+ tcg_gen_qemu_st32(val, addr, mem_index);
+ }
+}
+
+
+/* Prefix flag and register are used to handle the more complex
+ addressing modes. */
+static void cris_set_prefix(DisasContext *dc)
+{
+ dc->clear_prefix = 0;
+ dc->tb_flags |= PFIX_FLAG;
+ tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG);
+
+ /* prefix insns don't clear the x flag. */
+ dc->clear_x = 0;
+ cris_lock_irq(dc);
+}
+
+static void crisv10_prepare_memaddr(DisasContext *dc,
+ TCGv addr, unsigned int size)
+{
+ if (dc->tb_flags & PFIX_FLAG) {
+ tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]);
+ } else {
+ tcg_gen_mov_tl(addr, cpu_R[dc->src]);
+ }
+}
+
+static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
+{
+ unsigned int insn_len = 0;
+
+ if (dc->tb_flags & PFIX_FLAG) {
+ if (dc->mode == CRISV10_MODE_AUTOINC) {
+ tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
+ }
+ } else {
+ if (dc->mode == CRISV10_MODE_AUTOINC) {
+ if (dc->src == 15) {
+ insn_len += size & ~1;
+ } else {
+ tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
+ }
+ }
+ }
+ return insn_len;
+}
+
+static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
+ int s_ext, int memsize, TCGv dst)
+{
+ unsigned int rs;
+ uint32_t imm;
+ int is_imm;
+ int insn_len = 0;
+
+ rs = dc->src;
+ is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
+ LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
+ rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
+
+ /* Load [$rs] onto T1. */
+ if (is_imm) {
+ if (memsize != 4) {
+ if (s_ext) {
+ if (memsize == 1)
+ imm = cpu_ldsb_code(env, dc->pc + 2);
+ else
+ imm = cpu_ldsw_code(env, dc->pc + 2);
+ } else {
+ if (memsize == 1)
+ imm = cpu_ldub_code(env, dc->pc + 2);
+ else
+ imm = cpu_lduw_code(env, dc->pc + 2);
+ }
+ } else
+ imm = cpu_ldl_code(env, dc->pc + 2);
+
+ tcg_gen_movi_tl(dst, imm);
+
+ if (dc->mode == CRISV10_MODE_AUTOINC) {
+ insn_len += memsize;
+ if (memsize == 1)
+ insn_len++;
+ tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len);
+ }
+ } else {
+ TCGv addr;
+
+ addr = tcg_temp_new();
+ cris_flush_cc_state(dc);
+ crisv10_prepare_memaddr(dc, addr, memsize);
+ gen_load(dc, dst, addr, memsize, 0);
+ if (s_ext)
+ t_gen_sext(dst, dst, memsize);
+ else
+ t_gen_zext(dst, dst, memsize);
+ insn_len += crisv10_post_memaddr(dc, memsize);
+ tcg_temp_free(addr);
+ }
+
+ if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
+ dc->dst = dc->src;
+ }
+ return insn_len;
+}
+
+static unsigned int dec10_quick_imm(DisasContext *dc)
+{
+ int32_t imm, simm;
+ int op;
+
+ /* sign extend. */
+ imm = dc->ir & ((1 << 6) - 1);
+ simm = (int8_t) (imm << 2);
+ simm >>= 2;
+ switch (dc->opcode) {
+ case CRISV10_QIMM_BDAP_R0:
+ case CRISV10_QIMM_BDAP_R1:
+ case CRISV10_QIMM_BDAP_R2:
+ case CRISV10_QIMM_BDAP_R3:
+ simm = (int8_t)dc->ir;
+ LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
+ LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
+ dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
+ cris_set_prefix(dc);
+ if (dc->dst == 15) {
+ tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
+ } else {
+ tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
+ }
+ break;
+
+ case CRISV10_QIMM_MOVEQ:
+ LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(simm), 4);
+ break;
+ case CRISV10_QIMM_CMPQ:
+ LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(simm), 4);
+ break;
+ case CRISV10_QIMM_ADDQ:
+ LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(imm), 4);
+ break;
+ case CRISV10_QIMM_ANDQ:
+ LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(simm), 4);
+ break;
+ case CRISV10_QIMM_ASHQ:
+ LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ op = imm & (1 << 5);
+ imm &= 0x1f;
+ if (op) {
+ cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(imm), 4);
+ } else {
+ /* BTST */
+ cris_update_cc_op(dc, CC_OP_FLAGS, 4);
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
+ tcg_const_tl(imm), cpu_PR[PR_CCS]);
+ }
+ break;
+ case CRISV10_QIMM_LSHQ:
+ LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
+
+ op = CC_OP_LSL;
+ if (imm & (1 << 5)) {
+ op = CC_OP_LSR;
+ }
+ imm &= 0x1f;
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, op, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(imm), 4);
+ break;
+ case CRISV10_QIMM_SUBQ:
+ LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(imm), 4);
+ break;
+ case CRISV10_QIMM_ORQ:
+ LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
+ cpu_R[dc->dst], tcg_const_tl(simm), 4);
+ break;
+
+ case CRISV10_QIMM_BCC_R0:
+ case CRISV10_QIMM_BCC_R1:
+ case CRISV10_QIMM_BCC_R2:
+ case CRISV10_QIMM_BCC_R3:
+ imm = dc->ir & 0xff;
+ /* bit 0 is a sign bit. */
+ if (imm & 1) {
+ imm |= 0xffffff00; /* sign extend. */
+ imm &= ~1; /* get rid of the sign bit. */
+ }
+ imm += 2;
+ LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
+
+ cris_cc_mask(dc, 0);
+ cris_prepare_cc_branch(dc, imm, dc->cond);
+ break;
+
+ default:
+ LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
+ dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
+ cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
+ break;
+ }
+ return 2;
+}
+
+static unsigned int dec10_setclrf(DisasContext *dc)
+{
+ uint32_t flags;
+ unsigned int set = ~dc->opcode & 1;
+
+ flags = EXTRACT_FIELD(dc->ir, 0, 3)
+ | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
+ LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
+
+
+ if (flags & X_FLAG) {
+ dc->flagx_known = 1;
+ if (set)
+ dc->flags_x = X_FLAG;
+ else
+ dc->flags_x = 0;
+ }
+
+ cris_evaluate_flags (dc);
+ cris_update_cc_op(dc, CC_OP_FLAGS, 4);
+ cris_update_cc_x(dc);
+ tcg_gen_movi_tl(cc_op, dc->cc_op);
+
+ if (set) {
+ tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
+ } else {
+ tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
+ ~(flags|F_FLAG_V10|P_FLAG_V10));
+ }
+
+ dc->flags_uptodate = 1;
+ dc->clear_x = 0;
+ cris_lock_irq(dc);
+ return 2;
+}
+
+static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
+ TCGv dd, TCGv ds, TCGv sd, TCGv ss)
+{
+ if (sext) {
+ t_gen_sext(dd, sd, size);
+ t_gen_sext(ds, ss, size);
+ } else {
+ t_gen_zext(dd, sd, size);
+ t_gen_zext(ds, ss, size);
+ }
+}
+
+static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
+{
+ TCGv t[2];
+
+ t[0] = tcg_temp_new();
+ t[1] = tcg_temp_new();
+ dec10_reg_prep_sext(dc, size, sext,
+ t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
+
+ if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
+ tcg_gen_andi_tl(t[1], t[1], 63);
+ }
+
+ assert(dc->dst != 15);
+ cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
+ tcg_temp_free(t[0]);
+ tcg_temp_free(t[1]);
+}
+
+static void dec10_reg_bound(DisasContext *dc, int size)
+{
+ TCGv t;
+
+ t = tcg_temp_local_new();
+ t_gen_zext(t, cpu_R[dc->src], size);
+ cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
+ tcg_temp_free(t);
+}
+
+static void dec10_reg_mul(DisasContext *dc, int size, int sext)
+{
+ int op = sext ? CC_OP_MULS : CC_OP_MULU;
+ TCGv t[2];
+
+ t[0] = tcg_temp_new();
+ t[1] = tcg_temp_new();
+ dec10_reg_prep_sext(dc, size, sext,
+ t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
+
+ cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
+
+ tcg_temp_free(t[0]);
+ tcg_temp_free(t[1]);
+}
+
+
+static void dec10_reg_movs(DisasContext *dc)
+{
+ int size = (dc->size & 1) + 1;
+ TCGv t;
+
+ LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+
+ t = tcg_temp_new();
+ if (dc->ir & 32)
+ t_gen_sext(t, cpu_R[dc->src], size);
+ else
+ t_gen_zext(t, cpu_R[dc->src], size);
+
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
+ tcg_temp_free(t);
+}
+
+static void dec10_reg_alux(DisasContext *dc, int op)
+{
+ int size = (dc->size & 1) + 1;
+ TCGv t;
+
+ LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+
+ t = tcg_temp_new();
+ if (dc->ir & 32)
+ t_gen_sext(t, cpu_R[dc->src], size);
+ else
+ t_gen_zext(t, cpu_R[dc->src], size);
+
+ cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
+ tcg_temp_free(t);
+}
+
+static void dec10_reg_mov_pr(DisasContext *dc)
+{
+ LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
+ cris_lock_irq(dc);
+ if (dc->src == 15) {
+ tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ return;
+ }
+ if (dc->dst == PR_CCS) {
+ cris_evaluate_flags(dc);
+ }
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
+ cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
+}
+
+static void dec10_reg_abs(DisasContext *dc)
+{
+ TCGv t0;
+
+ LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
+
+ assert(dc->dst != 15);
+ t0 = tcg_temp_new();
+ tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
+ tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
+ tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
+
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
+ tcg_temp_free(t0);
+}
+
+static void dec10_reg_swap(DisasContext *dc)
+{
+ TCGv t0;
+
+ LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ t0 = tcg_temp_new();
+ tcg_gen_mov_tl(t0, cpu_R[dc->src]);
+ if (dc->dst & 8)
+ tcg_gen_not_tl(t0, t0);
+ if (dc->dst & 4)
+ t_gen_swapw(t0, t0);
+ if (dc->dst & 2)
+ t_gen_swapb(t0, t0);
+ if (dc->dst & 1)
+ t_gen_swapr(t0, t0);
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
+ tcg_temp_free(t0);
+}
+
+static void dec10_reg_scc(DisasContext *dc)
+{
+ int cond = dc->dst;
+
+ LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
+
+ gen_tst_cc(dc, cpu_R[dc->src], cond);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0);
+
+ cris_cc_mask(dc, 0);
+}
+
+static unsigned int dec10_reg(DisasContext *dc)
+{
+ TCGv t;
+ unsigned int insn_len = 2;
+ unsigned int size = dec10_size(dc->size);
+ unsigned int tmp;
+
+ if (dc->size != 3) {
+ switch (dc->opcode) {
+ case CRISV10_REG_MOVE_R:
+ LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
+ if (dc->dst == 15) {
+ tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch = 1;
+ }
+ break;
+ case CRISV10_REG_MOVX:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_movs(dc);
+ break;
+ case CRISV10_REG_ADDX:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alux(dc, CC_OP_ADD);
+ break;
+ case CRISV10_REG_SUBX:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alux(dc, CC_OP_SUB);
+ break;
+ case CRISV10_REG_ADD:
+ LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_ADD, size, 0);
+ break;
+ case CRISV10_REG_SUB:
+ LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_SUB, size, 0);
+ break;
+ case CRISV10_REG_CMP:
+ LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_CMP, size, 0);
+ break;
+ case CRISV10_REG_BOUND:
+ LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_bound(dc, size);
+ break;
+ case CRISV10_REG_AND:
+ LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_AND, size, 0);
+ break;
+ case CRISV10_REG_ADDI:
+ if (dc->src == 15) {
+ /* nop. */
+ return 2;
+ }
+ t = tcg_temp_new();
+ LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
+ tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
+ tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
+ tcg_temp_free(t);
+ break;
+ case CRISV10_REG_LSL:
+ LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_LSL, size, 0);
+ break;
+ case CRISV10_REG_LSR:
+ LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_LSR, size, 0);
+ break;
+ case CRISV10_REG_ASR:
+ LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_ASR, size, 1);
+ break;
+ case CRISV10_REG_OR:
+ LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_OR, size, 0);
+ break;
+ case CRISV10_REG_NEG:
+ LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_NEG, size, 0);
+ break;
+ case CRISV10_REG_BIAP:
+ LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
+ dc->opcode, dc->src, dc->dst, size);
+ switch (size) {
+ case 4: tmp = 2; break;
+ case 2: tmp = 1; break;
+ case 1: tmp = 0; break;
+ default:
+ cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
+ break;
+ }
+
+ t = tcg_temp_new();
+ tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
+ if (dc->src == 15) {
+ tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
+ } else {
+ tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
+ }
+ tcg_temp_free(t);
+ cris_set_prefix(dc);
+ break;
+
+ default:
+ LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
+ dc->opcode, dc->src, dc->dst);
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
+ break;
+ }
+ } else {
+ switch (dc->opcode) {
+ case CRISV10_REG_MOVX:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_movs(dc);
+ break;
+ case CRISV10_REG_ADDX:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alux(dc, CC_OP_ADD);
+ break;
+ case CRISV10_REG_SUBX:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alux(dc, CC_OP_SUB);
+ break;
+ case CRISV10_REG_MOVE_SPR_R:
+ cris_evaluate_flags(dc);
+ cris_cc_mask(dc, 0);
+ dec10_reg_mov_pr(dc);
+ break;
+ case CRISV10_REG_MOVE_R_SPR:
+ LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
+ cris_evaluate_flags(dc);
+ if (dc->src != 11) /* fast for srp. */
+ dc->cpustate_changed = 1;
+ t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
+ break;
+ case CRISV10_REG_SETF:
+ case CRISV10_REG_CLEARF:
+ dec10_setclrf(dc);
+ break;
+ case CRISV10_REG_SWAP:
+ dec10_reg_swap(dc);
+ break;
+ case CRISV10_REG_ABS:
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_abs(dc);
+ break;
+ case CRISV10_REG_LZ:
+ LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
+ break;
+ case CRISV10_REG_XOR:
+ LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
+ break;
+ case CRISV10_REG_BTST:
+ LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_update_cc_op(dc, CC_OP_FLAGS, 4);
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
+ cpu_R[dc->src], cpu_PR[PR_CCS]);
+ break;
+ case CRISV10_REG_DSTEP:
+ LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
+ cpu_R[dc->dst], cpu_R[dc->src], 4);
+ break;
+ case CRISV10_REG_MSTEP:
+ LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
+ cris_evaluate_flags(dc);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
+ cpu_R[dc->dst], cpu_R[dc->src], 4);
+ break;
+ case CRISV10_REG_SCC:
+ dec10_reg_scc(dc);
+ break;
+ default:
+ LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
+ dc->opcode, dc->src, dc->dst);
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
+ break;
+ }
+ }
+ return insn_len;
+}
+
+static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
+ unsigned int size)
+{
+ unsigned int insn_len = 2;
+ TCGv t;
+
+ LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
+ size, dc->src, dc->dst);
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ t = tcg_temp_new();
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t);
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
+ if (dc->dst == 15) {
+ tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch = 1;
+ return insn_len;
+ }
+
+ tcg_temp_free(t);
+ return insn_len;
+}
+
+static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
+{
+ unsigned int insn_len = 2;
+ TCGv addr;
+
+ LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
+ addr = tcg_temp_new();
+ crisv10_prepare_memaddr(dc, addr, size);
+ gen_store_v10(dc, addr, cpu_R[dc->dst], size);
+ insn_len += crisv10_post_memaddr(dc, size);
+
+ return insn_len;
+}
+
+static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
+{
+ unsigned int insn_len = 2, rd = dc->dst;
+ TCGv t, addr;
+
+ LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
+ cris_lock_irq(dc);
+
+ addr = tcg_temp_new();
+ t = tcg_temp_new();
+ insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
+ if (rd == 15) {
+ tcg_gen_mov_tl(env_btarget, t);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch = 1;
+ return insn_len;
+ }
+
+ tcg_gen_mov_tl(cpu_PR[rd], t);
+ dc->cpustate_changed = 1;
+ tcg_temp_free(addr);
+ tcg_temp_free(t);
+ return insn_len;
+}
+
+static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
+{
+ unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
+ TCGv addr, t0;
+
+ LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
+
+ addr = tcg_temp_new();
+ crisv10_prepare_memaddr(dc, addr, size);
+ if (dc->dst == PR_CCS) {
+ t0 = tcg_temp_new();
+ cris_evaluate_flags(dc);
+ tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
+ gen_store_v10(dc, addr, t0, size);
+ tcg_temp_free(t0);
+ } else {
+ gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
+ }
+ t0 = tcg_temp_new();
+ insn_len += crisv10_post_memaddr(dc, size);
+ cris_lock_irq(dc);
+
+ return insn_len;
+}
+
+static void dec10_movem_r_m(DisasContext *dc)
+{
+ int i, pfix = dc->tb_flags & PFIX_FLAG;
+ TCGv addr, t0;
+
+ LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
+ dc->dst, dc->src, dc->postinc, dc->ir);
+
+ addr = tcg_temp_new();
+ t0 = tcg_temp_new();
+ crisv10_prepare_memaddr(dc, addr, 4);
+ tcg_gen_mov_tl(t0, addr);
+ for (i = dc->dst; i >= 0; i--) {
+ if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
+ gen_store_v10(dc, addr, t0, 4);
+ } else {
+ gen_store_v10(dc, addr, cpu_R[i], 4);
+ }
+ tcg_gen_addi_tl(addr, addr, 4);
+ }
+
+ if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
+ tcg_gen_mov_tl(cpu_R[dc->src], t0);
+ }
+
+ if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
+ tcg_gen_mov_tl(cpu_R[dc->src], addr);
+ }
+ tcg_temp_free(addr);
+ tcg_temp_free(t0);
+}
+
+static void dec10_movem_m_r(DisasContext *dc)
+{
+ int i, pfix = dc->tb_flags & PFIX_FLAG;
+ TCGv addr, t0;
+
+ LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
+ dc->src, dc->dst, dc->postinc, dc->ir);
+
+ addr = tcg_temp_new();
+ t0 = tcg_temp_new();
+ crisv10_prepare_memaddr(dc, addr, 4);
+ tcg_gen_mov_tl(t0, addr);
+ for (i = dc->dst; i >= 0; i--) {
+ gen_load(dc, cpu_R[i], addr, 4, 0);
+ tcg_gen_addi_tl(addr, addr, 4);
+ }
+
+ if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
+ tcg_gen_mov_tl(cpu_R[dc->src], t0);
+ }
+
+ if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
+ tcg_gen_mov_tl(cpu_R[dc->src], addr);
+ }
+ tcg_temp_free(addr);
+ tcg_temp_free(t0);
+}
+
+static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
+ int op, unsigned int size)
+{
+ int insn_len = 0;
+ int rd = dc->dst;
+ TCGv t[2];
+
+ cris_alu_m_alloc_temps(t);
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
+ cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
+ if (dc->dst == 15) {
+ tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch = 1;
+ return insn_len;
+ }
+
+ cris_alu_m_free_temps(t);
+
+ return insn_len;
+}
+
+static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
+ unsigned int size)
+{
+ int insn_len = 0;
+ int rd = dc->dst;
+ TCGv t;
+
+ t = tcg_temp_local_new();
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t);
+ cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
+ if (dc->dst == 15) {
+ tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch = 1;
+ return insn_len;
+ }
+
+ tcg_temp_free(t);
+ return insn_len;
+}
+
+static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
+{
+ unsigned int size = (dc->size & 1) ? 2 : 1;
+ unsigned int sx = !!(dc->size & 2);
+ int insn_len = 2;
+ int rd = dc->dst;
+ TCGv t;
+
+ LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
+
+ t = tcg_temp_new();
+
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_prep_move_m(env, dc, sx, size, t);
+ cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
+ if (dc->dst == 15) {
+ tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch = 1;
+ return insn_len;
+ }
+
+ tcg_temp_free(t);
+ return insn_len;
+}
+
+static int dec10_dip(CPUCRISState *env, DisasContext *dc)
+{
+ int insn_len = 2;
+ uint32_t imm;
+
+ LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
+ dc->pc, dc->opcode, dc->src, dc->dst);
+ if (dc->src == 15) {
+ imm = cpu_ldl_code(env, dc->pc + 2);
+ tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
+ if (dc->postinc)
+ insn_len += 4;
+ tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2);
+ } else {
+ gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
+ if (dc->postinc)
+ tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
+ }
+
+ cris_set_prefix(dc);
+ return insn_len;
+}
+
+static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
+{
+ int insn_len = 2;
+ int rd = dc->dst;
+
+ LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
+ dc->pc, dc->opcode, dc->src, dc->dst, size);
+
+ assert(dc->dst != 15);
+#if 0
+ /* 8bit embedded offset? */
+ if (!dc->postinc && (dc->ir & (1 << 11))) {
+ int simm = dc->ir & 0xff;
+
+ /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
+ /* sign extended. */
+ simm = (int8_t)simm;
+
+ tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
+
+ cris_set_prefix(dc);
+ return insn_len;
+ }
+#endif
+ /* Now the rest of the modes are truly indirect. */
+ insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
+ tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
+ cris_set_prefix(dc);
+ return insn_len;
+}
+
+static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
+{
+ unsigned int insn_len = 2;
+ unsigned int size = dec10_size(dc->size);
+ uint32_t imm;
+ int32_t simm;
+ TCGv t[2];
+
+ if (dc->size != 3) {
+ switch (dc->opcode) {
+ case CRISV10_IND_MOVE_M_R:
+ return dec10_ind_move_m_r(env, dc, size);
+ break;
+ case CRISV10_IND_MOVE_R_M:
+ return dec10_ind_move_r_m(dc, size);
+ break;
+ case CRISV10_IND_CMP:
+ LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
+ break;
+ case CRISV10_IND_TEST:
+ LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
+
+ cris_evaluate_flags(dc);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ cris_alu_m_alloc_temps(t);
+ insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
+ tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
+ cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
+ t[0], tcg_const_tl(0), size);
+ cris_alu_m_free_temps(t);
+ break;
+ case CRISV10_IND_ADD:
+ LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
+ break;
+ case CRISV10_IND_SUB:
+ LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
+ break;
+ case CRISV10_IND_BOUND:
+ LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_bound(env, dc, size);
+ break;
+ case CRISV10_IND_AND:
+ LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
+ break;
+ case CRISV10_IND_OR:
+ LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
+ break;
+ case CRISV10_IND_MOVX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
+ break;
+ case CRISV10_IND_ADDX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
+ break;
+ case CRISV10_IND_SUBX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
+ break;
+ case CRISV10_IND_CMPX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
+ break;
+ case CRISV10_IND_MUL:
+ /* This is a reg insn coded in the mem indir space. */
+ LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ dec10_reg_mul(dc, size, dc->ir & (1 << 10));
+ break;
+ case CRISV10_IND_BDAP_M:
+ insn_len = dec10_bdap_m(env, dc, size);
+ break;
+ default:
+ /*
+ * ADDC for v17:
+ *
+ * Instruction format: ADDC [Rs],Rd
+ *
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
+ * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)|
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
+ *
+ * Instruction format: ADDC [Rs+],Rd
+ *
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
+ * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)|
+ * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
+ */
+ if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
+ env->pregs[PR_VR] == 17) {
+ LOG_DIS("addc op=%d %d\n", dc->src, dc->dst);
+ cris_cc_mask(dc, CC_MASK_NZVC);
+ insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);
+ break;
+ }
+
+ LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
+ dc->pc, size, dc->opcode, dc->src, dc->dst);
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
+ break;
+ }
+ return insn_len;
+ }
+
+ switch (dc->opcode) {
+ case CRISV10_IND_MOVE_M_SPR:
+ insn_len = dec10_ind_move_m_pr(env, dc);
+ break;
+ case CRISV10_IND_MOVE_SPR_M:
+ insn_len = dec10_ind_move_pr_m(dc);
+ break;
+ case CRISV10_IND_JUMP_M:
+ if (dc->src == 15) {
+ LOG_DIS("jump.%d %d r%d r%d direct\n", size,
+ dc->opcode, dc->src, dc->dst);
+ imm = cpu_ldl_code(env, dc->pc + 2);
+ if (dc->mode == CRISV10_MODE_AUTOINC)
+ insn_len += size;
+
+ t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
+ dc->jmp_pc = imm;
+ cris_prepare_jmp(dc, JMP_DIRECT);
+ dc->delayed_branch--; /* v10 has no dslot here. */
+ } else {
+ if (dc->dst == 14) {
+ LOG_DIS("break %d\n", dc->src);
+ cris_evaluate_flags(dc);
+ tcg_gen_movi_tl(env_pc, dc->pc + 2);
+ t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2));
+ t_gen_raise_exception(EXCP_BREAK);
+ dc->is_jmp = DISAS_UPDATE;
+ return insn_len;
+ }
+ LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
+ dc->opcode, dc->src, dc->dst);
+ t[0] = tcg_temp_new();
+ t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
+ crisv10_prepare_memaddr(dc, t[0], size);
+ gen_load(dc, env_btarget, t[0], 4, 0);
+ insn_len += crisv10_post_memaddr(dc, size);
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch--; /* v10 has no dslot here. */
+ tcg_temp_free(t[0]);
+ }
+ break;
+
+ case CRISV10_IND_MOVEM_R_M:
+ LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
+ dc->pc, dc->opcode, dc->dst, dc->src);
+ dec10_movem_r_m(dc);
+ break;
+ case CRISV10_IND_MOVEM_M_R:
+ LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
+ dec10_movem_m_r(dc);
+ break;
+ case CRISV10_IND_JUMP_R:
+ LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
+ dc->pc, dc->opcode, dc->dst, dc->src);
+ tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
+ t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
+ cris_prepare_jmp(dc, JMP_INDIRECT);
+ dc->delayed_branch--; /* v10 has no dslot here. */
+ break;
+ case CRISV10_IND_MOVX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
+ break;
+ case CRISV10_IND_ADDX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
+ break;
+ case CRISV10_IND_SUBX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
+ break;
+ case CRISV10_IND_CMPX:
+ insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
+ break;
+ case CRISV10_IND_DIP:
+ insn_len = dec10_dip(env, dc);
+ break;
+ case CRISV10_IND_BCC_M:
+
+ cris_cc_mask(dc, 0);
+ simm = cpu_ldsw_code(env, dc->pc + 2);
+ simm += 4;
+
+ LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
+ cris_prepare_cc_branch(dc, simm, dc->cond);
+ insn_len = 4;
+ break;
+ default:
+ LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
+ break;
+ }
+
+ return insn_len;
+}
+
+static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
+{
+ unsigned int insn_len = 2;
+
+ /* Load a halfword onto the instruction register. */
+ dc->ir = cpu_lduw_code(env, dc->pc);
+
+ /* Now decode it. */
+ dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
+ dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
+ dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
+ dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
+ dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
+ dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
+
+ dc->clear_prefix = 1;
+
+ /* FIXME: What if this insn insn't 2 in length?? */
+ if (dc->src == 15 || dc->dst == 15)
+ tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
+
+ switch (dc->mode) {
+ case CRISV10_MODE_QIMMEDIATE:
+ insn_len = dec10_quick_imm(dc);
+ break;
+ case CRISV10_MODE_REG:
+ insn_len = dec10_reg(dc);
+ break;
+ case CRISV10_MODE_AUTOINC:
+ case CRISV10_MODE_INDIRECT:
+ insn_len = dec10_ind(env, dc);
+ break;
+ }
+
+ if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
+ dc->tb_flags &= ~PFIX_FLAG;
+ tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
+ if (dc->tb_flags != dc->tb->flags) {
+ dc->cpustate_changed = 1;
+ }
+ }
+
+ /* CRISv10 locks out interrupts on dslots. */
+ if (dc->delayed_branch == 2) {
+ cris_lock_irq(dc);
+ }
+ return insn_len;
+}
+
+void cris_initialize_crisv10_tcg(void)
+{
+ int i;
+
+ cc_x = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_x), "cc_x");
+ cc_src = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_src), "cc_src");
+ cc_dest = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_dest),
+ "cc_dest");
+ cc_result = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_result),
+ "cc_result");
+ cc_op = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_op), "cc_op");
+ cc_size = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_size),
+ "cc_size");
+ cc_mask = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, cc_mask),
+ "cc_mask");
+
+ env_pc = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, pc),
+ "pc");
+ env_btarget = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, btarget),
+ "btarget");
+ env_btaken = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, btaken),
+ "btaken");
+ for (i = 0; i < 16; i++) {
+ cpu_R[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, regs[i]),
+ regnames_v10[i]);
+ }
+ for (i = 0; i < 16; i++) {
+ cpu_PR[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUCRISState, pregs[i]),
+ pregnames_v10[i]);
+ }
+}
+++ /dev/null
-/*
- * CRISv10 emulation for qemu: main translation routines.
- *
- * Copyright (c) 2010 AXIS Communications AB
- * Written by Edgar E. Iglesias.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "crisv10-decode.h"
-
-static const char *regnames_v10[] =
-{
- "$r0", "$r1", "$r2", "$r3",
- "$r4", "$r5", "$r6", "$r7",
- "$r8", "$r9", "$r10", "$r11",
- "$r12", "$r13", "$sp", "$pc",
-};
-
-static const char *pregnames_v10[] =
-{
- "$bz", "$vr", "$p2", "$p3",
- "$wz", "$ccr", "$p6-prefix", "$mof",
- "$dz", "$ibr", "$irp", "$srp",
- "$bar", "$dccr", "$brp", "$usp",
-};
-
-/* We need this table to handle preg-moves with implicit width. */
-static int preg_sizes_v10[] = {
- 1, /* bz. */
- 1, /* vr. */
- 1, /* pid. */
- 1, /* srs. */
- 2, /* wz. */
- 2, 2, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
-};
-
-static inline int dec10_size(unsigned int size)
-{
- size++;
- if (size == 3)
- size++;
- return size;
-}
-
-static inline void cris_illegal_insn(DisasContext *dc)
-{
- qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc);
- t_gen_raise_exception(EXCP_BREAK);
-}
-
-static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
- unsigned int size, int mem_index)
-{
- TCGLabel *l1 = gen_new_label();
- TCGv taddr = tcg_temp_local_new();
- TCGv tval = tcg_temp_local_new();
- TCGv t1 = tcg_temp_local_new();
- dc->postinc = 0;
- cris_evaluate_flags(dc);
-
- tcg_gen_mov_tl(taddr, addr);
- tcg_gen_mov_tl(tval, val);
-
- /* Store only if F flag isn't set */
- tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- if (size == 1) {
- tcg_gen_qemu_st8(tval, taddr, mem_index);
- } else if (size == 2) {
- tcg_gen_qemu_st16(tval, taddr, mem_index);
- } else {
- tcg_gen_qemu_st32(tval, taddr, mem_index);
- }
- gen_set_label(l1);
- tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
- tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
- tcg_temp_free(t1);
- tcg_temp_free(tval);
- tcg_temp_free(taddr);
-}
-
-static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
- unsigned int size)
-{
- int mem_index = cpu_mmu_index(&dc->cpu->env, false);
-
- /* If we get a fault on a delayslot we must keep the jmp state in
- the cpu-state to be able to re-execute the jmp. */
- if (dc->delayed_branch == 1) {
- cris_store_direct_jmp(dc);
- }
-
- /* Conditional writes. We only support the kind were X is known
- at translation time. */
- if (dc->flagx_known && dc->flags_x) {
- gen_store_v10_conditional(dc, addr, val, size, mem_index);
- return;
- }
-
- if (size == 1) {
- tcg_gen_qemu_st8(val, addr, mem_index);
- } else if (size == 2) {
- tcg_gen_qemu_st16(val, addr, mem_index);
- } else {
- tcg_gen_qemu_st32(val, addr, mem_index);
- }
-}
-
-
-/* Prefix flag and register are used to handle the more complex
- addressing modes. */
-static void cris_set_prefix(DisasContext *dc)
-{
- dc->clear_prefix = 0;
- dc->tb_flags |= PFIX_FLAG;
- tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG);
-
- /* prefix insns don't clear the x flag. */
- dc->clear_x = 0;
- cris_lock_irq(dc);
-}
-
-static void crisv10_prepare_memaddr(DisasContext *dc,
- TCGv addr, unsigned int size)
-{
- if (dc->tb_flags & PFIX_FLAG) {
- tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]);
- } else {
- tcg_gen_mov_tl(addr, cpu_R[dc->src]);
- }
-}
-
-static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
-{
- unsigned int insn_len = 0;
-
- if (dc->tb_flags & PFIX_FLAG) {
- if (dc->mode == CRISV10_MODE_AUTOINC) {
- tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
- }
- } else {
- if (dc->mode == CRISV10_MODE_AUTOINC) {
- if (dc->src == 15) {
- insn_len += size & ~1;
- } else {
- tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
- }
- }
- }
- return insn_len;
-}
-
-static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
- int s_ext, int memsize, TCGv dst)
-{
- unsigned int rs;
- uint32_t imm;
- int is_imm;
- int insn_len = 0;
-
- rs = dc->src;
- is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
- LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
- rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
-
- /* Load [$rs] onto T1. */
- if (is_imm) {
- if (memsize != 4) {
- if (s_ext) {
- if (memsize == 1)
- imm = cpu_ldsb_code(env, dc->pc + 2);
- else
- imm = cpu_ldsw_code(env, dc->pc + 2);
- } else {
- if (memsize == 1)
- imm = cpu_ldub_code(env, dc->pc + 2);
- else
- imm = cpu_lduw_code(env, dc->pc + 2);
- }
- } else
- imm = cpu_ldl_code(env, dc->pc + 2);
-
- tcg_gen_movi_tl(dst, imm);
-
- if (dc->mode == CRISV10_MODE_AUTOINC) {
- insn_len += memsize;
- if (memsize == 1)
- insn_len++;
- tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len);
- }
- } else {
- TCGv addr;
-
- addr = tcg_temp_new();
- cris_flush_cc_state(dc);
- crisv10_prepare_memaddr(dc, addr, memsize);
- gen_load(dc, dst, addr, memsize, 0);
- if (s_ext)
- t_gen_sext(dst, dst, memsize);
- else
- t_gen_zext(dst, dst, memsize);
- insn_len += crisv10_post_memaddr(dc, memsize);
- tcg_temp_free(addr);
- }
-
- if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
- dc->dst = dc->src;
- }
- return insn_len;
-}
-
-static unsigned int dec10_quick_imm(DisasContext *dc)
-{
- int32_t imm, simm;
- int op;
-
- /* sign extend. */
- imm = dc->ir & ((1 << 6) - 1);
- simm = (int8_t) (imm << 2);
- simm >>= 2;
- switch (dc->opcode) {
- case CRISV10_QIMM_BDAP_R0:
- case CRISV10_QIMM_BDAP_R1:
- case CRISV10_QIMM_BDAP_R2:
- case CRISV10_QIMM_BDAP_R3:
- simm = (int8_t)dc->ir;
- LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
- LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
- dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
- cris_set_prefix(dc);
- if (dc->dst == 15) {
- tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
- } else {
- tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
- }
- break;
-
- case CRISV10_QIMM_MOVEQ:
- LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(simm), 4);
- break;
- case CRISV10_QIMM_CMPQ:
- LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(simm), 4);
- break;
- case CRISV10_QIMM_ADDQ:
- LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(imm), 4);
- break;
- case CRISV10_QIMM_ANDQ:
- LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(simm), 4);
- break;
- case CRISV10_QIMM_ASHQ:
- LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- op = imm & (1 << 5);
- imm &= 0x1f;
- if (op) {
- cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(imm), 4);
- } else {
- /* BTST */
- cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
- tcg_const_tl(imm), cpu_PR[PR_CCS]);
- }
- break;
- case CRISV10_QIMM_LSHQ:
- LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
-
- op = CC_OP_LSL;
- if (imm & (1 << 5)) {
- op = CC_OP_LSR;
- }
- imm &= 0x1f;
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, op, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(imm), 4);
- break;
- case CRISV10_QIMM_SUBQ:
- LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(imm), 4);
- break;
- case CRISV10_QIMM_ORQ:
- LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
- cpu_R[dc->dst], tcg_const_tl(simm), 4);
- break;
-
- case CRISV10_QIMM_BCC_R0:
- case CRISV10_QIMM_BCC_R1:
- case CRISV10_QIMM_BCC_R2:
- case CRISV10_QIMM_BCC_R3:
- imm = dc->ir & 0xff;
- /* bit 0 is a sign bit. */
- if (imm & 1) {
- imm |= 0xffffff00; /* sign extend. */
- imm &= ~1; /* get rid of the sign bit. */
- }
- imm += 2;
- LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
-
- cris_cc_mask(dc, 0);
- cris_prepare_cc_branch(dc, imm, dc->cond);
- break;
-
- default:
- LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
- dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
- break;
- }
- return 2;
-}
-
-static unsigned int dec10_setclrf(DisasContext *dc)
-{
- uint32_t flags;
- unsigned int set = ~dc->opcode & 1;
-
- flags = EXTRACT_FIELD(dc->ir, 0, 3)
- | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
- LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
-
-
- if (flags & X_FLAG) {
- dc->flagx_known = 1;
- if (set)
- dc->flags_x = X_FLAG;
- else
- dc->flags_x = 0;
- }
-
- cris_evaluate_flags (dc);
- cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- cris_update_cc_x(dc);
- tcg_gen_movi_tl(cc_op, dc->cc_op);
-
- if (set) {
- tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
- } else {
- tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
- ~(flags|F_FLAG_V10|P_FLAG_V10));
- }
-
- dc->flags_uptodate = 1;
- dc->clear_x = 0;
- cris_lock_irq(dc);
- return 2;
-}
-
-static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
- TCGv dd, TCGv ds, TCGv sd, TCGv ss)
-{
- if (sext) {
- t_gen_sext(dd, sd, size);
- t_gen_sext(ds, ss, size);
- } else {
- t_gen_zext(dd, sd, size);
- t_gen_zext(ds, ss, size);
- }
-}
-
-static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
-{
- TCGv t[2];
-
- t[0] = tcg_temp_new();
- t[1] = tcg_temp_new();
- dec10_reg_prep_sext(dc, size, sext,
- t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
-
- if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
- tcg_gen_andi_tl(t[1], t[1], 63);
- }
-
- assert(dc->dst != 15);
- cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
- tcg_temp_free(t[0]);
- tcg_temp_free(t[1]);
-}
-
-static void dec10_reg_bound(DisasContext *dc, int size)
-{
- TCGv t;
-
- t = tcg_temp_local_new();
- t_gen_zext(t, cpu_R[dc->src], size);
- cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
- tcg_temp_free(t);
-}
-
-static void dec10_reg_mul(DisasContext *dc, int size, int sext)
-{
- int op = sext ? CC_OP_MULS : CC_OP_MULU;
- TCGv t[2];
-
- t[0] = tcg_temp_new();
- t[1] = tcg_temp_new();
- dec10_reg_prep_sext(dc, size, sext,
- t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
-
- cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
-
- tcg_temp_free(t[0]);
- tcg_temp_free(t[1]);
-}
-
-
-static void dec10_reg_movs(DisasContext *dc)
-{
- int size = (dc->size & 1) + 1;
- TCGv t;
-
- LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
-
- t = tcg_temp_new();
- if (dc->ir & 32)
- t_gen_sext(t, cpu_R[dc->src], size);
- else
- t_gen_zext(t, cpu_R[dc->src], size);
-
- cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
- tcg_temp_free(t);
-}
-
-static void dec10_reg_alux(DisasContext *dc, int op)
-{
- int size = (dc->size & 1) + 1;
- TCGv t;
-
- LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
-
- t = tcg_temp_new();
- if (dc->ir & 32)
- t_gen_sext(t, cpu_R[dc->src], size);
- else
- t_gen_zext(t, cpu_R[dc->src], size);
-
- cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
- tcg_temp_free(t);
-}
-
-static void dec10_reg_mov_pr(DisasContext *dc)
-{
- LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
- cris_lock_irq(dc);
- if (dc->src == 15) {
- tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- return;
- }
- if (dc->dst == PR_CCS) {
- cris_evaluate_flags(dc);
- }
- cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
- cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
-}
-
-static void dec10_reg_abs(DisasContext *dc)
-{
- TCGv t0;
-
- LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
-
- assert(dc->dst != 15);
- t0 = tcg_temp_new();
- tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
- tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
- tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
-
- cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
- tcg_temp_free(t0);
-}
-
-static void dec10_reg_swap(DisasContext *dc)
-{
- TCGv t0;
-
- LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- t0 = tcg_temp_new();
- tcg_gen_mov_tl(t0, cpu_R[dc->src]);
- if (dc->dst & 8)
- tcg_gen_not_tl(t0, t0);
- if (dc->dst & 4)
- t_gen_swapw(t0, t0);
- if (dc->dst & 2)
- t_gen_swapb(t0, t0);
- if (dc->dst & 1)
- t_gen_swapr(t0, t0);
- cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
- tcg_temp_free(t0);
-}
-
-static void dec10_reg_scc(DisasContext *dc)
-{
- int cond = dc->dst;
-
- LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
-
- gen_tst_cc(dc, cpu_R[dc->src], cond);
- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0);
-
- cris_cc_mask(dc, 0);
-}
-
-static unsigned int dec10_reg(DisasContext *dc)
-{
- TCGv t;
- unsigned int insn_len = 2;
- unsigned int size = dec10_size(dc->size);
- unsigned int tmp;
-
- if (dc->size != 3) {
- switch (dc->opcode) {
- case CRISV10_REG_MOVE_R:
- LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
- if (dc->dst == 15) {
- tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch = 1;
- }
- break;
- case CRISV10_REG_MOVX:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_movs(dc);
- break;
- case CRISV10_REG_ADDX:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alux(dc, CC_OP_ADD);
- break;
- case CRISV10_REG_SUBX:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alux(dc, CC_OP_SUB);
- break;
- case CRISV10_REG_ADD:
- LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_ADD, size, 0);
- break;
- case CRISV10_REG_SUB:
- LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_SUB, size, 0);
- break;
- case CRISV10_REG_CMP:
- LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_CMP, size, 0);
- break;
- case CRISV10_REG_BOUND:
- LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_bound(dc, size);
- break;
- case CRISV10_REG_AND:
- LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_AND, size, 0);
- break;
- case CRISV10_REG_ADDI:
- if (dc->src == 15) {
- /* nop. */
- return 2;
- }
- t = tcg_temp_new();
- LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
- tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
- tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
- tcg_temp_free(t);
- break;
- case CRISV10_REG_LSL:
- LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_LSL, size, 0);
- break;
- case CRISV10_REG_LSR:
- LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_LSR, size, 0);
- break;
- case CRISV10_REG_ASR:
- LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_ASR, size, 1);
- break;
- case CRISV10_REG_OR:
- LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_OR, size, 0);
- break;
- case CRISV10_REG_NEG:
- LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_NEG, size, 0);
- break;
- case CRISV10_REG_BIAP:
- LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
- dc->opcode, dc->src, dc->dst, size);
- switch (size) {
- case 4: tmp = 2; break;
- case 2: tmp = 1; break;
- case 1: tmp = 0; break;
- default:
- cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
- break;
- }
-
- t = tcg_temp_new();
- tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
- if (dc->src == 15) {
- tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
- } else {
- tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
- }
- tcg_temp_free(t);
- cris_set_prefix(dc);
- break;
-
- default:
- LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
- dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(dc->cpu), "Unhandled opcode");
- break;
- }
- } else {
- switch (dc->opcode) {
- case CRISV10_REG_MOVX:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_movs(dc);
- break;
- case CRISV10_REG_ADDX:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alux(dc, CC_OP_ADD);
- break;
- case CRISV10_REG_SUBX:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alux(dc, CC_OP_SUB);
- break;
- case CRISV10_REG_MOVE_SPR_R:
- cris_evaluate_flags(dc);
- cris_cc_mask(dc, 0);
- dec10_reg_mov_pr(dc);
- break;
- case CRISV10_REG_MOVE_R_SPR:
- LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
- cris_evaluate_flags(dc);
- if (dc->src != 11) /* fast for srp. */
- dc->cpustate_changed = 1;
- t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
- break;
- case CRISV10_REG_SETF:
- case CRISV10_REG_CLEARF:
- dec10_setclrf(dc);
- break;
- case CRISV10_REG_SWAP:
- dec10_reg_swap(dc);
- break;
- case CRISV10_REG_ABS:
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_abs(dc);
- break;
- case CRISV10_REG_LZ:
- LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
- break;
- case CRISV10_REG_XOR:
- LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
- break;
- case CRISV10_REG_BTST:
- LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
- cpu_R[dc->src], cpu_PR[PR_CCS]);
- break;
- case CRISV10_REG_DSTEP:
- LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
- cpu_R[dc->dst], cpu_R[dc->src], 4);
- break;
- case CRISV10_REG_MSTEP:
- LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
- cris_evaluate_flags(dc);
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
- cpu_R[dc->dst], cpu_R[dc->src], 4);
- break;
- case CRISV10_REG_SCC:
- dec10_reg_scc(dc);
- break;
- default:
- LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
- dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(dc->cpu), "Unhandled opcode");
- break;
- }
- }
- return insn_len;
-}
-
-static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
- unsigned int size)
-{
- unsigned int insn_len = 2;
- TCGv t;
-
- LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
- size, dc->src, dc->dst);
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- t = tcg_temp_new();
- insn_len += dec10_prep_move_m(env, dc, 0, size, t);
- cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
- if (dc->dst == 15) {
- tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch = 1;
- return insn_len;
- }
-
- tcg_temp_free(t);
- return insn_len;
-}
-
-static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
-{
- unsigned int insn_len = 2;
- TCGv addr;
-
- LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
- addr = tcg_temp_new();
- crisv10_prepare_memaddr(dc, addr, size);
- gen_store_v10(dc, addr, cpu_R[dc->dst], size);
- insn_len += crisv10_post_memaddr(dc, size);
-
- return insn_len;
-}
-
-static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
-{
- unsigned int insn_len = 2, rd = dc->dst;
- TCGv t, addr;
-
- LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
- cris_lock_irq(dc);
-
- addr = tcg_temp_new();
- t = tcg_temp_new();
- insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
- if (rd == 15) {
- tcg_gen_mov_tl(env_btarget, t);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch = 1;
- return insn_len;
- }
-
- tcg_gen_mov_tl(cpu_PR[rd], t);
- dc->cpustate_changed = 1;
- tcg_temp_free(addr);
- tcg_temp_free(t);
- return insn_len;
-}
-
-static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
-{
- unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
- TCGv addr, t0;
-
- LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
-
- addr = tcg_temp_new();
- crisv10_prepare_memaddr(dc, addr, size);
- if (dc->dst == PR_CCS) {
- t0 = tcg_temp_new();
- cris_evaluate_flags(dc);
- tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
- gen_store_v10(dc, addr, t0, size);
- tcg_temp_free(t0);
- } else {
- gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
- }
- t0 = tcg_temp_new();
- insn_len += crisv10_post_memaddr(dc, size);
- cris_lock_irq(dc);
-
- return insn_len;
-}
-
-static void dec10_movem_r_m(DisasContext *dc)
-{
- int i, pfix = dc->tb_flags & PFIX_FLAG;
- TCGv addr, t0;
-
- LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
- dc->dst, dc->src, dc->postinc, dc->ir);
-
- addr = tcg_temp_new();
- t0 = tcg_temp_new();
- crisv10_prepare_memaddr(dc, addr, 4);
- tcg_gen_mov_tl(t0, addr);
- for (i = dc->dst; i >= 0; i--) {
- if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
- gen_store_v10(dc, addr, t0, 4);
- } else {
- gen_store_v10(dc, addr, cpu_R[i], 4);
- }
- tcg_gen_addi_tl(addr, addr, 4);
- }
-
- if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
- tcg_gen_mov_tl(cpu_R[dc->src], t0);
- }
-
- if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
- tcg_gen_mov_tl(cpu_R[dc->src], addr);
- }
- tcg_temp_free(addr);
- tcg_temp_free(t0);
-}
-
-static void dec10_movem_m_r(DisasContext *dc)
-{
- int i, pfix = dc->tb_flags & PFIX_FLAG;
- TCGv addr, t0;
-
- LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
- dc->src, dc->dst, dc->postinc, dc->ir);
-
- addr = tcg_temp_new();
- t0 = tcg_temp_new();
- crisv10_prepare_memaddr(dc, addr, 4);
- tcg_gen_mov_tl(t0, addr);
- for (i = dc->dst; i >= 0; i--) {
- gen_load(dc, cpu_R[i], addr, 4, 0);
- tcg_gen_addi_tl(addr, addr, 4);
- }
-
- if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
- tcg_gen_mov_tl(cpu_R[dc->src], t0);
- }
-
- if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
- tcg_gen_mov_tl(cpu_R[dc->src], addr);
- }
- tcg_temp_free(addr);
- tcg_temp_free(t0);
-}
-
-static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
- int op, unsigned int size)
-{
- int insn_len = 0;
- int rd = dc->dst;
- TCGv t[2];
-
- cris_alu_m_alloc_temps(t);
- insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
- cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
- if (dc->dst == 15) {
- tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch = 1;
- return insn_len;
- }
-
- cris_alu_m_free_temps(t);
-
- return insn_len;
-}
-
-static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
- unsigned int size)
-{
- int insn_len = 0;
- int rd = dc->dst;
- TCGv t;
-
- t = tcg_temp_local_new();
- insn_len += dec10_prep_move_m(env, dc, 0, size, t);
- cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
- if (dc->dst == 15) {
- tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch = 1;
- return insn_len;
- }
-
- tcg_temp_free(t);
- return insn_len;
-}
-
-static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
-{
- unsigned int size = (dc->size & 1) ? 2 : 1;
- unsigned int sx = !!(dc->size & 2);
- int insn_len = 2;
- int rd = dc->dst;
- TCGv t;
-
- LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
-
- t = tcg_temp_new();
-
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_prep_move_m(env, dc, sx, size, t);
- cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
- if (dc->dst == 15) {
- tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch = 1;
- return insn_len;
- }
-
- tcg_temp_free(t);
- return insn_len;
-}
-
-static int dec10_dip(CPUCRISState *env, DisasContext *dc)
-{
- int insn_len = 2;
- uint32_t imm;
-
- LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
- dc->pc, dc->opcode, dc->src, dc->dst);
- if (dc->src == 15) {
- imm = cpu_ldl_code(env, dc->pc + 2);
- tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
- if (dc->postinc)
- insn_len += 4;
- tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2);
- } else {
- gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
- if (dc->postinc)
- tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
- }
-
- cris_set_prefix(dc);
- return insn_len;
-}
-
-static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
-{
- int insn_len = 2;
- int rd = dc->dst;
-
- LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
- dc->pc, dc->opcode, dc->src, dc->dst, size);
-
- assert(dc->dst != 15);
-#if 0
- /* 8bit embedded offset? */
- if (!dc->postinc && (dc->ir & (1 << 11))) {
- int simm = dc->ir & 0xff;
-
- /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
- /* sign extended. */
- simm = (int8_t)simm;
-
- tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
-
- cris_set_prefix(dc);
- return insn_len;
- }
-#endif
- /* Now the rest of the modes are truly indirect. */
- insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
- tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
- cris_set_prefix(dc);
- return insn_len;
-}
-
-static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
-{
- unsigned int insn_len = 2;
- unsigned int size = dec10_size(dc->size);
- uint32_t imm;
- int32_t simm;
- TCGv t[2];
-
- if (dc->size != 3) {
- switch (dc->opcode) {
- case CRISV10_IND_MOVE_M_R:
- return dec10_ind_move_m_r(env, dc, size);
- break;
- case CRISV10_IND_MOVE_R_M:
- return dec10_ind_move_r_m(dc, size);
- break;
- case CRISV10_IND_CMP:
- LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
- break;
- case CRISV10_IND_TEST:
- LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
-
- cris_evaluate_flags(dc);
- cris_cc_mask(dc, CC_MASK_NZVC);
- cris_alu_m_alloc_temps(t);
- insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
- tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
- cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
- t[0], tcg_const_tl(0), size);
- cris_alu_m_free_temps(t);
- break;
- case CRISV10_IND_ADD:
- LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
- break;
- case CRISV10_IND_SUB:
- LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
- break;
- case CRISV10_IND_BOUND:
- LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_bound(env, dc, size);
- break;
- case CRISV10_IND_AND:
- LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
- break;
- case CRISV10_IND_OR:
- LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
- break;
- case CRISV10_IND_MOVX:
- insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
- break;
- case CRISV10_IND_ADDX:
- insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
- break;
- case CRISV10_IND_SUBX:
- insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
- break;
- case CRISV10_IND_CMPX:
- insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
- break;
- case CRISV10_IND_MUL:
- /* This is a reg insn coded in the mem indir space. */
- LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
- cris_cc_mask(dc, CC_MASK_NZVC);
- dec10_reg_mul(dc, size, dc->ir & (1 << 10));
- break;
- case CRISV10_IND_BDAP_M:
- insn_len = dec10_bdap_m(env, dc, size);
- break;
- default:
- /*
- * ADDC for v17:
- *
- * Instruction format: ADDC [Rs],Rd
- *
- * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
- * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)|
- * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
- *
- * Instruction format: ADDC [Rs+],Rd
- *
- * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
- * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)|
- * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+
- */
- if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
- env->pregs[PR_VR] == 17) {
- LOG_DIS("addc op=%d %d\n", dc->src, dc->dst);
- cris_cc_mask(dc, CC_MASK_NZVC);
- insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);
- break;
- }
-
- LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
- dc->pc, size, dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(dc->cpu), "Unhandled opcode");
- break;
- }
- return insn_len;
- }
-
- switch (dc->opcode) {
- case CRISV10_IND_MOVE_M_SPR:
- insn_len = dec10_ind_move_m_pr(env, dc);
- break;
- case CRISV10_IND_MOVE_SPR_M:
- insn_len = dec10_ind_move_pr_m(dc);
- break;
- case CRISV10_IND_JUMP_M:
- if (dc->src == 15) {
- LOG_DIS("jump.%d %d r%d r%d direct\n", size,
- dc->opcode, dc->src, dc->dst);
- imm = cpu_ldl_code(env, dc->pc + 2);
- if (dc->mode == CRISV10_MODE_AUTOINC)
- insn_len += size;
-
- t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
- dc->jmp_pc = imm;
- cris_prepare_jmp(dc, JMP_DIRECT);
- dc->delayed_branch--; /* v10 has no dslot here. */
- } else {
- if (dc->dst == 14) {
- LOG_DIS("break %d\n", dc->src);
- cris_evaluate_flags(dc);
- tcg_gen_movi_tl(env_pc, dc->pc + 2);
- t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2));
- t_gen_raise_exception(EXCP_BREAK);
- dc->is_jmp = DISAS_UPDATE;
- return insn_len;
- }
- LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
- dc->opcode, dc->src, dc->dst);
- t[0] = tcg_temp_new();
- t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
- crisv10_prepare_memaddr(dc, t[0], size);
- gen_load(dc, env_btarget, t[0], 4, 0);
- insn_len += crisv10_post_memaddr(dc, size);
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch--; /* v10 has no dslot here. */
- tcg_temp_free(t[0]);
- }
- break;
-
- case CRISV10_IND_MOVEM_R_M:
- LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
- dc->pc, dc->opcode, dc->dst, dc->src);
- dec10_movem_r_m(dc);
- break;
- case CRISV10_IND_MOVEM_M_R:
- LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
- dec10_movem_m_r(dc);
- break;
- case CRISV10_IND_JUMP_R:
- LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
- dc->pc, dc->opcode, dc->dst, dc->src);
- tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
- t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
- cris_prepare_jmp(dc, JMP_INDIRECT);
- dc->delayed_branch--; /* v10 has no dslot here. */
- break;
- case CRISV10_IND_MOVX:
- insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
- break;
- case CRISV10_IND_ADDX:
- insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
- break;
- case CRISV10_IND_SUBX:
- insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
- break;
- case CRISV10_IND_CMPX:
- insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
- break;
- case CRISV10_IND_DIP:
- insn_len = dec10_dip(env, dc);
- break;
- case CRISV10_IND_BCC_M:
-
- cris_cc_mask(dc, 0);
- simm = cpu_ldsw_code(env, dc->pc + 2);
- simm += 4;
-
- LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
- cris_prepare_cc_branch(dc, simm, dc->cond);
- insn_len = 4;
- break;
- default:
- LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
- cpu_abort(CPU(dc->cpu), "Unhandled opcode");
- break;
- }
-
- return insn_len;
-}
-
-static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
-{
- unsigned int insn_len = 2;
-
- /* Load a halfword onto the instruction register. */
- dc->ir = cpu_lduw_code(env, dc->pc);
-
- /* Now decode it. */
- dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
- dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
- dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
- dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
- dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
- dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
-
- dc->clear_prefix = 1;
-
- /* FIXME: What if this insn insn't 2 in length?? */
- if (dc->src == 15 || dc->dst == 15)
- tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
-
- switch (dc->mode) {
- case CRISV10_MODE_QIMMEDIATE:
- insn_len = dec10_quick_imm(dc);
- break;
- case CRISV10_MODE_REG:
- insn_len = dec10_reg(dc);
- break;
- case CRISV10_MODE_AUTOINC:
- case CRISV10_MODE_INDIRECT:
- insn_len = dec10_ind(env, dc);
- break;
- }
-
- if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
- dc->tb_flags &= ~PFIX_FLAG;
- tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
- if (dc->tb_flags != dc->tb->flags) {
- dc->cpustate_changed = 1;
- }
- }
-
- /* CRISv10 locks out interrupts on dslots. */
- if (dc->delayed_branch == 2) {
- cris_lock_irq(dc);
- }
- return insn_len;
-}
-
-void cris_initialize_crisv10_tcg(void)
-{
- int i;
-
- cc_x = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_x), "cc_x");
- cc_src = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_src), "cc_src");
- cc_dest = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_dest),
- "cc_dest");
- cc_result = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_result),
- "cc_result");
- cc_op = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_op), "cc_op");
- cc_size = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_size),
- "cc_size");
- cc_mask = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, cc_mask),
- "cc_mask");
-
- env_pc = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, pc),
- "pc");
- env_btarget = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, btarget),
- "btarget");
- env_btaken = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, btaken),
- "btaken");
- for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, regs[i]),
- regnames_v10[i]);
- }
- for (i = 0; i < 16; i++) {
- cpu_PR[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUCRISState, pregs[i]),
- pregnames_v10[i]);
- }
-}
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
-target/hppa/decode.inc.c: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
+target/hppa/decode.c.inc: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
-target/hppa/translate.o: target/hppa/decode.inc.c
+target/hppa/translate.o: target/hppa/decode.c.inc
/* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
/* We are not using a goto_tb (for whatever reason), but have updated
the iaq (for whatever reason), so don't do it again on exit. */
#endif
}
-#include "translate_init.inc.c"
+#include "translate_init.c.inc"
void cpu_mips_realize_env(CPUMIPSState *env)
{
--- /dev/null
+/*
+ * MIPS emulation for qemu: CPU initialisation routines.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2007 Herve Poussineau
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* CPU / CPU family specific config register values. */
+
+/* Have config1, uncached coherency */
+#define MIPS_CONFIG0 \
+ ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
+
+/* Have config2, no coprocessor2 attached, no MDMX support attached,
+ no performance counters, watch registers present,
+ no code compression, EJTAG present, no FPU */
+#define MIPS_CONFIG1 \
+((1U << CP0C1_M) | \
+ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
+ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
+ (0 << CP0C1_FP))
+
+/* Have config3, no tertiary/secondary caches implemented */
+#define MIPS_CONFIG2 \
+((1U << CP0C2_M))
+
+/* No config4, no DSP ASE, no large physaddr (PABITS),
+ no external interrupt controller, no vectored interrupts,
+ no 1kb pages, no SmartMIPS ASE, no trace logic */
+#define MIPS_CONFIG3 \
+((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
+ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
+ (0 << CP0C3_SM) | (0 << CP0C3_TL))
+
+#define MIPS_CONFIG4 \
+((0 << CP0C4_M))
+
+#define MIPS_CONFIG5 \
+((0 << CP0C5_M))
+
+/*****************************************************************************/
+/* MIPS CPU definitions */
+const mips_def_t mips_defs[] =
+{
+ {
+ .name = "4Kc",
+ .CP0_PRid = 0x00018000,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "4Km",
+ .CP0_PRid = 0x00018300,
+ /* Config1 implemented, fixed mapping MMU,
+ no virtual icache, uncached coherency. */
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "4KEcR1",
+ .CP0_PRid = 0x00018400,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "4KEmR1",
+ .CP0_PRid = 0x00018500,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "4KEc",
+ .CP0_PRid = 0x00019000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "4KEm",
+ .CP0_PRid = 0x00019100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "24Kc",
+ .CP0_PRid = 0x00019300,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x1278FF1F,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "24KEc",
+ .CP0_PRid = 0x00019600,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* we have a DSP, but no FPU */
+ .CP0_Status_rw_bitmask = 0x1378FF1F,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "24Kf",
+ .CP0_PRid = 0x00019300,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x3678FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "34Kf",
+ .CP0_PRid = 0x00019500,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
+ (1 << CP0C3_DSPP),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
+ (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
+ (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
+ (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
+ (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
+ (0xff << CP0TCSt_TASID),
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
+ .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
+ (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
+ .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
+ (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
+ .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
+ (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
+ .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
+ (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
+ .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
+ (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "74Kf",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
+ (1 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "M14K",
+ .CP0_PRid = 0x00019b00,
+ /* Config1 implemented, fixed mapping MMU,
+ no virtual icache, uncached coherency. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
+ (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1,
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "M14Kc",
+ /* This is the TLB-based MMU core. */
+ .CP0_PRid = 0x00019c00,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ /* FIXME:
+ * Config3: VZ, CTXTC, CDMM, TL
+ * Config4: MMUExtDef
+ * Config5: MRP
+ * FIR(FCR0): Has2008
+ * */
+ .name = "P5600",
+ .CP0_PRid = 0x0001A800,
+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_FP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
+ (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
+ (0x1c << CP0C4_KScrExist),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
+ (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3C68FF1F,
+ .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
+ (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+ .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
+ (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 32,
+ .PABITS = 40,
+ .insn_flags = CPU_MIPS32R5 | ASE_MSA,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ /* A generic CPU supporting MIPS32 Release 6 ISA.
+ FIXME: Support IEEE 754-2008 FP.
+ Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r6-generic",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
+ (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1U << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
+ (3 << CP0C4_IE) | (1U << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
+ (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3058FF1F,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = 0,
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .CP1_fcr31_rw_bitmask = 0x0103FFFF,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "I7200",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
+ (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
+ (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
+ (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
+ (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
+ (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
+ (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
+ (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
+ (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
+ (2 << CP0C4_IE) | (1U << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
+ (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3158FF1F,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = 0,
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
+ ASE_MT,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+#if defined(TARGET_MIPS64)
+ {
+ .name = "R4000",
+ .CP0_PRid = 0x00000400,
+ /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
+ .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
+ /* Note: Config1 is only used internally, the R4000 has only Config0. */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3678FFFF,
+ /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0x0183FFFF,
+ .SEGBITS = 40,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS3,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "VR5432",
+ .CP0_PRid = 0x00005400,
+ /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
+ .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3678FFFF,
+ /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 40,
+ .PABITS = 32,
+ .insn_flags = CPU_VR54XX,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "5Kc",
+ .CP0_PRid = 0x00018100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "5Kf",
+ .CP0_PRid = 0x00018100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x36F8FFFF,
+ /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "20Kc",
+ /* We emulate a later version of the 20Kc, earlier ones had a broken
+ WAIT instruction. */
+ .CP0_PRid = 0x000182a0,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 1,
+ .CP0_Status_rw_bitmask = 0x36FBFFFF,
+ /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
+ (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 40,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ /* A generic CPU providing MIPS64 Release 2 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "MIPS64R2-generic",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x36FBFFFF,
+ .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "5KEc",
+ .CP0_PRid = 0x00018900,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64R2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "5KEf",
+ .CP0_PRid = 0x00018900,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x36F8FFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64R2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "I6400",
+ .CP0_PRid = 0x1A900,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
+ (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
+ (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x30D8FFFF,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
+ .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .CP1_fcr31_rw_bitmask = 0x0103FFFF,
+ .MSAIR = 0x03 << MSAIR_ProcID,
+ .SEGBITS = 48,
+ .PABITS = 48,
+ .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "I6500",
+ .CP0_PRid = 0x1B000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
+ (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
+ (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 64,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x30D8FFFF,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
+ .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .CP1_fcr31_rw_bitmask = 0x0103FFFF,
+ .MSAIR = 0x03 << MSAIR_ProcID,
+ .SEGBITS = 48,
+ .PABITS = 48,
+ .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-2E",
+ .CP0_PRid = 0x6302,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
+ (0x1<<5) | (0x1<<4) | (0x1<<1),
+ /* Note: Config1 is only used internally,
+ Loongson-2E has only Config0. */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x35D0FFFF,
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 40,
+ .PABITS = 40,
+ .insn_flags = CPU_LOONGSON2E,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-2F",
+ .CP0_PRid = 0x6303,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
+ (0x1<<5) | (0x1<<4) | (0x1<<1),
+ /* Note: Config1 is only used internally,
+ Loongson-2F has only Config0. */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 40,
+ .PABITS = 40,
+ .insn_flags = CPU_LOONGSON2F,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-3A1000",
+ .CP0_PRid = 0x6305,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
+ (3 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x74D8FFFF,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
+ (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
+ (0x1 << FCR0_D) | (0x1 << FCR0_S),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 48,
+ .insn_flags = CPU_LOONGSON3A,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-3A4000",
+ .CP0_PRid = 0x14C000,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
+ (15 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
+ (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
+ .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
+ (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
+ (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
+ .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
+ (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
+ (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
+ (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
+ (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
+ (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
+ (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
+ (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
+ (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
+ (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
+ (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
+ (1 << CP0C6_DATAPREF),
+ .CP0_Config7 = 0,
+ .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
+ (1 << CP0C7_VFPUCGEN),
+ .CP0_LLAddr_rw_bitmask = 1,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x7DDBFFFF,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
+ (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
+ (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
+ (0x1 << FCR0_D) | (0x1 << FCR0_S),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 48,
+ .PABITS = 48,
+ .insn_flags = CPU_LOONGSON3A,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ /* A generic CPU providing MIPS64 DSP R2 ASE features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips64dspr2",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
+ (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x37FBFFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+
+#endif
+};
+const int mips_defs_number = ARRAY_SIZE(mips_defs);
+
+void mips_cpu_list(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
+ qemu_printf("MIPS '%s'\n", mips_defs[i].name);
+ }
+}
+
+#ifndef CONFIG_USER_ONLY
+static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &no_mmu_map_address;
+}
+
+static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &fixed_mmu_map_address;
+}
+
+static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+ env->tlb->map_address = &r4k_map_address;
+ env->tlb->helper_tlbwi = r4k_helper_tlbwi;
+ env->tlb->helper_tlbwr = r4k_helper_tlbwr;
+ env->tlb->helper_tlbp = r4k_helper_tlbp;
+ env->tlb->helper_tlbr = r4k_helper_tlbr;
+ env->tlb->helper_tlbinv = r4k_helper_tlbinv;
+ env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
+}
+
+static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+{
+ env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
+
+ switch (def->mmu_type) {
+ case MMU_TYPE_NONE:
+ no_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R4000:
+ r4k_mmu_init(env, def);
+ break;
+ case MMU_TYPE_FMT:
+ fixed_mmu_init(env, def);
+ break;
+ case MMU_TYPE_R3000:
+ case MMU_TYPE_R6000:
+ case MMU_TYPE_R8000:
+ default:
+ cpu_abort(env_cpu(env), "MMU type not supported\n");
+ }
+}
+#endif /* CONFIG_USER_ONLY */
+
+static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
+{
+ int i;
+
+ for (i = 0; i < MIPS_FPU_MAX; i++)
+ env->fpus[i].fcr0 = def->CP1_fcr0;
+
+ memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
+}
+
+static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
+{
+ env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
+
+ /* MVPConf1 implemented, TLB sharable, no gating storage support,
+ programmable cache partitioning implemented, number of allocatable
+ and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+ implemented, 5 TCs implemented. */
+ env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+ (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+// TODO: actually do 2 VPEs.
+// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
+// (0x04 << CP0MVPC0_PTC);
+ (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+ (0x00 << CP0MVPC0_PTC);
+#if !defined(CONFIG_USER_ONLY)
+ /* Usermode has no TLB support */
+ env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+#endif
+
+ /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
+ no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
+ env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+ (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
+ (0x1 << CP0MVPC1_PCP1);
+}
+
+static void msa_reset(CPUMIPSState *env)
+{
+#ifdef CONFIG_USER_ONLY
+ /* MSA access enabled */
+ env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+ env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+ /* MSA CSR:
+ - non-signaling floating point exception mode off (NX bit is 0)
+ - Cause, Enables, and Flags are all 0
+ - round to nearest / ties to even (RM bits are 0) */
+ env->active_tc.msacsr = 0;
+
+ restore_msa_fp_status(env);
+
+ /* tininess detected after rounding.*/
+ set_float_detect_tininess(float_tininess_after_rounding,
+ &env->active_tc.msa_fp_status);
+
+ /* clear float_status exception flags */
+ set_float_exception_flags(0, &env->active_tc.msa_fp_status);
+
+ /* clear float_status nan mode */
+ set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+ /* set proper signanling bit meaning ("1" means "quiet") */
+ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+}
+++ /dev/null
-/*
- * MIPS emulation for qemu: CPU initialisation routines.
- *
- * Copyright (c) 2004-2005 Jocelyn Mayer
- * Copyright (c) 2007 Herve Poussineau
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/* CPU / CPU family specific config register values. */
-
-/* Have config1, uncached coherency */
-#define MIPS_CONFIG0 \
- ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
-
-/* Have config2, no coprocessor2 attached, no MDMX support attached,
- no performance counters, watch registers present,
- no code compression, EJTAG present, no FPU */
-#define MIPS_CONFIG1 \
-((1U << CP0C1_M) | \
- (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
- (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
- (0 << CP0C1_FP))
-
-/* Have config3, no tertiary/secondary caches implemented */
-#define MIPS_CONFIG2 \
-((1U << CP0C2_M))
-
-/* No config4, no DSP ASE, no large physaddr (PABITS),
- no external interrupt controller, no vectored interrupts,
- no 1kb pages, no SmartMIPS ASE, no trace logic */
-#define MIPS_CONFIG3 \
-((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
- (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
- (0 << CP0C3_SM) | (0 << CP0C3_TL))
-
-#define MIPS_CONFIG4 \
-((0 << CP0C4_M))
-
-#define MIPS_CONFIG5 \
-((0 << CP0C5_M))
-
-/*****************************************************************************/
-/* MIPS CPU definitions */
-const mips_def_t mips_defs[] =
-{
- {
- .name = "4Kc",
- .CP0_PRid = 0x00018000,
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (0 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "4Km",
- .CP0_PRid = 0x00018300,
- /* Config1 implemented, fixed mapping MMU,
- no virtual icache, uncached coherency. */
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "4KEcR1",
- .CP0_PRid = 0x00018400,
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (0 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "4KEmR1",
- .CP0_PRid = 0x00018500,
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "4KEc",
- .CP0_PRid = 0x00019000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (0 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "4KEm",
- .CP0_PRid = 0x00019100,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "24Kc",
- .CP0_PRid = 0x00019300,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- /* No DSP implemented. */
- .CP0_Status_rw_bitmask = 0x1278FF1F,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "24KEc",
- .CP0_PRid = 0x00019600,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- /* we have a DSP, but no FPU */
- .CP0_Status_rw_bitmask = 0x1378FF1F,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "24Kf",
- .CP0_PRid = 0x00019300,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- /* No DSP implemented. */
- .CP0_Status_rw_bitmask = 0x3678FF1F,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "34Kf",
- .CP0_PRid = 0x00019500,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
- (1 << CP0C3_DSPP),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3778FF1F,
- .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
- (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
- (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
- (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
- (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
- (0xff << CP0TCSt_TASID),
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
- .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
- (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
- .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
- (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
- .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
- (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
- .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
- (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
- .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
- (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "74Kf",
- .CP0_PRid = 0x00019700,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
- (1 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3778FF1F,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "M14K",
- .CP0_PRid = 0x00019b00,
- /* Config1 implemented, fixed mapping MMU,
- no virtual icache, uncached coherency. */
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
- (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1,
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "M14Kc",
- /* This is the TLB-based MMU core. */
- .CP0_PRid = 0x00019c00,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- /* FIXME:
- * Config3: VZ, CTXTC, CDMM, TL
- * Config4: MMUExtDef
- * Config5: MRP
- * FIR(FCR0): Has2008
- * */
- .name = "P5600",
- .CP0_PRid = 0x0001A800,
- .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_FP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
- (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
- (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
- (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
- (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
- .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
- (0x1c << CP0C4_KScrExist),
- .CP0_Config4_rw_bitmask = 0,
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
- (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
- (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
- (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3C68FF1F,
- .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
- (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
- .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
- .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
- (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
- .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 32,
- .PABITS = 40,
- .insn_flags = CPU_MIPS32R5 | ASE_MSA,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- /* A generic CPU supporting MIPS32 Release 6 ISA.
- FIXME: Support IEEE 754-2008 FP.
- Eventually this should be replaced by a real CPU model. */
- .name = "mips32r6-generic",
- .CP0_PRid = 0x00010000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
- (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
- (1 << CP0C3_RXI) | (1U << CP0C3_M),
- .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
- (3 << CP0C4_IE) | (1U << CP0C4_M),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
- (1 << CP0C5_UFE),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3058FF1F,
- .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
- (1U << CP0PG_RIE),
- .CP0_PageGrain_rw_bitmask = 0,
- .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
- .CP1_fcr31_rw_bitmask = 0x0103FFFF,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "I7200",
- .CP0_PRid = 0x00010000,
- .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
- (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
- (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
- (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
- (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
- (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
- (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
- (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
- (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
- (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
- .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
- (2 << CP0C4_IE) | (1U << CP0C4_M),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
- (1 << CP0C5_UFE),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3158FF1F,
- .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
- (1U << CP0PG_RIE),
- .CP0_PageGrain_rw_bitmask = 0,
- .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
- ASE_MT,
- .mmu_type = MMU_TYPE_R4000,
- },
-#if defined(TARGET_MIPS64)
- {
- .name = "R4000",
- .CP0_PRid = 0x00000400,
- /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
- /* Note: Config1 is only used internally, the R4000 has only Config0. */
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3678FFFF,
- /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0x0183FFFF,
- .SEGBITS = 40,
- .PABITS = 36,
- .insn_flags = CPU_MIPS3,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "VR5432",
- .CP0_PRid = 0x00005400,
- /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3678FFFF,
- /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 40,
- .PABITS = 32,
- .insn_flags = CPU_VR54XX,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "5Kc",
- .CP0_PRid = 0x00018100,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
- (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
- (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x12F8FFFF,
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "5Kf",
- .CP0_PRid = 0x00018100,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
- (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
- (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x36F8FFFF,
- /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
- (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "20Kc",
- /* We emulate a later version of the 20Kc, earlier ones had a broken
- WAIT instruction. */
- .CP0_PRid = 0x000182a0,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 1,
- .CP0_Status_rw_bitmask = 0x36FBFFFF,
- /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
- (1 << FCR0_D) | (1 << FCR0_S) |
- (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 40,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- /* A generic CPU providing MIPS64 Release 2 features.
- FIXME: Eventually this should be replaced by a real CPU model. */
- .name = "MIPS64R2-generic",
- .CP0_PRid = 0x00010000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x36FBFFFF,
- .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "5KEc",
- .CP0_PRid = 0x00018900,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
- (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
- (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x12F8FFFF,
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64R2,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "5KEf",
- .CP0_PRid = 0x00018900,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
- (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
- (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x36F8FFFF,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) |
- (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64R2,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "I6400",
- .CP0_PRid = 0x1A900,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
- (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
- (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
- (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
- (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
- .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
- (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
- (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
- (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x30D8FFFF,
- .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
- (1U << CP0PG_RIE),
- .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
- .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
- .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
- .CP1_fcr31_rw_bitmask = 0x0103FFFF,
- .MSAIR = 0x03 << MSAIR_ProcID,
- .SEGBITS = 48,
- .PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "I6500",
- .CP0_PRid = 0x1B000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
- (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
- (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
- (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
- (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
- .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
- (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
- (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
- (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 64,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x30D8FFFF,
- .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
- (1U << CP0PG_RIE),
- .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
- .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
- .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
- .CP1_fcr31_rw_bitmask = 0x0103FFFF,
- .MSAIR = 0x03 << MSAIR_ProcID,
- .SEGBITS = 48,
- .PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "Loongson-2E",
- .CP0_PRid = 0x6302,
- /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
- (0x1<<5) | (0x1<<4) | (0x1<<1),
- /* Note: Config1 is only used internally,
- Loongson-2E has only Config0. */
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x35D0FFFF,
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 40,
- .PABITS = 40,
- .insn_flags = CPU_LOONGSON2E,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "Loongson-2F",
- .CP0_PRid = 0x6303,
- /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
- (0x1<<5) | (0x1<<4) | (0x1<<1),
- /* Note: Config1 is only used internally,
- Loongson-2F has only Config0. */
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 40,
- .PABITS = 40,
- .insn_flags = CPU_LOONGSON2F,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "Loongson-3A1000",
- .CP0_PRid = 0x6305,
- /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
- (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
- (3 << CP0C2_SA),
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
- .CP0_LLAddr_rw_bitmask = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x74D8FFFF,
- .CP0_PageGrain = (1 << CP0PG_ELPA),
- .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
- (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
- (0x1 << FCR0_D) | (0x1 << FCR0_S),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 42,
- .PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "Loongson-3A4000",
- .CP0_PRid = 0x14C000,
- /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
- (15 << CP0C2_SA),
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
- (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
- (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
- .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
- (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
- .CP0_Config4_rw_bitmask = 0,
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
- (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
- (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
- .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
- (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
- (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
- .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
- (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
- (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
- (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
- (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
- (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
- (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
- (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
- (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
- (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
- (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
- (1 << CP0C6_DATAPREF),
- .CP0_Config7 = 0,
- .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
- (1 << CP0C7_VFPUCGEN),
- .CP0_LLAddr_rw_bitmask = 1,
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x7DDBFFFF,
- .CP0_PageGrain = (1 << CP0PG_ELPA),
- .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
- (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
- (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
- (0x1 << FCR0_D) | (0x1 << FCR0_S),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 48,
- .PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- /* A generic CPU providing MIPS64 DSP R2 ASE features.
- FIXME: Eventually this should be replaced by a real CPU model. */
- .name = "mips64dspr2",
- .CP0_PRid = 0x00010000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
- (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x37FBFFFF,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
- .CP1_fcr31 = 0,
- .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
- .mmu_type = MMU_TYPE_R4000,
- },
-
-#endif
-};
-const int mips_defs_number = ARRAY_SIZE(mips_defs);
-
-void mips_cpu_list(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
- qemu_printf("MIPS '%s'\n", mips_defs[i].name);
- }
-}
-
-#ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &no_mmu_map_address;
-}
-
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &fixed_mmu_map_address;
-}
-
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
- env->tlb->map_address = &r4k_map_address;
- env->tlb->helper_tlbwi = r4k_helper_tlbwi;
- env->tlb->helper_tlbwr = r4k_helper_tlbwr;
- env->tlb->helper_tlbp = r4k_helper_tlbp;
- env->tlb->helper_tlbr = r4k_helper_tlbr;
- env->tlb->helper_tlbinv = r4k_helper_tlbinv;
- env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
-}
-
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
- switch (def->mmu_type) {
- case MMU_TYPE_NONE:
- no_mmu_init(env, def);
- break;
- case MMU_TYPE_R4000:
- r4k_mmu_init(env, def);
- break;
- case MMU_TYPE_FMT:
- fixed_mmu_init(env, def);
- break;
- case MMU_TYPE_R3000:
- case MMU_TYPE_R6000:
- case MMU_TYPE_R8000:
- default:
- cpu_abort(env_cpu(env), "MMU type not supported\n");
- }
-}
-#endif /* CONFIG_USER_ONLY */
-
-static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- int i;
-
- for (i = 0; i < MIPS_FPU_MAX; i++)
- env->fpus[i].fcr0 = def->CP1_fcr0;
-
- memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
-}
-
-static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
- /* MVPConf1 implemented, TLB sharable, no gating storage support,
- programmable cache partitioning implemented, number of allocatable
- and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
- implemented, 5 TCs implemented. */
- env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
- (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
-// TODO: actually do 2 VPEs.
-// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
-// (0x04 << CP0MVPC0_PTC);
- (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
- (0x00 << CP0MVPC0_PTC);
-#if !defined(CONFIG_USER_ONLY)
- /* Usermode has no TLB support */
- env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
-#endif
-
- /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
- no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
- env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
- (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
- (0x1 << CP0MVPC1_PCP1);
-}
-
-static void msa_reset(CPUMIPSState *env)
-{
-#ifdef CONFIG_USER_ONLY
- /* MSA access enabled */
- env->CP0_Config5 |= 1 << CP0C5_MSAEn;
- env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
- /* MSA CSR:
- - non-signaling floating point exception mode off (NX bit is 0)
- - Cause, Enables, and Flags are all 0
- - round to nearest / ties to even (RM bits are 0) */
- env->active_tc.msacsr = 0;
-
- restore_msa_fp_status(env);
-
- /* tininess detected after rounding.*/
- set_float_detect_tininess(float_tininess_after_rounding,
- &env->active_tc.msa_fp_status);
-
- /* clear float_status exception flags */
- set_float_exception_flags(0, &env->active_tc.msa_fp_status);
-
- /* clear float_status nan mode */
- set_default_nan_mode(0, &env->active_tc.msa_fp_status);
-
- /* set proper signanling bit meaning ("1" means "quiet") */
- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
-}
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
-target/openrisc/decode.inc.c: \
+target/openrisc/decode.c.inc: \
$(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
-target/openrisc/translate.o: target/openrisc/decode.inc.c
-target/openrisc/disas.o: target/openrisc/decode.inc.c
+target/openrisc/translate.o: target/openrisc/decode.c.inc
+target/openrisc/disas.o: target/openrisc/decode.c.inc
typedef disassemble_info DisasContext;
/* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
#define output(mnemonic, format, ...) \
(info->fprintf_func(info->stream, "%-9s " format, \
}
/* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
static TCGv cpu_sr;
static TCGv cpu_regs[32];
target_ulong helper_602_mfrom(target_ulong arg)
{
if (likely(arg < 602)) {
-#include "mfrom_table.inc.c"
+#include "mfrom_table.c.inc"
return mfrom_ROM_table[arg];
} else {
return 0;
--- /dev/null
+static const uint8_t mfrom_ROM_table[602] = {
+ 77, 77, 76, 76, 75, 75, 74, 74,
+ 73, 73, 72, 72, 71, 71, 70, 70,
+ 69, 69, 68, 68, 68, 67, 67, 66,
+ 66, 65, 65, 64, 64, 64, 63, 63,
+ 62, 62, 61, 61, 61, 60, 60, 59,
+ 59, 58, 58, 58, 57, 57, 56, 56,
+ 56, 55, 55, 54, 54, 54, 53, 53,
+ 53, 52, 52, 51, 51, 51, 50, 50,
+ 50, 49, 49, 49, 48, 48, 47, 47,
+ 47, 46, 46, 46, 45, 45, 45, 44,
+ 44, 44, 43, 43, 43, 42, 42, 42,
+ 42, 41, 41, 41, 40, 40, 40, 39,
+ 39, 39, 39, 38, 38, 38, 37, 37,
+ 37, 37, 36, 36, 36, 35, 35, 35,
+ 35, 34, 34, 34, 34, 33, 33, 33,
+ 33, 32, 32, 32, 32, 31, 31, 31,
+ 31, 30, 30, 30, 30, 29, 29, 29,
+ 29, 28, 28, 28, 28, 28, 27, 27,
+ 27, 27, 26, 26, 26, 26, 26, 25,
+ 25, 25, 25, 25, 24, 24, 24, 24,
+ 24, 23, 23, 23, 23, 23, 23, 22,
+ 22, 22, 22, 22, 21, 21, 21, 21,
+ 21, 21, 20, 20, 20, 20, 20, 20,
+ 19, 19, 19, 19, 19, 19, 19, 18,
+ 18, 18, 18, 18, 18, 17, 17, 17,
+ 17, 17, 17, 17, 16, 16, 16, 16,
+ 16, 16, 16, 16, 15, 15, 15, 15,
+ 15, 15, 15, 15, 14, 14, 14, 14,
+ 14, 14, 14, 14, 13, 13, 13, 13,
+ 13, 13, 13, 13, 13, 12, 12, 12,
+ 12, 12, 12, 12, 12, 12, 12, 11,
+ 11, 11, 11, 11, 11, 11, 11, 11,
+ 11, 11, 10, 10, 10, 10, 10, 10,
+ 10, 10, 10, 10, 10, 9, 9, 9,
+ 9, 9, 9, 9, 9, 9, 9, 9,
+ 9, 9, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 8, 8,
+ 7, 7, 7, 7, 7, 7, 7, 7,
+ 7, 7, 7, 7, 7, 7, 7, 7,
+ 7, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 5, 5, 5, 5,
+ 5, 5, 5, 5, 5, 5, 5, 5,
+ 5, 5, 5, 5, 5, 5, 5, 5,
+ 5, 5, 5, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 0,
+};
+++ /dev/null
-static const uint8_t mfrom_ROM_table[602] = {
- 77, 77, 76, 76, 75, 75, 74, 74,
- 73, 73, 72, 72, 71, 71, 70, 70,
- 69, 69, 68, 68, 68, 67, 67, 66,
- 66, 65, 65, 64, 64, 64, 63, 63,
- 62, 62, 61, 61, 61, 60, 60, 59,
- 59, 58, 58, 58, 57, 57, 56, 56,
- 56, 55, 55, 54, 54, 54, 53, 53,
- 53, 52, 52, 51, 51, 51, 50, 50,
- 50, 49, 49, 49, 48, 48, 47, 47,
- 47, 46, 46, 46, 45, 45, 45, 44,
- 44, 44, 43, 43, 43, 42, 42, 42,
- 42, 41, 41, 41, 40, 40, 40, 39,
- 39, 39, 39, 38, 38, 38, 37, 37,
- 37, 37, 36, 36, 36, 35, 35, 35,
- 35, 34, 34, 34, 34, 33, 33, 33,
- 33, 32, 32, 32, 32, 31, 31, 31,
- 31, 30, 30, 30, 30, 29, 29, 29,
- 29, 28, 28, 28, 28, 28, 27, 27,
- 27, 27, 26, 26, 26, 26, 26, 25,
- 25, 25, 25, 25, 24, 24, 24, 24,
- 24, 23, 23, 23, 23, 23, 23, 22,
- 22, 22, 22, 22, 21, 21, 21, 21,
- 21, 21, 20, 20, 20, 20, 20, 20,
- 19, 19, 19, 19, 19, 19, 19, 18,
- 18, 18, 18, 18, 18, 17, 17, 17,
- 17, 17, 17, 17, 16, 16, 16, 16,
- 16, 16, 16, 16, 15, 15, 15, 15,
- 15, 15, 15, 15, 14, 14, 14, 14,
- 14, 14, 14, 14, 13, 13, 13, 13,
- 13, 13, 13, 13, 13, 12, 12, 12,
- 12, 12, 12, 12, 12, 12, 12, 11,
- 11, 11, 11, 11, 11, 11, 11, 11,
- 11, 11, 10, 10, 10, 10, 10, 10,
- 10, 10, 10, 10, 10, 9, 9, 9,
- 9, 9, 9, 9, 9, 9, 9, 9,
- 9, 9, 8, 8, 8, 8, 8, 8,
- 8, 8, 8, 8, 8, 8, 8, 8,
- 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 7, 7, 7, 7, 7, 7, 7,
- 7, 6, 6, 6, 6, 6, 6, 6,
- 6, 6, 6, 6, 6, 6, 6, 6,
- 6, 6, 6, 6, 5, 5, 5, 5,
- 5, 5, 5, 5, 5, 5, 5, 5,
- 5, 5, 5, 5, 5, 5, 5, 5,
- 5, 5, 5, 4, 4, 4, 4, 4,
- 4, 4, 4, 4, 4, 4, 4, 4,
- 4, 4, 4, 4, 4, 4, 4, 4,
- 4, 4, 4, 4, 4, 4, 4, 3,
- 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 3, 3, 3, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 0,
-};
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
-#include "translate/fp-impl.inc.c"
+#include "translate/fp-impl.c.inc"
-#include "translate/vmx-impl.inc.c"
+#include "translate/vmx-impl.c.inc"
-#include "translate/vsx-impl.inc.c"
+#include "translate/vsx-impl.c.inc"
-#include "translate/dfp-impl.inc.c"
+#include "translate/dfp-impl.c.inc"
-#include "translate/spe-impl.inc.c"
+#include "translate/spe-impl.c.inc"
/* Handles lfdp, lxsd, lxssp */
static void gen_dform39(DisasContext *ctx)
GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
PPC_NONE, PPC2_TM),
-#include "translate/fp-ops.inc.c"
+#include "translate/fp-ops.c.inc"
-#include "translate/vmx-ops.inc.c"
+#include "translate/vmx-ops.c.inc"
-#include "translate/vsx-ops.inc.c"
+#include "translate/vsx-ops.c.inc"
-#include "translate/dfp-ops.inc.c"
+#include "translate/dfp-ops.c.inc"
-#include "translate/spe-ops.inc.c"
+#include "translate/spe-ops.c.inc"
};
#include "helper_regs.h"
-#include "translate_init.inc.c"
+#include "translate_init.c.inc"
/*****************************************************************************/
/* Misc PowerPC helpers */
--- /dev/null
+/*** Decimal Floating Point ***/
+
+static inline TCGv_ptr gen_fprp_ptr(int reg)
+{
+ TCGv_ptr r = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
+ return r;
+}
+
+#define GEN_DFP_T_A_B_Rc(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr rd, ra, rb; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ rd = gen_fprp_ptr(rD(ctx->opcode)); \
+ ra = gen_fprp_ptr(rA(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rd, ra, rb); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rd); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+}
+
+#define GEN_DFP_BF_A_B(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rb; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ ra = gen_fprp_ptr(rA(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
+ cpu_env, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+}
+
+#define GEN_DFP_BF_I_B(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 uim; \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ uim = tcg_const_i32(UIMM5(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
+ cpu_env, uim, rb); \
+ tcg_temp_free_i32(uim); \
+ tcg_temp_free_ptr(rb); \
+}
+
+#define GEN_DFP_BF_A_DCM(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra; \
+ TCGv_i32 dcm; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ ra = gen_fprp_ptr(rA(ctx->opcode)); \
+ dcm = tcg_const_i32(DCM(ctx->opcode)); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
+ cpu_env, ra, dcm); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_i32(dcm); \
+}
+
+#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr rt, rb; \
+ TCGv_i32 u32_1, u32_2; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ rt = gen_fprp_ptr(rD(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
+ u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_i32(u32_1); \
+ tcg_temp_free_i32(u32_2); \
+}
+
+#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr rt, ra, rb; \
+ TCGv_i32 i32; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ rt = gen_fprp_ptr(rD(ctx->opcode)); \
+ ra = gen_fprp_ptr(rA(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ i32 = tcg_const_i32(i32fld(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rt, ra, rb, i32); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_i32(i32); \
+ }
+
+#define GEN_DFP_T_B_Rc(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr rt, rb; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ rt = gen_fprp_ptr(rD(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rt, rb); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rb); \
+ }
+
+#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr rt, rs; \
+ TCGv_i32 i32; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->base.pc_next - 4); \
+ rt = gen_fprp_ptr(rD(ctx->opcode)); \
+ rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
+ i32 = tcg_const_i32(i32fld(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rt, rs, i32); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rs); \
+ tcg_temp_free_i32(i32); \
+}
+
+GEN_DFP_T_A_B_Rc(dadd)
+GEN_DFP_T_A_B_Rc(daddq)
+GEN_DFP_T_A_B_Rc(dsub)
+GEN_DFP_T_A_B_Rc(dsubq)
+GEN_DFP_T_A_B_Rc(dmul)
+GEN_DFP_T_A_B_Rc(dmulq)
+GEN_DFP_T_A_B_Rc(ddiv)
+GEN_DFP_T_A_B_Rc(ddivq)
+GEN_DFP_BF_A_B(dcmpu)
+GEN_DFP_BF_A_B(dcmpuq)
+GEN_DFP_BF_A_B(dcmpo)
+GEN_DFP_BF_A_B(dcmpoq)
+GEN_DFP_BF_A_DCM(dtstdc)
+GEN_DFP_BF_A_DCM(dtstdcq)
+GEN_DFP_BF_A_DCM(dtstdg)
+GEN_DFP_BF_A_DCM(dtstdgq)
+GEN_DFP_BF_A_B(dtstex)
+GEN_DFP_BF_A_B(dtstexq)
+GEN_DFP_BF_A_B(dtstsf)
+GEN_DFP_BF_A_B(dtstsfq)
+GEN_DFP_BF_I_B(dtstsfi)
+GEN_DFP_BF_I_B(dtstsfiq)
+GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
+GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
+GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
+GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
+GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
+GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
+GEN_DFP_T_B_Rc(dctdp)
+GEN_DFP_T_B_Rc(dctqpq)
+GEN_DFP_T_B_Rc(drsp)
+GEN_DFP_T_B_Rc(drdpq)
+GEN_DFP_T_B_Rc(dcffix)
+GEN_DFP_T_B_Rc(dcffixq)
+GEN_DFP_T_B_Rc(dctfix)
+GEN_DFP_T_B_Rc(dctfixq)
+GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
+GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
+GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
+GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
+GEN_DFP_T_B_Rc(dxex)
+GEN_DFP_T_B_Rc(dxexq)
+GEN_DFP_T_A_B_Rc(diex)
+GEN_DFP_T_A_B_Rc(diexq)
+GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
+GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
+GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
+GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
+
+#undef GEN_DFP_T_A_B_Rc
+#undef GEN_DFP_BF_A_B
+#undef GEN_DFP_BF_A_DCM
+#undef GEN_DFP_T_B_U32_U32_Rc
+#undef GEN_DFP_T_A_B_I32_Rc
+#undef GEN_DFP_T_B_Rc
+#undef GEN_DFP_T_FPR_I32_Rc
+++ /dev/null
-/*** Decimal Floating Point ***/
-
-static inline TCGv_ptr gen_fprp_ptr(int reg)
-{
- TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
- return r;
-}
-
-#define GEN_DFP_T_A_B_Rc(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rd, ra, rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- rd = gen_fprp_ptr(rD(ctx->opcode)); \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, ra, rb); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rd); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
-}
-
-#define GEN_DFP_BF_A_B(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
- cpu_env, ra, rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
-}
-
-#define GEN_DFP_BF_I_B(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 uim; \
- TCGv_ptr rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- uim = tcg_const_i32(UIMM5(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
- cpu_env, uim, rb); \
- tcg_temp_free_i32(uim); \
- tcg_temp_free_ptr(rb); \
-}
-
-#define GEN_DFP_BF_A_DCM(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr ra; \
- TCGv_i32 dcm; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- dcm = tcg_const_i32(DCM(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
- cpu_env, ra, dcm); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_i32(dcm); \
-}
-
-#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, rb; \
- TCGv_i32 u32_1, u32_2; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
- u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_i32(u32_1); \
- tcg_temp_free_i32(u32_2); \
-}
-
-#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, ra, rb; \
- TCGv_i32 i32; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- i32 = tcg_const_i32(i32fld(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, ra, rb, i32); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_i32(i32); \
- }
-
-#define GEN_DFP_T_B_Rc(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, rb); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rb); \
- }
-
-#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, rs; \
- TCGv_i32 i32; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
- i32 = tcg_const_i32(i32fld(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, rs, i32); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rs); \
- tcg_temp_free_i32(i32); \
-}
-
-GEN_DFP_T_A_B_Rc(dadd)
-GEN_DFP_T_A_B_Rc(daddq)
-GEN_DFP_T_A_B_Rc(dsub)
-GEN_DFP_T_A_B_Rc(dsubq)
-GEN_DFP_T_A_B_Rc(dmul)
-GEN_DFP_T_A_B_Rc(dmulq)
-GEN_DFP_T_A_B_Rc(ddiv)
-GEN_DFP_T_A_B_Rc(ddivq)
-GEN_DFP_BF_A_B(dcmpu)
-GEN_DFP_BF_A_B(dcmpuq)
-GEN_DFP_BF_A_B(dcmpo)
-GEN_DFP_BF_A_B(dcmpoq)
-GEN_DFP_BF_A_DCM(dtstdc)
-GEN_DFP_BF_A_DCM(dtstdcq)
-GEN_DFP_BF_A_DCM(dtstdg)
-GEN_DFP_BF_A_DCM(dtstdgq)
-GEN_DFP_BF_A_B(dtstex)
-GEN_DFP_BF_A_B(dtstexq)
-GEN_DFP_BF_A_B(dtstsf)
-GEN_DFP_BF_A_B(dtstsfq)
-GEN_DFP_BF_I_B(dtstsfi)
-GEN_DFP_BF_I_B(dtstsfiq)
-GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
-GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
-GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
-GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
-GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
-GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
-GEN_DFP_T_B_Rc(dctdp)
-GEN_DFP_T_B_Rc(dctqpq)
-GEN_DFP_T_B_Rc(drsp)
-GEN_DFP_T_B_Rc(drdpq)
-GEN_DFP_T_B_Rc(dcffix)
-GEN_DFP_T_B_Rc(dcffixq)
-GEN_DFP_T_B_Rc(dctfix)
-GEN_DFP_T_B_Rc(dctfixq)
-GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
-GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
-GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
-GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
-GEN_DFP_T_B_Rc(dxex)
-GEN_DFP_T_B_Rc(dxexq)
-GEN_DFP_T_A_B_Rc(diex)
-GEN_DFP_T_A_B_Rc(diexq)
-GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
-GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
-GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
-GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-
-#undef GEN_DFP_T_A_B_Rc
-#undef GEN_DFP_BF_A_B
-#undef GEN_DFP_BF_A_DCM
-#undef GEN_DFP_T_B_U32_U32_Rc
-#undef GEN_DFP_T_A_B_I32_Rc
-#undef GEN_DFP_T_B_Rc
-#undef GEN_DFP_T_FPR_I32_Rc
--- /dev/null
+#define _GEN_DFP_LONG(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_LONG_300(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300)
+
+#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_QUAD(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300)
+
+#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
+
+#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
+
+#define GEN_DFP_T_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
+
+#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
+
+#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
+
+#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
+
+#define GEN_DFP_BF_A_B(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x00000001)
+
+#define GEN_DFP_BF_A_B_300(name, op1, op2) \
+_GEN_DFP_LONG_300(name, op1, op2, 0x00400001)
+
+#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
+
+#define GEN_DFP_BF_A_Bp(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
+
+#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \
+_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001)
+
+#define GEN_DFP_BF_A_DCM(name, op1, op2) \
+_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
+
+#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
+_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
+
+#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
+_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
+
+#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
+
+#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
+_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
+
+#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
+_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
+
+#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
+
+#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x00070000)
+
+#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
+
+#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
+
+#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
+
+#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
+_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
+_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
+
+GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
+GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
+GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
+GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
+GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
+GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
+GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
+GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
+GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
+GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
+GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
+GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
+GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
+GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
+GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
+GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
+GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
+GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
+GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
+GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
+GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15),
+GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15),
+GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
+GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
+GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
+GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
+GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
+GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
+GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
+GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
+GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
+GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
+GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
+GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
+GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
+GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
+GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
+GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
+GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
+GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
+GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
+GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
+GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
+GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
+GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
+GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
+GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
+GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
+GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
+GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
+GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
+GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
+++ /dev/null
-#define _GEN_DFP_LONG(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_LONG_300(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300)
-
-#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_QUAD(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300)
-
-#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-
-#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
-
-#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
-
-#define GEN_DFP_T_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
-
-#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
-
-#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
-
-#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
-
-#define GEN_DFP_BF_A_B(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x00000001)
-
-#define GEN_DFP_BF_A_B_300(name, op1, op2) \
-_GEN_DFP_LONG_300(name, op1, op2, 0x00400001)
-
-#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
-
-#define GEN_DFP_BF_A_Bp(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
-
-#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \
-_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001)
-
-#define GEN_DFP_BF_A_DCM(name, op1, op2) \
-_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
-
-#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
-_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
-
-#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
-
-#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
-
-#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
-
-#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
-
-#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
-
-#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x00070000)
-
-#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
-
-#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
-
-#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
-
-#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
-_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
-_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-
-GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
-GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
-GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
-GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
-GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
-GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
-GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
-GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
-GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
-GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
-GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
-GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
-GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
-GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
-GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
-GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
-GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
-GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
-GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
-GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
-GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15),
-GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15),
-GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
-GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
-GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
-GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
-GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
-GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
-GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
-GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
-GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
-GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
-GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
-GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
-GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
-GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
-GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
-GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
-GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
-GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
-GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
-GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
-GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
-GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
-GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
-GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
-GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
-GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
-GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
-GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
-GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
-GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
--- /dev/null
+/*
+ * translate-fp.c
+ *
+ * Standard FPU translation
+ */
+
+static inline void gen_reset_fpstatus(void)
+{
+ gen_helper_reset_fpstatus(cpu_env);
+}
+
+static inline void gen_compute_fprf_float64(TCGv_i64 arg)
+{
+ gen_helper_compute_fprf_float64(cpu_env, arg);
+ gen_helper_float_check_status(cpu_env);
+}
+
+#if defined(TARGET_PPC64)
+static void gen_set_cr1_from_fpscr(DisasContext *ctx)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
+ tcg_temp_free_i32(tmp);
+}
+#else
+static void gen_set_cr1_from_fpscr(DisasContext *ctx)
+{
+ tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
+}
+#endif
+
+/*** Floating-Point arithmetic ***/
+#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
+static void gen_f##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ TCGv_i64 t2; \
+ TCGv_i64 t3; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ t2 = tcg_temp_new_i64(); \
+ t3 = tcg_temp_new_i64(); \
+ gen_reset_fpstatus(); \
+ get_fpr(t0, rA(ctx->opcode)); \
+ get_fpr(t1, rC(ctx->opcode)); \
+ get_fpr(t2, rB(ctx->opcode)); \
+ gen_helper_f##op(t3, cpu_env, t0, t1, t2); \
+ if (isfloat) { \
+ gen_helper_frsp(t3, cpu_env, t3); \
+ } \
+ set_fpr(rD(ctx->opcode), t3); \
+ if (set_fprf) { \
+ gen_compute_fprf_float64(t3); \
+ } \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+ tcg_temp_free_i64(t3); \
+}
+
+#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
+_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
+_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
+
+#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+static void gen_f##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ TCGv_i64 t2; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ t2 = tcg_temp_new_i64(); \
+ gen_reset_fpstatus(); \
+ get_fpr(t0, rA(ctx->opcode)); \
+ get_fpr(t1, rB(ctx->opcode)); \
+ gen_helper_f##op(t2, cpu_env, t0, t1); \
+ if (isfloat) { \
+ gen_helper_frsp(t2, cpu_env, t2); \
+ } \
+ set_fpr(rD(ctx->opcode), t2); \
+ if (set_fprf) { \
+ gen_compute_fprf_float64(t2); \
+ } \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+}
+#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
+_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
+_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
+
+#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+static void gen_f##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ TCGv_i64 t2; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ t2 = tcg_temp_new_i64(); \
+ gen_reset_fpstatus(); \
+ get_fpr(t0, rA(ctx->opcode)); \
+ get_fpr(t1, rC(ctx->opcode)); \
+ gen_helper_f##op(t2, cpu_env, t0, t1); \
+ if (isfloat) { \
+ gen_helper_frsp(t2, cpu_env, t2); \
+ } \
+ set_fpr(rD(ctx->opcode), t2); \
+ if (set_fprf) { \
+ gen_compute_fprf_float64(t2); \
+ } \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+}
+#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
+_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
+_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
+
+#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
+static void gen_f##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ gen_reset_fpstatus(); \
+ get_fpr(t0, rB(ctx->opcode)); \
+ gen_helper_f##name(t1, cpu_env, t0); \
+ set_fpr(rD(ctx->opcode), t1); \
+ if (set_fprf) { \
+ gen_compute_fprf_float64(t1); \
+ } \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+}
+
+#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
+static void gen_f##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ gen_reset_fpstatus(); \
+ get_fpr(t0, rB(ctx->opcode)); \
+ gen_helper_f##name(t1, cpu_env, t0); \
+ set_fpr(rD(ctx->opcode), t1); \
+ if (set_fprf) { \
+ gen_compute_fprf_float64(t1); \
+ } \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+}
+
+/* fadd - fadds */
+GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
+/* fdiv - fdivs */
+GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
+/* fmul - fmuls */
+GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
+
+/* fre */
+GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
+
+/* fres */
+GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
+
+/* frsqrte */
+GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
+
+/* frsqrtes */
+static void gen_frsqrtes(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ get_fpr(t0, rB(ctx->opcode));
+ gen_helper_frsqrte(t1, cpu_env, t0);
+ gen_helper_frsp(t1, cpu_env, t1);
+ set_fpr(rD(ctx->opcode), t1);
+ gen_compute_fprf_float64(t1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* fsel */
+_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
+/* fsub - fsubs */
+GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
+/* Optional: */
+
+/* fsqrt */
+static void gen_fsqrt(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ get_fpr(t0, rB(ctx->opcode));
+ gen_helper_fsqrt(t1, cpu_env, t0);
+ set_fpr(rD(ctx->opcode), t1);
+ gen_compute_fprf_float64(t1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static void gen_fsqrts(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ get_fpr(t0, rB(ctx->opcode));
+ gen_helper_fsqrt(t1, cpu_env, t0);
+ gen_helper_frsp(t1, cpu_env, t1);
+ set_fpr(rD(ctx->opcode), t1);
+ gen_compute_fprf_float64(t1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/*** Floating-Point multiply-and-add ***/
+/* fmadd - fmadds */
+GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
+/* fmsub - fmsubs */
+GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
+/* fnmadd - fnmadds */
+GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
+/* fnmsub - fnmsubs */
+GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
+
+/*** Floating-Point round & convert ***/
+/* fctiw */
+GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
+/* fctiwu */
+GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
+/* fctiwz */
+GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
+/* fctiwuz */
+GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
+/* frsp */
+GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
+/* fcfid */
+GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
+/* fcfids */
+GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
+/* fcfidu */
+GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
+/* fcfidus */
+GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
+/* fctid */
+GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
+/* fctidu */
+GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
+/* fctidz */
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
+/* fctidu */
+GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
+
+/* frin */
+GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
+/* friz */
+GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
+/* frip */
+GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
+/* frim */
+GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
+
+static void gen_ftdiv(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ get_fpr(t0, rA(ctx->opcode));
+ get_fpr(t1, rB(ctx->opcode));
+ gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static void gen_ftsqrt(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0);
+ tcg_temp_free_i64(t0);
+}
+
+
+
+/*** Floating-Point compare ***/
+
+/* fcmpo */
+static void gen_fcmpo(DisasContext *ctx)
+{
+ TCGv_i32 crf;
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ crf = tcg_const_i32(crfD(ctx->opcode));
+ get_fpr(t0, rA(ctx->opcode));
+ get_fpr(t1, rB(ctx->opcode));
+ gen_helper_fcmpo(cpu_env, t0, t1, crf);
+ tcg_temp_free_i32(crf);
+ gen_helper_float_check_status(cpu_env);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* fcmpu */
+static void gen_fcmpu(DisasContext *ctx)
+{
+ TCGv_i32 crf;
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ crf = tcg_const_i32(crfD(ctx->opcode));
+ get_fpr(t0, rA(ctx->opcode));
+ get_fpr(t1, rB(ctx->opcode));
+ gen_helper_fcmpu(cpu_env, t0, t1, crf);
+ tcg_temp_free_i32(crf);
+ gen_helper_float_check_status(cpu_env);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/*** Floating-point move ***/
+/* fabs */
+/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
+static void gen_fabs(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ tcg_gen_andi_i64(t1, t0, ~(1ULL << 63));
+ set_fpr(rD(ctx->opcode), t1);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* fmr - fmr. */
+/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
+static void gen_fmr(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ set_fpr(rD(ctx->opcode), t0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+}
+
+/* fnabs */
+/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
+static void gen_fnabs(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ tcg_gen_ori_i64(t1, t0, 1ULL << 63);
+ set_fpr(rD(ctx->opcode), t1);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* fneg */
+/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
+static void gen_fneg(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ tcg_gen_xori_i64(t1, t0, 1ULL << 63);
+ set_fpr(rD(ctx->opcode), t1);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* fcpsgn: PowerPC 2.05 specification */
+/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
+static void gen_fcpsgn(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ TCGv_i64 t2;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+ get_fpr(t0, rA(ctx->opcode));
+ get_fpr(t1, rB(ctx->opcode));
+ tcg_gen_deposit_i64(t2, t0, t1, 0, 63);
+ set_fpr(rD(ctx->opcode), t2);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+static void gen_fmrgew(DisasContext *ctx)
+{
+ TCGv_i64 b0;
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ b0 = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ tcg_gen_shri_i64(b0, t0, 32);
+ get_fpr(t0, rA(ctx->opcode));
+ tcg_gen_deposit_i64(t1, t0, b0, 0, 32);
+ set_fpr(rD(ctx->opcode), t1);
+ tcg_temp_free_i64(b0);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static void gen_fmrgow(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ TCGv_i64 t2;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+ get_fpr(t0, rB(ctx->opcode));
+ get_fpr(t1, rA(ctx->opcode));
+ tcg_gen_deposit_i64(t2, t0, t1, 32, 32);
+ set_fpr(rD(ctx->opcode), t2);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*** Floating-Point status & ctrl register ***/
+
+/* mcrfs */
+static void gen_mcrfs(DisasContext *ctx)
+{
+ TCGv tmp = tcg_temp_new();
+ TCGv_i32 tmask;
+ TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
+ int bfa;
+ int nibble;
+ int shift;
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ bfa = crfS(ctx->opcode);
+ nibble = 7 - bfa;
+ shift = 4 * nibble;
+ tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
+ tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
+ tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
+ 0xf);
+ tcg_temp_free(tmp);
+ tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
+ /* Only the exception bits (including FX) should be cleared if read */
+ tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
+ ~((0xF << shift) & FP_EX_CLEAR_BITS));
+ /* FEX and VX need to be updated, so don't set fpscr directly */
+ tmask = tcg_const_i32(1 << nibble);
+ gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
+ tcg_temp_free_i32(tmask);
+ tcg_temp_free_i64(tnew_fpscr);
+}
+
+/* mffs */
+static void gen_mffs(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ tcg_gen_extu_tl_i64(t0, cpu_fpscr);
+ set_fpr(rD(ctx->opcode), t0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+ tcg_temp_free_i64(t0);
+}
+
+/* mffsl */
+static void gen_mffsl(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+
+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
+ return gen_mffs(ctx);
+ }
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ gen_reset_fpstatus();
+ tcg_gen_extu_tl_i64(t0, cpu_fpscr);
+ /* Mask everything except mode, status, and enables. */
+ tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
+ set_fpr(rD(ctx->opcode), t0);
+ tcg_temp_free_i64(t0);
+}
+
+/* mffsce */
+static void gen_mffsce(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ TCGv_i32 mask;
+
+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
+ return gen_mffs(ctx);
+ }
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+
+ t0 = tcg_temp_new_i64();
+
+ gen_reset_fpstatus();
+ tcg_gen_extu_tl_i64(t0, cpu_fpscr);
+ set_fpr(rD(ctx->opcode), t0);
+
+ /* Clear exception enable bits in the FPSCR. */
+ tcg_gen_andi_i64(t0, t0, ~FP_ENABLES);
+ mask = tcg_const_i32(0x0003);
+ gen_helper_store_fpscr(cpu_env, t0, mask);
+
+ tcg_temp_free_i32(mask);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i32 mask = tcg_const_i32(0x0001);
+
+ gen_reset_fpstatus();
+ tcg_gen_extu_tl_i64(t0, cpu_fpscr);
+ tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN);
+ set_fpr(rD(ctx->opcode), t0);
+
+ /* Mask FPSCR value to clear RN. */
+ tcg_gen_andi_i64(t0, t0, ~FP_RN);
+
+ /* Merge RN into FPSCR value. */
+ tcg_gen_or_i64(t0, t0, t1);
+
+ gen_helper_store_fpscr(cpu_env, t0, mask);
+
+ tcg_temp_free_i32(mask);
+ tcg_temp_free_i64(t0);
+}
+
+/* mffscrn */
+static void gen_mffscrn(DisasContext *ctx)
+{
+ TCGv_i64 t1;
+
+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
+ return gen_mffs(ctx);
+ }
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+
+ t1 = tcg_temp_new_i64();
+ get_fpr(t1, rB(ctx->opcode));
+ /* Mask FRB to get just RN. */
+ tcg_gen_andi_i64(t1, t1, FP_RN);
+
+ gen_helper_mffscrn(ctx, t1);
+
+ tcg_temp_free_i64(t1);
+}
+
+/* mffscrni */
+static void gen_mffscrni(DisasContext *ctx)
+{
+ TCGv_i64 t1;
+
+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
+ return gen_mffs(ctx);
+ }
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+
+ t1 = tcg_const_i64((uint64_t)RM(ctx->opcode));
+
+ gen_helper_mffscrn(ctx, t1);
+
+ tcg_temp_free_i64(t1);
+}
+
+/* mtfsb0 */
+static void gen_mtfsb0(DisasContext *ctx)
+{
+ uint8_t crb;
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ crb = 31 - crbD(ctx->opcode);
+ gen_reset_fpstatus();
+ if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
+ TCGv_i32 t0;
+ t0 = tcg_const_i32(crb);
+ gen_helper_fpscr_clrbit(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+ }
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+ }
+}
+
+/* mtfsb1 */
+static void gen_mtfsb1(DisasContext *ctx)
+{
+ uint8_t crb;
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ crb = 31 - crbD(ctx->opcode);
+ gen_reset_fpstatus();
+ /* XXX: we pretend we can only do IEEE floating-point computations */
+ if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
+ TCGv_i32 t0;
+ t0 = tcg_const_i32(crb);
+ gen_helper_fpscr_setbit(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+ }
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+ }
+ /* We can raise a deferred exception */
+ gen_helper_float_check_status(cpu_env);
+}
+
+/* mtfsf */
+static void gen_mtfsf(DisasContext *ctx)
+{
+ TCGv_i32 t0;
+ TCGv_i64 t1;
+ int flm, l, w;
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ flm = FPFLM(ctx->opcode);
+ l = FPL(ctx->opcode);
+ w = FPW(ctx->opcode);
+ if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+ return;
+ }
+ gen_reset_fpstatus();
+ if (l) {
+ t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
+ } else {
+ t0 = tcg_const_i32(flm << (w * 8));
+ }
+ t1 = tcg_temp_new_i64();
+ get_fpr(t1, rB(ctx->opcode));
+ gen_helper_store_fpscr(cpu_env, t1, t0);
+ tcg_temp_free_i32(t0);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+ }
+ /* We can raise a deferred exception */
+ gen_helper_float_check_status(cpu_env);
+ tcg_temp_free_i64(t1);
+}
+
+/* mtfsfi */
+static void gen_mtfsfi(DisasContext *ctx)
+{
+ int bf, sh, w;
+ TCGv_i64 t0;
+ TCGv_i32 t1;
+
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ w = FPW(ctx->opcode);
+ bf = FPBF(ctx->opcode);
+ if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+ return;
+ }
+ sh = (8 * w) + 7 - bf;
+ gen_reset_fpstatus();
+ t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
+ t1 = tcg_const_i32(1 << sh);
+ gen_helper_store_fpscr(cpu_env, t0, t1);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i32(t1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+ }
+ /* We can raise a deferred exception */
+ gen_helper_float_check_status(cpu_env);
+}
+
+/*** Floating-point load ***/
+#define GEN_LDF(name, ldop, opc, type) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_imm_index(ctx, EA, 0); \
+ gen_qemu_##ldop(ctx, t0, EA); \
+ set_fpr(rD(ctx->opcode), t0); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_LDUF(name, ldop, opc, type) \
+static void glue(gen_, name##u)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ if (unlikely(rA(ctx->opcode) == 0)) { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_imm_index(ctx, EA, 0); \
+ gen_qemu_##ldop(ctx, t0, EA); \
+ set_fpr(rD(ctx->opcode), t0); \
+ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_LDUXF(name, ldop, opc, type) \
+static void glue(gen_, name##ux)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ if (unlikely(rA(ctx->opcode) == 0)) { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ gen_qemu_##ldop(ctx, t0, EA); \
+ set_fpr(rD(ctx->opcode), t0); \
+ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_LDXF(name, ldop, opc2, opc3, type) \
+static void glue(gen_, name##x)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_reg_index(ctx, EA); \
+ gen_qemu_##ldop(ctx, t0, EA); \
+ set_fpr(rD(ctx->opcode), t0); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_LDFS(name, ldop, op, type) \
+GEN_LDF(name, ldop, op | 0x20, type); \
+GEN_LDUF(name, ldop, op | 0x21, type); \
+GEN_LDUXF(name, ldop, op | 0x01, type); \
+GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
+
+static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
+ gen_helper_todouble(dest, tmp);
+ tcg_temp_free_i32(tmp);
+}
+
+ /* lfd lfdu lfdux lfdx */
+GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
+ /* lfs lfsu lfsux lfsx */
+GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
+
+/* lfdepx (external PID lfdx) */
+static void gen_lfdepx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ CHK_SV;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ t0 = tcg_temp_new_i64();
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q));
+ set_fpr(rD(ctx->opcode), t0);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+/* lfdp */
+static void gen_lfdp(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_imm_index(ctx, EA, 0);
+ t0 = tcg_temp_new_i64();
+ /*
+ * We only need to swap high and low halves. gen_qemu_ld64_i64
+ * does necessary 64-bit byteswap already.
+ */
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode) + 1, t0);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode), t0);
+ } else {
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode), t0);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode) + 1, t0);
+ }
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+/* lfdpx */
+static void gen_lfdpx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ t0 = tcg_temp_new_i64();
+ /*
+ * We only need to swap high and low halves. gen_qemu_ld64_i64
+ * does necessary 64-bit byteswap already.
+ */
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode) + 1, t0);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode), t0);
+ } else {
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode), t0);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode) + 1, t0);
+ }
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+/* lfiwax */
+static void gen_lfiwax(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new_i64();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld32s(ctx, t0, EA);
+ tcg_gen_ext_tl_i64(t1, t0);
+ set_fpr(rD(ctx->opcode), t1);
+ tcg_temp_free(EA);
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* lfiwzx */
+static void gen_lfiwzx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ t0 = tcg_temp_new_i64();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld32u_i64(ctx, t0, EA);
+ set_fpr(rD(ctx->opcode), t0);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+/*** Floating-point store ***/
+#define GEN_STF(name, stop, opc, type) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_imm_index(ctx, EA, 0); \
+ get_fpr(t0, rS(ctx->opcode)); \
+ gen_qemu_##stop(ctx, t0, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_STUF(name, stop, opc, type) \
+static void glue(gen_, name##u)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ if (unlikely(rA(ctx->opcode) == 0)) { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_imm_index(ctx, EA, 0); \
+ get_fpr(t0, rS(ctx->opcode)); \
+ gen_qemu_##stop(ctx, t0, EA); \
+ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_STUXF(name, stop, opc, type) \
+static void glue(gen_, name##ux)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ if (unlikely(rA(ctx->opcode) == 0)) { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_reg_index(ctx, EA); \
+ get_fpr(t0, rS(ctx->opcode)); \
+ gen_qemu_##stop(ctx, t0, EA); \
+ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_STXF(name, stop, opc2, opc3, type) \
+static void glue(gen_, name##x)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ gen_addr_reg_index(ctx, EA); \
+ get_fpr(t0, rS(ctx->opcode)); \
+ gen_qemu_##stop(ctx, t0, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+#define GEN_STFS(name, stop, op, type) \
+GEN_STF(name, stop, op | 0x20, type); \
+GEN_STUF(name, stop, op | 0x21, type); \
+GEN_STUXF(name, stop, op | 0x01, type); \
+GEN_STXF(name, stop, 0x17, op | 0x00, type)
+
+static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ gen_helper_tosingle(tmp, src);
+ tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
+ tcg_temp_free_i32(tmp);
+}
+
+/* stfd stfdu stfdux stfdx */
+GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
+/* stfs stfsu stfsux stfsx */
+GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
+
+/* stfdepx (external PID lfdx) */
+static void gen_stfdepx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ CHK_SV;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ t0 = tcg_temp_new_i64();
+ gen_addr_reg_index(ctx, EA);
+ get_fpr(t0, rD(ctx->opcode));
+ tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q));
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+/* stfdp */
+static void gen_stfdp(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ t0 = tcg_temp_new_i64();
+ gen_addr_imm_index(ctx, EA, 0);
+ /*
+ * We only need to swap high and low halves. gen_qemu_st64_i64
+ * does necessary 64-bit byteswap already.
+ */
+ if (unlikely(ctx->le_mode)) {
+ get_fpr(t0, rD(ctx->opcode) + 1);
+ gen_qemu_st64_i64(ctx, t0, EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ get_fpr(t0, rD(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, EA);
+ } else {
+ get_fpr(t0, rD(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ get_fpr(t0, rD(ctx->opcode) + 1);
+ gen_qemu_st64_i64(ctx, t0, EA);
+ }
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+/* stfdpx */
+static void gen_stfdpx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ EA = tcg_temp_new();
+ t0 = tcg_temp_new_i64();
+ gen_addr_reg_index(ctx, EA);
+ /*
+ * We only need to swap high and low halves. gen_qemu_st64_i64
+ * does necessary 64-bit byteswap already.
+ */
+ if (unlikely(ctx->le_mode)) {
+ get_fpr(t0, rD(ctx->opcode) + 1);
+ gen_qemu_st64_i64(ctx, t0, EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ get_fpr(t0, rD(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, EA);
+ } else {
+ get_fpr(t0, rD(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ get_fpr(t0, rD(ctx->opcode) + 1);
+ gen_qemu_st64_i64(ctx, t0, EA);
+ }
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+/* Optional: */
+static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_trunc_i64_tl(t0, arg1),
+ gen_qemu_st32(ctx, t0, arg2);
+ tcg_temp_free(t0);
+}
+/* stfiwx */
+GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
+
+/* POWER2 specific instructions */
+/* Quad manipulation (load/store two floats at a time) */
+
+/* lfq */
+static void gen_lfq(DisasContext *ctx)
+{
+ int rd = rD(ctx->opcode);
+ TCGv t0;
+ TCGv_i64 t1;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new_i64();
+ gen_addr_imm_index(ctx, t0, 0);
+ gen_qemu_ld64_i64(ctx, t1, t0);
+ set_fpr(rd, t1);
+ gen_addr_add(ctx, t0, t0, 8);
+ gen_qemu_ld64_i64(ctx, t1, t0);
+ set_fpr((rd + 1) % 32, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* lfqu */
+static void gen_lfqu(DisasContext *ctx)
+{
+ int ra = rA(ctx->opcode);
+ int rd = rD(ctx->opcode);
+ TCGv t0, t1;
+ TCGv_i64 t2;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new_i64();
+ gen_addr_imm_index(ctx, t0, 0);
+ gen_qemu_ld64_i64(ctx, t2, t0);
+ set_fpr(rd, t2);
+ gen_addr_add(ctx, t1, t0, 8);
+ gen_qemu_ld64_i64(ctx, t2, t1);
+ set_fpr((rd + 1) % 32, t2);
+ if (ra != 0) {
+ tcg_gen_mov_tl(cpu_gpr[ra], t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/* lfqux */
+static void gen_lfqux(DisasContext *ctx)
+{
+ int ra = rA(ctx->opcode);
+ int rd = rD(ctx->opcode);
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ TCGv t0, t1;
+ TCGv_i64 t2;
+ t2 = tcg_temp_new_i64();
+ t0 = tcg_temp_new();
+ gen_addr_reg_index(ctx, t0);
+ gen_qemu_ld64_i64(ctx, t2, t0);
+ set_fpr(rd, t2);
+ t1 = tcg_temp_new();
+ gen_addr_add(ctx, t1, t0, 8);
+ gen_qemu_ld64_i64(ctx, t2, t1);
+ set_fpr((rd + 1) % 32, t2);
+ tcg_temp_free(t1);
+ if (ra != 0) {
+ tcg_gen_mov_tl(cpu_gpr[ra], t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t2);
+}
+
+/* lfqx */
+static void gen_lfqx(DisasContext *ctx)
+{
+ int rd = rD(ctx->opcode);
+ TCGv t0;
+ TCGv_i64 t1;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new_i64();
+ gen_addr_reg_index(ctx, t0);
+ gen_qemu_ld64_i64(ctx, t1, t0);
+ set_fpr(rd, t1);
+ gen_addr_add(ctx, t0, t0, 8);
+ gen_qemu_ld64_i64(ctx, t1, t0);
+ set_fpr((rd + 1) % 32, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* stfq */
+static void gen_stfq(DisasContext *ctx)
+{
+ int rd = rD(ctx->opcode);
+ TCGv t0;
+ TCGv_i64 t1;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new_i64();
+ gen_addr_imm_index(ctx, t0, 0);
+ get_fpr(t1, rd);
+ gen_qemu_st64_i64(ctx, t1, t0);
+ gen_addr_add(ctx, t0, t0, 8);
+ get_fpr(t1, (rd + 1) % 32);
+ gen_qemu_st64_i64(ctx, t1, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t1);
+}
+
+/* stfqu */
+static void gen_stfqu(DisasContext *ctx)
+{
+ int ra = rA(ctx->opcode);
+ int rd = rD(ctx->opcode);
+ TCGv t0, t1;
+ TCGv_i64 t2;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t2 = tcg_temp_new_i64();
+ t0 = tcg_temp_new();
+ gen_addr_imm_index(ctx, t0, 0);
+ get_fpr(t2, rd);
+ gen_qemu_st64_i64(ctx, t2, t0);
+ t1 = tcg_temp_new();
+ gen_addr_add(ctx, t1, t0, 8);
+ get_fpr(t2, (rd + 1) % 32);
+ gen_qemu_st64_i64(ctx, t2, t1);
+ tcg_temp_free(t1);
+ if (ra != 0) {
+ tcg_gen_mov_tl(cpu_gpr[ra], t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t2);
+}
+
+/* stfqux */
+static void gen_stfqux(DisasContext *ctx)
+{
+ int ra = rA(ctx->opcode);
+ int rd = rD(ctx->opcode);
+ TCGv t0, t1;
+ TCGv_i64 t2;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t2 = tcg_temp_new_i64();
+ t0 = tcg_temp_new();
+ gen_addr_reg_index(ctx, t0);
+ get_fpr(t2, rd);
+ gen_qemu_st64_i64(ctx, t2, t0);
+ t1 = tcg_temp_new();
+ gen_addr_add(ctx, t1, t0, 8);
+ get_fpr(t2, (rd + 1) % 32);
+ gen_qemu_st64_i64(ctx, t2, t1);
+ tcg_temp_free(t1);
+ if (ra != 0) {
+ tcg_gen_mov_tl(cpu_gpr[ra], t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t2);
+}
+
+/* stfqx */
+static void gen_stfqx(DisasContext *ctx)
+{
+ int rd = rD(ctx->opcode);
+ TCGv t0;
+ TCGv_i64 t1;
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t1 = tcg_temp_new_i64();
+ t0 = tcg_temp_new();
+ gen_addr_reg_index(ctx, t0);
+ get_fpr(t1, rd);
+ gen_qemu_st64_i64(ctx, t1, t0);
+ gen_addr_add(ctx, t0, t0, 8);
+ get_fpr(t1, (rd + 1) % 32);
+ gen_qemu_st64_i64(ctx, t1, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free_i64(t1);
+}
+
+#undef _GEN_FLOAT_ACB
+#undef GEN_FLOAT_ACB
+#undef _GEN_FLOAT_AB
+#undef GEN_FLOAT_AB
+#undef _GEN_FLOAT_AC
+#undef GEN_FLOAT_AC
+#undef GEN_FLOAT_B
+#undef GEN_FLOAT_BS
+
+#undef GEN_LDF
+#undef GEN_LDUF
+#undef GEN_LDUXF
+#undef GEN_LDXF
+#undef GEN_LDFS
+
+#undef GEN_STF
+#undef GEN_STUF
+#undef GEN_STUXF
+#undef GEN_STXF
+#undef GEN_STFS
+++ /dev/null
-/*
- * translate-fp.c
- *
- * Standard FPU translation
- */
-
-static inline void gen_reset_fpstatus(void)
-{
- gen_helper_reset_fpstatus(cpu_env);
-}
-
-static inline void gen_compute_fprf_float64(TCGv_i64 arg)
-{
- gen_helper_compute_fprf_float64(cpu_env, arg);
- gen_helper_float_check_status(cpu_env);
-}
-
-#if defined(TARGET_PPC64)
-static void gen_set_cr1_from_fpscr(DisasContext *ctx)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
- tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
- tcg_temp_free_i32(tmp);
-}
-#else
-static void gen_set_cr1_from_fpscr(DisasContext *ctx)
-{
- tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
-}
-#endif
-
-/*** Floating-Point arithmetic ***/
-#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
-static void gen_f##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
- TCGv_i64 t3; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- t3 = tcg_temp_new_i64(); \
- gen_reset_fpstatus(); \
- get_fpr(t0, rA(ctx->opcode)); \
- get_fpr(t1, rC(ctx->opcode)); \
- get_fpr(t2, rB(ctx->opcode)); \
- gen_helper_f##op(t3, cpu_env, t0, t1, t2); \
- if (isfloat) { \
- gen_helper_frsp(t3, cpu_env, t3); \
- } \
- set_fpr(rD(ctx->opcode), t3); \
- if (set_fprf) { \
- gen_compute_fprf_float64(t3); \
- } \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(t2); \
- tcg_temp_free_i64(t3); \
-}
-
-#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
-_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
-_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
-
-#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
-static void gen_f##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- gen_reset_fpstatus(); \
- get_fpr(t0, rA(ctx->opcode)); \
- get_fpr(t1, rB(ctx->opcode)); \
- gen_helper_f##op(t2, cpu_env, t0, t1); \
- if (isfloat) { \
- gen_helper_frsp(t2, cpu_env, t2); \
- } \
- set_fpr(rD(ctx->opcode), t2); \
- if (set_fprf) { \
- gen_compute_fprf_float64(t2); \
- } \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(t2); \
-}
-#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
-_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
-
-#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
-static void gen_f##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- gen_reset_fpstatus(); \
- get_fpr(t0, rA(ctx->opcode)); \
- get_fpr(t1, rC(ctx->opcode)); \
- gen_helper_f##op(t2, cpu_env, t0, t1); \
- if (isfloat) { \
- gen_helper_frsp(t2, cpu_env, t2); \
- } \
- set_fpr(rD(ctx->opcode), t2); \
- if (set_fprf) { \
- gen_compute_fprf_float64(t2); \
- } \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(t2); \
-}
-#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
-_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
-
-#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
-static void gen_f##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- gen_reset_fpstatus(); \
- get_fpr(t0, rB(ctx->opcode)); \
- gen_helper_f##name(t1, cpu_env, t0); \
- set_fpr(rD(ctx->opcode), t1); \
- if (set_fprf) { \
- gen_compute_fprf_float64(t1); \
- } \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
-}
-
-#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
-static void gen_f##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- gen_reset_fpstatus(); \
- get_fpr(t0, rB(ctx->opcode)); \
- gen_helper_f##name(t1, cpu_env, t0); \
- set_fpr(rD(ctx->opcode), t1); \
- if (set_fprf) { \
- gen_compute_fprf_float64(t1); \
- } \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
-}
-
-/* fadd - fadds */
-GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
-/* fdiv - fdivs */
-GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
-/* fmul - fmuls */
-GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
-
-/* fre */
-GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
-
-/* fres */
-GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
-
-/* frsqrte */
-GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
-
-/* frsqrtes */
-static void gen_frsqrtes(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- get_fpr(t0, rB(ctx->opcode));
- gen_helper_frsqrte(t1, cpu_env, t0);
- gen_helper_frsp(t1, cpu_env, t1);
- set_fpr(rD(ctx->opcode), t1);
- gen_compute_fprf_float64(t1);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* fsel */
-_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
-/* fsub - fsubs */
-GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
-/* Optional: */
-
-/* fsqrt */
-static void gen_fsqrt(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- get_fpr(t0, rB(ctx->opcode));
- gen_helper_fsqrt(t1, cpu_env, t0);
- set_fpr(rD(ctx->opcode), t1);
- gen_compute_fprf_float64(t1);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static void gen_fsqrts(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- get_fpr(t0, rB(ctx->opcode));
- gen_helper_fsqrt(t1, cpu_env, t0);
- gen_helper_frsp(t1, cpu_env, t1);
- set_fpr(rD(ctx->opcode), t1);
- gen_compute_fprf_float64(t1);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/*** Floating-Point multiply-and-add ***/
-/* fmadd - fmadds */
-GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
-/* fmsub - fmsubs */
-GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
-/* fnmadd - fnmadds */
-GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
-/* fnmsub - fnmsubs */
-GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
-
-/*** Floating-Point round & convert ***/
-/* fctiw */
-GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
-/* fctiwu */
-GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
-/* fctiwz */
-GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
-/* fctiwuz */
-GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
-/* frsp */
-GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
-/* fcfid */
-GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
-/* fcfids */
-GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
-/* fcfidu */
-GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
-/* fcfidus */
-GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
-/* fctid */
-GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
-/* fctidu */
-GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
-/* fctidz */
-GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
-/* fctidu */
-GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
-
-/* frin */
-GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
-/* friz */
-GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
-/* frip */
-GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
-/* frim */
-GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
-
-static void gen_ftdiv(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rA(ctx->opcode));
- get_fpr(t1, rB(ctx->opcode));
- gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static void gen_ftsqrt(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0);
- tcg_temp_free_i64(t0);
-}
-
-
-
-/*** Floating-Point compare ***/
-
-/* fcmpo */
-static void gen_fcmpo(DisasContext *ctx)
-{
- TCGv_i32 crf;
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- crf = tcg_const_i32(crfD(ctx->opcode));
- get_fpr(t0, rA(ctx->opcode));
- get_fpr(t1, rB(ctx->opcode));
- gen_helper_fcmpo(cpu_env, t0, t1, crf);
- tcg_temp_free_i32(crf);
- gen_helper_float_check_status(cpu_env);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* fcmpu */
-static void gen_fcmpu(DisasContext *ctx)
-{
- TCGv_i32 crf;
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- crf = tcg_const_i32(crfD(ctx->opcode));
- get_fpr(t0, rA(ctx->opcode));
- get_fpr(t1, rB(ctx->opcode));
- gen_helper_fcmpu(cpu_env, t0, t1, crf);
- tcg_temp_free_i32(crf);
- gen_helper_float_check_status(cpu_env);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/*** Floating-point move ***/
-/* fabs */
-/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
-static void gen_fabs(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_andi_i64(t1, t0, ~(1ULL << 63));
- set_fpr(rD(ctx->opcode), t1);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* fmr - fmr. */
-/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
-static void gen_fmr(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- set_fpr(rD(ctx->opcode), t0);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
-}
-
-/* fnabs */
-/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
-static void gen_fnabs(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_ori_i64(t1, t0, 1ULL << 63);
- set_fpr(rD(ctx->opcode), t1);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* fneg */
-/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
-static void gen_fneg(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_xori_i64(t1, t0, 1ULL << 63);
- set_fpr(rD(ctx->opcode), t1);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* fcpsgn: PowerPC 2.05 specification */
-/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
-static void gen_fcpsgn(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- TCGv_i64 t2;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- t2 = tcg_temp_new_i64();
- get_fpr(t0, rA(ctx->opcode));
- get_fpr(t1, rB(ctx->opcode));
- tcg_gen_deposit_i64(t2, t0, t1, 0, 63);
- set_fpr(rD(ctx->opcode), t2);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
-}
-
-static void gen_fmrgew(DisasContext *ctx)
-{
- TCGv_i64 b0;
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- b0 = tcg_temp_new_i64();
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- tcg_gen_shri_i64(b0, t0, 32);
- get_fpr(t0, rA(ctx->opcode));
- tcg_gen_deposit_i64(t1, t0, b0, 0, 32);
- set_fpr(rD(ctx->opcode), t1);
- tcg_temp_free_i64(b0);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static void gen_fmrgow(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i64 t1;
- TCGv_i64 t2;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- t2 = tcg_temp_new_i64();
- get_fpr(t0, rB(ctx->opcode));
- get_fpr(t1, rA(ctx->opcode));
- tcg_gen_deposit_i64(t2, t0, t1, 32, 32);
- set_fpr(rD(ctx->opcode), t2);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
-}
-
-/*** Floating-Point status & ctrl register ***/
-
-/* mcrfs */
-static void gen_mcrfs(DisasContext *ctx)
-{
- TCGv tmp = tcg_temp_new();
- TCGv_i32 tmask;
- TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
- int bfa;
- int nibble;
- int shift;
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- bfa = crfS(ctx->opcode);
- nibble = 7 - bfa;
- shift = 4 * nibble;
- tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
- tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
- tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
- 0xf);
- tcg_temp_free(tmp);
- tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
- /* Only the exception bits (including FX) should be cleared if read */
- tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
- ~((0xF << shift) & FP_EX_CLEAR_BITS));
- /* FEX and VX need to be updated, so don't set fpscr directly */
- tmask = tcg_const_i32(1 << nibble);
- gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
- tcg_temp_free_i32(tmask);
- tcg_temp_free_i64(tnew_fpscr);
-}
-
-/* mffs */
-static void gen_mffs(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- set_fpr(rD(ctx->opcode), t0);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
-}
-
-/* mffsl */
-static void gen_mffsl(DisasContext *ctx)
-{
- TCGv_i64 t0;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- /* Mask everything except mode, status, and enables. */
- tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
- set_fpr(rD(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
-/* mffsce */
-static void gen_mffsce(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i32 mask;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
-
- t0 = tcg_temp_new_i64();
-
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- set_fpr(rD(ctx->opcode), t0);
-
- /* Clear exception enable bits in the FPSCR. */
- tcg_gen_andi_i64(t0, t0, ~FP_ENABLES);
- mask = tcg_const_i32(0x0003);
- gen_helper_store_fpscr(cpu_env, t0, mask);
-
- tcg_temp_free_i32(mask);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i32 mask = tcg_const_i32(0x0001);
-
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN);
- set_fpr(rD(ctx->opcode), t0);
-
- /* Mask FPSCR value to clear RN. */
- tcg_gen_andi_i64(t0, t0, ~FP_RN);
-
- /* Merge RN into FPSCR value. */
- tcg_gen_or_i64(t0, t0, t1);
-
- gen_helper_store_fpscr(cpu_env, t0, mask);
-
- tcg_temp_free_i32(mask);
- tcg_temp_free_i64(t0);
-}
-
-/* mffscrn */
-static void gen_mffscrn(DisasContext *ctx)
-{
- TCGv_i64 t1;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
-
- t1 = tcg_temp_new_i64();
- get_fpr(t1, rB(ctx->opcode));
- /* Mask FRB to get just RN. */
- tcg_gen_andi_i64(t1, t1, FP_RN);
-
- gen_helper_mffscrn(ctx, t1);
-
- tcg_temp_free_i64(t1);
-}
-
-/* mffscrni */
-static void gen_mffscrni(DisasContext *ctx)
-{
- TCGv_i64 t1;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
-
- t1 = tcg_const_i64((uint64_t)RM(ctx->opcode));
-
- gen_helper_mffscrn(ctx, t1);
-
- tcg_temp_free_i64(t1);
-}
-
-/* mtfsb0 */
-static void gen_mtfsb0(DisasContext *ctx)
-{
- uint8_t crb;
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- crb = 31 - crbD(ctx->opcode);
- gen_reset_fpstatus();
- if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
- TCGv_i32 t0;
- t0 = tcg_const_i32(crb);
- gen_helper_fpscr_clrbit(cpu_env, t0);
- tcg_temp_free_i32(t0);
- }
- if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
- tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
- }
-}
-
-/* mtfsb1 */
-static void gen_mtfsb1(DisasContext *ctx)
-{
- uint8_t crb;
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- crb = 31 - crbD(ctx->opcode);
- gen_reset_fpstatus();
- /* XXX: we pretend we can only do IEEE floating-point computations */
- if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
- TCGv_i32 t0;
- t0 = tcg_const_i32(crb);
- gen_helper_fpscr_setbit(cpu_env, t0);
- tcg_temp_free_i32(t0);
- }
- if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
- tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
- }
- /* We can raise a deferred exception */
- gen_helper_float_check_status(cpu_env);
-}
-
-/* mtfsf */
-static void gen_mtfsf(DisasContext *ctx)
-{
- TCGv_i32 t0;
- TCGv_i64 t1;
- int flm, l, w;
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- flm = FPFLM(ctx->opcode);
- l = FPL(ctx->opcode);
- w = FPW(ctx->opcode);
- if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- gen_reset_fpstatus();
- if (l) {
- t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
- } else {
- t0 = tcg_const_i32(flm << (w * 8));
- }
- t1 = tcg_temp_new_i64();
- get_fpr(t1, rB(ctx->opcode));
- gen_helper_store_fpscr(cpu_env, t1, t0);
- tcg_temp_free_i32(t0);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
- tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
- }
- /* We can raise a deferred exception */
- gen_helper_float_check_status(cpu_env);
- tcg_temp_free_i64(t1);
-}
-
-/* mtfsfi */
-static void gen_mtfsfi(DisasContext *ctx)
-{
- int bf, sh, w;
- TCGv_i64 t0;
- TCGv_i32 t1;
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- w = FPW(ctx->opcode);
- bf = FPBF(ctx->opcode);
- if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- sh = (8 * w) + 7 - bf;
- gen_reset_fpstatus();
- t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
- t1 = tcg_const_i32(1 << sh);
- gen_helper_store_fpscr(cpu_env, t0, t1);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i32(t1);
- if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
- tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
- }
- /* We can raise a deferred exception */
- gen_helper_float_check_status(cpu_env);
-}
-
-/*** Floating-point load ***/
-#define GEN_LDF(name, ldop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDUF(name, ldop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDUXF(name, ldop, opc, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDXF(name, ldop, opc2, opc3, type) \
-static void glue(gen_, name##x)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDFS(name, ldop, op, type) \
-GEN_LDF(name, ldop, op | 0x20, type); \
-GEN_LDUF(name, ldop, op | 0x21, type); \
-GEN_LDUXF(name, ldop, op | 0x01, type); \
-GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-
-static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
- gen_helper_todouble(dest, tmp);
- tcg_temp_free_i32(tmp);
-}
-
- /* lfd lfdu lfdux lfdx */
-GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
- /* lfs lfsu lfsux lfsx */
-GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
-
-/* lfdepx (external PID lfdx) */
-static void gen_lfdepx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- CHK_SV;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- t0 = tcg_temp_new_i64();
- gen_addr_reg_index(ctx, EA);
- tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q));
- set_fpr(rD(ctx->opcode), t0);
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-/* lfdp */
-static void gen_lfdp(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0);
- t0 = tcg_temp_new_i64();
- /*
- * We only need to swap high and low halves. gen_qemu_ld64_i64
- * does necessary 64-bit byteswap already.
- */
- if (unlikely(ctx->le_mode)) {
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode) + 1, t0);
- tcg_gen_addi_tl(EA, EA, 8);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode), t0);
- } else {
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode), t0);
- tcg_gen_addi_tl(EA, EA, 8);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode) + 1, t0);
- }
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-/* lfdpx */
-static void gen_lfdpx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- t0 = tcg_temp_new_i64();
- /*
- * We only need to swap high and low halves. gen_qemu_ld64_i64
- * does necessary 64-bit byteswap already.
- */
- if (unlikely(ctx->le_mode)) {
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode) + 1, t0);
- tcg_gen_addi_tl(EA, EA, 8);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode), t0);
- } else {
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode), t0);
- tcg_gen_addi_tl(EA, EA, 8);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode) + 1, t0);
- }
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-/* lfiwax */
-static void gen_lfiwax(DisasContext *ctx)
-{
- TCGv EA;
- TCGv t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- t0 = tcg_temp_new();
- t1 = tcg_temp_new_i64();
- gen_addr_reg_index(ctx, EA);
- gen_qemu_ld32s(ctx, t0, EA);
- tcg_gen_ext_tl_i64(t1, t0);
- set_fpr(rD(ctx->opcode), t1);
- tcg_temp_free(EA);
- tcg_temp_free(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* lfiwzx */
-static void gen_lfiwzx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- t0 = tcg_temp_new_i64();
- gen_addr_reg_index(ctx, EA);
- gen_qemu_ld32u_i64(ctx, t0, EA);
- set_fpr(rD(ctx->opcode), t0);
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-/*** Floating-point store ***/
-#define GEN_STF(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STUF(name, stop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STUXF(name, stop, opc, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STXF(name, stop, opc2, opc3, type) \
-static void glue(gen_, name##x)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STFS(name, stop, op, type) \
-GEN_STF(name, stop, op | 0x20, type); \
-GEN_STUF(name, stop, op | 0x21, type); \
-GEN_STUXF(name, stop, op | 0x01, type); \
-GEN_STXF(name, stop, 0x17, op | 0x00, type)
-
-static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- gen_helper_tosingle(tmp, src);
- tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
- tcg_temp_free_i32(tmp);
-}
-
-/* stfd stfdu stfdux stfdx */
-GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
-/* stfs stfsu stfsux stfsx */
-GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
-
-/* stfdepx (external PID lfdx) */
-static void gen_stfdepx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- CHK_SV;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- t0 = tcg_temp_new_i64();
- gen_addr_reg_index(ctx, EA);
- get_fpr(t0, rD(ctx->opcode));
- tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q));
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-/* stfdp */
-static void gen_stfdp(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- t0 = tcg_temp_new_i64();
- gen_addr_imm_index(ctx, EA, 0);
- /*
- * We only need to swap high and low halves. gen_qemu_st64_i64
- * does necessary 64-bit byteswap already.
- */
- if (unlikely(ctx->le_mode)) {
- get_fpr(t0, rD(ctx->opcode) + 1);
- gen_qemu_st64_i64(ctx, t0, EA);
- tcg_gen_addi_tl(EA, EA, 8);
- get_fpr(t0, rD(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, EA);
- } else {
- get_fpr(t0, rD(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, EA);
- tcg_gen_addi_tl(EA, EA, 8);
- get_fpr(t0, rD(ctx->opcode) + 1);
- gen_qemu_st64_i64(ctx, t0, EA);
- }
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-/* stfdpx */
-static void gen_stfdpx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_FLOAT);
- EA = tcg_temp_new();
- t0 = tcg_temp_new_i64();
- gen_addr_reg_index(ctx, EA);
- /*
- * We only need to swap high and low halves. gen_qemu_st64_i64
- * does necessary 64-bit byteswap already.
- */
- if (unlikely(ctx->le_mode)) {
- get_fpr(t0, rD(ctx->opcode) + 1);
- gen_qemu_st64_i64(ctx, t0, EA);
- tcg_gen_addi_tl(EA, EA, 8);
- get_fpr(t0, rD(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, EA);
- } else {
- get_fpr(t0, rD(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, EA);
- tcg_gen_addi_tl(EA, EA, 8);
- get_fpr(t0, rD(ctx->opcode) + 1);
- gen_qemu_st64_i64(ctx, t0, EA);
- }
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-/* Optional: */
-static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_trunc_i64_tl(t0, arg1),
- gen_qemu_st32(ctx, t0, arg2);
- tcg_temp_free(t0);
-}
-/* stfiwx */
-GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
-
-/* POWER2 specific instructions */
-/* Quad manipulation (load/store two floats at a time) */
-
-/* lfq */
-static void gen_lfq(DisasContext *ctx)
-{
- int rd = rD(ctx->opcode);
- TCGv t0;
- TCGv_i64 t1;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t0 = tcg_temp_new();
- t1 = tcg_temp_new_i64();
- gen_addr_imm_index(ctx, t0, 0);
- gen_qemu_ld64_i64(ctx, t1, t0);
- set_fpr(rd, t1);
- gen_addr_add(ctx, t0, t0, 8);
- gen_qemu_ld64_i64(ctx, t1, t0);
- set_fpr((rd + 1) % 32, t1);
- tcg_temp_free(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* lfqu */
-static void gen_lfqu(DisasContext *ctx)
-{
- int ra = rA(ctx->opcode);
- int rd = rD(ctx->opcode);
- TCGv t0, t1;
- TCGv_i64 t2;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- t2 = tcg_temp_new_i64();
- gen_addr_imm_index(ctx, t0, 0);
- gen_qemu_ld64_i64(ctx, t2, t0);
- set_fpr(rd, t2);
- gen_addr_add(ctx, t1, t0, 8);
- gen_qemu_ld64_i64(ctx, t2, t1);
- set_fpr((rd + 1) % 32, t2);
- if (ra != 0) {
- tcg_gen_mov_tl(cpu_gpr[ra], t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free_i64(t2);
-}
-
-/* lfqux */
-static void gen_lfqux(DisasContext *ctx)
-{
- int ra = rA(ctx->opcode);
- int rd = rD(ctx->opcode);
- gen_set_access_type(ctx, ACCESS_FLOAT);
- TCGv t0, t1;
- TCGv_i64 t2;
- t2 = tcg_temp_new_i64();
- t0 = tcg_temp_new();
- gen_addr_reg_index(ctx, t0);
- gen_qemu_ld64_i64(ctx, t2, t0);
- set_fpr(rd, t2);
- t1 = tcg_temp_new();
- gen_addr_add(ctx, t1, t0, 8);
- gen_qemu_ld64_i64(ctx, t2, t1);
- set_fpr((rd + 1) % 32, t2);
- tcg_temp_free(t1);
- if (ra != 0) {
- tcg_gen_mov_tl(cpu_gpr[ra], t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free_i64(t2);
-}
-
-/* lfqx */
-static void gen_lfqx(DisasContext *ctx)
-{
- int rd = rD(ctx->opcode);
- TCGv t0;
- TCGv_i64 t1;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t0 = tcg_temp_new();
- t1 = tcg_temp_new_i64();
- gen_addr_reg_index(ctx, t0);
- gen_qemu_ld64_i64(ctx, t1, t0);
- set_fpr(rd, t1);
- gen_addr_add(ctx, t0, t0, 8);
- gen_qemu_ld64_i64(ctx, t1, t0);
- set_fpr((rd + 1) % 32, t1);
- tcg_temp_free(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* stfq */
-static void gen_stfq(DisasContext *ctx)
-{
- int rd = rD(ctx->opcode);
- TCGv t0;
- TCGv_i64 t1;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t0 = tcg_temp_new();
- t1 = tcg_temp_new_i64();
- gen_addr_imm_index(ctx, t0, 0);
- get_fpr(t1, rd);
- gen_qemu_st64_i64(ctx, t1, t0);
- gen_addr_add(ctx, t0, t0, 8);
- get_fpr(t1, (rd + 1) % 32);
- gen_qemu_st64_i64(ctx, t1, t0);
- tcg_temp_free(t0);
- tcg_temp_free_i64(t1);
-}
-
-/* stfqu */
-static void gen_stfqu(DisasContext *ctx)
-{
- int ra = rA(ctx->opcode);
- int rd = rD(ctx->opcode);
- TCGv t0, t1;
- TCGv_i64 t2;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t2 = tcg_temp_new_i64();
- t0 = tcg_temp_new();
- gen_addr_imm_index(ctx, t0, 0);
- get_fpr(t2, rd);
- gen_qemu_st64_i64(ctx, t2, t0);
- t1 = tcg_temp_new();
- gen_addr_add(ctx, t1, t0, 8);
- get_fpr(t2, (rd + 1) % 32);
- gen_qemu_st64_i64(ctx, t2, t1);
- tcg_temp_free(t1);
- if (ra != 0) {
- tcg_gen_mov_tl(cpu_gpr[ra], t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free_i64(t2);
-}
-
-/* stfqux */
-static void gen_stfqux(DisasContext *ctx)
-{
- int ra = rA(ctx->opcode);
- int rd = rD(ctx->opcode);
- TCGv t0, t1;
- TCGv_i64 t2;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t2 = tcg_temp_new_i64();
- t0 = tcg_temp_new();
- gen_addr_reg_index(ctx, t0);
- get_fpr(t2, rd);
- gen_qemu_st64_i64(ctx, t2, t0);
- t1 = tcg_temp_new();
- gen_addr_add(ctx, t1, t0, 8);
- get_fpr(t2, (rd + 1) % 32);
- gen_qemu_st64_i64(ctx, t2, t1);
- tcg_temp_free(t1);
- if (ra != 0) {
- tcg_gen_mov_tl(cpu_gpr[ra], t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free_i64(t2);
-}
-
-/* stfqx */
-static void gen_stfqx(DisasContext *ctx)
-{
- int rd = rD(ctx->opcode);
- TCGv t0;
- TCGv_i64 t1;
- gen_set_access_type(ctx, ACCESS_FLOAT);
- t1 = tcg_temp_new_i64();
- t0 = tcg_temp_new();
- gen_addr_reg_index(ctx, t0);
- get_fpr(t1, rd);
- gen_qemu_st64_i64(ctx, t1, t0);
- gen_addr_add(ctx, t0, t0, 8);
- get_fpr(t1, (rd + 1) % 32);
- gen_qemu_st64_i64(ctx, t1, t0);
- tcg_temp_free(t0);
- tcg_temp_free_i64(t1);
-}
-
-#undef _GEN_FLOAT_ACB
-#undef GEN_FLOAT_ACB
-#undef _GEN_FLOAT_AB
-#undef GEN_FLOAT_AB
-#undef _GEN_FLOAT_AC
-#undef GEN_FLOAT_AC
-#undef GEN_FLOAT_B
-#undef GEN_FLOAT_BS
-
-#undef GEN_LDF
-#undef GEN_LDUF
-#undef GEN_LDUXF
-#undef GEN_LDXF
-#undef GEN_LDFS
-
-#undef GEN_STF
-#undef GEN_STUF
-#undef GEN_STUXF
-#undef GEN_STXF
-#undef GEN_STFS
--- /dev/null
+#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
+GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
+#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
+_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
+_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
+#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
+#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
+_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
+_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
+#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
+#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
+_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
+_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
+#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
+GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
+#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
+GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
+
+GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
+GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
+GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
+GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
+GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
+GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
+_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
+GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
+GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
+GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
+GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
+GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
+GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
+GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
+GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
+GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
+GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
+GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
+GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
+GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
+GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
+GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
+GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
+GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
+
+#define GEN_LDF(name, ldop, opc, type) \
+GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
+#define GEN_LDUF(name, ldop, opc, type) \
+GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
+#define GEN_LDUXF(name, ldop, opc, type) \
+GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
+#define GEN_LDXF(name, ldop, opc2, opc3, type) \
+GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
+#define GEN_LDFS(name, ldop, op, type) \
+GEN_LDF(name, ldop, op | 0x20, type) \
+GEN_LDUF(name, ldop, op | 0x21, type) \
+GEN_LDUXF(name, ldop, op | 0x01, type) \
+GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
+
+GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
+GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
+GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
+GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
+GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
+
+#define GEN_STF(name, stop, opc, type) \
+GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
+#define GEN_STUF(name, stop, opc, type) \
+GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
+#define GEN_STUXF(name, stop, opc, type) \
+GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
+#define GEN_STXF(name, stop, opc2, opc3, type) \
+GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
+#define GEN_STFS(name, stop, op, type) \
+GEN_STF(name, stop, op | 0x20, type) \
+GEN_STUF(name, stop, op | 0x21, type) \
+GEN_STUXF(name, stop, op | 0x01, type) \
+GEN_STXF(name, stop, 0x17, op | 0x00, type)
+
+GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
+GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
+GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
+GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
+GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
+
+GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
+GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
+GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
+GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
+GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
+GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
+GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
+GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
+ PPC2_ISA300),
+GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
+ PPC2_ISA300),
+GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
+ PPC_NONE),
+GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT,
+ PPC_NONE),
+GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
+GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
+GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
+GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
+++ /dev/null
-#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
-GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
-#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
-_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
-_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
-#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
-GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
-#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
-_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
-#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
-GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
-#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
-_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
-#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
-GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
-#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
-GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
-
-GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
-GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
-GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
-GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
-GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
-_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
-GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
-GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
-GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
-GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
-GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
-GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
-GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
-GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
-GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
-GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
-GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
-GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
-GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
-GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
-
-#define GEN_LDF(name, ldop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUF(name, ldop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUXF(name, ldop, opc, type) \
-GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
-#define GEN_LDXF(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_LDFS(name, ldop, op, type) \
-GEN_LDF(name, ldop, op | 0x20, type) \
-GEN_LDUF(name, ldop, op | 0x21, type) \
-GEN_LDUXF(name, ldop, op | 0x01, type) \
-GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-
-GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
-GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
-GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
-GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
-GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
-
-#define GEN_STF(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUF(name, stop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUXF(name, stop, opc, type) \
-GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
-#define GEN_STXF(name, stop, opc2, opc3, type) \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_STFS(name, stop, op, type) \
-GEN_STF(name, stop, op | 0x20, type) \
-GEN_STUF(name, stop, op | 0x21, type) \
-GEN_STUXF(name, stop, op | 0x01, type) \
-GEN_STXF(name, stop, 0x17, op | 0x00, type)
-
-GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
-GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
-GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
-GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
-GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
-
-GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
-GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
-GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
-GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
-GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
-GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
-GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
-GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
-GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
-GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
- PPC2_ISA300),
-GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
- PPC2_ISA300),
-GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
- PPC_NONE),
-GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT,
- PPC_NONE),
-GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
-GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
-GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
-GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
--- /dev/null
+/*
+ * translate-spe.c
+ *
+ * Freescale SPE extension translation
+ */
+
+/*** SPE extension ***/
+/* Register moves */
+
+static inline void gen_evmra(DisasContext *ctx)
+{
+
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ /* tmp := rA_lo + rA_hi << 32 */
+ tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)],
+ cpu_gprh[rA(ctx->opcode)]);
+
+ /* spe_acc := tmp */
+ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_temp_free_i64(tmp);
+
+ /* rD := rA */
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
+}
+
+static inline void gen_load_gpr64(TCGv_i64 t, int reg)
+{
+ tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
+}
+
+static inline void gen_store_gpr64(int reg, TCGv_i64 t)
+{
+ tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
+}
+
+#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if (Rc(ctx->opcode)) \
+ gen_##name1(ctx); \
+ else \
+ gen_##name0(ctx); \
+}
+
+/* Handler for undefined SPE opcodes */
+static inline void gen_speundef(DisasContext *ctx)
+{
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+}
+
+/* SPE logic */
+#define GEN_SPEOP_LOGIC2(name, tcg_op) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
+ cpu_gpr[rB(ctx->opcode)]); \
+ tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
+ cpu_gprh[rB(ctx->opcode)]); \
+}
+
+GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
+GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
+GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
+GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
+GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
+GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
+GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
+GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
+
+/* SPE logic immediate */
+#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_opi(t0, t0, rB(ctx->opcode)); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
+ tcg_opi(t0, t0, rB(ctx->opcode)); \
+ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
+ \
+ tcg_temp_free_i32(t0); \
+}
+GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
+GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
+GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
+GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
+
+/* SPE arithmetic */
+#define GEN_SPEOP_ARITH1(name, tcg_op) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_op(t0, t0); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
+ tcg_op(t0, t0); \
+ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
+ \
+ tcg_temp_free_i32(t0); \
+}
+
+GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32);
+GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
+GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
+GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
+static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
+{
+ tcg_gen_addi_i32(ret, arg1, 0x8000);
+ tcg_gen_ext16u_i32(ret, ret);
+}
+GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
+GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
+GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
+
+#define GEN_SPEOP_ARITH2(name, tcg_op) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0, t1; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ t1 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_op(t0, t0, t1); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
+ tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
+ tcg_op(t0, t0, t1); \
+ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
+ \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_i32(t1); \
+}
+
+static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
+
+ /* No error here: 6 bits are used */
+ tcg_gen_andi_i32(t0, arg2, 0x3F);
+ tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
+ tcg_gen_shr_i32(ret, arg1, t0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_movi_i32(ret, 0);
+ gen_set_label(l2);
+ tcg_temp_free_i32(t0);
+}
+GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
+static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
+
+ /* No error here: 6 bits are used */
+ tcg_gen_andi_i32(t0, arg2, 0x3F);
+ tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
+ tcg_gen_sar_i32(ret, arg1, t0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_movi_i32(ret, 0);
+ gen_set_label(l2);
+ tcg_temp_free_i32(t0);
+}
+GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
+static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
+
+ /* No error here: 6 bits are used */
+ tcg_gen_andi_i32(t0, arg2, 0x3F);
+ tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
+ tcg_gen_shl_i32(ret, arg1, t0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_movi_i32(ret, 0);
+ gen_set_label(l2);
+ tcg_temp_free_i32(t0);
+}
+GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
+static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_andi_i32(t0, arg2, 0x1F);
+ tcg_gen_rotl_i32(ret, arg1, t0);
+ tcg_temp_free_i32(t0);
+}
+GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
+static inline void gen_evmergehi(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
+}
+GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
+static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ tcg_gen_sub_i32(ret, arg2, arg1);
+}
+GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
+
+/* SPE arithmetic immediate */
+#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_op(t0, t0, rA(ctx->opcode)); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
+ tcg_op(t0, t0, rA(ctx->opcode)); \
+ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
+ \
+ tcg_temp_free_i32(t0); \
+}
+GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
+GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
+
+/* SPE comparison */
+#define GEN_SPEOP_COMP(name, tcg_cond) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ TCGLabel *l1 = gen_new_label(); \
+ TCGLabel *l2 = gen_new_label(); \
+ TCGLabel *l3 = gen_new_label(); \
+ TCGLabel *l4 = gen_new_label(); \
+ \
+ tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
+ tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
+ \
+ tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
+ cpu_gpr[rB(ctx->opcode)], l1); \
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
+ tcg_gen_br(l2); \
+ gen_set_label(l1); \
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
+ CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
+ gen_set_label(l2); \
+ tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
+ cpu_gprh[rB(ctx->opcode)], l3); \
+ tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
+ ~(CRF_CH | CRF_CH_AND_CL)); \
+ tcg_gen_br(l4); \
+ gen_set_label(l3); \
+ tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
+ CRF_CH | CRF_CH_OR_CL); \
+ gen_set_label(l4); \
+}
+GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
+GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
+GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
+GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
+GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
+
+/* SPE misc */
+static inline void gen_brinc(DisasContext *ctx)
+{
+ /* Note: brinc is usable even if SPE is disabled */
+ gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
+ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+}
+static inline void gen_evmergelo(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+}
+static inline void gen_evmergehilo(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
+}
+static inline void gen_evmergelohi(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ if (rD(ctx->opcode) == rA(ctx->opcode)) {
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
+ tcg_temp_free(tmp);
+ } else {
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ }
+}
+static inline void gen_evsplati(DisasContext *ctx)
+{
+ uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
+
+ tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
+ tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
+}
+static inline void gen_evsplatfi(DisasContext *ctx)
+{
+ uint64_t imm = rA(ctx->opcode) << 27;
+
+ tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
+ tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
+}
+
+static inline void gen_evsel(DisasContext *ctx)
+{
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGLabel *l3 = gen_new_label();
+ TCGLabel *l4 = gen_new_label();
+ TCGv_i32 t0 = tcg_temp_local_new_i32();
+
+ tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
+ gen_set_label(l2);
+ tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_br(l4);
+ gen_set_label(l3);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+ gen_set_label(l4);
+ tcg_temp_free_i32(t0);
+}
+
+static void gen_evsel0(DisasContext *ctx)
+{
+ gen_evsel(ctx);
+}
+
+static void gen_evsel1(DisasContext *ctx)
+{
+ gen_evsel(ctx);
+}
+
+static void gen_evsel2(DisasContext *ctx)
+{
+ gen_evsel(ctx);
+}
+
+static void gen_evsel3(DisasContext *ctx)
+{
+ gen_evsel(ctx);
+}
+
+/* Multiply */
+
+static inline void gen_evmwumi(DisasContext *ctx)
+{
+ TCGv_i64 t0, t1;
+
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ /* t0 := rA; t1 := rB */
+ tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_ext32u_i64(t0, t0);
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_ext32u_i64(t1, t1);
+
+ tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
+
+ gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static inline void gen_evmwumia(DisasContext *ctx)
+{
+ TCGv_i64 tmp;
+
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+
+ gen_evmwumi(ctx); /* rD := rA * rB */
+
+ tmp = tcg_temp_new_i64();
+
+ /* acc := rD */
+ gen_load_gpr64(tmp, rD(ctx->opcode));
+ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_temp_free_i64(tmp);
+}
+
+static inline void gen_evmwumiaa(DisasContext *ctx)
+{
+ TCGv_i64 acc;
+ TCGv_i64 tmp;
+
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+
+ gen_evmwumi(ctx); /* rD := rA * rB */
+
+ acc = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+
+ /* tmp := rD */
+ gen_load_gpr64(tmp, rD(ctx->opcode));
+
+ /* Load acc */
+ tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+
+ /* acc := tmp + acc */
+ tcg_gen_add_i64(acc, acc, tmp);
+
+ /* Store acc */
+ tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+
+ /* rD := acc */
+ gen_store_gpr64(rD(ctx->opcode), acc);
+
+ tcg_temp_free_i64(acc);
+ tcg_temp_free_i64(tmp);
+}
+
+static inline void gen_evmwsmi(DisasContext *ctx)
+{
+ TCGv_i64 t0, t1;
+
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ /* t0 := rA; t1 := rB */
+ tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_ext32s_i64(t0, t0);
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_ext32s_i64(t1, t1);
+
+ tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
+
+ gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static inline void gen_evmwsmia(DisasContext *ctx)
+{
+ TCGv_i64 tmp;
+
+ gen_evmwsmi(ctx); /* rD := rA * rB */
+
+ tmp = tcg_temp_new_i64();
+
+ /* acc := rD */
+ gen_load_gpr64(tmp, rD(ctx->opcode));
+ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+
+ tcg_temp_free_i64(tmp);
+}
+
+static inline void gen_evmwsmiaa(DisasContext *ctx)
+{
+ TCGv_i64 acc = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ gen_evmwsmi(ctx); /* rD := rA * rB */
+
+ acc = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+
+ /* tmp := rD */
+ gen_load_gpr64(tmp, rD(ctx->opcode));
+
+ /* Load acc */
+ tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+
+ /* acc := tmp + acc */
+ tcg_gen_add_i64(acc, acc, tmp);
+
+ /* Store acc */
+ tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+
+ /* rD := acc */
+ gen_store_gpr64(rD(ctx->opcode), acc);
+
+ tcg_temp_free_i64(acc);
+ tcg_temp_free_i64(tmp);
+}
+
+GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
+GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
+GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
+GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
+GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
+GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
+GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
+GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
+GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
+GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
+GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
+GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
+GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
+GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
+GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
+GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
+GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
+GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
+GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
+GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
+GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
+GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
+GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
+GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
+GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
+
+/* SPE load and stores */
+static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
+{
+ target_ulong uimm = rB(ctx->opcode);
+
+ if (rA(ctx->opcode) == 0) {
+ tcg_gen_movi_tl(EA, uimm << sh);
+ } else {
+ tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(EA, EA);
+ }
+ }
+}
+
+static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ gen_qemu_ld64_i64(ctx, t0, addr);
+ gen_store_gpr64(rD(ctx->opcode), t0);
+ tcg_temp_free_i64(t0);
+}
+
+static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
+ gen_addr_add(ctx, addr, addr, 4);
+ gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(t0, t0, 16);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld16s(ctx, t0, addr);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld32u(ctx, t0, addr);
+ tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
+ tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_ld16u(ctx, t0, addr);
+ tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
+ tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ gen_load_gpr64(t0, rS(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, addr);
+ tcg_temp_free_i64(t0);
+}
+
+static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
+ gen_addr_add(ctx, addr, addr, 4);
+ gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
+ gen_qemu_st16(ctx, t0, addr);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
+ gen_addr_add(ctx, addr, addr, 2);
+ tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
+ gen_qemu_st16(ctx, t0, addr);
+ tcg_temp_free(t0);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
+ gen_qemu_st16(ctx, t0, addr);
+ gen_addr_add(ctx, addr, addr, 2);
+ tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
+ gen_qemu_st16(ctx, t0, addr);
+ tcg_temp_free(t0);
+}
+
+static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
+ gen_addr_add(ctx, addr, addr, 2);
+ gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
+}
+
+static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
+{
+ gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
+}
+
+#define GEN_SPEOP_LDST(name, opc2, sh) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv t0; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ t0 = tcg_temp_new(); \
+ if (Rc(ctx->opcode)) { \
+ gen_addr_spe_imm_index(ctx, t0, sh); \
+ } else { \
+ gen_addr_reg_index(ctx, t0); \
+ } \
+ gen_op_##name(ctx, t0); \
+ tcg_temp_free(t0); \
+}
+
+GEN_SPEOP_LDST(evldd, 0x00, 3);
+GEN_SPEOP_LDST(evldw, 0x01, 3);
+GEN_SPEOP_LDST(evldh, 0x02, 3);
+GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
+GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
+GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
+GEN_SPEOP_LDST(evlwhe, 0x08, 2);
+GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
+GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
+GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
+GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
+
+GEN_SPEOP_LDST(evstdd, 0x10, 3);
+GEN_SPEOP_LDST(evstdw, 0x11, 3);
+GEN_SPEOP_LDST(evstdh, 0x12, 3);
+GEN_SPEOP_LDST(evstwhe, 0x18, 2);
+GEN_SPEOP_LDST(evstwho, 0x1A, 2);
+GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
+GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
+
+/* Multiply and add - TODO */
+#if 0
+GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
+GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+
+GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
+GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
+GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+
+GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
+GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
+GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
+GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
+GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
+
+GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+
+GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+
+GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+
+GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
+GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
+#endif
+
+/*** SPE floating-point extension ***/
+#define GEN_SPEFPUOP_CONV_32_32(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
+ gen_helper_##name(t0, cpu_env, t0); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
+ tcg_temp_free_i32(t0); \
+}
+#define GEN_SPEFPUOP_CONV_32_64(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i32 t1 = tcg_temp_new_i32(); \
+ gen_load_gpr64(t0, rB(ctx->opcode)); \
+ gen_helper_##name(t1, cpu_env, t0); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i32(t1); \
+}
+#define GEN_SPEFPUOP_CONV_64_32(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i32 t1 = tcg_temp_new_i32(); \
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
+ gen_helper_##name(t0, cpu_env, t1); \
+ gen_store_gpr64(rD(ctx->opcode), t0); \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i32(t1); \
+}
+#define GEN_SPEFPUOP_CONV_64_64(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ gen_load_gpr64(t0, rB(ctx->opcode)); \
+ gen_helper_##name(t0, cpu_env, t0); \
+ gen_store_gpr64(rD(ctx->opcode), t0); \
+ tcg_temp_free_i64(t0); \
+}
+#define GEN_SPEFPUOP_ARITH2_32_32(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0, t1; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ t1 = tcg_temp_new_i32(); \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
+ gen_helper_##name(t0, cpu_env, t0, t1); \
+ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
+ \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_i32(t1); \
+}
+#define GEN_SPEFPUOP_ARITH2_64_64(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0, t1; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ gen_load_gpr64(t0, rA(ctx->opcode)); \
+ gen_load_gpr64(t1, rB(ctx->opcode)); \
+ gen_helper_##name(t0, cpu_env, t0, t1); \
+ gen_store_gpr64(rD(ctx->opcode), t0); \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+}
+#define GEN_SPEFPUOP_COMP_32(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 t0, t1; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ t1 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
+ \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_i32(t1); \
+}
+#define GEN_SPEFPUOP_COMP_64(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0, t1; \
+ if (unlikely(!ctx->spe_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ gen_load_gpr64(t0, rA(ctx->opcode)); \
+ gen_load_gpr64(t1, rB(ctx->opcode)); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+}
+
+/* Single precision floating-point vectors operations */
+/* Arithmetic */
+GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
+GEN_SPEFPUOP_ARITH2_64_64(evfssub);
+GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
+GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
+static inline void gen_evfsabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
+ ~0x80000000);
+ tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
+ ~0x80000000);
+}
+static inline void gen_evfsnabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
+ 0x80000000);
+ tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
+ 0x80000000);
+}
+static inline void gen_evfsneg(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
+ 0x80000000);
+ tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
+ 0x80000000);
+}
+
+/* Conversion */
+GEN_SPEFPUOP_CONV_64_64(evfscfui);
+GEN_SPEFPUOP_CONV_64_64(evfscfsi);
+GEN_SPEFPUOP_CONV_64_64(evfscfuf);
+GEN_SPEFPUOP_CONV_64_64(evfscfsf);
+GEN_SPEFPUOP_CONV_64_64(evfsctui);
+GEN_SPEFPUOP_CONV_64_64(evfsctsi);
+GEN_SPEFPUOP_CONV_64_64(evfsctuf);
+GEN_SPEFPUOP_CONV_64_64(evfsctsf);
+GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
+GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
+
+/* Comparison */
+GEN_SPEFPUOP_COMP_64(evfscmpgt);
+GEN_SPEFPUOP_COMP_64(evfscmplt);
+GEN_SPEFPUOP_COMP_64(evfscmpeq);
+GEN_SPEFPUOP_COMP_64(evfststgt);
+GEN_SPEFPUOP_COMP_64(evfststlt);
+GEN_SPEFPUOP_COMP_64(evfststeq);
+
+/* Opcodes definitions */
+GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
+GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
+GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
+GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
+GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
+GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+
+/* Single precision floating-point operations */
+/* Arithmetic */
+GEN_SPEFPUOP_ARITH2_32_32(efsadd);
+GEN_SPEFPUOP_ARITH2_32_32(efssub);
+GEN_SPEFPUOP_ARITH2_32_32(efsmul);
+GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
+static inline void gen_efsabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
+ (target_long)~0x80000000LL);
+}
+static inline void gen_efsnabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
+ 0x80000000);
+}
+static inline void gen_efsneg(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
+ 0x80000000);
+}
+
+/* Conversion */
+GEN_SPEFPUOP_CONV_32_32(efscfui);
+GEN_SPEFPUOP_CONV_32_32(efscfsi);
+GEN_SPEFPUOP_CONV_32_32(efscfuf);
+GEN_SPEFPUOP_CONV_32_32(efscfsf);
+GEN_SPEFPUOP_CONV_32_32(efsctui);
+GEN_SPEFPUOP_CONV_32_32(efsctsi);
+GEN_SPEFPUOP_CONV_32_32(efsctuf);
+GEN_SPEFPUOP_CONV_32_32(efsctsf);
+GEN_SPEFPUOP_CONV_32_32(efsctuiz);
+GEN_SPEFPUOP_CONV_32_32(efsctsiz);
+GEN_SPEFPUOP_CONV_32_64(efscfd);
+
+/* Comparison */
+GEN_SPEFPUOP_COMP_32(efscmpgt);
+GEN_SPEFPUOP_COMP_32(efscmplt);
+GEN_SPEFPUOP_COMP_32(efscmpeq);
+GEN_SPEFPUOP_COMP_32(efststgt);
+GEN_SPEFPUOP_COMP_32(efststlt);
+GEN_SPEFPUOP_COMP_32(efststeq);
+
+/* Opcodes definitions */
+GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
+GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
+GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
+GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
+GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
+GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
+GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
+
+/* Double precision floating-point operations */
+/* Arithmetic */
+GEN_SPEFPUOP_ARITH2_64_64(efdadd);
+GEN_SPEFPUOP_ARITH2_64_64(efdsub);
+GEN_SPEFPUOP_ARITH2_64_64(efdmul);
+GEN_SPEFPUOP_ARITH2_64_64(efddiv);
+static inline void gen_efdabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
+ ~0x80000000);
+}
+static inline void gen_efdnabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
+ 0x80000000);
+}
+static inline void gen_efdneg(DisasContext *ctx)
+{
+ if (unlikely(!ctx->spe_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
+ return;
+ }
+ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
+ 0x80000000);
+}
+
+/* Conversion */
+GEN_SPEFPUOP_CONV_64_32(efdcfui);
+GEN_SPEFPUOP_CONV_64_32(efdcfsi);
+GEN_SPEFPUOP_CONV_64_32(efdcfuf);
+GEN_SPEFPUOP_CONV_64_32(efdcfsf);
+GEN_SPEFPUOP_CONV_32_64(efdctui);
+GEN_SPEFPUOP_CONV_32_64(efdctsi);
+GEN_SPEFPUOP_CONV_32_64(efdctuf);
+GEN_SPEFPUOP_CONV_32_64(efdctsf);
+GEN_SPEFPUOP_CONV_32_64(efdctuiz);
+GEN_SPEFPUOP_CONV_32_64(efdctsiz);
+GEN_SPEFPUOP_CONV_64_32(efdcfs);
+GEN_SPEFPUOP_CONV_64_64(efdcfuid);
+GEN_SPEFPUOP_CONV_64_64(efdcfsid);
+GEN_SPEFPUOP_CONV_64_64(efdctuidz);
+GEN_SPEFPUOP_CONV_64_64(efdctsidz);
+
+/* Comparison */
+GEN_SPEFPUOP_COMP_64(efdcmpgt);
+GEN_SPEFPUOP_COMP_64(efdcmplt);
+GEN_SPEFPUOP_COMP_64(efdcmpeq);
+GEN_SPEFPUOP_COMP_64(efdtstgt);
+GEN_SPEFPUOP_COMP_64(efdtstlt);
+GEN_SPEFPUOP_COMP_64(efdtsteq);
+
+/* Opcodes definitions */
+GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
+GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
+GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
+GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
+GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
+GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
+
+#undef GEN_SPE
+#undef GEN_SPEOP_LDST
+++ /dev/null
-/*
- * translate-spe.c
- *
- * Freescale SPE extension translation
- */
-
-/*** SPE extension ***/
-/* Register moves */
-
-static inline void gen_evmra(DisasContext *ctx)
-{
-
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
-
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- /* tmp := rA_lo + rA_hi << 32 */
- tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)],
- cpu_gprh[rA(ctx->opcode)]);
-
- /* spe_acc := tmp */
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
- tcg_temp_free_i64(tmp);
-
- /* rD := rA */
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
-}
-
-static inline void gen_load_gpr64(TCGv_i64 t, int reg)
-{
- tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
-}
-
-static inline void gen_store_gpr64(int reg, TCGv_i64 t)
-{
- tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
-}
-
-#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
-static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
-{ \
- if (Rc(ctx->opcode)) \
- gen_##name1(ctx); \
- else \
- gen_##name0(ctx); \
-}
-
-/* Handler for undefined SPE opcodes */
-static inline void gen_speundef(DisasContext *ctx)
-{
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
-}
-
-/* SPE logic */
-#define GEN_SPEOP_LOGIC2(name, tcg_op) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
- cpu_gpr[rB(ctx->opcode)]); \
- tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
- cpu_gprh[rB(ctx->opcode)]); \
-}
-
-GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
-GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
-GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
-GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
-GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
-GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
-GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
-GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
-
-/* SPE logic immediate */
-#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i32(); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
- tcg_opi(t0, t0, rB(ctx->opcode)); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
- tcg_opi(t0, t0, rB(ctx->opcode)); \
- tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
- \
- tcg_temp_free_i32(t0); \
-}
-GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
-GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
-GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
-GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
-
-/* SPE arithmetic */
-#define GEN_SPEOP_ARITH1(name, tcg_op) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i32(); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
- tcg_op(t0, t0); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
- tcg_op(t0, t0); \
- tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
- \
- tcg_temp_free_i32(t0); \
-}
-
-GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32);
-GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
-GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
-GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
-static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
-{
- tcg_gen_addi_i32(ret, arg1, 0x8000);
- tcg_gen_ext16u_i32(ret, ret);
-}
-GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
-GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
-GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
-
-#define GEN_SPEOP_ARITH2(name, tcg_op) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0, t1; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i32(); \
- t1 = tcg_temp_new_i32(); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
- tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- tcg_op(t0, t0, t1); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
- tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
- tcg_op(t0, t0, t1); \
- tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
- \
- tcg_temp_free_i32(t0); \
- tcg_temp_free_i32(t1); \
-}
-
-static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGv_i32 t0 = tcg_temp_local_new_i32();
-
- /* No error here: 6 bits are used */
- tcg_gen_andi_i32(t0, arg2, 0x3F);
- tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
- tcg_gen_shr_i32(ret, arg1, t0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_movi_i32(ret, 0);
- gen_set_label(l2);
- tcg_temp_free_i32(t0);
-}
-GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
-static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGv_i32 t0 = tcg_temp_local_new_i32();
-
- /* No error here: 6 bits are used */
- tcg_gen_andi_i32(t0, arg2, 0x3F);
- tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
- tcg_gen_sar_i32(ret, arg1, t0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_movi_i32(ret, 0);
- gen_set_label(l2);
- tcg_temp_free_i32(t0);
-}
-GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
-static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGv_i32 t0 = tcg_temp_local_new_i32();
-
- /* No error here: 6 bits are used */
- tcg_gen_andi_i32(t0, arg2, 0x3F);
- tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
- tcg_gen_shl_i32(ret, arg1, t0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_movi_i32(ret, 0);
- gen_set_label(l2);
- tcg_temp_free_i32(t0);
-}
-GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
-static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_andi_i32(t0, arg2, 0x1F);
- tcg_gen_rotl_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
-}
-GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
-static inline void gen_evmergehi(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
-}
-GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
-static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_sub_i32(ret, arg2, arg1);
-}
-GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
-
-/* SPE arithmetic immediate */
-#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i32(); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
- tcg_op(t0, t0, rA(ctx->opcode)); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
- tcg_op(t0, t0, rA(ctx->opcode)); \
- tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
- \
- tcg_temp_free_i32(t0); \
-}
-GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
-GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
-
-/* SPE comparison */
-#define GEN_SPEOP_COMP(name, tcg_cond) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- TCGLabel *l1 = gen_new_label(); \
- TCGLabel *l2 = gen_new_label(); \
- TCGLabel *l3 = gen_new_label(); \
- TCGLabel *l4 = gen_new_label(); \
- \
- tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
- tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
- tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
- tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
- \
- tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
- cpu_gpr[rB(ctx->opcode)], l1); \
- tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
- tcg_gen_br(l2); \
- gen_set_label(l1); \
- tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
- CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
- gen_set_label(l2); \
- tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
- cpu_gprh[rB(ctx->opcode)], l3); \
- tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
- ~(CRF_CH | CRF_CH_AND_CL)); \
- tcg_gen_br(l4); \
- gen_set_label(l3); \
- tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
- CRF_CH | CRF_CH_OR_CL); \
- gen_set_label(l4); \
-}
-GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
-GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
-GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
-GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
-GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
-
-/* SPE misc */
-static inline void gen_brinc(DisasContext *ctx)
-{
- /* Note: brinc is usable even if SPE is disabled */
- gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
-}
-static inline void gen_evmergelo(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
-}
-static inline void gen_evmergehilo(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
-}
-static inline void gen_evmergelohi(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- if (rD(ctx->opcode) == rA(ctx->opcode)) {
- TCGv tmp = tcg_temp_new();
- tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
- tcg_temp_free(tmp);
- } else {
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- }
-}
-static inline void gen_evsplati(DisasContext *ctx)
-{
- uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
-
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
- tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
-}
-static inline void gen_evsplatfi(DisasContext *ctx)
-{
- uint64_t imm = rA(ctx->opcode) << 27;
-
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
- tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
-}
-
-static inline void gen_evsel(DisasContext *ctx)
-{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- TCGLabel *l4 = gen_new_label();
- TCGv_i32 t0 = tcg_temp_local_new_i32();
-
- tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
- tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
- gen_set_label(l2);
- tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
- tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_br(l4);
- gen_set_label(l3);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
- gen_set_label(l4);
- tcg_temp_free_i32(t0);
-}
-
-static void gen_evsel0(DisasContext *ctx)
-{
- gen_evsel(ctx);
-}
-
-static void gen_evsel1(DisasContext *ctx)
-{
- gen_evsel(ctx);
-}
-
-static void gen_evsel2(DisasContext *ctx)
-{
- gen_evsel(ctx);
-}
-
-static void gen_evsel3(DisasContext *ctx)
-{
- gen_evsel(ctx);
-}
-
-/* Multiply */
-
-static inline void gen_evmwumi(DisasContext *ctx)
-{
- TCGv_i64 t0, t1;
-
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
-
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
-
- /* t0 := rA; t1 := rB */
- tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32u_i64(t0, t0);
- tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_ext32u_i64(t1, t1);
-
- tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
-
- gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static inline void gen_evmwumia(DisasContext *ctx)
-{
- TCGv_i64 tmp;
-
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
-
- gen_evmwumi(ctx); /* rD := rA * rB */
-
- tmp = tcg_temp_new_i64();
-
- /* acc := rD */
- gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
- tcg_temp_free_i64(tmp);
-}
-
-static inline void gen_evmwumiaa(DisasContext *ctx)
-{
- TCGv_i64 acc;
- TCGv_i64 tmp;
-
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
-
- gen_evmwumi(ctx); /* rD := rA * rB */
-
- acc = tcg_temp_new_i64();
- tmp = tcg_temp_new_i64();
-
- /* tmp := rD */
- gen_load_gpr64(tmp, rD(ctx->opcode));
-
- /* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
-
- /* acc := tmp + acc */
- tcg_gen_add_i64(acc, acc, tmp);
-
- /* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
-
- /* rD := acc */
- gen_store_gpr64(rD(ctx->opcode), acc);
-
- tcg_temp_free_i64(acc);
- tcg_temp_free_i64(tmp);
-}
-
-static inline void gen_evmwsmi(DisasContext *ctx)
-{
- TCGv_i64 t0, t1;
-
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
-
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
-
- /* t0 := rA; t1 := rB */
- tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32s_i64(t0, t0);
- tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_ext32s_i64(t1, t1);
-
- tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
-
- gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static inline void gen_evmwsmia(DisasContext *ctx)
-{
- TCGv_i64 tmp;
-
- gen_evmwsmi(ctx); /* rD := rA * rB */
-
- tmp = tcg_temp_new_i64();
-
- /* acc := rD */
- gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
-
- tcg_temp_free_i64(tmp);
-}
-
-static inline void gen_evmwsmiaa(DisasContext *ctx)
-{
- TCGv_i64 acc = tcg_temp_new_i64();
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- gen_evmwsmi(ctx); /* rD := rA * rB */
-
- acc = tcg_temp_new_i64();
- tmp = tcg_temp_new_i64();
-
- /* tmp := rD */
- gen_load_gpr64(tmp, rD(ctx->opcode));
-
- /* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
-
- /* acc := tmp + acc */
- tcg_gen_add_i64(acc, acc, tmp);
-
- /* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
-
- /* rD := acc */
- gen_store_gpr64(rD(ctx->opcode), acc);
-
- tcg_temp_free_i64(acc);
- tcg_temp_free_i64(tmp);
-}
-
-GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
-GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
-GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
-GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
-GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
-GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
-GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
-GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
-GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
-GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
-GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
-GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
-GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
-GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
-GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
-GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
-GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
-GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
-GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
-GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
-GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
-GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
-GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
-GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
-GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
-
-/* SPE load and stores */
-static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
-{
- target_ulong uimm = rB(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- tcg_gen_movi_tl(EA, uimm << sh);
- } else {
- tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
- if (NARROW_MODE(ctx)) {
- tcg_gen_ext32u_tl(EA, EA);
- }
- }
-}
-
-static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- gen_qemu_ld64_i64(ctx, t0, addr);
- gen_store_gpr64(rD(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
-static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
- gen_addr_add(ctx, addr, addr, 4);
- gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(t0, t0, 16);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld16s(ctx, t0, addr);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld32u(ctx, t0, addr);
- tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
- tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_ld16u(ctx, t0, addr);
- tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
- tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- gen_load_gpr64(t0, rS(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, addr);
- tcg_temp_free_i64(t0);
-}
-
-static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
- gen_addr_add(ctx, addr, addr, 4);
- gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
- gen_qemu_st16(ctx, t0, addr);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
- gen_addr_add(ctx, addr, addr, 2);
- tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
- gen_qemu_st16(ctx, t0, addr);
- tcg_temp_free(t0);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
- gen_qemu_st16(ctx, t0, addr);
- gen_addr_add(ctx, addr, addr, 2);
- tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
- gen_qemu_st16(ctx, t0, addr);
- tcg_temp_free(t0);
-}
-
-static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
- gen_addr_add(ctx, addr, addr, 2);
- gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
-}
-
-static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
-{
- gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
-}
-
-#define GEN_SPEOP_LDST(name, opc2, sh) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- t0 = tcg_temp_new(); \
- if (Rc(ctx->opcode)) { \
- gen_addr_spe_imm_index(ctx, t0, sh); \
- } else { \
- gen_addr_reg_index(ctx, t0); \
- } \
- gen_op_##name(ctx, t0); \
- tcg_temp_free(t0); \
-}
-
-GEN_SPEOP_LDST(evldd, 0x00, 3);
-GEN_SPEOP_LDST(evldw, 0x01, 3);
-GEN_SPEOP_LDST(evldh, 0x02, 3);
-GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
-GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
-GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
-GEN_SPEOP_LDST(evlwhe, 0x08, 2);
-GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
-GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
-GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
-GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
-
-GEN_SPEOP_LDST(evstdd, 0x10, 3);
-GEN_SPEOP_LDST(evstdw, 0x11, 3);
-GEN_SPEOP_LDST(evstdh, 0x12, 3);
-GEN_SPEOP_LDST(evstwhe, 0x18, 2);
-GEN_SPEOP_LDST(evstwho, 0x1A, 2);
-GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
-GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
-
-/* Multiply and add - TODO */
-#if 0
-GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
-GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-
-GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
-GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
-GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-
-GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
-GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
-GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
-GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
-GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
-
-GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-
-GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-
-GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-
-GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
-GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
-#endif
-
-/*** SPE floating-point extension ***/
-#define GEN_SPEFPUOP_CONV_32_32(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0 = tcg_temp_new_i32(); \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t0); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
- tcg_temp_free_i32(t0); \
-}
-#define GEN_SPEFPUOP_CONV_32_64(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0 = tcg_temp_new_i64(); \
- TCGv_i32 t1 = tcg_temp_new_i32(); \
- gen_load_gpr64(t0, rB(ctx->opcode)); \
- gen_helper_##name(t1, cpu_env, t0); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i32(t1); \
-}
-#define GEN_SPEFPUOP_CONV_64_32(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0 = tcg_temp_new_i64(); \
- TCGv_i32 t1 = tcg_temp_new_i32(); \
- tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t1); \
- gen_store_gpr64(rD(ctx->opcode), t0); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i32(t1); \
-}
-#define GEN_SPEFPUOP_CONV_64_64(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0 = tcg_temp_new_i64(); \
- gen_load_gpr64(t0, rB(ctx->opcode)); \
- gen_helper_##name(t0, cpu_env, t0); \
- gen_store_gpr64(rD(ctx->opcode), t0); \
- tcg_temp_free_i64(t0); \
-}
-#define GEN_SPEFPUOP_ARITH2_32_32(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0, t1; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i32(); \
- t1 = tcg_temp_new_i32(); \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
- tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t0, t1); \
- tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
- \
- tcg_temp_free_i32(t0); \
- tcg_temp_free_i32(t1); \
-}
-#define GEN_SPEFPUOP_ARITH2_64_64(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0, t1; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- gen_load_gpr64(t0, rA(ctx->opcode)); \
- gen_load_gpr64(t1, rB(ctx->opcode)); \
- gen_helper_##name(t0, cpu_env, t0, t1); \
- gen_store_gpr64(rD(ctx->opcode), t0); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
-}
-#define GEN_SPEFPUOP_COMP_32(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 t0, t1; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i32(); \
- t1 = tcg_temp_new_i32(); \
- \
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
- tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
- \
- tcg_temp_free_i32(t0); \
- tcg_temp_free_i32(t1); \
-}
-#define GEN_SPEFPUOP_COMP_64(name) \
-static inline void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0, t1; \
- if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_SPEU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- gen_load_gpr64(t0, rA(ctx->opcode)); \
- gen_load_gpr64(t1, rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
-}
-
-/* Single precision floating-point vectors operations */
-/* Arithmetic */
-GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
-GEN_SPEFPUOP_ARITH2_64_64(evfssub);
-GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
-GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
-static inline void gen_evfsabs(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- ~0x80000000);
- tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
- ~0x80000000);
-}
-static inline void gen_evfsnabs(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- 0x80000000);
- tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
- 0x80000000);
-}
-static inline void gen_evfsneg(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- 0x80000000);
- tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
- 0x80000000);
-}
-
-/* Conversion */
-GEN_SPEFPUOP_CONV_64_64(evfscfui);
-GEN_SPEFPUOP_CONV_64_64(evfscfsi);
-GEN_SPEFPUOP_CONV_64_64(evfscfuf);
-GEN_SPEFPUOP_CONV_64_64(evfscfsf);
-GEN_SPEFPUOP_CONV_64_64(evfsctui);
-GEN_SPEFPUOP_CONV_64_64(evfsctsi);
-GEN_SPEFPUOP_CONV_64_64(evfsctuf);
-GEN_SPEFPUOP_CONV_64_64(evfsctsf);
-GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
-GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
-
-/* Comparison */
-GEN_SPEFPUOP_COMP_64(evfscmpgt);
-GEN_SPEFPUOP_COMP_64(evfscmplt);
-GEN_SPEFPUOP_COMP_64(evfscmpeq);
-GEN_SPEFPUOP_COMP_64(evfststgt);
-GEN_SPEFPUOP_COMP_64(evfststlt);
-GEN_SPEFPUOP_COMP_64(evfststeq);
-
-/* Opcodes definitions */
-GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
-GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
-GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
-GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
-GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
-GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-
-/* Single precision floating-point operations */
-/* Arithmetic */
-GEN_SPEFPUOP_ARITH2_32_32(efsadd);
-GEN_SPEFPUOP_ARITH2_32_32(efssub);
-GEN_SPEFPUOP_ARITH2_32_32(efsmul);
-GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
-static inline void gen_efsabs(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- (target_long)~0x80000000LL);
-}
-static inline void gen_efsnabs(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- 0x80000000);
-}
-static inline void gen_efsneg(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- 0x80000000);
-}
-
-/* Conversion */
-GEN_SPEFPUOP_CONV_32_32(efscfui);
-GEN_SPEFPUOP_CONV_32_32(efscfsi);
-GEN_SPEFPUOP_CONV_32_32(efscfuf);
-GEN_SPEFPUOP_CONV_32_32(efscfsf);
-GEN_SPEFPUOP_CONV_32_32(efsctui);
-GEN_SPEFPUOP_CONV_32_32(efsctsi);
-GEN_SPEFPUOP_CONV_32_32(efsctuf);
-GEN_SPEFPUOP_CONV_32_32(efsctsf);
-GEN_SPEFPUOP_CONV_32_32(efsctuiz);
-GEN_SPEFPUOP_CONV_32_32(efsctsiz);
-GEN_SPEFPUOP_CONV_32_64(efscfd);
-
-/* Comparison */
-GEN_SPEFPUOP_COMP_32(efscmpgt);
-GEN_SPEFPUOP_COMP_32(efscmplt);
-GEN_SPEFPUOP_COMP_32(efscmpeq);
-GEN_SPEFPUOP_COMP_32(efststgt);
-GEN_SPEFPUOP_COMP_32(efststlt);
-GEN_SPEFPUOP_COMP_32(efststeq);
-
-/* Opcodes definitions */
-GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
-GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
-GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
-GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
-GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
-GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
-GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
-
-/* Double precision floating-point operations */
-/* Arithmetic */
-GEN_SPEFPUOP_ARITH2_64_64(efdadd);
-GEN_SPEFPUOP_ARITH2_64_64(efdsub);
-GEN_SPEFPUOP_ARITH2_64_64(efdmul);
-GEN_SPEFPUOP_ARITH2_64_64(efddiv);
-static inline void gen_efdabs(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
- ~0x80000000);
-}
-static inline void gen_efdnabs(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
- 0x80000000);
-}
-static inline void gen_efdneg(DisasContext *ctx)
-{
- if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_SPEU);
- return;
- }
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
- 0x80000000);
-}
-
-/* Conversion */
-GEN_SPEFPUOP_CONV_64_32(efdcfui);
-GEN_SPEFPUOP_CONV_64_32(efdcfsi);
-GEN_SPEFPUOP_CONV_64_32(efdcfuf);
-GEN_SPEFPUOP_CONV_64_32(efdcfsf);
-GEN_SPEFPUOP_CONV_32_64(efdctui);
-GEN_SPEFPUOP_CONV_32_64(efdctsi);
-GEN_SPEFPUOP_CONV_32_64(efdctuf);
-GEN_SPEFPUOP_CONV_32_64(efdctsf);
-GEN_SPEFPUOP_CONV_32_64(efdctuiz);
-GEN_SPEFPUOP_CONV_32_64(efdctsiz);
-GEN_SPEFPUOP_CONV_64_32(efdcfs);
-GEN_SPEFPUOP_CONV_64_64(efdcfuid);
-GEN_SPEFPUOP_CONV_64_64(efdcfsid);
-GEN_SPEFPUOP_CONV_64_64(efdctuidz);
-GEN_SPEFPUOP_CONV_64_64(efdctsidz);
-
-/* Comparison */
-GEN_SPEFPUOP_COMP_64(efdcmpgt);
-GEN_SPEFPUOP_COMP_64(efdcmplt);
-GEN_SPEFPUOP_COMP_64(efdcmpeq);
-GEN_SPEFPUOP_COMP_64(efdtstgt);
-GEN_SPEFPUOP_COMP_64(efdtstlt);
-GEN_SPEFPUOP_COMP_64(efdtsteq);
-
-/* Opcodes definitions */
-GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
-GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
-GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
-GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
-GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
-GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
-
-#undef GEN_SPE
-#undef GEN_SPEOP_LDST
--- /dev/null
+GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
+GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
+GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
+GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
+
+#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
+ GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
+GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
+GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
+GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
+GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
+GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
+GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
+GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
+GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
+GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
+GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
+GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
+GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
+GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
+
+GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
+GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
+GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
+GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
+GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
+GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+
+GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
+GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
+GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
+GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
+GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
+GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
+GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
+
+GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
+GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
+GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
+GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
+GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
+GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
+GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
+GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
+GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
+GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
+
+#define GEN_SPEOP_LDST(name, opc2, sh) \
+GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
+GEN_SPEOP_LDST(evldd, 0x00, 3),
+GEN_SPEOP_LDST(evldw, 0x01, 3),
+GEN_SPEOP_LDST(evldh, 0x02, 3),
+GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
+GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
+GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
+GEN_SPEOP_LDST(evlwhe, 0x08, 2),
+GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
+GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
+GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
+GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
+
+GEN_SPEOP_LDST(evstdd, 0x10, 3),
+GEN_SPEOP_LDST(evstdw, 0x11, 3),
+GEN_SPEOP_LDST(evstdh, 0x12, 3),
+GEN_SPEOP_LDST(evstwhe, 0x18, 2),
+GEN_SPEOP_LDST(evstwho, 0x1A, 2),
+GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
+GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
+++ /dev/null
-GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
-GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
-GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
-GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
-
-#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
- GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
-GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
-GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
-GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
-GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
-GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
-GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
-GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
-GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
-GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
-GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
-GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
-GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
-GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
-
-GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
-GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
-GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
-GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
-GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
-GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-
-GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
-GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
-GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
-GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
-GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
-GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
-GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
-
-GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
-GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
-GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
-GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
-GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
-GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
-GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
-GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
-GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
-GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
-
-#define GEN_SPEOP_LDST(name, opc2, sh) \
-GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
-GEN_SPEOP_LDST(evldd, 0x00, 3),
-GEN_SPEOP_LDST(evldw, 0x01, 3),
-GEN_SPEOP_LDST(evldh, 0x02, 3),
-GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
-GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
-GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
-GEN_SPEOP_LDST(evlwhe, 0x08, 2),
-GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
-GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
-GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
-GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
-
-GEN_SPEOP_LDST(evstdd, 0x10, 3),
-GEN_SPEOP_LDST(evstdw, 0x11, 3),
-GEN_SPEOP_LDST(evstdh, 0x12, 3),
-GEN_SPEOP_LDST(evstwhe, 0x18, 2),
-GEN_SPEOP_LDST(evstwho, 0x1A, 2),
-GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
-GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
--- /dev/null
+/*
+ * translate/vmx-impl.c
+ *
+ * Altivec/VMX translation
+ */
+
+/*** Altivec vector extension ***/
+/* Altivec registers moves */
+
+static inline TCGv_ptr gen_avr_ptr(int reg)
+{
+ TCGv_ptr r = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
+ return r;
+}
+
+#define GEN_VR_LDX(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 avr; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ avr = tcg_temp_new_i64(); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ tcg_gen_andi_tl(EA, EA, ~0xf); \
+ /* \
+ * We only need to swap high and low halves. gen_qemu_ld64_i64 \
+ * does necessary 64-bit byteswap already. \
+ */ \
+ if (ctx->le_mode) { \
+ gen_qemu_ld64_i64(ctx, avr, EA); \
+ set_avr64(rD(ctx->opcode), avr, false); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ gen_qemu_ld64_i64(ctx, avr, EA); \
+ set_avr64(rD(ctx->opcode), avr, true); \
+ } else { \
+ gen_qemu_ld64_i64(ctx, avr, EA); \
+ set_avr64(rD(ctx->opcode), avr, true); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ gen_qemu_ld64_i64(ctx, avr, EA); \
+ set_avr64(rD(ctx->opcode), avr, false); \
+ } \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(avr); \
+}
+
+#define GEN_VR_STX(name, opc2, opc3) \
+static void gen_st##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 avr; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ avr = tcg_temp_new_i64(); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ tcg_gen_andi_tl(EA, EA, ~0xf); \
+ /* \
+ * We only need to swap high and low halves. gen_qemu_st64_i64 \
+ * does necessary 64-bit byteswap already. \
+ */ \
+ if (ctx->le_mode) { \
+ get_avr64(avr, rD(ctx->opcode), false); \
+ gen_qemu_st64_i64(ctx, avr, EA); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ get_avr64(avr, rD(ctx->opcode), true); \
+ gen_qemu_st64_i64(ctx, avr, EA); \
+ } else { \
+ get_avr64(avr, rD(ctx->opcode), true); \
+ gen_qemu_st64_i64(ctx, avr, EA); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ get_avr64(avr, rD(ctx->opcode), false); \
+ gen_qemu_st64_i64(ctx, avr, EA); \
+ } \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(avr); \
+}
+
+#define GEN_VR_LVE(name, opc2, opc3, size) \
+static void gen_lve##name(DisasContext *ctx) \
+ { \
+ TCGv EA; \
+ TCGv_ptr rs; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ if (size > 1) { \
+ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
+ } \
+ rs = gen_avr_ptr(rS(ctx->opcode)); \
+ gen_helper_lve##name(cpu_env, rs, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(rs); \
+ }
+
+#define GEN_VR_STVE(name, opc2, opc3, size) \
+static void gen_stve##name(DisasContext *ctx) \
+ { \
+ TCGv EA; \
+ TCGv_ptr rs; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ if (size > 1) { \
+ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
+ } \
+ rs = gen_avr_ptr(rS(ctx->opcode)); \
+ gen_helper_stve##name(cpu_env, rs, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(rs); \
+ }
+
+GEN_VR_LDX(lvx, 0x07, 0x03);
+/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
+GEN_VR_LDX(lvxl, 0x07, 0x0B);
+
+GEN_VR_LVE(bx, 0x07, 0x00, 1);
+GEN_VR_LVE(hx, 0x07, 0x01, 2);
+GEN_VR_LVE(wx, 0x07, 0x02, 4);
+
+GEN_VR_STX(svx, 0x07, 0x07);
+/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
+GEN_VR_STX(svxl, 0x07, 0x0F);
+
+GEN_VR_STVE(bx, 0x07, 0x04, 1);
+GEN_VR_STVE(hx, 0x07, 0x05, 2);
+GEN_VR_STVE(wx, 0x07, 0x06, 4);
+
+static void gen_mfvscr(DisasContext *ctx)
+{
+ TCGv_i32 t;
+ TCGv_i64 avr;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ avr = tcg_temp_new_i64();
+ tcg_gen_movi_i64(avr, 0);
+ set_avr64(rD(ctx->opcode), avr, true);
+ t = tcg_temp_new_i32();
+ gen_helper_mfvscr(t, cpu_env);
+ tcg_gen_extu_i32_i64(avr, t);
+ set_avr64(rD(ctx->opcode), avr, false);
+ tcg_temp_free_i32(t);
+ tcg_temp_free_i64(avr);
+}
+
+static void gen_mtvscr(DisasContext *ctx)
+{
+ TCGv_i32 val;
+ int bofs;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+
+ val = tcg_temp_new_i32();
+ bofs = avr_full_offset(rB(ctx->opcode));
+#ifdef HOST_WORDS_BIGENDIAN
+ bofs += 3 * 4;
+#endif
+
+ tcg_gen_ld_i32(val, cpu_env, bofs);
+ gen_helper_mtvscr(cpu_env, val);
+ tcg_temp_free_i32(val);
+}
+
+#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ TCGv_i64 t2; \
+ TCGv_i64 avr; \
+ TCGv_i64 ten, z; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ t2 = tcg_temp_new_i64(); \
+ avr = tcg_temp_new_i64(); \
+ ten = tcg_const_i64(10); \
+ z = tcg_const_i64(0); \
+ \
+ if (add_cin) { \
+ get_avr64(avr, rA(ctx->opcode), false); \
+ tcg_gen_mulu2_i64(t0, t1, avr, ten); \
+ get_avr64(avr, rB(ctx->opcode), false); \
+ tcg_gen_andi_i64(t2, avr, 0xF); \
+ tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
+ set_avr64(rD(ctx->opcode), avr, false); \
+ } else { \
+ get_avr64(avr, rA(ctx->opcode), false); \
+ tcg_gen_mulu2_i64(avr, t2, avr, ten); \
+ set_avr64(rD(ctx->opcode), avr, false); \
+ } \
+ \
+ if (ret_carry) { \
+ get_avr64(avr, rA(ctx->opcode), true); \
+ tcg_gen_mulu2_i64(t0, t1, avr, ten); \
+ tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
+ set_avr64(rD(ctx->opcode), avr, false); \
+ set_avr64(rD(ctx->opcode), z, true); \
+ } else { \
+ get_avr64(avr, rA(ctx->opcode), true); \
+ tcg_gen_mul_i64(t0, avr, ten); \
+ tcg_gen_add_i64(avr, t0, t2); \
+ set_avr64(rD(ctx->opcode), avr, true); \
+ } \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+ tcg_temp_free_i64(avr); \
+ tcg_temp_free_i64(ten); \
+ tcg_temp_free_i64(z); \
+} \
+
+GEN_VX_VMUL10(vmul10uq, 0, 0);
+GEN_VX_VMUL10(vmul10euq, 1, 0);
+GEN_VX_VMUL10(vmul10cuq, 0, 1);
+GEN_VX_VMUL10(vmul10ecuq, 1, 1);
+
+#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ \
+ tcg_op(vece, \
+ avr_full_offset(rD(ctx->opcode)), \
+ avr_full_offset(rA(ctx->opcode)), \
+ avr_full_offset(rB(ctx->opcode)), \
+ 16, 16); \
+}
+
+/* Logical operations */
+GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
+GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
+GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
+GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
+GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
+GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
+GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
+GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
+
+#define GEN_VXFORM(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(rd, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+}
+
+#define GEN_VXFORM_TRANS(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ trans_##name(ctx); \
+}
+
+#define GEN_VXFORM_ENV(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rd, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+}
+
+#define GEN_VXFORM3(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rb, rc, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rc = gen_avr_ptr(rC(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(rd, ra, rb, rc); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rc); \
+ tcg_temp_free_ptr(rd); \
+}
+
+/*
+ * Support for Altivec instruction pairs that use bit 31 (Rc) as
+ * an opcode bit. In general, these pairs come from different
+ * versions of the ISA, so we must also support a pair of flags for
+ * each instruction.
+ */
+#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if ((Rc(ctx->opcode) == 0) && \
+ ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
+ gen_##name0(ctx); \
+ } else if ((Rc(ctx->opcode) == 1) && \
+ ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
+ gen_##name1(ctx); \
+ } else { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ } \
+}
+
+/*
+ * We use this macro if one instruction is realized with direct
+ * translation, and second one with helper.
+ */
+#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if ((Rc(ctx->opcode) == 0) && \
+ ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ trans_##name0(ctx); \
+ } else if ((Rc(ctx->opcode) == 1) && \
+ ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
+ gen_##name1(ctx); \
+ } else { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ } \
+}
+
+/* Adds support to provide invalid mask */
+#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
+ name1, flg1, flg2_1, inval1) \
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if ((Rc(ctx->opcode) == 0) && \
+ ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
+ !(ctx->opcode & inval0)) { \
+ gen_##name0(ctx); \
+ } else if ((Rc(ctx->opcode) == 1) && \
+ ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
+ !(ctx->opcode & inval1)) { \
+ gen_##name1(ctx); \
+ } else { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ } \
+}
+
+#define GEN_VXFORM_HETRO(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
+ tcg_temp_free_ptr(rb); \
+}
+
+GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
+GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
+ vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
+GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
+GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
+ vmul10ecuq, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
+GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
+GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
+GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
+GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
+GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
+GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
+GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
+GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
+GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
+GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
+GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
+GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
+GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
+GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
+GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
+GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
+GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
+GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
+GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
+GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
+GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
+GEN_VXFORM(vavgub, 1, 16);
+GEN_VXFORM(vabsdub, 1, 16);
+GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
+ vabsdub, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM(vavguh, 1, 17);
+GEN_VXFORM(vabsduh, 1, 17);
+GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
+ vabsduh, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM(vavguw, 1, 18);
+GEN_VXFORM(vabsduw, 1, 18);
+GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
+ vabsduw, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM(vavgsb, 1, 20);
+GEN_VXFORM(vavgsh, 1, 21);
+GEN_VXFORM(vavgsw, 1, 22);
+GEN_VXFORM(vmrghb, 6, 0);
+GEN_VXFORM(vmrghh, 6, 1);
+GEN_VXFORM(vmrghw, 6, 2);
+GEN_VXFORM(vmrglb, 6, 4);
+GEN_VXFORM(vmrglh, 6, 5);
+GEN_VXFORM(vmrglw, 6, 6);
+
+static void trans_vmrgew(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VA = rA(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv_i64 avr = tcg_temp_new_i64();
+
+ get_avr64(avr, VB, true);
+ tcg_gen_shri_i64(tmp, avr, 32);
+ get_avr64(avr, VA, true);
+ tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
+ set_avr64(VT, avr, true);
+
+ get_avr64(avr, VB, false);
+ tcg_gen_shri_i64(tmp, avr, 32);
+ get_avr64(avr, VA, false);
+ tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
+ set_avr64(VT, avr, false);
+
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(avr);
+}
+
+static void trans_vmrgow(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VA = rA(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 avr = tcg_temp_new_i64();
+
+ get_avr64(t0, VB, true);
+ get_avr64(t1, VA, true);
+ tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
+ set_avr64(VT, avr, true);
+
+ get_avr64(t0, VB, false);
+ get_avr64(t1, VA, false);
+ tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
+ set_avr64(VT, avr, false);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(avr);
+}
+
+/*
+ * lvsl VRT,RA,RB - Load Vector for Shift Left
+ *
+ * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
+ * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
+ * Bytes sh:sh+15 of X are placed into vD.
+ */
+static void trans_lvsl(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ TCGv_i64 result = tcg_temp_new_i64();
+ TCGv_i64 sh = tcg_temp_new_i64();
+ TCGv EA = tcg_temp_new();
+
+ /* Get sh(from description) by anding EA with 0xf. */
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_extu_tl_i64(sh, EA);
+ tcg_gen_andi_i64(sh, sh, 0xfULL);
+
+ /*
+ * Create bytes sh:sh+7 of X(from description) and place them in
+ * higher doubleword of vD.
+ */
+ tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
+ tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
+ set_avr64(VT, result, true);
+ /*
+ * Create bytes sh+8:sh+15 of X(from description) and place them in
+ * lower doubleword of vD.
+ */
+ tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
+ set_avr64(VT, result, false);
+
+ tcg_temp_free_i64(result);
+ tcg_temp_free_i64(sh);
+ tcg_temp_free(EA);
+}
+
+/*
+ * lvsr VRT,RA,RB - Load Vector for Shift Right
+ *
+ * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
+ * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
+ * Bytes (16-sh):(31-sh) of X are placed into vD.
+ */
+static void trans_lvsr(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ TCGv_i64 result = tcg_temp_new_i64();
+ TCGv_i64 sh = tcg_temp_new_i64();
+ TCGv EA = tcg_temp_new();
+
+
+ /* Get sh(from description) by anding EA with 0xf. */
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_extu_tl_i64(sh, EA);
+ tcg_gen_andi_i64(sh, sh, 0xfULL);
+
+ /*
+ * Create bytes (16-sh):(23-sh) of X(from description) and place them in
+ * higher doubleword of vD.
+ */
+ tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
+ tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
+ set_avr64(VT, result, true);
+ /*
+ * Create bytes (24-sh):(32-sh) of X(from description) and place them in
+ * lower doubleword of vD.
+ */
+ tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
+ set_avr64(VT, result, false);
+
+ tcg_temp_free_i64(result);
+ tcg_temp_free_i64(sh);
+ tcg_temp_free(EA);
+}
+
+/*
+ * vsl VRT,VRA,VRB - Vector Shift Left
+ *
+ * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
+ * Lowest 3 bits in each byte element of register vB must be identical or
+ * result is undefined.
+ */
+static void trans_vsl(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VA = rA(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 avr = tcg_temp_new_i64();
+ TCGv_i64 sh = tcg_temp_new_i64();
+ TCGv_i64 carry = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ /* Place bits 125-127 of vB in 'sh'. */
+ get_avr64(avr, VB, false);
+ tcg_gen_andi_i64(sh, avr, 0x07ULL);
+
+ /*
+ * Save highest 'sh' bits of lower doubleword element of vA in variable
+ * 'carry' and perform shift on lower doubleword.
+ */
+ get_avr64(avr, VA, false);
+ tcg_gen_subfi_i64(tmp, 32, sh);
+ tcg_gen_shri_i64(carry, avr, 32);
+ tcg_gen_shr_i64(carry, carry, tmp);
+ tcg_gen_shl_i64(avr, avr, sh);
+ set_avr64(VT, avr, false);
+
+ /*
+ * Perform shift on higher doubleword element of vA and replace lowest
+ * 'sh' bits with 'carry'.
+ */
+ get_avr64(avr, VA, true);
+ tcg_gen_shl_i64(avr, avr, sh);
+ tcg_gen_or_i64(avr, avr, carry);
+ set_avr64(VT, avr, true);
+
+ tcg_temp_free_i64(avr);
+ tcg_temp_free_i64(sh);
+ tcg_temp_free_i64(carry);
+ tcg_temp_free_i64(tmp);
+}
+
+/*
+ * vsr VRT,VRA,VRB - Vector Shift Right
+ *
+ * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
+ * Lowest 3 bits in each byte element of register vB must be identical or
+ * result is undefined.
+ */
+static void trans_vsr(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VA = rA(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 avr = tcg_temp_new_i64();
+ TCGv_i64 sh = tcg_temp_new_i64();
+ TCGv_i64 carry = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ /* Place bits 125-127 of vB in 'sh'. */
+ get_avr64(avr, VB, false);
+ tcg_gen_andi_i64(sh, avr, 0x07ULL);
+
+ /*
+ * Save lowest 'sh' bits of higher doubleword element of vA in variable
+ * 'carry' and perform shift on higher doubleword.
+ */
+ get_avr64(avr, VA, true);
+ tcg_gen_subfi_i64(tmp, 32, sh);
+ tcg_gen_shli_i64(carry, avr, 32);
+ tcg_gen_shl_i64(carry, carry, tmp);
+ tcg_gen_shr_i64(avr, avr, sh);
+ set_avr64(VT, avr, true);
+ /*
+ * Perform shift on lower doubleword element of vA and replace highest
+ * 'sh' bits with 'carry'.
+ */
+ get_avr64(avr, VA, false);
+ tcg_gen_shr_i64(avr, avr, sh);
+ tcg_gen_or_i64(avr, avr, carry);
+ set_avr64(VT, avr, false);
+
+ tcg_temp_free_i64(avr);
+ tcg_temp_free_i64(sh);
+ tcg_temp_free_i64(carry);
+ tcg_temp_free_i64(tmp);
+}
+
+/*
+ * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
+ *
+ * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
+ * register are concatenated and placed into ith byte of appropriate doubleword
+ * element in destination register.
+ *
+ * Following solution is done for both doubleword elements of source register
+ * in parallel, in order to reduce the number of instructions needed(that's why
+ * arrays are used):
+ * First, both doubleword elements of source register vB are placed in
+ * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
+ * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
+ * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
+ * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
+ * have to be shifted right for 7 and 8 places, respectively, in order to get
+ * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
+ * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
+ * After first 8 iteration(first loop), all the first bits are in their final
+ * places, all second bits but second bit from eight byte are in their places...
+ * only 1 eight bit from eight byte is in it's place). In second loop we do all
+ * operations symmetrically, in order to get other half of bits in their final
+ * spots. Results for first and second doubleword elements are saved in
+ * result[0] and result[1] respectively. In the end those results are saved in
+ * appropriate doubleword element of destination register vD.
+ */
+static void trans_vgbbd(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ uint64_t mask = 0x8040201008040201ULL;
+ int i, j;
+
+ TCGv_i64 result[2];
+ result[0] = tcg_temp_new_i64();
+ result[1] = tcg_temp_new_i64();
+ TCGv_i64 avr[2];
+ avr[0] = tcg_temp_new_i64();
+ avr[1] = tcg_temp_new_i64();
+ TCGv_i64 tcg_mask = tcg_temp_new_i64();
+
+ tcg_gen_movi_i64(tcg_mask, mask);
+ for (j = 0; j < 2; j++) {
+ get_avr64(avr[j], VB, j);
+ tcg_gen_and_i64(result[j], avr[j], tcg_mask);
+ }
+ for (i = 1; i < 8; i++) {
+ tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
+ for (j = 0; j < 2; j++) {
+ tcg_gen_shri_i64(tmp, avr[j], i * 7);
+ tcg_gen_and_i64(tmp, tmp, tcg_mask);
+ tcg_gen_or_i64(result[j], result[j], tmp);
+ }
+ }
+ for (i = 1; i < 8; i++) {
+ tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
+ for (j = 0; j < 2; j++) {
+ tcg_gen_shli_i64(tmp, avr[j], i * 7);
+ tcg_gen_and_i64(tmp, tmp, tcg_mask);
+ tcg_gen_or_i64(result[j], result[j], tmp);
+ }
+ }
+ for (j = 0; j < 2; j++) {
+ set_avr64(VT, result[j], j);
+ }
+
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(tcg_mask);
+ tcg_temp_free_i64(result[0]);
+ tcg_temp_free_i64(result[1]);
+ tcg_temp_free_i64(avr[0]);
+ tcg_temp_free_i64(avr[1]);
+}
+
+/*
+ * vclzw VRT,VRB - Vector Count Leading Zeros Word
+ *
+ * Counting the number of leading zero bits of each word element in source
+ * register and placing result in appropriate word element of destination
+ * register.
+ */
+static void trans_vclzw(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ int i;
+
+ /* Perform count for every word element using tcg_gen_clzi_i32. */
+ for (i = 0; i < 4; i++) {
+ tcg_gen_ld_i32(tmp, cpu_env,
+ offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
+ tcg_gen_clzi_i32(tmp, tmp, 32);
+ tcg_gen_st_i32(tmp, cpu_env,
+ offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
+ }
+
+ tcg_temp_free_i32(tmp);
+}
+
+/*
+ * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
+ *
+ * Counting the number of leading zero bits of each doubleword element in source
+ * register and placing result in appropriate doubleword element of destination
+ * register.
+ */
+static void trans_vclzd(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 avr = tcg_temp_new_i64();
+
+ /* high doubleword */
+ get_avr64(avr, VB, true);
+ tcg_gen_clzi_i64(avr, avr, 64);
+ set_avr64(VT, avr, true);
+
+ /* low doubleword */
+ get_avr64(avr, VB, false);
+ tcg_gen_clzi_i64(avr, avr, 64);
+ set_avr64(VT, avr, false);
+
+ tcg_temp_free_i64(avr);
+}
+
+GEN_VXFORM(vmuloub, 4, 0);
+GEN_VXFORM(vmulouh, 4, 1);
+GEN_VXFORM(vmulouw, 4, 2);
+GEN_VXFORM(vmuluwm, 4, 2);
+GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
+ vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM(vmulosb, 4, 4);
+GEN_VXFORM(vmulosh, 4, 5);
+GEN_VXFORM(vmulosw, 4, 6);
+GEN_VXFORM(vmuleub, 4, 8);
+GEN_VXFORM(vmuleuh, 4, 9);
+GEN_VXFORM(vmuleuw, 4, 10);
+GEN_VXFORM(vmulesb, 4, 12);
+GEN_VXFORM(vmulesh, 4, 13);
+GEN_VXFORM(vmulesw, 4, 14);
+GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
+GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
+GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
+GEN_VXFORM(vrlwnm, 2, 6);
+GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
+ vrlwnm, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
+GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
+GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
+GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
+GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
+GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
+GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
+GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
+GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
+GEN_VXFORM(vsrv, 2, 28);
+GEN_VXFORM(vslv, 2, 29);
+GEN_VXFORM(vslo, 6, 16);
+GEN_VXFORM(vsro, 6, 17);
+GEN_VXFORM(vaddcuw, 0, 6);
+GEN_VXFORM(vsubcuw, 0, 22);
+
+#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
+static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
+ TCGv_vec sat, TCGv_vec a, \
+ TCGv_vec b) \
+{ \
+ TCGv_vec x = tcg_temp_new_vec_matching(t); \
+ glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
+ glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
+ tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
+ tcg_gen_or_vec(VECE, sat, sat, x); \
+ tcg_temp_free_vec(x); \
+} \
+static void glue(gen_, NAME)(DisasContext *ctx) \
+{ \
+ static const TCGOpcode vecop_list[] = { \
+ glue(glue(INDEX_op_, NORM), _vec), \
+ glue(glue(INDEX_op_, SAT), _vec), \
+ INDEX_op_cmp_vec, 0 \
+ }; \
+ static const GVecGen4 g = { \
+ .fniv = glue(glue(gen_, NAME), _vec), \
+ .fno = glue(gen_helper_, NAME), \
+ .opt_opc = vecop_list, \
+ .write_aofs = true, \
+ .vece = VECE, \
+ }; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
+ offsetof(CPUPPCState, vscr_sat), \
+ avr_full_offset(rA(ctx->opcode)), \
+ avr_full_offset(rB(ctx->opcode)), \
+ 16, 16, &g); \
+}
+
+GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
+GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
+ vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
+GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
+GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
+ vmul10euq, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
+GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
+GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
+GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
+GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
+GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
+GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
+GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
+GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
+GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
+GEN_VXFORM(vadduqm, 0, 4);
+GEN_VXFORM(vaddcuq, 0, 5);
+GEN_VXFORM3(vaddeuqm, 30, 0);
+GEN_VXFORM3(vaddecuq, 30, 0);
+GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
+ vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM(vsubuqm, 0, 20);
+GEN_VXFORM(vsubcuq, 0, 21);
+GEN_VXFORM3(vsubeuqm, 31, 0);
+GEN_VXFORM3(vsubecuq, 31, 0);
+GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
+ vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
+GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
+GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
+GEN_VXFORM(vrlwmi, 2, 2);
+GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
+ vrlwmi, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
+GEN_VXFORM(vrldmi, 2, 3);
+GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
+ vrldmi, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_TRANS(vsl, 2, 7);
+GEN_VXFORM(vrldnm, 2, 7);
+GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
+ vrldnm, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_TRANS(vsr, 2, 11);
+GEN_VXFORM_ENV(vpkuhum, 7, 0);
+GEN_VXFORM_ENV(vpkuwum, 7, 1);
+GEN_VXFORM_ENV(vpkudum, 7, 17);
+GEN_VXFORM_ENV(vpkuhus, 7, 2);
+GEN_VXFORM_ENV(vpkuwus, 7, 3);
+GEN_VXFORM_ENV(vpkudus, 7, 19);
+GEN_VXFORM_ENV(vpkshus, 7, 4);
+GEN_VXFORM_ENV(vpkswus, 7, 5);
+GEN_VXFORM_ENV(vpksdus, 7, 21);
+GEN_VXFORM_ENV(vpkshss, 7, 6);
+GEN_VXFORM_ENV(vpkswss, 7, 7);
+GEN_VXFORM_ENV(vpksdss, 7, 23);
+GEN_VXFORM(vpkpx, 7, 12);
+GEN_VXFORM_ENV(vsum4ubs, 4, 24);
+GEN_VXFORM_ENV(vsum4sbs, 4, 28);
+GEN_VXFORM_ENV(vsum4shs, 4, 25);
+GEN_VXFORM_ENV(vsum2sws, 4, 26);
+GEN_VXFORM_ENV(vsumsws, 4, 30);
+GEN_VXFORM_ENV(vaddfp, 5, 0);
+GEN_VXFORM_ENV(vsubfp, 5, 1);
+GEN_VXFORM_ENV(vmaxfp, 5, 16);
+GEN_VXFORM_ENV(vminfp, 5, 17);
+GEN_VXFORM_HETRO(vextublx, 6, 24)
+GEN_VXFORM_HETRO(vextuhlx, 6, 25)
+GEN_VXFORM_HETRO(vextuwlx, 6, 26)
+GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+ vextuwlx, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_HETRO(vextubrx, 6, 28)
+GEN_VXFORM_HETRO(vextuhrx, 6, 29)
+GEN_VXFORM_HETRO(vextuwrx, 6, 30)
+GEN_VXFORM_TRANS(lvsl, 6, 31)
+GEN_VXFORM_TRANS(lvsr, 6, 32)
+GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
+ vextuwrx, PPC_NONE, PPC2_ISA300)
+
+#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr ra, rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##opname(cpu_env, rd, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+#define GEN_VXRFORM(name, opc2, opc3) \
+ GEN_VXRFORM1(name, name, #name, opc2, opc3) \
+ GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+
+/*
+ * Support for Altivec instructions that use bit 31 (Rc) as an opcode
+ * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
+ * come from different versions of the ISA, so we must also support a
+ * pair of flags for each instruction.
+ */
+#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if ((Rc(ctx->opcode) == 0) && \
+ ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
+ if (Rc21(ctx->opcode) == 0) { \
+ gen_##name0(ctx); \
+ } else { \
+ gen_##name0##_(ctx); \
+ } \
+ } else if ((Rc(ctx->opcode) == 1) && \
+ ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
+ if (Rc21(ctx->opcode) == 0) { \
+ gen_##name1(ctx); \
+ } else { \
+ gen_##name1##_(ctx); \
+ } \
+ } else { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ } \
+}
+
+GEN_VXRFORM(vcmpequb, 3, 0)
+GEN_VXRFORM(vcmpequh, 3, 1)
+GEN_VXRFORM(vcmpequw, 3, 2)
+GEN_VXRFORM(vcmpequd, 3, 3)
+GEN_VXRFORM(vcmpnezb, 3, 4)
+GEN_VXRFORM(vcmpnezh, 3, 5)
+GEN_VXRFORM(vcmpnezw, 3, 6)
+GEN_VXRFORM(vcmpgtsb, 3, 12)
+GEN_VXRFORM(vcmpgtsh, 3, 13)
+GEN_VXRFORM(vcmpgtsw, 3, 14)
+GEN_VXRFORM(vcmpgtsd, 3, 15)
+GEN_VXRFORM(vcmpgtub, 3, 8)
+GEN_VXRFORM(vcmpgtuh, 3, 9)
+GEN_VXRFORM(vcmpgtuw, 3, 10)
+GEN_VXRFORM(vcmpgtud, 3, 11)
+GEN_VXRFORM(vcmpeqfp, 3, 3)
+GEN_VXRFORM(vcmpgefp, 3, 7)
+GEN_VXRFORM(vcmpgtfp, 3, 11)
+GEN_VXRFORM(vcmpbfp, 3, 15)
+GEN_VXRFORM(vcmpneb, 3, 0)
+GEN_VXRFORM(vcmpneh, 3, 1)
+GEN_VXRFORM(vcmpnew, 3, 2)
+
+GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
+ vcmpneb, PPC_NONE, PPC2_ISA300)
+GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
+ vcmpneh, PPC_NONE, PPC2_ISA300)
+GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
+ vcmpnew, PPC_NONE, PPC2_ISA300)
+GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
+ vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
+ vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
+ vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
+
+static void gen_vsplti(DisasContext *ctx, int vece)
+{
+ int simm;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+
+ simm = SIMM5(ctx->opcode);
+ tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
+}
+
+#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
+
+GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
+GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
+GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
+
+#define GEN_VXFORM_NOA(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(rd, rb); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr rb, rd; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rd, rb); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(rd, rb); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
+ tcg_temp_free_ptr(rb); \
+ }
+GEN_VXFORM_NOA(vupkhsb, 7, 8);
+GEN_VXFORM_NOA(vupkhsh, 7, 9);
+GEN_VXFORM_NOA(vupkhsw, 7, 25);
+GEN_VXFORM_NOA(vupklsb, 7, 10);
+GEN_VXFORM_NOA(vupklsh, 7, 11);
+GEN_VXFORM_NOA(vupklsw, 7, 27);
+GEN_VXFORM_NOA(vupkhpx, 7, 13);
+GEN_VXFORM_NOA(vupklpx, 7, 15);
+GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
+GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
+GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
+GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
+GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
+GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
+GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
+GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
+GEN_VXFORM_NOA(vprtybw, 1, 24);
+GEN_VXFORM_NOA(vprtybd, 1, 24);
+GEN_VXFORM_NOA(vprtybq, 1, 24);
+
+static void gen_vsplt(DisasContext *ctx, int vece)
+{
+ int uimm, dofs, bofs;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+
+ uimm = UIMM5(ctx->opcode);
+ bofs = avr_full_offset(rB(ctx->opcode));
+ dofs = avr_full_offset(rD(ctx->opcode));
+
+ /* Experimental testing shows that hardware masks the immediate. */
+ bofs += (uimm << vece) & 15;
+#ifndef HOST_WORDS_BIGENDIAN
+ bofs ^= 15;
+ bofs &= ~((1 << vece) - 1);
+#endif
+
+ tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
+}
+
+#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
+
+#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr rb, rd; \
+ TCGv_i32 uimm; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rd, rb, uimm); \
+ tcg_temp_free_i32(uimm); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_ptr rb, rd; \
+ uint8_t uimm = UIMM4(ctx->opcode); \
+ TCGv_i32 t0; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ if (uimm > splat_max) { \
+ uimm = 0; \
+ } \
+ t0 = tcg_temp_new_i32(); \
+ tcg_gen_movi_i32(t0, uimm); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(rd, rb, t0); \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
+GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
+GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
+GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
+GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
+GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
+GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
+GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
+GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
+GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
+GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
+GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
+GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
+GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
+GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
+GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
+ vextractub, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
+ vextractuh, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
+ vextractuw, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
+ vinsertb, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
+ vinserth, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
+ vinsertw, PPC_NONE, PPC2_ISA300);
+
+static void gen_vsldoi(DisasContext *ctx)
+{
+ TCGv_ptr ra, rb, rd;
+ TCGv_i32 sh;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rb = gen_avr_ptr(rB(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ sh = tcg_const_i32(VSH(ctx->opcode));
+ gen_helper_vsldoi(rd, ra, rb, sh);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rd);
+ tcg_temp_free_i32(sh);
+}
+
+#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+ { \
+ TCGv_ptr ra, rb, rc, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rc = gen_avr_ptr(rC(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ if (Rc(ctx->opcode)) { \
+ gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
+ } else { \
+ gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
+ } \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rc); \
+ tcg_temp_free_ptr(rd); \
+ }
+
+GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
+
+static void gen_vmladduhm(DisasContext *ctx)
+{
+ TCGv_ptr ra, rb, rc, rd;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rb = gen_avr_ptr(rB(ctx->opcode));
+ rc = gen_avr_ptr(rC(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_vmladduhm(rd, ra, rb, rc);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rc);
+ tcg_temp_free_ptr(rd);
+}
+
+static void gen_vpermr(DisasContext *ctx)
+{
+ TCGv_ptr ra, rb, rc, rd;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rb = gen_avr_ptr(rB(ctx->opcode));
+ rc = gen_avr_ptr(rC(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rc);
+ tcg_temp_free_ptr(rd);
+}
+
+GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
+GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
+GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
+GEN_VAFORM_PAIRED(vsel, vperm, 21)
+GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
+
+GEN_VXFORM_NOA(vclzb, 1, 28)
+GEN_VXFORM_NOA(vclzh, 1, 29)
+GEN_VXFORM_TRANS(vclzw, 1, 30)
+GEN_VXFORM_TRANS(vclzd, 1, 31)
+GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
+GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
+GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
+GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
+GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
+GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
+GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
+GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
+GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
+GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
+GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
+GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
+GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
+GEN_VXFORM_NOA(vpopcntb, 1, 28)
+GEN_VXFORM_NOA(vpopcnth, 1, 29)
+GEN_VXFORM_NOA(vpopcntw, 1, 30)
+GEN_VXFORM_NOA(vpopcntd, 1, 31)
+GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
+ vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
+ vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
+ vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
+ vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM(vbpermd, 6, 23);
+GEN_VXFORM(vbpermq, 6, 21);
+GEN_VXFORM_TRANS(vgbbd, 6, 20);
+GEN_VXFORM(vpmsumb, 4, 16)
+GEN_VXFORM(vpmsumh, 4, 17)
+GEN_VXFORM(vpmsumw, 4, 18)
+GEN_VXFORM(vpmsumd, 4, 19)
+
+#define GEN_BCD(op) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rb, rd; \
+ TCGv_i32 ps; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ \
+ ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+ \
+ gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
+ \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ tcg_temp_free_i32(ps); \
+}
+
+#define GEN_BCD2(op) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ TCGv_ptr rd, rb; \
+ TCGv_i32 ps; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ \
+ ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+ \
+ gen_helper_##op(cpu_crf[6], rd, rb, ps); \
+ \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+ tcg_temp_free_i32(ps); \
+}
+
+GEN_BCD(bcdadd)
+GEN_BCD(bcdsub)
+GEN_BCD2(bcdcfn)
+GEN_BCD2(bcdctn)
+GEN_BCD2(bcdcfz)
+GEN_BCD2(bcdctz)
+GEN_BCD2(bcdcfsq)
+GEN_BCD2(bcdctsq)
+GEN_BCD2(bcdsetsgn)
+GEN_BCD(bcdcpsgn);
+GEN_BCD(bcds);
+GEN_BCD(bcdus);
+GEN_BCD(bcdsr);
+GEN_BCD(bcdtrunc);
+GEN_BCD(bcdutrunc);
+
+static void gen_xpnd04_1(DisasContext *ctx)
+{
+ switch (opc4(ctx->opcode)) {
+ case 0:
+ gen_bcdctsq(ctx);
+ break;
+ case 2:
+ gen_bcdcfsq(ctx);
+ break;
+ case 4:
+ gen_bcdctz(ctx);
+ break;
+ case 5:
+ gen_bcdctn(ctx);
+ break;
+ case 6:
+ gen_bcdcfz(ctx);
+ break;
+ case 7:
+ gen_bcdcfn(ctx);
+ break;
+ case 31:
+ gen_bcdsetsgn(ctx);
+ break;
+ default:
+ gen_invalid(ctx);
+ break;
+ }
+}
+
+static void gen_xpnd04_2(DisasContext *ctx)
+{
+ switch (opc4(ctx->opcode)) {
+ case 0:
+ gen_bcdctsq(ctx);
+ break;
+ case 2:
+ gen_bcdcfsq(ctx);
+ break;
+ case 4:
+ gen_bcdctz(ctx);
+ break;
+ case 6:
+ gen_bcdcfz(ctx);
+ break;
+ case 7:
+ gen_bcdcfn(ctx);
+ break;
+ case 31:
+ gen_bcdsetsgn(ctx);
+ break;
+ default:
+ gen_invalid(ctx);
+ break;
+ }
+}
+
+
+GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
+ xpnd04_1, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
+ xpnd04_2, PPC_NONE, PPC2_ISA300)
+
+GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
+ bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
+ bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
+ bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
+ bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
+ bcdcpsgn, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
+ bcds, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
+ bcdus, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
+ bcdtrunc, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
+ bcdtrunc, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
+ bcdutrunc, PPC_NONE, PPC2_ISA300)
+
+
+static void gen_vsbox(DisasContext *ctx)
+{
+ TCGv_ptr ra, rd;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_vsbox(rd, ra);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rd);
+}
+
+GEN_VXFORM(vcipher, 4, 20)
+GEN_VXFORM(vcipherlast, 4, 20)
+GEN_VXFORM(vncipher, 4, 21)
+GEN_VXFORM(vncipherlast, 4, 21)
+
+GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
+ vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
+ vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
+
+#define VSHASIGMA(op) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rd; \
+ TCGv_i32 st_six; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ st_six = tcg_const_i32(rB(ctx->opcode)); \
+ gen_helper_##op(rd, ra, st_six); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rd); \
+ tcg_temp_free_i32(st_six); \
+}
+
+VSHASIGMA(vshasigmaw)
+VSHASIGMA(vshasigmad)
+
+GEN_VXFORM3(vpermxor, 22, 0xFF)
+GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
+ vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
+
+#undef GEN_VR_LDX
+#undef GEN_VR_STX
+#undef GEN_VR_LVE
+#undef GEN_VR_STVE
+
+#undef GEN_VX_LOGICAL
+#undef GEN_VX_LOGICAL_207
+#undef GEN_VXFORM
+#undef GEN_VXFORM_207
+#undef GEN_VXFORM_DUAL
+#undef GEN_VXRFORM_DUAL
+#undef GEN_VXRFORM1
+#undef GEN_VXRFORM
+#undef GEN_VXFORM_VSPLTI
+#undef GEN_VXFORM_NOA
+#undef GEN_VXFORM_UIMM
+#undef GEN_VAFORM_PAIRED
+
+#undef GEN_BCD2
+++ /dev/null
-/*
- * translate/vmx-impl.c
- *
- * Altivec/VMX translation
- */
-
-/*** Altivec vector extension ***/
-/* Altivec registers moves */
-
-static inline TCGv_ptr gen_avr_ptr(int reg)
-{
- TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
- return r;
-}
-
-#define GEN_VR_LDX(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 avr; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- avr = tcg_temp_new_i64(); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- tcg_gen_andi_tl(EA, EA, ~0xf); \
- /* \
- * We only need to swap high and low halves. gen_qemu_ld64_i64 \
- * does necessary 64-bit byteswap already. \
- */ \
- if (ctx->le_mode) { \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, false); \
- tcg_gen_addi_tl(EA, EA, 8); \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, true); \
- } else { \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, true); \
- tcg_gen_addi_tl(EA, EA, 8); \
- gen_qemu_ld64_i64(ctx, avr, EA); \
- set_avr64(rD(ctx->opcode), avr, false); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(avr); \
-}
-
-#define GEN_VR_STX(name, opc2, opc3) \
-static void gen_st##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 avr; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- avr = tcg_temp_new_i64(); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- tcg_gen_andi_tl(EA, EA, ~0xf); \
- /* \
- * We only need to swap high and low halves. gen_qemu_st64_i64 \
- * does necessary 64-bit byteswap already. \
- */ \
- if (ctx->le_mode) { \
- get_avr64(avr, rD(ctx->opcode), false); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- tcg_gen_addi_tl(EA, EA, 8); \
- get_avr64(avr, rD(ctx->opcode), true); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- } else { \
- get_avr64(avr, rD(ctx->opcode), true); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- tcg_gen_addi_tl(EA, EA, 8); \
- get_avr64(avr, rD(ctx->opcode), false); \
- gen_qemu_st64_i64(ctx, avr, EA); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(avr); \
-}
-
-#define GEN_VR_LVE(name, opc2, opc3, size) \
-static void gen_lve##name(DisasContext *ctx) \
- { \
- TCGv EA; \
- TCGv_ptr rs; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- if (size > 1) { \
- tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
- } \
- rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_lve##name(cpu_env, rs, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_ptr(rs); \
- }
-
-#define GEN_VR_STVE(name, opc2, opc3, size) \
-static void gen_stve##name(DisasContext *ctx) \
- { \
- TCGv EA; \
- TCGv_ptr rs; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- if (size > 1) { \
- tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
- } \
- rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_stve##name(cpu_env, rs, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_ptr(rs); \
- }
-
-GEN_VR_LDX(lvx, 0x07, 0x03);
-/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
-GEN_VR_LDX(lvxl, 0x07, 0x0B);
-
-GEN_VR_LVE(bx, 0x07, 0x00, 1);
-GEN_VR_LVE(hx, 0x07, 0x01, 2);
-GEN_VR_LVE(wx, 0x07, 0x02, 4);
-
-GEN_VR_STX(svx, 0x07, 0x07);
-/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
-GEN_VR_STX(svxl, 0x07, 0x0F);
-
-GEN_VR_STVE(bx, 0x07, 0x04, 1);
-GEN_VR_STVE(hx, 0x07, 0x05, 2);
-GEN_VR_STVE(wx, 0x07, 0x06, 4);
-
-static void gen_mfvscr(DisasContext *ctx)
-{
- TCGv_i32 t;
- TCGv_i64 avr;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- avr = tcg_temp_new_i64();
- tcg_gen_movi_i64(avr, 0);
- set_avr64(rD(ctx->opcode), avr, true);
- t = tcg_temp_new_i32();
- gen_helper_mfvscr(t, cpu_env);
- tcg_gen_extu_i32_i64(avr, t);
- set_avr64(rD(ctx->opcode), avr, false);
- tcg_temp_free_i32(t);
- tcg_temp_free_i64(avr);
-}
-
-static void gen_mtvscr(DisasContext *ctx)
-{
- TCGv_i32 val;
- int bofs;
-
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
-
- val = tcg_temp_new_i32();
- bofs = avr_full_offset(rB(ctx->opcode));
-#ifdef HOST_WORDS_BIGENDIAN
- bofs += 3 * 4;
-#endif
-
- tcg_gen_ld_i32(val, cpu_env, bofs);
- gen_helper_mtvscr(cpu_env, val);
- tcg_temp_free_i32(val);
-}
-
-#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
- TCGv_i64 avr; \
- TCGv_i64 ten, z; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- avr = tcg_temp_new_i64(); \
- ten = tcg_const_i64(10); \
- z = tcg_const_i64(0); \
- \
- if (add_cin) { \
- get_avr64(avr, rA(ctx->opcode), false); \
- tcg_gen_mulu2_i64(t0, t1, avr, ten); \
- get_avr64(avr, rB(ctx->opcode), false); \
- tcg_gen_andi_i64(t2, avr, 0xF); \
- tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
- set_avr64(rD(ctx->opcode), avr, false); \
- } else { \
- get_avr64(avr, rA(ctx->opcode), false); \
- tcg_gen_mulu2_i64(avr, t2, avr, ten); \
- set_avr64(rD(ctx->opcode), avr, false); \
- } \
- \
- if (ret_carry) { \
- get_avr64(avr, rA(ctx->opcode), true); \
- tcg_gen_mulu2_i64(t0, t1, avr, ten); \
- tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
- set_avr64(rD(ctx->opcode), avr, false); \
- set_avr64(rD(ctx->opcode), z, true); \
- } else { \
- get_avr64(avr, rA(ctx->opcode), true); \
- tcg_gen_mul_i64(t0, avr, ten); \
- tcg_gen_add_i64(avr, t0, t2); \
- set_avr64(rD(ctx->opcode), avr, true); \
- } \
- \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(t2); \
- tcg_temp_free_i64(avr); \
- tcg_temp_free_i64(ten); \
- tcg_temp_free_i64(z); \
-} \
-
-GEN_VX_VMUL10(vmul10uq, 0, 0);
-GEN_VX_VMUL10(vmul10euq, 1, 0);
-GEN_VX_VMUL10(vmul10cuq, 0, 1);
-GEN_VX_VMUL10(vmul10ecuq, 1, 1);
-
-#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- \
- tcg_op(vece, \
- avr_full_offset(rD(ctx->opcode)), \
- avr_full_offset(rA(ctx->opcode)), \
- avr_full_offset(rB(ctx->opcode)), \
- 16, 16); \
-}
-
-/* Logical operations */
-GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
-GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
-GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
-GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
-GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
-GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
-GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
-GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
-
-#define GEN_VXFORM(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rb, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(rd, ra, rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
-}
-
-#define GEN_VXFORM_TRANS(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- trans_##name(ctx); \
-}
-
-#define GEN_VXFORM_ENV(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rb, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, ra, rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
-}
-
-#define GEN_VXFORM3(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rb, rc, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rc = gen_avr_ptr(rC(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(rd, ra, rb, rc); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rc); \
- tcg_temp_free_ptr(rd); \
-}
-
-/*
- * Support for Altivec instruction pairs that use bit 31 (Rc) as
- * an opcode bit. In general, these pairs come from different
- * versions of the ISA, so we must also support a pair of flags for
- * each instruction.
- */
-#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
-static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
-{ \
- if ((Rc(ctx->opcode) == 0) && \
- ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
- gen_##name0(ctx); \
- } else if ((Rc(ctx->opcode) == 1) && \
- ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
- gen_##name1(ctx); \
- } else { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- } \
-}
-
-/*
- * We use this macro if one instruction is realized with direct
- * translation, and second one with helper.
- */
-#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
-static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
-{ \
- if ((Rc(ctx->opcode) == 0) && \
- ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- trans_##name0(ctx); \
- } else if ((Rc(ctx->opcode) == 1) && \
- ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
- gen_##name1(ctx); \
- } else { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- } \
-}
-
-/* Adds support to provide invalid mask */
-#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
- name1, flg1, flg2_1, inval1) \
-static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
-{ \
- if ((Rc(ctx->opcode) == 0) && \
- ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
- !(ctx->opcode & inval0)) { \
- gen_##name0(ctx); \
- } else if ((Rc(ctx->opcode) == 1) && \
- ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
- !(ctx->opcode & inval1)) { \
- gen_##name1(ctx); \
- } else { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- } \
-}
-
-#define GEN_VXFORM_HETRO(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv_ptr rb; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
- tcg_temp_free_ptr(rb); \
-}
-
-GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
-GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
- vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
-GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
-GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
- vmul10ecuq, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
-GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
-GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
-GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
-GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
-GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
-GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
-GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
-GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
-GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
-GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
-GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
-GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
-GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
-GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
-GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
-GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
-GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
-GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
-GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
-GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
-GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
-GEN_VXFORM(vavgub, 1, 16);
-GEN_VXFORM(vabsdub, 1, 16);
-GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
- vabsdub, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM(vavguh, 1, 17);
-GEN_VXFORM(vabsduh, 1, 17);
-GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
- vabsduh, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM(vavguw, 1, 18);
-GEN_VXFORM(vabsduw, 1, 18);
-GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
- vabsduw, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM(vavgsb, 1, 20);
-GEN_VXFORM(vavgsh, 1, 21);
-GEN_VXFORM(vavgsw, 1, 22);
-GEN_VXFORM(vmrghb, 6, 0);
-GEN_VXFORM(vmrghh, 6, 1);
-GEN_VXFORM(vmrghw, 6, 2);
-GEN_VXFORM(vmrglb, 6, 4);
-GEN_VXFORM(vmrglh, 6, 5);
-GEN_VXFORM(vmrglw, 6, 6);
-
-static void trans_vmrgew(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VA = rA(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv_i64 avr = tcg_temp_new_i64();
-
- get_avr64(avr, VB, true);
- tcg_gen_shri_i64(tmp, avr, 32);
- get_avr64(avr, VA, true);
- tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
- set_avr64(VT, avr, true);
-
- get_avr64(avr, VB, false);
- tcg_gen_shri_i64(tmp, avr, 32);
- get_avr64(avr, VA, false);
- tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
- set_avr64(VT, avr, false);
-
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(avr);
-}
-
-static void trans_vmrgow(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VA = rA(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 avr = tcg_temp_new_i64();
-
- get_avr64(t0, VB, true);
- get_avr64(t1, VA, true);
- tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
- set_avr64(VT, avr, true);
-
- get_avr64(t0, VB, false);
- get_avr64(t1, VA, false);
- tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
- set_avr64(VT, avr, false);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(avr);
-}
-
-/*
- * lvsl VRT,RA,RB - Load Vector for Shift Left
- *
- * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
- * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
- * Bytes sh:sh+15 of X are placed into vD.
- */
-static void trans_lvsl(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- TCGv_i64 result = tcg_temp_new_i64();
- TCGv_i64 sh = tcg_temp_new_i64();
- TCGv EA = tcg_temp_new();
-
- /* Get sh(from description) by anding EA with 0xf. */
- gen_addr_reg_index(ctx, EA);
- tcg_gen_extu_tl_i64(sh, EA);
- tcg_gen_andi_i64(sh, sh, 0xfULL);
-
- /*
- * Create bytes sh:sh+7 of X(from description) and place them in
- * higher doubleword of vD.
- */
- tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
- tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
- set_avr64(VT, result, true);
- /*
- * Create bytes sh+8:sh+15 of X(from description) and place them in
- * lower doubleword of vD.
- */
- tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
- set_avr64(VT, result, false);
-
- tcg_temp_free_i64(result);
- tcg_temp_free_i64(sh);
- tcg_temp_free(EA);
-}
-
-/*
- * lvsr VRT,RA,RB - Load Vector for Shift Right
- *
- * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
- * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
- * Bytes (16-sh):(31-sh) of X are placed into vD.
- */
-static void trans_lvsr(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- TCGv_i64 result = tcg_temp_new_i64();
- TCGv_i64 sh = tcg_temp_new_i64();
- TCGv EA = tcg_temp_new();
-
-
- /* Get sh(from description) by anding EA with 0xf. */
- gen_addr_reg_index(ctx, EA);
- tcg_gen_extu_tl_i64(sh, EA);
- tcg_gen_andi_i64(sh, sh, 0xfULL);
-
- /*
- * Create bytes (16-sh):(23-sh) of X(from description) and place them in
- * higher doubleword of vD.
- */
- tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
- tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
- set_avr64(VT, result, true);
- /*
- * Create bytes (24-sh):(32-sh) of X(from description) and place them in
- * lower doubleword of vD.
- */
- tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
- set_avr64(VT, result, false);
-
- tcg_temp_free_i64(result);
- tcg_temp_free_i64(sh);
- tcg_temp_free(EA);
-}
-
-/*
- * vsl VRT,VRA,VRB - Vector Shift Left
- *
- * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
- * Lowest 3 bits in each byte element of register vB must be identical or
- * result is undefined.
- */
-static void trans_vsl(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VA = rA(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i64 avr = tcg_temp_new_i64();
- TCGv_i64 sh = tcg_temp_new_i64();
- TCGv_i64 carry = tcg_temp_new_i64();
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- /* Place bits 125-127 of vB in 'sh'. */
- get_avr64(avr, VB, false);
- tcg_gen_andi_i64(sh, avr, 0x07ULL);
-
- /*
- * Save highest 'sh' bits of lower doubleword element of vA in variable
- * 'carry' and perform shift on lower doubleword.
- */
- get_avr64(avr, VA, false);
- tcg_gen_subfi_i64(tmp, 32, sh);
- tcg_gen_shri_i64(carry, avr, 32);
- tcg_gen_shr_i64(carry, carry, tmp);
- tcg_gen_shl_i64(avr, avr, sh);
- set_avr64(VT, avr, false);
-
- /*
- * Perform shift on higher doubleword element of vA and replace lowest
- * 'sh' bits with 'carry'.
- */
- get_avr64(avr, VA, true);
- tcg_gen_shl_i64(avr, avr, sh);
- tcg_gen_or_i64(avr, avr, carry);
- set_avr64(VT, avr, true);
-
- tcg_temp_free_i64(avr);
- tcg_temp_free_i64(sh);
- tcg_temp_free_i64(carry);
- tcg_temp_free_i64(tmp);
-}
-
-/*
- * vsr VRT,VRA,VRB - Vector Shift Right
- *
- * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
- * Lowest 3 bits in each byte element of register vB must be identical or
- * result is undefined.
- */
-static void trans_vsr(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VA = rA(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i64 avr = tcg_temp_new_i64();
- TCGv_i64 sh = tcg_temp_new_i64();
- TCGv_i64 carry = tcg_temp_new_i64();
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- /* Place bits 125-127 of vB in 'sh'. */
- get_avr64(avr, VB, false);
- tcg_gen_andi_i64(sh, avr, 0x07ULL);
-
- /*
- * Save lowest 'sh' bits of higher doubleword element of vA in variable
- * 'carry' and perform shift on higher doubleword.
- */
- get_avr64(avr, VA, true);
- tcg_gen_subfi_i64(tmp, 32, sh);
- tcg_gen_shli_i64(carry, avr, 32);
- tcg_gen_shl_i64(carry, carry, tmp);
- tcg_gen_shr_i64(avr, avr, sh);
- set_avr64(VT, avr, true);
- /*
- * Perform shift on lower doubleword element of vA and replace highest
- * 'sh' bits with 'carry'.
- */
- get_avr64(avr, VA, false);
- tcg_gen_shr_i64(avr, avr, sh);
- tcg_gen_or_i64(avr, avr, carry);
- set_avr64(VT, avr, false);
-
- tcg_temp_free_i64(avr);
- tcg_temp_free_i64(sh);
- tcg_temp_free_i64(carry);
- tcg_temp_free_i64(tmp);
-}
-
-/*
- * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
- *
- * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
- * register are concatenated and placed into ith byte of appropriate doubleword
- * element in destination register.
- *
- * Following solution is done for both doubleword elements of source register
- * in parallel, in order to reduce the number of instructions needed(that's why
- * arrays are used):
- * First, both doubleword elements of source register vB are placed in
- * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
- * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
- * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
- * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
- * have to be shifted right for 7 and 8 places, respectively, in order to get
- * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
- * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
- * After first 8 iteration(first loop), all the first bits are in their final
- * places, all second bits but second bit from eight byte are in their places...
- * only 1 eight bit from eight byte is in it's place). In second loop we do all
- * operations symmetrically, in order to get other half of bits in their final
- * spots. Results for first and second doubleword elements are saved in
- * result[0] and result[1] respectively. In the end those results are saved in
- * appropriate doubleword element of destination register vD.
- */
-static void trans_vgbbd(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i64 tmp = tcg_temp_new_i64();
- uint64_t mask = 0x8040201008040201ULL;
- int i, j;
-
- TCGv_i64 result[2];
- result[0] = tcg_temp_new_i64();
- result[1] = tcg_temp_new_i64();
- TCGv_i64 avr[2];
- avr[0] = tcg_temp_new_i64();
- avr[1] = tcg_temp_new_i64();
- TCGv_i64 tcg_mask = tcg_temp_new_i64();
-
- tcg_gen_movi_i64(tcg_mask, mask);
- for (j = 0; j < 2; j++) {
- get_avr64(avr[j], VB, j);
- tcg_gen_and_i64(result[j], avr[j], tcg_mask);
- }
- for (i = 1; i < 8; i++) {
- tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
- for (j = 0; j < 2; j++) {
- tcg_gen_shri_i64(tmp, avr[j], i * 7);
- tcg_gen_and_i64(tmp, tmp, tcg_mask);
- tcg_gen_or_i64(result[j], result[j], tmp);
- }
- }
- for (i = 1; i < 8; i++) {
- tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
- for (j = 0; j < 2; j++) {
- tcg_gen_shli_i64(tmp, avr[j], i * 7);
- tcg_gen_and_i64(tmp, tmp, tcg_mask);
- tcg_gen_or_i64(result[j], result[j], tmp);
- }
- }
- for (j = 0; j < 2; j++) {
- set_avr64(VT, result[j], j);
- }
-
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(tcg_mask);
- tcg_temp_free_i64(result[0]);
- tcg_temp_free_i64(result[1]);
- tcg_temp_free_i64(avr[0]);
- tcg_temp_free_i64(avr[1]);
-}
-
-/*
- * vclzw VRT,VRB - Vector Count Leading Zeros Word
- *
- * Counting the number of leading zero bits of each word element in source
- * register and placing result in appropriate word element of destination
- * register.
- */
-static void trans_vclzw(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i32 tmp = tcg_temp_new_i32();
- int i;
-
- /* Perform count for every word element using tcg_gen_clzi_i32. */
- for (i = 0; i < 4; i++) {
- tcg_gen_ld_i32(tmp, cpu_env,
- offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
- tcg_gen_clzi_i32(tmp, tmp, 32);
- tcg_gen_st_i32(tmp, cpu_env,
- offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
- }
-
- tcg_temp_free_i32(tmp);
-}
-
-/*
- * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
- *
- * Counting the number of leading zero bits of each doubleword element in source
- * register and placing result in appropriate doubleword element of destination
- * register.
- */
-static void trans_vclzd(DisasContext *ctx)
-{
- int VT = rD(ctx->opcode);
- int VB = rB(ctx->opcode);
- TCGv_i64 avr = tcg_temp_new_i64();
-
- /* high doubleword */
- get_avr64(avr, VB, true);
- tcg_gen_clzi_i64(avr, avr, 64);
- set_avr64(VT, avr, true);
-
- /* low doubleword */
- get_avr64(avr, VB, false);
- tcg_gen_clzi_i64(avr, avr, 64);
- set_avr64(VT, avr, false);
-
- tcg_temp_free_i64(avr);
-}
-
-GEN_VXFORM(vmuloub, 4, 0);
-GEN_VXFORM(vmulouh, 4, 1);
-GEN_VXFORM(vmulouw, 4, 2);
-GEN_VXFORM(vmuluwm, 4, 2);
-GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
- vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM(vmulosb, 4, 4);
-GEN_VXFORM(vmulosh, 4, 5);
-GEN_VXFORM(vmulosw, 4, 6);
-GEN_VXFORM(vmuleub, 4, 8);
-GEN_VXFORM(vmuleuh, 4, 9);
-GEN_VXFORM(vmuleuw, 4, 10);
-GEN_VXFORM(vmulesb, 4, 12);
-GEN_VXFORM(vmulesh, 4, 13);
-GEN_VXFORM(vmulesw, 4, 14);
-GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
-GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
-GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
-GEN_VXFORM(vrlwnm, 2, 6);
-GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
- vrlwnm, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
-GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
-GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
-GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
-GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
-GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
-GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
-GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
-GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
-GEN_VXFORM(vsrv, 2, 28);
-GEN_VXFORM(vslv, 2, 29);
-GEN_VXFORM(vslo, 6, 16);
-GEN_VXFORM(vsro, 6, 17);
-GEN_VXFORM(vaddcuw, 0, 6);
-GEN_VXFORM(vsubcuw, 0, 22);
-
-#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
-static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
- TCGv_vec sat, TCGv_vec a, \
- TCGv_vec b) \
-{ \
- TCGv_vec x = tcg_temp_new_vec_matching(t); \
- glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
- glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
- tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
- tcg_gen_or_vec(VECE, sat, sat, x); \
- tcg_temp_free_vec(x); \
-} \
-static void glue(gen_, NAME)(DisasContext *ctx) \
-{ \
- static const TCGOpcode vecop_list[] = { \
- glue(glue(INDEX_op_, NORM), _vec), \
- glue(glue(INDEX_op_, SAT), _vec), \
- INDEX_op_cmp_vec, 0 \
- }; \
- static const GVecGen4 g = { \
- .fniv = glue(glue(gen_, NAME), _vec), \
- .fno = glue(gen_helper_, NAME), \
- .opt_opc = vecop_list, \
- .write_aofs = true, \
- .vece = VECE, \
- }; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
- offsetof(CPUPPCState, vscr_sat), \
- avr_full_offset(rA(ctx->opcode)), \
- avr_full_offset(rB(ctx->opcode)), \
- 16, 16, &g); \
-}
-
-GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
-GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
- vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
-GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
-GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
- vmul10euq, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
-GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
-GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
-GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
-GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
-GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
-GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
-GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
-GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
-GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
-GEN_VXFORM(vadduqm, 0, 4);
-GEN_VXFORM(vaddcuq, 0, 5);
-GEN_VXFORM3(vaddeuqm, 30, 0);
-GEN_VXFORM3(vaddecuq, 30, 0);
-GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
- vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM(vsubuqm, 0, 20);
-GEN_VXFORM(vsubcuq, 0, 21);
-GEN_VXFORM3(vsubeuqm, 31, 0);
-GEN_VXFORM3(vsubecuq, 31, 0);
-GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
- vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
-GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
-GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
-GEN_VXFORM(vrlwmi, 2, 2);
-GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
- vrlwmi, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
-GEN_VXFORM(vrldmi, 2, 3);
-GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
- vrldmi, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_TRANS(vsl, 2, 7);
-GEN_VXFORM(vrldnm, 2, 7);
-GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
- vrldnm, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_TRANS(vsr, 2, 11);
-GEN_VXFORM_ENV(vpkuhum, 7, 0);
-GEN_VXFORM_ENV(vpkuwum, 7, 1);
-GEN_VXFORM_ENV(vpkudum, 7, 17);
-GEN_VXFORM_ENV(vpkuhus, 7, 2);
-GEN_VXFORM_ENV(vpkuwus, 7, 3);
-GEN_VXFORM_ENV(vpkudus, 7, 19);
-GEN_VXFORM_ENV(vpkshus, 7, 4);
-GEN_VXFORM_ENV(vpkswus, 7, 5);
-GEN_VXFORM_ENV(vpksdus, 7, 21);
-GEN_VXFORM_ENV(vpkshss, 7, 6);
-GEN_VXFORM_ENV(vpkswss, 7, 7);
-GEN_VXFORM_ENV(vpksdss, 7, 23);
-GEN_VXFORM(vpkpx, 7, 12);
-GEN_VXFORM_ENV(vsum4ubs, 4, 24);
-GEN_VXFORM_ENV(vsum4sbs, 4, 28);
-GEN_VXFORM_ENV(vsum4shs, 4, 25);
-GEN_VXFORM_ENV(vsum2sws, 4, 26);
-GEN_VXFORM_ENV(vsumsws, 4, 30);
-GEN_VXFORM_ENV(vaddfp, 5, 0);
-GEN_VXFORM_ENV(vsubfp, 5, 1);
-GEN_VXFORM_ENV(vmaxfp, 5, 16);
-GEN_VXFORM_ENV(vminfp, 5, 17);
-GEN_VXFORM_HETRO(vextublx, 6, 24)
-GEN_VXFORM_HETRO(vextuhlx, 6, 25)
-GEN_VXFORM_HETRO(vextuwlx, 6, 26)
-GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
- vextuwlx, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_HETRO(vextubrx, 6, 28)
-GEN_VXFORM_HETRO(vextuhrx, 6, 29)
-GEN_VXFORM_HETRO(vextuwrx, 6, 30)
-GEN_VXFORM_TRANS(lvsl, 6, 31)
-GEN_VXFORM_TRANS(lvsr, 6, 32)
-GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
- vextuwrx, PPC_NONE, PPC2_ISA300)
-
-#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr ra, rb, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##opname(cpu_env, rd, ra, rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- }
-
-#define GEN_VXRFORM(name, opc2, opc3) \
- GEN_VXRFORM1(name, name, #name, opc2, opc3) \
- GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
-
-/*
- * Support for Altivec instructions that use bit 31 (Rc) as an opcode
- * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
- * come from different versions of the ISA, so we must also support a
- * pair of flags for each instruction.
- */
-#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
-static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
-{ \
- if ((Rc(ctx->opcode) == 0) && \
- ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
- if (Rc21(ctx->opcode) == 0) { \
- gen_##name0(ctx); \
- } else { \
- gen_##name0##_(ctx); \
- } \
- } else if ((Rc(ctx->opcode) == 1) && \
- ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
- if (Rc21(ctx->opcode) == 0) { \
- gen_##name1(ctx); \
- } else { \
- gen_##name1##_(ctx); \
- } \
- } else { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- } \
-}
-
-GEN_VXRFORM(vcmpequb, 3, 0)
-GEN_VXRFORM(vcmpequh, 3, 1)
-GEN_VXRFORM(vcmpequw, 3, 2)
-GEN_VXRFORM(vcmpequd, 3, 3)
-GEN_VXRFORM(vcmpnezb, 3, 4)
-GEN_VXRFORM(vcmpnezh, 3, 5)
-GEN_VXRFORM(vcmpnezw, 3, 6)
-GEN_VXRFORM(vcmpgtsb, 3, 12)
-GEN_VXRFORM(vcmpgtsh, 3, 13)
-GEN_VXRFORM(vcmpgtsw, 3, 14)
-GEN_VXRFORM(vcmpgtsd, 3, 15)
-GEN_VXRFORM(vcmpgtub, 3, 8)
-GEN_VXRFORM(vcmpgtuh, 3, 9)
-GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM(vcmpgtud, 3, 11)
-GEN_VXRFORM(vcmpeqfp, 3, 3)
-GEN_VXRFORM(vcmpgefp, 3, 7)
-GEN_VXRFORM(vcmpgtfp, 3, 11)
-GEN_VXRFORM(vcmpbfp, 3, 15)
-GEN_VXRFORM(vcmpneb, 3, 0)
-GEN_VXRFORM(vcmpneh, 3, 1)
-GEN_VXRFORM(vcmpnew, 3, 2)
-
-GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
- vcmpneb, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
- vcmpneh, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
- vcmpnew, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
-
-static void gen_vsplti(DisasContext *ctx, int vece)
-{
- int simm;
-
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
-
- simm = SIMM5(ctx->opcode);
- tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
-}
-
-#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
-
-GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
-GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
-GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
-
-#define GEN_VXFORM_NOA(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(rd, rb); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- }
-
-#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb, rd; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, rb); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- }
-
-#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(rd, rb); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- }
-
-#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
- tcg_temp_free_ptr(rb); \
- }
-GEN_VXFORM_NOA(vupkhsb, 7, 8);
-GEN_VXFORM_NOA(vupkhsh, 7, 9);
-GEN_VXFORM_NOA(vupkhsw, 7, 25);
-GEN_VXFORM_NOA(vupklsb, 7, 10);
-GEN_VXFORM_NOA(vupklsh, 7, 11);
-GEN_VXFORM_NOA(vupklsw, 7, 27);
-GEN_VXFORM_NOA(vupkhpx, 7, 13);
-GEN_VXFORM_NOA(vupklpx, 7, 15);
-GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
-GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
-GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
-GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
-GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
-GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
-GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
-GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
-GEN_VXFORM_NOA(vprtybw, 1, 24);
-GEN_VXFORM_NOA(vprtybd, 1, 24);
-GEN_VXFORM_NOA(vprtybq, 1, 24);
-
-static void gen_vsplt(DisasContext *ctx, int vece)
-{
- int uimm, dofs, bofs;
-
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
-
- uimm = UIMM5(ctx->opcode);
- bofs = avr_full_offset(rB(ctx->opcode));
- dofs = avr_full_offset(rD(ctx->opcode));
-
- /* Experimental testing shows that hardware masks the immediate. */
- bofs += (uimm << vece) & 15;
-#ifndef HOST_WORDS_BIGENDIAN
- bofs ^= 15;
- bofs &= ~((1 << vece) - 1);
-#endif
-
- tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
-}
-
-#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
-
-#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb, rd; \
- TCGv_i32 uimm; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, rb, uimm); \
- tcg_temp_free_i32(uimm); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- }
-
-#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb, rd; \
- uint8_t uimm = UIMM4(ctx->opcode); \
- TCGv_i32 t0; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- if (uimm > splat_max) { \
- uimm = 0; \
- } \
- t0 = tcg_temp_new_i32(); \
- tcg_gen_movi_i32(t0, uimm); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(rd, rb, t0); \
- tcg_temp_free_i32(t0); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- }
-
-GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
-GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
-GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
-GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
-GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
-GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
-GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
-GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
-GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
-GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
-GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
-GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
-GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
-GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
-GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
-GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
- vextractub, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
- vextractuh, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
- vextractuw, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
- vinsertb, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
- vinserth, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
- vinsertw, PPC_NONE, PPC2_ISA300);
-
-static void gen_vsldoi(DisasContext *ctx)
-{
- TCGv_ptr ra, rb, rd;
- TCGv_i32 sh;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- ra = gen_avr_ptr(rA(ctx->opcode));
- rb = gen_avr_ptr(rB(ctx->opcode));
- rd = gen_avr_ptr(rD(ctx->opcode));
- sh = tcg_const_i32(VSH(ctx->opcode));
- gen_helper_vsldoi(rd, ra, rb, sh);
- tcg_temp_free_ptr(ra);
- tcg_temp_free_ptr(rb);
- tcg_temp_free_ptr(rd);
- tcg_temp_free_i32(sh);
-}
-
-#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
-static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
- { \
- TCGv_ptr ra, rb, rc, rd; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rc = gen_avr_ptr(rC(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- if (Rc(ctx->opcode)) { \
- gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
- } else { \
- gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
- } \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rc); \
- tcg_temp_free_ptr(rd); \
- }
-
-GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
-
-static void gen_vmladduhm(DisasContext *ctx)
-{
- TCGv_ptr ra, rb, rc, rd;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- ra = gen_avr_ptr(rA(ctx->opcode));
- rb = gen_avr_ptr(rB(ctx->opcode));
- rc = gen_avr_ptr(rC(ctx->opcode));
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_vmladduhm(rd, ra, rb, rc);
- tcg_temp_free_ptr(ra);
- tcg_temp_free_ptr(rb);
- tcg_temp_free_ptr(rc);
- tcg_temp_free_ptr(rd);
-}
-
-static void gen_vpermr(DisasContext *ctx)
-{
- TCGv_ptr ra, rb, rc, rd;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- ra = gen_avr_ptr(rA(ctx->opcode));
- rb = gen_avr_ptr(rB(ctx->opcode));
- rc = gen_avr_ptr(rC(ctx->opcode));
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
- tcg_temp_free_ptr(ra);
- tcg_temp_free_ptr(rb);
- tcg_temp_free_ptr(rc);
- tcg_temp_free_ptr(rd);
-}
-
-GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
-GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
-GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
-GEN_VAFORM_PAIRED(vsel, vperm, 21)
-GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
-
-GEN_VXFORM_NOA(vclzb, 1, 28)
-GEN_VXFORM_NOA(vclzh, 1, 29)
-GEN_VXFORM_TRANS(vclzw, 1, 30)
-GEN_VXFORM_TRANS(vclzd, 1, 31)
-GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
-GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
-GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
-GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
-GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
-GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
-GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
-GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
-GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
-GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
-GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
-GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
-GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
-GEN_VXFORM_NOA(vpopcntb, 1, 28)
-GEN_VXFORM_NOA(vpopcnth, 1, 29)
-GEN_VXFORM_NOA(vpopcntw, 1, 30)
-GEN_VXFORM_NOA(vpopcntd, 1, 31)
-GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM(vbpermd, 6, 23);
-GEN_VXFORM(vbpermq, 6, 21);
-GEN_VXFORM_TRANS(vgbbd, 6, 20);
-GEN_VXFORM(vpmsumb, 4, 16)
-GEN_VXFORM(vpmsumh, 4, 17)
-GEN_VXFORM(vpmsumw, 4, 18)
-GEN_VXFORM(vpmsumd, 4, 19)
-
-#define GEN_BCD(op) \
-static void gen_##op(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rb, rd; \
- TCGv_i32 ps; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- \
- ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
- \
- gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
- \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- tcg_temp_free_i32(ps); \
-}
-
-#define GEN_BCD2(op) \
-static void gen_##op(DisasContext *ctx) \
-{ \
- TCGv_ptr rd, rb; \
- TCGv_i32 ps; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- \
- ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
- \
- gen_helper_##op(cpu_crf[6], rd, rb, ps); \
- \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
- tcg_temp_free_i32(ps); \
-}
-
-GEN_BCD(bcdadd)
-GEN_BCD(bcdsub)
-GEN_BCD2(bcdcfn)
-GEN_BCD2(bcdctn)
-GEN_BCD2(bcdcfz)
-GEN_BCD2(bcdctz)
-GEN_BCD2(bcdcfsq)
-GEN_BCD2(bcdctsq)
-GEN_BCD2(bcdsetsgn)
-GEN_BCD(bcdcpsgn);
-GEN_BCD(bcds);
-GEN_BCD(bcdus);
-GEN_BCD(bcdsr);
-GEN_BCD(bcdtrunc);
-GEN_BCD(bcdutrunc);
-
-static void gen_xpnd04_1(DisasContext *ctx)
-{
- switch (opc4(ctx->opcode)) {
- case 0:
- gen_bcdctsq(ctx);
- break;
- case 2:
- gen_bcdcfsq(ctx);
- break;
- case 4:
- gen_bcdctz(ctx);
- break;
- case 5:
- gen_bcdctn(ctx);
- break;
- case 6:
- gen_bcdcfz(ctx);
- break;
- case 7:
- gen_bcdcfn(ctx);
- break;
- case 31:
- gen_bcdsetsgn(ctx);
- break;
- default:
- gen_invalid(ctx);
- break;
- }
-}
-
-static void gen_xpnd04_2(DisasContext *ctx)
-{
- switch (opc4(ctx->opcode)) {
- case 0:
- gen_bcdctsq(ctx);
- break;
- case 2:
- gen_bcdcfsq(ctx);
- break;
- case 4:
- gen_bcdctz(ctx);
- break;
- case 6:
- gen_bcdcfz(ctx);
- break;
- case 7:
- gen_bcdcfn(ctx);
- break;
- case 31:
- gen_bcdsetsgn(ctx);
- break;
- default:
- gen_invalid(ctx);
- break;
- }
-}
-
-
-GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
- xpnd04_1, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
- xpnd04_2, PPC_NONE, PPC2_ISA300)
-
-GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
- bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
- bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
- bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
- bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
- bcdcpsgn, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
- bcds, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
- bcdus, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
- bcdtrunc, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
- bcdtrunc, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
- bcdutrunc, PPC_NONE, PPC2_ISA300)
-
-
-static void gen_vsbox(DisasContext *ctx)
-{
- TCGv_ptr ra, rd;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- ra = gen_avr_ptr(rA(ctx->opcode));
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_vsbox(rd, ra);
- tcg_temp_free_ptr(ra);
- tcg_temp_free_ptr(rd);
-}
-
-GEN_VXFORM(vcipher, 4, 20)
-GEN_VXFORM(vcipherlast, 4, 20)
-GEN_VXFORM(vncipher, 4, 21)
-GEN_VXFORM(vncipherlast, 4, 21)
-
-GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
- vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
- vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
-
-#define VSHASIGMA(op) \
-static void gen_##op(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rd; \
- TCGv_i32 st_six; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- ra = gen_avr_ptr(rA(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- st_six = tcg_const_i32(rB(ctx->opcode)); \
- gen_helper_##op(rd, ra, st_six); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rd); \
- tcg_temp_free_i32(st_six); \
-}
-
-VSHASIGMA(vshasigmaw)
-VSHASIGMA(vshasigmad)
-
-GEN_VXFORM3(vpermxor, 22, 0xFF)
-GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
- vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
-
-#undef GEN_VR_LDX
-#undef GEN_VR_STX
-#undef GEN_VR_LVE
-#undef GEN_VR_STVE
-
-#undef GEN_VX_LOGICAL
-#undef GEN_VX_LOGICAL_207
-#undef GEN_VXFORM
-#undef GEN_VXFORM_207
-#undef GEN_VXFORM_DUAL
-#undef GEN_VXRFORM_DUAL
-#undef GEN_VXRFORM1
-#undef GEN_VXRFORM
-#undef GEN_VXFORM_VSPLTI
-#undef GEN_VXFORM_NOA
-#undef GEN_VXFORM_UIMM
-#undef GEN_VAFORM_PAIRED
-
-#undef GEN_BCD2
--- /dev/null
+#define GEN_VR_LDX(name, opc2, opc3) \
+GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
+#define GEN_VR_STX(name, opc2, opc3) \
+GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
+#define GEN_VR_LVE(name, opc2, opc3) \
+ GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
+#define GEN_VR_STVE(name, opc2, opc3) \
+ GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
+GEN_VR_LDX(lvx, 0x07, 0x03),
+GEN_VR_LDX(lvxl, 0x07, 0x0B),
+GEN_VR_LVE(bx, 0x07, 0x00),
+GEN_VR_LVE(hx, 0x07, 0x01),
+GEN_VR_LVE(wx, 0x07, 0x02),
+GEN_VR_STX(svx, 0x07, 0x07),
+GEN_VR_STX(svxl, 0x07, 0x0F),
+GEN_VR_STVE(bx, 0x07, 0x04),
+GEN_VR_STVE(hx, 0x07, 0x05),
+GEN_VR_STVE(wx, 0x07, 0x06),
+
+#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
+GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
+
+#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
+
+GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
+GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
+GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
+GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
+GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
+GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
+GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
+GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
+
+#define GEN_VXFORM(name, opc2, opc3) \
+GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
+
+#define GEN_VXFORM_207(name, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
+
+#define GEN_VXFORM_300(name, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
+
+#define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
+
+#define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \
+GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
+ PPC2_ISA300)
+
+#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
+GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
+
+#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
+GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
+GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
+
+GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vadduwm, 0, 2),
+GEN_VXFORM_207(vaddudm, 0, 3),
+GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
+GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_300(bcds, 0, 27),
+GEN_VXFORM(vmaxub, 1, 0),
+GEN_VXFORM(vmaxuh, 1, 1),
+GEN_VXFORM(vmaxuw, 1, 2),
+GEN_VXFORM_207(vmaxud, 1, 3),
+GEN_VXFORM(vmaxsb, 1, 4),
+GEN_VXFORM(vmaxsh, 1, 5),
+GEN_VXFORM(vmaxsw, 1, 6),
+GEN_VXFORM_207(vmaxsd, 1, 7),
+GEN_VXFORM(vminub, 1, 8),
+GEN_VXFORM(vminuh, 1, 9),
+GEN_VXFORM(vminuw, 1, 10),
+GEN_VXFORM_207(vminud, 1, 11),
+GEN_VXFORM(vminsb, 1, 12),
+GEN_VXFORM(vminsh, 1, 13),
+GEN_VXFORM(vminsw, 1, 14),
+GEN_VXFORM_207(vminsd, 1, 15),
+GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vavgsb, 1, 20),
+GEN_VXFORM(vavgsh, 1, 21),
+GEN_VXFORM(vavgsw, 1, 22),
+GEN_VXFORM(vmrghb, 6, 0),
+GEN_VXFORM(vmrghh, 6, 1),
+GEN_VXFORM(vmrghw, 6, 2),
+GEN_VXFORM(vmrglb, 6, 4),
+GEN_VXFORM(vmrglh, 6, 5),
+GEN_VXFORM(vmrglw, 6, 6),
+GEN_VXFORM_300(vextublx, 6, 24),
+GEN_VXFORM_300(vextuhlx, 6, 25),
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_300(vextubrx, 6, 28),
+GEN_VXFORM_300(vextuhrx, 6, 29),
+GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM(vmuloub, 4, 0),
+GEN_VXFORM(vmulouh, 4, 1),
+GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vmulosb, 4, 4),
+GEN_VXFORM(vmulosh, 4, 5),
+GEN_VXFORM_207(vmulosw, 4, 6),
+GEN_VXFORM(vmuleub, 4, 8),
+GEN_VXFORM(vmuleuh, 4, 9),
+GEN_VXFORM_207(vmuleuw, 4, 10),
+GEN_VXFORM(vmulesb, 4, 12),
+GEN_VXFORM(vmulesh, 4, 13),
+GEN_VXFORM_207(vmulesw, 4, 14),
+GEN_VXFORM(vslb, 2, 4),
+GEN_VXFORM(vslh, 2, 5),
+GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_207(vsld, 2, 23),
+GEN_VXFORM(vsrb, 2, 8),
+GEN_VXFORM(vsrh, 2, 9),
+GEN_VXFORM(vsrw, 2, 10),
+GEN_VXFORM_207(vsrd, 2, 27),
+GEN_VXFORM(vsrab, 2, 12),
+GEN_VXFORM(vsrah, 2, 13),
+GEN_VXFORM(vsraw, 2, 14),
+GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vsrv, 2, 28),
+GEN_VXFORM_300(vslv, 2, 29),
+GEN_VXFORM(vslo, 6, 16),
+GEN_VXFORM(vsro, 6, 17),
+GEN_VXFORM(vaddcuw, 0, 6),
+GEN_HANDLER_E_2(vprtybw, 0x4, 0x1, 0x18, 8, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
+
+GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_300(bcdsr, 0, 23),
+GEN_VXFORM_300(bcdsr, 0, 31),
+GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vadduws, 0, 10),
+GEN_VXFORM(vaddsbs, 0, 12),
+GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vaddsws, 0, 14),
+GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vsubuws, 0, 26),
+GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300),
+GEN_VXFORM(vsubshs, 0, 29),
+GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_207(vadduqm, 0, 4),
+GEN_VXFORM_207(vaddcuq, 0, 5),
+GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM(vrlb, 2, 0),
+GEN_VXFORM(vrlh, 2, 1),
+GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vsr, 2, 11),
+GEN_VXFORM(vpkuhum, 7, 0),
+GEN_VXFORM(vpkuwum, 7, 1),
+GEN_VXFORM_207(vpkudum, 7, 17),
+GEN_VXFORM(vpkuhus, 7, 2),
+GEN_VXFORM(vpkuwus, 7, 3),
+GEN_VXFORM_207(vpkudus, 7, 19),
+GEN_VXFORM(vpkshus, 7, 4),
+GEN_VXFORM(vpkswus, 7, 5),
+GEN_VXFORM_207(vpksdus, 7, 21),
+GEN_VXFORM(vpkshss, 7, 6),
+GEN_VXFORM(vpkswss, 7, 7),
+GEN_VXFORM_207(vpksdss, 7, 23),
+GEN_VXFORM(vpkpx, 7, 12),
+GEN_VXFORM(vsum4ubs, 4, 24),
+GEN_VXFORM(vsum4sbs, 4, 28),
+GEN_VXFORM(vsum4shs, 4, 25),
+GEN_VXFORM(vsum2sws, 4, 26),
+GEN_VXFORM(vsumsws, 4, 30),
+GEN_VXFORM(vaddfp, 5, 0),
+GEN_VXFORM(vsubfp, 5, 1),
+GEN_VXFORM(vmaxfp, 5, 16),
+GEN_VXFORM(vminfp, 5, 17),
+
+#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
+ GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
+#define GEN_VXRFORM1_300(opname, name, str, opc2, opc3) \
+GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
+#define GEN_VXRFORM(name, opc2, opc3) \
+ GEN_VXRFORM1(name, name, #name, opc2, opc3) \
+ GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+#define GEN_VXRFORM_300(name, opc2, opc3) \
+ GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \
+ GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+
+GEN_VXRFORM_300(vcmpnezb, 3, 4)
+GEN_VXRFORM_300(vcmpnezh, 3, 5)
+GEN_VXRFORM_300(vcmpnezw, 3, 6)
+GEN_VXRFORM(vcmpgtsb, 3, 12)
+GEN_VXRFORM(vcmpgtsh, 3, 13)
+GEN_VXRFORM(vcmpgtsw, 3, 14)
+GEN_VXRFORM(vcmpgtub, 3, 8)
+GEN_VXRFORM(vcmpgtuh, 3, 9)
+GEN_VXRFORM(vcmpgtuw, 3, 10)
+GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM(vcmpgefp, 3, 7)
+GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE)
+
+#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \
+GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \
+ PPC_NONE)
+GEN_VXFORM_DUAL_INV(vspltb, vextractub, 6, 8, 0x00000000, 0x100000,
+ PPC_ALTIVEC),
+GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000,
+ PPC_ALTIVEC),
+GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000,
+ PPC_ALTIVEC),
+GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000),
+GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000,
+ PPC_ALTIVEC),
+GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
+ PPC_ALTIVEC),
+GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
+ PPC_ALTIVEC),
+GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
+GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
+GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
+GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
+GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11),
+GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18),
+GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19),
+GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A),
+GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
+GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
+GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
+GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
+GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0),
+GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1),
+GEN_VXFORM_300(vpermr, 0x1D, 0xFF),
+
+#define GEN_VXFORM_NOA(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
+GEN_VXFORM_NOA(vupkhsb, 7, 8),
+GEN_VXFORM_NOA(vupkhsh, 7, 9),
+GEN_VXFORM_207(vupkhsw, 7, 25),
+GEN_VXFORM_NOA(vupklsb, 7, 10),
+GEN_VXFORM_NOA(vupklsh, 7, 11),
+GEN_VXFORM_207(vupklsw, 7, 27),
+GEN_VXFORM_NOA(vupkhpx, 7, 13),
+GEN_VXFORM_NOA(vupklpx, 7, 15),
+GEN_VXFORM_NOA(vrefp, 5, 4),
+GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
+GEN_VXFORM_NOA(vexptefp, 5, 6),
+GEN_VXFORM_NOA(vlogefp, 5, 7),
+GEN_VXFORM_NOA(vrfim, 5, 11),
+GEN_VXFORM_NOA(vrfin, 5, 8),
+GEN_VXFORM_NOA(vrfip, 5, 10),
+GEN_VXFORM_NOA(vrfiz, 5, 9),
+
+#define GEN_VXFORM_UIMM(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
+GEN_VXFORM_UIMM(vcfux, 5, 12),
+GEN_VXFORM_UIMM(vcfsx, 5, 13),
+GEN_VXFORM_UIMM(vctuxs, 5, 14),
+GEN_VXFORM_UIMM(vctsxs, 5, 15),
+
+
+#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
+ GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
+GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
+GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
+GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
+GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
+GEN_VAFORM_PAIRED(vsel, vperm, 21),
+GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+
+GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
+
+GEN_VXFORM_300(vbpermd, 6, 23),
+GEN_VXFORM_207(vbpermq, 6, 21),
+GEN_VXFORM_207(vgbbd, 6, 20),
+GEN_VXFORM_207(vpmsumb, 4, 16),
+GEN_VXFORM_207(vpmsumh, 4, 17),
+GEN_VXFORM_207(vpmsumw, 4, 18),
+GEN_VXFORM_207(vpmsumd, 4, 19),
+
+GEN_VXFORM_207(vsbox, 4, 23),
+
+GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
+
+GEN_VXFORM_207(vshasigmaw, 1, 26),
+GEN_VXFORM_207(vshasigmad, 1, 27),
+
+GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
+++ /dev/null
-#define GEN_VR_LDX(name, opc2, opc3) \
-GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-#define GEN_VR_STX(name, opc2, opc3) \
-GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-#define GEN_VR_LVE(name, opc2, opc3) \
- GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-#define GEN_VR_STVE(name, opc2, opc3) \
- GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
-GEN_VR_LDX(lvx, 0x07, 0x03),
-GEN_VR_LDX(lvxl, 0x07, 0x0B),
-GEN_VR_LVE(bx, 0x07, 0x00),
-GEN_VR_LVE(hx, 0x07, 0x01),
-GEN_VR_LVE(wx, 0x07, 0x02),
-GEN_VR_STX(svx, 0x07, 0x07),
-GEN_VR_STX(svxl, 0x07, 0x0F),
-GEN_VR_STVE(bx, 0x07, 0x04),
-GEN_VR_STVE(hx, 0x07, 0x05),
-GEN_VR_STVE(wx, 0x07, 0x06),
-
-#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
-GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
-
-#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
-GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
-
-GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
-GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
-GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
-GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
-GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
-GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
-GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
-GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
-
-#define GEN_VXFORM(name, opc2, opc3) \
-GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
-
-#define GEN_VXFORM_207(name, opc2, opc3) \
-GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
-
-#define GEN_VXFORM_300(name, opc2, opc3) \
-GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
-
-#define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \
-GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
-
-#define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \
-GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
- PPC2_ISA300)
-
-#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
-GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
-
-#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
-GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
-GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
-
-GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vadduwm, 0, 2),
-GEN_VXFORM_207(vaddudm, 0, 3),
-GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
-GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
-GEN_VXFORM_300(bcds, 0, 27),
-GEN_VXFORM(vmaxub, 1, 0),
-GEN_VXFORM(vmaxuh, 1, 1),
-GEN_VXFORM(vmaxuw, 1, 2),
-GEN_VXFORM_207(vmaxud, 1, 3),
-GEN_VXFORM(vmaxsb, 1, 4),
-GEN_VXFORM(vmaxsh, 1, 5),
-GEN_VXFORM(vmaxsw, 1, 6),
-GEN_VXFORM_207(vmaxsd, 1, 7),
-GEN_VXFORM(vminub, 1, 8),
-GEN_VXFORM(vminuh, 1, 9),
-GEN_VXFORM(vminuw, 1, 10),
-GEN_VXFORM_207(vminud, 1, 11),
-GEN_VXFORM(vminsb, 1, 12),
-GEN_VXFORM(vminsh, 1, 13),
-GEN_VXFORM(vminsw, 1, 14),
-GEN_VXFORM_207(vminsd, 1, 15),
-GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vavgsb, 1, 20),
-GEN_VXFORM(vavgsh, 1, 21),
-GEN_VXFORM(vavgsw, 1, 22),
-GEN_VXFORM(vmrghb, 6, 0),
-GEN_VXFORM(vmrghh, 6, 1),
-GEN_VXFORM(vmrghw, 6, 2),
-GEN_VXFORM(vmrglb, 6, 4),
-GEN_VXFORM(vmrglh, 6, 5),
-GEN_VXFORM(vmrglw, 6, 6),
-GEN_VXFORM_300(vextublx, 6, 24),
-GEN_VXFORM_300(vextuhlx, 6, 25),
-GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_300(vextubrx, 6, 28),
-GEN_VXFORM_300(vextuhrx, 6, 29),
-GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM(vmuloub, 4, 0),
-GEN_VXFORM(vmulouh, 4, 1),
-GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vmulosb, 4, 4),
-GEN_VXFORM(vmulosh, 4, 5),
-GEN_VXFORM_207(vmulosw, 4, 6),
-GEN_VXFORM(vmuleub, 4, 8),
-GEN_VXFORM(vmuleuh, 4, 9),
-GEN_VXFORM_207(vmuleuw, 4, 10),
-GEN_VXFORM(vmulesb, 4, 12),
-GEN_VXFORM(vmulesh, 4, 13),
-GEN_VXFORM_207(vmulesw, 4, 14),
-GEN_VXFORM(vslb, 2, 4),
-GEN_VXFORM(vslh, 2, 5),
-GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_207(vsld, 2, 23),
-GEN_VXFORM(vsrb, 2, 8),
-GEN_VXFORM(vsrh, 2, 9),
-GEN_VXFORM(vsrw, 2, 10),
-GEN_VXFORM_207(vsrd, 2, 27),
-GEN_VXFORM(vsrab, 2, 12),
-GEN_VXFORM(vsrah, 2, 13),
-GEN_VXFORM(vsraw, 2, 14),
-GEN_VXFORM_207(vsrad, 2, 15),
-GEN_VXFORM_300(vsrv, 2, 28),
-GEN_VXFORM_300(vslv, 2, 29),
-GEN_VXFORM(vslo, 6, 16),
-GEN_VXFORM(vsro, 6, 17),
-GEN_VXFORM(vaddcuw, 0, 6),
-GEN_HANDLER_E_2(vprtybw, 0x4, 0x1, 0x18, 8, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
-
-GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_300(bcdsr, 0, 23),
-GEN_VXFORM_300(bcdsr, 0, 31),
-GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vadduws, 0, 10),
-GEN_VXFORM(vaddsbs, 0, 12),
-GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vaddsws, 0, 14),
-GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vsubuws, 0, 26),
-GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300),
-GEN_VXFORM(vsubshs, 0, 29),
-GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_207(vadduqm, 0, 4),
-GEN_VXFORM_207(vaddcuq, 0, 5),
-GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
-GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
-GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM(vrlb, 2, 0),
-GEN_VXFORM(vrlh, 2, 1),
-GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vsr, 2, 11),
-GEN_VXFORM(vpkuhum, 7, 0),
-GEN_VXFORM(vpkuwum, 7, 1),
-GEN_VXFORM_207(vpkudum, 7, 17),
-GEN_VXFORM(vpkuhus, 7, 2),
-GEN_VXFORM(vpkuwus, 7, 3),
-GEN_VXFORM_207(vpkudus, 7, 19),
-GEN_VXFORM(vpkshus, 7, 4),
-GEN_VXFORM(vpkswus, 7, 5),
-GEN_VXFORM_207(vpksdus, 7, 21),
-GEN_VXFORM(vpkshss, 7, 6),
-GEN_VXFORM(vpkswss, 7, 7),
-GEN_VXFORM_207(vpksdss, 7, 23),
-GEN_VXFORM(vpkpx, 7, 12),
-GEN_VXFORM(vsum4ubs, 4, 24),
-GEN_VXFORM(vsum4sbs, 4, 28),
-GEN_VXFORM(vsum4shs, 4, 25),
-GEN_VXFORM(vsum2sws, 4, 26),
-GEN_VXFORM(vsumsws, 4, 30),
-GEN_VXFORM(vaddfp, 5, 0),
-GEN_VXFORM(vsubfp, 5, 1),
-GEN_VXFORM(vmaxfp, 5, 16),
-GEN_VXFORM(vminfp, 5, 17),
-
-#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
- GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
-#define GEN_VXRFORM1_300(opname, name, str, opc2, opc3) \
-GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
-#define GEN_VXRFORM(name, opc2, opc3) \
- GEN_VXRFORM1(name, name, #name, opc2, opc3) \
- GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
-#define GEN_VXRFORM_300(name, opc2, opc3) \
- GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \
- GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
-
-GEN_VXRFORM_300(vcmpnezb, 3, 4)
-GEN_VXRFORM_300(vcmpnezh, 3, 5)
-GEN_VXRFORM_300(vcmpnezw, 3, 6)
-GEN_VXRFORM(vcmpgtsb, 3, 12)
-GEN_VXRFORM(vcmpgtsh, 3, 13)
-GEN_VXRFORM(vcmpgtsw, 3, 14)
-GEN_VXRFORM(vcmpgtub, 3, 8)
-GEN_VXRFORM(vcmpgtuh, 3, 9)
-GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM(vcmpgefp, 3, 7)
-GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE)
-
-#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \
-GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \
- PPC_NONE)
-GEN_VXFORM_DUAL_INV(vspltb, vextractub, 6, 8, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000),
-GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
-GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
-GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
-GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
-GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11),
-GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18),
-GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19),
-GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A),
-GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
-GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
-GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
-GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
-GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0),
-GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1),
-GEN_VXFORM_300(vpermr, 0x1D, 0xFF),
-
-#define GEN_VXFORM_NOA(name, opc2, opc3) \
- GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
-GEN_VXFORM_NOA(vupkhsb, 7, 8),
-GEN_VXFORM_NOA(vupkhsh, 7, 9),
-GEN_VXFORM_207(vupkhsw, 7, 25),
-GEN_VXFORM_NOA(vupklsb, 7, 10),
-GEN_VXFORM_NOA(vupklsh, 7, 11),
-GEN_VXFORM_207(vupklsw, 7, 27),
-GEN_VXFORM_NOA(vupkhpx, 7, 13),
-GEN_VXFORM_NOA(vupklpx, 7, 15),
-GEN_VXFORM_NOA(vrefp, 5, 4),
-GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
-GEN_VXFORM_NOA(vexptefp, 5, 6),
-GEN_VXFORM_NOA(vlogefp, 5, 7),
-GEN_VXFORM_NOA(vrfim, 5, 11),
-GEN_VXFORM_NOA(vrfin, 5, 8),
-GEN_VXFORM_NOA(vrfip, 5, 10),
-GEN_VXFORM_NOA(vrfiz, 5, 9),
-
-#define GEN_VXFORM_UIMM(name, opc2, opc3) \
- GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
-GEN_VXFORM_UIMM(vcfux, 5, 12),
-GEN_VXFORM_UIMM(vcfsx, 5, 13),
-GEN_VXFORM_UIMM(vctuxs, 5, 14),
-GEN_VXFORM_UIMM(vctsxs, 5, 15),
-
-
-#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
- GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
-GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
-GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
-GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
-GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
-GEN_VAFORM_PAIRED(vsel, vperm, 21),
-GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
-
-GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
-
-GEN_VXFORM_300(vbpermd, 6, 23),
-GEN_VXFORM_207(vbpermq, 6, 21),
-GEN_VXFORM_207(vgbbd, 6, 20),
-GEN_VXFORM_207(vpmsumb, 4, 16),
-GEN_VXFORM_207(vpmsumh, 4, 17),
-GEN_VXFORM_207(vpmsumw, 4, 18),
-GEN_VXFORM_207(vpmsumd, 4, 19),
-
-GEN_VXFORM_207(vsbox, 4, 23),
-
-GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
-
-GEN_VXFORM_207(vshasigmaw, 1, 26),
-GEN_VXFORM_207(vshasigmad, 1, 27),
-
-GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
--- /dev/null
+/*** VSX extension ***/
+
+static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
+{
+ tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true));
+}
+
+static inline void get_cpu_vsrl(TCGv_i64 dst, int n)
+{
+ tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false));
+}
+
+static inline void set_cpu_vsrh(int n, TCGv_i64 src)
+{
+ tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true));
+}
+
+static inline void set_cpu_vsrl(int n, TCGv_i64 src)
+{
+ tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false));
+}
+
+static inline TCGv_ptr gen_vsr_ptr(int reg)
+{
+ TCGv_ptr r = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg));
+ return r;
+}
+
+#define VSX_LOAD_SCALAR(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ gen_qemu_##operation(ctx, t0, EA); \
+ set_cpu_vsrh(xT(ctx->opcode), t0); \
+ /* NOTE: cpu_vsrl is undefined */ \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+VSX_LOAD_SCALAR(lxsdx, ld64_i64)
+VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
+VSX_LOAD_SCALAR(lxsibzx, ld8u_i64)
+VSX_LOAD_SCALAR(lxsihzx, ld16u_i64)
+VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
+VSX_LOAD_SCALAR(lxsspx, ld32fs)
+
+static void gen_lxvd2x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_cpu_vsrh(xT(ctx->opcode), t0);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_cpu_vsrl(xT(ctx->opcode), t0);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_lxvdsx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ TCGv_i64 t1;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld64_i64(ctx, t0, EA);
+ set_cpu_vsrh(xT(ctx->opcode), t0);
+ tcg_gen_mov_i64(t1, t0);
+ set_cpu_vsrl(xT(ctx->opcode), t1);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static void gen_lxvw4x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+
+ gen_addr_reg_index(ctx, EA);
+ if (ctx->le_mode) {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ);
+ tcg_gen_shri_i64(t1, t0, 32);
+ tcg_gen_deposit_i64(xth, t1, t0, 32, 32);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ);
+ tcg_gen_shri_i64(t1, t0, 32);
+ tcg_gen_deposit_i64(xtl, t1, t0, 32, 32);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ } else {
+ tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
+ }
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+}
+
+static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
+ TCGv_i64 inh, TCGv_i64 inl)
+{
+ TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ /* outh = ((inh & mask) << 8) | ((inh >> 8) & mask) */
+ tcg_gen_and_i64(t0, inh, mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_shri_i64(t1, inh, 8);
+ tcg_gen_and_i64(t1, t1, mask);
+ tcg_gen_or_i64(outh, t0, t1);
+
+ /* outl = ((inl & mask) << 8) | ((inl >> 8) & mask) */
+ tcg_gen_and_i64(t0, inl, mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_shri_i64(t1, inl, 8);
+ tcg_gen_and_i64(t1, t1, mask);
+ tcg_gen_or_i64(outl, t0, t1);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(mask);
+}
+
+static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl,
+ TCGv_i64 inh, TCGv_i64 inl)
+{
+ TCGv_i64 hi = tcg_temp_new_i64();
+ TCGv_i64 lo = tcg_temp_new_i64();
+
+ tcg_gen_bswap64_i64(hi, inh);
+ tcg_gen_bswap64_i64(lo, inl);
+ tcg_gen_shri_i64(outh, hi, 32);
+ tcg_gen_deposit_i64(outh, outh, hi, 32, 32);
+ tcg_gen_shri_i64(outl, lo, 32);
+ tcg_gen_deposit_i64(outl, outl, lo, 32, 32);
+
+ tcg_temp_free_i64(hi);
+ tcg_temp_free_i64(lo);
+}
+static void gen_lxvh8x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ gen_set_access_type(ctx, ACCESS_INT);
+
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
+ if (ctx->le_mode) {
+ gen_bswap16x8(xth, xtl, xth, xtl);
+ }
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+}
+
+static void gen_lxvb16x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+}
+
+#define VSX_VECTOR_LOAD(name, op, indexed) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int xt; \
+ TCGv EA; \
+ TCGv_i64 xth; \
+ TCGv_i64 xtl; \
+ \
+ if (indexed) { \
+ xt = xT(ctx->opcode); \
+ } else { \
+ xt = DQxT(ctx->opcode); \
+ } \
+ \
+ if (xt < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ xth = tcg_temp_new_i64(); \
+ xtl = tcg_temp_new_i64(); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ if (indexed) { \
+ gen_addr_reg_index(ctx, EA); \
+ } else { \
+ gen_addr_imm_index(ctx, EA, 0x0F); \
+ } \
+ if (ctx->le_mode) { \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
+ set_cpu_vsrl(xt, xtl); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
+ set_cpu_vsrh(xt, xth); \
+ } else { \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
+ set_cpu_vsrh(xt, xth); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
+ set_cpu_vsrl(xt, xtl); \
+ } \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(xth); \
+ tcg_temp_free_i64(xtl); \
+}
+
+VSX_VECTOR_LOAD(lxv, ld_i64, 0)
+VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
+
+#define VSX_VECTOR_STORE(name, op, indexed) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int xt; \
+ TCGv EA; \
+ TCGv_i64 xth; \
+ TCGv_i64 xtl; \
+ \
+ if (indexed) { \
+ xt = xT(ctx->opcode); \
+ } else { \
+ xt = DQxT(ctx->opcode); \
+ } \
+ \
+ if (xt < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ xth = tcg_temp_new_i64(); \
+ xtl = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xth, xt); \
+ get_cpu_vsrl(xtl, xt); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ if (indexed) { \
+ gen_addr_reg_index(ctx, EA); \
+ } else { \
+ gen_addr_imm_index(ctx, EA, 0x0F); \
+ } \
+ if (ctx->le_mode) { \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
+ } else { \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
+ } \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(xth); \
+ tcg_temp_free_i64(xtl); \
+}
+
+VSX_VECTOR_STORE(stxv, st_i64, 0)
+VSX_VECTOR_STORE(stxvx, st_i64, 1)
+
+#ifdef TARGET_PPC64
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_ptr xt; \
+ \
+ if (xT(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ EA = tcg_temp_new(); \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ gen_addr_register(ctx, EA); \
+ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(xt); \
+}
+
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
+#endif
+
+#define VSX_LOAD_SCALAR_DS(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 xth; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ xth = tcg_temp_new_i64(); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_imm_index(ctx, EA, 0x03); \
+ gen_qemu_##operation(ctx, xth, EA); \
+ set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \
+ /* NOTE: cpu_vsrl is undefined */ \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(xth); \
+}
+
+VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
+VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
+
+#define VSX_STORE_SCALAR(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ get_cpu_vsrh(t0, xS(ctx->opcode)); \
+ gen_qemu_##operation(ctx, t0, EA); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
+VSX_STORE_SCALAR(stxsdx, st64_i64)
+
+VSX_STORE_SCALAR(stxsibx, st8_i64)
+VSX_STORE_SCALAR(stxsihx, st16_i64)
+VSX_STORE_SCALAR(stxsiwx, st32_i64)
+VSX_STORE_SCALAR(stxsspx, st32fs)
+
+static void gen_stxvd2x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 t0;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ get_cpu_vsrh(t0, xS(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ get_cpu_vsrl(t0, xS(ctx->opcode));
+ gen_qemu_st64_i64(ctx, t0, EA);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_stxvw4x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 xsh;
+ TCGv_i64 xsl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xsh = tcg_temp_new_i64();
+ xsl = tcg_temp_new_i64();
+ get_cpu_vsrh(xsh, xS(ctx->opcode));
+ get_cpu_vsrl(xsl, xS(ctx->opcode));
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ if (ctx->le_mode) {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t0, xsh, 32);
+ tcg_gen_deposit_i64(t1, t0, xsh, 32, 32);
+ tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_shri_i64(t0, xsl, 32);
+ tcg_gen_deposit_i64(t1, t0, xsl, 32, 32);
+ tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ } else {
+ tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
+ }
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(xsh);
+ tcg_temp_free_i64(xsl);
+}
+
+static void gen_stxvh8x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 xsh;
+ TCGv_i64 xsl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xsh = tcg_temp_new_i64();
+ xsl = tcg_temp_new_i64();
+ get_cpu_vsrh(xsh, xS(ctx->opcode));
+ get_cpu_vsrl(xsl, xS(ctx->opcode));
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ if (ctx->le_mode) {
+ TCGv_i64 outh = tcg_temp_new_i64();
+ TCGv_i64 outl = tcg_temp_new_i64();
+
+ gen_bswap16x8(outh, outl, xsh, xsl);
+ tcg_gen_qemu_st_i64(outh, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_st_i64(outl, EA, ctx->mem_idx, MO_BEQ);
+ tcg_temp_free_i64(outh);
+ tcg_temp_free_i64(outl);
+ } else {
+ tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
+ }
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(xsh);
+ tcg_temp_free_i64(xsl);
+}
+
+static void gen_stxvb16x(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 xsh;
+ TCGv_i64 xsl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xsh = tcg_temp_new_i64();
+ xsl = tcg_temp_new_i64();
+ get_cpu_vsrh(xsh, xS(ctx->opcode));
+ get_cpu_vsrl(xsl, xS(ctx->opcode));
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(xsh);
+ tcg_temp_free_i64(xsl);
+}
+
+#define VSX_STORE_SCALAR_DS(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 xth; \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ xth = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_imm_index(ctx, EA, 0x03); \
+ gen_qemu_##operation(ctx, xth, EA); \
+ /* NOTE: cpu_vsrl is undefined */ \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(xth); \
+}
+
+VSX_STORE_SCALAR_DS(stxsd, st64_i64)
+VSX_STORE_SCALAR_DS(stxssp, st32fs)
+
+static void gen_mfvsrwz(DisasContext *ctx)
+{
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv_i64 xsh = tcg_temp_new_i64();
+ get_cpu_vsrh(xsh, xS(ctx->opcode));
+ tcg_gen_ext32u_i64(tmp, xsh);
+ tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp);
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(xsh);
+}
+
+static void gen_mtvsrwa(DisasContext *ctx)
+{
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv_i64 xsh = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_ext32s_i64(xsh, tmp);
+ set_cpu_vsrh(xT(ctx->opcode), xsh);
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(xsh);
+}
+
+static void gen_mtvsrwz(DisasContext *ctx)
+{
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv_i64 xsh = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_ext32u_i64(xsh, tmp);
+ set_cpu_vsrh(xT(ctx->opcode), xsh);
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(xsh);
+}
+
+#if defined(TARGET_PPC64)
+static void gen_mfvsrd(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ t0 = tcg_temp_new_i64();
+ get_cpu_vsrh(t0, xS(ctx->opcode));
+ tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_mtvsrd(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
+ set_cpu_vsrh(xT(ctx->opcode), t0);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_mfvsrld(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (xS(ctx->opcode) < 32) {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ t0 = tcg_temp_new_i64();
+ get_cpu_vsrl(t0, xS(ctx->opcode));
+ tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_mtvsrdd(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (xT(ctx->opcode) < 32) {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+
+ t0 = tcg_temp_new_i64();
+ if (!rA(ctx->opcode)) {
+ tcg_gen_movi_i64(t0, 0);
+ } else {
+ tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
+ }
+ set_cpu_vsrh(xT(ctx->opcode), t0);
+
+ tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]);
+ set_cpu_vsrl(xT(ctx->opcode), t0);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_mtvsrws(DisasContext *ctx)
+{
+ TCGv_i64 t0;
+ if (xT(ctx->opcode) < 32) {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+
+ t0 = tcg_temp_new_i64();
+ tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)],
+ cpu_gpr[rA(ctx->opcode)], 32, 32);
+ set_cpu_vsrl(xT(ctx->opcode), t0);
+ set_cpu_vsrh(xT(ctx->opcode), t0);
+ tcg_temp_free_i64(t0);
+}
+
+#endif
+
+static void gen_xxpermdi(DisasContext *ctx)
+{
+ TCGv_i64 xh, xl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ xh = tcg_temp_new_i64();
+ xl = tcg_temp_new_i64();
+
+ if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
+ (xT(ctx->opcode) == xB(ctx->opcode)))) {
+ if ((DM(ctx->opcode) & 2) == 0) {
+ get_cpu_vsrh(xh, xA(ctx->opcode));
+ } else {
+ get_cpu_vsrl(xh, xA(ctx->opcode));
+ }
+ if ((DM(ctx->opcode) & 1) == 0) {
+ get_cpu_vsrh(xl, xB(ctx->opcode));
+ } else {
+ get_cpu_vsrl(xl, xB(ctx->opcode));
+ }
+
+ set_cpu_vsrh(xT(ctx->opcode), xh);
+ set_cpu_vsrl(xT(ctx->opcode), xl);
+ } else {
+ if ((DM(ctx->opcode) & 2) == 0) {
+ get_cpu_vsrh(xh, xA(ctx->opcode));
+ set_cpu_vsrh(xT(ctx->opcode), xh);
+ } else {
+ get_cpu_vsrl(xh, xA(ctx->opcode));
+ set_cpu_vsrh(xT(ctx->opcode), xh);
+ }
+ if ((DM(ctx->opcode) & 1) == 0) {
+ get_cpu_vsrh(xl, xB(ctx->opcode));
+ set_cpu_vsrl(xT(ctx->opcode), xl);
+ } else {
+ get_cpu_vsrl(xl, xB(ctx->opcode));
+ set_cpu_vsrl(xT(ctx->opcode), xl);
+ }
+ }
+ tcg_temp_free_i64(xh);
+ tcg_temp_free_i64(xl);
+}
+
+#define OP_ABS 1
+#define OP_NABS 2
+#define OP_NEG 3
+#define OP_CPSGN 4
+#define SGN_MASK_DP 0x8000000000000000ull
+#define SGN_MASK_SP 0x8000000080000000ull
+
+#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_i64 xb, sgm; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xb = tcg_temp_new_i64(); \
+ sgm = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xb, xB(ctx->opcode)); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andc_i64(xb, xb, sgm); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_or_i64(xb, xb, sgm); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xor_i64(xb, xb, sgm); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xa = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xa, xA(ctx->opcode)); \
+ tcg_gen_and_i64(xa, xa, sgm); \
+ tcg_gen_andc_i64(xb, xb, sgm); \
+ tcg_gen_or_i64(xb, xb, xa); \
+ tcg_temp_free_i64(xa); \
+ break; \
+ } \
+ } \
+ set_cpu_vsrh(xT(ctx->opcode), xb); \
+ tcg_temp_free_i64(xb); \
+ tcg_temp_free_i64(sgm); \
+ }
+
+VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+
+#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ int xa; \
+ int xt = rD(ctx->opcode) + 32; \
+ int xb = rB(ctx->opcode) + 32; \
+ TCGv_i64 xah, xbh, xbl, sgm, tmp; \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new_i64(); \
+ xbl = tcg_temp_new_i64(); \
+ sgm = tcg_temp_new_i64(); \
+ tmp = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xbh, xb); \
+ get_cpu_vsrl(xbl, xb); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ break; \
+ case OP_NABS: \
+ tcg_gen_or_i64(xbh, xbh, sgm); \
+ break; \
+ case OP_NEG: \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ break; \
+ case OP_CPSGN: \
+ xah = tcg_temp_new_i64(); \
+ xa = rA(ctx->opcode) + 32; \
+ get_cpu_vsrh(tmp, xa); \
+ tcg_gen_and_i64(xah, tmp, sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_temp_free_i64(xah); \
+ break; \
+ } \
+ set_cpu_vsrh(xt, xbh); \
+ set_cpu_vsrl(xt, xbl); \
+ tcg_temp_free_i64(xbl); \
+ tcg_temp_free_i64(xbh); \
+ tcg_temp_free_i64(sgm); \
+ tcg_temp_free_i64(tmp); \
+}
+
+VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
+
+#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_i64 xbh, xbl, sgm; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new_i64(); \
+ xbl = tcg_temp_new_i64(); \
+ sgm = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xbh, xB(ctx->opcode)); \
+ get_cpu_vsrl(xbl, xB(ctx->opcode)); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_andc_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_or_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ tcg_gen_xor_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xah = tcg_temp_new_i64(); \
+ TCGv_i64 xal = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xah, xA(ctx->opcode)); \
+ get_cpu_vsrl(xal, xA(ctx->opcode)); \
+ tcg_gen_and_i64(xah, xah, sgm); \
+ tcg_gen_and_i64(xal, xal, sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_andc_i64(xbl, xbl, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_gen_or_i64(xbl, xbl, xal); \
+ tcg_temp_free_i64(xah); \
+ tcg_temp_free_i64(xal); \
+ break; \
+ } \
+ } \
+ set_cpu_vsrh(xT(ctx->opcode), xbh); \
+ set_cpu_vsrl(xT(ctx->opcode), xbl); \
+ tcg_temp_free_i64(xbh); \
+ tcg_temp_free_i64(xbl); \
+ tcg_temp_free_i64(sgm); \
+ }
+
+VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+
+#define VSX_CMP(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 ignored; \
+ TCGv_ptr xt, xa, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ xa = gen_vsr_ptr(xA(ctx->opcode)); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
+ if ((ctx->opcode >> (31 - 21)) & 1) { \
+ gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \
+ } else { \
+ ignored = tcg_temp_new_i32(); \
+ gen_helper_##name(ignored, cpu_env, xt, xa, xb); \
+ tcg_temp_free_i32(ignored); \
+ } \
+ gen_helper_float_check_status(cpu_env); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(xa); \
+ tcg_temp_free_ptr(xb); \
+}
+
+VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
+VSX_CMP(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
+VSX_CMP(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
+VSX_CMP(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300)
+VSX_CMP(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
+VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
+VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
+VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
+
+static void gen_xscvqpdp(DisasContext *ctx)
+{
+ TCGv_i32 opc;
+ TCGv_ptr xt, xb;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ opc = tcg_const_i32(ctx->opcode);
+ xt = gen_vsr_ptr(xT(ctx->opcode));
+ xb = gen_vsr_ptr(xB(ctx->opcode));
+ gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
+ tcg_temp_free_i32(opc);
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xb);
+}
+
+#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 opc; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ opc = tcg_const_i32(ctx->opcode); \
+ gen_helper_##name(cpu_env, opc); \
+ tcg_temp_free_i32(opc); \
+}
+
+#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr xt, xa, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ xa = gen_vsr_ptr(xA(ctx->opcode)); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
+ gen_helper_##name(cpu_env, xt, xa, xb); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(xa); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr xt, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
+ gen_helper_##name(cpu_env, xt, xb); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 opc; \
+ TCGv_ptr xa, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ opc = tcg_const_i32(ctx->opcode); \
+ xa = gen_vsr_ptr(xA(ctx->opcode)); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
+ gen_helper_##name(cpu_env, opc, xa, xb); \
+ tcg_temp_free_i32(opc); \
+ tcg_temp_free_ptr(xa); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 opc; \
+ TCGv_ptr xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ opc = tcg_const_i32(ctx->opcode); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
+ gen_helper_##name(cpu_env, opc, xb); \
+ tcg_temp_free_i32(opc); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 opc; \
+ TCGv_ptr xt, xa, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ opc = tcg_const_i32(ctx->opcode); \
+ xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
+ xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
+ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
+ gen_helper_##name(cpu_env, opc, xt, xa, xb); \
+ tcg_temp_free_i32(opc); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(xa); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 opc; \
+ TCGv_ptr xt, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ opc = tcg_const_i32(ctx->opcode); \
+ xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
+ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
+ gen_helper_##name(cpu_env, opc, xt, xb); \
+ tcg_temp_free_i32(opc); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 opc; \
+ TCGv_ptr xa, xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ opc = tcg_const_i32(ctx->opcode); \
+ xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
+ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
+ gen_helper_##name(cpu_env, opc, xa, xb); \
+ tcg_temp_free_i32(opc); \
+ tcg_temp_free_ptr(xa); \
+ tcg_temp_free_ptr(xb); \
+}
+
+#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i64 t0; \
+ TCGv_i64 t1; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ t0 = tcg_temp_new_i64(); \
+ t1 = tcg_temp_new_i64(); \
+ get_cpu_vsrh(t0, xB(ctx->opcode)); \
+ gen_helper_##name(t1, cpu_env, t0); \
+ set_cpu_vsrh(xT(ctx->opcode), t1); \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+}
+
+GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_R3(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
+GEN_VSX_HELPER_R3(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_R3(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
+GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
+GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
+GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
+GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
+GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
+GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
+GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
+GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
+GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
+GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
+GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
+GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
+GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
+GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
+GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300)
+
+GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
+
+GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300)
+GEN_VSX_HELPER_X2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
+GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
+GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
+
+#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr xt, xa, b, c; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ xa = gen_vsr_ptr(xA(ctx->opcode)); \
+ if (ctx->opcode & PPC_BIT32(25)) { \
+ /* \
+ * AxT + B \
+ */ \
+ b = gen_vsr_ptr(xT(ctx->opcode)); \
+ c = gen_vsr_ptr(xB(ctx->opcode)); \
+ } else { \
+ /* \
+ * AxB + T \
+ */ \
+ b = gen_vsr_ptr(xB(ctx->opcode)); \
+ c = gen_vsr_ptr(xT(ctx->opcode)); \
+ } \
+ gen_helper_##name(cpu_env, xt, xa, b, c); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(xa); \
+ tcg_temp_free_ptr(b); \
+ tcg_temp_free_ptr(c); \
+}
+
+GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207)
+GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207)
+GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207)
+GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvnmsubdp, 0x04, 0x1E, 0x1F, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvmaddsp, 0x04, 0x08, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvmsubsp, 0x04, 0x0A, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvnmaddsp, 0x04, 0x18, 0x19, 0, PPC2_VSX)
+GEN_VSX_HELPER_VSX_MADD(xvnmsubsp, 0x04, 0x1A, 0x1B, 0, PPC2_VSX)
+
+static void gen_xxbrd(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+
+ tcg_gen_bswap64_i64(xth, xbh);
+ tcg_gen_bswap64_i64(xtl, xbl);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+static void gen_xxbrh(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+
+ gen_bswap16x8(xth, xtl, xbh, xbl);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+static void gen_xxbrq(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+ t0 = tcg_temp_new_i64();
+
+ tcg_gen_bswap64_i64(t0, xbl);
+ tcg_gen_bswap64_i64(xtl, xbh);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+ tcg_gen_mov_i64(xth, t0);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+static void gen_xxbrw(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+
+ gen_bswap32x4(xth, xtl, xbh, xbl);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+#define VSX_LOGICAL(name, vece, tcg_op) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \
+ vsr_full_offset(xA(ctx->opcode)), \
+ vsr_full_offset(xB(ctx->opcode)), 16, 16); \
+ }
+
+VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)
+VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)
+VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)
+VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)
+VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)
+VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)
+VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)
+VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)
+
+#define VSX_XXMRG(name, high) \
+static void glue(gen_, name)(DisasContext *ctx) \
+ { \
+ TCGv_i64 a0, a1, b0, b1, tmp; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ a0 = tcg_temp_new_i64(); \
+ a1 = tcg_temp_new_i64(); \
+ b0 = tcg_temp_new_i64(); \
+ b1 = tcg_temp_new_i64(); \
+ tmp = tcg_temp_new_i64(); \
+ if (high) { \
+ get_cpu_vsrh(a0, xA(ctx->opcode)); \
+ get_cpu_vsrh(a1, xA(ctx->opcode)); \
+ get_cpu_vsrh(b0, xB(ctx->opcode)); \
+ get_cpu_vsrh(b1, xB(ctx->opcode)); \
+ } else { \
+ get_cpu_vsrl(a0, xA(ctx->opcode)); \
+ get_cpu_vsrl(a1, xA(ctx->opcode)); \
+ get_cpu_vsrl(b0, xB(ctx->opcode)); \
+ get_cpu_vsrl(b1, xB(ctx->opcode)); \
+ } \
+ tcg_gen_shri_i64(a0, a0, 32); \
+ tcg_gen_shri_i64(b0, b0, 32); \
+ tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \
+ set_cpu_vsrh(xT(ctx->opcode), tmp); \
+ tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \
+ set_cpu_vsrl(xT(ctx->opcode), tmp); \
+ tcg_temp_free_i64(a0); \
+ tcg_temp_free_i64(a1); \
+ tcg_temp_free_i64(b0); \
+ tcg_temp_free_i64(b1); \
+ tcg_temp_free_i64(tmp); \
+ }
+
+VSX_XXMRG(xxmrghw, 1)
+VSX_XXMRG(xxmrglw, 0)
+
+static void gen_xxsel(DisasContext *ctx)
+{
+ int rt = xT(ctx->opcode);
+ int ra = xA(ctx->opcode);
+ int rb = xB(ctx->opcode);
+ int rc = xC(ctx->opcode);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc),
+ vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
+}
+
+static void gen_xxspltw(DisasContext *ctx)
+{
+ int rt = xT(ctx->opcode);
+ int rb = xB(ctx->opcode);
+ int uim = UIM(ctx->opcode);
+ int tofs, bofs;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ tofs = vsr_full_offset(rt);
+ bofs = vsr_full_offset(rb);
+ bofs += uim << MO_32;
+#ifndef HOST_WORDS_BIG_ENDIAN
+ bofs ^= 8 | 4;
+#endif
+
+ tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
+}
+
+#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
+
+static void gen_xxspltib(DisasContext *ctx)
+{
+ uint8_t uim8 = IMM8(ctx->opcode);
+ int rt = xT(ctx->opcode);
+
+ if (rt < 32) {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+ tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
+}
+
+static void gen_xxsldwi(DisasContext *ctx)
+{
+ TCGv_i64 xth, xtl;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+
+ switch (SHW(ctx->opcode)) {
+ case 0: {
+ get_cpu_vsrh(xth, xA(ctx->opcode));
+ get_cpu_vsrl(xtl, xA(ctx->opcode));
+ break;
+ }
+ case 1: {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ get_cpu_vsrh(xth, xA(ctx->opcode));
+ tcg_gen_shli_i64(xth, xth, 32);
+ get_cpu_vsrl(t0, xA(ctx->opcode));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xth, xth, t0);
+ get_cpu_vsrl(xtl, xA(ctx->opcode));
+ tcg_gen_shli_i64(xtl, xtl, 32);
+ get_cpu_vsrh(t0, xB(ctx->opcode));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free_i64(t0);
+ break;
+ }
+ case 2: {
+ get_cpu_vsrl(xth, xA(ctx->opcode));
+ get_cpu_vsrh(xtl, xB(ctx->opcode));
+ break;
+ }
+ case 3: {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ get_cpu_vsrl(xth, xA(ctx->opcode));
+ tcg_gen_shli_i64(xth, xth, 32);
+ get_cpu_vsrh(t0, xB(ctx->opcode));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xth, xth, t0);
+ get_cpu_vsrh(xtl, xB(ctx->opcode));
+ tcg_gen_shli_i64(xtl, xtl, 32);
+ get_cpu_vsrl(t0, xB(ctx->opcode));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free_i64(t0);
+ break;
+ }
+ }
+
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+}
+
+#define VSX_EXTRACT_INSERT(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_ptr xt, xb; \
+ TCGv_i32 t0; \
+ TCGv_i64 t1; \
+ uint8_t uimm = UIMM4(ctx->opcode); \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ xb = gen_vsr_ptr(xB(ctx->opcode)); \
+ t0 = tcg_temp_new_i32(); \
+ t1 = tcg_temp_new_i64(); \
+ /* \
+ * uimm > 15 out of bound and for \
+ * uimm > 12 handle as per hardware in helper \
+ */ \
+ if (uimm > 15) { \
+ tcg_gen_movi_i64(t1, 0); \
+ set_cpu_vsrh(xT(ctx->opcode), t1); \
+ set_cpu_vsrl(xT(ctx->opcode), t1); \
+ return; \
+ } \
+ tcg_gen_movi_i32(t0, uimm); \
+ gen_helper_##name(cpu_env, xt, xb, t0); \
+ tcg_temp_free_ptr(xb); \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_i64(t1); \
+}
+
+VSX_EXTRACT_INSERT(xxextractuw)
+VSX_EXTRACT_INSERT(xxinsertw)
+
+#ifdef TARGET_PPC64
+static void gen_xsxexpdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ TCGv_i64 t0;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ get_cpu_vsrh(t0, xB(ctx->opcode));
+ tcg_gen_extract_i64(rt, t0, 52, 11);
+ tcg_temp_free_i64(t0);
+}
+
+static void gen_xsxexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+
+ tcg_gen_extract_i64(xth, xbh, 48, 15);
+ set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ tcg_gen_movi_i64(xtl, 0);
+ set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+}
+
+static void gen_xsiexpdp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv rb = cpu_gpr[rB(ctx->opcode)];
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ xth = tcg_temp_new_i64();
+ tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, rb, 0x7FF);
+ tcg_gen_shli_i64(t0, t0, 52);
+ tcg_gen_or_i64(xth, xth, t0);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ /* dword[1] is undefined */
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(xth);
+}
+
+static void gen_xsiexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xah;
+ TCGv_i64 xal;
+ TCGv_i64 xbh;
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xah = tcg_temp_new_i64();
+ xal = tcg_temp_new_i64();
+ get_cpu_vsrh(xah, rA(ctx->opcode) + 32);
+ get_cpu_vsrl(xal, rA(ctx->opcode) + 32);
+ xbh = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+ t0 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, xbh, 0x7FFF);
+ tcg_gen_shli_i64(t0, t0, 48);
+ tcg_gen_or_i64(xth, xth, t0);
+ set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ tcg_gen_mov_i64(xtl, xal);
+ set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xah);
+ tcg_temp_free_i64(xal);
+ tcg_temp_free_i64(xbh);
+}
+
+static void gen_xsxsigdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ TCGv_i64 t0, t1, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ get_cpu_vsrh(t1, xB(ctx->opcode));
+ tcg_gen_extract_i64(exp, t1, 52, 11);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ get_cpu_vsrh(t1, xB(ctx->opcode));
+ tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
+
+static void gen_xsxsigqp(DisasContext *ctx)
+{
+ TCGv_i64 t0, zr, nan, exp;
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+ get_cpu_vsrl(xbl, rB(ctx->opcode) + 32);
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(32767);
+
+ tcg_gen_extract_i64(exp, xbh, 48, 15);
+ tcg_gen_movi_i64(t0, 0x0001000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
+ set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ tcg_gen_mov_i64(xtl, xbl);
+ set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+#endif
+
+static void gen_xviexpsp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xah;
+ TCGv_i64 xal;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xah = tcg_temp_new_i64();
+ xal = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xah, xA(ctx->opcode));
+ get_cpu_vsrl(xal, xA(ctx->opcode));
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+ t0 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF);
+ tcg_gen_andi_i64(t0, xbh, 0xFF000000FF);
+ tcg_gen_shli_i64(t0, t0, 23);
+ tcg_gen_or_i64(xth, xth, t0);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF);
+ tcg_gen_andi_i64(t0, xbl, 0xFF000000FF);
+ tcg_gen_shli_i64(t0, t0, 23);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xah);
+ tcg_temp_free_i64(xal);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+static void gen_xviexpdp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xah;
+ TCGv_i64 xal;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xah = tcg_temp_new_i64();
+ xal = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xah, xA(ctx->opcode));
+ get_cpu_vsrl(xal, xA(ctx->opcode));
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+
+ tcg_gen_deposit_i64(xth, xah, xbh, 52, 11);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+
+ tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xah);
+ tcg_temp_free_i64(xal);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+static void gen_xvxexpsp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+
+ tcg_gen_shri_i64(xth, xbh, 23);
+ tcg_gen_andi_i64(xth, xth, 0xFF000000FF);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ tcg_gen_shri_i64(xtl, xbl, 23);
+ tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+static void gen_xvxexpdp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+
+ tcg_gen_extract_i64(xth, xbh, 52, 11);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+ tcg_gen_extract_i64(xtl, xbl, 52, 11);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
+
+static void gen_xvxsigdp(DisasContext *ctx)
+{
+ TCGv_i64 xth;
+ TCGv_i64 xtl;
+ TCGv_i64 xbh;
+ TCGv_i64 xbl;
+ TCGv_i64 t0, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new_i64();
+ xtl = tcg_temp_new_i64();
+ xbh = tcg_temp_new_i64();
+ xbl = tcg_temp_new_i64();
+ get_cpu_vsrh(xbh, xB(ctx->opcode));
+ get_cpu_vsrl(xbl, xB(ctx->opcode));
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ tcg_gen_extract_i64(exp, xbh, 52, 11);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
+ set_cpu_vsrh(xT(ctx->opcode), xth);
+
+ tcg_gen_extract_i64(exp, xbl, 52, 11);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52);
+ set_cpu_vsrl(xT(ctx->opcode), xtl);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+ tcg_temp_free_i64(xth);
+ tcg_temp_free_i64(xtl);
+ tcg_temp_free_i64(xbh);
+ tcg_temp_free_i64(xbl);
+}
+
+#undef GEN_XX2FORM
+#undef GEN_XX3FORM
+#undef GEN_XX2IFORM
+#undef GEN_XX3_RC_FORM
+#undef GEN_XX3FORM_DM
+#undef VSX_LOGICAL
+++ /dev/null
-/*** VSX extension ***/
-
-static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
-{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true));
-}
-
-static inline void get_cpu_vsrl(TCGv_i64 dst, int n)
-{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false));
-}
-
-static inline void set_cpu_vsrh(int n, TCGv_i64 src)
-{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true));
-}
-
-static inline void set_cpu_vsrl(int n, TCGv_i64 src)
-{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false));
-}
-
-static inline TCGv_ptr gen_vsr_ptr(int reg)
-{
- TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg));
- return r;
-}
-
-#define VSX_LOAD_SCALAR(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##operation(ctx, t0, EA); \
- set_cpu_vsrh(xT(ctx->opcode), t0); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-VSX_LOAD_SCALAR(lxsdx, ld64_i64)
-VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
-VSX_LOAD_SCALAR(lxsibzx, ld8u_i64)
-VSX_LOAD_SCALAR(lxsihzx, ld16u_i64)
-VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
-VSX_LOAD_SCALAR(lxsspx, ld32fs)
-
-static void gen_lxvd2x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrh(xT(ctx->opcode), t0);
- tcg_gen_addi_tl(EA, EA, 8);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrl(xT(ctx->opcode), t0);
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_lxvdsx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrh(xT(ctx->opcode), t0);
- tcg_gen_mov_i64(t1, t0);
- set_cpu_vsrl(xT(ctx->opcode), t1);
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
-static void gen_lxvw4x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 xth;
- TCGv_i64 xtl;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
-
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
-
- gen_addr_reg_index(ctx, EA);
- if (ctx->le_mode) {
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ);
- tcg_gen_shri_i64(t1, t0, 32);
- tcg_gen_deposit_i64(xth, t1, t0, 32, 32);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ);
- tcg_gen_shri_i64(t1, t0, 32);
- tcg_gen_deposit_i64(xtl, t1, t0, 32, 32);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- } else {
- tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
- }
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
- tcg_temp_free(EA);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
-}
-
-static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
- TCGv_i64 inh, TCGv_i64 inl)
-{
- TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- /* outh = ((inh & mask) << 8) | ((inh >> 8) & mask) */
- tcg_gen_and_i64(t0, inh, mask);
- tcg_gen_shli_i64(t0, t0, 8);
- tcg_gen_shri_i64(t1, inh, 8);
- tcg_gen_and_i64(t1, t1, mask);
- tcg_gen_or_i64(outh, t0, t1);
-
- /* outl = ((inl & mask) << 8) | ((inl >> 8) & mask) */
- tcg_gen_and_i64(t0, inl, mask);
- tcg_gen_shli_i64(t0, t0, 8);
- tcg_gen_shri_i64(t1, inl, 8);
- tcg_gen_and_i64(t1, t1, mask);
- tcg_gen_or_i64(outl, t0, t1);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(mask);
-}
-
-static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl,
- TCGv_i64 inh, TCGv_i64 inl)
-{
- TCGv_i64 hi = tcg_temp_new_i64();
- TCGv_i64 lo = tcg_temp_new_i64();
-
- tcg_gen_bswap64_i64(hi, inh);
- tcg_gen_bswap64_i64(lo, inl);
- tcg_gen_shri_i64(outh, hi, 32);
- tcg_gen_deposit_i64(outh, outh, hi, 32, 32);
- tcg_gen_shri_i64(outl, lo, 32);
- tcg_gen_deposit_i64(outl, outl, lo, 32, 32);
-
- tcg_temp_free_i64(hi);
- tcg_temp_free_i64(lo);
-}
-static void gen_lxvh8x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 xth;
- TCGv_i64 xtl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- gen_set_access_type(ctx, ACCESS_INT);
-
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
- if (ctx->le_mode) {
- gen_bswap16x8(xth, xtl, xth, xtl);
- }
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
- tcg_temp_free(EA);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
-}
-
-static void gen_lxvb16x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 xth;
- TCGv_i64 xtl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
- tcg_temp_free(EA);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
-}
-
-#define VSX_VECTOR_LOAD(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsrl(xt, xtl); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsrh(xt, xth); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsrh(xt, xth); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsrl(xt, xtl); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_LOAD(lxv, ld_i64, 0)
-VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
-
-#define VSX_VECTOR_STORE(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, xt); \
- get_cpu_vsrl(xtl, xt); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_STORE(stxv, st_i64, 0)
-VSX_VECTOR_STORE(stxvx, st_i64, 1)
-
-#ifdef TARGET_PPC64
-#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_ptr xt; \
- \
- if (xT(ctx->opcode) < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- EA = tcg_temp_new(); \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- gen_set_access_type(ctx, ACCESS_INT); \
- gen_addr_register(ctx, EA); \
- gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
- tcg_temp_free(EA); \
- tcg_temp_free_ptr(xt); \
-}
-
-VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
-VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
-VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
-VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
-#endif
-
-#define VSX_LOAD_SCALAR_DS(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 xth; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- xth = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0x03); \
- gen_qemu_##operation(ctx, xth, EA); \
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
-}
-
-VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
-VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
-
-#define VSX_STORE_SCALAR(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- get_cpu_vsrh(t0, xS(ctx->opcode)); \
- gen_qemu_##operation(ctx, t0, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-VSX_STORE_SCALAR(stxsdx, st64_i64)
-
-VSX_STORE_SCALAR(stxsibx, st8_i64)
-VSX_STORE_SCALAR(stxsihx, st16_i64)
-VSX_STORE_SCALAR(stxsiwx, st32_i64)
-VSX_STORE_SCALAR(stxsspx, st32fs)
-
-static void gen_stxvd2x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- get_cpu_vsrh(t0, xS(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, EA);
- tcg_gen_addi_tl(EA, EA, 8);
- get_cpu_vsrl(t0, xS(ctx->opcode));
- gen_qemu_st64_i64(ctx, t0, EA);
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_stxvw4x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 xsh;
- TCGv_i64 xsl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xsh = tcg_temp_new_i64();
- xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- if (ctx->le_mode) {
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- tcg_gen_shri_i64(t0, xsh, 32);
- tcg_gen_deposit_i64(t1, t0, xsh, 32, 32);
- tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_shri_i64(t0, xsl, 32);
- tcg_gen_deposit_i64(t1, t0, xsl, 32, 32);
- tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- } else {
- tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
- }
- tcg_temp_free(EA);
- tcg_temp_free_i64(xsh);
- tcg_temp_free_i64(xsl);
-}
-
-static void gen_stxvh8x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 xsh;
- TCGv_i64 xsl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xsh = tcg_temp_new_i64();
- xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- if (ctx->le_mode) {
- TCGv_i64 outh = tcg_temp_new_i64();
- TCGv_i64 outl = tcg_temp_new_i64();
-
- gen_bswap16x8(outh, outl, xsh, xsl);
- tcg_gen_qemu_st_i64(outh, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_st_i64(outl, EA, ctx->mem_idx, MO_BEQ);
- tcg_temp_free_i64(outh);
- tcg_temp_free_i64(outl);
- } else {
- tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
- }
- tcg_temp_free(EA);
- tcg_temp_free_i64(xsh);
- tcg_temp_free_i64(xsl);
-}
-
-static void gen_stxvb16x(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 xsh;
- TCGv_i64 xsl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xsh = tcg_temp_new_i64();
- xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
- tcg_gen_addi_tl(EA, EA, 8);
- tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
- tcg_temp_free(EA);
- tcg_temp_free_i64(xsh);
- tcg_temp_free_i64(xsl);
-}
-
-#define VSX_STORE_SCALAR_DS(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 xth; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- xth = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0x03); \
- gen_qemu_##operation(ctx, xth, EA); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
-}
-
-VSX_STORE_SCALAR_DS(stxsd, st64_i64)
-VSX_STORE_SCALAR_DS(stxssp, st32fs)
-
-static void gen_mfvsrwz(DisasContext *ctx)
-{
- if (xS(ctx->opcode) < 32) {
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv_i64 xsh = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- tcg_gen_ext32u_i64(tmp, xsh);
- tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(xsh);
-}
-
-static void gen_mtvsrwa(DisasContext *ctx)
-{
- if (xS(ctx->opcode) < 32) {
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv_i64 xsh = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32s_i64(xsh, tmp);
- set_cpu_vsrh(xT(ctx->opcode), xsh);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(xsh);
-}
-
-static void gen_mtvsrwz(DisasContext *ctx)
-{
- if (xS(ctx->opcode) < 32) {
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv_i64 xsh = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_ext32u_i64(xsh, tmp);
- set_cpu_vsrh(xT(ctx->opcode), xsh);
- tcg_temp_free_i64(tmp);
- tcg_temp_free_i64(xsh);
-}
-
-#if defined(TARGET_PPC64)
-static void gen_mfvsrd(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (xS(ctx->opcode) < 32) {
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- t0 = tcg_temp_new_i64();
- get_cpu_vsrh(t0, xS(ctx->opcode));
- tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_mtvsrd(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (xS(ctx->opcode) < 32) {
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- t0 = tcg_temp_new_i64();
- tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- set_cpu_vsrh(xT(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_mfvsrld(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (xS(ctx->opcode) < 32) {
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- t0 = tcg_temp_new_i64();
- get_cpu_vsrl(t0, xS(ctx->opcode));
- tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_mtvsrdd(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (xT(ctx->opcode) < 32) {
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
-
- t0 = tcg_temp_new_i64();
- if (!rA(ctx->opcode)) {
- tcg_gen_movi_i64(t0, 0);
- } else {
- tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- }
- set_cpu_vsrh(xT(ctx->opcode), t0);
-
- tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]);
- set_cpu_vsrl(xT(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_mtvsrws(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (xT(ctx->opcode) < 32) {
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
-
- t0 = tcg_temp_new_i64();
- tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], 32, 32);
- set_cpu_vsrl(xT(ctx->opcode), t0);
- set_cpu_vsrh(xT(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
-}
-
-#endif
-
-static void gen_xxpermdi(DisasContext *ctx)
-{
- TCGv_i64 xh, xl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
-
- xh = tcg_temp_new_i64();
- xl = tcg_temp_new_i64();
-
- if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
- (xT(ctx->opcode) == xB(ctx->opcode)))) {
- if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsrh(xh, xA(ctx->opcode));
- } else {
- get_cpu_vsrl(xh, xA(ctx->opcode));
- }
- if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsrh(xl, xB(ctx->opcode));
- } else {
- get_cpu_vsrl(xl, xB(ctx->opcode));
- }
-
- set_cpu_vsrh(xT(ctx->opcode), xh);
- set_cpu_vsrl(xT(ctx->opcode), xl);
- } else {
- if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsrh(xh, xA(ctx->opcode));
- set_cpu_vsrh(xT(ctx->opcode), xh);
- } else {
- get_cpu_vsrl(xh, xA(ctx->opcode));
- set_cpu_vsrh(xT(ctx->opcode), xh);
- }
- if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsrh(xl, xB(ctx->opcode));
- set_cpu_vsrl(xT(ctx->opcode), xl);
- } else {
- get_cpu_vsrl(xl, xB(ctx->opcode));
- set_cpu_vsrl(xT(ctx->opcode), xl);
- }
- }
- tcg_temp_free_i64(xh);
- tcg_temp_free_i64(xl);
-}
-
-#define OP_ABS 1
-#define OP_NABS 2
-#define OP_NEG 3
-#define OP_CPSGN 4
-#define SGN_MASK_DP 0x8000000000000000ull
-#define SGN_MASK_SP 0x8000000080000000ull
-
-#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_i64 xb, sgm; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xb = tcg_temp_new_i64(); \
- sgm = tcg_temp_new_i64(); \
- get_cpu_vsrh(xb, xB(ctx->opcode)); \
- tcg_gen_movi_i64(sgm, sgn_mask); \
- switch (op) { \
- case OP_ABS: { \
- tcg_gen_andc_i64(xb, xb, sgm); \
- break; \
- } \
- case OP_NABS: { \
- tcg_gen_or_i64(xb, xb, sgm); \
- break; \
- } \
- case OP_NEG: { \
- tcg_gen_xor_i64(xb, xb, sgm); \
- break; \
- } \
- case OP_CPSGN: { \
- TCGv_i64 xa = tcg_temp_new_i64(); \
- get_cpu_vsrh(xa, xA(ctx->opcode)); \
- tcg_gen_and_i64(xa, xa, sgm); \
- tcg_gen_andc_i64(xb, xb, sgm); \
- tcg_gen_or_i64(xb, xb, xa); \
- tcg_temp_free_i64(xa); \
- break; \
- } \
- } \
- set_cpu_vsrh(xT(ctx->opcode), xb); \
- tcg_temp_free_i64(xb); \
- tcg_temp_free_i64(sgm); \
- }
-
-VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
-VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
-VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
-VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
-
-#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- int xa; \
- int xt = rD(ctx->opcode) + 32; \
- int xb = rB(ctx->opcode) + 32; \
- TCGv_i64 xah, xbh, xbl, sgm, tmp; \
- \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xbh = tcg_temp_new_i64(); \
- xbl = tcg_temp_new_i64(); \
- sgm = tcg_temp_new_i64(); \
- tmp = tcg_temp_new_i64(); \
- get_cpu_vsrh(xbh, xb); \
- get_cpu_vsrl(xbl, xb); \
- tcg_gen_movi_i64(sgm, sgn_mask); \
- switch (op) { \
- case OP_ABS: \
- tcg_gen_andc_i64(xbh, xbh, sgm); \
- break; \
- case OP_NABS: \
- tcg_gen_or_i64(xbh, xbh, sgm); \
- break; \
- case OP_NEG: \
- tcg_gen_xor_i64(xbh, xbh, sgm); \
- break; \
- case OP_CPSGN: \
- xah = tcg_temp_new_i64(); \
- xa = rA(ctx->opcode) + 32; \
- get_cpu_vsrh(tmp, xa); \
- tcg_gen_and_i64(xah, tmp, sgm); \
- tcg_gen_andc_i64(xbh, xbh, sgm); \
- tcg_gen_or_i64(xbh, xbh, xah); \
- tcg_temp_free_i64(xah); \
- break; \
- } \
- set_cpu_vsrh(xt, xbh); \
- set_cpu_vsrl(xt, xbl); \
- tcg_temp_free_i64(xbl); \
- tcg_temp_free_i64(xbh); \
- tcg_temp_free_i64(sgm); \
- tcg_temp_free_i64(tmp); \
-}
-
-VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
-VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
-VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
-VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
-
-#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_i64 xbh, xbl, sgm; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xbh = tcg_temp_new_i64(); \
- xbl = tcg_temp_new_i64(); \
- sgm = tcg_temp_new_i64(); \
- get_cpu_vsrh(xbh, xB(ctx->opcode)); \
- get_cpu_vsrl(xbl, xB(ctx->opcode)); \
- tcg_gen_movi_i64(sgm, sgn_mask); \
- switch (op) { \
- case OP_ABS: { \
- tcg_gen_andc_i64(xbh, xbh, sgm); \
- tcg_gen_andc_i64(xbl, xbl, sgm); \
- break; \
- } \
- case OP_NABS: { \
- tcg_gen_or_i64(xbh, xbh, sgm); \
- tcg_gen_or_i64(xbl, xbl, sgm); \
- break; \
- } \
- case OP_NEG: { \
- tcg_gen_xor_i64(xbh, xbh, sgm); \
- tcg_gen_xor_i64(xbl, xbl, sgm); \
- break; \
- } \
- case OP_CPSGN: { \
- TCGv_i64 xah = tcg_temp_new_i64(); \
- TCGv_i64 xal = tcg_temp_new_i64(); \
- get_cpu_vsrh(xah, xA(ctx->opcode)); \
- get_cpu_vsrl(xal, xA(ctx->opcode)); \
- tcg_gen_and_i64(xah, xah, sgm); \
- tcg_gen_and_i64(xal, xal, sgm); \
- tcg_gen_andc_i64(xbh, xbh, sgm); \
- tcg_gen_andc_i64(xbl, xbl, sgm); \
- tcg_gen_or_i64(xbh, xbh, xah); \
- tcg_gen_or_i64(xbl, xbl, xal); \
- tcg_temp_free_i64(xah); \
- tcg_temp_free_i64(xal); \
- break; \
- } \
- } \
- set_cpu_vsrh(xT(ctx->opcode), xbh); \
- set_cpu_vsrl(xT(ctx->opcode), xbl); \
- tcg_temp_free_i64(xbh); \
- tcg_temp_free_i64(xbl); \
- tcg_temp_free_i64(sgm); \
- }
-
-VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
-VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
-VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
-VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
-VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
-VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
-VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
-VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
-
-#define VSX_CMP(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 ignored; \
- TCGv_ptr xt, xa, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xa = gen_vsr_ptr(xA(ctx->opcode)); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- if ((ctx->opcode >> (31 - 21)) & 1) { \
- gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \
- } else { \
- ignored = tcg_temp_new_i32(); \
- gen_helper_##name(ignored, cpu_env, xt, xa, xb); \
- tcg_temp_free_i32(ignored); \
- } \
- gen_helper_float_check_status(cpu_env); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(xb); \
-}
-
-VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
-VSX_CMP(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
-VSX_CMP(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
-VSX_CMP(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300)
-VSX_CMP(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
-VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
-VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
-VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
-
-static void gen_xscvqpdp(DisasContext *ctx)
-{
- TCGv_i32 opc;
- TCGv_ptr xt, xb;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- opc = tcg_const_i32(ctx->opcode);
- xt = gen_vsr_ptr(xT(ctx->opcode));
- xb = gen_vsr_ptr(xB(ctx->opcode));
- gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
- tcg_temp_free_i32(opc);
- tcg_temp_free_ptr(xt);
- tcg_temp_free_ptr(xb);
-}
-
-#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 opc; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- opc = tcg_const_i32(ctx->opcode); \
- gen_helper_##name(cpu_env, opc); \
- tcg_temp_free_i32(opc); \
-}
-
-#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr xt, xa, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xa = gen_vsr_ptr(xA(ctx->opcode)); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, xt, xa, xb); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr xt, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, xt, xb); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 opc; \
- TCGv_ptr xa, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- opc = tcg_const_i32(ctx->opcode); \
- xa = gen_vsr_ptr(xA(ctx->opcode)); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, opc, xa, xb); \
- tcg_temp_free_i32(opc); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 opc; \
- TCGv_ptr xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- opc = tcg_const_i32(ctx->opcode); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, opc, xb); \
- tcg_temp_free_i32(opc); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 opc; \
- TCGv_ptr xt, xa, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- opc = tcg_const_i32(ctx->opcode); \
- xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
- xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
- xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xt, xa, xb); \
- tcg_temp_free_i32(opc); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 opc; \
- TCGv_ptr xt, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- opc = tcg_const_i32(ctx->opcode); \
- xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
- xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xt, xb); \
- tcg_temp_free_i32(opc); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 opc; \
- TCGv_ptr xa, xb; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- opc = tcg_const_i32(ctx->opcode); \
- xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
- xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xa, xb); \
- tcg_temp_free_i32(opc); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(xb); \
-}
-
-#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- get_cpu_vsrh(t0, xB(ctx->opcode)); \
- gen_helper_##name(t1, cpu_env, t0); \
- set_cpu_vsrh(xT(ctx->opcode), t1); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
-}
-
-GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_R3(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
-GEN_VSX_HELPER_R3(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
-GEN_VSX_HELPER_R3(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
-GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
-GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
-GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
-GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
-GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
-GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
-GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
-GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
-GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
-GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
-GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
-GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300)
-GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300)
-
-GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
-GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
-
-GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
-GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300)
-GEN_VSX_HELPER_X2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
-GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
-GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
-GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
-
-#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr xt, xa, b, c; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xa = gen_vsr_ptr(xA(ctx->opcode)); \
- if (ctx->opcode & PPC_BIT32(25)) { \
- /* \
- * AxT + B \
- */ \
- b = gen_vsr_ptr(xT(ctx->opcode)); \
- c = gen_vsr_ptr(xB(ctx->opcode)); \
- } else { \
- /* \
- * AxB + T \
- */ \
- b = gen_vsr_ptr(xB(ctx->opcode)); \
- c = gen_vsr_ptr(xT(ctx->opcode)); \
- } \
- gen_helper_##name(cpu_env, xt, xa, b, c); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(b); \
- tcg_temp_free_ptr(c); \
-}
-
-GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvnmsubdp, 0x04, 0x1E, 0x1F, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvmaddsp, 0x04, 0x08, 0x09, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvmsubsp, 0x04, 0x0A, 0x0B, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvnmaddsp, 0x04, 0x18, 0x19, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xvnmsubsp, 0x04, 0x1A, 0x1B, 0, PPC2_VSX)
-
-static void gen_xxbrd(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
-
- tcg_gen_bswap64_i64(xth, xbh);
- tcg_gen_bswap64_i64(xtl, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-static void gen_xxbrh(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
-
- gen_bswap16x8(xth, xtl, xbh, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-static void gen_xxbrq(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
- TCGv_i64 t0;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
- t0 = tcg_temp_new_i64();
-
- tcg_gen_bswap64_i64(t0, xbl);
- tcg_gen_bswap64_i64(xtl, xbh);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
- tcg_gen_mov_i64(xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-static void gen_xxbrw(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
-
- gen_bswap32x4(xth, xtl, xbh, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-#define VSX_LOGICAL(name, vece, tcg_op) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \
- vsr_full_offset(xA(ctx->opcode)), \
- vsr_full_offset(xB(ctx->opcode)), 16, 16); \
- }
-
-VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)
-VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)
-VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)
-VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)
-VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)
-VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)
-VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)
-VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)
-
-#define VSX_XXMRG(name, high) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_i64 a0, a1, b0, b1, tmp; \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- a0 = tcg_temp_new_i64(); \
- a1 = tcg_temp_new_i64(); \
- b0 = tcg_temp_new_i64(); \
- b1 = tcg_temp_new_i64(); \
- tmp = tcg_temp_new_i64(); \
- if (high) { \
- get_cpu_vsrh(a0, xA(ctx->opcode)); \
- get_cpu_vsrh(a1, xA(ctx->opcode)); \
- get_cpu_vsrh(b0, xB(ctx->opcode)); \
- get_cpu_vsrh(b1, xB(ctx->opcode)); \
- } else { \
- get_cpu_vsrl(a0, xA(ctx->opcode)); \
- get_cpu_vsrl(a1, xA(ctx->opcode)); \
- get_cpu_vsrl(b0, xB(ctx->opcode)); \
- get_cpu_vsrl(b1, xB(ctx->opcode)); \
- } \
- tcg_gen_shri_i64(a0, a0, 32); \
- tcg_gen_shri_i64(b0, b0, 32); \
- tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \
- set_cpu_vsrh(xT(ctx->opcode), tmp); \
- tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \
- set_cpu_vsrl(xT(ctx->opcode), tmp); \
- tcg_temp_free_i64(a0); \
- tcg_temp_free_i64(a1); \
- tcg_temp_free_i64(b0); \
- tcg_temp_free_i64(b1); \
- tcg_temp_free_i64(tmp); \
- }
-
-VSX_XXMRG(xxmrghw, 1)
-VSX_XXMRG(xxmrglw, 0)
-
-static void gen_xxsel(DisasContext *ctx)
-{
- int rt = xT(ctx->opcode);
- int ra = xA(ctx->opcode);
- int rb = xB(ctx->opcode);
- int rc = xC(ctx->opcode);
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc),
- vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
-}
-
-static void gen_xxspltw(DisasContext *ctx)
-{
- int rt = xT(ctx->opcode);
- int rb = xB(ctx->opcode);
- int uim = UIM(ctx->opcode);
- int tofs, bofs;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
-
- tofs = vsr_full_offset(rt);
- bofs = vsr_full_offset(rb);
- bofs += uim << MO_32;
-#ifndef HOST_WORDS_BIG_ENDIAN
- bofs ^= 8 | 4;
-#endif
-
- tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
-}
-
-#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
-
-static void gen_xxspltib(DisasContext *ctx)
-{
- uint8_t uim8 = IMM8(ctx->opcode);
- int rt = xT(ctx->opcode);
-
- if (rt < 32) {
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- } else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- }
- tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
-}
-
-static void gen_xxsldwi(DisasContext *ctx)
-{
- TCGv_i64 xth, xtl;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
-
- switch (SHW(ctx->opcode)) {
- case 0: {
- get_cpu_vsrh(xth, xA(ctx->opcode));
- get_cpu_vsrl(xtl, xA(ctx->opcode));
- break;
- }
- case 1: {
- TCGv_i64 t0 = tcg_temp_new_i64();
- get_cpu_vsrh(xth, xA(ctx->opcode));
- tcg_gen_shli_i64(xth, xth, 32);
- get_cpu_vsrl(t0, xA(ctx->opcode));
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_or_i64(xth, xth, t0);
- get_cpu_vsrl(xtl, xA(ctx->opcode));
- tcg_gen_shli_i64(xtl, xtl, 32);
- get_cpu_vsrh(t0, xB(ctx->opcode));
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_or_i64(xtl, xtl, t0);
- tcg_temp_free_i64(t0);
- break;
- }
- case 2: {
- get_cpu_vsrl(xth, xA(ctx->opcode));
- get_cpu_vsrh(xtl, xB(ctx->opcode));
- break;
- }
- case 3: {
- TCGv_i64 t0 = tcg_temp_new_i64();
- get_cpu_vsrl(xth, xA(ctx->opcode));
- tcg_gen_shli_i64(xth, xth, 32);
- get_cpu_vsrh(t0, xB(ctx->opcode));
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_or_i64(xth, xth, t0);
- get_cpu_vsrh(xtl, xB(ctx->opcode));
- tcg_gen_shli_i64(xtl, xtl, 32);
- get_cpu_vsrl(t0, xB(ctx->opcode));
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_or_i64(xtl, xtl, t0);
- tcg_temp_free_i64(t0);
- break;
- }
- }
-
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
-}
-
-#define VSX_EXTRACT_INSERT(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr xt, xb; \
- TCGv_i32 t0; \
- TCGv_i64 t1; \
- uint8_t uimm = UIMM4(ctx->opcode); \
- \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xb = gen_vsr_ptr(xB(ctx->opcode)); \
- t0 = tcg_temp_new_i32(); \
- t1 = tcg_temp_new_i64(); \
- /* \
- * uimm > 15 out of bound and for \
- * uimm > 12 handle as per hardware in helper \
- */ \
- if (uimm > 15) { \
- tcg_gen_movi_i64(t1, 0); \
- set_cpu_vsrh(xT(ctx->opcode), t1); \
- set_cpu_vsrl(xT(ctx->opcode), t1); \
- return; \
- } \
- tcg_gen_movi_i32(t0, uimm); \
- gen_helper_##name(cpu_env, xt, xb, t0); \
- tcg_temp_free_ptr(xb); \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_i32(t0); \
- tcg_temp_free_i64(t1); \
-}
-
-VSX_EXTRACT_INSERT(xxextractuw)
-VSX_EXTRACT_INSERT(xxinsertw)
-
-#ifdef TARGET_PPC64
-static void gen_xsxexpdp(DisasContext *ctx)
-{
- TCGv rt = cpu_gpr[rD(ctx->opcode)];
- TCGv_i64 t0;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- t0 = tcg_temp_new_i64();
- get_cpu_vsrh(t0, xB(ctx->opcode));
- tcg_gen_extract_i64(rt, t0, 52, 11);
- tcg_temp_free_i64(t0);
-}
-
-static void gen_xsxexpqp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
-
- tcg_gen_extract_i64(xth, xbh, 48, 15);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
- tcg_gen_movi_i64(xtl, 0);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
-
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
-}
-
-static void gen_xsiexpdp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv ra = cpu_gpr[rA(ctx->opcode)];
- TCGv rb = cpu_gpr[rB(ctx->opcode)];
- TCGv_i64 t0;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- t0 = tcg_temp_new_i64();
- xth = tcg_temp_new_i64();
- tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
- tcg_gen_andi_i64(t0, rb, 0x7FF);
- tcg_gen_shli_i64(t0, t0, 52);
- tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- /* dword[1] is undefined */
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(xth);
-}
-
-static void gen_xsiexpqp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xah;
- TCGv_i64 xal;
- TCGv_i64 xbh;
- TCGv_i64 t0;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xah = tcg_temp_new_i64();
- xal = tcg_temp_new_i64();
- get_cpu_vsrh(xah, rA(ctx->opcode) + 32);
- get_cpu_vsrl(xal, rA(ctx->opcode) + 32);
- xbh = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
- t0 = tcg_temp_new_i64();
-
- tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF);
- tcg_gen_andi_i64(t0, xbh, 0x7FFF);
- tcg_gen_shli_i64(t0, t0, 48);
- tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
- tcg_gen_mov_i64(xtl, xal);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xah);
- tcg_temp_free_i64(xal);
- tcg_temp_free_i64(xbh);
-}
-
-static void gen_xsxsigdp(DisasContext *ctx)
-{
- TCGv rt = cpu_gpr[rD(ctx->opcode)];
- TCGv_i64 t0, t1, zr, nan, exp;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- exp = tcg_temp_new_i64();
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
-
- get_cpu_vsrh(t1, xB(ctx->opcode));
- tcg_gen_extract_i64(exp, t1, 52, 11);
- tcg_gen_movi_i64(t0, 0x0010000000000000);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- get_cpu_vsrh(t1, xB(ctx->opcode));
- tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(exp);
- tcg_temp_free_i64(zr);
- tcg_temp_free_i64(nan);
-}
-
-static void gen_xsxsigqp(DisasContext *ctx)
-{
- TCGv_i64 t0, zr, nan, exp;
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
- get_cpu_vsrl(xbl, rB(ctx->opcode) + 32);
- exp = tcg_temp_new_i64();
- t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(32767);
-
- tcg_gen_extract_i64(exp, xbh, 48, 15);
- tcg_gen_movi_i64(t0, 0x0001000000000000);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
- tcg_gen_mov_i64(xtl, xbl);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(exp);
- tcg_temp_free_i64(zr);
- tcg_temp_free_i64(nan);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-#endif
-
-static void gen_xviexpsp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xah;
- TCGv_i64 xal;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
- TCGv_i64 t0;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xah = tcg_temp_new_i64();
- xal = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xah, xA(ctx->opcode));
- get_cpu_vsrl(xal, xA(ctx->opcode));
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
- t0 = tcg_temp_new_i64();
-
- tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF);
- tcg_gen_andi_i64(t0, xbh, 0xFF000000FF);
- tcg_gen_shli_i64(t0, t0, 23);
- tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF);
- tcg_gen_andi_i64(t0, xbl, 0xFF000000FF);
- tcg_gen_shli_i64(t0, t0, 23);
- tcg_gen_or_i64(xtl, xtl, t0);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xah);
- tcg_temp_free_i64(xal);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-static void gen_xviexpdp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xah;
- TCGv_i64 xal;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xah = tcg_temp_new_i64();
- xal = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xah, xA(ctx->opcode));
- get_cpu_vsrl(xal, xA(ctx->opcode));
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
-
- tcg_gen_deposit_i64(xth, xah, xbh, 52, 11);
- set_cpu_vsrh(xT(ctx->opcode), xth);
-
- tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xah);
- tcg_temp_free_i64(xal);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-static void gen_xvxexpsp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
-
- tcg_gen_shri_i64(xth, xbh, 23);
- tcg_gen_andi_i64(xth, xth, 0xFF000000FF);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- tcg_gen_shri_i64(xtl, xbl, 23);
- tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-static void gen_xvxexpdp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
-
- tcg_gen_extract_i64(xth, xbh, 52, 11);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- tcg_gen_extract_i64(xtl, xbl, 52, 11);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
-
-static void gen_xvxsigdp(DisasContext *ctx)
-{
- TCGv_i64 xth;
- TCGv_i64 xtl;
- TCGv_i64 xbh;
- TCGv_i64 xbl;
- TCGv_i64 t0, zr, nan, exp;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- xth = tcg_temp_new_i64();
- xtl = tcg_temp_new_i64();
- xbh = tcg_temp_new_i64();
- xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
- exp = tcg_temp_new_i64();
- t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
-
- tcg_gen_extract_i64(exp, xbh, 52, 11);
- tcg_gen_movi_i64(t0, 0x0010000000000000);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
- set_cpu_vsrh(xT(ctx->opcode), xth);
-
- tcg_gen_extract_i64(exp, xbl, 52, 11);
- tcg_gen_movi_i64(t0, 0x0010000000000000);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
- tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(exp);
- tcg_temp_free_i64(zr);
- tcg_temp_free_i64(nan);
- tcg_temp_free_i64(xth);
- tcg_temp_free_i64(xtl);
- tcg_temp_free_i64(xbh);
- tcg_temp_free_i64(xbl);
-}
-
-#undef GEN_XX2FORM
-#undef GEN_XX3FORM
-#undef GEN_XX2IFORM
-#undef GEN_XX3_RC_FORM
-#undef GEN_XX3FORM_DM
-#undef VSX_LOGICAL
--- /dev/null
+GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
+#endif
+
+GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
+#endif
+
+GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
+#endif
+
+#define GEN_XX1FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
+#define GEN_XX2FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
+
+#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
+
+#define GEN_XX3FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
+
+#define GEN_XX3FORM_NAME(name, opcname, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
+
+#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
+
+#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
+
+#define GEN_XX3FORM_DM(name, opc2, opc3) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
+
+#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \
+GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
+
+#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \
+GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300)
+
+#define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
+
+GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
+GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
+GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x0),
+GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0),
+
+GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
+GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
+GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+
+GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
+GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
+GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpuwz, 0x04, 0x1A, 0x01, 0x00000001),
+
+#ifdef TARGET_PPC64
+GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
+GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
+GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
+GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
+#endif
+
+GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300),
+GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300),
+GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001),
+
+GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
+GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
+
+/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */
+#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \
+GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
+
+GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
+GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
+
+GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
+GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
+GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
+GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
+
+GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
+GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
+GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
+GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
+GEN_VSX_XFORM_300(xsmulqp, 0x04, 0x01, 0x0),
+GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
+GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
+GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
+GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
+GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
+GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
+GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX),
+GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX),
+GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX),
+GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX),
+GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX),
+GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX),
+GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX),
+GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
+GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
+GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
+GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300),
+GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
+GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
+GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
+GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
+GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
+GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
+GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
+GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
+GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
+GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
+GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
+GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
+GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
+GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
+GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001),
+GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
+GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
+GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
+GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
+GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
+GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
+GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
+GEN_VSX_XFORM_300_EO(xscvudqp, 0x04, 0x1A, 0x02, 0x00000001),
+GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
+GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
+GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
+GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
+GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
+GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
+
+GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
+GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
+GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
+GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
+GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0),
+GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
+GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
+GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
+GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207),
+GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207),
+GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
+GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
+
+GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
+GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
+GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
+GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
+GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
+GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
+GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
+GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
+GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmadddp, "xvmaddadp", 0x04, 0x0C, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmadddp, "xvmaddmdp", 0x04, 0x0D, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmsubdp, "xvmsubadp", 0x04, 0x0E, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmsubdp, "xvmsubmdp", 0x04, 0x0F, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddadp", 0x04, 0x1C, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddmdp", 0x04, 0x1D, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubadp", 0x04, 0x1E, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubmdp", 0x04, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
+GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpnedp, 0x0C, 0x0F, PPC2_ISA300),
+GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
+GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
+GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
+GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
+GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
+GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
+GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
+GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
+GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
+GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
+GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
+GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
+GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
+
+GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
+GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
+GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
+GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
+GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
+GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
+GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
+GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
+GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmaddsp, "xvmaddasp", 0x04, 0x08, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmaddsp, "xvmaddmsp", 0x04, 0x09, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmsubsp, "xvmsubasp", 0x04, 0x0A, PPC2_VSX),
+GEN_XX3FORM_NAME(xvmsubsp, "xvmsubmsp", 0x04, 0x0B, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddasp", 0x04, 0x18, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddmsp", 0x04, 0x19, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubasp", 0x04, 0x1A, PPC2_VSX),
+GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubmsp", 0x04, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
+GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpnesp, 0x0C, 0x0B, PPC2_ISA300),
+GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
+GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
+GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
+GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
+GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
+GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
+GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
+GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
+GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
+GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
+GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
+GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
+GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
+GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
+GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300),
+GEN_XX2FORM_EO(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300),
+GEN_XX2FORM_EO(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300),
+GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300),
+
+#define VSX_LOGICAL(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3, fl2)
+
+VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
+VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
+VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
+VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
+VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
+VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
+VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
+GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
+GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
+GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
+GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
+GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
+GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
+GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
+GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
+
+#define GEN_XXSEL_ROW(opc3) \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
+
+GEN_XXSEL_ROW(0x00)
+GEN_XXSEL_ROW(0x01)
+GEN_XXSEL_ROW(0x02)
+GEN_XXSEL_ROW(0x03)
+GEN_XXSEL_ROW(0x04)
+GEN_XXSEL_ROW(0x05)
+GEN_XXSEL_ROW(0x06)
+GEN_XXSEL_ROW(0x07)
+GEN_XXSEL_ROW(0x08)
+GEN_XXSEL_ROW(0x09)
+GEN_XXSEL_ROW(0x0A)
+GEN_XXSEL_ROW(0x0B)
+GEN_XXSEL_ROW(0x0C)
+GEN_XXSEL_ROW(0x0D)
+GEN_XXSEL_ROW(0x0E)
+GEN_XXSEL_ROW(0x0F)
+GEN_XXSEL_ROW(0x10)
+GEN_XXSEL_ROW(0x11)
+GEN_XXSEL_ROW(0x12)
+GEN_XXSEL_ROW(0x13)
+GEN_XXSEL_ROW(0x14)
+GEN_XXSEL_ROW(0x15)
+GEN_XXSEL_ROW(0x16)
+GEN_XXSEL_ROW(0x17)
+GEN_XXSEL_ROW(0x18)
+GEN_XXSEL_ROW(0x19)
+GEN_XXSEL_ROW(0x1A)
+GEN_XXSEL_ROW(0x1B)
+GEN_XXSEL_ROW(0x1C)
+GEN_XXSEL_ROW(0x1D)
+GEN_XXSEL_ROW(0x1E)
+GEN_XXSEL_ROW(0x1F)
+
+GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
+++ /dev/null
-GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
-#endif
-
-GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
-GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
-#endif
-
-GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
-GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
-#endif
-
-#define GEN_XX1FORM(name, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
-
-#define GEN_XX2FORM(name, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
-
-#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
-
-#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
-GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
-
-#define GEN_XX3FORM(name, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
-
-#define GEN_XX3FORM_NAME(name, opcname, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
-
-#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
-
-#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
-
-#define GEN_XX3FORM_DM(name, opc2, opc3) \
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
-GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
-
-#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \
-GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
-
-#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \
-GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300)
-
-#define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x0, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x0, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x0, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x1, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x1, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \
-GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
-
-GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
-GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
-GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x0),
-GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0),
-
-GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
-GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
-GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
-GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
-
-GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
-GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
-GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
-GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
-GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpuwz, 0x04, 0x1A, 0x01, 0x00000001),
-
-#ifdef TARGET_PPC64
-GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
-GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
-GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
-GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
-GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
-GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
-#endif
-
-GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300),
-GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300),
-GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001),
-
-GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
-GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
-GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
-GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300),
-GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
-GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
-
-/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */
-#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \
-GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \
-GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
-
-GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
-GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
-
-GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
-GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
-GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
-GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
-GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
-GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
-GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
-GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
-
-GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
-GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
-GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
-GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
-GEN_VSX_XFORM_300(xsmulqp, 0x04, 0x01, 0x0),
-GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
-GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
-GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
-GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
-GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
-GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX),
-GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
-GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
-GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
-GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300),
-GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
-GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
-GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
-GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
-GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
-GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
-GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
-GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
-GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
-GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
-GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
-GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
-GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
-GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
-GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
-GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
-GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001),
-GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
-GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
-GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
-GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
-GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
-GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
-GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
-GEN_VSX_XFORM_300_EO(xscvudqp, 0x04, 0x1A, 0x02, 0x00000001),
-GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
-GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
-GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
-GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
-GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
-GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
-
-GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
-GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
-GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
-GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
-GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0),
-GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
-GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
-GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
-GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207),
-GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
-GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
-
-GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
-GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
-GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
-GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
-GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
-GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
-GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
-GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
-GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmadddp, "xvmaddadp", 0x04, 0x0C, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmadddp, "xvmaddmdp", 0x04, 0x0D, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmsubdp, "xvmsubadp", 0x04, 0x0E, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmsubdp, "xvmsubmdp", 0x04, 0x0F, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddadp", 0x04, 0x1C, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddmdp", 0x04, 0x1D, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubadp", 0x04, 0x1E, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubmdp", 0x04, 0x1F, PPC2_VSX),
-GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
-GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpnedp, 0x0C, 0x0F, PPC2_ISA300),
-GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
-GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
-GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
-GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
-GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
-GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
-GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
-GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
-GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
-GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
-GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
-GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
-GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
-GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
-
-GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
-GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
-GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
-GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
-GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
-GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
-GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
-GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
-GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmaddsp, "xvmaddasp", 0x04, 0x08, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmaddsp, "xvmaddmsp", 0x04, 0x09, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmsubsp, "xvmsubasp", 0x04, 0x0A, PPC2_VSX),
-GEN_XX3FORM_NAME(xvmsubsp, "xvmsubmsp", 0x04, 0x0B, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddasp", 0x04, 0x18, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddmsp", 0x04, 0x19, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubasp", 0x04, 0x1A, PPC2_VSX),
-GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubmsp", 0x04, 0x1B, PPC2_VSX),
-GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
-GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
-GEN_XX3_RC_FORM(xvcmpnesp, 0x0C, 0x0B, PPC2_ISA300),
-GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
-GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
-GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
-GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
-GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
-GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
-GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
-GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
-GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
-GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
-GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
-GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
-GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
-GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
-GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300),
-GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300),
-GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300),
-GEN_XX2FORM_EO(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300),
-GEN_XX2FORM_EO(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300),
-GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300),
-
-#define VSX_LOGICAL(name, opc2, opc3, fl2) \
-GEN_XX3FORM(name, opc2, opc3, fl2)
-
-VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
-VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
-VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
-VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
-VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
-VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
-VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
-VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
-GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
-GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
-GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
-GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
-GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
-GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
-GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
-GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
-GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
-
-#define GEN_XXSEL_ROW(opc3) \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
-
-GEN_XXSEL_ROW(0x00)
-GEN_XXSEL_ROW(0x01)
-GEN_XXSEL_ROW(0x02)
-GEN_XXSEL_ROW(0x03)
-GEN_XXSEL_ROW(0x04)
-GEN_XXSEL_ROW(0x05)
-GEN_XXSEL_ROW(0x06)
-GEN_XXSEL_ROW(0x07)
-GEN_XXSEL_ROW(0x08)
-GEN_XXSEL_ROW(0x09)
-GEN_XXSEL_ROW(0x0A)
-GEN_XXSEL_ROW(0x0B)
-GEN_XXSEL_ROW(0x0C)
-GEN_XXSEL_ROW(0x0D)
-GEN_XXSEL_ROW(0x0E)
-GEN_XXSEL_ROW(0x0F)
-GEN_XXSEL_ROW(0x10)
-GEN_XXSEL_ROW(0x11)
-GEN_XXSEL_ROW(0x12)
-GEN_XXSEL_ROW(0x13)
-GEN_XXSEL_ROW(0x14)
-GEN_XXSEL_ROW(0x15)
-GEN_XXSEL_ROW(0x16)
-GEN_XXSEL_ROW(0x17)
-GEN_XXSEL_ROW(0x18)
-GEN_XXSEL_ROW(0x19)
-GEN_XXSEL_ROW(0x1A)
-GEN_XXSEL_ROW(0x1B)
-GEN_XXSEL_ROW(0x1C)
-GEN_XXSEL_ROW(0x1D)
-GEN_XXSEL_ROW(0x1E)
-GEN_XXSEL_ROW(0x1F)
-
-GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
--- /dev/null
+/*
+ * PowerPC CPU initialization for qemu.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "disas/dis-asm.h"
+#include "exec/gdbstub.h"
+#include "kvm_ppc.h"
+#include "sysemu/arch_init.h"
+#include "sysemu/cpus.h"
+#include "sysemu/hw_accel.h"
+#include "sysemu/tcg.h"
+#include "cpu-models.h"
+#include "mmu-hash32.h"
+#include "mmu-hash64.h"
+#include "qemu/error-report.h"
+#include "qemu/module.h"
+#include "qemu/qemu-print.h"
+#include "qapi/error.h"
+#include "qapi/qmp/qnull.h"
+#include "qapi/visitor.h"
+#include "hw/qdev-properties.h"
+#include "hw/ppc/ppc.h"
+#include "mmu-book3s-v3.h"
+#include "sysemu/qtest.h"
+#include "qemu/cutils.h"
+#include "disas/capstone.h"
+#include "fpu/softfloat.h"
+#include "qapi/qapi-commands-machine-target.h"
+
+/* #define PPC_DUMP_CPU */
+/* #define PPC_DEBUG_SPR */
+/* #define PPC_DUMP_SPR_ACCESSES */
+/* #define USE_APPLE_GDB */
+
+/*
+ * Generic callbacks:
+ * do nothing but store/retrieve spr value
+ */
+static void spr_load_dump_spr(int sprn)
+{
+#ifdef PPC_DUMP_SPR_ACCESSES
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_load_dump_spr(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+#endif
+}
+
+static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], sprn);
+ spr_load_dump_spr(sprn);
+}
+
+static void spr_store_dump_spr(int sprn)
+{
+#ifdef PPC_DUMP_SPR_ACCESSES
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_store_dump_spr(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+#endif
+}
+
+static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+ spr_store_dump_spr(sprn);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
+{
+#ifdef TARGET_PPC64
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ spr_store_dump_spr(sprn);
+#else
+ spr_write_generic(ctx, sprn, gprn);
+#endif
+}
+
+static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_load_spr(t0, sprn);
+ tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
+ tcg_gen_and_tl(t0, t0, t1);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
+{
+}
+
+#endif
+
+/* SPR common to all PowerPC */
+/* XER */
+static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_read_xer(ctx, cpu_gpr[gprn]);
+}
+
+static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_write_xer(cpu_gpr[gprn]);
+}
+
+/* LR */
+static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
+}
+
+static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
+}
+
+/* CFAR */
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
+}
+
+static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
+}
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
+
+/* CTR */
+static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
+}
+
+static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
+}
+
+/* User read access to SPR */
+/* USPRx */
+/* UMMCRx */
+/* UPMCx */
+/* USIA */
+/* UDECR */
+static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
+}
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
+}
+#endif
+
+/* SPR common to all non-embedded PowerPC */
+/* DECR */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+#endif
+
+/* SPR common to all non-embedded PowerPC, except 601 */
+/* Time base */
+static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+ATTRIBUTE_UNUSED
+static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
+}
+
+ATTRIBUTE_UNUSED
+static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+ATTRIBUTE_UNUSED
+static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
+}
+
+ATTRIBUTE_UNUSED
+static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
+}
+
+#if defined(TARGET_PPC64)
+ATTRIBUTE_UNUSED
+static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
+}
+
+/* HDECR */
+static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
+}
+
+#endif
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+/* IBAT0U...IBAT0U */
+/* IBAT0L...IBAT7L */
+static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+}
+
+static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
+}
+
+static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
+ gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
+ gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
+ gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+/* DBAT0U...DBAT7U */
+/* DBAT0L...DBAT7L */
+static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
+}
+
+static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
+}
+
+static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
+ gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
+ gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
+ gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
+ gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+/* SDR1 */
+static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
+}
+
+#if defined(TARGET_PPC64)
+/* 64 bits PowerPC specific SPRs */
+/* PIDR */
+static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
+}
+
+static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ tcg_temp_free(t0);
+}
+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
+}
+
+/* DPDES */
+static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
+}
+#endif
+#endif
+
+/* PowerPC 601 specific registers */
+/* RTC */
+static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
+ /* Must stop the translation as endianness may have changed */
+ gen_stop_exception(ctx);
+}
+#endif
+
+/* Unified bats */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+}
+
+static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+#endif
+
+/* PowerPC 40x specific registers */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+ gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
+ /* We must stop translation as we may have rebooted */
+ gen_stop_exception(ctx);
+}
+
+static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
+}
+#endif
+
+/* PowerPC 403 specific registers */
+/* PBL1 / PBU1 / PBL2 / PBU2 */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
+}
+
+static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
+ gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
+ gen_store_spr(SPR_PIR, t0);
+ tcg_temp_free(t0);
+}
+#endif
+
+/* SPE specific registers */
+static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_temp_free_i32(t0);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+/* Callback used to write the exception vector base */
+static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
+{
+ int sprn_offs;
+
+ if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR0;
+ } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
+ } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
+ } else {
+ printf("Trying to write an unknown exception vector %d %03x\n",
+ sprn, sprn);
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+ return;
+ }
+
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+#endif
+
+static inline void vscr_init(CPUPPCState *env, uint32_t val)
+{
+ /* Altivec always uses round-to-nearest */
+ set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
+ helper_mtvscr(env, val);
+}
+
+#ifdef CONFIG_USER_ONLY
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, initial_value)
+#else
+#if !defined(CONFIG_KVM)
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, oea_read, oea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, initial_value)
+#else
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, oea_read, oea_write, \
+ one_reg_id, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value)
+#endif
+#endif
+
+#define spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, initial_value) \
+ spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, 0, initial_value)
+
+#define spr_register_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ initial_value) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ 0, initial_value)
+
+static inline void _spr_register(CPUPPCState *env, int num,
+ const char *name,
+ void (*uea_read)(DisasContext *ctx,
+ int gprn, int sprn),
+ void (*uea_write)(DisasContext *ctx,
+ int sprn, int gprn),
+#if !defined(CONFIG_USER_ONLY)
+
+ void (*oea_read)(DisasContext *ctx,
+ int gprn, int sprn),
+ void (*oea_write)(DisasContext *ctx,
+ int sprn, int gprn),
+ void (*hea_read)(DisasContext *opaque,
+ int gprn, int sprn),
+ void (*hea_write)(DisasContext *opaque,
+ int sprn, int gprn),
+#endif
+#if defined(CONFIG_KVM)
+ uint64_t one_reg_id,
+#endif
+ target_ulong initial_value)
+{
+ ppc_spr_t *spr;
+
+ spr = &env->spr_cb[num];
+ if (spr->name != NULL || env->spr[num] != 0x00000000 ||
+#if !defined(CONFIG_USER_ONLY)
+ spr->oea_read != NULL || spr->oea_write != NULL ||
+#endif
+ spr->uea_read != NULL || spr->uea_write != NULL) {
+ printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
+ exit(1);
+ }
+#if defined(PPC_DEBUG_SPR)
+ printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
+ name, initial_value);
+#endif
+ spr->name = name;
+ spr->uea_read = uea_read;
+ spr->uea_write = uea_write;
+#if !defined(CONFIG_USER_ONLY)
+ spr->oea_read = oea_read;
+ spr->oea_write = oea_write;
+ spr->hea_read = hea_read;
+ spr->hea_write = hea_write;
+#endif
+#if defined(CONFIG_KVM)
+ spr->one_reg_id = one_reg_id,
+#endif
+ env->spr[num] = spr->default_value = initial_value;
+}
+
+/* Generic PowerPC SPRs */
+static void gen_spr_generic(CPUPPCState *env)
+{
+ /* Integer processing */
+ spr_register(env, SPR_XER, "XER",
+ &spr_read_xer, &spr_write_xer,
+ &spr_read_xer, &spr_write_xer,
+ 0x00000000);
+ /* Branch contol */
+ spr_register(env, SPR_LR, "LR",
+ &spr_read_lr, &spr_write_lr,
+ &spr_read_lr, &spr_write_lr,
+ 0x00000000);
+ spr_register(env, SPR_CTR, "CTR",
+ &spr_read_ctr, &spr_write_ctr,
+ &spr_read_ctr, &spr_write_ctr,
+ 0x00000000);
+ /* Interrupt processing */
+ spr_register(env, SPR_SRR0, "SRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SRR1, "SRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Processor control */
+ spr_register(env, SPR_SPRG0, "SPRG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG1, "SPRG1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG2, "SPRG2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG3, "SPRG3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR common to all non-embedded PowerPC, including 601 */
+static void gen_spr_ne_601(CPUPPCState *env)
+{
+ /* Exception processing */
+ spr_register_kvm(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSISR, 0x00000000);
+ spr_register_kvm(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAR, 0x00000000);
+ /* Timer */
+ spr_register(env, SPR_DECR, "DECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_decr, &spr_write_decr,
+ 0x00000000);
+}
+
+/* Storage Description Register 1 */
+static void gen_spr_sdr1(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ if (env->has_hv_mode) {
+ /*
+ * SDR1 is a hypervisor resource on CPUs which have a
+ * hypervisor mode
+ */
+ spr_register_hv(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ } else {
+ spr_register(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ }
+#endif
+}
+
+/* BATs 0-3 */
+static void gen_low_BATs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT0U, "IBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT0L, "IBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1U, "IBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1L, "IBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2U, "IBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2L, "IBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3U, "IBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3L, "IBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT0U, "DBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT0L, "DBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT1U, "DBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT1L, "DBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT2U, "DBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT2L, "DBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT3U, "DBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT3L, "DBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ env->nb_BATs += 4;
+#endif
+}
+
+/* BATs 4-7 */
+static void gen_high_BATs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT4U, "IBAT4U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT4L, "IBAT4L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT5U, "IBAT5U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT5L, "IBAT5L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT6U, "IBAT6U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT6L, "IBAT6L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT7U, "IBAT7U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT7L, "IBAT7L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT4U, "DBAT4U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT4L, "DBAT4L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT5U, "DBAT5U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT5L, "DBAT5L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT6U, "DBAT6U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT6L, "DBAT6L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT7U, "DBAT7U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT7L, "DBAT7L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ env->nb_BATs += 4;
+#endif
+}
+
+/* Generic PowerPC time base */
+static void gen_tbl(CPUPPCState *env)
+{
+ spr_register(env, SPR_VTBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_VTBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
+ 0x00000000);
+}
+
+/* Softare table search registers */
+static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = nb_tlbs;
+ env->nb_ways = nb_ways;
+ env->id_tlbs = 1;
+ env->tlb_type = TLB_6XX;
+ spr_register(env, SPR_DMISS, "DMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_DCMP, "DCMP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_HASH1, "HASH1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_HASH2, "HASH2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_IMISS, "IMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_ICMP, "ICMP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_RPA, "RPA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#endif
+}
+
+/* SPR common to MPC755 and G2 */
+static void gen_spr_G2_755(CPUPPCState *env)
+{
+ /* SGPRs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR common to all 7xx PowerPC implementations */
+static void gen_spr_7xx(CPUPPCState *env)
+{
+ /* Breakpoints */
+ /* XXX : not implemented */
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Cache management */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTC, "ICTC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Performance monitors */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC1, "UPMC1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC2, "UPMC2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC3, "UPMC3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC4, "UPMC4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_USIAR, "USIAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+#ifdef TARGET_PPC64
+#ifndef CONFIG_USER_ONLY
+static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 PR=0 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ if (ctx->pr) {
+ gen_load_spr(t1, SPR_UAMOR);
+ } else {
+ gen_load_spr(t1, SPR_AMOR);
+ }
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_AMR, t0);
+ spr_store_dump_spr(SPR_AMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_UAMOR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_UAMOR, t0);
+ spr_store_dump_spr(SPR_UAMOR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_IAMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_IAMR, t0);
+ spr_store_dump_spr(SPR_IAMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+#endif /* CONFIG_USER_ONLY */
+
+static void gen_spr_amr(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ /*
+ * Virtual Page Class Key protection
+ *
+ * The AMR is accessible either via SPR 13 or SPR 29. 13 is
+ * userspace accessible, 29 is privileged. So we only need to set
+ * the kvm ONE_REG id on one of them, we use 29
+ */
+ spr_register(env, SPR_UAMR, "UAMR",
+ &spr_read_generic, &spr_write_amr,
+ &spr_read_generic, &spr_write_amr,
+ 0);
+ spr_register_kvm_hv(env, SPR_AMR, "AMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_amr,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_AMR, 0);
+ spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_uamor,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_UAMOR, 0);
+ spr_register_hv(env, SPR_AMOR, "AMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+#endif /* !CONFIG_USER_ONLY */
+}
+
+static void gen_spr_iamr(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_iamr,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_IAMR, 0);
+#endif /* !CONFIG_USER_ONLY */
+}
+#endif /* TARGET_PPC64 */
+
+#ifndef CONFIG_USER_ONLY
+static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_fixup_thrm(cpu_env);
+ gen_load_spr(cpu_gpr[gprn], sprn);
+ spr_load_dump_spr(sprn);
+}
+#endif /* !CONFIG_USER_ONLY */
+
+static void gen_spr_thrm(CPUPPCState *env)
+{
+ /* Thermal management */
+ /* XXX : not implemented */
+ spr_register(env, SPR_THRM1, "THRM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_THRM2, "THRM2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_THRM3, "THRM3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 604 implementation */
+static void gen_spr_604(CPUPPCState *env)
+{
+ /* Processor identification */
+ spr_register(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* Breakpoints */
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+ /* Performance counters */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_SDA, "SDA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 603 implementation */
+static void gen_spr_603(CPUPPCState *env)
+{
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Breakpoints */
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+}
+
+/* SPR specific to PowerPC G2 implementation */
+static void gen_spr_G2(CPUPPCState *env)
+{
+ /* Memory base address */
+ /* MBAR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MBAR, "MBAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Exception processing */
+ spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Breakpoints */
+ /* XXX : not implemented */
+ spr_register(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_DABR2, "DABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR2, "IABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IBCR, "IBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_DBCR, "DBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 602 implementation */
+static void gen_spr_602(CPUPPCState *env)
+{
+ /* ESA registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_SER, "SER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_SEBR, "SEBR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_ESASRR, "ESASRR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Floating point status */
+ /* XXX : not implemented */
+ spr_register(env, SPR_SP, "SP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_LT, "LT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Watchdog timer */
+ /* XXX : not implemented */
+ spr_register(env, SPR_TCR, "TCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Interrupt base */
+ spr_register(env, SPR_IBR, "IBR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 601 implementation */
+static void gen_spr_601(CPUPPCState *env)
+{
+ /* Multiplication/division register */
+ /* MQ */
+ spr_register(env, SPR_MQ, "MQ",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* RTC registers */
+ spr_register(env, SPR_601_RTCU, "RTCU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_601_rtcu,
+ 0x00000000);
+ spr_register(env, SPR_601_VRTCU, "RTCU",
+ &spr_read_601_rtcu, SPR_NOACCESS,
+ &spr_read_601_rtcu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_601_RTCL, "RTCL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_601_rtcl,
+ 0x00000000);
+ spr_register(env, SPR_601_VRTCL, "RTCL",
+ &spr_read_601_rtcl, SPR_NOACCESS,
+ &spr_read_601_rtcl, SPR_NOACCESS,
+ 0x00000000);
+ /* Timer */
+#if 0 /* ? */
+ spr_register(env, SPR_601_UDECR, "UDECR",
+ &spr_read_decr, SPR_NOACCESS,
+ &spr_read_decr, SPR_NOACCESS,
+ 0x00000000);
+#endif
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT0U, "IBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT0L, "IBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1U, "IBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1L, "IBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2U, "IBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2L, "IBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3U, "IBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3L, "IBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_601_ubat, &spr_write_601_ubatl,
+ 0x00000000);
+ env->nb_BATs = 4;
+#endif
+}
+
+static void gen_spr_74xx(CPUPPCState *env)
+{
+ /* Processor identification */
+ spr_register(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_74XX_MMCR2, "MMCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX: not implemented */
+ spr_register(env, SPR_BAMR, "BAMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSCR0, "MSSCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Altivec */
+ spr_register(env, SPR_VRSAVE, "VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* Not strictly an SPR */
+ vscr_init(env, 0x00010000);
+}
+
+static void gen_l3_ctrl(CPUPPCState *env)
+{
+ /* L3CR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3CR, "L3CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR0, "L3ITCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3PM */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3PM, "L3PM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = nb_tlbs;
+ env->nb_ways = nb_ways;
+ env->id_tlbs = 1;
+ env->tlb_type = TLB_6XX;
+ /* XXX : not implemented */
+ spr_register(env, SPR_PTEHI, "PTEHI",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_PTELO, "PTELO",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_TLBMISS, "TLBMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#endif
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
+}
+static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
+}
+
+#endif
+
+static void gen_spr_usprg3(CPUPPCState *env)
+{
+ spr_register(env, SPR_USPRG3, "USPRG3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_usprgh(CPUPPCState *env)
+{
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
+/* PowerPC BookE SPR */
+static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
+{
+ const char *ivor_names[64] = {
+ "IVOR0", "IVOR1", "IVOR2", "IVOR3",
+ "IVOR4", "IVOR5", "IVOR6", "IVOR7",
+ "IVOR8", "IVOR9", "IVOR10", "IVOR11",
+ "IVOR12", "IVOR13", "IVOR14", "IVOR15",
+ "IVOR16", "IVOR17", "IVOR18", "IVOR19",
+ "IVOR20", "IVOR21", "IVOR22", "IVOR23",
+ "IVOR24", "IVOR25", "IVOR26", "IVOR27",
+ "IVOR28", "IVOR29", "IVOR30", "IVOR31",
+ "IVOR32", "IVOR33", "IVOR34", "IVOR35",
+ "IVOR36", "IVOR37", "IVOR38", "IVOR39",
+ "IVOR40", "IVOR41", "IVOR42", "IVOR43",
+ "IVOR44", "IVOR45", "IVOR46", "IVOR47",
+ "IVOR48", "IVOR49", "IVOR50", "IVOR51",
+ "IVOR52", "IVOR53", "IVOR54", "IVOR55",
+ "IVOR56", "IVOR57", "IVOR58", "IVOR59",
+ "IVOR60", "IVOR61", "IVOR62", "IVOR63",
+ };
+#define SPR_BOOKE_IVORxx (-1)
+ int ivor_sprn[64] = {
+ SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
+ SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
+ SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
+ SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
+ SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
+ SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
+ };
+ int i;
+
+ /* Interrupt processing */
+ spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Debug */
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC1, "IAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC2, "IAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DAC1, "DAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DAC2, "DAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_40x_dbcr0,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DBSR, "DBSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DEAR, "DEAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_ESR, "ESR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_IVPR, "IVPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_excp_prefix,
+ 0x00000000);
+ /* Exception vectors */
+ for (i = 0; i < 64; i++) {
+ if (ivor_mask & (1ULL << i)) {
+ if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
+ fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
+ exit(1);
+ }
+ spr_register(env, ivor_sprn[i], ivor_names[i],
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_excp_vector,
+ 0x00000000);
+ }
+ }
+ spr_register(env, SPR_BOOKE_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_pid,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_TCR, "TCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_tcr,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_TSR, "TSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_tsr,
+ 0x00000000);
+ /* Timer */
+ spr_register(env, SPR_DECR, "DECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_decr, &spr_write_decr,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DECAR, "DECAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* SPRGs */
+ spr_register(env, SPR_USPRG0, "USPRG0",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
+ uint32_t maxsize, uint32_t flags,
+ uint32_t nentries)
+{
+ return (assoc << TLBnCFG_ASSOC_SHIFT) |
+ (minsize << TLBnCFG_MINSIZE_SHIFT) |
+ (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
+ flags | nentries;
+}
+
+/* BookE 2.06 storage control registers */
+static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
+ uint32_t *tlbncfg, uint32_t mmucfg)
+{
+#if !defined(CONFIG_USER_ONLY)
+ const char *mas_names[8] = {
+ "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
+ };
+ int mas_sprn[8] = {
+ SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
+ SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
+ };
+ int i;
+
+ /* TLB assist registers */
+ /* XXX : not implemented */
+ for (i = 0; i < 8; i++) {
+ void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
+ &spr_write_generic32;
+ if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
+ uea_write = &spr_write_generic;
+ }
+ if (mas_mask & (1 << i)) {
+ spr_register(env, mas_sprn[i], mas_names[i],
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, uea_write,
+ 0x00000000);
+ }
+ }
+ if (env->nb_pids > 1) {
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_PID1, "PID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_pid,
+ 0x00000000);
+ }
+ if (env->nb_pids > 2) {
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_PID2, "PID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_pid,
+ 0x00000000);
+ }
+
+ spr_register(env, SPR_BOOKE_EPLC, "EPLC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_eplc,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_EPSC, "EPSC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_epsc,
+ 0x00000000);
+
+ /* XXX : not implemented */
+ spr_register(env, SPR_MMUCFG, "MMUCFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ mmucfg);
+ switch (env->nb_ways) {
+ case 4:
+ spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ tlbncfg[3]);
+ /* Fallthru */
+ case 3:
+ spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ tlbncfg[2]);
+ /* Fallthru */
+ case 2:
+ spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ tlbncfg[1]);
+ /* Fallthru */
+ case 1:
+ spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ tlbncfg[0]);
+ /* Fallthru */
+ case 0:
+ default:
+ break;
+ }
+#endif
+
+ gen_spr_usprgh(env);
+}
+
+/* SPR specific to PowerPC 440 implementation */
+static void gen_spr_440(CPUPPCState *env)
+{
+ /* Cache control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DNV0, "DNV0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DNV1, "DNV1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DNV2, "DNV2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DNV3, "DNV3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DTV0, "DTV0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DTV1, "DTV1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DTV2, "DTV2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DTV3, "DTV3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DVLIM, "DVLIM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_INV0, "INV0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_INV1, "INV1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_INV2, "INV2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_INV3, "INV3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_ITV0, "ITV0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_ITV1, "ITV1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_ITV2, "ITV2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_ITV3, "ITV3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_IVLIM, "IVLIM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Cache debug */
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_DBDR, "DBDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Processor control */
+ spr_register(env, SPR_4xx_CCR0, "CCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_440_RSTCFG, "RSTCFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* Storage control */
+ spr_register(env, SPR_440_MMUCR, "MMUCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR shared between PowerPC 40x implementations */
+static void gen_spr_40x(CPUPPCState *env)
+{
+ /* Cache */
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_DCCR, "DCCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_ICCR, "ICCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* Exception */
+ spr_register(env, SPR_40x_DEAR, "DEAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_ESR, "ESR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_EVPR, "EVPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_excp_prefix,
+ 0x00000000);
+ spr_register(env, SPR_40x_SRR2, "SRR2",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_SRR3, "SRR3",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Timers */
+ spr_register(env, SPR_40x_PIT, "PIT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_40x_pit, &spr_write_40x_pit,
+ 0x00000000);
+ spr_register(env, SPR_40x_TCR, "TCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_tcr,
+ 0x00000000);
+ spr_register(env, SPR_40x_TSR, "TSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke_tsr,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 405 implementation */
+static void gen_spr_405(CPUPPCState *env)
+{
+ /* MMU */
+ spr_register(env, SPR_40x_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_4xx_CCR0, "CCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00700000);
+ /* Debug interface */
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DBCR0, "DBCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_40x_dbcr0,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_405_DBCR1, "DBCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DBSR, "DBSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ /* Last reset was system reset */
+ 0x00000300);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DAC1, "DAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_DAC2, "DAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_405_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_405_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_IAC1, "IAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_IAC2, "IAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_405_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_405_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Storage control */
+ /* XXX: TODO: not implemented */
+ spr_register(env, SPR_405_SLER, "SLER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_40x_sler,
+ 0x00000000);
+ spr_register(env, SPR_40x_ZPR, "ZPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_405_SU0R, "SU0R",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* SPRG */
+ spr_register(env, SPR_USPRG0, "USPRG0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ gen_spr_usprgh(env);
+}
+
+/* SPR shared between PowerPC 401 & 403 implementations */
+static void gen_spr_401_403(CPUPPCState *env)
+{
+ /* Time base */
+ spr_register(env, SPR_403_VTBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_403_TBL, "TBL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_403_VTBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_403_TBU, "TBU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbu,
+ 0x00000000);
+ /* Debug */
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_403_CDBCR, "CDBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 401 implementation */
+static void gen_spr_401(CPUPPCState *env)
+{
+ /* Debug interface */
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DBCR0, "DBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_40x_dbcr0,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DBSR, "DBSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ /* Last reset was system reset */
+ 0x00000300);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DAC1, "DAC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_IAC1, "IAC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Storage control */
+ /* XXX: TODO: not implemented */
+ spr_register(env, SPR_405_SLER, "SLER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_40x_sler,
+ 0x00000000);
+ /* not emulated, as QEMU never does speculative access */
+ spr_register(env, SPR_40x_SGR, "SGR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0xFFFFFFFF);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_DCWR, "DCWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_401x2(CPUPPCState *env)
+{
+ gen_spr_401(env);
+ spr_register(env, SPR_40x_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_ZPR, "ZPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC 403 implementation */
+static void gen_spr_403(CPUPPCState *env)
+{
+ /* Debug interface */
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DBCR0, "DBCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_40x_dbcr0,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DBSR, "DBSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ /* Last reset was system reset */
+ 0x00000300);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DAC1, "DAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_DAC2, "DAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_IAC1, "IAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_40x_IAC2, "IAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_403_real(CPUPPCState *env)
+{
+ spr_register(env, SPR_403_PBL1, "PBL1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_403_pbr, &spr_write_403_pbr,
+ 0x00000000);
+ spr_register(env, SPR_403_PBU1, "PBU1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_403_pbr, &spr_write_403_pbr,
+ 0x00000000);
+ spr_register(env, SPR_403_PBL2, "PBL2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_403_pbr, &spr_write_403_pbr,
+ 0x00000000);
+ spr_register(env, SPR_403_PBU2, "PBU2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_403_pbr, &spr_write_403_pbr,
+ 0x00000000);
+}
+
+static void gen_spr_403_mmu(CPUPPCState *env)
+{
+ /* MMU */
+ spr_register(env, SPR_40x_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_40x_ZPR, "ZPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/* SPR specific to PowerPC compression coprocessor extension */
+static void gen_spr_compress(CPUPPCState *env)
+{
+ /* XXX : not implemented */
+ spr_register(env, SPR_401_SKR, "SKR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_5xx_8xx(CPUPPCState *env)
+{
+ /* Exception processing */
+ spr_register_kvm(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSISR, 0x00000000);
+ spr_register_kvm(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAR, 0x00000000);
+ /* Timer */
+ spr_register(env, SPR_DECR, "DECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_decr, &spr_write_decr,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_EIE, "EIE",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_EID, "EID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_NRI, "NRI",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPA, "CMPA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPB, "CMPB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPC, "CMPC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPD, "CMPD",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_ECR, "ECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DER, "DER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_COUNTA, "COUNTA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_COUNTB, "COUNTB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPE, "CMPE",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPF, "CMPF",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPG, "CMPG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_CMPH, "CMPH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_BAR, "BAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DPDR, "DPDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IMMR, "IMMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_5xx(CPUPPCState *env)
+{
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_RCPU_FPECR, "FPECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_8xx(CPUPPCState *env)
+{
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IC_CST, "IC_CST",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DC_CST, "DC_CST",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_AP, "MI_AP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_AP, "MD_AP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_TW, "MD_TW",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+/*
+ * AMR => SPR 29 (Power 2.04)
+ * CTRL => SPR 136 (Power 2.04)
+ * CTRL => SPR 152 (Power 2.04)
+ * SCOMC => SPR 276 (64 bits ?)
+ * SCOMD => SPR 277 (64 bits ?)
+ * TBU40 => SPR 286 (Power 2.04 hypv)
+ * HSPRG0 => SPR 304 (Power 2.04 hypv)
+ * HSPRG1 => SPR 305 (Power 2.04 hypv)
+ * HDSISR => SPR 306 (Power 2.04 hypv)
+ * HDAR => SPR 307 (Power 2.04 hypv)
+ * PURR => SPR 309 (Power 2.04 hypv)
+ * HDEC => SPR 310 (Power 2.04 hypv)
+ * HIOR => SPR 311 (hypv)
+ * RMOR => SPR 312 (970)
+ * HRMOR => SPR 313 (Power 2.04 hypv)
+ * HSRR0 => SPR 314 (Power 2.04 hypv)
+ * HSRR1 => SPR 315 (Power 2.04 hypv)
+ * LPIDR => SPR 317 (970)
+ * EPR => SPR 702 (Power 2.04 emb)
+ * perf => 768-783 (Power 2.04)
+ * perf => 784-799 (Power 2.04)
+ * PPR => SPR 896 (Power 2.04)
+ * DABRX => 1015 (Power 2.04 hypv)
+ * FPECR => SPR 1022 (?)
+ * ... and more (thermal management, performance counters, ...)
+ */
+
+/*****************************************************************************/
+/* Exception vectors models */
+static void init_excp_4xx_real(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
+ env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
+ env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_4xx_softmmu(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
+ env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
+ env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_MPC5xx(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
+ env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
+ env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_MPC8xx(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
+ env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
+ env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
+ env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_G2(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
+ env->ivor_mask = 0x0000FFF7UL;
+ env->ivpr_mask = ivpr_mask;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_BookE(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
+ env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
+ env->ivor_mask = 0x0000FFF0UL;
+ env->ivpr_mask = 0xFFFF0000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_601(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_602(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* XXX: exception prefix has a special behavior on 602 */
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
+ env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_603(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_604(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_7x0(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_750cl(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_750cx(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+/* XXX: Check if this is correct */
+static void init_excp_7x5(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_7400(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+static void init_excp_7450(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
+ env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
+ env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
+ env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x00000100UL;
+#endif
+}
+
+#if defined(TARGET_PPC64)
+static void init_excp_970(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
+ env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x0000000000000100ULL;
+#endif
+}
+
+static void init_excp_POWER7(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
+ env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
+ env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
+ env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
+ env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x0000000000000100ULL;
+#endif
+}
+
+static void init_excp_POWER8(CPUPPCState *env)
+{
+ init_excp_POWER7(env);
+
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
+ env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
+ env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
+ env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
+#endif
+}
+
+static void init_excp_POWER9(CPUPPCState *env)
+{
+ init_excp_POWER8(env);
+
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000;
+#endif
+}
+
+static void init_excp_POWER10(CPUPPCState *env)
+{
+ init_excp_POWER9(env);
+}
+
+#endif
+
+/*****************************************************************************/
+/* Power management enable checks */
+static int check_pow_none(CPUPPCState *env)
+{
+ return 0;
+}
+
+static int check_pow_nocheck(CPUPPCState *env)
+{
+ return 1;
+}
+
+static int check_pow_hid0(CPUPPCState *env)
+{
+ if (env->spr[SPR_HID0] & 0x00E00000) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static int check_pow_hid0_74xx(CPUPPCState *env)
+{
+ if (env->spr[SPR_HID0] & 0x00600000) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
+{
+ return true;
+}
+
+#ifdef TARGET_PPC64
+static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
+{
+ return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
+}
+#endif
+
+/*****************************************************************************/
+/* PowerPC implementations definitions */
+
+#define POWERPC_FAMILY(_name) \
+ static void \
+ glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
+ \
+ static const TypeInfo \
+ glue(glue(ppc_, _name), _cpu_family_type_info) = { \
+ .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
+ .parent = TYPE_POWERPC_CPU, \
+ .abstract = true, \
+ .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
+ }; \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
+ { \
+ type_register_static( \
+ &glue(glue(ppc_, _name), _cpu_family_type_info)); \
+ } \
+ \
+ type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_class_init)
+
+static void init_proc_401(CPUPPCState *env)
+{
+ gen_spr_40x(env);
+ gen_spr_401_403(env);
+ gen_spr_401(env);
+ init_excp_4xx_real(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 401";
+ pcc->init_proc = init_proc_401;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_WRTEE | PPC_DCR |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << MSR_KEY) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_REAL;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_401x2(CPUPPCState *env)
+{
+ gen_spr_40x(env);
+ gen_spr_401_403(env);
+ gen_spr_401x2(env);
+ gen_spr_compress(env);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_4xx_softmmu(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 401x2";
+ pcc->init_proc = init_proc_401x2;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << 20) |
+ (1ull << MSR_KEY) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_401x3(CPUPPCState *env)
+{
+ gen_spr_40x(env);
+ gen_spr_401_403(env);
+ gen_spr_401(env);
+ gen_spr_401x2(env);
+ gen_spr_compress(env);
+ init_excp_4xx_softmmu(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 401x3";
+ pcc->init_proc = init_proc_401x3;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << 20) |
+ (1ull << MSR_KEY) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_IOP480(CPUPPCState *env)
+{
+ gen_spr_40x(env);
+ gen_spr_401_403(env);
+ gen_spr_401x2(env);
+ gen_spr_compress(env);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_4xx_softmmu(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(8, 12, 16, 20);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "IOP480";
+ pcc->init_proc = init_proc_IOP480;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << 20) |
+ (1ull << MSR_KEY) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_403(CPUPPCState *env)
+{
+ gen_spr_40x(env);
+ gen_spr_401_403(env);
+ gen_spr_403(env);
+ gen_spr_403_real(env);
+ init_excp_4xx_real(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(8, 12, 16, 20);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 403";
+ pcc->init_proc = init_proc_403;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_PE) |
+ (1ull << MSR_PX) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_REAL;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_403GCX(CPUPPCState *env)
+{
+ gen_spr_40x(env);
+ gen_spr_401_403(env);
+ gen_spr_403(env);
+ gen_spr_403_real(env);
+ gen_spr_403_mmu(env);
+ /* Bus access control */
+ /* not emulated, as QEMU never does speculative access */
+ spr_register(env, SPR_40x_SGR, "SGR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0xFFFFFFFF);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_DCWR, "DCWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_4xx_softmmu(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(8, 12, 16, 20);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 403 GCX";
+ pcc->init_proc = init_proc_403GCX;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_PE) |
+ (1ull << MSR_PX) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_401;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_405(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_40x(env);
+ gen_spr_405(env);
+ /* Bus access control */
+ /* not emulated, as QEMU never does speculative access */
+ spr_register(env, SPR_40x_SGR, "SGR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0xFFFFFFFF);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_DCWR, "DCWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_4xx_softmmu(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(8, 12, 16, 20);
+ SET_WDT_PERIOD(16, 20, 24, 28);
+}
+
+POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 405";
+ pcc->init_proc = init_proc_405;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
+ PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
+ pcc->excp_model = POWERPC_EXCP_40x;
+ pcc->bus_model = PPC_FLAGS_INPUT_405;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_440EP(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
+ gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_MCSR, "MCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_CCR1, "CCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_BookE(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(20, 24, 28, 32);
+}
+
+POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 440 EP";
+ pcc->init_proc = init_proc_440EP;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 460 EX";
+ pcc->init_proc = init_proc_440EP;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_440GP(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
+ gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_BookE(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(20, 24, 28, 32);
+}
+
+POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 440 GP";
+ pcc->init_proc = init_proc_440GP;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_440x4(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
+ gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_BookE(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(20, 24, 28, 32);
+}
+
+POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 440x4";
+ pcc->init_proc = init_proc_440x4;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_440x5(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_BookE(env, 0x000000000000FFFFULL);
+ gen_spr_440(env);
+ gen_spr_usprgh(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_MCSR, "MCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_440_CCR1, "CCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_BookE(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ ppc40x_irq_init(env_archcpu(env));
+
+ SET_FIT_PERIOD(12, 16, 20, 24);
+ SET_WDT_PERIOD(20, 24, 28, 32);
+}
+
+POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 440x5";
+ pcc->init_proc = init_proc_440x5;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 440x5 with double precision FPU";
+ pcc->init_proc = init_proc_440x5;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_FLOAT | PPC_FLOAT_FSQRT |
+ PPC_FLOAT_STFIWX |
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_MFTB |
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
+ PPC_440_SPEC;
+ pcc->insns_flags2 = PPC2_FP_CVT_S64;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_403;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_MPC5xx(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_5xx_8xx(env);
+ gen_spr_5xx(env);
+ init_excp_MPC5xx(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+}
+
+POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "Freescale 5xx cores (aka RCPU)";
+ pcc->init_proc = init_proc_MPC5xx;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_MEM_EIEIO | PPC_MEM_SYNC |
+ PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
+ PPC_MFTB;
+ pcc->msr_mask = (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_REAL;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
+ pcc->bfd_mach = bfd_mach_ppc_505;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_MPC8xx(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_5xx_8xx(env);
+ gen_spr_8xx(env);
+ init_excp_MPC8xx(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+}
+
+POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
+ pcc->init_proc = init_proc_MPC8xx;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+ PPC_MEM_EIEIO | PPC_MEM_SYNC |
+ PPC_CACHE_ICBI | PPC_MFTB;
+ pcc->msr_mask = (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_MPC8xx;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+/* Freescale 82xx cores (aka PowerQUICC-II) */
+
+static void init_proc_G2(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_G2_755(env);
+ gen_spr_G2(env);
+ /* Time base */
+ gen_tbl(env);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation register */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_G2(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC G2";
+ pcc->init_proc = init_proc_G2;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_AL) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_G2;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_ec603e;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_G2LE(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_G2_755(env);
+ gen_spr_G2(env);
+ /* Time base */
+ gen_tbl(env);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation register */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_G2(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC G2LE";
+ pcc->init_proc = init_proc_G2LE;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_AL) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_G2;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_ec603e;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_e200(CPUPPCState *env)
+{
+ /* Time base */
+ gen_tbl(env);
+ gen_spr_BookE(env, 0x000000070000FFFFULL);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
+ &spr_read_spefscr, &spr_write_spefscr,
+ &spr_read_spefscr, &spr_write_spefscr,
+ 0x00000000);
+ /* Memory management */
+ gen_spr_BookE206(env, 0x0000005D, NULL, 0);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000); /* TOFIX */
+ spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 64;
+ env->nb_ways = 1;
+ env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
+#endif
+ init_excp_e200(env, 0xFFFF0000UL);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* XXX: TODO: allocate internal IRQ controller */
+}
+
+POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e200 core";
+ pcc->init_proc = init_proc_e200;
+ pcc->check_pow = check_pow_hid0;
+ /*
+ * XXX: unimplemented instructions:
+ * dcblc
+ * dcbtlst
+ * dcbtstls
+ * icblc
+ * icbtls
+ * tlbivax
+ * all SPE multiply-accumulate instructions
+ */
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_SPE | PPC_SPE_SINGLE |
+ PPC_WRTEE | PPC_RFDI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX |
+ PPC_BOOKE;
+ pcc->msr_mask = (1ull << MSR_UCLE) |
+ (1ull << MSR_SPE) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_e300(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_603(env);
+ /* Time base */
+ gen_tbl(env);
+ /* hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Breakpoints */
+ /* XXX : not implemented */
+ spr_register(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_DABR2, "DABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR2, "IABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_IBCR, "IBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_DBCR, "DBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_603(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e300 core";
+ pcc->init_proc = init_proc_e300;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_AL) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_603;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv val = tcg_temp_new();
+ tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
+ gen_store_spr(SPR_BOOKE_MAS3, val);
+ tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
+ gen_store_spr(SPR_BOOKE_MAS7, val);
+ tcg_temp_free(val);
+}
+
+static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv mas7 = tcg_temp_new();
+ TCGv mas3 = tcg_temp_new();
+ gen_load_spr(mas7, SPR_BOOKE_MAS7);
+ tcg_gen_shli_tl(mas7, mas7, 32);
+ gen_load_spr(mas3, SPR_BOOKE_MAS3);
+ tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
+ tcg_temp_free(mas3);
+ tcg_temp_free(mas7);
+}
+
+#endif
+
+enum fsl_e500_version {
+ fsl_e500v1,
+ fsl_e500v2,
+ fsl_e500mc,
+ fsl_e5500,
+ fsl_e6500,
+};
+
+static void init_proc_e500(CPUPPCState *env, int version)
+{
+ uint32_t tlbncfg[2];
+ uint64_t ivor_mask;
+ uint64_t ivpr_mask = 0xFFFF0000ULL;
+ uint32_t l1cfg0 = 0x3800 /* 8 ways */
+ | 0x0020; /* 32 kb */
+ uint32_t l1cfg1 = 0x3800 /* 8 ways */
+ | 0x0020; /* 32 kb */
+ uint32_t mmucfg = 0;
+#if !defined(CONFIG_USER_ONLY)
+ int i;
+#endif
+
+ /* Time base */
+ gen_tbl(env);
+ /*
+ * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
+ * complain when accessing them.
+ * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ */
+ switch (version) {
+ case fsl_e500v1:
+ case fsl_e500v2:
+ default:
+ ivor_mask = 0x0000000F0000FFFFULL;
+ break;
+ case fsl_e500mc:
+ case fsl_e5500:
+ ivor_mask = 0x000003FE0000FFFFULL;
+ break;
+ case fsl_e6500:
+ ivor_mask = 0x000003FF0000FFFFULL;
+ break;
+ }
+ gen_spr_BookE(env, ivor_mask);
+ gen_spr_usprg3(env);
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
+ &spr_read_spefscr, &spr_write_spefscr,
+ &spr_read_spefscr, &spr_write_spefscr,
+ 0x00000000);
+#if !defined(CONFIG_USER_ONLY)
+ /* Memory management */
+ env->nb_pids = 3;
+ env->nb_ways = 2;
+ env->id_tlbs = 0;
+ switch (version) {
+ case fsl_e500v1:
+ tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
+ tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ break;
+ case fsl_e500v2:
+ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ break;
+ case fsl_e500mc:
+ case fsl_e5500:
+ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
+ break;
+ case fsl_e6500:
+ mmucfg = 0x6510B45;
+ env->nb_pids = 1;
+ tlbncfg[0] = 0x08052400;
+ tlbncfg[1] = 0x40028040;
+ break;
+ default:
+ cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
+ env->spr[SPR_PVR]);
+ }
+#endif
+ /* Cache sizes */
+ switch (version) {
+ case fsl_e500v1:
+ case fsl_e500v2:
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ break;
+ case fsl_e500mc:
+ case fsl_e5500:
+ env->dcache_line_size = 64;
+ env->icache_line_size = 64;
+ l1cfg0 |= 0x1000000; /* 64 byte cache block size */
+ l1cfg1 |= 0x1000000; /* 64 byte cache block size */
+ break;
+ case fsl_e6500:
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ l1cfg0 |= 0x0F83820;
+ l1cfg1 |= 0x0B83820;
+ break;
+ default:
+ cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
+ env->spr[SPR_PVR]);
+ }
+ gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_MCAR, "MCAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_BOOKE_MCSR, "MCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ l1cfg0);
+ spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ l1cfg1);
+ spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_e500_l1csr0,
+ 0x00000000);
+ spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_e500_l1csr1,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke206_mmucsr0,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_EPR, "EPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX better abstract into Emb.xxx features */
+ if ((version == fsl_e5500) || (version == fsl_e6500)) {
+ spr_register(env, SPR_BOOKE_EPCR, "EPCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_mas73, &spr_write_mas73,
+ 0x00000000);
+ ivpr_mask = (target_ulong)~0xFFFFULL;
+ }
+
+ if (version == fsl_e6500) {
+ /* Thread identification */
+ spr_register(env, SPR_TIR, "TIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000004);
+ spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x7FFFFFFC);
+ }
+
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = 0;
+ env->tlb_type = TLB_MAS;
+ for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
+ env->nb_tlb += booke206_tlb_size(env, i);
+ }
+#endif
+
+ init_excp_e200(env, ivpr_mask);
+ /* Allocate hardware IRQ controller */
+ ppce500_irq_init(env_archcpu(env));
+}
+
+static void init_proc_e500v1(CPUPPCState *env)
+{
+ init_proc_e500(env, fsl_e500v1);
+}
+
+POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e500v1 core";
+ pcc->init_proc = init_proc_e500v1;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_SPE | PPC_SPE_SINGLE |
+ PPC_WRTEE | PPC_RFDI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
+ pcc->insns_flags2 = PPC2_BOOKE206;
+ pcc->msr_mask = (1ull << MSR_UCLE) |
+ (1ull << MSR_SPE) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_e500v2(CPUPPCState *env)
+{
+ init_proc_e500(env, fsl_e500v2);
+}
+
+POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e500v2 core";
+ pcc->init_proc = init_proc_e500v2;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
+ PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
+ PPC_WRTEE | PPC_RFDI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
+ pcc->insns_flags2 = PPC2_BOOKE206;
+ pcc->msr_mask = (1ull << MSR_UCLE) |
+ (1ull << MSR_SPE) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DWE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_860;
+ pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_e500mc(CPUPPCState *env)
+{
+ init_proc_e500(env, fsl_e500mc);
+}
+
+POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e500mc core";
+ pcc->init_proc = init_proc_e500mc;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_FLOAT | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+ PPC_FLOAT_STFIWX | PPC_WAIT |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
+ pcc->msr_mask = (1ull << MSR_GS) |
+ (1ull << MSR_UCLE) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PX) |
+ (1ull << MSR_RI);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ /* FIXME: figure out the correct flag for e500mc */
+ pcc->bfd_mach = bfd_mach_ppc_e500;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+#ifdef TARGET_PPC64
+static void init_proc_e5500(CPUPPCState *env)
+{
+ init_proc_e500(env, fsl_e5500);
+}
+
+POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e5500 core";
+ pcc->init_proc = init_proc_e5500;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_FLOAT | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+ PPC_FLOAT_STFIWX | PPC_WAIT |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
+ PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
+ PPC2_FP_CVT_S64;
+ pcc->msr_mask = (1ull << MSR_CM) |
+ (1ull << MSR_GS) |
+ (1ull << MSR_UCLE) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PX) |
+ (1ull << MSR_RI);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ /* FIXME: figure out the correct flag for e5500 */
+ pcc->bfd_mach = bfd_mach_ppc_e500;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_e6500(CPUPPCState *env)
+{
+ init_proc_e500(env, fsl_e6500);
+}
+
+POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e6500 core";
+ pcc->init_proc = init_proc_e6500;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
+ PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+ PPC_FLOAT | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+ PPC_FLOAT_STFIWX | PPC_WAIT |
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
+ PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
+ PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
+ pcc->msr_mask = (1ull << MSR_CM) |
+ (1ull << MSR_GS) |
+ (1ull << MSR_UCLE) |
+ (1ull << MSR_CE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IS) |
+ (1ull << MSR_DS) |
+ (1ull << MSR_PX) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_VR);
+ pcc->mmu_model = POWERPC_MMU_BOOKE206;
+ pcc->excp_model = POWERPC_EXCP_BOOKE;
+ pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+ pcc->bfd_mach = bfd_mach_ppc_e500;
+ pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
+}
+
+#endif
+
+/* Non-embedded PowerPC */
+
+#define POWERPC_MSRR_601 (0x0000000000001040ULL)
+
+static void init_proc_601(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_601(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_hid0_601,
+ 0x80010080);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_601_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_601_HID5, "HID5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ init_excp_601(env);
+ /*
+ * XXX: beware that dcache line size is 64
+ * but dcbz uses 32 bytes "sectors"
+ * XXX: this breaks clcs instruction !
+ */
+ env->dcache_line_size = 32;
+ env->icache_line_size = 64;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 601";
+ pcc->init_proc = init_proc_601;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
+ PPC_FLOAT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_601;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_601;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_601;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
+}
+
+#define POWERPC_MSRR_601v (0x0000000000001040ULL)
+
+static void init_proc_601v(CPUPPCState *env)
+{
+ init_proc_601(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_601_HID15, "HID15",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 601v";
+ pcc->init_proc = init_proc_601v;
+ pcc->check_pow = check_pow_none;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
+ PPC_FLOAT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR);
+ pcc->mmu_model = POWERPC_MMU_601;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_601;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
+}
+
+static void init_proc_602(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_602(env);
+ /* Time base */
+ gen_tbl(env);
+ /* hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_602(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 602";
+ pcc->init_proc = init_proc_602;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_602_SPEC;
+ pcc->msr_mask = (1ull << MSR_VSX) |
+ (1ull << MSR_SA) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ /* XXX: 602 MMU is quite specific. Should add a special case */
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_602;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_602;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_603(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_603(env);
+ /* Time base */
+ gen_tbl(env);
+ /* hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_603(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 603";
+ pcc->init_proc = init_proc_603;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_603;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_603;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_603E(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_603(env);
+ /* Time base */
+ gen_tbl(env);
+ /* hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_603(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 603e";
+ pcc->init_proc = init_proc_603E;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_603E;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_ec603e;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_604(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_604(env);
+ /* Time base */
+ gen_tbl(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ init_excp_604(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 604";
+ pcc->init_proc = init_proc_604;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_604;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_604;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_604E(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_604(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ init_excp_604(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 604E";
+ pcc->init_proc = init_proc_604E;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_604;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_604;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_740(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 740";
+ pcc->init_proc = init_proc_740;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_750(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /*
+ * XXX: high BATs are also present but are known to be bugged on
+ * die version 1.x
+ */
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 750";
+ pcc->init_proc = init_proc_750;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_750cl(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ /* Those registers are fake on 750CL */
+ spr_register(env, SPR_THRM1, "THRM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_THRM2, "THRM2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_THRM3, "THRM3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX: not implemented */
+ spr_register(env, SPR_750_TDCL, "TDCL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_750_TDCH, "TDCH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* DMA */
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_WPAR, "WPAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_750_DMAL, "DMAL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_750_DMAU, "DMAU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750CL_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750CL_HID4, "HID4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Quantization registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR0, "GQR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR1, "GQR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR2, "GQR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR3, "GQR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR4, "GQR4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR5, "GQR5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR6, "GQR6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR7, "GQR7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750cl has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_750cl(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 750 CL";
+ pcc->init_proc = init_proc_750cl;
+ pcc->check_pow = check_pow_hid0;
+ /*
+ * XXX: not implemented:
+ * cache lock instructions:
+ * dcbz_l
+ * floating point paired instructions
+ * psq_lux
+ * psq_lx
+ * psq_stux
+ * psq_stx
+ * ps_abs
+ * ps_add
+ * ps_cmpo0
+ * ps_cmpo1
+ * ps_cmpu0
+ * ps_cmpu1
+ * ps_div
+ * ps_madd
+ * ps_madds0
+ * ps_madds1
+ * ps_merge00
+ * ps_merge01
+ * ps_merge10
+ * ps_merge11
+ * ps_mr
+ * ps_msub
+ * ps_mul
+ * ps_muls0
+ * ps_muls1
+ * ps_nabs
+ * ps_neg
+ * ps_nmadd
+ * ps_nmsub
+ * ps_res
+ * ps_rsqrte
+ * ps_sel
+ * ps_sub
+ * ps_sum0
+ * ps_sum1
+ */
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_750cx(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* This register is not implemented but is present for compatibility */
+ spr_register(env, SPR_SDA, "SDA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750cx has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_750cx(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 750CX";
+ pcc->init_proc = init_proc_750cx;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_750fx(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_THRM4, "THRM4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750FX_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 750FX";
+ pcc->init_proc = init_proc_750fx;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_750gx(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented (XXX: different from 750fx) */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_THRM4, "THRM4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented (XXX: different from 750fx) */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented (XXX: different from 750fx) */
+ spr_register(env, SPR_750FX_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 750GX";
+ pcc->init_proc = init_proc_750gx;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_7x0;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_745(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ gen_spr_G2_755(env);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_7x5(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 745";
+ pcc->init_proc = init_proc_745;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_7x5;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_755(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ gen_spr_G2_755(env);
+ /* Time base */
+ gen_tbl(env);
+ /* L2 cache control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2PMCR, "L2PMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_7x5(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 755";
+ pcc->init_proc = init_proc_755;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_7x5;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_750;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7400(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX: this seems not implemented on all revisions. */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSCR1, "MSSCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Memory management */
+ gen_low_BATs(env);
+ init_excp_7400(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7400 (aka G4)";
+ pcc->init_proc = init_proc_7400;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7410(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* L2PMCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2PMCR, "L2PMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* LDSTDB */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTDB, "LDSTDB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ init_excp_7400(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7410 (aka G4)";
+ pcc->init_proc = init_proc_7410;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7440(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* LDSTCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* ICTRL */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* MSSSR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* PMC */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7440 (aka G4)";
+ pcc->init_proc = init_proc_7440;
+ pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7450(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* Level 3 cache control */
+ gen_l3_ctrl(env);
+ /* L3ITCR1 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR1, "L3ITCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR2 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR2, "L3ITCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR3 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR3, "L3ITCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3OHCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3OHCR, "L3OHCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* LDSTCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* ICTRL */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* MSSSR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* PMC */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7450 (aka G4)";
+ pcc->init_proc = init_proc_7450;
+ pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7445(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* LDSTCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* ICTRL */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* MSSSR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* PMC */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* SPRGs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7445 (aka G4)";
+ pcc->init_proc = init_proc_7445;
+ pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7455(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* Level 3 cache control */
+ gen_l3_ctrl(env);
+ /* LDSTCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* ICTRL */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* MSSSR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* PMC */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* SPRGs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7455 (aka G4)";
+ pcc->init_proc = init_proc_7455;
+ pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_7457(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* Level 3 cache control */
+ gen_l3_ctrl(env);
+ /* L3ITCR1 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR1, "L3ITCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR2 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR2, "L3ITCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR3 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR3, "L3ITCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3OHCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3OHCR, "L3OHCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* LDSTCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* ICTRL */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* MSSSR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* PMC */
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* SPRGs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 7457 (aka G4)";
+ pcc->init_proc = init_proc_7457;
+ pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+static void init_proc_e600(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_sdr1(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* SPRGs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC e600";
+ pcc->init_proc = init_proc_e600;
+ pcc->check_pow = check_pow_hid0_74xx;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI |
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN |
+ PPC_ALTIVEC;
+ pcc->insns_flags2 = PPC_NONE;
+ pcc->msr_mask = (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
+ pcc->excp_model = POWERPC_EXCP_74xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_7400;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+}
+
+#if defined(TARGET_PPC64)
+#if defined(CONFIG_USER_ONLY)
+#define POWERPC970_HID5_INIT 0x00000080
+#else
+#define POWERPC970_HID5_INIT 0x00000000
+#endif
+
+static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
+ int bit, int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
+ int bit, int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv spr_up = tcg_temp_new();
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_shri_tl(spr_up, spr, 32);
+ tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
+
+ tcg_temp_free(spr);
+ tcg_temp_free(spr_up);
+}
+
+static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
+ gen_store_spr(sprn - 1, spr);
+
+ tcg_temp_free(spr);
+}
+
+static int check_pow_970(CPUPPCState *env)
+{
+ if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void gen_spr_970_hid(CPUPPCState *env)
+{
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ 0x60000000);
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_970_HID5, "HID5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ POWERPC970_HID5_INIT);
+}
+
+static void gen_spr_970_hior(CPUPPCState *env)
+{
+ spr_register(env, SPR_HIOR, "SPR_HIOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_ctrl(CPUPPCState *env)
+{
+ spr_register(env, SPR_CTRL, "SPR_CTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_altivec(CPUPPCState *env)
+{
+ if (!(env->insns_flags & PPC_ALTIVEC)) {
+ return;
+ }
+
+ spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_VRSAVE, 0x00000000);
+
+ /*
+ * Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors.
+ */
+ vscr_init(env, 0x00010000);
+}
+
+static void gen_spr_book3s_dbg(CPUPPCState *env)
+{
+ /*
+ * TODO: different specs define different scopes for these,
+ * will have to address this:
+ * 970: super/write and super/read
+ * powerisa 2.03..2.04: hypv/write and super/read.
+ * powerisa 2.05 and newer: hypv/write and hypv/read.
+ */
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+ spr_register_kvm(env, SPR_DABRX, "DABRX",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABRX, 0x00000000);
+}
+
+static void gen_spr_book3s_207_dbg(CPUPPCState *env)
+{
+ spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAWR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAWRX, 0x00000000);
+ spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_CIABR, 0x00000000);
+}
+
+static void gen_spr_970_dbg(CPUPPCState *env)
+{
+ /* Breakpoints */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR0, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR1, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRA, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC1, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC3, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC4, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC5, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC6, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIAR, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SDAR, 0x00000000);
+}
+
+static void gen_spr_book3s_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC1, "UPMC1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC2, "UPMC2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC3, "UPMC3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC4, "UPMC4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIAR, "USIAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USDAR, "USDAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+}
+
+static void gen_spr_970_pmu_sup(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_970_PMC7, "PMC7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC7, 0x00000000);
+ spr_register_kvm(env, SPR_970_PMC8, "PMC8",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC8, 0x00000000);
+}
+
+static void gen_spr_970_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_970_UPMC7, "UPMC7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_970_UPMC8, "UPMC8",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+}
+
+static void gen_spr_power8_pmu_sup(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRS, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER, "SIER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SPMC1, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SPMC2, 0x00000000);
+ spr_register_kvm(env, SPR_TACR, "TACR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_TACR, 0x00000000);
+ spr_register_kvm(env, SPR_TCSCR, "TCSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_TCSCR, 0x00000000);
+ spr_register_kvm(env, SPR_CSIGR, "CSIGR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_CSIGR, 0x00000000);
+}
+
+static void gen_spr_power8_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER, "USIER",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_power5p_ear(CPUPPCState *env)
+{
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_power5p_tb(CPUPPCState *env)
+{
+ /* TBU40 (High 40 bits of the Timebase register */
+ spr_register_hv(env, SPR_TBU40, "TBU40",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbu40,
+ 0x00000000);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv hmer = tcg_temp_new();
+
+ gen_load_spr(hmer, sprn);
+ tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
+ gen_store_spr(sprn, hmer);
+ spr_store_dump_spr(sprn);
+ tcg_temp_free(hmer);
+}
+
+static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
+}
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+static void gen_spr_970_lpar(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /*
+ * PPC970: HID4 covers things later controlled by the LPCR and
+ * RMOR in later CPUs, but with a different encoding. We only
+ * support the 970 in "Apple mode" which has all hypervisor
+ * facilities disabled by strapping, so we can basically just
+ * ignore it
+ */
+ spr_register(env, SPR_970_HID4, "HID4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#endif
+}
+
+static void gen_spr_power5p_lpar(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* Logical partitionning */
+ spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_lpcr,
+ KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
+ spr_register_hv(env, SPR_HDEC, "HDEC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_hdecr, &spr_write_hdecr, 0);
+#endif
+}
+
+static void gen_spr_book3s_ids(CPUPPCState *env)
+{
+ /* FIXME: Will need to deal with thread vs core only SPRs */
+
+ /* Processor identification */
+ spr_register_hv(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, NULL,
+ 0x00000000);
+ spr_register_hv(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TSCR, "TSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMER, "HMER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_hmer,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMEER, "HMEER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TFMR, "TFMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_LPIDR, "LPIDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_lpidr,
+ 0x00000000);
+ spr_register_hv(env, SPR_HFSCR, "HFSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_MMCRC, "MMCRC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_MMCRH, "MMCRH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSRR0, "HSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSRR1, "HSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HDAR, "HDAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HDSISR, "HDSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HRMOR, "HRMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_rmor(CPUPPCState *env)
+{
+ spr_register_hv(env, SPR_RMOR, "RMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_power8_ids(CPUPPCState *env)
+{
+ /* Thread identification */
+ spr_register(env, SPR_TIR, "TIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_purr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
+ spr_register_kvm_hv(env, SPR_PURR, "PURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, &spr_write_purr,
+ KVM_REG_PPC_PURR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, &spr_write_purr,
+ KVM_REG_PPC_SPURR, 0x00000000);
+#endif
+}
+
+static void gen_spr_power6_dbg(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_CFAR, "SPR_CFAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_cfar, &spr_write_cfar,
+ 0x00000000);
+#endif
+}
+
+static void gen_spr_power5p_common(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PPR, 0x00000000);
+}
+
+static void gen_spr_power6_common(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSCR, 0x00000000);
+#endif
+ /*
+ * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
+ * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
+ */
+ spr_register_hv(env, SPR_PCR, "PCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pcr,
+ 0x00000000);
+}
+
+static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void gen_spr_power8_tce_address_control(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_TAR, "TAR",
+ &spr_read_tar, &spr_write_tar,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_TAR, 0x00000000);
+}
+
+static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_prev_upper32(ctx, gprn, sprn);
+}
+
+static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_prev_upper32(ctx, sprn, gprn);
+}
+
+static void gen_spr_power8_tm(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_TFHAR, "TFHAR",
+ &spr_read_tm, &spr_write_tm,
+ &spr_read_tm, &spr_write_tm,
+ KVM_REG_PPC_TFHAR, 0x00000000);
+ spr_register_kvm(env, SPR_TFIAR, "TFIAR",
+ &spr_read_tm, &spr_write_tm,
+ &spr_read_tm, &spr_write_tm,
+ KVM_REG_PPC_TFIAR, 0x00000000);
+ spr_register_kvm(env, SPR_TEXASR, "TEXASR",
+ &spr_read_tm, &spr_write_tm,
+ &spr_read_tm, &spr_write_tm,
+ KVM_REG_PPC_TEXASR, 0x00000000);
+ spr_register(env, SPR_TEXASRU, "TEXASRU",
+ &spr_read_tm_upper32, &spr_write_tm_upper32,
+ &spr_read_tm_upper32, &spr_write_tm_upper32,
+ 0x00000000);
+}
+
+static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_prev_upper32(ctx, gprn, sprn);
+}
+
+static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_prev_upper32(ctx, sprn, gprn);
+}
+
+static void gen_spr_power8_ebb(CPUPPCState *env)
+{
+ spr_register(env, SPR_BESCRS, "BESCRS",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRSU, "BESCRSU",
+ &spr_read_ebb_upper32, &spr_write_ebb_upper32,
+ &spr_read_prev_upper32, &spr_write_prev_upper32,
+ 0x00000000);
+ spr_register(env, SPR_BESCRR, "BESCRR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRRU, "BESCRRU",
+ &spr_read_ebb_upper32, &spr_write_ebb_upper32,
+ &spr_read_prev_upper32, &spr_write_prev_upper32,
+ 0x00000000);
+ spr_register_kvm(env, SPR_EBBHR, "EBBHR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_EBBHR, 0x00000000);
+ spr_register_kvm(env, SPR_EBBRR, "EBBRR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_EBBRR, 0x00000000);
+ spr_register_kvm(env, SPR_BESCR, "BESCR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_BESCR, 0x00000000);
+}
+
+/* Virtual Time Base */
+static void gen_spr_vtb(CPUPPCState *env)
+{
+ spr_register_kvm_hv(env, SPR_VTB, "VTB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_vtb, SPR_NOACCESS,
+ &spr_read_vtb, &spr_write_vtb,
+ KVM_REG_PPC_VTB, 0x00000000);
+}
+
+static void gen_spr_power8_fscr(CPUPPCState *env)
+{
+#if defined(CONFIG_USER_ONLY)
+ target_ulong initval = 1ULL << FSCR_TAR;
+#else
+ target_ulong initval = 0;
+#endif
+ spr_register_kvm(env, SPR_FSCR, "FSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_FSCR, initval);
+}
+
+static void gen_spr_power8_pspb(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_PSPB, "PSPB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic32,
+ KVM_REG_PPC_PSPB, 0);
+}
+
+static void gen_spr_power8_dpdes(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* Directed Privileged Door-bell Exception State, used for IPI */
+ spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dpdes, SPR_NOACCESS,
+ &spr_read_dpdes, &spr_write_dpdes,
+ KVM_REG_PPC_DPDES, 0x00000000);
+#endif
+}
+
+static void gen_spr_power8_ic(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_IC, "IC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+#endif
+}
+
+static void gen_spr_power8_book4(CPUPPCState *env)
+{
+ /* Add a number of P8 book4 registers */
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_ACOP, "ACOP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_ACOP, 0);
+ spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pidr,
+ KVM_REG_PPC_PID, 0);
+ spr_register_kvm(env, SPR_WORT, "WORT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_WORT, 0);
+#endif
+}
+
+static void gen_spr_power7_book4(CPUPPCState *env)
+{
+ /* Add a number of P7 book4 registers */
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_ACOP, "ACOP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_ACOP, 0);
+ spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PID, 0);
+#endif
+}
+
+static void gen_spr_power8_rpr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_RPR, "RPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000103070F1F3F);
+#endif
+}
+
+static void gen_spr_power9_mmu(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* Partition Table Control */
+ spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_ptcr,
+ KVM_REG_PPC_PTCR, 0x00000000);
+ /* Address Segment Descriptor Register */
+ spr_register_hv(env, SPR_ASDR, "ASDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x0000000000000000);
+#endif
+}
+
+static void init_proc_book3s_common(CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_tbl(env);
+ gen_spr_usprg3(env);
+ gen_spr_book3s_altivec(env);
+ gen_spr_book3s_pmu_sup(env);
+ gen_spr_book3s_pmu_user(env);
+ gen_spr_book3s_ctrl(env);
+}
+
+static void init_proc_970(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_sdr1(env);
+ gen_spr_book3s_dbg(env);
+
+ /* 970 Specific Registers */
+ gen_spr_970_hid(env);
+ gen_spr_970_hior(env);
+ gen_low_BATs(env);
+ gen_spr_970_pmu_sup(env);
+ gen_spr_970_pmu_user(env);
+ gen_spr_970_lpar(env);
+ gen_spr_970_dbg(env);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_970(env);
+ ppc970_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "PowerPC 970";
+ pcc->init_proc = init_proc_970;
+ pcc->check_pow = check_pow_970;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC2_FP_CVT_S64;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI);
+ pcc->mmu_model = POWERPC_MMU_64B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_basic;
+#endif
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_970;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x10000;
+}
+
+static void init_proc_power5plus(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_sdr1(env);
+ gen_spr_book3s_dbg(env);
+
+ /* POWER5+ Specific Registers */
+ gen_spr_970_hid(env);
+ gen_spr_970_hior(env);
+ gen_low_BATs(env);
+ gen_spr_970_pmu_sup(env);
+ gen_spr_970_pmu_user(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_970(env);
+ ppc970_irq_init(env_archcpu(env));
+}
+
+POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER5";
+ dc->desc = "POWER5+";
+ pcc->init_proc = init_proc_power5plus;
+ pcc->check_pow = check_pow_970;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B |
+ PPC_SEGMENT_64B | PPC_SLBI;
+ pcc->insns_flags2 = PPC2_FP_CVT_S64;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_POW) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI);
+ pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
+ LPCR_RMI | LPCR_HDICE;
+ pcc->mmu_model = POWERPC_MMU_2_03;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_basic;
+ pcc->lrg_decr_bits = 32;
+#endif
+ pcc->excp_model = POWERPC_EXCP_970;
+ pcc->bus_model = PPC_FLAGS_INPUT_970;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x10000;
+}
+
+static void init_proc_POWER7(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_sdr1(env);
+ gen_spr_book3s_dbg(env);
+
+ /* POWER7 Specific Registers */
+ gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
+ gen_spr_amr(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ gen_spr_power7_book4(env);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_POWER7(env);
+ ppcPOWER7_irq_init(env_archcpu(env));
+}
+
+static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
+ return true;
+ }
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
+ return true;
+ }
+ return false;
+}
+
+static bool cpu_has_work_POWER7(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (cs->halted) {
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+ return false;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+ (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+ (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
+ (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
+ (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
+ return true;
+ }
+ if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+ return true;
+ }
+ return false;
+ } else {
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ }
+}
+
+POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER7";
+ dc->desc = "POWER7";
+ pcc->pvr_match = ppc_pvr_match_power7;
+ pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
+ pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
+ pcc->init_proc = init_proc_POWER7;
+ pcc->check_pow = check_pow_nocheck;
+ cc->has_work = cpu_has_work_POWER7;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
+ PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD |
+ PPC_CILDST;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+ PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
+ PPC2_PM_ISA206;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_VSX) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
+ LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
+ LPCR_MER | LPCR_TC |
+ LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
+ pcc->mmu_model = POWERPC_MMU_2_06;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
+ pcc->lrg_decr_bits = 32;
+#endif
+ pcc->excp_model = POWERPC_EXCP_POWER7;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+ POWERPC_FLAG_VSX;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x8000;
+ pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+}
+
+static void init_proc_POWER8(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_sdr1(env);
+ gen_spr_book3s_207_dbg(env);
+
+ /* POWER8 Specific Registers */
+ gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
+ gen_spr_amr(env);
+ gen_spr_iamr(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ gen_spr_power8_tce_address_control(env);
+ gen_spr_power8_ids(env);
+ gen_spr_power8_ebb(env);
+ gen_spr_power8_fscr(env);
+ gen_spr_power8_pmu_sup(env);
+ gen_spr_power8_pmu_user(env);
+ gen_spr_power8_tm(env);
+ gen_spr_power8_pspb(env);
+ gen_spr_power8_dpdes(env);
+ gen_spr_vtb(env);
+ gen_spr_power8_ic(env);
+ gen_spr_power8_book4(env);
+ gen_spr_power8_rpr(env);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_POWER8(env);
+ ppcPOWER7_irq_init(env_archcpu(env));
+}
+
+static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
+ return true;
+ }
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
+ return true;
+ }
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
+ return true;
+ }
+ return false;
+}
+
+static bool cpu_has_work_POWER8(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (cs->halted) {
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+ return false;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+ (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+ (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
+ (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
+ (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
+ return true;
+ }
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
+ return true;
+ }
+ if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+ return true;
+ }
+ return false;
+ } else {
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ }
+}
+
+POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER8";
+ dc->desc = "POWER8";
+ pcc->pvr_match = ppc_pvr_match_power8;
+ pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
+ pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
+ pcc->init_proc = init_proc_POWER8;
+ pcc->check_pow = check_pow_nocheck;
+ cc->has_work = cpu_has_work_POWER8;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
+ PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD |
+ PPC_CILDST;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+ PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM | PPC2_PM_ISA206;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_HV) |
+ (1ull << MSR_TM) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_VSX) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_TS0) |
+ (1ull << MSR_TS1) |
+ (1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
+ LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
+ LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
+ LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
+ pcc->mmu_model = POWERPC_MMU_2_07;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
+ pcc->lrg_decr_bits = 32;
+ pcc->n_host_threads = 8;
+#endif
+ pcc->excp_model = POWERPC_EXCP_POWER8;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x8000;
+ pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+}
+
+#ifdef CONFIG_SOFTMMU
+/*
+ * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
+ * Encoded as array of int_32s in the form:
+ * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
+ * x -> AP encoding
+ * y -> radix mode supported page size (encoded as a shift)
+ */
+static struct ppc_radix_page_info POWER9_radix_page_info = {
+ .count = 4,
+ .entries = {
+ 0x0000000c, /* 4K - enc: 0x0 */
+ 0xa0000010, /* 64K - enc: 0x5 */
+ 0x20000015, /* 2M - enc: 0x1 */
+ 0x4000001e /* 1G - enc: 0x2 */
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
+static void init_proc_POWER9(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_book3s_207_dbg(env);
+
+ /* POWER8 Specific Registers */
+ gen_spr_book3s_ids(env);
+ gen_spr_amr(env);
+ gen_spr_iamr(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ gen_spr_power8_tce_address_control(env);
+ gen_spr_power8_ids(env);
+ gen_spr_power8_ebb(env);
+ gen_spr_power8_fscr(env);
+ gen_spr_power8_pmu_sup(env);
+ gen_spr_power8_pmu_user(env);
+ gen_spr_power8_tm(env);
+ gen_spr_power8_pspb(env);
+ gen_spr_power8_dpdes(env);
+ gen_spr_vtb(env);
+ gen_spr_power8_ic(env);
+ gen_spr_power8_book4(env);
+ gen_spr_power8_rpr(env);
+ gen_spr_power9_mmu(env);
+
+ /* POWER9 Specific registers */
+ spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
+ spr_read_generic, spr_write_generic,
+ KVM_REG_PPC_TIDR, 0);
+
+ /* FIXME: Filter fields properly based on privilege level */
+ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
+ spr_read_generic, spr_write_generic,
+ KVM_REG_PPC_PSSCR, 0);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_POWER9(env);
+ ppcPOWER9_irq_init(env_archcpu(env));
+}
+
+static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
+ return true;
+ }
+ return false;
+}
+
+static bool cpu_has_work_POWER9(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (cs->halted) {
+ uint64_t psscr = env->spr[SPR_PSSCR];
+
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+ return false;
+ }
+
+ /* If EC is clear, just return true on any pending interrupt */
+ if (!(psscr & PSSCR_EC)) {
+ return true;
+ }
+ /* External Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+ (env->spr[SPR_LPCR] & LPCR_EEE)) {
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ if (heic == 0 || !msr_hv || msr_pr) {
+ return true;
+ }
+ }
+ /* Decrementer Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+ (env->spr[SPR_LPCR] & LPCR_DEE)) {
+ return true;
+ }
+ /* Machine Check or Hypervisor Maintenance Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
+ 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
+ return true;
+ }
+ /* Privileged Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_PDEE)) {
+ return true;
+ }
+ /* Hypervisor Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_HDEE)) {
+ return true;
+ }
+ /* Hypervisor virtualization exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
+ (env->spr[SPR_LPCR] & LPCR_HVEE)) {
+ return true;
+ }
+ if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+ return true;
+ }
+ return false;
+ } else {
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ }
+}
+
+POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER9";
+ dc->desc = "POWER9";
+ pcc->pvr_match = ppc_pvr_match_power9;
+ pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
+ pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
+ PCR_COMPAT_2_05;
+ pcc->init_proc = init_proc_POWER9;
+ pcc->check_pow = check_pow_nocheck;
+ cc->has_work = cpu_has_work_POWER9;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
+ PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD |
+ PPC_CILDST;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+ PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_HV) |
+ (1ull << MSR_TM) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_VSX) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
+ pcc->mmu_model = POWERPC_MMU_3_00;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
+ /* segment page size remain the same */
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
+ pcc->radix_page_info = &POWER9_radix_page_info;
+ pcc->lrg_decr_bits = 56;
+ pcc->n_host_threads = 4;
+#endif
+ pcc->excp_model = POWERPC_EXCP_POWER9;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x8000;
+ pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+}
+
+#ifdef CONFIG_SOFTMMU
+/*
+ * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
+ * Encoded as array of int_32s in the form:
+ * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
+ * x -> AP encoding
+ * y -> radix mode supported page size (encoded as a shift)
+ */
+static struct ppc_radix_page_info POWER10_radix_page_info = {
+ .count = 4,
+ .entries = {
+ 0x0000000c, /* 4K - enc: 0x0 */
+ 0xa0000010, /* 64K - enc: 0x5 */
+ 0x20000015, /* 2M - enc: 0x1 */
+ 0x4000001e /* 1G - enc: 0x2 */
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
+static void init_proc_POWER10(CPUPPCState *env)
+{
+ /* Common Registers */
+ init_proc_book3s_common(env);
+ gen_spr_book3s_207_dbg(env);
+
+ /* POWER8 Specific Registers */
+ gen_spr_book3s_ids(env);
+ gen_spr_amr(env);
+ gen_spr_iamr(env);
+ gen_spr_book3s_purr(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ gen_spr_power8_tce_address_control(env);
+ gen_spr_power8_ids(env);
+ gen_spr_power8_ebb(env);
+ gen_spr_power8_fscr(env);
+ gen_spr_power8_pmu_sup(env);
+ gen_spr_power8_pmu_user(env);
+ gen_spr_power8_tm(env);
+ gen_spr_power8_pspb(env);
+ gen_spr_vtb(env);
+ gen_spr_power8_ic(env);
+ gen_spr_power8_book4(env);
+ gen_spr_power8_rpr(env);
+ gen_spr_power9_mmu(env);
+
+ /* FIXME: Filter fields properly based on privilege level */
+ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
+ spr_read_generic, spr_write_generic,
+ KVM_REG_PPC_PSSCR, 0);
+
+ /* env variables */
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+
+ /* Allocate hardware IRQ controller */
+ init_excp_POWER10(env);
+ ppcPOWER9_irq_init(env_archcpu(env));
+}
+
+static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+ if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
+ return true;
+ }
+ return false;
+}
+
+static bool cpu_has_work_POWER10(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (cs->halted) {
+ uint64_t psscr = env->spr[SPR_PSSCR];
+
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+ return false;
+ }
+
+ /* If EC is clear, just return true on any pending interrupt */
+ if (!(psscr & PSSCR_EC)) {
+ return true;
+ }
+ /* External Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+ (env->spr[SPR_LPCR] & LPCR_EEE)) {
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ if (heic == 0 || !msr_hv || msr_pr) {
+ return true;
+ }
+ }
+ /* Decrementer Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+ (env->spr[SPR_LPCR] & LPCR_DEE)) {
+ return true;
+ }
+ /* Machine Check or Hypervisor Maintenance Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
+ 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
+ return true;
+ }
+ /* Privileged Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_PDEE)) {
+ return true;
+ }
+ /* Hypervisor Doorbell Exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
+ (env->spr[SPR_LPCR] & LPCR_HDEE)) {
+ return true;
+ }
+ /* Hypervisor virtualization exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
+ (env->spr[SPR_LPCR] & LPCR_HVEE)) {
+ return true;
+ }
+ if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+ return true;
+ }
+ return false;
+ } else {
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ }
+}
+
+POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER10";
+ dc->desc = "POWER10";
+ pcc->pvr_match = ppc_pvr_match_power10;
+ pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_3_00;
+ pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
+ pcc->init_proc = init_proc_POWER10;
+ pcc->check_pow = check_pow_nocheck;
+ cc->has_work = cpu_has_work_POWER10;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
+ PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD |
+ PPC_CILDST;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+ PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_HV) |
+ (1ull << MSR_TM) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_VSX) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
+ pcc->mmu_model = POWERPC_MMU_3_00;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
+ /* segment page size remain the same */
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
+ pcc->radix_page_info = &POWER10_radix_page_info;
+ pcc->lrg_decr_bits = 56;
+#endif
+ pcc->excp_model = POWERPC_EXCP_POWER9;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x8000;
+ pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+}
+
+#if !defined(CONFIG_USER_ONLY)
+void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
+{
+ CPUPPCState *env = &cpu->env;
+
+ cpu->vhyp = vhyp;
+
+ /*
+ * With a virtual hypervisor mode we never allow the CPU to go
+ * hypervisor mode itself
+ */
+ env->msr_mask &= ~MSR_HVB;
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+#endif /* defined(TARGET_PPC64) */
+
+/*****************************************************************************/
+/* Generic CPU instantiation routine */
+static void init_ppc_proc(PowerPCCPU *cpu)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+#if !defined(CONFIG_USER_ONLY)
+ int i;
+
+ env->irq_inputs = NULL;
+ /* Set all exception vectors to an invalid address */
+ for (i = 0; i < POWERPC_EXCP_NB; i++) {
+ env->excp_vectors[i] = (target_ulong)(-1ULL);
+ }
+ env->ivor_mask = 0x00000000;
+ env->ivpr_mask = 0x00000000;
+ /* Default MMU definitions */
+ env->nb_BATs = 0;
+ env->nb_tlb = 0;
+ env->nb_ways = 0;
+ env->tlb_type = TLB_NONE;
+#endif
+ /* Register SPR common to all PowerPC implementations */
+ gen_spr_generic(env);
+ spr_register(env, SPR_PVR, "PVR",
+ /* Linux permits userspace to read PVR */
+#if defined(CONFIG_LINUX_USER)
+ &spr_read_generic,
+#else
+ SPR_NOACCESS,
+#endif
+ SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->pvr);
+ /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
+ if (pcc->svr != POWERPC_SVR_NONE) {
+ if (pcc->svr & POWERPC_SVR_E500) {
+ spr_register(env, SPR_E500_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr & ~POWERPC_SVR_E500);
+ } else {
+ spr_register(env, SPR_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr);
+ }
+ }
+ /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
+ (*pcc->init_proc)(env);
+
+#if !defined(CONFIG_USER_ONLY)
+ ppc_gdb_gen_spr_xml(cpu);
+#endif
+
+ /* MSR bits & flags consistency checks */
+ if (env->msr_mask & (1 << 25)) {
+ switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
+ case POWERPC_FLAG_SPE:
+ case POWERPC_FLAG_VRE:
+ break;
+ default:
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
+ exit(1);
+ }
+ } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
+ exit(1);
+ }
+ if (env->msr_mask & (1 << 17)) {
+ switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
+ case POWERPC_FLAG_TGPR:
+ case POWERPC_FLAG_CE:
+ break;
+ default:
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
+ exit(1);
+ }
+ } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
+ exit(1);
+ }
+ if (env->msr_mask & (1 << 10)) {
+ switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_UBLE)) {
+ case POWERPC_FLAG_SE:
+ case POWERPC_FLAG_DWE:
+ case POWERPC_FLAG_UBLE:
+ break;
+ default:
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
+ "POWERPC_FLAG_UBLE\n");
+ exit(1);
+ }
+ } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
+ POWERPC_FLAG_UBLE)) {
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
+ "POWERPC_FLAG_UBLE\n");
+ exit(1);
+ }
+ if (env->msr_mask & (1 << 9)) {
+ switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
+ case POWERPC_FLAG_BE:
+ case POWERPC_FLAG_DE:
+ break;
+ default:
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
+ exit(1);
+ }
+ } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
+ exit(1);
+ }
+ if (env->msr_mask & (1 << 2)) {
+ switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
+ case POWERPC_FLAG_PX:
+ case POWERPC_FLAG_PMM:
+ break;
+ default:
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
+ exit(1);
+ }
+ } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
+ fprintf(stderr, "PowerPC MSR definition inconsistency\n"
+ "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
+ exit(1);
+ }
+ if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
+ fprintf(stderr, "PowerPC flags inconsistency\n"
+ "Should define the time-base and decrementer clock source\n");
+ exit(1);
+ }
+ /* Allocate TLBs buffer when needed */
+#if !defined(CONFIG_USER_ONLY)
+ if (env->nb_tlb != 0) {
+ int nb_tlb = env->nb_tlb;
+ if (env->id_tlbs != 0) {
+ nb_tlb *= 2;
+ }
+ switch (env->tlb_type) {
+ case TLB_6XX:
+ env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
+ break;
+ case TLB_EMB:
+ env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
+ break;
+ case TLB_MAS:
+ env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
+ break;
+ }
+ /* Pre-compute some useful values */
+ env->tlb_per_way = env->nb_tlb / env->nb_ways;
+ }
+ if (env->irq_inputs == NULL) {
+ warn_report("no internal IRQ controller registered."
+ " Attempt QEMU to crash very soon !");
+ }
+#endif
+ if (env->check_pow == NULL) {
+ warn_report("no power management check handler registered."
+ " Attempt QEMU to crash very soon !");
+ }
+}
+
+#if defined(PPC_DUMP_CPU)
+static void dump_ppc_sprs(CPUPPCState *env)
+{
+ ppc_spr_t *spr;
+#if !defined(CONFIG_USER_ONLY)
+ uint32_t sr, sw;
+#endif
+ uint32_t ur, uw;
+ int i, j, n;
+
+ printf("Special purpose registers:\n");
+ for (i = 0; i < 32; i++) {
+ for (j = 0; j < 32; j++) {
+ n = (i << 5) | j;
+ spr = &env->spr_cb[n];
+ uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
+ ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
+#if !defined(CONFIG_USER_ONLY)
+ sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
+ sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
+ if (sw || sr || uw || ur) {
+ printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
+ (i << 5) | j, (i << 5) | j, spr->name,
+ sw ? 'w' : '-', sr ? 'r' : '-',
+ uw ? 'w' : '-', ur ? 'r' : '-');
+ }
+#else
+ if (uw || ur) {
+ printf("SPR: %4d (%03x) %-8s u%c%c\n",
+ (i << 5) | j, (i << 5) | j, spr->name,
+ uw ? 'w' : '-', ur ? 'r' : '-');
+ }
+#endif
+ }
+ }
+ fflush(stdout);
+ fflush(stderr);
+}
+#endif
+
+/*****************************************************************************/
+
+/* Opcode types */
+enum {
+ PPC_DIRECT = 0, /* Opcode routine */
+ PPC_INDIRECT = 1, /* Indirect opcode table */
+};
+
+#define PPC_OPCODE_MASK 0x3
+
+static inline int is_indirect_opcode(void *handler)
+{
+ return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
+}
+
+static inline opc_handler_t **ind_table(void *handler)
+{
+ return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
+}
+
+/* Instruction table creation */
+/* Opcodes tables creation */
+static void fill_new_table(opc_handler_t **table, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ table[i] = &invalid_handler;
+ }
+}
+
+static int create_new_table(opc_handler_t **table, unsigned char idx)
+{
+ opc_handler_t **tmp;
+
+ tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
+ fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
+ table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
+
+ return 0;
+}
+
+static int insert_in_table(opc_handler_t **table, unsigned char idx,
+ opc_handler_t *handler)
+{
+ if (table[idx] != &invalid_handler) {
+ return -1;
+ }
+ table[idx] = handler;
+
+ return 0;
+}
+
+static int register_direct_insn(opc_handler_t **ppc_opcodes,
+ unsigned char idx, opc_handler_t *handler)
+{
+ if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
+ printf("*** ERROR: opcode %02x already assigned in main "
+ "opcode table\n", idx);
+#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
+ printf(" Registered handler '%s' - new handler '%s'\n",
+ ppc_opcodes[idx]->oname, handler->oname);
+#endif
+ return -1;
+ }
+
+ return 0;
+}
+
+static int register_ind_in_table(opc_handler_t **table,
+ unsigned char idx1, unsigned char idx2,
+ opc_handler_t *handler)
+{
+ if (table[idx1] == &invalid_handler) {
+ if (create_new_table(table, idx1) < 0) {
+ printf("*** ERROR: unable to create indirect table "
+ "idx=%02x\n", idx1);
+ return -1;
+ }
+ } else {
+ if (!is_indirect_opcode(table[idx1])) {
+ printf("*** ERROR: idx %02x already assigned to a direct "
+ "opcode\n", idx1);
+#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
+ printf(" Registered handler '%s' - new handler '%s'\n",
+ ind_table(table[idx1])[idx2]->oname, handler->oname);
+#endif
+ return -1;
+ }
+ }
+ if (handler != NULL &&
+ insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
+ printf("*** ERROR: opcode %02x already assigned in "
+ "opcode table %02x\n", idx2, idx1);
+#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
+ printf(" Registered handler '%s' - new handler '%s'\n",
+ ind_table(table[idx1])[idx2]->oname, handler->oname);
+#endif
+ return -1;
+ }
+
+ return 0;
+}
+
+static int register_ind_insn(opc_handler_t **ppc_opcodes,
+ unsigned char idx1, unsigned char idx2,
+ opc_handler_t *handler)
+{
+ return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
+}
+
+static int register_dblind_insn(opc_handler_t **ppc_opcodes,
+ unsigned char idx1, unsigned char idx2,
+ unsigned char idx3, opc_handler_t *handler)
+{
+ if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
+ printf("*** ERROR: unable to join indirect table idx "
+ "[%02x-%02x]\n", idx1, idx2);
+ return -1;
+ }
+ if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
+ handler) < 0) {
+ printf("*** ERROR: unable to insert opcode "
+ "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int register_trplind_insn(opc_handler_t **ppc_opcodes,
+ unsigned char idx1, unsigned char idx2,
+ unsigned char idx3, unsigned char idx4,
+ opc_handler_t *handler)
+{
+ opc_handler_t **table;
+
+ if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
+ printf("*** ERROR: unable to join indirect table idx "
+ "[%02x-%02x]\n", idx1, idx2);
+ return -1;
+ }
+ table = ind_table(ppc_opcodes[idx1]);
+ if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
+ printf("*** ERROR: unable to join 2nd-level indirect table idx "
+ "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
+ return -1;
+ }
+ table = ind_table(table[idx2]);
+ if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
+ printf("*** ERROR: unable to insert opcode "
+ "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
+ return -1;
+ }
+ return 0;
+}
+static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
+{
+ if (insn->opc2 != 0xFF) {
+ if (insn->opc3 != 0xFF) {
+ if (insn->opc4 != 0xFF) {
+ if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
+ insn->opc3, insn->opc4,
+ &insn->handler) < 0) {
+ return -1;
+ }
+ } else {
+ if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
+ insn->opc3, &insn->handler) < 0) {
+ return -1;
+ }
+ }
+ } else {
+ if (register_ind_insn(ppc_opcodes, insn->opc1,
+ insn->opc2, &insn->handler) < 0) {
+ return -1;
+ }
+ }
+ } else {
+ if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int test_opcode_table(opc_handler_t **table, int len)
+{
+ int i, count, tmp;
+
+ for (i = 0, count = 0; i < len; i++) {
+ /* Consistency fixup */
+ if (table[i] == NULL) {
+ table[i] = &invalid_handler;
+ }
+ if (table[i] != &invalid_handler) {
+ if (is_indirect_opcode(table[i])) {
+ tmp = test_opcode_table(ind_table(table[i]),
+ PPC_CPU_INDIRECT_OPCODES_LEN);
+ if (tmp == 0) {
+ free(table[i]);
+ table[i] = &invalid_handler;
+ } else {
+ count++;
+ }
+ } else {
+ count++;
+ }
+ }
+ }
+
+ return count;
+}
+
+static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
+{
+ if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
+ printf("*** WARNING: no opcode defined !\n");
+ }
+}
+
+/*****************************************************************************/
+static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ opcode_t *opc;
+
+ fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
+ for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
+ if (((opc->handler.type & pcc->insns_flags) != 0) ||
+ ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
+ if (register_insn(cpu->opcodes, opc) < 0) {
+ error_setg(errp, "ERROR initializing PowerPC instruction "
+ "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
+ opc->opc3);
+ return;
+ }
+ }
+ }
+ fix_opcode_tables(cpu->opcodes);
+ fflush(stdout);
+ fflush(stderr);
+}
+
+#if defined(PPC_DUMP_CPU)
+static void dump_ppc_insns(CPUPPCState *env)
+{
+ opc_handler_t **table, *handler;
+ const char *p, *q;
+ uint8_t opc1, opc2, opc3, opc4;
+
+ printf("Instructions set:\n");
+ /* opc1 is 6 bits long */
+ for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
+ table = env->opcodes;
+ handler = table[opc1];
+ if (is_indirect_opcode(handler)) {
+ /* opc2 is 5 bits long */
+ for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
+ table = env->opcodes;
+ handler = env->opcodes[opc1];
+ table = ind_table(handler);
+ handler = table[opc2];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ /* opc3 is 5 bits long */
+ for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
+ opc3++) {
+ handler = table[opc3];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ /* opc4 is 5 bits long */
+ for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
+ opc4++) {
+ handler = table[opc4];
+ if (handler->handler != &gen_invalid) {
+ printf("INSN: %02x %02x %02x %02x -- "
+ "(%02d %04d %02d) : %s\n",
+ opc1, opc2, opc3, opc4,
+ opc1, (opc3 << 5) | opc2, opc4,
+ handler->oname);
+ }
+ }
+ } else {
+ if (handler->handler != &gen_invalid) {
+ /* Special hack to properly dump SPE insns */
+ p = strchr(handler->oname, '_');
+ if (p == NULL) {
+ printf("INSN: %02x %02x %02x (%02d %04d) : "
+ "%s\n",
+ opc1, opc2, opc3, opc1,
+ (opc3 << 5) | opc2,
+ handler->oname);
+ } else {
+ q = "speundef";
+ if ((p - handler->oname) != strlen(q)
+ || (memcmp(handler->oname, q, strlen(q))
+ != 0)) {
+ /* First instruction */
+ printf("INSN: %02x %02x %02x"
+ "(%02d %04d) : %.*s\n",
+ opc1, opc2 << 1, opc3, opc1,
+ (opc3 << 6) | (opc2 << 1),
+ (int)(p - handler->oname),
+ handler->oname);
+ }
+ if (strcmp(p + 1, q) != 0) {
+ /* Second instruction */
+ printf("INSN: %02x %02x %02x "
+ "(%02d %04d) : %s\n", opc1,
+ (opc2 << 1) | 1, opc3, opc1,
+ (opc3 << 6) | (opc2 << 1) | 1,
+ p + 1);
+ }
+ }
+ }
+ }
+ }
+ } else {
+ if (handler->handler != &gen_invalid) {
+ printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
+ opc1, opc2, opc1, opc2, handler->oname);
+ }
+ }
+ }
+ } else {
+ if (handler->handler != &gen_invalid) {
+ printf("INSN: %02x -- -- (%02d ----) : %s\n",
+ opc1, opc1, handler->oname);
+ }
+ }
+ }
+}
+#endif
+
+static bool avr_need_swap(CPUPPCState *env)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+ return msr_le;
+#else
+ return !msr_le;
+#endif
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static int gdb_find_spr_idx(CPUPPCState *env, int n)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
+ ppc_spr_t *spr = &env->spr_cb[i];
+
+ if (spr->name && spr->gdb_id == n) {
+ return i;
+ }
+ }
+ return -1;
+}
+
+static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
+{
+ int reg;
+ int len;
+
+ reg = gdb_find_spr_idx(env, n);
+ if (reg < 0) {
+ return 0;
+ }
+
+ len = TARGET_LONG_SIZE;
+ gdb_get_regl(buf, env->spr[reg]);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
+ return len;
+}
+
+static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ int reg;
+ int len;
+
+ reg = gdb_find_spr_idx(env, n);
+ if (reg < 0) {
+ return 0;
+ }
+
+ len = TARGET_LONG_SIZE;
+ ppc_maybe_bswap_register(env, mem_buf, len);
+ env->spr[reg] = ldn_p(mem_buf, len);
+
+ return len;
+}
+#endif
+
+static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
+{
+ uint8_t *mem_buf;
+ if (n < 32) {
+ gdb_get_float64(buf, *cpu_fpr_ptr(env, n));
+ mem_buf = gdb_get_reg_ptr(buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ return 8;
+ }
+ if (n == 32) {
+ gdb_get_reg32(buf, env->fpscr);
+ mem_buf = gdb_get_reg_ptr(buf, 4);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf);
+ return 8;
+ }
+ if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
+{
+ uint8_t *mem_buf;
+
+ if (n < 32) {
+ ppc_avr_t *avr = cpu_avr_ptr(env, n);
+ if (!avr_need_swap(env)) {
+ gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
+ } else {
+ gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
+ }
+ mem_buf = gdb_get_reg_ptr(buf, 16);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf + 8, 8);
+ return 16;
+ }
+ if (n == 32) {
+ gdb_get_reg32(buf, helper_mfvscr(env));
+ mem_buf = gdb_get_reg_ptr(buf, 4);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ return 4;
+ }
+ if (n == 33) {
+ gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
+ mem_buf = gdb_get_reg_ptr(buf, 4);
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ ppc_avr_t *avr = cpu_avr_ptr(env, n);
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ ppc_maybe_bswap_register(env, mem_buf + 8, 8);
+ if (!avr_need_swap(env)) {
+ avr->u64[0] = ldq_p(mem_buf);
+ avr->u64[1] = ldq_p(mem_buf + 8);
+ } else {
+ avr->u64[1] = ldq_p(mem_buf);
+ avr->u64[0] = ldq_p(mem_buf + 8);
+ }
+ return 16;
+ }
+ if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ helper_mtvscr(env, ldl_p(mem_buf));
+ return 4;
+ }
+ if (n == 33) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
+{
+ if (n < 32) {
+#if defined(TARGET_PPC64)
+ gdb_get_reg32(buf, env->gpr[n] >> 32);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
+#else
+ gdb_get_reg32(buf, env->gprh[n]);
+#endif
+ return 4;
+ }
+ if (n == 32) {
+ gdb_get_reg64(buf, env->spe_acc);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
+ return 8;
+ }
+ if (n == 33) {
+ gdb_get_reg32(buf, env->spe_fscr);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+#if defined(TARGET_PPC64)
+ target_ulong lo = (uint32_t)env->gpr[n];
+ target_ulong hi;
+
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+
+ hi = (target_ulong)ldl_p(mem_buf) << 32;
+ env->gpr[n] = lo | hi;
+#else
+ env->gprh[n] = ldl_p(mem_buf);
+#endif
+ return 4;
+ }
+ if (n == 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ env->spe_acc = ldq_p(mem_buf);
+ return 8;
+ }
+ if (n == 33) {
+ ppc_maybe_bswap_register(env, mem_buf, 4);
+ env->spe_fscr = ldl_p(mem_buf);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
+{
+ if (n < 32) {
+ gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
+ return 8;
+ }
+ return 0;
+}
+
+static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ ppc_maybe_bswap_register(env, mem_buf, 8);
+ *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
+ return 8;
+ }
+ return 0;
+}
+
+static int ppc_fixup_cpu(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ /*
+ * TCG doesn't (yet) emulate some groups of instructions that are
+ * implemented on some otherwise supported CPUs (e.g. VSX and
+ * decimal floating point instructions on POWER7). We remove
+ * unsupported instruction groups from the cpu state's instruction
+ * masks and hope the guest can cope. For at least the pseries
+ * machine, the unavailability of these instructions can be
+ * advertised to the guest via the device tree.
+ */
+ if ((env->insns_flags & ~PPC_TCG_INSNS)
+ || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
+ warn_report("Disabling some instructions which are not "
+ "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
+ env->insns_flags & ~PPC_TCG_INSNS,
+ env->insns_flags2 & ~PPC_TCG_INSNS2);
+ }
+ env->insns_flags &= PPC_TCG_INSNS;
+ env->insns_flags2 &= PPC_TCG_INSNS2;
+ return 0;
+}
+
+static void ppc_cpu_realize(DeviceState *dev, Error **errp)
+{
+ CPUState *cs = CPU(dev);
+ PowerPCCPU *cpu = POWERPC_CPU(dev);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ Error *local_err = NULL;
+
+ cpu_exec_realizefn(cs, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
+ cpu->vcpu_id = cs->cpu_index;
+ }
+
+ if (tcg_enabled()) {
+ if (ppc_fixup_cpu(cpu) != 0) {
+ error_setg(errp, "Unable to emulate selected CPU with TCG");
+ goto unrealize;
+ }
+ }
+
+ create_ppc_opcodes(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ goto unrealize;
+ }
+ init_ppc_proc(cpu);
+
+ if (pcc->insns_flags & PPC_FLOAT) {
+ gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
+ 33, "power-fpu.xml", 0);
+ }
+ if (pcc->insns_flags & PPC_ALTIVEC) {
+ gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
+ 34, "power-altivec.xml", 0);
+ }
+ if (pcc->insns_flags & PPC_SPE) {
+ gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
+ 34, "power-spe.xml", 0);
+ }
+ if (pcc->insns_flags2 & PPC2_VSX) {
+ gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
+ 32, "power-vsx.xml", 0);
+ }
+#ifndef CONFIG_USER_ONLY
+ gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
+ pcc->gdb_num_sprs, "power-spr.xml", 0);
+#endif
+ qemu_init_vcpu(cs);
+
+ pcc->parent_realize(dev, errp);
+
+#if defined(PPC_DUMP_CPU)
+ {
+ CPUPPCState *env = &cpu->env;
+ const char *mmu_model, *excp_model, *bus_model;
+ switch (env->mmu_model) {
+ case POWERPC_MMU_32B:
+ mmu_model = "PowerPC 32";
+ break;
+ case POWERPC_MMU_SOFT_6xx:
+ mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
+ break;
+ case POWERPC_MMU_SOFT_74xx:
+ mmu_model = "PowerPC 74xx with software driven TLBs";
+ break;
+ case POWERPC_MMU_SOFT_4xx:
+ mmu_model = "PowerPC 4xx with software driven TLBs";
+ break;
+ case POWERPC_MMU_SOFT_4xx_Z:
+ mmu_model = "PowerPC 4xx with software driven TLBs "
+ "and zones protections";
+ break;
+ case POWERPC_MMU_REAL:
+ mmu_model = "PowerPC real mode only";
+ break;
+ case POWERPC_MMU_MPC8xx:
+ mmu_model = "PowerPC MPC8xx";
+ break;
+ case POWERPC_MMU_BOOKE:
+ mmu_model = "PowerPC BookE";
+ break;
+ case POWERPC_MMU_BOOKE206:
+ mmu_model = "PowerPC BookE 2.06";
+ break;
+ case POWERPC_MMU_601:
+ mmu_model = "PowerPC 601";
+ break;
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ mmu_model = "PowerPC 64";
+ break;
+#endif
+ default:
+ mmu_model = "Unknown or invalid";
+ break;
+ }
+ switch (env->excp_model) {
+ case POWERPC_EXCP_STD:
+ excp_model = "PowerPC";
+ break;
+ case POWERPC_EXCP_40x:
+ excp_model = "PowerPC 40x";
+ break;
+ case POWERPC_EXCP_601:
+ excp_model = "PowerPC 601";
+ break;
+ case POWERPC_EXCP_602:
+ excp_model = "PowerPC 602";
+ break;
+ case POWERPC_EXCP_603:
+ excp_model = "PowerPC 603";
+ break;
+ case POWERPC_EXCP_603E:
+ excp_model = "PowerPC 603e";
+ break;
+ case POWERPC_EXCP_604:
+ excp_model = "PowerPC 604";
+ break;
+ case POWERPC_EXCP_7x0:
+ excp_model = "PowerPC 740/750";
+ break;
+ case POWERPC_EXCP_7x5:
+ excp_model = "PowerPC 745/755";
+ break;
+ case POWERPC_EXCP_74xx:
+ excp_model = "PowerPC 74xx";
+ break;
+ case POWERPC_EXCP_BOOKE:
+ excp_model = "PowerPC BookE";
+ break;
+#if defined(TARGET_PPC64)
+ case POWERPC_EXCP_970:
+ excp_model = "PowerPC 970";
+ break;
+#endif
+ default:
+ excp_model = "Unknown or invalid";
+ break;
+ }
+ switch (env->bus_model) {
+ case PPC_FLAGS_INPUT_6xx:
+ bus_model = "PowerPC 6xx";
+ break;
+ case PPC_FLAGS_INPUT_BookE:
+ bus_model = "PowerPC BookE";
+ break;
+ case PPC_FLAGS_INPUT_405:
+ bus_model = "PowerPC 405";
+ break;
+ case PPC_FLAGS_INPUT_401:
+ bus_model = "PowerPC 401/403";
+ break;
+ case PPC_FLAGS_INPUT_RCPU:
+ bus_model = "RCPU / MPC8xx";
+ break;
+#if defined(TARGET_PPC64)
+ case PPC_FLAGS_INPUT_970:
+ bus_model = "PowerPC 970";
+ break;
+#endif
+ default:
+ bus_model = "Unknown or invalid";
+ break;
+ }
+ printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
+ " MMU model : %s\n",
+ object_class_get_name(OBJECT_CLASS(pcc)),
+ pcc->pvr, pcc->msr_mask, mmu_model);
+#if !defined(CONFIG_USER_ONLY)
+ if (env->tlb.tlb6) {
+ printf(" %d %s TLB in %d ways\n",
+ env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
+ env->nb_ways);
+ }
+#endif
+ printf(" Exceptions model : %s\n"
+ " Bus model : %s\n",
+ excp_model, bus_model);
+ printf(" MSR features :\n");
+ if (env->flags & POWERPC_FLAG_SPE) {
+ printf(" signal processing engine enable"
+ "\n");
+ } else if (env->flags & POWERPC_FLAG_VRE) {
+ printf(" vector processor enable\n");
+ }
+ if (env->flags & POWERPC_FLAG_TGPR) {
+ printf(" temporary GPRs\n");
+ } else if (env->flags & POWERPC_FLAG_CE) {
+ printf(" critical input enable\n");
+ }
+ if (env->flags & POWERPC_FLAG_SE) {
+ printf(" single-step trace mode\n");
+ } else if (env->flags & POWERPC_FLAG_DWE) {
+ printf(" debug wait enable\n");
+ } else if (env->flags & POWERPC_FLAG_UBLE) {
+ printf(" user BTB lock enable\n");
+ }
+ if (env->flags & POWERPC_FLAG_BE) {
+ printf(" branch-step trace mode\n");
+ } else if (env->flags & POWERPC_FLAG_DE) {
+ printf(" debug interrupt enable\n");
+ }
+ if (env->flags & POWERPC_FLAG_PX) {
+ printf(" inclusive protection\n");
+ } else if (env->flags & POWERPC_FLAG_PMM) {
+ printf(" performance monitor mark\n");
+ }
+ if (env->flags == POWERPC_FLAG_NONE) {
+ printf(" none\n");
+ }
+ printf(" Time-base/decrementer clock source: %s\n",
+ env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
+ dump_ppc_insns(env);
+ dump_ppc_sprs(env);
+ fflush(stdout);
+ }
+#endif
+ return;
+
+unrealize:
+ cpu_exec_unrealizefn(cs);
+}
+
+static void ppc_cpu_unrealize(DeviceState *dev)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(dev);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ opc_handler_t **table, **table_2;
+ int i, j, k;
+
+ pcc->parent_unrealize(dev);
+
+ for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
+ if (cpu->opcodes[i] == &invalid_handler) {
+ continue;
+ }
+ if (is_indirect_opcode(cpu->opcodes[i])) {
+ table = ind_table(cpu->opcodes[i]);
+ for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
+ if (table[j] == &invalid_handler) {
+ continue;
+ }
+ if (is_indirect_opcode(table[j])) {
+ table_2 = ind_table(table[j]);
+ for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
+ if (table_2[k] != &invalid_handler &&
+ is_indirect_opcode(table_2[k])) {
+ g_free((opc_handler_t *)((uintptr_t)table_2[k] &
+ ~PPC_INDIRECT));
+ }
+ }
+ g_free((opc_handler_t *)((uintptr_t)table[j] &
+ ~PPC_INDIRECT));
+ }
+ }
+ g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
+ ~PPC_INDIRECT));
+ }
+ }
+}
+
+static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *oc = (ObjectClass *)a;
+ uint32_t pvr = *(uint32_t *)b;
+ PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
+
+ /* -cpu host does a PVR lookup during construction */
+ if (unlikely(strcmp(object_class_get_name(oc),
+ TYPE_HOST_POWERPC_CPU) == 0)) {
+ return -1;
+ }
+
+ return pcc->pvr == pvr ? 0 : -1;
+}
+
+PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
+{
+ GSList *list, *item;
+ PowerPCCPUClass *pcc = NULL;
+
+ list = object_class_get_list(TYPE_POWERPC_CPU, false);
+ item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
+ if (item != NULL) {
+ pcc = POWERPC_CPU_CLASS(item->data);
+ }
+ g_slist_free(list);
+
+ return pcc;
+}
+
+static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *oc = (ObjectClass *)a;
+ uint32_t pvr = *(uint32_t *)b;
+ PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
+
+ /* -cpu host does a PVR lookup during construction */
+ if (unlikely(strcmp(object_class_get_name(oc),
+ TYPE_HOST_POWERPC_CPU) == 0)) {
+ return -1;
+ }
+
+ if (pcc->pvr_match(pcc, pvr)) {
+ return 0;
+ }
+
+ return -1;
+}
+
+PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
+{
+ GSList *list, *item;
+ PowerPCCPUClass *pcc = NULL;
+
+ list = object_class_get_list(TYPE_POWERPC_CPU, true);
+ item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
+ if (item != NULL) {
+ pcc = POWERPC_CPU_CLASS(item->data);
+ }
+ g_slist_free(list);
+
+ return pcc;
+}
+
+static const char *ppc_cpu_lookup_alias(const char *alias)
+{
+ int ai;
+
+ for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
+ if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
+ return ppc_cpu_aliases[ai].model;
+ }
+ }
+
+ return NULL;
+}
+
+static ObjectClass *ppc_cpu_class_by_name(const char *name)
+{
+ char *cpu_model, *typename;
+ ObjectClass *oc;
+ const char *p;
+ unsigned long pvr;
+
+ /*
+ * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
+ * 0x prefix if present)
+ */
+ if (!qemu_strtoul(name, &p, 16, &pvr)) {
+ int len = p - name;
+ len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
+ if ((len == 8) && (*p == '\0')) {
+ return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
+ }
+ }
+
+ cpu_model = g_ascii_strdown(name, -1);
+ p = ppc_cpu_lookup_alias(cpu_model);
+ if (p) {
+ g_free(cpu_model);
+ cpu_model = g_strdup(p);
+ }
+
+ typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ g_free(cpu_model);
+
+ return oc;
+}
+
+static void ppc_cpu_parse_featurestr(const char *type, char *features,
+ Error **errp)
+{
+ Object *machine = qdev_get_machine();
+ const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type));
+
+ if (!features) {
+ return;
+ }
+
+ if (object_property_find(machine, "max-cpu-compat", NULL)) {
+ int i;
+ char **inpieces;
+ char *s = features;
+ Error *local_err = NULL;
+ char *compat_str = NULL;
+
+ /*
+ * Backwards compatibility hack:
+ *
+ * CPUs had a "compat=" property which didn't make sense for
+ * anything except pseries. It was replaced by "max-cpu-compat"
+ * machine option. This supports old command lines like
+ * -cpu POWER8,compat=power7
+ * By stripping the compat option and applying it to the machine
+ * before passing it on to the cpu level parser.
+ */
+ inpieces = g_strsplit(features, ",", 0);
+ *s = '\0';
+ for (i = 0; inpieces[i]; i++) {
+ if (g_str_has_prefix(inpieces[i], "compat=")) {
+ warn_report_once("CPU 'compat' property is deprecated; "
+ "use max-cpu-compat machine property instead");
+ compat_str = inpieces[i];
+ continue;
+ }
+ if ((i != 0) && (s != features)) {
+ s = g_stpcpy(s, ",");
+ }
+ s = g_stpcpy(s, inpieces[i]);
+ }
+
+ if (compat_str) {
+ char *v = compat_str + strlen("compat=");
+ object_property_set_str(machine, "max-cpu-compat", v, &local_err);
+ }
+ g_strfreev(inpieces);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ }
+
+ /* do property processing with generic handler */
+ pcc->parent_parse_features(type, features, errp);
+}
+
+PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
+{
+ ObjectClass *oc = OBJECT_CLASS(pcc);
+
+ while (oc && !object_class_is_abstract(oc)) {
+ oc = object_class_get_parent(oc);
+ }
+ assert(oc);
+
+ return POWERPC_CPU_CLASS(oc);
+}
+
+/* Sort by PVR, ordering special case "host" last. */
+static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *oc_a = (ObjectClass *)a;
+ ObjectClass *oc_b = (ObjectClass *)b;
+ PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
+ PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
+ const char *name_a = object_class_get_name(oc_a);
+ const char *name_b = object_class_get_name(oc_b);
+
+ if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
+ return 1;
+ } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
+ return -1;
+ } else {
+ /* Avoid an integer overflow during subtraction */
+ if (pcc_a->pvr < pcc_b->pvr) {
+ return -1;
+ } else if (pcc_a->pvr > pcc_b->pvr) {
+ return 1;
+ } else {
+ return 0;
+ }
+ }
+}
+
+static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
+ const char *typename = object_class_get_name(oc);
+ char *name;
+ int i;
+
+ if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
+ return;
+ }
+
+ name = g_strndup(typename,
+ strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
+ qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
+ for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
+ PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
+ ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
+
+ if (alias_oc != oc) {
+ continue;
+ }
+ /*
+ * If running with KVM, we might update the family alias later, so
+ * avoid printing the wrong alias here and use "preferred" instead
+ */
+ if (strcmp(alias->alias, family->desc) == 0) {
+ qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
+ alias->alias, family->desc);
+ } else {
+ qemu_printf("PowerPC %-16s (alias for %s)\n",
+ alias->alias, name);
+ }
+ }
+ g_free(name);
+}
+
+void ppc_cpu_list(void)
+{
+ GSList *list;
+
+ list = object_class_get_list(TYPE_POWERPC_CPU, false);
+ list = g_slist_sort(list, ppc_cpu_list_compare);
+ g_slist_foreach(list, ppc_cpu_list_entry, NULL);
+ g_slist_free(list);
+
+#ifdef CONFIG_KVM
+ qemu_printf("\n");
+ qemu_printf("PowerPC %-16s\n", "host");
+#endif
+}
+
+static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **first = user_data;
+ const char *typename;
+ CpuDefinitionInfoList *entry;
+ CpuDefinitionInfo *info;
+
+ typename = object_class_get_name(oc);
+ info = g_malloc0(sizeof(*info));
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
+
+ entry = g_malloc0(sizeof(*entry));
+ entry->value = info;
+ entry->next = *first;
+ *first = entry;
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list;
+ int i;
+
+ list = object_class_get_list(TYPE_POWERPC_CPU, false);
+ g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
+ g_slist_free(list);
+
+ for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
+ PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
+ ObjectClass *oc;
+ CpuDefinitionInfoList *entry;
+ CpuDefinitionInfo *info;
+
+ oc = ppc_cpu_class_by_name(alias->model);
+ if (oc == NULL) {
+ continue;
+ }
+
+ info = g_malloc0(sizeof(*info));
+ info->name = g_strdup(alias->alias);
+ info->q_typename = g_strdup(object_class_get_name(oc));
+
+ entry = g_malloc0(sizeof(*entry));
+ entry->value = info;
+ entry->next = cpu_list;
+ cpu_list = entry;
+ }
+
+ return cpu_list;
+}
+
+static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ cpu->env.nip = value;
+}
+
+static bool ppc_cpu_has_work(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+}
+
+static void ppc_cpu_reset(DeviceState *dev)
+{
+ CPUState *s = CPU(dev);
+ PowerPCCPU *cpu = POWERPC_CPU(s);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+ target_ulong msr;
+ int i;
+
+ pcc->parent_reset(dev);
+
+ msr = (target_ulong)0;
+ msr |= (target_ulong)MSR_HVB;
+ msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
+ msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
+ msr |= (target_ulong)1 << MSR_EP;
+#if defined(DO_SINGLE_STEP) && 0
+ /* Single step trace mode */
+ msr |= (target_ulong)1 << MSR_SE;
+ msr |= (target_ulong)1 << MSR_BE;
+#endif
+#if defined(CONFIG_USER_ONLY)
+ msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
+ msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
+ msr |= (target_ulong)1 << MSR_FE1;
+ msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
+ msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
+ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
+ msr |= (target_ulong)1 << MSR_PR;
+#if defined(TARGET_PPC64)
+ msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
+#endif
+#if !defined(TARGET_WORDS_BIGENDIAN)
+ msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
+ if (!((env->msr_mask >> MSR_LE) & 1)) {
+ fprintf(stderr, "Selected CPU does not support little-endian.\n");
+ exit(1);
+ }
+#endif
+#endif
+
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64) {
+ msr |= (1ULL << MSR_SF);
+ }
+#endif
+
+ hreg_store_msr(env, msr, 1);
+
+#if !defined(CONFIG_USER_ONLY)
+ env->nip = env->hreset_vector | env->excp_prefix;
+ if (env->mmu_model != POWERPC_MMU_REAL) {
+ ppc_tlb_invalidate_all(env);
+ }
+#endif
+
+ hreg_compute_hflags(env);
+ env->reserve_addr = (target_ulong)-1ULL;
+ /* Be sure no exception or interrupt is pending */
+ env->pending_interrupts = 0;
+ s->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ ppc_irq_reset(cpu);
+
+ /* tininess for underflow is detected before rounding */
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->fp_status);
+
+ for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
+ ppc_spr_t *spr = &env->spr_cb[i];
+
+ if (!spr->name) {
+ continue;
+ }
+ env->spr[i] = spr->default_value;
+ }
+}
+
+#ifndef CONFIG_USER_ONLY
+static bool ppc_cpu_is_big_endian(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ cpu_synchronize_state(cs);
+
+ return !msr_le;
+}
+
+static void ppc_cpu_exec_enter(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ if (cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->cpu_exec_enter(cpu->vhyp, cpu);
+ }
+}
+
+static void ppc_cpu_exec_exit(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ if (cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->cpu_exec_exit(cpu->vhyp, cpu);
+ }
+}
+#endif
+
+static void ppc_cpu_instance_init(Object *obj)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ cpu_set_cpustate_pointers(cpu);
+ cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
+
+ env->msr_mask = pcc->msr_mask;
+ env->mmu_model = pcc->mmu_model;
+ env->excp_model = pcc->excp_model;
+ env->bus_model = pcc->bus_model;
+ env->insns_flags = pcc->insns_flags;
+ env->insns_flags2 = pcc->insns_flags2;
+ env->flags = pcc->flags;
+ env->bfd_mach = pcc->bfd_mach;
+ env->check_pow = pcc->check_pow;
+
+ /*
+ * Mark HV mode as supported if the CPU has an MSR_HV bit in the
+ * msr_mask. The mask can later be cleared by PAPR mode but the hv
+ * mode support will remain, thus enforcing that we cannot use
+ * priv. instructions in guest in PAPR mode. For 970 we currently
+ * simply don't set HV in msr_mask thus simulating an "Apple mode"
+ * 970. If we ever want to support 970 HV mode, we'll have to add
+ * a processor attribute of some sort.
+ */
+#if !defined(CONFIG_USER_ONLY)
+ env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
+#endif
+
+ ppc_hash64_init(cpu);
+}
+
+static void ppc_cpu_instance_finalize(Object *obj)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+
+ ppc_hash64_finalize(cpu);
+}
+
+static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+ return pcc->pvr == pvr;
+}
+
+static gchar *ppc_gdb_arch_name(CPUState *cs)
+{
+#if defined(TARGET_PPC64)
+ return g_strdup("powerpc:common64");
+#else
+ return g_strdup("powerpc:common");
+#endif
+}
+
+static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if ((env->hflags >> MSR_LE) & 1) {
+ info->endian = BFD_ENDIAN_LITTLE;
+ }
+ info->mach = env->bfd_mach;
+ if (!env->bfd_mach) {
+#ifdef TARGET_PPC64
+ info->mach = bfd_mach_ppc64;
+#else
+ info->mach = bfd_mach_ppc;
+#endif
+ }
+ info->disassembler_options = (char *)"any";
+ info->print_insn = print_insn_ppc;
+
+ info->cap_arch = CS_ARCH_PPC;
+#ifdef TARGET_PPC64
+ info->cap_mode = CS_MODE_64;
+#endif
+}
+
+static Property ppc_cpu_properties[] = {
+ DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
+ DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
+ false),
+ DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
+ false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc_cpu_class_init(ObjectClass *oc, void *data)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ device_class_set_parent_realize(dc, ppc_cpu_realize,
+ &pcc->parent_realize);
+ device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
+ &pcc->parent_unrealize);
+ pcc->pvr_match = ppc_pvr_match_default;
+ pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
+ device_class_set_props(dc, ppc_cpu_properties);
+
+ device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
+
+ cc->class_by_name = ppc_cpu_class_by_name;
+ pcc->parent_parse_features = cc->parse_features;
+ cc->parse_features = ppc_cpu_parse_featurestr;
+ cc->has_work = ppc_cpu_has_work;
+ cc->do_interrupt = ppc_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
+ cc->dump_state = ppc_cpu_dump_state;
+ cc->dump_statistics = ppc_cpu_dump_statistics;
+ cc->set_pc = ppc_cpu_set_pc;
+ cc->gdb_read_register = ppc_cpu_gdb_read_register;
+ cc->gdb_write_register = ppc_cpu_gdb_write_register;
+ cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
+#ifndef CONFIG_USER_ONLY
+ cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
+ cc->vmsd = &vmstate_ppc_cpu;
+#endif
+#if defined(CONFIG_SOFTMMU)
+ cc->write_elf64_note = ppc64_cpu_write_elf64_note;
+ cc->write_elf32_note = ppc32_cpu_write_elf32_note;
+#endif
+
+ cc->gdb_num_core_regs = 71;
+#ifndef CONFIG_USER_ONLY
+ cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
+#endif
+#ifdef USE_APPLE_GDB
+ cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
+ cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
+ cc->gdb_num_core_regs = 71 + 32;
+#endif
+
+ cc->gdb_arch_name = ppc_gdb_arch_name;
+#if defined(TARGET_PPC64)
+ cc->gdb_core_xml_file = "power64-core.xml";
+#else
+ cc->gdb_core_xml_file = "power-core.xml";
+#endif
+#ifndef CONFIG_USER_ONLY
+ cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
+#endif
+#ifdef CONFIG_TCG
+ cc->tcg_initialize = ppc_translate_init;
+ cc->tlb_fill = ppc_cpu_tlb_fill;
+#endif
+#ifndef CONFIG_USER_ONLY
+ cc->cpu_exec_enter = ppc_cpu_exec_enter;
+ cc->cpu_exec_exit = ppc_cpu_exec_exit;
+#endif
+
+ cc->disas_set_info = ppc_disas_set_info;
+
+ dc->fw_name = "PowerPC,UNKNOWN";
+}
+
+static const TypeInfo ppc_cpu_type_info = {
+ .name = TYPE_POWERPC_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(PowerPCCPU),
+ .instance_init = ppc_cpu_instance_init,
+ .instance_finalize = ppc_cpu_instance_finalize,
+ .abstract = true,
+ .class_size = sizeof(PowerPCCPUClass),
+ .class_init = ppc_cpu_class_init,
+};
+
+#ifndef CONFIG_USER_ONLY
+static const TypeInfo ppc_vhyp_type_info = {
+ .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(PPCVirtualHypervisorClass),
+};
+#endif
+
+static void ppc_cpu_register_types(void)
+{
+ type_register_static(&ppc_cpu_type_info);
+#ifndef CONFIG_USER_ONLY
+ type_register_static(&ppc_vhyp_type_info);
+#endif
+}
+
+type_init(ppc_cpu_register_types)
+++ /dev/null
-/*
- * PowerPC CPU initialization for qemu.
- *
- * Copyright (c) 2003-2007 Jocelyn Mayer
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "disas/dis-asm.h"
-#include "exec/gdbstub.h"
-#include "kvm_ppc.h"
-#include "sysemu/arch_init.h"
-#include "sysemu/cpus.h"
-#include "sysemu/hw_accel.h"
-#include "sysemu/tcg.h"
-#include "cpu-models.h"
-#include "mmu-hash32.h"
-#include "mmu-hash64.h"
-#include "qemu/error-report.h"
-#include "qemu/module.h"
-#include "qemu/qemu-print.h"
-#include "qapi/error.h"
-#include "qapi/qmp/qnull.h"
-#include "qapi/visitor.h"
-#include "hw/qdev-properties.h"
-#include "hw/ppc/ppc.h"
-#include "mmu-book3s-v3.h"
-#include "sysemu/qtest.h"
-#include "qemu/cutils.h"
-#include "disas/capstone.h"
-#include "fpu/softfloat.h"
-#include "qapi/qapi-commands-machine-target.h"
-
-/* #define PPC_DUMP_CPU */
-/* #define PPC_DEBUG_SPR */
-/* #define PPC_DUMP_SPR_ACCESSES */
-/* #define USE_APPLE_GDB */
-
-/*
- * Generic callbacks:
- * do nothing but store/retrieve spr value
- */
-static void spr_load_dump_spr(int sprn)
-{
-#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_load_dump_spr(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif
-}
-
-static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
-{
- gen_load_spr(cpu_gpr[gprn], sprn);
- spr_load_dump_spr(sprn);
-}
-
-static void spr_store_dump_spr(int sprn)
-{
-#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_store_dump_spr(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif
-}
-
-static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn, cpu_gpr[gprn]);
- spr_store_dump_spr(sprn);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
-{
-#ifdef TARGET_PPC64
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
- spr_store_dump_spr(sprn);
-#else
- spr_write_generic(ctx, sprn, gprn);
-#endif
-}
-
-static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_load_spr(t0, sprn);
- tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
- tcg_gen_and_tl(t0, t0, t1);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
-{
-}
-
-#endif
-
-/* SPR common to all PowerPC */
-/* XER */
-static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
-{
- gen_read_xer(ctx, cpu_gpr[gprn]);
-}
-
-static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
-{
- gen_write_xer(cpu_gpr[gprn]);
-}
-
-/* LR */
-static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
-}
-
-static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
-}
-
-/* CFAR */
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
-}
-
-static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
-}
-#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
-
-/* CTR */
-static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
-}
-
-static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
-}
-
-/* User read access to SPR */
-/* USPRx */
-/* UMMCRx */
-/* UPMCx */
-/* USIA */
-/* UDECR */
-static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
-{
- gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
-}
-
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
-}
-#endif
-
-/* SPR common to all non-embedded PowerPC */
-/* DECR */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-#endif
-
-/* SPR common to all non-embedded PowerPC, except 601 */
-/* Time base */
-static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
-}
-
-ATTRIBUTE_UNUSED
-static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-ATTRIBUTE_UNUSED
-static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
-}
-
-ATTRIBUTE_UNUSED
-static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
-}
-
-#if defined(TARGET_PPC64)
-ATTRIBUTE_UNUSED
-static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
-}
-
-/* HDECR */
-static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
-}
-
-#endif
-#endif
-
-#if !defined(CONFIG_USER_ONLY)
-/* IBAT0U...IBAT0U */
-/* IBAT0L...IBAT7L */
-static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
-}
-
-static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
-}
-
-static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-/* DBAT0U...DBAT7U */
-/* DBAT0L...DBAT7L */
-static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
-}
-
-static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
-}
-
-static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-/* SDR1 */
-static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
-}
-
-#if defined(TARGET_PPC64)
-/* 64 bits PowerPC specific SPRs */
-/* PIDR */
-static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
-}
-
-static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
- tcg_temp_free(t0);
-}
-static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
-}
-
-/* DPDES */
-static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
-}
-#endif
-#endif
-
-/* PowerPC 601 specific registers */
-/* RTC */
-static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
- /* Must stop the translation as endianness may have changed */
- gen_stop_exception(ctx);
-}
-#endif
-
-/* Unified bats */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
-}
-
-static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-#endif
-
-/* PowerPC 40x specific registers */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn, cpu_gpr[gprn]);
- gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
- /* We must stop translation as we may have rebooted */
- gen_stop_exception(ctx);
-}
-
-static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
-}
-#endif
-
-/* PowerPC 403 specific registers */
-/* PBL1 / PBU1 / PBL2 / PBU2 */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
-}
-
-static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
- gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
- gen_store_spr(SPR_PIR, t0);
- tcg_temp_free(t0);
-}
-#endif
-
-/* SPE specific registers */
-static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
- tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
- tcg_temp_free_i32(t0);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-/* Callback used to write the exception vector base */
-static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
-{
- int sprn_offs;
-
- if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
- sprn_offs = sprn - SPR_BOOKE_IVOR0;
- } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
- sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
- } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
- sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
- } else {
- printf("Trying to write an unknown exception vector %d %03x\n",
- sprn, sprn);
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
- return;
- }
-
- TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-#endif
-
-static inline void vscr_init(CPUPPCState *env, uint32_t val)
-{
- /* Altivec always uses round-to-nearest */
- set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
- helper_mtvscr(env, val);
-}
-
-#ifdef CONFIG_USER_ONLY
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, initial_value)
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, initial_value)
-#else
-#if !defined(CONFIG_KVM)
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, oea_read, oea_write, initial_value)
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, initial_value)
-#else
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, oea_read, oea_write, \
- one_reg_id, initial_value)
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value)
-#endif
-#endif
-
-#define spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, initial_value) \
- spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, 0, initial_value)
-
-#define spr_register_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- initial_value) \
- spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- 0, initial_value)
-
-static inline void _spr_register(CPUPPCState *env, int num,
- const char *name,
- void (*uea_read)(DisasContext *ctx,
- int gprn, int sprn),
- void (*uea_write)(DisasContext *ctx,
- int sprn, int gprn),
-#if !defined(CONFIG_USER_ONLY)
-
- void (*oea_read)(DisasContext *ctx,
- int gprn, int sprn),
- void (*oea_write)(DisasContext *ctx,
- int sprn, int gprn),
- void (*hea_read)(DisasContext *opaque,
- int gprn, int sprn),
- void (*hea_write)(DisasContext *opaque,
- int sprn, int gprn),
-#endif
-#if defined(CONFIG_KVM)
- uint64_t one_reg_id,
-#endif
- target_ulong initial_value)
-{
- ppc_spr_t *spr;
-
- spr = &env->spr_cb[num];
- if (spr->name != NULL || env->spr[num] != 0x00000000 ||
-#if !defined(CONFIG_USER_ONLY)
- spr->oea_read != NULL || spr->oea_write != NULL ||
-#endif
- spr->uea_read != NULL || spr->uea_write != NULL) {
- printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
- exit(1);
- }
-#if defined(PPC_DEBUG_SPR)
- printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
- name, initial_value);
-#endif
- spr->name = name;
- spr->uea_read = uea_read;
- spr->uea_write = uea_write;
-#if !defined(CONFIG_USER_ONLY)
- spr->oea_read = oea_read;
- spr->oea_write = oea_write;
- spr->hea_read = hea_read;
- spr->hea_write = hea_write;
-#endif
-#if defined(CONFIG_KVM)
- spr->one_reg_id = one_reg_id,
-#endif
- env->spr[num] = spr->default_value = initial_value;
-}
-
-/* Generic PowerPC SPRs */
-static void gen_spr_generic(CPUPPCState *env)
-{
- /* Integer processing */
- spr_register(env, SPR_XER, "XER",
- &spr_read_xer, &spr_write_xer,
- &spr_read_xer, &spr_write_xer,
- 0x00000000);
- /* Branch contol */
- spr_register(env, SPR_LR, "LR",
- &spr_read_lr, &spr_write_lr,
- &spr_read_lr, &spr_write_lr,
- 0x00000000);
- spr_register(env, SPR_CTR, "CTR",
- &spr_read_ctr, &spr_write_ctr,
- &spr_read_ctr, &spr_write_ctr,
- 0x00000000);
- /* Interrupt processing */
- spr_register(env, SPR_SRR0, "SRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SRR1, "SRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Processor control */
- spr_register(env, SPR_SPRG0, "SPRG0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG1, "SPRG1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG2, "SPRG2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG3, "SPRG3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR common to all non-embedded PowerPC, including 601 */
-static void gen_spr_ne_601(CPUPPCState *env)
-{
- /* Exception processing */
- spr_register_kvm(env, SPR_DSISR, "DSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSISR, 0x00000000);
- spr_register_kvm(env, SPR_DAR, "DAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DAR, 0x00000000);
- /* Timer */
- spr_register(env, SPR_DECR, "DECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_decr, &spr_write_decr,
- 0x00000000);
-}
-
-/* Storage Description Register 1 */
-static void gen_spr_sdr1(CPUPPCState *env)
-{
-#ifndef CONFIG_USER_ONLY
- if (env->has_hv_mode) {
- /*
- * SDR1 is a hypervisor resource on CPUs which have a
- * hypervisor mode
- */
- spr_register_hv(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
- } else {
- spr_register(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
- }
-#endif
-}
-
-/* BATs 0-3 */
-static void gen_low_BATs(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT0U, "IBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT0L, "IBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT1U, "IBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT1L, "IBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT2U, "IBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT2L, "IBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT3U, "IBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT3L, "IBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_DBAT0U, "DBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT0L, "DBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT1U, "DBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT1L, "DBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT2U, "DBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT2L, "DBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT3U, "DBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT3L, "DBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- env->nb_BATs += 4;
-#endif
-}
-
-/* BATs 4-7 */
-static void gen_high_BATs(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT4U, "IBAT4U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT4L, "IBAT4L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT5U, "IBAT5U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT5L, "IBAT5L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT6U, "IBAT6U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT6L, "IBAT6L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT7U, "IBAT7U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT7L, "IBAT7L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT4U, "DBAT4U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT4L, "DBAT4L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT5U, "DBAT5U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT5L, "DBAT5L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT6U, "DBAT6U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT6L, "DBAT6L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT7U, "DBAT7U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT7L, "DBAT7L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- env->nb_BATs += 4;
-#endif
-}
-
-/* Generic PowerPC time base */
-static void gen_tbl(CPUPPCState *env)
-{
- spr_register(env, SPR_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, &spr_write_tbu,
- 0x00000000);
-}
-
-/* Softare table search registers */
-static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = nb_tlbs;
- env->nb_ways = nb_ways;
- env->id_tlbs = 1;
- env->tlb_type = TLB_6XX;
- spr_register(env, SPR_DMISS, "DMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_DCMP, "DCMP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_HASH1, "HASH1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_HASH2, "HASH2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_IMISS, "IMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_ICMP, "ICMP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_RPA, "RPA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
-}
-
-/* SPR common to MPC755 and G2 */
-static void gen_spr_G2_755(CPUPPCState *env)
-{
- /* SGPRs */
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR common to all 7xx PowerPC implementations */
-static void gen_spr_7xx(CPUPPCState *env)
-{
- /* Breakpoints */
- /* XXX : not implemented */
- spr_register_kvm(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DABR, 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Cache management */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTC, "ICTC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Performance monitors */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_MMCR0, "MMCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC1, "PMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC2, "PMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_SIAR, "SIAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC1, "UPMC1",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC2, "UPMC2",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC3, "UPMC3",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC4, "UPMC4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_USIAR, "USIAR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-#ifdef TARGET_PPC64
-#ifndef CONFIG_USER_ONLY
-static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 PR=0 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- if (ctx->pr) {
- gen_load_spr(t1, SPR_UAMOR);
- } else {
- gen_load_spr(t1, SPR_AMOR);
- }
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_AMR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_AMR, t0);
- spr_store_dump_spr(SPR_AMR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- gen_load_spr(t1, SPR_AMOR);
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_UAMOR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_UAMOR, t0);
- spr_store_dump_spr(SPR_UAMOR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- gen_load_spr(t1, SPR_AMOR);
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_IAMR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_IAMR, t0);
- spr_store_dump_spr(SPR_IAMR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-#endif /* CONFIG_USER_ONLY */
-
-static void gen_spr_amr(CPUPPCState *env)
-{
-#ifndef CONFIG_USER_ONLY
- /*
- * Virtual Page Class Key protection
- *
- * The AMR is accessible either via SPR 13 or SPR 29. 13 is
- * userspace accessible, 29 is privileged. So we only need to set
- * the kvm ONE_REG id on one of them, we use 29
- */
- spr_register(env, SPR_UAMR, "UAMR",
- &spr_read_generic, &spr_write_amr,
- &spr_read_generic, &spr_write_amr,
- 0);
- spr_register_kvm_hv(env, SPR_AMR, "AMR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_amr,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_AMR, 0);
- spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_uamor,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_UAMOR, 0);
- spr_register_hv(env, SPR_AMOR, "AMOR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0);
-#endif /* !CONFIG_USER_ONLY */
-}
-
-static void gen_spr_iamr(CPUPPCState *env)
-{
-#ifndef CONFIG_USER_ONLY
- spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_iamr,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_IAMR, 0);
-#endif /* !CONFIG_USER_ONLY */
-}
-#endif /* TARGET_PPC64 */
-
-#ifndef CONFIG_USER_ONLY
-static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_fixup_thrm(cpu_env);
- gen_load_spr(cpu_gpr[gprn], sprn);
- spr_load_dump_spr(sprn);
-}
-#endif /* !CONFIG_USER_ONLY */
-
-static void gen_spr_thrm(CPUPPCState *env)
-{
- /* Thermal management */
- /* XXX : not implemented */
- spr_register(env, SPR_THRM1, "THRM1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_THRM2, "THRM2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_THRM3, "THRM3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 604 implementation */
-static void gen_spr_604(CPUPPCState *env)
-{
- /* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* Breakpoints */
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register_kvm(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DABR, 0x00000000);
- /* Performance counters */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_MMCR0, "MMCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC1, "PMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC2, "PMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_SIAR, "SIAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_SDA, "SDA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 603 implementation */
-static void gen_spr_603(CPUPPCState *env)
-{
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Breakpoints */
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
-}
-
-/* SPR specific to PowerPC G2 implementation */
-static void gen_spr_G2(CPUPPCState *env)
-{
- /* Memory base address */
- /* MBAR */
- /* XXX : not implemented */
- spr_register(env, SPR_MBAR, "MBAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Exception processing */
- spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Breakpoints */
- /* XXX : not implemented */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DABR2, "DABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IABR2, "IABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IBCR, "IBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DBCR, "DBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 602 implementation */
-static void gen_spr_602(CPUPPCState *env)
-{
- /* ESA registers */
- /* XXX : not implemented */
- spr_register(env, SPR_SER, "SER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_SEBR, "SEBR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_ESASRR, "ESASRR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Floating point status */
- /* XXX : not implemented */
- spr_register(env, SPR_SP, "SP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_LT, "LT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Watchdog timer */
- /* XXX : not implemented */
- spr_register(env, SPR_TCR, "TCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Interrupt base */
- spr_register(env, SPR_IBR, "IBR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 601 implementation */
-static void gen_spr_601(CPUPPCState *env)
-{
- /* Multiplication/division register */
- /* MQ */
- spr_register(env, SPR_MQ, "MQ",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* RTC registers */
- spr_register(env, SPR_601_RTCU, "RTCU",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_601_rtcu,
- 0x00000000);
- spr_register(env, SPR_601_VRTCU, "RTCU",
- &spr_read_601_rtcu, SPR_NOACCESS,
- &spr_read_601_rtcu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_601_RTCL, "RTCL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_601_rtcl,
- 0x00000000);
- spr_register(env, SPR_601_VRTCL, "RTCL",
- &spr_read_601_rtcl, SPR_NOACCESS,
- &spr_read_601_rtcl, SPR_NOACCESS,
- 0x00000000);
- /* Timer */
-#if 0 /* ? */
- spr_register(env, SPR_601_UDECR, "UDECR",
- &spr_read_decr, SPR_NOACCESS,
- &spr_read_decr, SPR_NOACCESS,
- 0x00000000);
-#endif
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT0U, "IBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatu,
- 0x00000000);
- spr_register(env, SPR_IBAT0L, "IBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatl,
- 0x00000000);
- spr_register(env, SPR_IBAT1U, "IBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatu,
- 0x00000000);
- spr_register(env, SPR_IBAT1L, "IBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatl,
- 0x00000000);
- spr_register(env, SPR_IBAT2U, "IBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatu,
- 0x00000000);
- spr_register(env, SPR_IBAT2L, "IBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatl,
- 0x00000000);
- spr_register(env, SPR_IBAT3U, "IBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatu,
- 0x00000000);
- spr_register(env, SPR_IBAT3L, "IBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_601_ubat, &spr_write_601_ubatl,
- 0x00000000);
- env->nb_BATs = 4;
-#endif
-}
-
-static void gen_spr_74xx(CPUPPCState *env)
-{
- /* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_74XX_MMCR2, "MMCR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX: not implemented */
- spr_register(env, SPR_BAMR, "BAMR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MSSCR0, "MSSCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Altivec */
- spr_register(env, SPR_VRSAVE, "VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* Not strictly an SPR */
- vscr_init(env, 0x00010000);
-}
-
-static void gen_l3_ctrl(CPUPPCState *env)
-{
- /* L3CR */
- /* XXX : not implemented */
- spr_register(env, SPR_L3CR, "L3CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR0, "L3ITCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3PM */
- /* XXX : not implemented */
- spr_register(env, SPR_L3PM, "L3PM",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = nb_tlbs;
- env->nb_ways = nb_ways;
- env->id_tlbs = 1;
- env->tlb_type = TLB_6XX;
- /* XXX : not implemented */
- spr_register(env, SPR_PTEHI, "PTEHI",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_PTELO, "PTELO",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_TLBMISS, "TLBMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
-}
-static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
-}
-
-#endif
-
-static void gen_spr_usprg3(CPUPPCState *env)
-{
- spr_register(env, SPR_USPRG3, "USPRG3",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
-static void gen_spr_usprgh(CPUPPCState *env)
-{
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
-/* PowerPC BookE SPR */
-static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
-{
- const char *ivor_names[64] = {
- "IVOR0", "IVOR1", "IVOR2", "IVOR3",
- "IVOR4", "IVOR5", "IVOR6", "IVOR7",
- "IVOR8", "IVOR9", "IVOR10", "IVOR11",
- "IVOR12", "IVOR13", "IVOR14", "IVOR15",
- "IVOR16", "IVOR17", "IVOR18", "IVOR19",
- "IVOR20", "IVOR21", "IVOR22", "IVOR23",
- "IVOR24", "IVOR25", "IVOR26", "IVOR27",
- "IVOR28", "IVOR29", "IVOR30", "IVOR31",
- "IVOR32", "IVOR33", "IVOR34", "IVOR35",
- "IVOR36", "IVOR37", "IVOR38", "IVOR39",
- "IVOR40", "IVOR41", "IVOR42", "IVOR43",
- "IVOR44", "IVOR45", "IVOR46", "IVOR47",
- "IVOR48", "IVOR49", "IVOR50", "IVOR51",
- "IVOR52", "IVOR53", "IVOR54", "IVOR55",
- "IVOR56", "IVOR57", "IVOR58", "IVOR59",
- "IVOR60", "IVOR61", "IVOR62", "IVOR63",
- };
-#define SPR_BOOKE_IVORxx (-1)
- int ivor_sprn[64] = {
- SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
- SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
- SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
- SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
- SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
- SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
- };
- int i;
-
- /* Interrupt processing */
- spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Debug */
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC1, "IAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC2, "IAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DAC1, "DAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DAC2, "DAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x00000000);
- spr_register(env, SPR_BOOKE_DEAR, "DEAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_ESR, "ESR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IVPR, "IVPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_prefix,
- 0x00000000);
- /* Exception vectors */
- for (i = 0; i < 64; i++) {
- if (ivor_mask & (1ULL << i)) {
- if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
- fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
- exit(1);
- }
- spr_register(env, ivor_sprn[i], ivor_names[i],
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_vector,
- 0x00000000);
- }
- }
- spr_register(env, SPR_BOOKE_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_pid,
- 0x00000000);
- spr_register(env, SPR_BOOKE_TCR, "TCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_tcr,
- 0x00000000);
- spr_register(env, SPR_BOOKE_TSR, "TSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_tsr,
- 0x00000000);
- /* Timer */
- spr_register(env, SPR_DECR, "DECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_decr, &spr_write_decr,
- 0x00000000);
- spr_register(env, SPR_BOOKE_DECAR, "DECAR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- /* SPRGs */
- spr_register(env, SPR_USPRG0, "USPRG0",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
- uint32_t maxsize, uint32_t flags,
- uint32_t nentries)
-{
- return (assoc << TLBnCFG_ASSOC_SHIFT) |
- (minsize << TLBnCFG_MINSIZE_SHIFT) |
- (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
- flags | nentries;
-}
-
-/* BookE 2.06 storage control registers */
-static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
- uint32_t *tlbncfg, uint32_t mmucfg)
-{
-#if !defined(CONFIG_USER_ONLY)
- const char *mas_names[8] = {
- "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
- };
- int mas_sprn[8] = {
- SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
- SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
- };
- int i;
-
- /* TLB assist registers */
- /* XXX : not implemented */
- for (i = 0; i < 8; i++) {
- void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
- &spr_write_generic32;
- if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
- uea_write = &spr_write_generic;
- }
- if (mas_mask & (1 << i)) {
- spr_register(env, mas_sprn[i], mas_names[i],
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, uea_write,
- 0x00000000);
- }
- }
- if (env->nb_pids > 1) {
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_PID1, "PID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_pid,
- 0x00000000);
- }
- if (env->nb_pids > 2) {
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_PID2, "PID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_pid,
- 0x00000000);
- }
-
- spr_register(env, SPR_BOOKE_EPLC, "EPLC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_eplc,
- 0x00000000);
- spr_register(env, SPR_BOOKE_EPSC, "EPSC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_epsc,
- 0x00000000);
-
- /* XXX : not implemented */
- spr_register(env, SPR_MMUCFG, "MMUCFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- mmucfg);
- switch (env->nb_ways) {
- case 4:
- spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[3]);
- /* Fallthru */
- case 3:
- spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[2]);
- /* Fallthru */
- case 2:
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[1]);
- /* Fallthru */
- case 1:
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- tlbncfg[0]);
- /* Fallthru */
- case 0:
- default:
- break;
- }
-#endif
-
- gen_spr_usprgh(env);
-}
-
-/* SPR specific to PowerPC 440 implementation */
-static void gen_spr_440(CPUPPCState *env)
-{
- /* Cache control */
- /* XXX : not implemented */
- spr_register(env, SPR_440_DNV0, "DNV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DNV1, "DNV1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DNV2, "DNV2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DNV3, "DNV3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DTV0, "DTV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DTV1, "DTV1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DTV2, "DTV2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DTV3, "DTV3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DVLIM, "DVLIM",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_INV0, "INV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_INV1, "INV1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_INV2, "INV2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_INV3, "INV3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_ITV0, "ITV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_ITV1, "ITV1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_ITV2, "ITV2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_ITV3, "ITV3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_IVLIM, "IVLIM",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Cache debug */
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_DBDR, "DBDR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Processor control */
- spr_register(env, SPR_4xx_CCR0, "CCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_440_RSTCFG, "RSTCFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* Storage control */
- spr_register(env, SPR_440_MMUCR, "MMUCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR shared between PowerPC 40x implementations */
-static void gen_spr_40x(CPUPPCState *env)
-{
- /* Cache */
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCCR, "DCCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_ICCR, "ICCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* Exception */
- spr_register(env, SPR_40x_DEAR, "DEAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_ESR, "ESR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_EVPR, "EVPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_excp_prefix,
- 0x00000000);
- spr_register(env, SPR_40x_SRR2, "SRR2",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_SRR3, "SRR3",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Timers */
- spr_register(env, SPR_40x_PIT, "PIT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_40x_pit, &spr_write_40x_pit,
- 0x00000000);
- spr_register(env, SPR_40x_TCR, "TCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_tcr,
- 0x00000000);
- spr_register(env, SPR_40x_TSR, "TSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_tsr,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 405 implementation */
-static void gen_spr_405(CPUPPCState *env)
-{
- /* MMU */
- spr_register(env, SPR_40x_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_4xx_CCR0, "CCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00700000);
- /* Debug interface */
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBCR0, "DBCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_405_DBCR1, "DBCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- /* Last reset was system reset */
- 0x00000300);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC1, "DAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_DAC2, "DAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_405_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_405_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC1, "IAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_IAC2, "IAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_405_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_405_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Storage control */
- /* XXX: TODO: not implemented */
- spr_register(env, SPR_405_SLER, "SLER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_sler,
- 0x00000000);
- spr_register(env, SPR_40x_ZPR, "ZPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_405_SU0R, "SU0R",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* SPRG */
- spr_register(env, SPR_USPRG0, "USPRG0",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- spr_read_generic, &spr_write_generic,
- 0x00000000);
- gen_spr_usprgh(env);
-}
-
-/* SPR shared between PowerPC 401 & 403 implementations */
-static void gen_spr_401_403(CPUPPCState *env)
-{
- /* Time base */
- spr_register(env, SPR_403_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_403_TBL, "TBL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_403_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_403_TBU, "TBU",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbu,
- 0x00000000);
- /* Debug */
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_403_CDBCR, "CDBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 401 implementation */
-static void gen_spr_401(CPUPPCState *env)
-{
- /* Debug interface */
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBCR0, "DBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- /* Last reset was system reset */
- 0x00000300);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC1, "DAC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC1, "IAC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Storage control */
- /* XXX: TODO: not implemented */
- spr_register(env, SPR_405_SLER, "SLER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_sler,
- 0x00000000);
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_401x2(CPUPPCState *env)
-{
- gen_spr_401(env);
- spr_register(env, SPR_40x_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_ZPR, "ZPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 403 implementation */
-static void gen_spr_403(CPUPPCState *env)
-{
- /* Debug interface */
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBCR0, "DBCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- /* Last reset was system reset */
- 0x00000300);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC1, "DAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC2, "DAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC1, "IAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC2, "IAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_403_real(CPUPPCState *env)
-{
- spr_register(env, SPR_403_PBL1, "PBL1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
- spr_register(env, SPR_403_PBU1, "PBU1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
- spr_register(env, SPR_403_PBL2, "PBL2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
- spr_register(env, SPR_403_PBU2, "PBU2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
-}
-
-static void gen_spr_403_mmu(CPUPPCState *env)
-{
- /* MMU */
- spr_register(env, SPR_40x_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_ZPR, "ZPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC compression coprocessor extension */
-static void gen_spr_compress(CPUPPCState *env)
-{
- /* XXX : not implemented */
- spr_register(env, SPR_401_SKR, "SKR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_5xx_8xx(CPUPPCState *env)
-{
- /* Exception processing */
- spr_register_kvm(env, SPR_DSISR, "DSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSISR, 0x00000000);
- spr_register_kvm(env, SPR_DAR, "DAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DAR, 0x00000000);
- /* Timer */
- spr_register(env, SPR_DECR, "DECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_decr, &spr_write_decr,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_EIE, "EIE",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_EID, "EID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_NRI, "NRI",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPA, "CMPA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPB, "CMPB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPC, "CMPC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPD, "CMPD",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_ECR, "ECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_DER, "DER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_COUNTA, "COUNTA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_COUNTB, "COUNTB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPE, "CMPE",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPF, "CMPF",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPG, "CMPG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_CMPH, "CMPH",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_BAR, "BAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_DPDR, "DPDR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_IMMR, "IMMR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_5xx(CPUPPCState *env)
-{
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_RCPU_FPECR, "FPECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_8xx(CPUPPCState *env)
-{
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_IC_CST, "IC_CST",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_DC_CST, "DC_CST",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_AP, "MI_AP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_AP, "MD_AP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_TW, "MD_TW",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/*
- * AMR => SPR 29 (Power 2.04)
- * CTRL => SPR 136 (Power 2.04)
- * CTRL => SPR 152 (Power 2.04)
- * SCOMC => SPR 276 (64 bits ?)
- * SCOMD => SPR 277 (64 bits ?)
- * TBU40 => SPR 286 (Power 2.04 hypv)
- * HSPRG0 => SPR 304 (Power 2.04 hypv)
- * HSPRG1 => SPR 305 (Power 2.04 hypv)
- * HDSISR => SPR 306 (Power 2.04 hypv)
- * HDAR => SPR 307 (Power 2.04 hypv)
- * PURR => SPR 309 (Power 2.04 hypv)
- * HDEC => SPR 310 (Power 2.04 hypv)
- * HIOR => SPR 311 (hypv)
- * RMOR => SPR 312 (970)
- * HRMOR => SPR 313 (Power 2.04 hypv)
- * HSRR0 => SPR 314 (Power 2.04 hypv)
- * HSRR1 => SPR 315 (Power 2.04 hypv)
- * LPIDR => SPR 317 (970)
- * EPR => SPR 702 (Power 2.04 emb)
- * perf => 768-783 (Power 2.04)
- * perf => 784-799 (Power 2.04)
- * PPR => SPR 896 (Power 2.04)
- * DABRX => 1015 (Power 2.04 hypv)
- * FPECR => SPR 1022 (?)
- * ... and more (thermal management, performance counters, ...)
- */
-
-/*****************************************************************************/
-/* Exception vectors models */
-static void init_excp_4xx_real(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
- env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
-static void init_excp_4xx_softmmu(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
- env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
-static void init_excp_MPC5xx(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
- env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
- env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
- env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_MPC8xx(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
- env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
- env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
- env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
- env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_G2(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
- env->ivor_mask = 0x0000FFF7UL;
- env->ivpr_mask = ivpr_mask;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
-static void init_excp_BookE(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
- env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
-static void init_excp_601(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_602(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- /* XXX: exception prefix has a special behavior on 602 */
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
- env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_603(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_604(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_7x0(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_750cl(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_750cx(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-/* XXX: Check if this is correct */
-static void init_excp_7x5(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_7400(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
- env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-static void init_excp_7450(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
- /* Hardware reset vector */
- env->hreset_vector = 0x00000100UL;
-#endif
-}
-
-#if defined(TARGET_PPC64)
-static void init_excp_970(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
- env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
- env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
- /* Hardware reset vector */
- env->hreset_vector = 0x0000000000000100ULL;
-#endif
-}
-
-static void init_excp_POWER7(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
- env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
- env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
- env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
- env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
- /* Hardware reset vector */
- env->hreset_vector = 0x0000000000000100ULL;
-#endif
-}
-
-static void init_excp_POWER8(CPUPPCState *env)
-{
- init_excp_POWER7(env);
-
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
- env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
- env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
- env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
-#endif
-}
-
-static void init_excp_POWER9(CPUPPCState *env)
-{
- init_excp_POWER8(env);
-
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
- env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000;
-#endif
-}
-
-static void init_excp_POWER10(CPUPPCState *env)
-{
- init_excp_POWER9(env);
-}
-
-#endif
-
-/*****************************************************************************/
-/* Power management enable checks */
-static int check_pow_none(CPUPPCState *env)
-{
- return 0;
-}
-
-static int check_pow_nocheck(CPUPPCState *env)
-{
- return 1;
-}
-
-static int check_pow_hid0(CPUPPCState *env)
-{
- if (env->spr[SPR_HID0] & 0x00E00000) {
- return 1;
- }
-
- return 0;
-}
-
-static int check_pow_hid0_74xx(CPUPPCState *env)
-{
- if (env->spr[SPR_HID0] & 0x00600000) {
- return 1;
- }
-
- return 0;
-}
-
-static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
-{
- return true;
-}
-
-#ifdef TARGET_PPC64
-static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
-{
- return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
-}
-#endif
-
-/*****************************************************************************/
-/* PowerPC implementations definitions */
-
-#define POWERPC_FAMILY(_name) \
- static void \
- glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
- \
- static const TypeInfo \
- glue(glue(ppc_, _name), _cpu_family_type_info) = { \
- .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
- .parent = TYPE_POWERPC_CPU, \
- .abstract = true, \
- .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
- }; \
- \
- static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
- { \
- type_register_static( \
- &glue(glue(ppc_, _name), _cpu_family_type_info)); \
- } \
- \
- type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
- \
- static void glue(glue(ppc_, _name), _cpu_family_class_init)
-
-static void init_proc_401(CPUPPCState *env)
-{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401(env);
- init_excp_4xx_real(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 401";
- pcc->init_proc = init_proc_401;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_WRTEE | PPC_DCR |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DE) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_REAL;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_401x2(CPUPPCState *env)
-{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 401x2";
- pcc->init_proc = init_proc_401x2;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << 20) |
- (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_401x3(CPUPPCState *env)
-{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 401x3";
- pcc->init_proc = init_proc_401x3;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << 20) |
- (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_IOP480(CPUPPCState *env)
-{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "IOP480";
- pcc->init_proc = init_proc_IOP480;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << 20) |
- (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_403(CPUPPCState *env)
-{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_403(env);
- gen_spr_403_real(env);
- init_excp_4xx_real(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 403";
- pcc->init_proc = init_proc_403;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_PE) |
- (1ull << MSR_PX) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_REAL;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_403GCX(CPUPPCState *env)
-{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_403(env);
- gen_spr_403_real(env);
- gen_spr_403_mmu(env);
- /* Bus access control */
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 403 GCX";
- pcc->init_proc = init_proc_403GCX;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_PE) |
- (1ull << MSR_PX) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_405(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_40x(env);
- gen_spr_405(env);
- /* Bus access control */
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 405";
- pcc->init_proc = init_proc_405;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_405;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_440EP(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MCSR, "MCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_CCR1, "CCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_BookE(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(20, 24, 28, 32);
-}
-
-POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 440 EP";
- pcc->init_proc = init_proc_440EP;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_DCR | PPC_WRTEE | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_MFTB |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 460 EX";
- pcc->init_proc = init_proc_440EP;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_MFTB |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_440GP(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_BookE(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(20, 24, 28, 32);
-}
-
-POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 440 GP";
- pcc->init_proc = init_proc_440GP;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_440x4(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_BookE(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(20, 24, 28, 32);
-}
-
-POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 440x4";
- pcc->init_proc = init_proc_440x4;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_MFTB |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_440x5(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MCSR, "MCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_CCR1, "CCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_BookE(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(20, 24, 28, 32);
-}
-
-POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 440x5";
- pcc->init_proc = init_proc_440x5;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_MFTB |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 440x5 with double precision FPU";
- pcc->init_proc = init_proc_440x5;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_FLOAT | PPC_FLOAT_FSQRT |
- PPC_FLOAT_STFIWX |
- PPC_DCR | PPC_WRTEE | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_MFTB |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->insns_flags2 = PPC2_FP_CVT_S64;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_MPC5xx(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_5xx_8xx(env);
- gen_spr_5xx(env);
- init_excp_MPC5xx(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-}
-
-POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "Freescale 5xx cores (aka RCPU)";
- pcc->init_proc = init_proc_MPC5xx;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_MEM_EIEIO | PPC_MEM_SYNC |
- PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
- PPC_MFTB;
- pcc->msr_mask = (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_REAL;
- pcc->excp_model = POWERPC_EXCP_603;
- pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
- pcc->bfd_mach = bfd_mach_ppc_505;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_MPC8xx(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_5xx_8xx(env);
- gen_spr_8xx(env);
- init_excp_MPC8xx(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-}
-
-POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
- pcc->init_proc = init_proc_MPC8xx;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_MEM_EIEIO | PPC_MEM_SYNC |
- PPC_CACHE_ICBI | PPC_MFTB;
- pcc->msr_mask = (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_MPC8xx;
- pcc->excp_model = POWERPC_EXCP_603;
- pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
- pcc->bfd_mach = bfd_mach_ppc_860;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-/* Freescale 82xx cores (aka PowerQUICC-II) */
-
-static void init_proc_G2(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
- /* Time base */
- gen_tbl(env);
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation register */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_G2(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC G2";
- pcc->init_proc = init_proc_G2;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_AL) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_G2;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_ec603e;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_G2LE(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
- /* Time base */
- gen_tbl(env);
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation register */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_G2(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC G2LE";
- pcc->init_proc = init_proc_G2LE;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_AL) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_G2;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_ec603e;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_e200(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000070000FFFFULL);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
- &spr_read_spefscr, &spr_write_spefscr,
- &spr_read_spefscr, &spr_write_spefscr,
- 0x00000000);
- /* Memory management */
- gen_spr_BookE206(env, 0x0000005D, NULL, 0);
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000); /* TOFIX */
- spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_e200(env, 0xFFFF0000UL);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-}
-
-POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e200 core";
- pcc->init_proc = init_proc_e200;
- pcc->check_pow = check_pow_hid0;
- /*
- * XXX: unimplemented instructions:
- * dcblc
- * dcbtlst
- * dcbtstls
- * icblc
- * icbtls
- * tlbivax
- * all SPE multiply-accumulate instructions
- */
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
- PPC_SPE | PPC_SPE_SINGLE |
- PPC_WRTEE | PPC_RFDI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX |
- PPC_BOOKE;
- pcc->msr_mask = (1ull << MSR_UCLE) |
- (1ull << MSR_SPE) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_860;
- pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_e300(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
- /* Time base */
- gen_tbl(env);
- /* hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Breakpoints */
- /* XXX : not implemented */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DABR2, "DABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IABR2, "IABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IBCR, "IBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DBCR, "DBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_603(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e300 core";
- pcc->init_proc = init_proc_e300;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_AL) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_603;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv val = tcg_temp_new();
- tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
- gen_store_spr(SPR_BOOKE_MAS3, val);
- tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
- gen_store_spr(SPR_BOOKE_MAS7, val);
- tcg_temp_free(val);
-}
-
-static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv mas7 = tcg_temp_new();
- TCGv mas3 = tcg_temp_new();
- gen_load_spr(mas7, SPR_BOOKE_MAS7);
- tcg_gen_shli_tl(mas7, mas7, 32);
- gen_load_spr(mas3, SPR_BOOKE_MAS3);
- tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
- tcg_temp_free(mas3);
- tcg_temp_free(mas7);
-}
-
-#endif
-
-enum fsl_e500_version {
- fsl_e500v1,
- fsl_e500v2,
- fsl_e500mc,
- fsl_e5500,
- fsl_e6500,
-};
-
-static void init_proc_e500(CPUPPCState *env, int version)
-{
- uint32_t tlbncfg[2];
- uint64_t ivor_mask;
- uint64_t ivpr_mask = 0xFFFF0000ULL;
- uint32_t l1cfg0 = 0x3800 /* 8 ways */
- | 0x0020; /* 32 kb */
- uint32_t l1cfg1 = 0x3800 /* 8 ways */
- | 0x0020; /* 32 kb */
- uint32_t mmucfg = 0;
-#if !defined(CONFIG_USER_ONLY)
- int i;
-#endif
-
- /* Time base */
- gen_tbl(env);
- /*
- * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
- * complain when accessing them.
- * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
- */
- switch (version) {
- case fsl_e500v1:
- case fsl_e500v2:
- default:
- ivor_mask = 0x0000000F0000FFFFULL;
- break;
- case fsl_e500mc:
- case fsl_e5500:
- ivor_mask = 0x000003FE0000FFFFULL;
- break;
- case fsl_e6500:
- ivor_mask = 0x000003FF0000FFFFULL;
- break;
- }
- gen_spr_BookE(env, ivor_mask);
- gen_spr_usprg3(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
- &spr_read_spefscr, &spr_write_spefscr,
- &spr_read_spefscr, &spr_write_spefscr,
- 0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- /* Memory management */
- env->nb_pids = 3;
- env->nb_ways = 2;
- env->id_tlbs = 0;
- switch (version) {
- case fsl_e500v1:
- tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
- tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
- break;
- case fsl_e500v2:
- tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
- tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
- break;
- case fsl_e500mc:
- case fsl_e5500:
- tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
- tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
- break;
- case fsl_e6500:
- mmucfg = 0x6510B45;
- env->nb_pids = 1;
- tlbncfg[0] = 0x08052400;
- tlbncfg[1] = 0x40028040;
- break;
- default:
- cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
- env->spr[SPR_PVR]);
- }
-#endif
- /* Cache sizes */
- switch (version) {
- case fsl_e500v1:
- case fsl_e500v2:
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- break;
- case fsl_e500mc:
- case fsl_e5500:
- env->dcache_line_size = 64;
- env->icache_line_size = 64;
- l1cfg0 |= 0x1000000; /* 64 byte cache block size */
- l1cfg1 |= 0x1000000; /* 64 byte cache block size */
- break;
- case fsl_e6500:
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- l1cfg0 |= 0x0F83820;
- l1cfg1 |= 0x0B83820;
- break;
- default:
- cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
- env->spr[SPR_PVR]);
- }
- gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_MCAR, "MCAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MCSR, "MCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- l1cfg0);
- spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- l1cfg1);
- spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_e500_l1csr0,
- 0x00000000);
- spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_e500_l1csr1,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke206_mmucsr0,
- 0x00000000);
- spr_register(env, SPR_BOOKE_EPR, "EPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX better abstract into Emb.xxx features */
- if ((version == fsl_e5500) || (version == fsl_e6500)) {
- spr_register(env, SPR_BOOKE_EPCR, "EPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_mas73, &spr_write_mas73,
- 0x00000000);
- ivpr_mask = (target_ulong)~0xFFFFULL;
- }
-
- if (version == fsl_e6500) {
- /* Thread identification */
- spr_register(env, SPR_TIR, "TIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000004);
- spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x7FFFFFFC);
- }
-
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 0;
- env->tlb_type = TLB_MAS;
- for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
- env->nb_tlb += booke206_tlb_size(env, i);
- }
-#endif
-
- init_excp_e200(env, ivpr_mask);
- /* Allocate hardware IRQ controller */
- ppce500_irq_init(env_archcpu(env));
-}
-
-static void init_proc_e500v1(CPUPPCState *env)
-{
- init_proc_e500(env, fsl_e500v1);
-}
-
-POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e500v1 core";
- pcc->init_proc = init_proc_e500v1;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
- PPC_SPE | PPC_SPE_SINGLE |
- PPC_WRTEE | PPC_RFDI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
- pcc->insns_flags2 = PPC2_BOOKE206;
- pcc->msr_mask = (1ull << MSR_UCLE) |
- (1ull << MSR_SPE) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_860;
- pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_e500v2(CPUPPCState *env)
-{
- init_proc_e500(env, fsl_e500v2);
-}
-
-POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e500v2 core";
- pcc->init_proc = init_proc_e500v2;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
- PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
- PPC_WRTEE | PPC_RFDI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
- pcc->insns_flags2 = PPC2_BOOKE206;
- pcc->msr_mask = (1ull << MSR_UCLE) |
- (1ull << MSR_SPE) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_860;
- pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_e500mc(CPUPPCState *env)
-{
- init_proc_e500(env, fsl_e500mc);
-}
-
-POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e500mc core";
- pcc->init_proc = init_proc_e500mc;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
- PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_FLOAT | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
- PPC_FLOAT_STFIWX | PPC_WAIT |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
- pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
- pcc->msr_mask = (1ull << MSR_GS) |
- (1ull << MSR_UCLE) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PX) |
- (1ull << MSR_RI);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- /* FIXME: figure out the correct flag for e500mc */
- pcc->bfd_mach = bfd_mach_ppc_e500;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-#ifdef TARGET_PPC64
-static void init_proc_e5500(CPUPPCState *env)
-{
- init_proc_e500(env, fsl_e5500);
-}
-
-POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e5500 core";
- pcc->init_proc = init_proc_e5500;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
- PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_FLOAT | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
- PPC_FLOAT_STFIWX | PPC_WAIT |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
- PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
- PPC2_FP_CVT_S64;
- pcc->msr_mask = (1ull << MSR_CM) |
- (1ull << MSR_GS) |
- (1ull << MSR_UCLE) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PX) |
- (1ull << MSR_RI);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- /* FIXME: figure out the correct flag for e5500 */
- pcc->bfd_mach = bfd_mach_ppc_e500;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_e6500(CPUPPCState *env)
-{
- init_proc_e500(env, fsl_e6500);
-}
-
-POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e6500 core";
- pcc->init_proc = init_proc_e6500;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
- PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_FLOAT | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
- PPC_FLOAT_STFIWX | PPC_WAIT |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
- PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
- pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
- PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
- pcc->msr_mask = (1ull << MSR_CM) |
- (1ull << MSR_GS) |
- (1ull << MSR_UCLE) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IS) |
- (1ull << MSR_DS) |
- (1ull << MSR_PX) |
- (1ull << MSR_RI) |
- (1ull << MSR_VR);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_e500;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
-}
-
-#endif
-
-/* Non-embedded PowerPC */
-
-#define POWERPC_MSRR_601 (0x0000000000001040ULL)
-
-static void init_proc_601(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_601(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_hid0_601,
- 0x80010080);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_601_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_601_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- init_excp_601(env);
- /*
- * XXX: beware that dcache line size is 64
- * but dcbz uses 32 bytes "sectors"
- * XXX: this breaks clcs instruction !
- */
- env->dcache_line_size = 32;
- env->icache_line_size = 64;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 601";
- pcc->init_proc = init_proc_601;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
- PPC_FLOAT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_601;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_601;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_601;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
-}
-
-#define POWERPC_MSRR_601v (0x0000000000001040ULL)
-
-static void init_proc_601v(CPUPPCState *env)
-{
- init_proc_601(env);
- /* XXX : not implemented */
- spr_register(env, SPR_601_HID15, "HID15",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 601v";
- pcc->init_proc = init_proc_601v;
- pcc->check_pow = check_pow_none;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
- PPC_FLOAT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_601;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_601;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
-}
-
-static void init_proc_602(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_602(env);
- /* Time base */
- gen_tbl(env);
- /* hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_602(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 602";
- pcc->init_proc = init_proc_602;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_602_SPEC;
- pcc->msr_mask = (1ull << MSR_VSX) |
- (1ull << MSR_SA) |
- (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- /* XXX: 602 MMU is quite specific. Should add a special case */
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_602;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_602;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_603(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
- /* Time base */
- gen_tbl(env);
- /* hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_603(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 603";
- pcc->init_proc = init_proc_603;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_603;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_603E(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
- /* Time base */
- gen_tbl(env);
- /* hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_603(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 603e";
- pcc->init_proc = init_proc_603E;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603E;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_ec603e;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_604(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_604(env);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- init_excp_604(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 604";
- pcc->init_proc = init_proc_604;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_604;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_604;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_604E(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_604(env);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- init_excp_604(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 604E";
- pcc->init_proc = init_proc_604E;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_604;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_604;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_740(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- init_excp_7x0(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 740";
- pcc->init_proc = init_proc_740;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_7x0;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_750(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- /*
- * XXX: high BATs are also present but are known to be bugged on
- * die version 1.x
- */
- init_excp_7x0(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 750";
- pcc->init_proc = init_proc_750;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_7x0;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_750cl(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- /* Those registers are fake on 750CL */
- spr_register(env, SPR_THRM1, "THRM1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_THRM2, "THRM2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_THRM3, "THRM3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX: not implemented */
- spr_register(env, SPR_750_TDCL, "TDCL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_750_TDCH, "TDCH",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* DMA */
- /* XXX : not implemented */
- spr_register(env, SPR_750_WPAR, "WPAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_750_DMAL, "DMAL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_750_DMAU, "DMAU",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750CL_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750CL_HID4, "HID4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Quantization registers */
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR0, "GQR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR1, "GQR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR2, "GQR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR3, "GQR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR4, "GQR4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR5, "GQR5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR6, "GQR6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_GQR7, "GQR7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- /* PowerPC 750cl has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
- init_excp_750cl(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 750 CL";
- pcc->init_proc = init_proc_750cl;
- pcc->check_pow = check_pow_hid0;
- /*
- * XXX: not implemented:
- * cache lock instructions:
- * dcbz_l
- * floating point paired instructions
- * psq_lux
- * psq_lx
- * psq_stux
- * psq_stx
- * ps_abs
- * ps_add
- * ps_cmpo0
- * ps_cmpo1
- * ps_cmpu0
- * ps_cmpu1
- * ps_div
- * ps_madd
- * ps_madds0
- * ps_madds1
- * ps_merge00
- * ps_merge01
- * ps_merge10
- * ps_merge11
- * ps_mr
- * ps_msub
- * ps_mul
- * ps_muls0
- * ps_muls1
- * ps_nabs
- * ps_neg
- * ps_nmadd
- * ps_nmsub
- * ps_res
- * ps_rsqrte
- * ps_sel
- * ps_sub
- * ps_sum0
- * ps_sum1
- */
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_7x0;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_750cx(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
- /* This register is not implemented but is present for compatibility */
- spr_register(env, SPR_SDA, "SDA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- /* PowerPC 750cx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
- init_excp_750cx(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 750CX";
- pcc->init_proc = init_proc_750cx;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_7x0;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_750fx(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
- /* XXX : not implemented */
- spr_register(env, SPR_750_THRM4, "THRM4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750FX_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
- init_excp_7x0(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 750FX";
- pcc->init_proc = init_proc_750fx;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_7x0;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_750gx(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* XXX : not implemented (XXX: different from 750fx) */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
- /* XXX : not implemented */
- spr_register(env, SPR_750_THRM4, "THRM4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- /* XXX : not implemented (XXX: different from 750fx) */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented (XXX: different from 750fx) */
- spr_register(env, SPR_750FX_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
- init_excp_7x0(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 750GX";
- pcc->init_proc = init_proc_750gx;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_7x0;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_745(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- gen_spr_G2_755(env);
- /* Time base */
- gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_7x5(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 745";
- pcc->init_proc = init_proc_745;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_7x5;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_755(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- gen_spr_G2_755(env);
- /* Time base */
- gen_tbl(env);
- /* L2 cache control */
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_L2PMCR, "L2PMCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Thermal management */
- gen_spr_thrm(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_7x5(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 755";
- pcc->init_proc = init_proc_755;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_7x5;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_750;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7400(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX: this seems not implemented on all revisions. */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSCR1, "MSSCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Thermal management */
- gen_spr_thrm(env);
- /* Memory management */
- gen_low_BATs(env);
- init_excp_7400(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7400 (aka G4)";
- pcc->init_proc = init_proc_7400;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7410(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Thermal management */
- gen_spr_thrm(env);
- /* L2PMCR */
- /* XXX : not implemented */
- spr_register(env, SPR_L2PMCR, "L2PMCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* LDSTDB */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTDB, "LDSTDB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- init_excp_7400(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7410 (aka G4)";
- pcc->init_proc = init_proc_7410;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7440(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* LDSTCR */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* ICTRL */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* MSSSR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* PMC */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7440 (aka G4)";
- pcc->init_proc = init_proc_7440;
- pcc->check_pow = check_pow_hid0_74xx;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7450(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* Level 3 cache control */
- gen_l3_ctrl(env);
- /* L3ITCR1 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR1, "L3ITCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR2 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR2, "L3ITCR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR3 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR3, "L3ITCR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3OHCR */
- /* XXX : not implemented */
- spr_register(env, SPR_L3OHCR, "L3OHCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* LDSTCR */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* ICTRL */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* MSSSR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* PMC */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7450 (aka G4)";
- pcc->init_proc = init_proc_7450;
- pcc->check_pow = check_pow_hid0_74xx;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7445(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* LDSTCR */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* ICTRL */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* MSSSR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* PMC */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* SPRGs */
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7445 (aka G4)";
- pcc->init_proc = init_proc_7445;
- pcc->check_pow = check_pow_hid0_74xx;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7455(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* Level 3 cache control */
- gen_l3_ctrl(env);
- /* LDSTCR */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* ICTRL */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* MSSSR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* PMC */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* SPRGs */
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7455 (aka G4)";
- pcc->init_proc = init_proc_7455;
- pcc->check_pow = check_pow_hid0_74xx;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_7457(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* Level 3 cache control */
- gen_l3_ctrl(env);
- /* L3ITCR1 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR1, "L3ITCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR2 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR2, "L3ITCR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR3 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR3, "L3ITCR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3OHCR */
- /* XXX : not implemented */
- spr_register(env, SPR_L3OHCR, "L3OHCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* LDSTCR */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* ICTRL */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* MSSSR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* PMC */
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* SPRGs */
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 7457 (aka G4)";
- pcc->init_proc = init_proc_7457;
- pcc->check_pow = check_pow_hid0_74xx;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_e600(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_7XX_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* SPRGs */
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC e600";
- pcc->init_proc = init_proc_e600;
- pcc->check_pow = check_pow_hid0_74xx;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
- pcc->msr_mask = (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_32B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_74xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_7400;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
-}
-
-#if defined(TARGET_PPC64)
-#if defined(CONFIG_USER_ONLY)
-#define POWERPC970_HID5_INIT 0x00000080
-#else
-#define POWERPC970_HID5_INIT 0x00000000
-#endif
-
-static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
- int bit, int sprn, int cause)
-{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
-
- gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
-
- tcg_temp_free_i32(t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t1);
-}
-
-static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
- int bit, int sprn, int cause)
-{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
-
- gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
-
- tcg_temp_free_i32(t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t1);
-}
-
-static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv spr_up = tcg_temp_new();
- TCGv spr = tcg_temp_new();
-
- gen_load_spr(spr, sprn - 1);
- tcg_gen_shri_tl(spr_up, spr, 32);
- tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
-
- tcg_temp_free(spr);
- tcg_temp_free(spr_up);
-}
-
-static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv spr = tcg_temp_new();
-
- gen_load_spr(spr, sprn - 1);
- tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
- gen_store_spr(sprn - 1, spr);
-
- tcg_temp_free(spr);
-}
-
-static int check_pow_970(CPUPPCState *env)
-{
- if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
- return 1;
- }
-
- return 0;
-}
-
-static void gen_spr_970_hid(CPUPPCState *env)
-{
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x60000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
-}
-
-static void gen_spr_970_hior(CPUPPCState *env)
-{
- spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x00000000);
-}
-
-static void gen_spr_book3s_ctrl(CPUPPCState *env)
-{
- spr_register(env, SPR_CTRL, "SPR_CTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
-static void gen_spr_book3s_altivec(CPUPPCState *env)
-{
- if (!(env->insns_flags & PPC_ALTIVEC)) {
- return;
- }
-
- spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_VRSAVE, 0x00000000);
-
- /*
- * Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors.
- */
- vscr_init(env, 0x00010000);
-}
-
-static void gen_spr_book3s_dbg(CPUPPCState *env)
-{
- /*
- * TODO: different specs define different scopes for these,
- * will have to address this:
- * 970: super/write and super/read
- * powerisa 2.03..2.04: hypv/write and super/read.
- * powerisa 2.05 and newer: hypv/write and hypv/read.
- */
- spr_register_kvm(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DABR, 0x00000000);
- spr_register_kvm(env, SPR_DABRX, "DABRX",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DABRX, 0x00000000);
-}
-
-static void gen_spr_book3s_207_dbg(CPUPPCState *env)
-{
- spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DAWR, 0x00000000);
- spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DAWRX, 0x00000000);
- spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_CIABR, 0x00000000);
-}
-
-static void gen_spr_970_dbg(CPUPPCState *env)
-{
- /* Breakpoints */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCR0, 0x00000000);
- spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCR1, 0x00000000);
- spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCRA, 0x00000000);
- spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC1, 0x00000000);
- spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC2, 0x00000000);
- spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC3, 0x00000000);
- spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC4, 0x00000000);
- spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC5, 0x00000000);
- spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC6, 0x00000000);
- spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_SIAR, 0x00000000);
- spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_SDAR, 0x00000000);
-}
-
-static void gen_spr_book3s_pmu_user(CPUPPCState *env)
-{
- spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UPMC1, "UPMC1",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UPMC2, "UPMC2",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UPMC3, "UPMC3",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UPMC4, "UPMC4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_USIAR, "USIAR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_USDAR, "USDAR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
-}
-
-static void gen_spr_970_pmu_sup(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_970_PMC7, "PMC7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC7, 0x00000000);
- spr_register_kvm(env, SPR_970_PMC8, "PMC8",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC8, 0x00000000);
-}
-
-static void gen_spr_970_pmu_user(CPUPPCState *env)
-{
- spr_register(env, SPR_970_UPMC7, "UPMC7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_970_UPMC8, "UPMC8",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
-}
-
-static void gen_spr_power8_pmu_sup(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCR2, 0x00000000);
- spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCRS, 0x00000000);
- spr_register_kvm(env, SPR_POWER_SIER, "SIER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_SIER, 0x00000000);
- spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_SPMC1, 0x00000000);
- spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_SPMC2, 0x00000000);
- spr_register_kvm(env, SPR_TACR, "TACR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_TACR, 0x00000000);
- spr_register_kvm(env, SPR_TCSCR, "TCSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_TCSCR, 0x00000000);
- spr_register_kvm(env, SPR_CSIGR, "CSIGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_CSIGR, 0x00000000);
-}
-
-static void gen_spr_power8_pmu_user(CPUPPCState *env)
-{
- spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, &spr_write_ureg,
- 0x00000000);
- spr_register(env, SPR_POWER_USIER, "USIER",
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_power5p_ear(CPUPPCState *env)
-{
- /* External access control */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_power5p_tb(CPUPPCState *env)
-{
- /* TBU40 (High 40 bits of the Timebase register */
- spr_register_hv(env, SPR_TBU40, "TBU40",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbu40,
- 0x00000000);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv hmer = tcg_temp_new();
-
- gen_load_spr(hmer, sprn);
- tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
- gen_store_spr(sprn, hmer);
- spr_store_dump_spr(sprn);
- tcg_temp_free(hmer);
-}
-
-static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
-}
-#endif /* !defined(CONFIG_USER_ONLY) */
-
-static void gen_spr_970_lpar(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- /*
- * PPC970: HID4 covers things later controlled by the LPCR and
- * RMOR in later CPUs, but with a different encoding. We only
- * support the 970 in "Apple mode" which has all hypervisor
- * facilities disabled by strapping, so we can basically just
- * ignore it
- */
- spr_register(env, SPR_970_HID4, "HID4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
-}
-
-static void gen_spr_power5p_lpar(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- /* Logical partitionning */
- spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_lpcr,
- KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
- spr_register_hv(env, SPR_HDEC, "HDEC",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hdecr, &spr_write_hdecr, 0);
-#endif
-}
-
-static void gen_spr_book3s_ids(CPUPPCState *env)
-{
- /* FIXME: Will need to deal with thread vs core only SPRs */
-
- /* Processor identification */
- spr_register_hv(env, SPR_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, NULL,
- 0x00000000);
- spr_register_hv(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_TSCR, "TSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HMER, "HMER",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_hmer,
- 0x00000000);
- spr_register_hv(env, SPR_HMEER, "HMEER",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_TFMR, "TFMR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_LPIDR, "LPIDR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_lpidr,
- 0x00000000);
- spr_register_hv(env, SPR_HFSCR, "HFSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_MMCRC, "MMCRC",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_MMCRH, "MMCRH",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HSRR0, "HSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HSRR1, "HSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HDAR, "HDAR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HDSISR, "HDSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_HRMOR, "HRMOR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_rmor(CPUPPCState *env)
-{
- spr_register_hv(env, SPR_RMOR, "RMOR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void gen_spr_power8_ids(CPUPPCState *env)
-{
- /* Thread identification */
- spr_register(env, SPR_TIR, "TIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
-}
-
-static void gen_spr_book3s_purr(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
- spr_register_kvm_hv(env, SPR_PURR, "PURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, &spr_write_purr,
- KVM_REG_PPC_PURR, 0x00000000);
- spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, &spr_write_purr,
- KVM_REG_PPC_SPURR, 0x00000000);
-#endif
-}
-
-static void gen_spr_power6_dbg(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_CFAR, "SPR_CFAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_cfar, &spr_write_cfar,
- 0x00000000);
-#endif
-}
-
-static void gen_spr_power5p_common(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_PPR, "PPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PPR, 0x00000000);
-}
-
-static void gen_spr_power6_common(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSCR, 0x00000000);
-#endif
- /*
- * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
- * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
- */
- spr_register_hv(env, SPR_PCR, "PCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pcr,
- 0x00000000);
-}
-
-static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void gen_spr_power8_tce_address_control(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_TAR, "TAR",
- &spr_read_tar, &spr_write_tar,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_TAR, 0x00000000);
-}
-
-static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_read_prev_upper32(ctx, gprn, sprn);
-}
-
-static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_write_prev_upper32(ctx, sprn, gprn);
-}
-
-static void gen_spr_power8_tm(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_TFHAR, "TFHAR",
- &spr_read_tm, &spr_write_tm,
- &spr_read_tm, &spr_write_tm,
- KVM_REG_PPC_TFHAR, 0x00000000);
- spr_register_kvm(env, SPR_TFIAR, "TFIAR",
- &spr_read_tm, &spr_write_tm,
- &spr_read_tm, &spr_write_tm,
- KVM_REG_PPC_TFIAR, 0x00000000);
- spr_register_kvm(env, SPR_TEXASR, "TEXASR",
- &spr_read_tm, &spr_write_tm,
- &spr_read_tm, &spr_write_tm,
- KVM_REG_PPC_TEXASR, 0x00000000);
- spr_register(env, SPR_TEXASRU, "TEXASRU",
- &spr_read_tm_upper32, &spr_write_tm_upper32,
- &spr_read_tm_upper32, &spr_write_tm_upper32,
- 0x00000000);
-}
-
-static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_read_prev_upper32(ctx, gprn, sprn);
-}
-
-static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_write_prev_upper32(ctx, sprn, gprn);
-}
-
-static void gen_spr_power8_ebb(CPUPPCState *env)
-{
- spr_register(env, SPR_BESCRS, "BESCRS",
- &spr_read_ebb, &spr_write_ebb,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BESCRSU, "BESCRSU",
- &spr_read_ebb_upper32, &spr_write_ebb_upper32,
- &spr_read_prev_upper32, &spr_write_prev_upper32,
- 0x00000000);
- spr_register(env, SPR_BESCRR, "BESCRR",
- &spr_read_ebb, &spr_write_ebb,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BESCRRU, "BESCRRU",
- &spr_read_ebb_upper32, &spr_write_ebb_upper32,
- &spr_read_prev_upper32, &spr_write_prev_upper32,
- 0x00000000);
- spr_register_kvm(env, SPR_EBBHR, "EBBHR",
- &spr_read_ebb, &spr_write_ebb,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_EBBHR, 0x00000000);
- spr_register_kvm(env, SPR_EBBRR, "EBBRR",
- &spr_read_ebb, &spr_write_ebb,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_EBBRR, 0x00000000);
- spr_register_kvm(env, SPR_BESCR, "BESCR",
- &spr_read_ebb, &spr_write_ebb,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_BESCR, 0x00000000);
-}
-
-/* Virtual Time Base */
-static void gen_spr_vtb(CPUPPCState *env)
-{
- spr_register_kvm_hv(env, SPR_VTB, "VTB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_vtb, SPR_NOACCESS,
- &spr_read_vtb, &spr_write_vtb,
- KVM_REG_PPC_VTB, 0x00000000);
-}
-
-static void gen_spr_power8_fscr(CPUPPCState *env)
-{
-#if defined(CONFIG_USER_ONLY)
- target_ulong initval = 1ULL << FSCR_TAR;
-#else
- target_ulong initval = 0;
-#endif
- spr_register_kvm(env, SPR_FSCR, "FSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_FSCR, initval);
-}
-
-static void gen_spr_power8_pspb(CPUPPCState *env)
-{
- spr_register_kvm(env, SPR_PSPB, "PSPB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic32,
- KVM_REG_PPC_PSPB, 0);
-}
-
-static void gen_spr_power8_dpdes(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- /* Directed Privileged Door-bell Exception State, used for IPI */
- spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dpdes, SPR_NOACCESS,
- &spr_read_dpdes, &spr_write_dpdes,
- KVM_REG_PPC_DPDES, 0x00000000);
-#endif
-}
-
-static void gen_spr_power8_ic(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register_hv(env, SPR_IC, "IC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0);
-#endif
-}
-
-static void gen_spr_power8_book4(CPUPPCState *env)
-{
- /* Add a number of P8 book4 registers */
-#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_ACOP, "ACOP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_ACOP, 0);
- spr_register_kvm(env, SPR_BOOKS_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pidr,
- KVM_REG_PPC_PID, 0);
- spr_register_kvm(env, SPR_WORT, "WORT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_WORT, 0);
-#endif
-}
-
-static void gen_spr_power7_book4(CPUPPCState *env)
-{
- /* Add a number of P7 book4 registers */
-#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_ACOP, "ACOP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_ACOP, 0);
- spr_register_kvm(env, SPR_BOOKS_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PID, 0);
-#endif
-}
-
-static void gen_spr_power8_rpr(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register_hv(env, SPR_RPR, "RPR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000103070F1F3F);
-#endif
-}
-
-static void gen_spr_power9_mmu(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- /* Partition Table Control */
- spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_ptcr,
- KVM_REG_PPC_PTCR, 0x00000000);
- /* Address Segment Descriptor Register */
- spr_register_hv(env, SPR_ASDR, "ASDR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x0000000000000000);
-#endif
-}
-
-static void init_proc_book3s_common(CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_tbl(env);
- gen_spr_usprg3(env);
- gen_spr_book3s_altivec(env);
- gen_spr_book3s_pmu_sup(env);
- gen_spr_book3s_pmu_user(env);
- gen_spr_book3s_ctrl(env);
-}
-
-static void init_proc_970(CPUPPCState *env)
-{
- /* Common Registers */
- init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
-
- /* 970 Specific Registers */
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
- gen_spr_970_lpar(env);
- gen_spr_970_dbg(env);
-
- /* env variables */
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- init_excp_970(env);
- ppc970_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 970";
- pcc->init_proc = init_proc_970;
- pcc->check_pow = check_pow_970;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC2_FP_CVT_S64;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI);
- pcc->mmu_model = POWERPC_MMU_64B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->hash64_opts = &ppc_hash64_opts_basic;
-#endif
- pcc->excp_model = POWERPC_EXCP_970;
- pcc->bus_model = PPC_FLAGS_INPUT_970;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x10000;
-}
-
-static void init_proc_power5plus(CPUPPCState *env)
-{
- /* Common Registers */
- init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
-
- /* POWER5+ Specific Registers */
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
-
- /* env variables */
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- init_excp_970(env);
- ppc970_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->fw_name = "PowerPC,POWER5";
- dc->desc = "POWER5+";
- pcc->init_proc = init_proc_power5plus;
- pcc->check_pow = check_pow_970;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B |
- PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC2_FP_CVT_S64;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI);
- pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
- LPCR_RMI | LPCR_HDICE;
- pcc->mmu_model = POWERPC_MMU_2_03;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->hash64_opts = &ppc_hash64_opts_basic;
- pcc->lrg_decr_bits = 32;
-#endif
- pcc->excp_model = POWERPC_EXCP_970;
- pcc->bus_model = PPC_FLAGS_INPUT_970;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x10000;
-}
-
-static void init_proc_POWER7(CPUPPCState *env)
-{
- /* Common Registers */
- init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
-
- /* POWER7 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_rmor(env);
- gen_spr_amr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power7_book4(env);
-
- /* env variables */
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- init_excp_POWER7(env);
- ppcPOWER7_irq_init(env_archcpu(env));
-}
-
-static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
-{
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
- return true;
- }
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
- return true;
- }
- return false;
-}
-
-static bool cpu_has_work_POWER7(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- if (cs->halted) {
- if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
- return false;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
- (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
- (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
- (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
- (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
- return true;
- }
- if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
- return true;
- }
- return false;
- } else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
- }
-}
-
-POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- dc->fw_name = "PowerPC,POWER7";
- dc->desc = "POWER7";
- pcc->pvr_match = ppc_pvr_match_power7;
- pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
- pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
- pcc->init_proc = init_proc_POWER7;
- pcc->check_pow = check_pow_nocheck;
- cc->has_work = cpu_has_work_POWER7;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_FRSQRTES |
- PPC_FLOAT_STFIWX |
- PPC_FLOAT_EXT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI |
- PPC_POPCNTB | PPC_POPCNTWD |
- PPC_CILDST;
- pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
- PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
- PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
- PPC2_PM_ISA206;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_VR) |
- (1ull << MSR_VSX) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
- LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
- LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
- LPCR_MER | LPCR_TC |
- LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
- pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
- pcc->mmu_model = POWERPC_MMU_2_06;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->hash64_opts = &ppc_hash64_opts_POWER7;
- pcc->lrg_decr_bits = 32;
-#endif
- pcc->excp_model = POWERPC_EXCP_POWER7;
- pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x8000;
- pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
-}
-
-static void init_proc_POWER8(CPUPPCState *env)
-{
- /* Common Registers */
- init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_207_dbg(env);
-
- /* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_rmor(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_power8_dpdes(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
-
- /* env variables */
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- init_excp_POWER8(env);
- ppcPOWER7_irq_init(env_archcpu(env));
-}
-
-static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
-{
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
- return true;
- }
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
- return true;
- }
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
- return true;
- }
- return false;
-}
-
-static bool cpu_has_work_POWER8(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- if (cs->halted) {
- if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
- return false;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
- (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
- (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
- (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
- (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
- (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
- return true;
- }
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
- (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
- return true;
- }
- if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
- return true;
- }
- return false;
- } else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
- }
-}
-
-POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- dc->fw_name = "PowerPC,POWER8";
- dc->desc = "POWER8";
- pcc->pvr_match = ppc_pvr_match_power8;
- pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
- pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
- pcc->init_proc = init_proc_POWER8;
- pcc->check_pow = check_pow_nocheck;
- cc->has_work = cpu_has_work_POWER8;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_FRSQRTES |
- PPC_FLOAT_STFIWX |
- PPC_FLOAT_EXT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI |
- PPC_POPCNTB | PPC_POPCNTWD |
- PPC_CILDST;
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
- PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
- PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
- PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
- PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_PM_ISA206;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_HV) |
- (1ull << MSR_TM) |
- (1ull << MSR_VR) |
- (1ull << MSR_VSX) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_TS0) |
- (1ull << MSR_TS1) |
- (1ull << MSR_LE);
- pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
- LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
- LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
- LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
- LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
- pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
- pcc->mmu_model = POWERPC_MMU_2_07;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->hash64_opts = &ppc_hash64_opts_POWER7;
- pcc->lrg_decr_bits = 32;
- pcc->n_host_threads = 8;
-#endif
- pcc->excp_model = POWERPC_EXCP_POWER8;
- pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x8000;
- pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
-}
-
-#ifdef CONFIG_SOFTMMU
-/*
- * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
- * Encoded as array of int_32s in the form:
- * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
- * x -> AP encoding
- * y -> radix mode supported page size (encoded as a shift)
- */
-static struct ppc_radix_page_info POWER9_radix_page_info = {
- .count = 4,
- .entries = {
- 0x0000000c, /* 4K - enc: 0x0 */
- 0xa0000010, /* 64K - enc: 0x5 */
- 0x20000015, /* 2M - enc: 0x1 */
- 0x4000001e /* 1G - enc: 0x2 */
- }
-};
-#endif /* CONFIG_SOFTMMU */
-
-static void init_proc_POWER9(CPUPPCState *env)
-{
- /* Common Registers */
- init_proc_book3s_common(env);
- gen_spr_book3s_207_dbg(env);
-
- /* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_power8_dpdes(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
- gen_spr_power9_mmu(env);
-
- /* POWER9 Specific registers */
- spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
- spr_read_generic, spr_write_generic,
- KVM_REG_PPC_TIDR, 0);
-
- /* FIXME: Filter fields properly based on privilege level */
- spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
- spr_read_generic, spr_write_generic,
- KVM_REG_PPC_PSSCR, 0);
-
- /* env variables */
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- init_excp_POWER9(env);
- ppcPOWER9_irq_init(env_archcpu(env));
-}
-
-static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
-{
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
- return true;
- }
- return false;
-}
-
-static bool cpu_has_work_POWER9(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- if (cs->halted) {
- uint64_t psscr = env->spr[SPR_PSSCR];
-
- if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
- return false;
- }
-
- /* If EC is clear, just return true on any pending interrupt */
- if (!(psscr & PSSCR_EC)) {
- return true;
- }
- /* External Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
- (env->spr[SPR_LPCR] & LPCR_EEE)) {
- bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
- if (heic == 0 || !msr_hv || msr_pr) {
- return true;
- }
- }
- /* Decrementer Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
- (env->spr[SPR_LPCR] & LPCR_DEE)) {
- return true;
- }
- /* Machine Check or Hypervisor Maintenance Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
- 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
- return true;
- }
- /* Privileged Doorbell Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
- (env->spr[SPR_LPCR] & LPCR_PDEE)) {
- return true;
- }
- /* Hypervisor Doorbell Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
- (env->spr[SPR_LPCR] & LPCR_HDEE)) {
- return true;
- }
- /* Hypervisor virtualization exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
- (env->spr[SPR_LPCR] & LPCR_HVEE)) {
- return true;
- }
- if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
- return true;
- }
- return false;
- } else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
- }
-}
-
-POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- dc->fw_name = "PowerPC,POWER9";
- dc->desc = "POWER9";
- pcc->pvr_match = ppc_pvr_match_power9;
- pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
- pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
- PCR_COMPAT_2_05;
- pcc->init_proc = init_proc_POWER9;
- pcc->check_pow = check_pow_nocheck;
- cc->has_work = cpu_has_work_POWER9;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_FRSQRTES |
- PPC_FLOAT_STFIWX |
- PPC_FLOAT_EXT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBSYNC |
- PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI |
- PPC_POPCNTB | PPC_POPCNTWD |
- PPC_CILDST;
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
- PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
- PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
- PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
- PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_HV) |
- (1ull << MSR_TM) |
- (1ull << MSR_VR) |
- (1ull << MSR_VSX) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
- (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
- LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
- (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
- LPCR_DEE | LPCR_OEE))
- | LPCR_MER | LPCR_GTSE | LPCR_TC |
- LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
- pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
- pcc->mmu_model = POWERPC_MMU_3_00;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
- /* segment page size remain the same */
- pcc->hash64_opts = &ppc_hash64_opts_POWER7;
- pcc->radix_page_info = &POWER9_radix_page_info;
- pcc->lrg_decr_bits = 56;
- pcc->n_host_threads = 4;
-#endif
- pcc->excp_model = POWERPC_EXCP_POWER9;
- pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x8000;
- pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
-}
-
-#ifdef CONFIG_SOFTMMU
-/*
- * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
- * Encoded as array of int_32s in the form:
- * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
- * x -> AP encoding
- * y -> radix mode supported page size (encoded as a shift)
- */
-static struct ppc_radix_page_info POWER10_radix_page_info = {
- .count = 4,
- .entries = {
- 0x0000000c, /* 4K - enc: 0x0 */
- 0xa0000010, /* 64K - enc: 0x5 */
- 0x20000015, /* 2M - enc: 0x1 */
- 0x4000001e /* 1G - enc: 0x2 */
- }
-};
-#endif /* CONFIG_SOFTMMU */
-
-static void init_proc_POWER10(CPUPPCState *env)
-{
- /* Common Registers */
- init_proc_book3s_common(env);
- gen_spr_book3s_207_dbg(env);
-
- /* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
- gen_spr_power9_mmu(env);
-
- /* FIXME: Filter fields properly based on privilege level */
- spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
- spr_read_generic, spr_write_generic,
- KVM_REG_PPC_PSSCR, 0);
-
- /* env variables */
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- init_excp_POWER10(env);
- ppcPOWER9_irq_init(env_archcpu(env));
-}
-
-static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
-{
- if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
- return true;
- }
- return false;
-}
-
-static bool cpu_has_work_POWER10(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- if (cs->halted) {
- uint64_t psscr = env->spr[SPR_PSSCR];
-
- if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
- return false;
- }
-
- /* If EC is clear, just return true on any pending interrupt */
- if (!(psscr & PSSCR_EC)) {
- return true;
- }
- /* External Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
- (env->spr[SPR_LPCR] & LPCR_EEE)) {
- bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
- if (heic == 0 || !msr_hv || msr_pr) {
- return true;
- }
- }
- /* Decrementer Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
- (env->spr[SPR_LPCR] & LPCR_DEE)) {
- return true;
- }
- /* Machine Check or Hypervisor Maintenance Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
- 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
- return true;
- }
- /* Privileged Doorbell Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
- (env->spr[SPR_LPCR] & LPCR_PDEE)) {
- return true;
- }
- /* Hypervisor Doorbell Exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
- (env->spr[SPR_LPCR] & LPCR_HDEE)) {
- return true;
- }
- /* Hypervisor virtualization exception */
- if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
- (env->spr[SPR_LPCR] & LPCR_HVEE)) {
- return true;
- }
- if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
- return true;
- }
- return false;
- } else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
- }
-}
-
-POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- dc->fw_name = "PowerPC,POWER10";
- dc->desc = "POWER10";
- pcc->pvr_match = ppc_pvr_match_power10;
- pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
- PCR_COMPAT_3_00;
- pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
- PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
- pcc->init_proc = init_proc_POWER10;
- pcc->check_pow = check_pow_nocheck;
- cc->has_work = cpu_has_work_POWER10;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_FRSQRTES |
- PPC_FLOAT_STFIWX |
- PPC_FLOAT_EXT |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBSYNC |
- PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI |
- PPC_POPCNTB | PPC_POPCNTWD |
- PPC_CILDST;
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
- PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
- PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
- PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
- PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_HV) |
- (1ull << MSR_TM) |
- (1ull << MSR_VR) |
- (1ull << MSR_VSX) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
- (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
- LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
- (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
- LPCR_DEE | LPCR_OEE))
- | LPCR_MER | LPCR_GTSE | LPCR_TC |
- LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
- pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
- pcc->mmu_model = POWERPC_MMU_3_00;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
- /* segment page size remain the same */
- pcc->hash64_opts = &ppc_hash64_opts_POWER7;
- pcc->radix_page_info = &POWER10_radix_page_info;
- pcc->lrg_decr_bits = 56;
-#endif
- pcc->excp_model = POWERPC_EXCP_POWER9;
- pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x8000;
- pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
-}
-
-#if !defined(CONFIG_USER_ONLY)
-void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
-{
- CPUPPCState *env = &cpu->env;
-
- cpu->vhyp = vhyp;
-
- /*
- * With a virtual hypervisor mode we never allow the CPU to go
- * hypervisor mode itself
- */
- env->msr_mask &= ~MSR_HVB;
-}
-
-#endif /* !defined(CONFIG_USER_ONLY) */
-
-#endif /* defined(TARGET_PPC64) */
-
-/*****************************************************************************/
-/* Generic CPU instantiation routine */
-static void init_ppc_proc(PowerPCCPU *cpu)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- CPUPPCState *env = &cpu->env;
-#if !defined(CONFIG_USER_ONLY)
- int i;
-
- env->irq_inputs = NULL;
- /* Set all exception vectors to an invalid address */
- for (i = 0; i < POWERPC_EXCP_NB; i++) {
- env->excp_vectors[i] = (target_ulong)(-1ULL);
- }
- env->ivor_mask = 0x00000000;
- env->ivpr_mask = 0x00000000;
- /* Default MMU definitions */
- env->nb_BATs = 0;
- env->nb_tlb = 0;
- env->nb_ways = 0;
- env->tlb_type = TLB_NONE;
-#endif
- /* Register SPR common to all PowerPC implementations */
- gen_spr_generic(env);
- spr_register(env, SPR_PVR, "PVR",
- /* Linux permits userspace to read PVR */
-#if defined(CONFIG_LINUX_USER)
- &spr_read_generic,
-#else
- SPR_NOACCESS,
-#endif
- SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->pvr);
- /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
- if (pcc->svr != POWERPC_SVR_NONE) {
- if (pcc->svr & POWERPC_SVR_E500) {
- spr_register(env, SPR_E500_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr & ~POWERPC_SVR_E500);
- } else {
- spr_register(env, SPR_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr);
- }
- }
- /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
- (*pcc->init_proc)(env);
-
-#if !defined(CONFIG_USER_ONLY)
- ppc_gdb_gen_spr_xml(cpu);
-#endif
-
- /* MSR bits & flags consistency checks */
- if (env->msr_mask & (1 << 25)) {
- switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
- case POWERPC_FLAG_SPE:
- case POWERPC_FLAG_VRE:
- break;
- default:
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
- exit(1);
- }
- } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
- exit(1);
- }
- if (env->msr_mask & (1 << 17)) {
- switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
- case POWERPC_FLAG_TGPR:
- case POWERPC_FLAG_CE:
- break;
- default:
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
- exit(1);
- }
- } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
- exit(1);
- }
- if (env->msr_mask & (1 << 10)) {
- switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_UBLE)) {
- case POWERPC_FLAG_SE:
- case POWERPC_FLAG_DWE:
- case POWERPC_FLAG_UBLE:
- break;
- default:
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
- "POWERPC_FLAG_UBLE\n");
- exit(1);
- }
- } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_UBLE)) {
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
- "POWERPC_FLAG_UBLE\n");
- exit(1);
- }
- if (env->msr_mask & (1 << 9)) {
- switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
- case POWERPC_FLAG_BE:
- case POWERPC_FLAG_DE:
- break;
- default:
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
- exit(1);
- }
- } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
- exit(1);
- }
- if (env->msr_mask & (1 << 2)) {
- switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
- case POWERPC_FLAG_PX:
- case POWERPC_FLAG_PMM:
- break;
- default:
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
- exit(1);
- }
- } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
- fprintf(stderr, "PowerPC MSR definition inconsistency\n"
- "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
- exit(1);
- }
- if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
- fprintf(stderr, "PowerPC flags inconsistency\n"
- "Should define the time-base and decrementer clock source\n");
- exit(1);
- }
- /* Allocate TLBs buffer when needed */
-#if !defined(CONFIG_USER_ONLY)
- if (env->nb_tlb != 0) {
- int nb_tlb = env->nb_tlb;
- if (env->id_tlbs != 0) {
- nb_tlb *= 2;
- }
- switch (env->tlb_type) {
- case TLB_6XX:
- env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
- break;
- case TLB_EMB:
- env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
- break;
- case TLB_MAS:
- env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
- break;
- }
- /* Pre-compute some useful values */
- env->tlb_per_way = env->nb_tlb / env->nb_ways;
- }
- if (env->irq_inputs == NULL) {
- warn_report("no internal IRQ controller registered."
- " Attempt QEMU to crash very soon !");
- }
-#endif
- if (env->check_pow == NULL) {
- warn_report("no power management check handler registered."
- " Attempt QEMU to crash very soon !");
- }
-}
-
-#if defined(PPC_DUMP_CPU)
-static void dump_ppc_sprs(CPUPPCState *env)
-{
- ppc_spr_t *spr;
-#if !defined(CONFIG_USER_ONLY)
- uint32_t sr, sw;
-#endif
- uint32_t ur, uw;
- int i, j, n;
-
- printf("Special purpose registers:\n");
- for (i = 0; i < 32; i++) {
- for (j = 0; j < 32; j++) {
- n = (i << 5) | j;
- spr = &env->spr_cb[n];
- uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
- ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
-#if !defined(CONFIG_USER_ONLY)
- sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
- sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
- if (sw || sr || uw || ur) {
- printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
- (i << 5) | j, (i << 5) | j, spr->name,
- sw ? 'w' : '-', sr ? 'r' : '-',
- uw ? 'w' : '-', ur ? 'r' : '-');
- }
-#else
- if (uw || ur) {
- printf("SPR: %4d (%03x) %-8s u%c%c\n",
- (i << 5) | j, (i << 5) | j, spr->name,
- uw ? 'w' : '-', ur ? 'r' : '-');
- }
-#endif
- }
- }
- fflush(stdout);
- fflush(stderr);
-}
-#endif
-
-/*****************************************************************************/
-
-/* Opcode types */
-enum {
- PPC_DIRECT = 0, /* Opcode routine */
- PPC_INDIRECT = 1, /* Indirect opcode table */
-};
-
-#define PPC_OPCODE_MASK 0x3
-
-static inline int is_indirect_opcode(void *handler)
-{
- return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
-}
-
-static inline opc_handler_t **ind_table(void *handler)
-{
- return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
-}
-
-/* Instruction table creation */
-/* Opcodes tables creation */
-static void fill_new_table(opc_handler_t **table, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- table[i] = &invalid_handler;
- }
-}
-
-static int create_new_table(opc_handler_t **table, unsigned char idx)
-{
- opc_handler_t **tmp;
-
- tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
- fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
- table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
-
- return 0;
-}
-
-static int insert_in_table(opc_handler_t **table, unsigned char idx,
- opc_handler_t *handler)
-{
- if (table[idx] != &invalid_handler) {
- return -1;
- }
- table[idx] = handler;
-
- return 0;
-}
-
-static int register_direct_insn(opc_handler_t **ppc_opcodes,
- unsigned char idx, opc_handler_t *handler)
-{
- if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
- printf("*** ERROR: opcode %02x already assigned in main "
- "opcode table\n", idx);
-#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
- printf(" Registered handler '%s' - new handler '%s'\n",
- ppc_opcodes[idx]->oname, handler->oname);
-#endif
- return -1;
- }
-
- return 0;
-}
-
-static int register_ind_in_table(opc_handler_t **table,
- unsigned char idx1, unsigned char idx2,
- opc_handler_t *handler)
-{
- if (table[idx1] == &invalid_handler) {
- if (create_new_table(table, idx1) < 0) {
- printf("*** ERROR: unable to create indirect table "
- "idx=%02x\n", idx1);
- return -1;
- }
- } else {
- if (!is_indirect_opcode(table[idx1])) {
- printf("*** ERROR: idx %02x already assigned to a direct "
- "opcode\n", idx1);
-#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
- printf(" Registered handler '%s' - new handler '%s'\n",
- ind_table(table[idx1])[idx2]->oname, handler->oname);
-#endif
- return -1;
- }
- }
- if (handler != NULL &&
- insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
- printf("*** ERROR: opcode %02x already assigned in "
- "opcode table %02x\n", idx2, idx1);
-#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
- printf(" Registered handler '%s' - new handler '%s'\n",
- ind_table(table[idx1])[idx2]->oname, handler->oname);
-#endif
- return -1;
- }
-
- return 0;
-}
-
-static int register_ind_insn(opc_handler_t **ppc_opcodes,
- unsigned char idx1, unsigned char idx2,
- opc_handler_t *handler)
-{
- return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
-}
-
-static int register_dblind_insn(opc_handler_t **ppc_opcodes,
- unsigned char idx1, unsigned char idx2,
- unsigned char idx3, opc_handler_t *handler)
-{
- if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
- printf("*** ERROR: unable to join indirect table idx "
- "[%02x-%02x]\n", idx1, idx2);
- return -1;
- }
- if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
- handler) < 0) {
- printf("*** ERROR: unable to insert opcode "
- "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
- return -1;
- }
-
- return 0;
-}
-
-static int register_trplind_insn(opc_handler_t **ppc_opcodes,
- unsigned char idx1, unsigned char idx2,
- unsigned char idx3, unsigned char idx4,
- opc_handler_t *handler)
-{
- opc_handler_t **table;
-
- if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
- printf("*** ERROR: unable to join indirect table idx "
- "[%02x-%02x]\n", idx1, idx2);
- return -1;
- }
- table = ind_table(ppc_opcodes[idx1]);
- if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
- printf("*** ERROR: unable to join 2nd-level indirect table idx "
- "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
- return -1;
- }
- table = ind_table(table[idx2]);
- if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
- printf("*** ERROR: unable to insert opcode "
- "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
- return -1;
- }
- return 0;
-}
-static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
-{
- if (insn->opc2 != 0xFF) {
- if (insn->opc3 != 0xFF) {
- if (insn->opc4 != 0xFF) {
- if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
- insn->opc3, insn->opc4,
- &insn->handler) < 0) {
- return -1;
- }
- } else {
- if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
- insn->opc3, &insn->handler) < 0) {
- return -1;
- }
- }
- } else {
- if (register_ind_insn(ppc_opcodes, insn->opc1,
- insn->opc2, &insn->handler) < 0) {
- return -1;
- }
- }
- } else {
- if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
- return -1;
- }
- }
-
- return 0;
-}
-
-static int test_opcode_table(opc_handler_t **table, int len)
-{
- int i, count, tmp;
-
- for (i = 0, count = 0; i < len; i++) {
- /* Consistency fixup */
- if (table[i] == NULL) {
- table[i] = &invalid_handler;
- }
- if (table[i] != &invalid_handler) {
- if (is_indirect_opcode(table[i])) {
- tmp = test_opcode_table(ind_table(table[i]),
- PPC_CPU_INDIRECT_OPCODES_LEN);
- if (tmp == 0) {
- free(table[i]);
- table[i] = &invalid_handler;
- } else {
- count++;
- }
- } else {
- count++;
- }
- }
- }
-
- return count;
-}
-
-static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
-{
- if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
- printf("*** WARNING: no opcode defined !\n");
- }
-}
-
-/*****************************************************************************/
-static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- opcode_t *opc;
-
- fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
- for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
- if (((opc->handler.type & pcc->insns_flags) != 0) ||
- ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
- if (register_insn(cpu->opcodes, opc) < 0) {
- error_setg(errp, "ERROR initializing PowerPC instruction "
- "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
- opc->opc3);
- return;
- }
- }
- }
- fix_opcode_tables(cpu->opcodes);
- fflush(stdout);
- fflush(stderr);
-}
-
-#if defined(PPC_DUMP_CPU)
-static void dump_ppc_insns(CPUPPCState *env)
-{
- opc_handler_t **table, *handler;
- const char *p, *q;
- uint8_t opc1, opc2, opc3, opc4;
-
- printf("Instructions set:\n");
- /* opc1 is 6 bits long */
- for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
- table = env->opcodes;
- handler = table[opc1];
- if (is_indirect_opcode(handler)) {
- /* opc2 is 5 bits long */
- for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
- table = env->opcodes;
- handler = env->opcodes[opc1];
- table = ind_table(handler);
- handler = table[opc2];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- /* opc3 is 5 bits long */
- for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
- opc3++) {
- handler = table[opc3];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- /* opc4 is 5 bits long */
- for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
- opc4++) {
- handler = table[opc4];
- if (handler->handler != &gen_invalid) {
- printf("INSN: %02x %02x %02x %02x -- "
- "(%02d %04d %02d) : %s\n",
- opc1, opc2, opc3, opc4,
- opc1, (opc3 << 5) | opc2, opc4,
- handler->oname);
- }
- }
- } else {
- if (handler->handler != &gen_invalid) {
- /* Special hack to properly dump SPE insns */
- p = strchr(handler->oname, '_');
- if (p == NULL) {
- printf("INSN: %02x %02x %02x (%02d %04d) : "
- "%s\n",
- opc1, opc2, opc3, opc1,
- (opc3 << 5) | opc2,
- handler->oname);
- } else {
- q = "speundef";
- if ((p - handler->oname) != strlen(q)
- || (memcmp(handler->oname, q, strlen(q))
- != 0)) {
- /* First instruction */
- printf("INSN: %02x %02x %02x"
- "(%02d %04d) : %.*s\n",
- opc1, opc2 << 1, opc3, opc1,
- (opc3 << 6) | (opc2 << 1),
- (int)(p - handler->oname),
- handler->oname);
- }
- if (strcmp(p + 1, q) != 0) {
- /* Second instruction */
- printf("INSN: %02x %02x %02x "
- "(%02d %04d) : %s\n", opc1,
- (opc2 << 1) | 1, opc3, opc1,
- (opc3 << 6) | (opc2 << 1) | 1,
- p + 1);
- }
- }
- }
- }
- }
- } else {
- if (handler->handler != &gen_invalid) {
- printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
- opc1, opc2, opc1, opc2, handler->oname);
- }
- }
- }
- } else {
- if (handler->handler != &gen_invalid) {
- printf("INSN: %02x -- -- (%02d ----) : %s\n",
- opc1, opc1, handler->oname);
- }
- }
- }
-}
-#endif
-
-static bool avr_need_swap(CPUPPCState *env)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return msr_le;
-#else
- return !msr_le;
-#endif
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static int gdb_find_spr_idx(CPUPPCState *env, int n)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
- ppc_spr_t *spr = &env->spr_cb[i];
-
- if (spr->name && spr->gdb_id == n) {
- return i;
- }
- }
- return -1;
-}
-
-static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
-{
- int reg;
- int len;
-
- reg = gdb_find_spr_idx(env, n);
- if (reg < 0) {
- return 0;
- }
-
- len = TARGET_LONG_SIZE;
- gdb_get_regl(buf, env->spr[reg]);
- ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
- return len;
-}
-
-static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- int reg;
- int len;
-
- reg = gdb_find_spr_idx(env, n);
- if (reg < 0) {
- return 0;
- }
-
- len = TARGET_LONG_SIZE;
- ppc_maybe_bswap_register(env, mem_buf, len);
- env->spr[reg] = ldn_p(mem_buf, len);
-
- return len;
-}
-#endif
-
-static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
-{
- uint8_t *mem_buf;
- if (n < 32) {
- gdb_get_float64(buf, *cpu_fpr_ptr(env, n));
- mem_buf = gdb_get_reg_ptr(buf, 8);
- ppc_maybe_bswap_register(env, mem_buf, 8);
- return 8;
- }
- if (n == 32) {
- gdb_get_reg32(buf, env->fpscr);
- mem_buf = gdb_get_reg_ptr(buf, 4);
- ppc_maybe_bswap_register(env, mem_buf, 4);
- return 4;
- }
- return 0;
-}
-
-static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- ppc_maybe_bswap_register(env, mem_buf, 8);
- *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf);
- return 8;
- }
- if (n == 32) {
- ppc_maybe_bswap_register(env, mem_buf, 4);
- helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
- return 4;
- }
- return 0;
-}
-
-static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
-{
- uint8_t *mem_buf;
-
- if (n < 32) {
- ppc_avr_t *avr = cpu_avr_ptr(env, n);
- if (!avr_need_swap(env)) {
- gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
- } else {
- gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
- }
- mem_buf = gdb_get_reg_ptr(buf, 16);
- ppc_maybe_bswap_register(env, mem_buf, 8);
- ppc_maybe_bswap_register(env, mem_buf + 8, 8);
- return 16;
- }
- if (n == 32) {
- gdb_get_reg32(buf, helper_mfvscr(env));
- mem_buf = gdb_get_reg_ptr(buf, 4);
- ppc_maybe_bswap_register(env, mem_buf, 4);
- return 4;
- }
- if (n == 33) {
- gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
- mem_buf = gdb_get_reg_ptr(buf, 4);
- ppc_maybe_bswap_register(env, mem_buf, 4);
- return 4;
- }
- return 0;
-}
-
-static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- ppc_avr_t *avr = cpu_avr_ptr(env, n);
- ppc_maybe_bswap_register(env, mem_buf, 8);
- ppc_maybe_bswap_register(env, mem_buf + 8, 8);
- if (!avr_need_swap(env)) {
- avr->u64[0] = ldq_p(mem_buf);
- avr->u64[1] = ldq_p(mem_buf + 8);
- } else {
- avr->u64[1] = ldq_p(mem_buf);
- avr->u64[0] = ldq_p(mem_buf + 8);
- }
- return 16;
- }
- if (n == 32) {
- ppc_maybe_bswap_register(env, mem_buf, 4);
- helper_mtvscr(env, ldl_p(mem_buf));
- return 4;
- }
- if (n == 33) {
- ppc_maybe_bswap_register(env, mem_buf, 4);
- env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
- return 4;
- }
- return 0;
-}
-
-static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
-{
- if (n < 32) {
-#if defined(TARGET_PPC64)
- gdb_get_reg32(buf, env->gpr[n] >> 32);
- ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
-#else
- gdb_get_reg32(buf, env->gprh[n]);
-#endif
- return 4;
- }
- if (n == 32) {
- gdb_get_reg64(buf, env->spe_acc);
- ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
- return 8;
- }
- if (n == 33) {
- gdb_get_reg32(buf, env->spe_fscr);
- ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
- return 4;
- }
- return 0;
-}
-
-static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
-#if defined(TARGET_PPC64)
- target_ulong lo = (uint32_t)env->gpr[n];
- target_ulong hi;
-
- ppc_maybe_bswap_register(env, mem_buf, 4);
-
- hi = (target_ulong)ldl_p(mem_buf) << 32;
- env->gpr[n] = lo | hi;
-#else
- env->gprh[n] = ldl_p(mem_buf);
-#endif
- return 4;
- }
- if (n == 32) {
- ppc_maybe_bswap_register(env, mem_buf, 8);
- env->spe_acc = ldq_p(mem_buf);
- return 8;
- }
- if (n == 33) {
- ppc_maybe_bswap_register(env, mem_buf, 4);
- env->spe_fscr = ldl_p(mem_buf);
- return 4;
- }
- return 0;
-}
-
-static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
-{
- if (n < 32) {
- gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
- ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
- return 8;
- }
- return 0;
-}
-
-static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
-{
- if (n < 32) {
- ppc_maybe_bswap_register(env, mem_buf, 8);
- *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
- return 8;
- }
- return 0;
-}
-
-static int ppc_fixup_cpu(PowerPCCPU *cpu)
-{
- CPUPPCState *env = &cpu->env;
-
- /*
- * TCG doesn't (yet) emulate some groups of instructions that are
- * implemented on some otherwise supported CPUs (e.g. VSX and
- * decimal floating point instructions on POWER7). We remove
- * unsupported instruction groups from the cpu state's instruction
- * masks and hope the guest can cope. For at least the pseries
- * machine, the unavailability of these instructions can be
- * advertised to the guest via the device tree.
- */
- if ((env->insns_flags & ~PPC_TCG_INSNS)
- || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
- warn_report("Disabling some instructions which are not "
- "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
- env->insns_flags & ~PPC_TCG_INSNS,
- env->insns_flags2 & ~PPC_TCG_INSNS2);
- }
- env->insns_flags &= PPC_TCG_INSNS;
- env->insns_flags2 &= PPC_TCG_INSNS2;
- return 0;
-}
-
-static void ppc_cpu_realize(DeviceState *dev, Error **errp)
-{
- CPUState *cs = CPU(dev);
- PowerPCCPU *cpu = POWERPC_CPU(dev);
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- Error *local_err = NULL;
-
- cpu_exec_realizefn(cs, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
- if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
- cpu->vcpu_id = cs->cpu_index;
- }
-
- if (tcg_enabled()) {
- if (ppc_fixup_cpu(cpu) != 0) {
- error_setg(errp, "Unable to emulate selected CPU with TCG");
- goto unrealize;
- }
- }
-
- create_ppc_opcodes(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- goto unrealize;
- }
- init_ppc_proc(cpu);
-
- if (pcc->insns_flags & PPC_FLOAT) {
- gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
- 33, "power-fpu.xml", 0);
- }
- if (pcc->insns_flags & PPC_ALTIVEC) {
- gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
- 34, "power-altivec.xml", 0);
- }
- if (pcc->insns_flags & PPC_SPE) {
- gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
- 34, "power-spe.xml", 0);
- }
- if (pcc->insns_flags2 & PPC2_VSX) {
- gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
- 32, "power-vsx.xml", 0);
- }
-#ifndef CONFIG_USER_ONLY
- gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
- pcc->gdb_num_sprs, "power-spr.xml", 0);
-#endif
- qemu_init_vcpu(cs);
-
- pcc->parent_realize(dev, errp);
-
-#if defined(PPC_DUMP_CPU)
- {
- CPUPPCState *env = &cpu->env;
- const char *mmu_model, *excp_model, *bus_model;
- switch (env->mmu_model) {
- case POWERPC_MMU_32B:
- mmu_model = "PowerPC 32";
- break;
- case POWERPC_MMU_SOFT_6xx:
- mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
- break;
- case POWERPC_MMU_SOFT_74xx:
- mmu_model = "PowerPC 74xx with software driven TLBs";
- break;
- case POWERPC_MMU_SOFT_4xx:
- mmu_model = "PowerPC 4xx with software driven TLBs";
- break;
- case POWERPC_MMU_SOFT_4xx_Z:
- mmu_model = "PowerPC 4xx with software driven TLBs "
- "and zones protections";
- break;
- case POWERPC_MMU_REAL:
- mmu_model = "PowerPC real mode only";
- break;
- case POWERPC_MMU_MPC8xx:
- mmu_model = "PowerPC MPC8xx";
- break;
- case POWERPC_MMU_BOOKE:
- mmu_model = "PowerPC BookE";
- break;
- case POWERPC_MMU_BOOKE206:
- mmu_model = "PowerPC BookE 2.06";
- break;
- case POWERPC_MMU_601:
- mmu_model = "PowerPC 601";
- break;
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_64B:
- mmu_model = "PowerPC 64";
- break;
-#endif
- default:
- mmu_model = "Unknown or invalid";
- break;
- }
- switch (env->excp_model) {
- case POWERPC_EXCP_STD:
- excp_model = "PowerPC";
- break;
- case POWERPC_EXCP_40x:
- excp_model = "PowerPC 40x";
- break;
- case POWERPC_EXCP_601:
- excp_model = "PowerPC 601";
- break;
- case POWERPC_EXCP_602:
- excp_model = "PowerPC 602";
- break;
- case POWERPC_EXCP_603:
- excp_model = "PowerPC 603";
- break;
- case POWERPC_EXCP_603E:
- excp_model = "PowerPC 603e";
- break;
- case POWERPC_EXCP_604:
- excp_model = "PowerPC 604";
- break;
- case POWERPC_EXCP_7x0:
- excp_model = "PowerPC 740/750";
- break;
- case POWERPC_EXCP_7x5:
- excp_model = "PowerPC 745/755";
- break;
- case POWERPC_EXCP_74xx:
- excp_model = "PowerPC 74xx";
- break;
- case POWERPC_EXCP_BOOKE:
- excp_model = "PowerPC BookE";
- break;
-#if defined(TARGET_PPC64)
- case POWERPC_EXCP_970:
- excp_model = "PowerPC 970";
- break;
-#endif
- default:
- excp_model = "Unknown or invalid";
- break;
- }
- switch (env->bus_model) {
- case PPC_FLAGS_INPUT_6xx:
- bus_model = "PowerPC 6xx";
- break;
- case PPC_FLAGS_INPUT_BookE:
- bus_model = "PowerPC BookE";
- break;
- case PPC_FLAGS_INPUT_405:
- bus_model = "PowerPC 405";
- break;
- case PPC_FLAGS_INPUT_401:
- bus_model = "PowerPC 401/403";
- break;
- case PPC_FLAGS_INPUT_RCPU:
- bus_model = "RCPU / MPC8xx";
- break;
-#if defined(TARGET_PPC64)
- case PPC_FLAGS_INPUT_970:
- bus_model = "PowerPC 970";
- break;
-#endif
- default:
- bus_model = "Unknown or invalid";
- break;
- }
- printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
- " MMU model : %s\n",
- object_class_get_name(OBJECT_CLASS(pcc)),
- pcc->pvr, pcc->msr_mask, mmu_model);
-#if !defined(CONFIG_USER_ONLY)
- if (env->tlb.tlb6) {
- printf(" %d %s TLB in %d ways\n",
- env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
- env->nb_ways);
- }
-#endif
- printf(" Exceptions model : %s\n"
- " Bus model : %s\n",
- excp_model, bus_model);
- printf(" MSR features :\n");
- if (env->flags & POWERPC_FLAG_SPE) {
- printf(" signal processing engine enable"
- "\n");
- } else if (env->flags & POWERPC_FLAG_VRE) {
- printf(" vector processor enable\n");
- }
- if (env->flags & POWERPC_FLAG_TGPR) {
- printf(" temporary GPRs\n");
- } else if (env->flags & POWERPC_FLAG_CE) {
- printf(" critical input enable\n");
- }
- if (env->flags & POWERPC_FLAG_SE) {
- printf(" single-step trace mode\n");
- } else if (env->flags & POWERPC_FLAG_DWE) {
- printf(" debug wait enable\n");
- } else if (env->flags & POWERPC_FLAG_UBLE) {
- printf(" user BTB lock enable\n");
- }
- if (env->flags & POWERPC_FLAG_BE) {
- printf(" branch-step trace mode\n");
- } else if (env->flags & POWERPC_FLAG_DE) {
- printf(" debug interrupt enable\n");
- }
- if (env->flags & POWERPC_FLAG_PX) {
- printf(" inclusive protection\n");
- } else if (env->flags & POWERPC_FLAG_PMM) {
- printf(" performance monitor mark\n");
- }
- if (env->flags == POWERPC_FLAG_NONE) {
- printf(" none\n");
- }
- printf(" Time-base/decrementer clock source: %s\n",
- env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
- dump_ppc_insns(env);
- dump_ppc_sprs(env);
- fflush(stdout);
- }
-#endif
- return;
-
-unrealize:
- cpu_exec_unrealizefn(cs);
-}
-
-static void ppc_cpu_unrealize(DeviceState *dev)
-{
- PowerPCCPU *cpu = POWERPC_CPU(dev);
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- opc_handler_t **table, **table_2;
- int i, j, k;
-
- pcc->parent_unrealize(dev);
-
- for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
- if (cpu->opcodes[i] == &invalid_handler) {
- continue;
- }
- if (is_indirect_opcode(cpu->opcodes[i])) {
- table = ind_table(cpu->opcodes[i]);
- for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
- if (table[j] == &invalid_handler) {
- continue;
- }
- if (is_indirect_opcode(table[j])) {
- table_2 = ind_table(table[j]);
- for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
- if (table_2[k] != &invalid_handler &&
- is_indirect_opcode(table_2[k])) {
- g_free((opc_handler_t *)((uintptr_t)table_2[k] &
- ~PPC_INDIRECT));
- }
- }
- g_free((opc_handler_t *)((uintptr_t)table[j] &
- ~PPC_INDIRECT));
- }
- }
- g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
- ~PPC_INDIRECT));
- }
- }
-}
-
-static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
-{
- ObjectClass *oc = (ObjectClass *)a;
- uint32_t pvr = *(uint32_t *)b;
- PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
-
- /* -cpu host does a PVR lookup during construction */
- if (unlikely(strcmp(object_class_get_name(oc),
- TYPE_HOST_POWERPC_CPU) == 0)) {
- return -1;
- }
-
- return pcc->pvr == pvr ? 0 : -1;
-}
-
-PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
-{
- GSList *list, *item;
- PowerPCCPUClass *pcc = NULL;
-
- list = object_class_get_list(TYPE_POWERPC_CPU, false);
- item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
- if (item != NULL) {
- pcc = POWERPC_CPU_CLASS(item->data);
- }
- g_slist_free(list);
-
- return pcc;
-}
-
-static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
-{
- ObjectClass *oc = (ObjectClass *)a;
- uint32_t pvr = *(uint32_t *)b;
- PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
-
- /* -cpu host does a PVR lookup during construction */
- if (unlikely(strcmp(object_class_get_name(oc),
- TYPE_HOST_POWERPC_CPU) == 0)) {
- return -1;
- }
-
- if (pcc->pvr_match(pcc, pvr)) {
- return 0;
- }
-
- return -1;
-}
-
-PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
-{
- GSList *list, *item;
- PowerPCCPUClass *pcc = NULL;
-
- list = object_class_get_list(TYPE_POWERPC_CPU, true);
- item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
- if (item != NULL) {
- pcc = POWERPC_CPU_CLASS(item->data);
- }
- g_slist_free(list);
-
- return pcc;
-}
-
-static const char *ppc_cpu_lookup_alias(const char *alias)
-{
- int ai;
-
- for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
- if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
- return ppc_cpu_aliases[ai].model;
- }
- }
-
- return NULL;
-}
-
-static ObjectClass *ppc_cpu_class_by_name(const char *name)
-{
- char *cpu_model, *typename;
- ObjectClass *oc;
- const char *p;
- unsigned long pvr;
-
- /*
- * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
- * 0x prefix if present)
- */
- if (!qemu_strtoul(name, &p, 16, &pvr)) {
- int len = p - name;
- len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
- if ((len == 8) && (*p == '\0')) {
- return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
- }
- }
-
- cpu_model = g_ascii_strdown(name, -1);
- p = ppc_cpu_lookup_alias(cpu_model);
- if (p) {
- g_free(cpu_model);
- cpu_model = g_strdup(p);
- }
-
- typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
- oc = object_class_by_name(typename);
- g_free(typename);
- g_free(cpu_model);
-
- return oc;
-}
-
-static void ppc_cpu_parse_featurestr(const char *type, char *features,
- Error **errp)
-{
- Object *machine = qdev_get_machine();
- const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type));
-
- if (!features) {
- return;
- }
-
- if (object_property_find(machine, "max-cpu-compat", NULL)) {
- int i;
- char **inpieces;
- char *s = features;
- Error *local_err = NULL;
- char *compat_str = NULL;
-
- /*
- * Backwards compatibility hack:
- *
- * CPUs had a "compat=" property which didn't make sense for
- * anything except pseries. It was replaced by "max-cpu-compat"
- * machine option. This supports old command lines like
- * -cpu POWER8,compat=power7
- * By stripping the compat option and applying it to the machine
- * before passing it on to the cpu level parser.
- */
- inpieces = g_strsplit(features, ",", 0);
- *s = '\0';
- for (i = 0; inpieces[i]; i++) {
- if (g_str_has_prefix(inpieces[i], "compat=")) {
- warn_report_once("CPU 'compat' property is deprecated; "
- "use max-cpu-compat machine property instead");
- compat_str = inpieces[i];
- continue;
- }
- if ((i != 0) && (s != features)) {
- s = g_stpcpy(s, ",");
- }
- s = g_stpcpy(s, inpieces[i]);
- }
-
- if (compat_str) {
- char *v = compat_str + strlen("compat=");
- object_property_set_str(machine, "max-cpu-compat", v, &local_err);
- }
- g_strfreev(inpieces);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
- }
-
- /* do property processing with generic handler */
- pcc->parent_parse_features(type, features, errp);
-}
-
-PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
-{
- ObjectClass *oc = OBJECT_CLASS(pcc);
-
- while (oc && !object_class_is_abstract(oc)) {
- oc = object_class_get_parent(oc);
- }
- assert(oc);
-
- return POWERPC_CPU_CLASS(oc);
-}
-
-/* Sort by PVR, ordering special case "host" last. */
-static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
-{
- ObjectClass *oc_a = (ObjectClass *)a;
- ObjectClass *oc_b = (ObjectClass *)b;
- PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
- PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
- const char *name_a = object_class_get_name(oc_a);
- const char *name_b = object_class_get_name(oc_b);
-
- if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
- return 1;
- } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
- return -1;
- } else {
- /* Avoid an integer overflow during subtraction */
- if (pcc_a->pvr < pcc_b->pvr) {
- return -1;
- } else if (pcc_a->pvr > pcc_b->pvr) {
- return 1;
- } else {
- return 0;
- }
- }
-}
-
-static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
-{
- ObjectClass *oc = data;
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
- const char *typename = object_class_get_name(oc);
- char *name;
- int i;
-
- if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
- return;
- }
-
- name = g_strndup(typename,
- strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
- qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
- for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
- ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
-
- if (alias_oc != oc) {
- continue;
- }
- /*
- * If running with KVM, we might update the family alias later, so
- * avoid printing the wrong alias here and use "preferred" instead
- */
- if (strcmp(alias->alias, family->desc) == 0) {
- qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
- alias->alias, family->desc);
- } else {
- qemu_printf("PowerPC %-16s (alias for %s)\n",
- alias->alias, name);
- }
- }
- g_free(name);
-}
-
-void ppc_cpu_list(void)
-{
- GSList *list;
-
- list = object_class_get_list(TYPE_POWERPC_CPU, false);
- list = g_slist_sort(list, ppc_cpu_list_compare);
- g_slist_foreach(list, ppc_cpu_list_entry, NULL);
- g_slist_free(list);
-
-#ifdef CONFIG_KVM
- qemu_printf("\n");
- qemu_printf("PowerPC %-16s\n", "host");
-#endif
-}
-
-static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
-{
- ObjectClass *oc = data;
- CpuDefinitionInfoList **first = user_data;
- const char *typename;
- CpuDefinitionInfoList *entry;
- CpuDefinitionInfo *info;
-
- typename = object_class_get_name(oc);
- info = g_malloc0(sizeof(*info));
- info->name = g_strndup(typename,
- strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
-
- entry = g_malloc0(sizeof(*entry));
- entry->value = info;
- entry->next = *first;
- *first = entry;
-}
-
-CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
-{
- CpuDefinitionInfoList *cpu_list = NULL;
- GSList *list;
- int i;
-
- list = object_class_get_list(TYPE_POWERPC_CPU, false);
- g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
- g_slist_free(list);
-
- for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
- ObjectClass *oc;
- CpuDefinitionInfoList *entry;
- CpuDefinitionInfo *info;
-
- oc = ppc_cpu_class_by_name(alias->model);
- if (oc == NULL) {
- continue;
- }
-
- info = g_malloc0(sizeof(*info));
- info->name = g_strdup(alias->alias);
- info->q_typename = g_strdup(object_class_get_name(oc));
-
- entry = g_malloc0(sizeof(*entry));
- entry->value = info;
- entry->next = cpu_list;
- cpu_list = entry;
- }
-
- return cpu_list;
-}
-
-static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- cpu->env.nip = value;
-}
-
-static bool ppc_cpu_has_work(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
-}
-
-static void ppc_cpu_reset(DeviceState *dev)
-{
- CPUState *s = CPU(dev);
- PowerPCCPU *cpu = POWERPC_CPU(s);
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- CPUPPCState *env = &cpu->env;
- target_ulong msr;
- int i;
-
- pcc->parent_reset(dev);
-
- msr = (target_ulong)0;
- msr |= (target_ulong)MSR_HVB;
- msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
- msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
- msr |= (target_ulong)1 << MSR_EP;
-#if defined(DO_SINGLE_STEP) && 0
- /* Single step trace mode */
- msr |= (target_ulong)1 << MSR_SE;
- msr |= (target_ulong)1 << MSR_BE;
-#endif
-#if defined(CONFIG_USER_ONLY)
- msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
- msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
- msr |= (target_ulong)1 << MSR_FE1;
- msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
- msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
- msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
- msr |= (target_ulong)1 << MSR_PR;
-#if defined(TARGET_PPC64)
- msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
-#endif
-#if !defined(TARGET_WORDS_BIGENDIAN)
- msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
- if (!((env->msr_mask >> MSR_LE) & 1)) {
- fprintf(stderr, "Selected CPU does not support little-endian.\n");
- exit(1);
- }
-#endif
-#endif
-
-#if defined(TARGET_PPC64)
- if (env->mmu_model & POWERPC_MMU_64) {
- msr |= (1ULL << MSR_SF);
- }
-#endif
-
- hreg_store_msr(env, msr, 1);
-
-#if !defined(CONFIG_USER_ONLY)
- env->nip = env->hreset_vector | env->excp_prefix;
- if (env->mmu_model != POWERPC_MMU_REAL) {
- ppc_tlb_invalidate_all(env);
- }
-#endif
-
- hreg_compute_hflags(env);
- env->reserve_addr = (target_ulong)-1ULL;
- /* Be sure no exception or interrupt is pending */
- env->pending_interrupts = 0;
- s->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- ppc_irq_reset(cpu);
-
- /* tininess for underflow is detected before rounding */
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->fp_status);
-
- for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
- ppc_spr_t *spr = &env->spr_cb[i];
-
- if (!spr->name) {
- continue;
- }
- env->spr[i] = spr->default_value;
- }
-}
-
-#ifndef CONFIG_USER_ONLY
-static bool ppc_cpu_is_big_endian(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- cpu_synchronize_state(cs);
-
- return !msr_le;
-}
-
-static void ppc_cpu_exec_enter(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- if (cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->cpu_exec_enter(cpu->vhyp, cpu);
- }
-}
-
-static void ppc_cpu_exec_exit(CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- if (cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->cpu_exec_exit(cpu->vhyp, cpu);
- }
-}
-#endif
-
-static void ppc_cpu_instance_init(Object *obj)
-{
- PowerPCCPU *cpu = POWERPC_CPU(obj);
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- CPUPPCState *env = &cpu->env;
-
- cpu_set_cpustate_pointers(cpu);
- cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
-
- env->msr_mask = pcc->msr_mask;
- env->mmu_model = pcc->mmu_model;
- env->excp_model = pcc->excp_model;
- env->bus_model = pcc->bus_model;
- env->insns_flags = pcc->insns_flags;
- env->insns_flags2 = pcc->insns_flags2;
- env->flags = pcc->flags;
- env->bfd_mach = pcc->bfd_mach;
- env->check_pow = pcc->check_pow;
-
- /*
- * Mark HV mode as supported if the CPU has an MSR_HV bit in the
- * msr_mask. The mask can later be cleared by PAPR mode but the hv
- * mode support will remain, thus enforcing that we cannot use
- * priv. instructions in guest in PAPR mode. For 970 we currently
- * simply don't set HV in msr_mask thus simulating an "Apple mode"
- * 970. If we ever want to support 970 HV mode, we'll have to add
- * a processor attribute of some sort.
- */
-#if !defined(CONFIG_USER_ONLY)
- env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
-#endif
-
- ppc_hash64_init(cpu);
-}
-
-static void ppc_cpu_instance_finalize(Object *obj)
-{
- PowerPCCPU *cpu = POWERPC_CPU(obj);
-
- ppc_hash64_finalize(cpu);
-}
-
-static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
-{
- return pcc->pvr == pvr;
-}
-
-static gchar *ppc_gdb_arch_name(CPUState *cs)
-{
-#if defined(TARGET_PPC64)
- return g_strdup("powerpc:common64");
-#else
- return g_strdup("powerpc:common");
-#endif
-}
-
-static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
- if ((env->hflags >> MSR_LE) & 1) {
- info->endian = BFD_ENDIAN_LITTLE;
- }
- info->mach = env->bfd_mach;
- if (!env->bfd_mach) {
-#ifdef TARGET_PPC64
- info->mach = bfd_mach_ppc64;
-#else
- info->mach = bfd_mach_ppc;
-#endif
- }
- info->disassembler_options = (char *)"any";
- info->print_insn = print_insn_ppc;
-
- info->cap_arch = CS_ARCH_PPC;
-#ifdef TARGET_PPC64
- info->cap_mode = CS_MODE_64;
-#endif
-}
-
-static Property ppc_cpu_properties[] = {
- DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
- DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
- false),
- DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
- false),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ppc_cpu_class_init(ObjectClass *oc, void *data)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- device_class_set_parent_realize(dc, ppc_cpu_realize,
- &pcc->parent_realize);
- device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
- &pcc->parent_unrealize);
- pcc->pvr_match = ppc_pvr_match_default;
- pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
- device_class_set_props(dc, ppc_cpu_properties);
-
- device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
-
- cc->class_by_name = ppc_cpu_class_by_name;
- pcc->parent_parse_features = cc->parse_features;
- cc->parse_features = ppc_cpu_parse_featurestr;
- cc->has_work = ppc_cpu_has_work;
- cc->do_interrupt = ppc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
- cc->dump_state = ppc_cpu_dump_state;
- cc->dump_statistics = ppc_cpu_dump_statistics;
- cc->set_pc = ppc_cpu_set_pc;
- cc->gdb_read_register = ppc_cpu_gdb_read_register;
- cc->gdb_write_register = ppc_cpu_gdb_write_register;
- cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
-#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
-#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
-
- cc->gdb_num_core_regs = 71;
-#ifndef CONFIG_USER_ONLY
- cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
-#endif
-#ifdef USE_APPLE_GDB
- cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
- cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
- cc->gdb_num_core_regs = 71 + 32;
-#endif
-
- cc->gdb_arch_name = ppc_gdb_arch_name;
-#if defined(TARGET_PPC64)
- cc->gdb_core_xml_file = "power64-core.xml";
-#else
- cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
-#endif
-#ifdef CONFIG_TCG
- cc->tcg_initialize = ppc_translate_init;
- cc->tlb_fill = ppc_cpu_tlb_fill;
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->cpu_exec_enter = ppc_cpu_exec_enter;
- cc->cpu_exec_exit = ppc_cpu_exec_exit;
-#endif
-
- cc->disas_set_info = ppc_disas_set_info;
-
- dc->fw_name = "PowerPC,UNKNOWN";
-}
-
-static const TypeInfo ppc_cpu_type_info = {
- .name = TYPE_POWERPC_CPU,
- .parent = TYPE_CPU,
- .instance_size = sizeof(PowerPCCPU),
- .instance_init = ppc_cpu_instance_init,
- .instance_finalize = ppc_cpu_instance_finalize,
- .abstract = true,
- .class_size = sizeof(PowerPCCPUClass),
- .class_init = ppc_cpu_class_init,
-};
-
-#ifndef CONFIG_USER_ONLY
-static const TypeInfo ppc_vhyp_type_info = {
- .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
- .parent = TYPE_INTERFACE,
- .class_size = sizeof(PPCVirtualHypervisorClass),
-};
-#endif
-
-static void ppc_cpu_register_types(void)
-{
- type_register_static(&ppc_cpu_type_info);
-#ifndef CONFIG_USER_ONLY
- type_register_static(&ppc_vhyp_type_info);
-#endif
-}
-
-type_init(ppc_cpu_register_types)
decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
-target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
+target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
$(decode32-y), "GEN", $(TARGET_DIR)$@)
-target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
+target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
--insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
- target/riscv/decode_insn16.inc.c
+target/riscv/translate.o: target/riscv/decode_insn32.c.inc \
+ target/riscv/decode_insn16.c.inc
--- /dev/null
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
+{
+ /* always generates U-level ECALL, fixed in do_interrupt handler */
+ generate_exception(ctx, RISCV_EXCP_U_ECALL);
+ exit_tb(ctx); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+{
+ generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+ exit_tb(ctx); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a)
+{
+ return false;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+ if (has_ext(ctx, RVS)) {
+ gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+ exit_tb(ctx); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ } else {
+ return false;
+ }
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+ exit_tb(ctx); /* no chaining */
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ gen_helper_wfi(cpu_env);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
+{
+ return false;
+}
+++ /dev/null
-/*
- * RISC-V translation routines for the RISC-V privileged instructions.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
-{
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- exit_tb(ctx); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
-}
-
-static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
-{
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- exit_tb(ctx); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
-}
-
-static bool trans_uret(DisasContext *ctx, arg_uret *a)
-{
- return false;
-}
-
-static bool trans_sret(DisasContext *ctx, arg_sret *a)
-{
-#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- if (has_ext(ctx, RVS)) {
- gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- exit_tb(ctx); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- return false;
- }
- return true;
-#else
- return false;
-#endif
-}
-
-static bool trans_mret(DisasContext *ctx, arg_mret *a)
-{
-#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- exit_tb(ctx); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
-#else
- return false;
-#endif
-}
-
-static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
-{
-#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- gen_helper_wfi(cpu_env);
- return true;
-#else
- return false;
-#endif
-}
-
-static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
- gen_helper_tlb_flush(cpu_env);
- return true;
-#endif
- return false;
-}
-
-static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
-{
- return false;
-}
--- /dev/null
+/*
+ * RISC-V translation routines for the RV64A Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ /* Put addr in load_res, data in load_val. */
+ gen_get_gpr(src1, a->rs1);
+ if (a->rl) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
+ tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
+ if (a->aq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+ tcg_gen_mov_tl(load_res, src1);
+ gen_set_gpr(a->rd, load_val);
+
+ tcg_temp_free(src1);
+ return true;
+}
+
+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+
+ gen_get_gpr(src1, a->rs1);
+ tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
+
+ gen_get_gpr(src2, a->rs2);
+ /*
+ * Note that the TCG atomic primitives are SC,
+ * so we can ignore AQ/RL along this path.
+ */
+ tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+ ctx->mem_idx, mop);
+ tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
+ gen_set_gpr(a->rd, dat);
+ tcg_gen_br(l2);
+
+ gen_set_label(l1);
+ /*
+ * Address comparison failure. However, we still need to
+ * provide the memory barrier implied by AQ/RL.
+ */
+ tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
+ tcg_gen_movi_tl(dat, 1);
+ gen_set_gpr(a->rd, dat);
+
+ gen_set_label(l2);
+ /*
+ * Clear the load reservation, since an SC must fail if there is
+ * an SC to any address, in between an LR and SC pair.
+ */
+ tcg_gen_movi_tl(load_res, -1);
+
+ tcg_temp_free(dat);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool gen_amo(DisasContext *ctx, arg_atomic *a,
+ void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
+ MemOp mop)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ gen_get_gpr(src2, a->rs2);
+
+ (*func)(src2, src1, src2, ctx->mem_idx, mop);
+
+ gen_set_gpr(a->rd, src2);
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ return true;
+}
+
+static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
+}
+
+static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
+{
+ REQUIRE_EXT(ctx, RVA);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+{
+ return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+}
+#endif
+++ /dev/null
-/*
- * RISC-V translation routines for the RV64A Standard Extension.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
-{
- TCGv src1 = tcg_temp_new();
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(src1, a->rs1);
- if (a->rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (a->aq) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- tcg_gen_mov_tl(load_res, src1);
- gen_set_gpr(a->rd, load_val);
-
- tcg_temp_free(src1);
- return true;
-}
-
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-{
- TCGv src1 = tcg_temp_new();
- TCGv src2 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
-
- gen_get_gpr(src1, a->rs1);
- tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-
- gen_get_gpr(src2, a->rs2);
- /*
- * Note that the TCG atomic primitives are SC,
- * so we can ignore AQ/RL along this path.
- */
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
- ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(a->rd, dat);
- tcg_gen_br(l2);
-
- gen_set_label(l1);
- /*
- * Address comparison failure. However, we still need to
- * provide the memory barrier implied by AQ/RL.
- */
- tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(a->rd, dat);
-
- gen_set_label(l2);
- /*
- * Clear the load reservation, since an SC must fail if there is
- * an SC to any address, in between an LR and SC pair.
- */
- tcg_gen_movi_tl(load_res, -1);
-
- tcg_temp_free(dat);
- tcg_temp_free(src1);
- tcg_temp_free(src2);
- return true;
-}
-
-static bool gen_amo(DisasContext *ctx, arg_atomic *a,
- void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
- MemOp mop)
-{
- TCGv src1 = tcg_temp_new();
- TCGv src2 = tcg_temp_new();
-
- gen_get_gpr(src1, a->rs1);
- gen_get_gpr(src2, a->rs2);
-
- (*func)(src2, src1, src2, ctx->mem_idx, mop);
-
- gen_set_gpr(a->rd, src2);
- tcg_temp_free(src1);
- tcg_temp_free(src2);
- return true;
-}
-
-static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
-}
-
-static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
-{
- REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
-}
-
-#ifdef TARGET_RISCV64
-
-static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
-{
- return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
-}
-
-static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
-{
- return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
-}
-
-static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
-{
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
-}
-#endif
--- /dev/null
+/*
+ * RISC-V translation routines for the RV64D Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_fld(DisasContext *ctx, arg_fld *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
+{
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else {
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
+ cpu_fpr[a->rs1], 0, 63);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+#endif
+++ /dev/null
-/*
- * RISC-V translation routines for the RV64D Standard Extension.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_fld(DisasContext *ctx, arg_fld *a)
-{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- tcg_gen_addi_tl(t0, t0, a->imm);
-
- tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
-
- mark_fs_dirty(ctx);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
-{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- tcg_gen_addi_tl(t0, t0, a->imm);
-
- tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
-
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- gen_set_rm(ctx, a->rm);
- gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- gen_set_rm(ctx, a->rm);
- gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- gen_set_rm(ctx, a->rm);
- gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- gen_set_rm(ctx, a->rm);
- gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
-{
- if (a->rs1 == a->rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
- } else {
- tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
- cpu_fpr[a->rs1], 0, 63);
- }
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- if (a->rs1 == a->rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
- tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
- tcg_temp_free_i64(t0);
- }
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
- if (a->rs1 == a->rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
- tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
- tcg_temp_free_i64(t0);
- }
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
- tcg_temp_free(t0);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
- tcg_temp_free(t0);
-
- mark_fs_dirty(ctx);
- return true;
-}
-
-#ifdef TARGET_RISCV64
-
-static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
- return true;
-}
-
-static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
- tcg_temp_free(t0);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
- tcg_temp_free(t0);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
- tcg_temp_free(t0);
- mark_fs_dirty(ctx);
- return true;
-}
-#endif
--- /dev/null
+/*
+ * RISC-V translation routines for the RV64F Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_FPU do {\
+ if (ctx->mstatus_fs == 0) \
+ return false; \
+} while (0)
+
+/*
+ * RISC-V requires NaN-boxing of narrower width floating
+ * point values. This applies when a 32-bit value is
+ * assigned to a 64-bit FP register. Thus this does not
+ * apply when the RVD extension is not present.
+ */
+static void gen_nanbox_fpr(DisasContext *ctx, int regno)
+{
+ if (has_ext(ctx, RVD)) {
+ tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
+ MAKE_64BIT_MASK(32, 32));
+ }
+}
+
+static bool trans_flw(DisasContext *ctx, arg_flw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
+ gen_nanbox_fpr(ctx, a->rd);
+
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
+{
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ if (a->rs1 == a->rs2) { /* FMOV */
+ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else { /* FSGNJ */
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
+ 0, 31);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
+ tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_temp_free_i64(t0);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
+{
+ /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+#endif
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+
+ gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
+
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
+{
+ /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+#if defined(TARGET_RISCV64)
+ tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
+#else
+ tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
+#endif
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
+++ /dev/null
-/*
- * RISC-V translation routines for the RV64F Standard Extension.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#define REQUIRE_FPU do {\
- if (ctx->mstatus_fs == 0) \
- return false; \
-} while (0)
-
-/*
- * RISC-V requires NaN-boxing of narrower width floating
- * point values. This applies when a 32-bit value is
- * assigned to a 64-bit FP register. Thus this does not
- * apply when the RVD extension is not present.
- */
-static void gen_nanbox_fpr(DisasContext *ctx, int regno)
-{
- if (has_ext(ctx, RVD)) {
- tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
- MAKE_64BIT_MASK(32, 32));
- }
-}
-
-static bool trans_flw(DisasContext *ctx, arg_flw *a)
-{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- tcg_gen_addi_tl(t0, t0, a->imm);
-
- tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
- gen_nanbox_fpr(ctx, a->rd);
-
- tcg_temp_free(t0);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
-{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- tcg_gen_addi_tl(t0, t0, a->imm);
-
- tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
-
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- gen_set_rm(ctx, a->rm);
- gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- gen_set_rm(ctx, a->rm);
- gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- gen_set_rm(ctx, a->rm);
- gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- gen_set_rm(ctx, a->rm);
- gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- if (a->rs1 == a->rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
- } else { /* FSGNJ */
- tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
- 0, 31);
- }
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- if (a->rs1 == a->rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
- tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
- tcg_temp_free_i64(t0);
- }
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- if (a->rs1 == a->rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
- tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
- tcg_temp_free_i64(t0);
- }
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2]);
- mark_fs_dirty(ctx);
- return true;
-}
-
-static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
-{
- /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
-
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
-#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
-#endif
-
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
-
- gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
-
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
-
- mark_fs_dirty(ctx);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
-
- mark_fs_dirty(ctx);
- tcg_temp_free(t0);
-
- return true;
-}
-
-static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
-{
- /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
-#endif
-
- mark_fs_dirty(ctx);
- tcg_temp_free(t0);
-
- return true;
-}
-
-#ifdef TARGET_RISCV64
-static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
-
- mark_fs_dirty(ctx);
- tcg_temp_free(t0);
- return true;
-}
-
-static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
-{
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
-
- mark_fs_dirty(ctx);
- tcg_temp_free(t0);
- return true;
-}
-#endif
--- /dev/null
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+++ /dev/null
-/*
- * RISC-V translation routines for the RVXI Base Integer Instruction Set.
- *
- * Copyright (c) 2020 Western Digital
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
-{
- REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
- gen_helper_hyp_tlb_flush(cpu_env);
- return true;
-#endif
- return false;
-}
-
-static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
-{
- REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
- gen_helper_hyp_tlb_flush(cpu_env);
- return true;
-#endif
- return false;
-}
--- /dev/null
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_illegal(DisasContext *ctx, arg_empty *a)
+{
+ gen_exception_illegal(ctx);
+ return true;
+}
+
+static bool trans_lui(DisasContext *ctx, arg_lui *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ }
+ return true;
+}
+
+static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
+{
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ }
+ return true;
+}
+
+static bool trans_jal(DisasContext *ctx, arg_jal *a)
+{
+ gen_jal(ctx, a->rd, a->imm);
+ return true;
+}
+
+static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+{
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!has_ext(ctx, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ lookup_and_goto_ptr(ctx);
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
+{
+ TCGLabel *l = gen_new_label();
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_brcond_tl(cond, source1, source2, l);
+ gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_set_label(l); /* branch taken */
+
+ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ /* misaligned */
+ gen_exception_inst_addr_mis(ctx);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
+ return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a)
+{
+ return gen_branch(ctx, a, TCG_COND_NE);
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a)
+{
+ return gen_branch(ctx, a, TCG_COND_LT);
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a)
+{
+ return gen_branch(ctx, a, TCG_COND_GE);
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
+{
+ return gen_branch(ctx, a, TCG_COND_LTU);
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+{
+ return gen_branch(ctx, a, TCG_COND_GEU);
+}
+
+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ return true;
+}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a)
+{
+ return gen_load(ctx, a, MO_SB);
+}
+
+static bool trans_lh(DisasContext *ctx, arg_lh *a)
+{
+ return gen_load(ctx, a, MO_TESW);
+}
+
+static bool trans_lw(DisasContext *ctx, arg_lw *a)
+{
+ return gen_load(ctx, a, MO_TESL);
+}
+
+static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
+{
+ return gen_load(ctx, a, MO_UB);
+}
+
+static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
+{
+ return gen_load(ctx, a, MO_TEUW);
+}
+
+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_get_gpr(dat, a->rs2);
+
+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ return true;
+}
+
+
+static bool trans_sb(DisasContext *ctx, arg_sb *a)
+{
+ return gen_store(ctx, a, MO_SB);
+}
+
+static bool trans_sh(DisasContext *ctx, arg_sh *a)
+{
+ return gen_store(ctx, a, MO_TESW);
+}
+
+static bool trans_sw(DisasContext *ctx, arg_sw *a)
+{
+ return gen_store(ctx, a, MO_TESL);
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ return gen_load(ctx, a, MO_TEQ);
+}
+
+static bool trans_sd(DisasContext *ctx, arg_sd *a)
+{
+ return gen_store(ctx, a, MO_TEQ);
+}
+#endif
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a)
+{
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
+}
+
+static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
+}
+
+static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
+}
+
+
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ return gen_arith_imm_tl(ctx, a, &gen_slt);
+}
+
+static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
+{
+ return gen_arith_imm_tl(ctx, a, &gen_sltu);
+}
+
+static bool trans_xori(DisasContext *ctx, arg_xori *a)
+{
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
+}
+static bool trans_ori(DisasContext *ctx, arg_ori *a)
+{
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
+}
+static bool trans_andi(DisasContext *ctx, arg_andi *a)
+{
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
+}
+static bool trans_slli(DisasContext *ctx, arg_slli *a)
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shli_tl(t, t, a->shamt);
+
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
+ return true;
+}
+
+static bool trans_srli(DisasContext *ctx, arg_srli *a)
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shri_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
+ return true;
+}
+
+static bool trans_srai(DisasContext *ctx, arg_srai *a)
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_sari_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
+ return true;
+}
+
+static bool trans_add(DisasContext *ctx, arg_add *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
+}
+
+static bool trans_sub(DisasContext *ctx, arg_sub *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
+}
+
+static bool trans_sll(DisasContext *ctx, arg_sll *a)
+{
+ return gen_shift(ctx, a, &tcg_gen_shl_tl);
+}
+
+static bool trans_slt(DisasContext *ctx, arg_slt *a)
+{
+ return gen_arith(ctx, a, &gen_slt);
+}
+
+static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
+{
+ return gen_arith(ctx, a, &gen_sltu);
+}
+
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
+}
+
+static bool trans_srl(DisasContext *ctx, arg_srl *a)
+{
+ return gen_shift(ctx, a, &tcg_gen_shr_tl);
+}
+
+static bool trans_sra(DisasContext *ctx, arg_sra *a)
+{
+ return gen_shift(ctx, a, &tcg_gen_sar_tl);
+}
+
+static bool trans_or(DisasContext *ctx, arg_or *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
+}
+
+static bool trans_and(DisasContext *ctx, arg_and *a)
+{
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
+{
+ return gen_arith_imm_tl(ctx, a, &gen_addw);
+}
+
+static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+{
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
+ return true;
+}
+
+static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+{
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+}
+
+static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+{
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+}
+
+static bool trans_addw(DisasContext *ctx, arg_addw *a)
+{
+ return gen_arith(ctx, a, &gen_addw);
+}
+
+static bool trans_subw(DisasContext *ctx, arg_subw *a)
+{
+ return gen_arith(ctx, a, &gen_subw);
+}
+
+static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shl_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* clear upper 32 */
+ tcg_gen_ext32u_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shr_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /*
+ * first, trick to get it to act like working on 32 bits (get rid of
+ * upper 32, sign extend to fill space)
+ */
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_sar_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
+ return true;
+}
+#endif
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a)
+{
+ /* FENCE is a full memory barrier. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+{
+ if (!ctx->ext_ifencei) {
+ return false;
+ }
+
+ /*
+ * FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block
+ */
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ exit_tb(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+#define RISCV_OP_CSR_PRE do {\
+ source1 = tcg_temp_new(); \
+ csr_store = tcg_temp_new(); \
+ dest = tcg_temp_new(); \
+ rs1_pass = tcg_temp_new(); \
+ gen_get_gpr(source1, a->rs1); \
+ tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
+ tcg_gen_movi_tl(rs1_pass, a->rs1); \
+ tcg_gen_movi_tl(csr_store, a->csr); \
+ gen_io_start();\
+} while (0)
+
+#define RISCV_OP_CSR_POST do {\
+ gen_set_gpr(a->rd, dest); \
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
+ exit_tb(ctx); \
+ ctx->base.is_jmp = DISAS_NORETURN; \
+ tcg_temp_free(source1); \
+ tcg_temp_free(csr_store); \
+ tcg_temp_free(dest); \
+ tcg_temp_free(rs1_pass); \
+} while (0)
+
+
+static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, source1, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+{
+ TCGv source1, csr_store, dest, rs1_pass;
+ RISCV_OP_CSR_PRE;
+ gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
+ RISCV_OP_CSR_POST;
+ return true;
+}
+++ /dev/null
-/*
- * RISC-V translation routines for the RVXI Base Integer Instruction Set.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_illegal(DisasContext *ctx, arg_empty *a)
-{
- gen_exception_illegal(ctx);
- return true;
-}
-
-static bool trans_lui(DisasContext *ctx, arg_lui *a)
-{
- if (a->rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
- }
- return true;
-}
-
-static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
-{
- if (a->rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
- }
- return true;
-}
-
-static bool trans_jal(DisasContext *ctx, arg_jal *a)
-{
- gen_jal(ctx, a->rd, a->imm);
- return true;
-}
-
-static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
-
- gen_get_gpr(cpu_pc, a->rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!has_ext(ctx, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (a->rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
- }
- lookup_and_goto_ptr(ctx);
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-
- tcg_temp_free(t0);
- return true;
-}
-
-static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
- gen_get_gpr(source2, a->rs2);
-
- tcg_gen_brcond_tl(cond, source1, source2, l);
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
-
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- return true;
-}
-
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
-{
- return gen_branch(ctx, a, TCG_COND_EQ);
-}
-
-static bool trans_bne(DisasContext *ctx, arg_bne *a)
-{
- return gen_branch(ctx, a, TCG_COND_NE);
-}
-
-static bool trans_blt(DisasContext *ctx, arg_blt *a)
-{
- return gen_branch(ctx, a, TCG_COND_LT);
-}
-
-static bool trans_bge(DisasContext *ctx, arg_bge *a)
-{
- return gen_branch(ctx, a, TCG_COND_GE);
-}
-
-static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
-{
- return gen_branch(ctx, a, TCG_COND_LTU);
-}
-
-static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
-{
- return gen_branch(ctx, a, TCG_COND_GEU);
-}
-
-static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(a->rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- return true;
-}
-
-static bool trans_lb(DisasContext *ctx, arg_lb *a)
-{
- return gen_load(ctx, a, MO_SB);
-}
-
-static bool trans_lh(DisasContext *ctx, arg_lh *a)
-{
- return gen_load(ctx, a, MO_TESW);
-}
-
-static bool trans_lw(DisasContext *ctx, arg_lw *a)
-{
- return gen_load(ctx, a, MO_TESL);
-}
-
-static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
-{
- return gen_load(ctx, a, MO_UB);
-}
-
-static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
-{
- return gen_load(ctx, a, MO_TEUW);
-}
-
-static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
-{
- TCGv t0 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
- gen_get_gpr(dat, a->rs2);
-
- tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
- tcg_temp_free(t0);
- tcg_temp_free(dat);
- return true;
-}
-
-
-static bool trans_sb(DisasContext *ctx, arg_sb *a)
-{
- return gen_store(ctx, a, MO_SB);
-}
-
-static bool trans_sh(DisasContext *ctx, arg_sh *a)
-{
- return gen_store(ctx, a, MO_TESW);
-}
-
-static bool trans_sw(DisasContext *ctx, arg_sw *a)
-{
- return gen_store(ctx, a, MO_TESL);
-}
-
-#ifdef TARGET_RISCV64
-static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
-{
- return gen_load(ctx, a, MO_TEUL);
-}
-
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
-{
- return gen_load(ctx, a, MO_TEQ);
-}
-
-static bool trans_sd(DisasContext *ctx, arg_sd *a)
-{
- return gen_store(ctx, a, MO_TEQ);
-}
-#endif
-
-static bool trans_addi(DisasContext *ctx, arg_addi *a)
-{
- return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
-}
-
-static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
-{
- tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
-}
-
-static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
-{
- tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
-}
-
-
-static bool trans_slti(DisasContext *ctx, arg_slti *a)
-{
- return gen_arith_imm_tl(ctx, a, &gen_slt);
-}
-
-static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
-{
- return gen_arith_imm_tl(ctx, a, &gen_sltu);
-}
-
-static bool trans_xori(DisasContext *ctx, arg_xori *a)
-{
- return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
-}
-static bool trans_ori(DisasContext *ctx, arg_ori *a)
-{
- return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
-}
-static bool trans_andi(DisasContext *ctx, arg_andi *a)
-{
- return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
-}
-static bool trans_slli(DisasContext *ctx, arg_slli *a)
-{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_shli_tl(t, t, a->shamt);
-
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
-}
-
-static bool trans_srli(DisasContext *ctx, arg_srli *a)
-{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_shri_tl(t, t, a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
-}
-
-static bool trans_srai(DisasContext *ctx, arg_srai *a)
-{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_sari_tl(t, t, a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
-}
-
-static bool trans_add(DisasContext *ctx, arg_add *a)
-{
- return gen_arith(ctx, a, &tcg_gen_add_tl);
-}
-
-static bool trans_sub(DisasContext *ctx, arg_sub *a)
-{
- return gen_arith(ctx, a, &tcg_gen_sub_tl);
-}
-
-static bool trans_sll(DisasContext *ctx, arg_sll *a)
-{
- return gen_shift(ctx, a, &tcg_gen_shl_tl);
-}
-
-static bool trans_slt(DisasContext *ctx, arg_slt *a)
-{
- return gen_arith(ctx, a, &gen_slt);
-}
-
-static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
-{
- return gen_arith(ctx, a, &gen_sltu);
-}
-
-static bool trans_xor(DisasContext *ctx, arg_xor *a)
-{
- return gen_arith(ctx, a, &tcg_gen_xor_tl);
-}
-
-static bool trans_srl(DisasContext *ctx, arg_srl *a)
-{
- return gen_shift(ctx, a, &tcg_gen_shr_tl);
-}
-
-static bool trans_sra(DisasContext *ctx, arg_sra *a)
-{
- return gen_shift(ctx, a, &tcg_gen_sar_tl);
-}
-
-static bool trans_or(DisasContext *ctx, arg_or *a)
-{
- return gen_arith(ctx, a, &tcg_gen_or_tl);
-}
-
-static bool trans_and(DisasContext *ctx, arg_and *a)
-{
- return gen_arith(ctx, a, &tcg_gen_and_tl);
-}
-
-#ifdef TARGET_RISCV64
-static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
-{
- return gen_arith_imm_tl(ctx, a, &gen_addw);
-}
-
-static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
-{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
- tcg_gen_shli_tl(source1, source1, a->shamt);
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(a->rd, source1);
-
- tcg_temp_free(source1);
- return true;
-}
-
-static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
-{
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
- tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
- /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(t, t);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- return true;
-}
-
-static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
-{
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
- tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- return true;
-}
-
-static bool trans_addw(DisasContext *ctx, arg_addw *a)
-{
- return gen_arith(ctx, a, &gen_addw);
-}
-
-static bool trans_subw(DisasContext *ctx, arg_subw *a)
-{
- return gen_arith(ctx, a, &gen_subw);
-}
-
-static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
-{
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
-
- gen_get_gpr(source1, a->rs1);
- gen_get_gpr(source2, a->rs2);
-
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shl_tl(source1, source1, source2);
-
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
-}
-
-static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
-{
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
-
- gen_get_gpr(source1, a->rs1);
- gen_get_gpr(source2, a->rs2);
-
- /* clear upper 32 */
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shr_tl(source1, source1, source2);
-
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
-}
-
-static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
-{
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
-
- gen_get_gpr(source1, a->rs1);
- gen_get_gpr(source2, a->rs2);
-
- /*
- * first, trick to get it to act like working on 32 bits (get rid of
- * upper 32, sign extend to fill space)
- */
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_sar_tl(source1, source1, source2);
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- return true;
-}
-#endif
-
-static bool trans_fence(DisasContext *ctx, arg_fence *a)
-{
- /* FENCE is a full memory barrier. */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- return true;
-}
-
-static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
-{
- if (!ctx->ext_ifencei) {
- return false;
- }
-
- /*
- * FENCE_I is a no-op in QEMU,
- * however we need to end the translation block
- */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- exit_tb(ctx);
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
-}
-
-#define RISCV_OP_CSR_PRE do {\
- source1 = tcg_temp_new(); \
- csr_store = tcg_temp_new(); \
- dest = tcg_temp_new(); \
- rs1_pass = tcg_temp_new(); \
- gen_get_gpr(source1, a->rs1); \
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
- tcg_gen_movi_tl(rs1_pass, a->rs1); \
- tcg_gen_movi_tl(csr_store, a->csr); \
- gen_io_start();\
-} while (0)
-
-#define RISCV_OP_CSR_POST do {\
- gen_set_gpr(a->rd, dest); \
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
- exit_tb(ctx); \
- ctx->base.is_jmp = DISAS_NORETURN; \
- tcg_temp_free(source1); \
- tcg_temp_free(csr_store); \
- tcg_temp_free(dest); \
- tcg_temp_free(rs1_pass); \
-} while (0)
-
-
-static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
-{
- TCGv source1, csr_store, dest, rs1_pass;
- RISCV_OP_CSR_PRE;
- gen_helper_csrrw(dest, cpu_env, source1, csr_store);
- RISCV_OP_CSR_POST;
- return true;
-}
-
-static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
-{
- TCGv source1, csr_store, dest, rs1_pass;
- RISCV_OP_CSR_PRE;
- gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
- RISCV_OP_CSR_POST;
- return true;
-}
-
-static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
-{
- TCGv source1, csr_store, dest, rs1_pass;
- RISCV_OP_CSR_PRE;
- gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
- RISCV_OP_CSR_POST;
- return true;
-}
-
-static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
-{
- TCGv source1, csr_store, dest, rs1_pass;
- RISCV_OP_CSR_PRE;
- gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
- RISCV_OP_CSR_POST;
- return true;
-}
-
-static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
-{
- TCGv source1, csr_store, dest, rs1_pass;
- RISCV_OP_CSR_PRE;
- gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
- RISCV_OP_CSR_POST;
- return true;
-}
-
-static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
-{
- TCGv source1, csr_store, dest, rs1_pass;
- RISCV_OP_CSR_PRE;
- gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
- RISCV_OP_CSR_POST;
- return true;
-}
--- /dev/null
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_muls2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_mulhsu);
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_mulu2_tl(source2, source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_div);
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_divu);
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_rem);
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_remu);
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, &gen_mulw);
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_w(ctx, a, &gen_div);
+}
+
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_uw(ctx, a, &gen_divu);
+}
+
+static bool trans_remw(DisasContext *ctx, arg_remw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_w(ctx, a, &gen_rem);
+}
+
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith_div_uw(ctx, a, &gen_remu);
+}
+#endif
+++ /dev/null
-/*
- * RISC-V translation routines for the RV64M Standard Extension.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-static bool trans_mul(DisasContext *ctx, arg_mul *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &tcg_gen_mul_tl);
-}
-
-static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
-{
- REQUIRE_EXT(ctx, RVM);
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
- gen_get_gpr(source2, a->rs2);
-
- tcg_gen_muls2_tl(source2, source1, source1, source2);
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
-}
-
-static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &gen_mulhsu);
-}
-
-static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
-{
- REQUIRE_EXT(ctx, RVM);
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
- gen_get_gpr(source2, a->rs2);
-
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
-}
-
-static bool trans_div(DisasContext *ctx, arg_div *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &gen_div);
-}
-
-static bool trans_divu(DisasContext *ctx, arg_divu *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &gen_divu);
-}
-
-static bool trans_rem(DisasContext *ctx, arg_rem *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &gen_rem);
-}
-
-static bool trans_remu(DisasContext *ctx, arg_remu *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &gen_remu);
-}
-
-#ifdef TARGET_RISCV64
-static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, &gen_mulw);
-}
-
-static bool trans_divw(DisasContext *ctx, arg_divw *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith_div_w(ctx, a, &gen_div);
-}
-
-static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith_div_uw(ctx, a, &gen_divu);
-}
-
-static bool trans_remw(DisasContext *ctx, arg_remw *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith_div_w(ctx, a, &gen_rem);
-}
-
-static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
-{
- REQUIRE_EXT(ctx, RVM);
- return gen_arith_div_uw(ctx, a, &gen_remu);
-}
-#endif
--- /dev/null
+/*
+ * RISC-V translation routines for the RVV Standard Extension.
+ *
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "tcg/tcg-op-gvec.h"
+#include "tcg/tcg-gvec-desc.h"
+#include "internals.h"
+
+static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+{
+ TCGv s1, s2, dst;
+
+ if (!has_ext(ctx, RVV)) {
+ return false;
+ }
+
+ s2 = tcg_temp_new();
+ dst = tcg_temp_new();
+
+ /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
+ if (a->rs1 == 0) {
+ /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
+ s1 = tcg_const_tl(RV_VLEN_MAX);
+ } else {
+ s1 = tcg_temp_new();
+ gen_get_gpr(s1, a->rs1);
+ }
+ gen_get_gpr(s2, a->rs2);
+ gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_set_gpr(a->rd, dst);
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ lookup_and_goto_ptr(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(s1);
+ tcg_temp_free(s2);
+ tcg_temp_free(dst);
+ return true;
+}
+
+static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
+{
+ TCGv s1, s2, dst;
+
+ if (!has_ext(ctx, RVV)) {
+ return false;
+ }
+
+ s2 = tcg_const_tl(a->zimm);
+ dst = tcg_temp_new();
+
+ /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
+ if (a->rs1 == 0) {
+ /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
+ s1 = tcg_const_tl(RV_VLEN_MAX);
+ } else {
+ s1 = tcg_temp_new();
+ gen_get_gpr(s1, a->rs1);
+ }
+ gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_set_gpr(a->rd, dst);
+ gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(s1);
+ tcg_temp_free(s2);
+ tcg_temp_free(dst);
+ return true;
+}
+
+/* vector register offset from env */
+static uint32_t vreg_ofs(DisasContext *s, int reg)
+{
+ return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
+}
+
+/* check functions */
+
+/*
+ * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
+ * So RVV is also be checked in this function.
+ */
+static bool vext_check_isa_ill(DisasContext *s)
+{
+ return !s->vill;
+}
+
+/*
+ * There are two rules check here.
+ *
+ * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
+ *
+ * 2. For all widening instructions, the destination LMUL value must also be
+ * a supported LMUL value. (Section 11.2)
+ */
+static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
+{
+ /*
+ * The destination vector register group results are arranged as if both
+ * SEW and LMUL were at twice their current settings. (Section 11.2).
+ */
+ int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+
+ return !((s->lmul == 0x3 && widen) || (reg % legal));
+}
+
+/*
+ * There are two rules check here.
+ *
+ * 1. The destination vector register group for a masked vector instruction can
+ * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
+ *
+ * 2. In widen instructions and some other insturctions, like vslideup.vx,
+ * there is no need to check whether LMUL=1.
+ */
+static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
+ bool force)
+{
+ return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
+}
+
+/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
+static bool vext_check_nf(DisasContext *s, uint32_t nf)
+{
+ return (1 << s->lmul) * nf <= 8;
+}
+
+/*
+ * The destination vector register group cannot overlap a source vector register
+ * group of a different element width. (Section 11.2)
+ */
+static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
+{
+ return ((rd >= rs + slen) || (rs >= rd + dlen));
+}
+/* common translation macro */
+#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
+{ \
+ if (CHECK(s, a)) { \
+ return OP(s, a, SEQ); \
+ } \
+ return false; \
+}
+
+/*
+ *** unit stride load and store
+ */
+typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
+ TCGv_env, TCGv_i32);
+
+static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+ gen_helper_ldst_us *fn, DisasContext *s)
+{
+ TCGv_ptr dest, mask;
+ TCGv base;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+
+ /*
+ * As simd_desc supports at most 256 bytes, and in this implementation,
+ * the max vector group length is 2048 bytes. So split it into two parts.
+ *
+ * The first part is vlen in bytes, encoded in maxsz of simd_desc.
+ * The second part is lmul, encoded in data of simd_desc.
+ */
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, base, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn;
+ static gen_helper_ldst_us * const fns[2][7][4] = {
+ /* masked unit stride load */
+ { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
+ gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
+ { NULL, gen_helper_vlh_v_h_mask,
+ gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
+ { NULL, NULL,
+ gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
+ { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
+ gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
+ { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
+ gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
+ { NULL, gen_helper_vlhu_v_h_mask,
+ gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
+ { NULL, NULL,
+ gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
+ /* unmasked unit stride load */
+ { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
+ gen_helper_vlb_v_w, gen_helper_vlb_v_d },
+ { NULL, gen_helper_vlh_v_h,
+ gen_helper_vlh_v_w, gen_helper_vlh_v_d },
+ { NULL, NULL,
+ gen_helper_vlw_v_w, gen_helper_vlw_v_d },
+ { gen_helper_vle_v_b, gen_helper_vle_v_h,
+ gen_helper_vle_v_w, gen_helper_vle_v_d },
+ { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
+ gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
+ { NULL, gen_helper_vlhu_v_h,
+ gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
+ { NULL, NULL,
+ gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
+ };
+
+ fn = fns[a->vm][seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s);
+}
+
+static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_nf(s, a->nf));
+}
+
+GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
+
+static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn;
+ static gen_helper_ldst_us * const fns[2][4][4] = {
+ /* masked unit stride load and store */
+ { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
+ gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
+ { NULL, gen_helper_vsh_v_h_mask,
+ gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
+ { NULL, NULL,
+ gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
+ { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
+ gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
+ /* unmasked unit stride store */
+ { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
+ gen_helper_vsb_v_w, gen_helper_vsb_v_d },
+ { NULL, gen_helper_vsh_v_h,
+ gen_helper_vsh_v_w, gen_helper_vsh_v_d },
+ { NULL, NULL,
+ gen_helper_vsw_v_w, gen_helper_vsw_v_d },
+ { gen_helper_vse_v_b, gen_helper_vse_v_h,
+ gen_helper_vse_v_w, gen_helper_vse_v_d } }
+ };
+
+ fn = fns[a->vm][seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s);
+}
+
+static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_nf(s, a->nf));
+}
+
+GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
+
+/*
+ *** stride load and store
+ */
+typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
+ TCGv, TCGv_env, TCGv_i32);
+
+static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
+ uint32_t data, gen_helper_ldst_stride *fn,
+ DisasContext *s)
+{
+ TCGv_ptr dest, mask;
+ TCGv base, stride;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ stride = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ gen_get_gpr(stride, rs2);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, base, stride, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free(base);
+ tcg_temp_free(stride);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_stride *fn;
+ static gen_helper_ldst_stride * const fns[7][4] = {
+ { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
+ gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
+ { NULL, gen_helper_vlsh_v_h,
+ gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
+ { NULL, NULL,
+ gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
+ { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
+ gen_helper_vlse_v_w, gen_helper_vlse_v_d },
+ { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
+ gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
+ { NULL, gen_helper_vlshu_v_h,
+ gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
+ { NULL, NULL,
+ gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+}
+
+static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_nf(s, a->nf));
+}
+
+GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
+
+static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_stride *fn;
+ static gen_helper_ldst_stride * const fns[4][4] = {
+ /* masked stride store */
+ { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
+ gen_helper_vssb_v_w, gen_helper_vssb_v_d },
+ { NULL, gen_helper_vssh_v_h,
+ gen_helper_vssh_v_w, gen_helper_vssh_v_d },
+ { NULL, NULL,
+ gen_helper_vssw_v_w, gen_helper_vssw_v_d },
+ { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
+ gen_helper_vsse_v_w, gen_helper_vsse_v_d }
+ };
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+}
+
+static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_nf(s, a->nf));
+}
+
+GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
+
+/*
+ *** index load and store
+ */
+typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
+ TCGv_ptr, TCGv_env, TCGv_i32);
+
+static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
+ uint32_t data, gen_helper_ldst_index *fn,
+ DisasContext *s)
+{
+ TCGv_ptr dest, mask, index;
+ TCGv base;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ index = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, base, index, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(index);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_index *fn;
+ static gen_helper_ldst_index * const fns[7][4] = {
+ { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
+ gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
+ { NULL, gen_helper_vlxh_v_h,
+ gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
+ { NULL, NULL,
+ gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
+ { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
+ gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
+ { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
+ gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
+ { NULL, gen_helper_vlxhu_v_h,
+ gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
+ { NULL, NULL,
+ gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+}
+
+/*
+ * For vector indexed segment loads, the destination vector register
+ * groups cannot overlap the source vector register group (specified by
+ * `vs2`), else an illegal instruction exception is raised.
+ */
+static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_nf(s, a->nf) &&
+ ((a->nf == 1) ||
+ vext_check_overlap_group(a->rd, a->nf << s->lmul,
+ a->rs2, 1 << s->lmul)));
+}
+
+GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
+
+static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_index *fn;
+ static gen_helper_ldst_index * const fns[4][4] = {
+ { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
+ gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
+ { NULL, gen_helper_vsxh_v_h,
+ gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
+ { NULL, NULL,
+ gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
+ { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
+ gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+}
+
+static bool st_index_check(DisasContext *s, arg_rnfvm* a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_nf(s, a->nf));
+}
+
+GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+
+/*
+ *** unit stride fault-only-first load
+ */
+static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+ gen_helper_ldst_us *fn, DisasContext *s)
+{
+ TCGv_ptr dest, mask;
+ TCGv base;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, base, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn;
+ static gen_helper_ldst_us * const fns[7][4] = {
+ { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
+ gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
+ { NULL, gen_helper_vlhff_v_h,
+ gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
+ { NULL, NULL,
+ gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
+ { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
+ gen_helper_vleff_v_w, gen_helper_vleff_v_d },
+ { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
+ gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
+ { NULL, gen_helper_vlhuff_v_h,
+ gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
+ { NULL, NULL,
+ gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, NF, a->nf);
+ return ldff_trans(a->rd, a->rs1, data, fn, s);
+}
+
+GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
+
+/*
+ *** vector atomic operation
+ */
+typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
+ TCGv_env, TCGv_i32);
+
+static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
+ uint32_t data, gen_helper_amo *fn, DisasContext *s)
+{
+ TCGv_ptr dest, mask, index;
+ TCGv base;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ index = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, base, index, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(index);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_amo *fn;
+ static gen_helper_amo *const fnsw[9] = {
+ /* no atomic operation */
+ gen_helper_vamoswapw_v_w,
+ gen_helper_vamoaddw_v_w,
+ gen_helper_vamoxorw_v_w,
+ gen_helper_vamoandw_v_w,
+ gen_helper_vamoorw_v_w,
+ gen_helper_vamominw_v_w,
+ gen_helper_vamomaxw_v_w,
+ gen_helper_vamominuw_v_w,
+ gen_helper_vamomaxuw_v_w
+ };
+#ifdef TARGET_RISCV64
+ static gen_helper_amo *const fnsd[18] = {
+ gen_helper_vamoswapw_v_d,
+ gen_helper_vamoaddw_v_d,
+ gen_helper_vamoxorw_v_d,
+ gen_helper_vamoandw_v_d,
+ gen_helper_vamoorw_v_d,
+ gen_helper_vamominw_v_d,
+ gen_helper_vamomaxw_v_d,
+ gen_helper_vamominuw_v_d,
+ gen_helper_vamomaxuw_v_d,
+ gen_helper_vamoswapd_v_d,
+ gen_helper_vamoaddd_v_d,
+ gen_helper_vamoxord_v_d,
+ gen_helper_vamoandd_v_d,
+ gen_helper_vamoord_v_d,
+ gen_helper_vamomind_v_d,
+ gen_helper_vamomaxd_v_d,
+ gen_helper_vamominud_v_d,
+ gen_helper_vamomaxud_v_d
+ };
+#endif
+
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+ gen_helper_exit_atomic(cpu_env);
+ s->base.is_jmp = DISAS_NORETURN;
+ return true;
+ } else {
+ if (s->sew == 3) {
+#ifdef TARGET_RISCV64
+ fn = fnsd[seq];
+#else
+ /* Check done in amo_check(). */
+ g_assert_not_reached();
+#endif
+ } else {
+ assert(seq < ARRAY_SIZE(fnsw));
+ fn = fnsw[seq];
+ }
+ }
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, WD, a->wd);
+ return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+}
+/*
+ * There are two rules check here.
+ *
+ * 1. SEW must be at least as wide as the AMO memory element size.
+ *
+ * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
+ */
+static bool amo_check(DisasContext *s, arg_rwdvm* a)
+{
+ return (!s->vill && has_ext(s, RVA) &&
+ (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ ((1 << s->sew) <= sizeof(target_ulong)) &&
+ ((1 << s->sew) >= 4));
+}
+
+GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
+#ifdef TARGET_RISCV64
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
+#endif
+
+/*
+ *** Vector Integer Arithmetic Instructions
+ */
+#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false));
+}
+
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+
+static inline bool
+do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
+ gen_helper_gvec_4_ptr *fn)
+{
+ TCGLabel *over = gen_new_label();
+ if (!opivv_check(s, a)) {
+ return false;
+ }
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ if (a->vm && s->vl_eq_vlmax) {
+ gvec_fn(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+ } else {
+ uint32_t data = 0;
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
+ cpu_env, 0, s->vlen / 8, data, fn);
+ }
+ gen_set_label(over);
+ return true;
+}
+
+/* OPIVV with GVEC IR */
+#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_gvec_4_ptr * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
+}
+
+GEN_OPIVV_GVEC_TRANS(vadd_vv, add)
+GEN_OPIVV_GVEC_TRANS(vsub_vv, sub)
+
+typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
+ TCGv_env, TCGv_i32);
+
+static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
+ gen_helper_opivx *fn, DisasContext *s)
+{
+ TCGv_ptr dest, src2, mask;
+ TCGv src1;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ src1 = tcg_temp_new();
+ gen_get_gpr(src1, rs1);
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, src1, src2, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(src1);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool opivx_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false));
+}
+
+typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
+ uint32_t, uint32_t);
+
+static inline bool
+do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
+ gen_helper_opivx *fn)
+{
+ if (!opivx_check(s, a)) {
+ return false;
+ }
+
+ if (a->vm && s->vl_eq_vlmax) {
+ TCGv_i64 src1 = tcg_temp_new_i64();
+ TCGv tmp = tcg_temp_new();
+
+ gen_get_gpr(tmp, a->rs1);
+ tcg_gen_ext_tl_i64(src1, tmp);
+ gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+ src1, MAXSZ(s), MAXSZ(s));
+
+ tcg_temp_free_i64(src1);
+ tcg_temp_free(tmp);
+ return true;
+ }
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+}
+
+/* OPIVX with GVEC IR */
+#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
+}
+
+GEN_OPIVX_GVEC_TRANS(vadd_vx, adds)
+GEN_OPIVX_GVEC_TRANS(vsub_vx, subs)
+
+static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_vec_sub8_i64(d, b, a);
+}
+
+static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_vec_sub16_i64(d, b, a);
+}
+
+static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+{
+ tcg_gen_sub_i32(ret, arg2, arg1);
+}
+
+static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
+{
+ tcg_gen_sub_i64(ret, arg2, arg1);
+}
+
+static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_sub_vec(vece, r, b, a);
+}
+
+static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
+ static const GVecGen2s rsub_op[4] = {
+ { .fni8 = gen_vec_rsub8_i64,
+ .fniv = gen_rsub_vec,
+ .fno = gen_helper_vec_rsubs8,
+ .opt_opc = vecop_list,
+ .vece = MO_8 },
+ { .fni8 = gen_vec_rsub16_i64,
+ .fniv = gen_rsub_vec,
+ .fno = gen_helper_vec_rsubs16,
+ .opt_opc = vecop_list,
+ .vece = MO_16 },
+ { .fni4 = gen_rsub_i32,
+ .fniv = gen_rsub_vec,
+ .fno = gen_helper_vec_rsubs32,
+ .opt_opc = vecop_list,
+ .vece = MO_32 },
+ { .fni8 = gen_rsub_i64,
+ .fniv = gen_rsub_vec,
+ .fno = gen_helper_vec_rsubs64,
+ .opt_opc = vecop_list,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
+}
+
+GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
+
+static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
+ gen_helper_opivx *fn, DisasContext *s, int zx)
+{
+ TCGv_ptr dest, src2, mask;
+ TCGv src1;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ if (zx) {
+ src1 = tcg_const_tl(imm);
+ } else {
+ src1 = tcg_const_tl(sextract64(imm, 0, 5));
+ }
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, src1, src2, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(src1);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
+ uint32_t, uint32_t);
+
+static inline bool
+do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
+ gen_helper_opivx *fn, int zx)
+{
+ if (!opivx_check(s, a)) {
+ return false;
+ }
+
+ if (a->vm && s->vl_eq_vlmax) {
+ if (zx) {
+ gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+ extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
+ } else {
+ gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+ sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
+ }
+ } else {
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
+ }
+ return true;
+}
+
+/* OPIVI with GVEC IR */
+#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
+ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
+ }; \
+ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
+ fns[s->sew], ZX); \
+}
+
+GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
+
+static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ TCGv_i64 tmp = tcg_const_i64(c);
+ tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
+ tcg_temp_free_i64(tmp);
+}
+
+GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
+
+/* Vector Widening Integer Add/Subtract */
+
+/* OPIVV with WIDEN */
+static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
+ gen_helper_gvec_4_ptr *fn,
+ bool (*checkfn)(DisasContext *, arg_rmrr *))
+{
+ if (checkfn(s, a)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs1),
+ vreg_ofs(s, a->rs2),
+ cpu_env, 0, s->vlen / 8,
+ data, fn);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_gvec_4_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w \
+ }; \
+ return do_opivv_widen(s, a, fns[s->sew], CHECK); \
+}
+
+GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
+
+/* OPIVX with WIDEN */
+static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
+ gen_helper_opivx *fn)
+{
+ if (opivx_widen_check(s, a)) {
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ }
+ return false;
+}
+
+#define GEN_OPIVX_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w \
+ }; \
+ return do_opivx_widen(s, a, fns[s->sew]); \
+}
+
+GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
+
+/* WIDEN OPIVV with WIDEN */
+static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
+ gen_helper_gvec_4_ptr *fn)
+{
+ if (opiwv_widen_check(s, a)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs1),
+ vreg_ofs(s, a->rs2),
+ cpu_env, 0, s->vlen / 8, data, fn);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+#define GEN_OPIWV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_gvec_4_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w \
+ }; \
+ return do_opiwv_widen(s, a, fns[s->sew]); \
+}
+
+GEN_OPIWV_WIDEN_TRANS(vwaddu_wv)
+GEN_OPIWV_WIDEN_TRANS(vwadd_wv)
+GEN_OPIWV_WIDEN_TRANS(vwsubu_wv)
+GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
+
+/* WIDEN OPIVX with WIDEN */
+static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, true) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
+ gen_helper_opivx *fn)
+{
+ if (opiwx_widen_check(s, a)) {
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+ }
+ return false;
+}
+
+#define GEN_OPIWX_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w \
+ }; \
+ return do_opiwx_widen(s, a, fns[s->sew]); \
+}
+
+GEN_OPIWX_WIDEN_TRANS(vwaddu_wx)
+GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
+GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
+GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
+
+/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
+/* OPIVV without GVEC IR */
+#define GEN_OPIVV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+/*
+ * For vadc and vsbc, an illegal instruction exception is raised if the
+ * destination vector register is v0 and LMUL > 1. (Section 12.3)
+ */
+static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ ((a->rd != 0) || (s->lmul == 0)));
+}
+
+GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
+GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
+
+/*
+ * For vmadc and vmsbc, an illegal instruction exception is raised if the
+ * destination vector register overlaps a source vector register group.
+ */
+static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
+ vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+}
+
+GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
+GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
+
+static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ ((a->rd != 0) || (s->lmul == 0)));
+}
+
+/* OPIVX without GVEC IR */
+#define GEN_OPIVX_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ \
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ } \
+ return false; \
+}
+
+GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check)
+GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
+
+static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+}
+
+GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
+GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check)
+
+/* OPIVI without GVEC IR */
+#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
+ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
+ }; \
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, ZX); \
+ } \
+ return false; \
+}
+
+GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check)
+GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check)
+
+/* Vector Bitwise Logical Instructions */
+GEN_OPIVV_GVEC_TRANS(vand_vv, and)
+GEN_OPIVV_GVEC_TRANS(vor_vv, or)
+GEN_OPIVV_GVEC_TRANS(vxor_vv, xor)
+GEN_OPIVX_GVEC_TRANS(vand_vx, ands)
+GEN_OPIVX_GVEC_TRANS(vor_vx, ors)
+GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
+GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
+GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
+GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
+
+/* Vector Single-Width Bit Shift Instructions */
+GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
+GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv)
+GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv)
+
+typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
+ uint32_t, uint32_t);
+
+static inline bool
+do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
+ gen_helper_opivx *fn)
+{
+ if (!opivx_check(s, a)) {
+ return false;
+ }
+
+ if (a->vm && s->vl_eq_vlmax) {
+ TCGv_i32 src1 = tcg_temp_new_i32();
+ TCGv tmp = tcg_temp_new();
+
+ gen_get_gpr(tmp, a->rs1);
+ tcg_gen_trunc_tl_i32(src1, tmp);
+ tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
+ gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+ src1, MAXSZ(s), MAXSZ(s));
+
+ tcg_temp_free_i32(src1);
+ tcg_temp_free(tmp);
+ return true;
+ }
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+}
+
+#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ static gen_helper_opivx * const fns[4] = { \
+ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
+ }; \
+ \
+ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
+}
+
+GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
+GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
+GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
+
+GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+
+/* Vector Narrowing Integer Right Shift Instructions */
+static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+ 2 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+/* OPIVV with NARROW */
+#define GEN_OPIVV_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opivv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+GEN_OPIVV_NARROW_TRANS(vnsra_vv)
+GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
+
+static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+ 2 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+/* OPIVX with NARROW */
+#define GEN_OPIVX_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opivx_narrow_check(s, a)) { \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ } \
+ return false; \
+}
+
+GEN_OPIVX_NARROW_TRANS(vnsra_vx)
+GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
+
+/* OPIVI with NARROW */
+#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opivx_narrow_check(s, a)) { \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##OPIVX##_b, \
+ gen_helper_##OPIVX##_h, \
+ gen_helper_##OPIVX##_w, \
+ }; \
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, ZX); \
+ } \
+ return false; \
+}
+
+GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
+GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
+
+/* Vector Integer Comparison Instructions */
+/*
+ * For all comparison instructions, an illegal instruction exception is raised
+ * if the destination vector register overlaps a source vector register group
+ * and LMUL > 1.
+ */
+static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
+ vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
+ (s->lmul == 0)));
+}
+GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
+GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
+GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
+GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check)
+GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check)
+GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
+
+static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
+ (s->lmul == 0)));
+}
+
+GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
+
+GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
+
+/* Vector Integer Min/Max Instructions */
+GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
+GEN_OPIVV_GVEC_TRANS(vmin_vv, smin)
+GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax)
+GEN_OPIVV_GVEC_TRANS(vmax_vv, smax)
+GEN_OPIVX_TRANS(vminu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmin_vx, opivx_check)
+GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmax_vx, opivx_check)
+
+/* Vector Single-Width Integer Multiply Instructions */
+GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
+GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
+GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
+
+/* Vector Integer Divide Instructions */
+GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
+GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
+GEN_OPIVV_TRANS(vremu_vv, opivv_check)
+GEN_OPIVV_TRANS(vrem_vv, opivv_check)
+GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
+GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
+GEN_OPIVX_TRANS(vremu_vx, opivx_check)
+GEN_OPIVX_TRANS(vrem_vx, opivx_check)
+
+/* Vector Widening Integer Multiply Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
+
+/* Vector Single-Width Integer Multiply-Add Instructions */
+GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
+GEN_OPIVV_TRANS(vnmsac_vv, opivv_check)
+GEN_OPIVV_TRANS(vmadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vnmsub_vv, opivv_check)
+GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
+GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
+GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
+
+/* Vector Widening Integer Multiply-Add Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
+
+/* Vector Integer Merge and Move Instructions */
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs1, false)) {
+
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+ } else {
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+ gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ }
+ return true;
+ }
+ return false;
+}
+
+typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
+static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false)) {
+
+ TCGv s1;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ s1 = tcg_temp_new();
+ gen_get_gpr(s1, a->rs1);
+
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+ } else {
+ TCGv_i32 desc ;
+ TCGv_i64 s1_i64 = tcg_temp_new_i64();
+ TCGv_ptr dest = tcg_temp_new_ptr();
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_vmv_vx * const fns[4] = {
+ gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+ };
+
+ tcg_gen_ext_tl_i64(s1_i64, s1);
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1_i64, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(s1_i64);
+ }
+
+ tcg_temp_free(s1);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false)) {
+
+ int64_t simm = sextract64(a->rs1, 0, 5);
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), simm);
+ } else {
+ TCGv_i32 desc;
+ TCGv_i64 s1;
+ TCGv_ptr dest;
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_vmv_vx * const fns[4] = {
+ gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ s1 = tcg_const_i64(simm);
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(s1);
+ gen_set_label(over);
+ }
+ return true;
+ }
+ return false;
+}
+
+GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
+GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
+GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
+
+/*
+ *** Vector Fixed-Point Arithmetic Instructions
+ */
+
+/* Vector Single-Width Saturating Add and Subtract */
+GEN_OPIVV_TRANS(vsaddu_vv, opivv_check)
+GEN_OPIVV_TRANS(vsadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vssubu_vv, opivv_check)
+GEN_OPIVV_TRANS(vssub_vv, opivv_check)
+GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
+GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
+GEN_OPIVX_TRANS(vssub_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
+
+/* Vector Single-Width Averaging Add and Subtract */
+GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vasub_vv, opivv_check)
+GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vasub_vx, opivx_check)
+GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
+
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
+GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
+
+/* Vector Widening Saturating Scaled Multiply-Add */
+GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
+
+/* Vector Single-Width Scaling Shift Instructions */
+GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
+GEN_OPIVV_TRANS(vssra_vv, opivv_check)
+GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
+GEN_OPIVX_TRANS(vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
+
+/* Vector Narrowing Fixed-Point Clip Instructions */
+GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
+GEN_OPIVV_NARROW_TRANS(vnclip_vv)
+GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
+GEN_OPIVX_NARROW_TRANS(vnclip_vx)
+GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
+GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
+
+/*
+ *** Vector Float Point Arithmetic Instructions
+ */
+/* Vector Single-Width Floating-Point Add/Subtract Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised.
+ */
+static bool opfvv_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ (s->sew != 0));
+}
+
+/* OPFVV without GVEC IR */
+#define GEN_OPFVV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
+
+typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
+ TCGv_env, TCGv_i32);
+
+static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
+ uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
+{
+ TCGv_ptr dest, src2, mask;
+ TCGv_i32 desc;
+
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ return true;
+}
+
+static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+{
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (s->sew != 0));
+}
+
+/* OPFVF without GVEC IR */
+#define GEN_OPFVF_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_opfvf *const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d, \
+ }; \
+ gen_set_rm(s, 7); \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
+ fns[s->sew - 1], s); \
+ } \
+ return false; \
+}
+
+GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Add/Subtract Instructions */
+static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+/* OPFVV with WIDEN */
+#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[2] = { \
+ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
+
+static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+/* OPFVF with WIDEN */
+#define GEN_OPFVF_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opfvf_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_opfvf *const fns[2] = { \
+ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
+ }; \
+ gen_set_rm(s, 7); \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
+ fns[s->sew - 1], s); \
+ } \
+ return false; \
+}
+
+GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
+
+static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+/* WIDEN OPFVV with WIDEN */
+#define GEN_OPFWV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opfwv_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[2] = { \
+ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
+GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
+
+static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, true) &&
+ (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+/* WIDEN OPFVF with WIDEN */
+#define GEN_OPFWF_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opfwf_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_opfvf *const fns[2] = { \
+ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
+ }; \
+ gen_set_rm(s, 7); \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
+ fns[s->sew - 1], s); \
+ } \
+ return false; \
+}
+
+GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
+GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
+
+/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
+GEN_OPFVV_TRANS(vfmul_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
+GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Multiply */
+GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
+
+/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
+GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
+GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
+GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
+
+/* Vector Floating-Point Square-Root Instruction */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_check(DisasContext *s, arg_rmr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (s->sew != 0));
+}
+
+#define GEN_OPFV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
+
+/* Vector Floating-Point MIN/MAX Instructions */
+GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
+GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
+
+/* Vector Floating-Point Sign-Injection Instructions */
+GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
+GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
+
+/* Vector Floating-Point Compare Instructions */
+static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ (s->sew != 0) &&
+ ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
+ vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
+ (s->lmul == 0)));
+}
+
+GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
+GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
+GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
+GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
+GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
+
+static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (s->sew != 0) &&
+ (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
+ (s->lmul == 0)));
+}
+
+GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
+GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check)
+GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
+GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
+GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
+GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
+GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
+
+/* Vector Floating-Point Classify Instruction */
+GEN_OPFV_TRANS(vfclass_v, opfv_check)
+
+/* Vector Floating-Point Merge Instruction */
+GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
+
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ (s->sew != 0)) {
+
+ if (s->vl_eq_vlmax) {
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ } else {
+ TCGv_ptr dest;
+ TCGv_i32 desc;
+ uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ static gen_helper_vmv_vx * const fns[3] = {
+ gen_helper_vmv_v_x_h,
+ gen_helper_vmv_v_x_w,
+ gen_helper_vmv_v_x_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ dest = tcg_temp_new_ptr();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free_i32(desc);
+ gen_set_label(over);
+ }
+ return true;
+ }
+ return false;
+}
+
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
+
+/* Widening Floating-Point/Integer Type-Convert Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, true) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+#define GEN_OPFV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opfv_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[2] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
+
+/* Narrowing Floating-Point/Integer Type-Convert Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+ 2 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+#define GEN_OPFV_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opfv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[2] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, 7); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+
+/*
+ *** Vector Reduction Operations
+ */
+/* Vector Single-Width Integer Reduction Instructions */
+static bool reduction_check(DisasContext *s, arg_rmrr *a)
+{
+ return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
+}
+
+GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
+GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check)
+GEN_OPIVV_TRANS(vredmax_vs, reduction_check)
+GEN_OPIVV_TRANS(vredminu_vs, reduction_check)
+GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
+GEN_OPIVV_TRANS(vredand_vs, reduction_check)
+GEN_OPIVV_TRANS(vredor_vs, reduction_check)
+GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
+
+/* Vector Widening Integer Reduction Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
+
+/* Vector Single-Width Floating-Point Reduction Instructions */
+GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
+GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
+GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
+
+/* Vector Widening Floating-Point Reduction Instructions */
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+
+/*
+ *** Vector Mask Operations
+ */
+
+/* Vector Mask-Register Logical Instructions */
+#define GEN_MM_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
+{ \
+ if (vext_check_isa_ill(s)) { \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_MM_TRANS(vmand_mm)
+GEN_MM_TRANS(vmnand_mm)
+GEN_MM_TRANS(vmandnot_mm)
+GEN_MM_TRANS(vmxor_mm)
+GEN_MM_TRANS(vmor_mm)
+GEN_MM_TRANS(vmnor_mm)
+GEN_MM_TRANS(vmornot_mm)
+GEN_MM_TRANS(vmxnor_mm)
+
+/* Vector mask population count vmpopc */
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
+{
+ if (vext_check_isa_ill(s)) {
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+ return true;
+ }
+ return false;
+}
+
+/* vmfirst find-first-set mask bit */
+static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+{
+ if (vext_check_isa_ill(s)) {
+ TCGv_ptr src2, mask;
+ TCGv dst;
+ TCGv_i32 desc;
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+
+ mask = tcg_temp_new_ptr();
+ src2 = tcg_temp_new_ptr();
+ dst = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+ gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free_ptr(mask);
+ tcg_temp_free_ptr(src2);
+ tcg_temp_free(dst);
+ tcg_temp_free_i32(desc);
+ return true;
+ }
+ return false;
+}
+
+/* vmsbf.m set-before-first mask bit */
+/* vmsif.m set-includ-first mask bit */
+/* vmsof.m set-only-first mask bit */
+#define GEN_M_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (vext_check_isa_ill(s)) { \
+ uint32_t data = 0; \
+ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
+ cpu_env, 0, s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_M_TRANS(vmsbf_m)
+GEN_M_TRANS(vmsif_m)
+GEN_M_TRANS(vmsof_m)
+
+/* Vector Iota Instruction */
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
+ (a->vm != 0 || a->rd != 0)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ static gen_helper_gvec_3_ptr * const fns[4] = {
+ gen_helper_viota_m_b, gen_helper_viota_m_h,
+ gen_helper_viota_m_w, gen_helper_viota_m_d,
+ };
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+/* Vector Element Index Instruction */
+static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
+{
+ if (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_vid_v_b, gen_helper_vid_v_h,
+ gen_helper_vid_v_w, gen_helper_vid_v_d,
+ };
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+/*
+ *** Vector Permutation Instructions
+ */
+
+/* Integer Extract Instruction */
+
+static void load_element(TCGv_i64 dest, TCGv_ptr base,
+ int ofs, int sew)
+{
+ switch (sew) {
+ case MO_8:
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ break;
+ case MO_16:
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ break;
+ case MO_32:
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ break;
+ case MO_64:
+ tcg_gen_ld_i64(dest, base, ofs);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+/* offset of the idx element with base regsiter r */
+static uint32_t endian_ofs(DisasContext *s, int r, int idx)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+ return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
+#else
+ return vreg_ofs(s, r) + (idx << s->sew);
+#endif
+}
+
+/* adjust the index according to the endian */
+static void endian_adjust(TCGv_i32 ofs, int sew)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+ tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
+#endif
+}
+
+/* Load idx >= VLMAX ? 0 : vreg[idx] */
+static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
+ int vreg, TCGv idx, int vlmax)
+{
+ TCGv_i32 ofs = tcg_temp_new_i32();
+ TCGv_ptr base = tcg_temp_new_ptr();
+ TCGv_i64 t_idx = tcg_temp_new_i64();
+ TCGv_i64 t_vlmax, t_zero;
+
+ /*
+ * Mask the index to the length so that we do
+ * not produce an out-of-range load.
+ */
+ tcg_gen_trunc_tl_i32(ofs, idx);
+ tcg_gen_andi_i32(ofs, ofs, vlmax - 1);
+
+ /* Convert the index to an offset. */
+ endian_adjust(ofs, s->sew);
+ tcg_gen_shli_i32(ofs, ofs, s->sew);
+
+ /* Convert the index to a pointer. */
+ tcg_gen_ext_i32_ptr(base, ofs);
+ tcg_gen_add_ptr(base, base, cpu_env);
+
+ /* Perform the load. */
+ load_element(dest, base,
+ vreg_ofs(s, vreg), s->sew);
+ tcg_temp_free_ptr(base);
+ tcg_temp_free_i32(ofs);
+
+ /* Flush out-of-range indexing to zero. */
+ t_vlmax = tcg_const_i64(vlmax);
+ t_zero = tcg_const_i64(0);
+ tcg_gen_extu_tl_i64(t_idx, idx);
+
+ tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
+ t_vlmax, dest, t_zero);
+
+ tcg_temp_free_i64(t_vlmax);
+ tcg_temp_free_i64(t_zero);
+ tcg_temp_free_i64(t_idx);
+}
+
+static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
+ int vreg, int idx)
+{
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+static bool trans_vext_x_v(DisasContext *s, arg_r *a)
+{
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv dest = tcg_temp_new();
+
+ if (a->rs1 == 0) {
+ /* Special case vmv.x.s rd, vs2. */
+ vec_element_loadi(s, tmp, a->rs2, 0);
+ } else {
+ /* This instruction ignores LMUL and vector register groups */
+ int vlmax = s->vlen >> (3 + s->sew);
+ vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
+ }
+ tcg_gen_trunc_i64_tl(dest, tmp);
+ gen_set_gpr(a->rd, dest);
+
+ tcg_temp_free(dest);
+ tcg_temp_free_i64(tmp);
+ return true;
+}
+
+/* Integer Scalar Move Instruction */
+
+static void store_element(TCGv_i64 val, TCGv_ptr base,
+ int ofs, int sew)
+{
+ switch (sew) {
+ case MO_8:
+ tcg_gen_st8_i64(val, base, ofs);
+ break;
+ case MO_16:
+ tcg_gen_st16_i64(val, base, ofs);
+ break;
+ case MO_32:
+ tcg_gen_st32_i64(val, base, ofs);
+ break;
+ case MO_64:
+ tcg_gen_st_i64(val, base, ofs);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+/*
+ * Store vreg[idx] = val.
+ * The index must be in range of VLMAX.
+ */
+static void vec_element_storei(DisasContext *s, int vreg,
+ int idx, TCGv_i64 val)
+{
+ store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+/* vmv.s.x vd, rs1 # vd[0] = rs1 */
+static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
+{
+ if (vext_check_isa_ill(s)) {
+ /* This instruction ignores LMUL and vector register groups */
+ int maxsz = s->vlen >> 3;
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
+ if (a->rs1 == 0) {
+ goto done;
+ }
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ done:
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+/* Floating-Point Scalar Move Instructions */
+static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
+{
+ if (!s->vill && has_ext(s, RVF) &&
+ (s->mstatus_fs != 0) && (s->sew != 0)) {
+ unsigned int len = 8 << s->sew;
+
+ vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
+ if (len < 64) {
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
+ MAKE_64BIT_MASK(len, 64 - len));
+ }
+
+ mark_fs_dirty(s);
+ return true;
+ }
+ return false;
+}
+
+/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
+static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
+{
+ if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
+ TCGv_i64 t1;
+ /* The instructions ignore LMUL and vector register group. */
+ uint32_t vlmax = s->vlen >> 3;
+
+ /* if vl == 0, skip vector register write back */
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ /* zeroed all elements */
+ tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
+
+ /* NaN-box f[rs1] as necessary for SEW */
+ t1 = tcg_temp_new_i64();
+ if (s->sew == MO_64 && !has_ext(s, RVD)) {
+ tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
+ } else {
+ tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
+ }
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+/* Vector Slide Instructions */
+static bool slideup_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (a->rd != a->rs2));
+}
+
+GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
+GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
+GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
+
+GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
+GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
+GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
+
+/* Vector Register Gather Instruction */
+static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (a->rd != a->rs2) && (a->rd != a->rs1));
+}
+
+GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
+
+static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ (a->rd != a->rs2));
+}
+
+/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
+static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
+{
+ if (!vrgather_vx_check(s, a)) {
+ return false;
+ }
+
+ if (a->vm && s->vl_eq_vlmax) {
+ int vlmax = s->vlen / s->mlen;
+ TCGv_i64 dest = tcg_temp_new_i64();
+
+ if (a->rs1 == 0) {
+ vec_element_loadi(s, dest, a->rs2, 0);
+ } else {
+ vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
+ }
+
+ tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), dest);
+ tcg_temp_free_i64(dest);
+ } else {
+ static gen_helper_opivx * const fns[4] = {
+ gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
+ gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
+ };
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
+ }
+ return true;
+}
+
+/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
+static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
+{
+ if (!vrgather_vx_check(s, a)) {
+ return false;
+ }
+
+ if (a->vm && s->vl_eq_vlmax) {
+ if (a->rs1 >= s->vlen / s->mlen) {
+ tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), 0);
+ } else {
+ tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
+ endian_ofs(s, a->rs2, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+ }
+ } else {
+ static gen_helper_opivx * const fns[4] = {
+ gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
+ gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
+ };
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1);
+ }
+ return true;
+}
+
+/* Vector Compress Instruction */
+static bool vcompress_vm_check(DisasContext *s, arg_r *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, false) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
+ (a->rd != a->rs2));
+}
+
+static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
+{
+ if (vcompress_vm_check(s, a)) {
+ uint32_t data = 0;
+ static gen_helper_gvec_4_ptr * const fns[4] = {
+ gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
+ gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
+ };
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+++ /dev/null
-/*
- * RISC-V translation routines for the RVV Standard Extension.
- *
- * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-#include "tcg/tcg-op-gvec.h"
-#include "tcg/tcg-gvec-desc.h"
-#include "internals.h"
-
-static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
-{
- TCGv s1, s2, dst;
-
- if (!has_ext(ctx, RVV)) {
- return false;
- }
-
- s2 = tcg_temp_new();
- dst = tcg_temp_new();
-
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
- gen_get_gpr(s2, a->rs2);
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
- gen_set_gpr(a->rd, dst);
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- lookup_and_goto_ptr(ctx);
- ctx->base.is_jmp = DISAS_NORETURN;
-
- tcg_temp_free(s1);
- tcg_temp_free(s2);
- tcg_temp_free(dst);
- return true;
-}
-
-static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
-{
- TCGv s1, s2, dst;
-
- if (!has_ext(ctx, RVV)) {
- return false;
- }
-
- s2 = tcg_const_tl(a->zimm);
- dst = tcg_temp_new();
-
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
- gen_set_gpr(a->rd, dst);
- gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
- ctx->base.is_jmp = DISAS_NORETURN;
-
- tcg_temp_free(s1);
- tcg_temp_free(s2);
- tcg_temp_free(dst);
- return true;
-}
-
-/* vector register offset from env */
-static uint32_t vreg_ofs(DisasContext *s, int reg)
-{
- return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
-}
-
-/* check functions */
-
-/*
- * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
- * So RVV is also be checked in this function.
- */
-static bool vext_check_isa_ill(DisasContext *s)
-{
- return !s->vill;
-}
-
-/*
- * There are two rules check here.
- *
- * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
- *
- * 2. For all widening instructions, the destination LMUL value must also be
- * a supported LMUL value. (Section 11.2)
- */
-static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
-{
- /*
- * The destination vector register group results are arranged as if both
- * SEW and LMUL were at twice their current settings. (Section 11.2).
- */
- int legal = widen ? 2 << s->lmul : 1 << s->lmul;
-
- return !((s->lmul == 0x3 && widen) || (reg % legal));
-}
-
-/*
- * There are two rules check here.
- *
- * 1. The destination vector register group for a masked vector instruction can
- * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
- *
- * 2. In widen instructions and some other insturctions, like vslideup.vx,
- * there is no need to check whether LMUL=1.
- */
-static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
- bool force)
-{
- return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
-}
-
-/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
-static bool vext_check_nf(DisasContext *s, uint32_t nf)
-{
- return (1 << s->lmul) * nf <= 8;
-}
-
-/*
- * The destination vector register group cannot overlap a source vector register
- * group of a different element width. (Section 11.2)
- */
-static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
-{
- return ((rd >= rs + slen) || (rs >= rd + dlen));
-}
-/* common translation macro */
-#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
-{ \
- if (CHECK(s, a)) { \
- return OP(s, a, SEQ); \
- } \
- return false; \
-}
-
-/*
- *** unit stride load and store
- */
-typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
- TCGv_env, TCGv_i32);
-
-static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
- gen_helper_ldst_us *fn, DisasContext *s)
-{
- TCGv_ptr dest, mask;
- TCGv base;
- TCGv_i32 desc;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- base = tcg_temp_new();
-
- /*
- * As simd_desc supports at most 256 bytes, and in this implementation,
- * the max vector group length is 2048 bytes. So split it into two parts.
- *
- * The first part is vlen in bytes, encoded in maxsz of simd_desc.
- * The second part is lmul, encoded in data of simd_desc.
- */
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, base, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free(base);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][7][4] = {
- /* masked unit stride load */
- { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
- gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
- { NULL, gen_helper_vlh_v_h_mask,
- gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
- { NULL, NULL,
- gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
- { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
- gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
- { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
- gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
- { NULL, gen_helper_vlhu_v_h_mask,
- gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
- { NULL, NULL,
- gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
- /* unmasked unit stride load */
- { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
- gen_helper_vlb_v_w, gen_helper_vlb_v_d },
- { NULL, gen_helper_vlh_v_h,
- gen_helper_vlh_v_w, gen_helper_vlh_v_d },
- { NULL, NULL,
- gen_helper_vlw_v_w, gen_helper_vlw_v_d },
- { gen_helper_vle_v_b, gen_helper_vle_v_h,
- gen_helper_vle_v_w, gen_helper_vle_v_d },
- { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
- gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
- { NULL, gen_helper_vlhu_v_h,
- gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
- { NULL, NULL,
- gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
- };
-
- fn = fns[a->vm][seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s);
-}
-
-static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
-}
-
-GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
-
-static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][4][4] = {
- /* masked unit stride load and store */
- { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
- gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
- { NULL, gen_helper_vsh_v_h_mask,
- gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
- { NULL, NULL,
- gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
- { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
- gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
- /* unmasked unit stride store */
- { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
- gen_helper_vsb_v_w, gen_helper_vsb_v_d },
- { NULL, gen_helper_vsh_v_h,
- gen_helper_vsh_v_w, gen_helper_vsh_v_d },
- { NULL, NULL,
- gen_helper_vsw_v_w, gen_helper_vsw_v_d },
- { gen_helper_vse_v_b, gen_helper_vse_v_h,
- gen_helper_vse_v_w, gen_helper_vse_v_d } }
- };
-
- fn = fns[a->vm][seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s);
-}
-
-static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
-}
-
-GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
-
-/*
- *** stride load and store
- */
-typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
- TCGv, TCGv_env, TCGv_i32);
-
-static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
- uint32_t data, gen_helper_ldst_stride *fn,
- DisasContext *s)
-{
- TCGv_ptr dest, mask;
- TCGv base, stride;
- TCGv_i32 desc;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- base = tcg_temp_new();
- stride = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- gen_get_gpr(stride, rs2);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, base, stride, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free(base);
- tcg_temp_free(stride);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[7][4] = {
- { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
- gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
- { NULL, gen_helper_vlsh_v_h,
- gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
- { NULL, NULL,
- gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
- { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
- gen_helper_vlse_v_w, gen_helper_vlse_v_d },
- { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
- gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
- { NULL, gen_helper_vlshu_v_h,
- gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
- { NULL, NULL,
- gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
- };
-
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
-}
-
-static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
-}
-
-GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
-
-static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[4][4] = {
- /* masked stride store */
- { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
- gen_helper_vssb_v_w, gen_helper_vssb_v_d },
- { NULL, gen_helper_vssh_v_h,
- gen_helper_vssh_v_w, gen_helper_vssh_v_d },
- { NULL, NULL,
- gen_helper_vssw_v_w, gen_helper_vssw_v_d },
- { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
- gen_helper_vsse_v_w, gen_helper_vsse_v_d }
- };
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
-}
-
-static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
-}
-
-GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
-
-/*
- *** index load and store
- */
-typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
- TCGv_ptr, TCGv_env, TCGv_i32);
-
-static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- uint32_t data, gen_helper_ldst_index *fn,
- DisasContext *s)
-{
- TCGv_ptr dest, mask, index;
- TCGv base;
- TCGv_i32 desc;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- index = tcg_temp_new_ptr();
- base = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, base, index, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(index);
- tcg_temp_free(base);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_index *fn;
- static gen_helper_ldst_index * const fns[7][4] = {
- { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
- gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
- { NULL, gen_helper_vlxh_v_h,
- gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
- { NULL, NULL,
- gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
- { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
- gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
- { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
- gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
- { NULL, gen_helper_vlxhu_v_h,
- gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
- { NULL, NULL,
- gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
- };
-
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
-}
-
-/*
- * For vector indexed segment loads, the destination vector register
- * groups cannot overlap the source vector register group (specified by
- * `vs2`), else an illegal instruction exception is raised.
- */
-static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf) &&
- ((a->nf == 1) ||
- vext_check_overlap_group(a->rd, a->nf << s->lmul,
- a->rs2, 1 << s->lmul)));
-}
-
-GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
-
-static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_index *fn;
- static gen_helper_ldst_index * const fns[4][4] = {
- { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
- gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
- { NULL, gen_helper_vsxh_v_h,
- gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
- { NULL, NULL,
- gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
- { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
- gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
- };
-
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
-}
-
-static bool st_index_check(DisasContext *s, arg_rnfvm* a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
-}
-
-GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
-
-/*
- *** unit stride fault-only-first load
- */
-static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
- gen_helper_ldst_us *fn, DisasContext *s)
-{
- TCGv_ptr dest, mask;
- TCGv base;
- TCGv_i32 desc;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- base = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, base, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free(base);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[7][4] = {
- { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
- gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
- { NULL, gen_helper_vlhff_v_h,
- gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
- { NULL, NULL,
- gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
- { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
- gen_helper_vleff_v_w, gen_helper_vleff_v_d },
- { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
- gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
- { NULL, gen_helper_vlhuff_v_h,
- gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
- { NULL, NULL,
- gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
- };
-
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldff_trans(a->rd, a->rs1, data, fn, s);
-}
-
-GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
-
-/*
- *** vector atomic operation
- */
-typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
- TCGv_env, TCGv_i32);
-
-static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- uint32_t data, gen_helper_amo *fn, DisasContext *s)
-{
- TCGv_ptr dest, mask, index;
- TCGv base;
- TCGv_i32 desc;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- index = tcg_temp_new_ptr();
- base = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, base, index, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(index);
- tcg_temp_free(base);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
-{
- uint32_t data = 0;
- gen_helper_amo *fn;
- static gen_helper_amo *const fnsw[9] = {
- /* no atomic operation */
- gen_helper_vamoswapw_v_w,
- gen_helper_vamoaddw_v_w,
- gen_helper_vamoxorw_v_w,
- gen_helper_vamoandw_v_w,
- gen_helper_vamoorw_v_w,
- gen_helper_vamominw_v_w,
- gen_helper_vamomaxw_v_w,
- gen_helper_vamominuw_v_w,
- gen_helper_vamomaxuw_v_w
- };
-#ifdef TARGET_RISCV64
- static gen_helper_amo *const fnsd[18] = {
- gen_helper_vamoswapw_v_d,
- gen_helper_vamoaddw_v_d,
- gen_helper_vamoxorw_v_d,
- gen_helper_vamoandw_v_d,
- gen_helper_vamoorw_v_d,
- gen_helper_vamominw_v_d,
- gen_helper_vamomaxw_v_d,
- gen_helper_vamominuw_v_d,
- gen_helper_vamomaxuw_v_d,
- gen_helper_vamoswapd_v_d,
- gen_helper_vamoaddd_v_d,
- gen_helper_vamoxord_v_d,
- gen_helper_vamoandd_v_d,
- gen_helper_vamoord_v_d,
- gen_helper_vamomind_v_d,
- gen_helper_vamomaxd_v_d,
- gen_helper_vamominud_v_d,
- gen_helper_vamomaxud_v_d
- };
-#endif
-
- if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_exit_atomic(cpu_env);
- s->base.is_jmp = DISAS_NORETURN;
- return true;
- } else {
- if (s->sew == 3) {
-#ifdef TARGET_RISCV64
- fn = fnsd[seq];
-#else
- /* Check done in amo_check(). */
- g_assert_not_reached();
-#endif
- } else {
- assert(seq < ARRAY_SIZE(fnsw));
- fn = fnsw[seq];
- }
- }
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- data = FIELD_DP32(data, VDATA, WD, a->wd);
- return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
-}
-/*
- * There are two rules check here.
- *
- * 1. SEW must be at least as wide as the AMO memory element size.
- *
- * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
- */
-static bool amo_check(DisasContext *s, arg_rwdvm* a)
-{
- return (!s->vill && has_ext(s, RVA) &&
- (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
- ((1 << s->sew) >= 4));
-}
-
-GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
-#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
-#endif
-
-/*
- *** Vector Integer Arithmetic Instructions
- */
-#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
-
-static bool opivv_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false));
-}
-
-typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
- uint32_t, uint32_t, uint32_t);
-
-static inline bool
-do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
- gen_helper_gvec_4_ptr *fn)
-{
- TCGLabel *over = gen_new_label();
- if (!opivv_check(s, a)) {
- return false;
- }
-
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- if (a->vm && s->vl_eq_vlmax) {
- gvec_fn(s->sew, vreg_ofs(s, a->rd),
- vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
- MAXSZ(s), MAXSZ(s));
- } else {
- uint32_t data = 0;
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- cpu_env, 0, s->vlen / 8, data, fn);
- }
- gen_set_label(over);
- return true;
-}
-
-/* OPIVV with GVEC IR */
-#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_gvec_4_ptr * const fns[4] = { \
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
- }; \
- return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
-}
-
-GEN_OPIVV_GVEC_TRANS(vadd_vv, add)
-GEN_OPIVV_GVEC_TRANS(vsub_vv, sub)
-
-typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
- TCGv_env, TCGv_i32);
-
-static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
- gen_helper_opivx *fn, DisasContext *s)
-{
- TCGv_ptr dest, src2, mask;
- TCGv src1;
- TCGv_i32 desc;
- uint32_t data = 0;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- src1 = tcg_temp_new();
- gen_get_gpr(src1, rs1);
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, src1, src2, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(src1);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool opivx_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false));
-}
-
-typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
- uint32_t, uint32_t);
-
-static inline bool
-do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
- gen_helper_opivx *fn)
-{
- if (!opivx_check(s, a)) {
- return false;
- }
-
- if (a->vm && s->vl_eq_vlmax) {
- TCGv_i64 src1 = tcg_temp_new_i64();
- TCGv tmp = tcg_temp_new();
-
- gen_get_gpr(tmp, a->rs1);
- tcg_gen_ext_tl_i64(src1, tmp);
- gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
- src1, MAXSZ(s), MAXSZ(s));
-
- tcg_temp_free_i64(src1);
- tcg_temp_free(tmp);
- return true;
- }
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
-}
-
-/* OPIVX with GVEC IR */
-#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_opivx * const fns[4] = { \
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
- }; \
- return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
-}
-
-GEN_OPIVX_GVEC_TRANS(vadd_vx, adds)
-GEN_OPIVX_GVEC_TRANS(vsub_vx, subs)
-
-static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- tcg_gen_vec_sub8_i64(d, b, a);
-}
-
-static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- tcg_gen_vec_sub16_i64(d, b, a);
-}
-
-static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-{
- tcg_gen_sub_i32(ret, arg2, arg1);
-}
-
-static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-{
- tcg_gen_sub_i64(ret, arg2, arg1);
-}
-
-static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
-{
- tcg_gen_sub_vec(vece, r, b, a);
-}
-
-static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
- TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
-{
- static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
- static const GVecGen2s rsub_op[4] = {
- { .fni8 = gen_vec_rsub8_i64,
- .fniv = gen_rsub_vec,
- .fno = gen_helper_vec_rsubs8,
- .opt_opc = vecop_list,
- .vece = MO_8 },
- { .fni8 = gen_vec_rsub16_i64,
- .fniv = gen_rsub_vec,
- .fno = gen_helper_vec_rsubs16,
- .opt_opc = vecop_list,
- .vece = MO_16 },
- { .fni4 = gen_rsub_i32,
- .fniv = gen_rsub_vec,
- .fno = gen_helper_vec_rsubs32,
- .opt_opc = vecop_list,
- .vece = MO_32 },
- { .fni8 = gen_rsub_i64,
- .fniv = gen_rsub_vec,
- .fno = gen_helper_vec_rsubs64,
- .opt_opc = vecop_list,
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
- .vece = MO_64 },
- };
-
- tcg_debug_assert(vece <= MO_64);
- tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
-}
-
-GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
-
-static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
- gen_helper_opivx *fn, DisasContext *s, int zx)
-{
- TCGv_ptr dest, src2, mask;
- TCGv src1;
- TCGv_i32 desc;
- uint32_t data = 0;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- if (zx) {
- src1 = tcg_const_tl(imm);
- } else {
- src1 = tcg_const_tl(sextract64(imm, 0, 5));
- }
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, src1, src2, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(src1);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
- uint32_t, uint32_t);
-
-static inline bool
-do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
- gen_helper_opivx *fn, int zx)
-{
- if (!opivx_check(s, a)) {
- return false;
- }
-
- if (a->vm && s->vl_eq_vlmax) {
- if (zx) {
- gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
- extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
- } else {
- gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
- sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
- }
- } else {
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
- }
- return true;
-}
-
-/* OPIVI with GVEC IR */
-#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_opivx * const fns[4] = { \
- gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
- gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
- }; \
- return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
- fns[s->sew], ZX); \
-}
-
-GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
-
-static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
- int64_t c, uint32_t oprsz, uint32_t maxsz)
-{
- TCGv_i64 tmp = tcg_const_i64(c);
- tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
- tcg_temp_free_i64(tmp);
-}
-
-GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
-
-/* Vector Widening Integer Add/Subtract */
-
-/* OPIVV with WIDEN */
-static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
-}
-
-static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
- gen_helper_gvec_4_ptr *fn,
- bool (*checkfn)(DisasContext *, arg_rmrr *))
-{
- if (checkfn(s, a)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2),
- cpu_env, 0, s->vlen / 8,
- data, fn);
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_gvec_4_ptr * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w \
- }; \
- return do_opivv_widen(s, a, fns[s->sew], CHECK); \
-}
-
-GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
-
-/* OPIVX with WIDEN */
-static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
-}
-
-static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
- gen_helper_opivx *fn)
-{
- if (opivx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
- }
- return false;
-}
-
-#define GEN_OPIVX_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_opivx * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w \
- }; \
- return do_opivx_widen(s, a, fns[s->sew]); \
-}
-
-GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
-
-/* WIDEN OPIVV with WIDEN */
-static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
-}
-
-static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
- gen_helper_gvec_4_ptr *fn)
-{
- if (opiwv_widen_check(s, a)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2),
- cpu_env, 0, s->vlen / 8, data, fn);
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-#define GEN_OPIWV_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_gvec_4_ptr * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w \
- }; \
- return do_opiwv_widen(s, a, fns[s->sew]); \
-}
-
-GEN_OPIWV_WIDEN_TRANS(vwaddu_wv)
-GEN_OPIWV_WIDEN_TRANS(vwadd_wv)
-GEN_OPIWV_WIDEN_TRANS(vwsubu_wv)
-GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
-
-/* WIDEN OPIVX with WIDEN */
-static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
-}
-
-static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
- gen_helper_opivx *fn)
-{
- if (opiwx_widen_check(s, a)) {
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
- }
- return false;
-}
-
-#define GEN_OPIWX_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_opivx * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w \
- }; \
- return do_opiwx_widen(s, a, fns[s->sew]); \
-}
-
-GEN_OPIWX_WIDEN_TRANS(vwaddu_wx)
-GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
-GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
-GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
-
-/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
-/* OPIVV without GVEC IR */
-#define GEN_OPIVV_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_4_ptr * const fns[4] = { \
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
- }; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-/*
- * For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.3)
- */
-static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
-}
-
-GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
-GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
-
-/*
- * For vmadc and vmsbc, an illegal instruction exception is raised if the
- * destination vector register overlaps a source vector register group.
- */
-static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
-}
-
-GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
-GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
-
-static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
-}
-
-/* OPIVX without GVEC IR */
-#define GEN_OPIVX_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- static gen_helper_opivx * const fns[4] = { \
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
- }; \
- \
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
- } \
- return false; \
-}
-
-GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check)
-GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
-
-static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
-}
-
-GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
-GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check)
-
-/* OPIVI without GVEC IR */
-#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- static gen_helper_opivx * const fns[4] = { \
- gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
- gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
- }; \
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
- fns[s->sew], s, ZX); \
- } \
- return false; \
-}
-
-GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check)
-GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check)
-
-/* Vector Bitwise Logical Instructions */
-GEN_OPIVV_GVEC_TRANS(vand_vv, and)
-GEN_OPIVV_GVEC_TRANS(vor_vv, or)
-GEN_OPIVV_GVEC_TRANS(vxor_vv, xor)
-GEN_OPIVX_GVEC_TRANS(vand_vx, ands)
-GEN_OPIVX_GVEC_TRANS(vor_vx, ors)
-GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
-GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
-GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
-GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
-
-/* Vector Single-Width Bit Shift Instructions */
-GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
-GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv)
-GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv)
-
-typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
- uint32_t, uint32_t);
-
-static inline bool
-do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
- gen_helper_opivx *fn)
-{
- if (!opivx_check(s, a)) {
- return false;
- }
-
- if (a->vm && s->vl_eq_vlmax) {
- TCGv_i32 src1 = tcg_temp_new_i32();
- TCGv tmp = tcg_temp_new();
-
- gen_get_gpr(tmp, a->rs1);
- tcg_gen_trunc_tl_i32(src1, tmp);
- tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
- gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
- src1, MAXSZ(s), MAXSZ(s));
-
- tcg_temp_free_i32(src1);
- tcg_temp_free(tmp);
- return true;
- }
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
-}
-
-#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- static gen_helper_opivx * const fns[4] = { \
- gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
- }; \
- \
- return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
-}
-
-GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
-GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
-GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-
-GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
-
-/* Vector Narrowing Integer Right Shift Instructions */
-static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
-}
-
-/* OPIVV with NARROW */
-#define GEN_OPIVV_NARROW_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (opivv_narrow_check(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_4_ptr * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- }; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-GEN_OPIVV_NARROW_TRANS(vnsra_vv)
-GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
-
-static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
-}
-
-/* OPIVX with NARROW */
-#define GEN_OPIVX_NARROW_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (opivx_narrow_check(s, a)) { \
- static gen_helper_opivx * const fns[3] = { \
- gen_helper_##NAME##_b, \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- }; \
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
- } \
- return false; \
-}
-
-GEN_OPIVX_NARROW_TRANS(vnsra_vx)
-GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
-
-/* OPIVI with NARROW */
-#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (opivx_narrow_check(s, a)) { \
- static gen_helper_opivx * const fns[3] = { \
- gen_helper_##OPIVX##_b, \
- gen_helper_##OPIVX##_h, \
- gen_helper_##OPIVX##_w, \
- }; \
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
- fns[s->sew], s, ZX); \
- } \
- return false; \
-}
-
-GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
-GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
-
-/* Vector Integer Comparison Instructions */
-/*
- * For all comparison instructions, an illegal instruction exception is raised
- * if the destination vector register overlaps a source vector register group
- * and LMUL > 1.
- */
-static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
-}
-GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
-GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
-GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
-GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check)
-GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check)
-GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
-
-static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
-}
-
-GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check)
-GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
-
-GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
-
-/* Vector Integer Min/Max Instructions */
-GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
-GEN_OPIVV_GVEC_TRANS(vmin_vv, smin)
-GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax)
-GEN_OPIVV_GVEC_TRANS(vmax_vv, smax)
-GEN_OPIVX_TRANS(vminu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmin_vx, opivx_check)
-GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmax_vx, opivx_check)
-
-/* Vector Single-Width Integer Multiply Instructions */
-GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
-GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
-GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
-GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
-
-/* Vector Integer Divide Instructions */
-GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
-GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
-GEN_OPIVV_TRANS(vremu_vv, opivv_check)
-GEN_OPIVV_TRANS(vrem_vv, opivv_check)
-GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
-GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
-GEN_OPIVX_TRANS(vremu_vx, opivx_check)
-GEN_OPIVX_TRANS(vrem_vx, opivx_check)
-
-/* Vector Widening Integer Multiply Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
-
-/* Vector Single-Width Integer Multiply-Add Instructions */
-GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
-GEN_OPIVV_TRANS(vnmsac_vv, opivv_check)
-GEN_OPIVV_TRANS(vmadd_vv, opivv_check)
-GEN_OPIVV_TRANS(vnmsub_vv, opivv_check)
-GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
-GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
-GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
-GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
-
-/* Vector Widening Integer Multiply-Add Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
-
-/* Vector Integer Merge and Move Instructions */
-static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
-{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false)) {
-
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
- vreg_ofs(s, a->rs1),
- MAXSZ(s), MAXSZ(s));
- } else {
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
- static gen_helper_gvec_2_ptr * const fns[4] = {
- gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
- gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- }
- return true;
- }
- return false;
-}
-
-typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
-static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
-{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
-
- TCGv s1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
-
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), s1);
- } else {
- TCGv_i32 desc ;
- TCGv_i64 s1_i64 = tcg_temp_new_i64();
- TCGv_ptr dest = tcg_temp_new_ptr();
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
- static gen_helper_vmv_vx * const fns[4] = {
- gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
- };
-
- tcg_gen_ext_tl_i64(s1_i64, s1);
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1_i64, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- tcg_temp_free_i64(s1_i64);
- }
-
- tcg_temp_free(s1);
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
-{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
-
- int64_t simm = sextract64(a->rs1, 0, 5);
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), simm);
- } else {
- TCGv_i32 desc;
- TCGv_i64 s1;
- TCGv_ptr dest;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
- static gen_helper_vmv_vx * const fns[4] = {
- gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- s1 = tcg_const_i64(simm);
- dest = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- tcg_temp_free_i64(s1);
- gen_set_label(over);
- }
- return true;
- }
- return false;
-}
-
-GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
-GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
-GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
-
-/*
- *** Vector Fixed-Point Arithmetic Instructions
- */
-
-/* Vector Single-Width Saturating Add and Subtract */
-GEN_OPIVV_TRANS(vsaddu_vv, opivv_check)
-GEN_OPIVV_TRANS(vsadd_vv, opivv_check)
-GEN_OPIVV_TRANS(vssubu_vv, opivv_check)
-GEN_OPIVV_TRANS(vssub_vv, opivv_check)
-GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
-GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
-GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
-GEN_OPIVX_TRANS(vssub_vx, opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
-GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
-
-/* Vector Single-Width Averaging Add and Subtract */
-GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
-GEN_OPIVV_TRANS(vasub_vv, opivv_check)
-GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
-GEN_OPIVX_TRANS(vasub_vx, opivx_check)
-GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
-
-/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
-GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
-GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
-
-/* Vector Widening Saturating Scaled Multiply-Add */
-GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
-
-/* Vector Single-Width Scaling Shift Instructions */
-GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
-GEN_OPIVV_TRANS(vssra_vv, opivv_check)
-GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
-GEN_OPIVX_TRANS(vssra_vx, opivx_check)
-GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
-GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
-
-/* Vector Narrowing Fixed-Point Clip Instructions */
-GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
-GEN_OPIVV_NARROW_TRANS(vnclip_vv)
-GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
-GEN_OPIVX_NARROW_TRANS(vnclip_vx)
-GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
-GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
-
-/*
- *** Vector Float Point Arithmetic Instructions
- */
-/* Vector Single-Width Floating-Point Add/Subtract Instructions */
-
-/*
- * If the current SEW does not correspond to a supported IEEE floating-point
- * type, an illegal instruction exception is raised.
- */
-static bool opfvv_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0));
-}
-
-/* OPFVV without GVEC IR */
-#define GEN_OPFVV_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_4_ptr * const fns[3] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- gen_helper_##NAME##_d, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
-
-typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
- TCGv_env, TCGv_i32);
-
-static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
-{
- TCGv_ptr dest, src2, mask;
- TCGv_i32 desc;
-
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- return true;
-}
-
-static bool opfvf_check(DisasContext *s, arg_rmrr *a)
-{
-/*
- * If the current SEW does not correspond to a supported IEEE floating-point
- * type, an illegal instruction exception is raised
- */
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
-}
-
-/* OPFVF without GVEC IR */
-#define GEN_OPFVF_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_opfvf *const fns[3] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- gen_helper_##NAME##_d, \
- }; \
- gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
- fns[s->sew - 1], s); \
- } \
- return false; \
-}
-
-GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
-
-/* Vector Widening Floating-Point Add/Subtract Instructions */
-static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
-}
-
-/* OPFVV with WIDEN */
-#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_4_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
-
-static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
-}
-
-/* OPFVF with WIDEN */
-#define GEN_OPFVF_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (opfvf_widen_check(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_opfvf *const fns[2] = { \
- gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
- }; \
- gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
- fns[s->sew - 1], s); \
- } \
- return false; \
-}
-
-GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
-
-static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
-}
-
-/* WIDEN OPFVV with WIDEN */
-#define GEN_OPFWV_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (opfwv_widen_check(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_4_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
-GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
-
-static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
-}
-
-/* WIDEN OPFVF with WIDEN */
-#define GEN_OPFWF_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
-{ \
- if (opfwf_widen_check(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_opfvf *const fns[2] = { \
- gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
- }; \
- gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
- fns[s->sew - 1], s); \
- } \
- return false; \
-}
-
-GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
-GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
-
-/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
-GEN_OPFVV_TRANS(vfmul_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
-GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
-
-/* Vector Widening Floating-Point Multiply */
-GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
-
-/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
-GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
-GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
-
-/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
-
-/* Vector Floating-Point Square-Root Instruction */
-
-/*
- * If the current SEW does not correspond to a supported IEEE floating-point
- * type, an illegal instruction exception is raised
- */
-static bool opfv_check(DisasContext *s, arg_rmr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
-}
-
-#define GEN_OPFV_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[3] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- gen_helper_##NAME##_d, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
-
-/* Vector Floating-Point MIN/MAX Instructions */
-GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
-GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
-
-/* Vector Floating-Point Sign-Injection Instructions */
-GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
-GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
-GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
-GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
-
-/* Vector Floating-Point Compare Instructions */
-static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
-}
-
-GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
-
-static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
-}
-
-GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
-
-/* Vector Floating-Point Classify Instruction */
-GEN_OPFV_TRANS(vfclass_v, opfv_check)
-
-/* Vector Floating-Point Merge Instruction */
-GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
-
-static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
-{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- (s->sew != 0)) {
-
- if (s->vl_eq_vlmax) {
- tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
- } else {
- TCGv_ptr dest;
- TCGv_i32 desc;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
- static gen_helper_vmv_vx * const fns[3] = {
- gen_helper_vmv_v_x_h,
- gen_helper_vmv_v_x_w,
- gen_helper_vmv_v_x_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- dest = tcg_temp_new_ptr();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
-
- tcg_temp_free_ptr(dest);
- tcg_temp_free_i32(desc);
- gen_set_label(over);
- }
- return true;
- }
- return false;
-}
-
-/* Single-Width Floating-Point/Integer Type-Convert Instructions */
-GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
-GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
-GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
-GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
-
-/* Widening Floating-Point/Integer Type-Convert Instructions */
-
-/*
- * If the current SEW does not correspond to a supported IEEE floating-point
- * type, an illegal instruction exception is raised
- */
-static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
-}
-
-#define GEN_OPFV_WIDEN_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
-{ \
- if (opfv_widen_check(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
-
-/* Narrowing Floating-Point/Integer Type-Convert Instructions */
-
-/*
- * If the current SEW does not correspond to a supported IEEE floating-point
- * type, an illegal instruction exception is raised
- */
-static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
-}
-
-#define GEN_OPFV_NARROW_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
-{ \
- if (opfv_narrow_check(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
-
-/*
- *** Vector Reduction Operations
- */
-/* Vector Single-Width Integer Reduction Instructions */
-static bool reduction_check(DisasContext *s, arg_rmrr *a)
-{
- return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
-}
-
-GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
-GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check)
-GEN_OPIVV_TRANS(vredmax_vs, reduction_check)
-GEN_OPIVV_TRANS(vredminu_vs, reduction_check)
-GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
-GEN_OPIVV_TRANS(vredand_vs, reduction_check)
-GEN_OPIVV_TRANS(vredor_vs, reduction_check)
-GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
-
-/* Vector Widening Integer Reduction Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
-GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
-
-/* Vector Single-Width Floating-Point Reduction Instructions */
-GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
-GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
-GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
-
-/* Vector Widening Floating-Point Reduction Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
-
-/*
- *** Vector Mask Operations
- */
-
-/* Vector Mask-Register Logical Instructions */
-#define GEN_MM_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_r *a) \
-{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_MM_TRANS(vmand_mm)
-GEN_MM_TRANS(vmnand_mm)
-GEN_MM_TRANS(vmandnot_mm)
-GEN_MM_TRANS(vmxor_mm)
-GEN_MM_TRANS(vmor_mm)
-GEN_MM_TRANS(vmnor_mm)
-GEN_MM_TRANS(vmornot_mm)
-GEN_MM_TRANS(vmxnor_mm)
-
-/* Vector mask population count vmpopc */
-static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
-{
- if (vext_check_isa_ill(s)) {
- TCGv_ptr src2, mask;
- TCGv dst;
- TCGv_i32 desc;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
- gen_set_gpr(a->rd, dst);
-
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(dst);
- tcg_temp_free_i32(desc);
- return true;
- }
- return false;
-}
-
-/* vmfirst find-first-set mask bit */
-static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
-{
- if (vext_check_isa_ill(s)) {
- TCGv_ptr src2, mask;
- TCGv dst;
- TCGv_i32 desc;
- uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-
- gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
- gen_set_gpr(a->rd, dst);
-
- tcg_temp_free_ptr(mask);
- tcg_temp_free_ptr(src2);
- tcg_temp_free(dst);
- tcg_temp_free_i32(desc);
- return true;
- }
- return false;
-}
-
-/* vmsbf.m set-before-first mask bit */
-/* vmsif.m set-includ-first mask bit */
-/* vmsof.m set-only-first mask bit */
-#define GEN_M_TRANS(NAME) \
-static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
-{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
- vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- cpu_env, 0, s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
-}
-
-GEN_M_TRANS(vmsbf_m)
-GEN_M_TRANS(vmsif_m)
-GEN_M_TRANS(vmsof_m)
-
-/* Vector Iota Instruction */
-static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
-{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
- (a->vm != 0 || a->rd != 0)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- static gen_helper_gvec_3_ptr * const fns[4] = {
- gen_helper_viota_m_b, gen_helper_viota_m_h,
- gen_helper_viota_m_w, gen_helper_viota_m_d,
- };
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs2), cpu_env, 0,
- s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-/* Vector Element Index Instruction */
-static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
-{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false)) {
- uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- static gen_helper_gvec_2_ptr * const fns[4] = {
- gen_helper_vid_v_b, gen_helper_vid_v_h,
- gen_helper_vid_v_w, gen_helper_vid_v_d,
- };
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-/*
- *** Vector Permutation Instructions
- */
-
-/* Integer Extract Instruction */
-
-static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
-{
- switch (sew) {
- case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
- break;
- case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
- break;
- case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
- break;
- case MO_64:
- tcg_gen_ld_i64(dest, base, ofs);
- break;
- default:
- g_assert_not_reached();
- break;
- }
-}
-
-/* offset of the idx element with base regsiter r */
-static uint32_t endian_ofs(DisasContext *s, int r, int idx)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
-#else
- return vreg_ofs(s, r) + (idx << s->sew);
-#endif
-}
-
-/* adjust the index according to the endian */
-static void endian_adjust(TCGv_i32 ofs, int sew)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
-#endif
-}
-
-/* Load idx >= VLMAX ? 0 : vreg[idx] */
-static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
- int vreg, TCGv idx, int vlmax)
-{
- TCGv_i32 ofs = tcg_temp_new_i32();
- TCGv_ptr base = tcg_temp_new_ptr();
- TCGv_i64 t_idx = tcg_temp_new_i64();
- TCGv_i64 t_vlmax, t_zero;
-
- /*
- * Mask the index to the length so that we do
- * not produce an out-of-range load.
- */
- tcg_gen_trunc_tl_i32(ofs, idx);
- tcg_gen_andi_i32(ofs, ofs, vlmax - 1);
-
- /* Convert the index to an offset. */
- endian_adjust(ofs, s->sew);
- tcg_gen_shli_i32(ofs, ofs, s->sew);
-
- /* Convert the index to a pointer. */
- tcg_gen_ext_i32_ptr(base, ofs);
- tcg_gen_add_ptr(base, base, cpu_env);
-
- /* Perform the load. */
- load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
- tcg_temp_free_ptr(base);
- tcg_temp_free_i32(ofs);
-
- /* Flush out-of-range indexing to zero. */
- t_vlmax = tcg_const_i64(vlmax);
- t_zero = tcg_const_i64(0);
- tcg_gen_extu_tl_i64(t_idx, idx);
-
- tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
- t_vlmax, dest, t_zero);
-
- tcg_temp_free_i64(t_vlmax);
- tcg_temp_free_i64(t_zero);
- tcg_temp_free_i64(t_idx);
-}
-
-static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
-{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
-}
-
-static bool trans_vext_x_v(DisasContext *s, arg_r *a)
-{
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv dest = tcg_temp_new();
-
- if (a->rs1 == 0) {
- /* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0);
- } else {
- /* This instruction ignores LMUL and vector register groups */
- int vlmax = s->vlen >> (3 + s->sew);
- vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
- }
- tcg_gen_trunc_i64_tl(dest, tmp);
- gen_set_gpr(a->rd, dest);
-
- tcg_temp_free(dest);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
-/* Integer Scalar Move Instruction */
-
-static void store_element(TCGv_i64 val, TCGv_ptr base,
- int ofs, int sew)
-{
- switch (sew) {
- case MO_8:
- tcg_gen_st8_i64(val, base, ofs);
- break;
- case MO_16:
- tcg_gen_st16_i64(val, base, ofs);
- break;
- case MO_32:
- tcg_gen_st32_i64(val, base, ofs);
- break;
- case MO_64:
- tcg_gen_st_i64(val, base, ofs);
- break;
- default:
- g_assert_not_reached();
- break;
- }
-}
-
-/*
- * Store vreg[idx] = val.
- * The index must be in range of VLMAX.
- */
-static void vec_element_storei(DisasContext *s, int vreg,
- int idx, TCGv_i64 val)
-{
- store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
-}
-
-/* vmv.s.x vd, rs1 # vd[0] = rs1 */
-static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
-{
- if (vext_check_isa_ill(s)) {
- /* This instruction ignores LMUL and vector register groups */
- int maxsz = s->vlen >> 3;
- TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
-
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
- if (a->rs1 == 0) {
- goto done;
- }
-
- t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
- vec_element_storei(s, a->rd, 0, t1);
- tcg_temp_free_i64(t1);
- done:
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-/* Floating-Point Scalar Move Instructions */
-static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
-{
- if (!s->vill && has_ext(s, RVF) &&
- (s->mstatus_fs != 0) && (s->sew != 0)) {
- unsigned int len = 8 << s->sew;
-
- vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
- if (len < 64) {
- tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
- MAKE_64BIT_MASK(len, 64 - len));
- }
-
- mark_fs_dirty(s);
- return true;
- }
- return false;
-}
-
-/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
-static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
-{
- if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
- TCGv_i64 t1;
- /* The instructions ignore LMUL and vector register group. */
- uint32_t vlmax = s->vlen >> 3;
-
- /* if vl == 0, skip vector register write back */
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- /* zeroed all elements */
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
-
- /* NaN-box f[rs1] as necessary for SEW */
- t1 = tcg_temp_new_i64();
- if (s->sew == MO_64 && !has_ext(s, RVD)) {
- tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
- } else {
- tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
- }
- vec_element_storei(s, a->rd, 0, t1);
- tcg_temp_free_i64(t1);
- gen_set_label(over);
- return true;
- }
- return false;
-}
-
-/* Vector Slide Instructions */
-static bool slideup_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
-}
-
-GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
-GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
-
-GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
-GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
-
-/* Vector Register Gather Instruction */
-static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2) && (a->rd != a->rs1));
-}
-
-GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
-
-static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
-}
-
-/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
-static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
-{
- if (!vrgather_vx_check(s, a)) {
- return false;
- }
-
- if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen / s->mlen;
- TCGv_i64 dest = tcg_temp_new_i64();
-
- if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
- } else {
- vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
- }
-
- tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), dest);
- tcg_temp_free_i64(dest);
- } else {
- static gen_helper_opivx * const fns[4] = {
- gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
- gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
- };
- return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
- }
- return true;
-}
-
-/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
-static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
-{
- if (!vrgather_vx_check(s, a)) {
- return false;
- }
-
- if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen / s->mlen) {
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), 0);
- } else {
- tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
- endian_ofs(s, a->rs2, a->rs1),
- MAXSZ(s), MAXSZ(s));
- }
- } else {
- static gen_helper_opivx * const fns[4] = {
- gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
- gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
- };
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1);
- }
- return true;
-}
-
-/* Vector Compress Instruction */
-static bool vcompress_vm_check(DisasContext *s, arg_r *a)
-{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
- (a->rd != a->rs2));
-}
-
-static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
-{
- if (vcompress_vm_check(s, a)) {
- uint32_t data = 0;
- static gen_helper_gvec_4_ptr * const fns[4] = {
- gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
- gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
- };
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- gen_set_label(over);
- return true;
- }
- return false;
-}
}
/* Include the auto-generated decoder for 32 bit insn */
-#include "decode_insn32.inc.c"
+#include "decode_insn32.c.inc"
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
void (*func)(TCGv, TCGv, target_long))
}
/* Include insn module translation function */
-#include "insn_trans/trans_rvi.inc.c"
-#include "insn_trans/trans_rvm.inc.c"
-#include "insn_trans/trans_rva.inc.c"
-#include "insn_trans/trans_rvf.inc.c"
-#include "insn_trans/trans_rvd.inc.c"
-#include "insn_trans/trans_rvh.inc.c"
-#include "insn_trans/trans_rvv.inc.c"
-#include "insn_trans/trans_privileged.inc.c"
+#include "insn_trans/trans_rvi.c.inc"
+#include "insn_trans/trans_rvm.c.inc"
+#include "insn_trans/trans_rva.c.inc"
+#include "insn_trans/trans_rvf.c.inc"
+#include "insn_trans/trans_rvd.c.inc"
+#include "insn_trans/trans_rvh.c.inc"
+#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
-#include "decode_insn16.inc.c"
+#include "decode_insn16.c.inc"
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
-target/rx/decode.inc.c: \
+target/rx/decode.c.inc: \
$(SRC_PATH)/target/rx/insns.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@)
-target/rx/translate.o: target/rx/decode.inc.c
-target/rx/disas.o: target/rx/decode.inc.c
+target/rx/translate.o: target/rx/decode.c.inc
+target/rx/disas.o: target/rx/decode.c.inc
}
/* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
static void dump_bytes(DisasContext *ctx)
{
}
/* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
}
#endif
-#include "translate_vx.inc.c"
+#include "translate_vx.c.inc"
/* ====================================================================== */
/* The "Cc OUTput" generators. Given the generated output (and in some cases
--- /dev/null
+/*
+ * QEMU TCG support -- s390x vector instruction translation functions
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * For most instructions that use the same element size for reads and
+ * writes, we can use real gvec vector expansion, which potantially uses
+ * real host vector instructions. As they only work up to 64 bit elements,
+ * 128 bit elements (vector is a single element) have to be handled
+ * differently. Operations that are too complicated to encode via TCG ops
+ * are handled via gvec ool (out-of-line) handlers.
+ *
+ * As soon as instructions use different element sizes for reads and writes
+ * or access elements "out of their element scope" we expand them manually
+ * in fancy loops, as gvec expansion does not deal with actual element
+ * numbers and does also not support access to other elements.
+ *
+ * 128 bit elements:
+ * As we only have i32/i64, such elements have to be loaded into two
+ * i64 values and can then be processed e.g. by tcg_gen_add2_i64.
+ *
+ * Sizes:
+ * On s390x, the operand size (oprsz) and the maximum size (maxsz) are
+ * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",
+ * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only
+ * 128 bit element size has to be treated in a special way (MO_64 + 1).
+ * We will use ES_* instead of MO_* for this reason in this file.
+ *
+ * CC handling:
+ * As gvec ool-helpers can currently not return values (besides via
+ * pointers like vectors or cpu_env), whenever we have to set the CC and
+ * can't conclude the value from the result vector, we will directly
+ * set it in "env->cc_op" and mark it as static via set_cc_static()".
+ * Whenever this is done, the helper writes globals (cc_op).
+ */
+
+#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es))
+#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))
+#define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)
+
+#define ES_8 MO_8
+#define ES_16 MO_16
+#define ES_32 MO_32
+#define ES_64 MO_64
+#define ES_128 4
+
+/* Floating-Point Format */
+#define FPF_SHORT 2
+#define FPF_LONG 3
+#define FPF_EXT 4
+
+static inline bool valid_vec_element(uint8_t enr, MemOp es)
+{
+ return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));
+}
+
+static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
+ MemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_ld8u_i64(dst, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i64(dst, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_ld32u_i64(dst, cpu_env, offs);
+ break;
+ case ES_8 | MO_SIGN:
+ tcg_gen_ld8s_i64(dst, cpu_env, offs);
+ break;
+ case ES_16 | MO_SIGN:
+ tcg_gen_ld16s_i64(dst, cpu_env, offs);
+ break;
+ case ES_32 | MO_SIGN:
+ tcg_gen_ld32s_i64(dst, cpu_env, offs);
+ break;
+ case ES_64:
+ case ES_64 | MO_SIGN:
+ tcg_gen_ld_i64(dst, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
+ MemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_ld8u_i32(dst, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i32(dst, cpu_env, offs);
+ break;
+ case ES_8 | MO_SIGN:
+ tcg_gen_ld8s_i32(dst, cpu_env, offs);
+ break;
+ case ES_16 | MO_SIGN:
+ tcg_gen_ld16s_i32(dst, cpu_env, offs);
+ break;
+ case ES_32:
+ case ES_32 | MO_SIGN:
+ tcg_gen_ld_i32(dst, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
+ MemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_st8_i64(src, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_st16_i64(src, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_st32_i64(src, cpu_env, offs);
+ break;
+ case ES_64:
+ tcg_gen_st_i64(src, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
+ MemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_st8_i32(src, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_st16_i32(src, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_st_i32(src, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
+ uint8_t es)
+{
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ /* mask off invalid parts from the element nr */
+ tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1);
+
+ /* convert it to an element offset relative to cpu_env (vec_reg_offset() */
+ tcg_gen_shli_i64(tmp, tmp, es);
+#ifndef HOST_WORDS_BIGENDIAN
+ tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
+#endif
+ tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
+
+ /* generate the final ptr by adding cpu_env */
+ tcg_gen_trunc_i64_ptr(ptr, tmp);
+ tcg_gen_add_ptr(ptr, ptr, cpu_env);
+
+ tcg_temp_free_i64(tmp);
+}
+
+#define gen_gvec_2(v1, v2, gen) \
+ tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, gen)
+#define gen_gvec_2s(v1, v2, c, gen) \
+ tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, c, gen)
+#define gen_gvec_2_ool(v1, v2, data, fn) \
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, data, fn)
+#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
+ tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ c, 16, 16, data, fn)
+#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ ptr, 16, 16, data, fn)
+#define gen_gvec_3(v1, v2, v3, gen) \
+ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16, gen)
+#define gen_gvec_3_ool(v1, v2, v3, data, fn) \
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16, data, fn)
+#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
+#define gen_gvec_3i(v1, v2, v3, c, gen) \
+ tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16, c, gen)
+#define gen_gvec_4(v1, v2, v3, v4, gen) \
+ tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
+ 16, 16, gen)
+#define gen_gvec_4_ool(v1, v2, v3, v4, data, fn) \
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
+ 16, 16, data, fn)
+#define gen_gvec_4_ptr(v1, v2, v3, v4, ptr, data, fn) \
+ tcg_gen_gvec_4_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
+ ptr, 16, 16, data, fn)
+#define gen_gvec_dup_i64(es, v1, c) \
+ tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
+#define gen_gvec_mov(v1, v2) \
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
+ 16)
+#define gen_gvec_dup_imm(es, v1, c) \
+ tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
+#define gen_gvec_fn_2(fn, es, v1, v2) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16)
+#define gen_gvec_fn_2i(fn, es, v1, v2, c) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ c, 16, 16)
+#define gen_gvec_fn_2s(fn, es, v1, v2, s) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ s, 16, 16)
+#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16)
+#define gen_gvec_fn_4(fn, es, v1, v2, v3, v4) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), vec_full_reg_offset(v4), 16, 16)
+
+/*
+ * Helper to carry out a 128 bit vector computation using 2 i64 values per
+ * vector.
+ */
+typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
+static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
+ uint8_t b)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 dl = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 al = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+ TCGv_i64 bl = tcg_temp_new_i64();
+
+ read_vec_element_i64(ah, a, 0, ES_64);
+ read_vec_element_i64(al, a, 1, ES_64);
+ read_vec_element_i64(bh, b, 0, ES_64);
+ read_vec_element_i64(bl, b, 1, ES_64);
+ fn(dl, dh, al, ah, bl, bh);
+ write_vec_element_i64(dh, d, 0, ES_64);
+ write_vec_element_i64(dl, d, 1, ES_64);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(dl);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(bh);
+ tcg_temp_free_i64(bl);
+}
+
+typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh,
+ TCGv_i64 cl, TCGv_i64 ch);
+static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
+ uint8_t b, uint8_t c)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 dl = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 al = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+ TCGv_i64 bl = tcg_temp_new_i64();
+ TCGv_i64 ch = tcg_temp_new_i64();
+ TCGv_i64 cl = tcg_temp_new_i64();
+
+ read_vec_element_i64(ah, a, 0, ES_64);
+ read_vec_element_i64(al, a, 1, ES_64);
+ read_vec_element_i64(bh, b, 0, ES_64);
+ read_vec_element_i64(bl, b, 1, ES_64);
+ read_vec_element_i64(ch, c, 0, ES_64);
+ read_vec_element_i64(cl, c, 1, ES_64);
+ fn(dl, dh, al, ah, bl, bh, cl, ch);
+ write_vec_element_i64(dh, d, 0, ES_64);
+ write_vec_element_i64(dl, d, 1, ES_64);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(dl);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(bh);
+ tcg_temp_free_i64(bl);
+ tcg_temp_free_i64(ch);
+ tcg_temp_free_i64(cl);
+}
+
+static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ uint64_t b)
+{
+ TCGv_i64 bl = tcg_const_i64(b);
+ TCGv_i64 bh = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ tcg_temp_free_i64(bl);
+ tcg_temp_free_i64(bh);
+}
+
+static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s, v2), enr, es);
+ tcg_gen_add_i64(o->addr1, o->addr1, tmp);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
+
+ tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ write_vec_element_i64(tmp, get_field(s, v1), enr, es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static uint64_t generate_byte_mask(uint8_t mask)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if ((mask >> i) & 1) {
+ r |= 0xffull << (i * 8);
+ }
+ }
+ return r;
+}
+
+static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
+{
+ const uint16_t i2 = get_field(s, i2);
+
+ if (i2 == (i2 & 0xff) * 0x0101) {
+ /*
+ * Masks for both 64 bit elements of the vector are the same.
+ * Trust tcg to produce a good constant loading.
+ */
+ gen_gvec_dup_imm(ES_64, get_field(s, v1),
+ generate_byte_mask(i2 & 0xff));
+ } else {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8));
+ write_vec_element_i64(t, get_field(s, v1), 0, ES_64);
+ tcg_gen_movi_i64(t, generate_byte_mask(i2));
+ write_vec_element_i64(t, get_field(s, v1), 1, ES_64);
+ tcg_temp_free_i64(t);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t bits = NUM_VEC_ELEMENT_BITS(es);
+ const uint8_t i2 = get_field(s, i2) & (bits - 1);
+ const uint8_t i3 = get_field(s, i3) & (bits - 1);
+ uint64_t mask = 0;
+ int i;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* generate the mask - take care of wrapping */
+ for (i = i2; ; i = (i + 1) % bits) {
+ mask |= 1ull << (bits - i - 1);
+ if (i == i3) {
+ break;
+ }
+ }
+
+ gen_gvec_dup_imm(es, get_field(s, v1), mask);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
+ write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlr(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_mov(get_field(s, v1), get_field(s, v2));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+ TCGv_i64 tmp;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ gen_gvec_dup_i64(es, get_field(s, v1), tmp);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ write_vec_element_i64(tmp, get_field(s, v1), enr, es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_const_i64((int16_t)get_field(s, i2));
+ write_vec_element_i64(tmp, get_field(s, v1), enr, es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ TCGv_ptr ptr;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* fast path if we don't need the register content */
+ if (!get_field(s, b2)) {
+ uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1);
+
+ read_vec_element_i64(o->out, get_field(s, v3), enr, es);
+ return DISAS_NEXT;
+ }
+
+ ptr = tcg_temp_new_ptr();
+ get_vec_element_ptr_i64(ptr, get_field(s, v3), o->addr1, es);
+ switch (es) {
+ case ES_8:
+ tcg_gen_ld8u_i64(o->out, ptr, 0);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i64(o->out, ptr, 0);
+ break;
+ case ES_32:
+ tcg_gen_ld32u_i64(o->out, ptr, 0);
+ break;
+ case ES_64:
+ tcg_gen_ld_i64(o->out, ptr, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_ptr(ptr);
+
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
+{
+ uint8_t es = get_field(s, m3);
+ uint8_t enr;
+ TCGv_i64 t;
+
+ switch (es) {
+ /* rightmost sub-element of leftmost doubleword */
+ case ES_8:
+ enr = 7;
+ break;
+ case ES_16:
+ enr = 3;
+ break;
+ case ES_32:
+ enr = 1;
+ break;
+ case ES_64:
+ enr = 0;
+ break;
+ /* leftmost sub-element of leftmost doubleword */
+ case 6:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ es = ES_32;
+ enr = 0;
+ break;
+ }
+ /* fallthrough */
+ default:
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ t = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
+ gen_gvec_dup_imm(es, get_field(s, v1), 0);
+ write_vec_element_i64(t, get_field(s, v1), enr, es);
+ tcg_temp_free_i64(t);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v3 = get_field(s, v3);
+ uint8_t v1 = get_field(s, v1);
+ TCGv_i64 t0, t1;
+
+ if (v3 < v1 || (v3 - v1 + 1) > 16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /*
+ * Check for possible access exceptions by trying to load the last
+ * element. The first element will be checked first next.
+ */
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8);
+ tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEQ);
+
+ for (;; v1++) {
+ tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
+ write_vec_element_i64(t1, v1, 0, ES_64);
+ if (v1 == v3) {
+ break;
+ }
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
+ write_vec_element_i64(t1, v1, 1, ES_64);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ }
+
+ /* Store the last element, loaded first */
+ write_vec_element_i64(t0, v1, 1, ES_64);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
+{
+ const int64_t block_size = (1ull << (get_field(s, m3) + 6));
+ const int v1_offs = vec_full_reg_offset(get_field(s, v1));
+ TCGv_ptr a0;
+ TCGv_i64 bytes;
+
+ if (get_field(s, m3) > 6) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ bytes = tcg_temp_new_i64();
+ a0 = tcg_temp_new_ptr();
+ /* calculate the number of bytes until the next block boundary */
+ tcg_gen_ori_i64(bytes, o->addr1, -block_size);
+ tcg_gen_neg_i64(bytes, bytes);
+
+ tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
+ gen_helper_vll(cpu_env, a0, o->addr1, bytes);
+ tcg_temp_free_i64(bytes);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ TCGv_ptr ptr;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* fast path if we don't need the register content */
+ if (!get_field(s, b2)) {
+ uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1);
+
+ write_vec_element_i64(o->in2, get_field(s, v1), enr, es);
+ return DISAS_NEXT;
+ }
+
+ ptr = tcg_temp_new_ptr();
+ get_vec_element_ptr_i64(ptr, get_field(s, v1), o->addr1, es);
+ switch (es) {
+ case ES_8:
+ tcg_gen_st8_i64(o->in2, ptr, 0);
+ break;
+ case ES_16:
+ tcg_gen_st16_i64(o->in2, ptr, 0);
+ break;
+ case ES_32:
+ tcg_gen_st32_i64(o->in2, ptr, 0);
+ break;
+ case ES_64:
+ tcg_gen_st_i64(o->in2, ptr, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_ptr(ptr);
+
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o)
+{
+ write_vec_element_i64(o->in1, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(o->in2, get_field(s, v1), 1, ES_64);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
+{
+ const int v1_offs = vec_full_reg_offset(get_field(s, v1));
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+
+ /* convert highest index into an actual length */
+ tcg_gen_addi_i64(o->in2, o->in2, 1);
+ tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
+ gen_helper_vll(cpu_env, a0, o->addr1, o->in2);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+ const uint8_t es = get_field(s, m4);
+ int dst_idx, src_idx;
+ TCGv_i64 tmp;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ if (s->fields.op2 == 0x61) {
+ /* iterate backwards to avoid overwriting data we might need later */
+ for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) {
+ src_idx = dst_idx / 2;
+ if (dst_idx % 2 == 0) {
+ read_vec_element_i64(tmp, v2, src_idx, es);
+ } else {
+ read_vec_element_i64(tmp, v3, src_idx, es);
+ }
+ write_vec_element_i64(tmp, v1, dst_idx, es);
+ }
+ } else {
+ /* iterate forward to avoid overwriting data we might need later */
+ for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) {
+ src_idx = (dst_idx + NUM_VEC_ELEMENTS(es)) / 2;
+ if (dst_idx % 2 == 0) {
+ read_vec_element_i64(tmp, v2, src_idx, es);
+ } else {
+ read_vec_element_i64(tmp, v3, src_idx, es);
+ }
+ write_vec_element_i64(tmp, v1, dst_idx, es);
+ }
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+ const uint8_t es = get_field(s, m4);
+ static gen_helper_gvec_3 * const vpk[3] = {
+ gen_helper_gvec_vpk16,
+ gen_helper_gvec_vpk32,
+ gen_helper_gvec_vpk64,
+ };
+ static gen_helper_gvec_3 * const vpks[3] = {
+ gen_helper_gvec_vpks16,
+ gen_helper_gvec_vpks32,
+ gen_helper_gvec_vpks64,
+ };
+ static gen_helper_gvec_3_ptr * const vpks_cc[3] = {
+ gen_helper_gvec_vpks_cc16,
+ gen_helper_gvec_vpks_cc32,
+ gen_helper_gvec_vpks_cc64,
+ };
+ static gen_helper_gvec_3 * const vpkls[3] = {
+ gen_helper_gvec_vpkls16,
+ gen_helper_gvec_vpkls32,
+ gen_helper_gvec_vpkls64,
+ };
+ static gen_helper_gvec_3_ptr * const vpkls_cc[3] = {
+ gen_helper_gvec_vpkls_cc16,
+ gen_helper_gvec_vpkls_cc32,
+ gen_helper_gvec_vpkls_cc64,
+ };
+
+ if (es == ES_8 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0x97:
+ if (get_field(s, m5) & 0x1) {
+ gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]);
+ }
+ break;
+ case 0x95:
+ if (get_field(s, m5) & 0x1) {
+ gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]);
+ }
+ break;
+ case 0x94:
+ /* If sources and destination dont't overlap -> fast path */
+ if (v1 != v2 && v1 != v3) {
+ const uint8_t src_es = get_field(s, m4);
+ const uint8_t dst_es = src_es - 1;
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ int dst_idx, src_idx;
+
+ for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) {
+ src_idx = dst_idx;
+ if (src_idx < NUM_VEC_ELEMENTS(src_es)) {
+ read_vec_element_i64(tmp, v2, src_idx, src_es);
+ } else {
+ src_idx -= NUM_VEC_ELEMENTS(src_es);
+ read_vec_element_i64(tmp, v3, src_idx, src_es);
+ }
+ write_vec_element_i64(tmp, v1, dst_idx, dst_es);
+ }
+ tcg_temp_free_i64(tmp);
+ } else {
+ gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vperm(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
+ 0, gen_helper_gvec_vperm);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
+{
+ const uint8_t i2 = extract32(get_field(s, m4), 2, 1);
+ const uint8_t i3 = extract32(get_field(s, m4), 0, 1);
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ read_vec_element_i64(t0, get_field(s, v2), i2, ES_64);
+ read_vec_element_i64(t1, get_field(s, v3), i3, ES_64);
+ write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vrep(DisasContext *s, DisasOps *o)
+{
+ const uint8_t enr = get_field(s, i2);
+ const uint8_t es = get_field(s, m4);
+
+ if (es > ES_64 || !valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s, v1)),
+ vec_reg_offset(get_field(s, v3), enr, es),
+ 16, 16);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
+{
+ const int64_t data = (int16_t)get_field(s, i2);
+ const uint8_t es = get_field(s, m3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_dup_imm(es, get_field(s, v1), data);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s, v2), enr, es);
+ tcg_gen_add_i64(o->addr1, o->addr1, tmp);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
+
+ read_vec_element_i64(tmp, get_field(s, v1), enr, es);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsel(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_4(bitsel, ES_8, get_field(s, v1),
+ get_field(s, v4), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+ int idx1, idx2;
+ TCGv_i64 tmp;
+
+ switch (es) {
+ case ES_8:
+ idx1 = 7;
+ idx2 = 15;
+ break;
+ case ES_16:
+ idx1 = 3;
+ idx2 = 7;
+ break;
+ case ES_32:
+ idx1 = 1;
+ idx2 = 3;
+ break;
+ default:
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s, v2), idx1, es | MO_SIGN);
+ write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
+ read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN);
+ write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 tmp = tcg_const_i64(16);
+
+ /* Probe write access before actually modifying memory */
+ gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
+
+ read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s, v1), enr, es);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v3 = get_field(s, v3);
+ uint8_t v1 = get_field(s, v1);
+ TCGv_i64 tmp;
+
+ while (v3 < v1 || (v3 - v1 + 1) > 16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* Probe write access before actually modifying memory */
+ tmp = tcg_const_i64((v3 - v1 + 1) * 16);
+ gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
+
+ for (;; v1++) {
+ read_vec_element_i64(tmp, v1, 0, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ read_vec_element_i64(tmp, v1, 1, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ if (v1 == v3) {
+ break;
+ }
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
+{
+ const int v1_offs = vec_full_reg_offset(get_field(s, v1));
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+
+ /* convert highest index into an actual length */
+ tcg_gen_addi_i64(o->in2, o->in2, 1);
+ tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
+ gen_helper_vstl(cpu_env, a0, o->addr1, o->in2);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
+{
+ const bool logical = s->fields.op2 == 0xd4 || s->fields.op2 == 0xd5;
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t src_es = get_field(s, m3);
+ const uint8_t dst_es = src_es + 1;
+ int dst_idx, src_idx;
+ TCGv_i64 tmp;
+
+ if (src_es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ if (s->fields.op2 == 0xd7 || s->fields.op2 == 0xd5) {
+ /* iterate backwards to avoid overwriting data we might need later */
+ for (dst_idx = NUM_VEC_ELEMENTS(dst_es) - 1; dst_idx >= 0; dst_idx--) {
+ src_idx = dst_idx;
+ read_vec_element_i64(tmp, v2, src_idx,
+ src_es | (logical ? 0 : MO_SIGN));
+ write_vec_element_i64(tmp, v1, dst_idx, dst_es);
+ }
+
+ } else {
+ /* iterate forward to avoid overwriting data we might need later */
+ for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) {
+ src_idx = dst_idx + NUM_VEC_ELEMENTS(src_es) / 2;
+ read_vec_element_i64(tmp, v2, src_idx,
+ src_es | (logical ? 0 : MO_SIGN));
+ write_vec_element_i64(tmp, v1, dst_idx, dst_es);
+ }
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_va(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_fn_3(add, es, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
+{
+ const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
+ TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ /* Calculate the carry into the MSB, ignoring the old MSBs */
+ tcg_gen_andc_i64(t1, a, msb_mask);
+ tcg_gen_andc_i64(t2, b, msb_mask);
+ tcg_gen_add_i64(t1, t1, t2);
+ /* Calculate the MSB without any carry into it */
+ tcg_gen_xor_i64(t3, a, b);
+ /* Calculate the carry out of the MSB in the MSB bit position */
+ tcg_gen_and_i64(d, a, b);
+ tcg_gen_and_i64(t1, t1, t3);
+ tcg_gen_or_i64(d, d, t1);
+ /* Isolate and shift the carry into position */
+ tcg_gen_and_i64(d, d, msb_mask);
+ tcg_gen_shri_i64(d, d, msb_bit_nr);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_8);
+}
+
+static void gen_acc16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_16);
+}
+
+static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_add_i32(t, a, b);
+ tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b);
+ tcg_temp_free_i32(t);
+}
+
+static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_add_i64(t, a, b);
+ tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(tl, th, al, zero, bl, zero);
+ tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
+ tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_acc8_i64, },
+ { .fni8 = gen_acc16_i64, },
+ { .fni4 = gen_acc_i32, },
+ { .fni8 = gen_acc_i64, },
+ };
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(gen_acc2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_const_i64(0);
+
+ /* extract the carry only */
+ tcg_gen_extract_i64(tl, cl, 0, 1);
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ tcg_gen_add2_i64(dl, dh, dl, dh, tl, th);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+}
+
+static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_ac2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
+ return DISAS_NEXT;
+}
+
+static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_add2_i64(tl, th, tl, zero, al, zero);
+ tcg_gen_add2_i64(tl, th, tl, th, bl, zero);
+ tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
+ tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_accc2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vn(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(and, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(andc, ES_8, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(t0, a);
+ tcg_gen_ext_i32_i64(t1, b);
+ tcg_gen_add_i64(t0, t0, t1);
+ tcg_gen_addi_i64(t0, t0, 1);
+ tcg_gen_shri_i64(t0, t0, 1);
+ tcg_gen_extrl_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+
+ /* extending the sign by one bit is sufficient */
+ tcg_gen_extract_i64(ah, al, 63, 1);
+ tcg_gen_extract_i64(bh, bl, 63, 1);
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ gen_addi2_i64(dl, dh, dl, dh, 1);
+ tcg_gen_extract2_i64(dl, dl, dh, 1);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(bh);
+}
+
+static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vavg8, },
+ { .fno = gen_helper_gvec_vavg16, },
+ { .fni4 = gen_avg_i32, },
+ { .fni8 = gen_avg_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t0, a);
+ tcg_gen_extu_i32_i64(t1, b);
+ tcg_gen_add_i64(t0, t0, t1);
+ tcg_gen_addi_i64(t0, t0, 1);
+ tcg_gen_shri_i64(t0, t0, 1);
+ tcg_gen_extrl_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
+ gen_addi2_i64(dl, dh, dl, dh, 1);
+ tcg_gen_extract2_i64(dl, dl, dh, 1);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vavgl8, },
+ { .fno = gen_helper_gvec_vavgl16, },
+ { .fni4 = gen_avgl_i32, },
+ { .fni8 = gen_avgl_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ TCGv_i32 sum = tcg_temp_new_i32();
+ int i;
+
+ read_vec_element_i32(sum, get_field(s, v3), 1, ES_32);
+ for (i = 0; i < 4; i++) {
+ read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
+ tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
+ }
+ gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
+ write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
+
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(sum);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
+{
+ uint8_t es = get_field(s, m3);
+ const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ if (s->fields.op2 == 0xdb) {
+ es |= MO_SIGN;
+ }
+
+ o->in1 = tcg_temp_new_i64();
+ o->in2 = tcg_temp_new_i64();
+ read_vec_element_i64(o->in1, get_field(s, v1), enr, es);
+ read_vec_element_i64(o->in2, get_field(s, v2), enr, es);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ TCGCond cond = s->insn->data;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tcg_gen_gvec_cmp(cond, es,
+ vec_full_reg_offset(get_field(s, v1)),
+ vec_full_reg_offset(get_field(s, v2)),
+ vec_full_reg_offset(get_field(s, v3)), 16, 16);
+ if (get_field(s, m5) & 0x1) {
+ TCGv_i64 low = tcg_temp_new_i64();
+ TCGv_i64 high = tcg_temp_new_i64();
+
+ read_vec_element_i64(high, get_field(s, v1), 0, ES_64);
+ read_vec_element_i64(low, get_field(s, v1), 1, ES_64);
+ gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
+
+ tcg_temp_free_i64(low);
+ tcg_temp_free_i64(high);
+ }
+ return DISAS_NEXT;
+}
+
+static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ tcg_gen_clzi_i32(d, a, 32);
+}
+
+static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ tcg_gen_clzi_i64(d, a, 64);
+}
+
+static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vclz8, },
+ { .fno = gen_helper_gvec_vclz16, },
+ { .fni4 = gen_clz_i32, },
+ { .fni8 = gen_clz_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
+ return DISAS_NEXT;
+}
+
+static void gen_ctz_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ tcg_gen_ctzi_i32(d, a, 32);
+}
+
+static void gen_ctz_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ tcg_gen_ctzi_i64(d, a, 64);
+}
+
+static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vctz8, },
+ { .fno = gen_helper_gvec_vctz16, },
+ { .fni4 = gen_ctz_i32, },
+ { .fni8 = gen_ctz_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(xor, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vgfm8, },
+ { .fno = gen_helper_gvec_vgfm16, },
+ { .fno = gen_helper_gvec_vgfm32, },
+ { .fno = gen_helper_gvec_vgfm64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m5);
+ static const GVecGen4 g[4] = {
+ { .fno = gen_helper_gvec_vgfma8, },
+ { .fno = gen_helper_gvec_vgfma16, },
+ { .fno = gen_helper_gvec_vgfma32, },
+ { .fno = gen_helper_gvec_vgfma64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_4(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_fn_2(neg, es, get_field(s, v1), get_field(s, v2));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_fn_2(abs, es, get_field(s, v1), get_field(s, v2));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+ const uint8_t es = get_field(s, m4);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0xff:
+ gen_gvec_fn_3(smax, es, v1, v2, v3);
+ break;
+ case 0xfd:
+ gen_gvec_fn_3(umax, es, v1, v2, v3);
+ break;
+ case 0xfe:
+ gen_gvec_fn_3(smin, es, v1, v2, v3);
+ break;
+ case 0xfc:
+ gen_gvec_fn_3(umin, es, v1, v2, v3);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return DISAS_NEXT;
+}
+
+static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_mul_i32(t0, a, b);
+ tcg_gen_add_i32(d, t0, c);
+
+ tcg_temp_free_i32(t0);
+}
+
+static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(t0, a);
+ tcg_gen_ext_i32_i64(t1, b);
+ tcg_gen_ext_i32_i64(t2, c);
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_add_i64(t0, t0, t2);
+ tcg_gen_extrh_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t0, a);
+ tcg_gen_extu_i32_i64(t1, b);
+ tcg_gen_extu_i32_i64(t2, c);
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_add_i64(t0, t0, t2);
+ tcg_gen_extrh_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m5);
+ static const GVecGen4 g_vmal[3] = {
+ { .fno = gen_helper_gvec_vmal8, },
+ { .fno = gen_helper_gvec_vmal16, },
+ { .fni4 = gen_mal_i32, },
+ };
+ static const GVecGen4 g_vmah[3] = {
+ { .fno = gen_helper_gvec_vmah8, },
+ { .fno = gen_helper_gvec_vmah16, },
+ { .fni4 = gen_mah_i32, },
+ };
+ static const GVecGen4 g_vmalh[3] = {
+ { .fno = gen_helper_gvec_vmalh8, },
+ { .fno = gen_helper_gvec_vmalh16, },
+ { .fni4 = gen_malh_i32, },
+ };
+ static const GVecGen4 g_vmae[3] = {
+ { .fno = gen_helper_gvec_vmae8, },
+ { .fno = gen_helper_gvec_vmae16, },
+ { .fno = gen_helper_gvec_vmae32, },
+ };
+ static const GVecGen4 g_vmale[3] = {
+ { .fno = gen_helper_gvec_vmale8, },
+ { .fno = gen_helper_gvec_vmale16, },
+ { .fno = gen_helper_gvec_vmale32, },
+ };
+ static const GVecGen4 g_vmao[3] = {
+ { .fno = gen_helper_gvec_vmao8, },
+ { .fno = gen_helper_gvec_vmao16, },
+ { .fno = gen_helper_gvec_vmao32, },
+ };
+ static const GVecGen4 g_vmalo[3] = {
+ { .fno = gen_helper_gvec_vmalo8, },
+ { .fno = gen_helper_gvec_vmalo16, },
+ { .fno = gen_helper_gvec_vmalo32, },
+ };
+ const GVecGen4 *fn;
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0xaa:
+ fn = &g_vmal[es];
+ break;
+ case 0xab:
+ fn = &g_vmah[es];
+ break;
+ case 0xa9:
+ fn = &g_vmalh[es];
+ break;
+ case 0xae:
+ fn = &g_vmae[es];
+ break;
+ case 0xac:
+ fn = &g_vmale[es];
+ break;
+ case 0xaf:
+ fn = &g_vmao[es];
+ break;
+ case 0xad:
+ fn = &g_vmalo[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_4(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4), fn);
+ return DISAS_NEXT;
+}
+
+static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_muls2_i32(t, d, a, b);
+ tcg_temp_free_i32(t);
+}
+
+static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_mulu2_i32(t, d, a, b);
+ tcg_temp_free_i32(t);
+}
+
+static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ static const GVecGen3 g_vmh[3] = {
+ { .fno = gen_helper_gvec_vmh8, },
+ { .fno = gen_helper_gvec_vmh16, },
+ { .fni4 = gen_mh_i32, },
+ };
+ static const GVecGen3 g_vmlh[3] = {
+ { .fno = gen_helper_gvec_vmlh8, },
+ { .fno = gen_helper_gvec_vmlh16, },
+ { .fni4 = gen_mlh_i32, },
+ };
+ static const GVecGen3 g_vme[3] = {
+ { .fno = gen_helper_gvec_vme8, },
+ { .fno = gen_helper_gvec_vme16, },
+ { .fno = gen_helper_gvec_vme32, },
+ };
+ static const GVecGen3 g_vmle[3] = {
+ { .fno = gen_helper_gvec_vmle8, },
+ { .fno = gen_helper_gvec_vmle16, },
+ { .fno = gen_helper_gvec_vmle32, },
+ };
+ static const GVecGen3 g_vmo[3] = {
+ { .fno = gen_helper_gvec_vmo8, },
+ { .fno = gen_helper_gvec_vmo16, },
+ { .fno = gen_helper_gvec_vmo32, },
+ };
+ static const GVecGen3 g_vmlo[3] = {
+ { .fno = gen_helper_gvec_vmlo8, },
+ { .fno = gen_helper_gvec_vmlo16, },
+ { .fno = gen_helper_gvec_vmlo32, },
+ };
+ const GVecGen3 *fn;
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0xa2:
+ gen_gvec_fn_3(mul, es, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+ case 0xa3:
+ fn = &g_vmh[es];
+ break;
+ case 0xa1:
+ fn = &g_vmlh[es];
+ break;
+ case 0xa6:
+ fn = &g_vme[es];
+ break;
+ case 0xa4:
+ fn = &g_vmle[es];
+ break;
+ case 0xa7:
+ fn = &g_vmo[es];
+ break;
+ case 0xa5:
+ fn = &g_vmlo[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(nand, ES_8, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(nor, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(eqv, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(or, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(orc, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vpopct8, },
+ { .fno = gen_helper_gvec_vpopct16, },
+ { .fni4 = tcg_gen_ctpop_i32, },
+ { .fni8 = tcg_gen_ctpop_i64, },
+ };
+
+ if (es > ES_64 || (es != ES_8 && !s390_has_feat(S390_FEAT_VECTOR_ENH))) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
+ return DISAS_NEXT;
+}
+
+static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_rotli_i32(t, a, c & 31);
+ tcg_gen_and_i32(t, t, b);
+ tcg_gen_andc_i32(d, d, b);
+ tcg_gen_or_i32(d, d, t);
+
+ tcg_temp_free_i32(t);
+}
+
+static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_rotli_i64(t, a, c & 63);
+ tcg_gen_and_i64(t, t, b);
+ tcg_gen_andc_i64(d, d, b);
+ tcg_gen_or_i64(d, d, t);
+
+ tcg_temp_free_i64(t);
+}
+
+static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m5);
+ const uint8_t i4 = get_field(s, i4) &
+ (NUM_VEC_ELEMENT_BITS(es) - 1);
+ static const GVecGen3i g[4] = {
+ { .fno = gen_helper_gvec_verim8, },
+ { .fno = gen_helper_gvec_verim16, },
+ { .fni4 = gen_rim_i32,
+ .load_dest = true, },
+ { .fni8 = gen_rim_i64,
+ .load_dest = true, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_3i(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), i4, &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0x70:
+ gen_gvec_fn_3(shlv, es, v1, v2, v3);
+ break;
+ case 0x73:
+ gen_gvec_fn_3(rotlv, es, v1, v2, v3);
+ break;
+ case 0x7a:
+ gen_gvec_fn_3(sarv, es, v1, v2, v3);
+ break;
+ case 0x78:
+ gen_gvec_fn_3(shrv, es, v1, v2, v3);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t d2 = get_field(s, d2) &
+ (NUM_VEC_ELEMENT_BITS(es) - 1);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v3 = get_field(s, v3);
+ TCGv_i32 shift;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (likely(!get_field(s, b2))) {
+ switch (s->fields.op2) {
+ case 0x30:
+ gen_gvec_fn_2i(shli, es, v1, v3, d2);
+ break;
+ case 0x33:
+ gen_gvec_fn_2i(rotli, es, v1, v3, d2);
+ break;
+ case 0x3a:
+ gen_gvec_fn_2i(sari, es, v1, v3, d2);
+ break;
+ case 0x38:
+ gen_gvec_fn_2i(shri, es, v1, v3, d2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ shift = tcg_temp_new_i32();
+ tcg_gen_extrl_i64_i32(shift, o->addr1);
+ tcg_gen_andi_i32(shift, shift, NUM_VEC_ELEMENT_BITS(es) - 1);
+ switch (s->fields.op2) {
+ case 0x30:
+ gen_gvec_fn_2s(shls, es, v1, v3, shift);
+ break;
+ case 0x33:
+ gen_gvec_fn_2s(rotls, es, v1, v3, shift);
+ break;
+ case 0x3a:
+ gen_gvec_fn_2s(sars, es, v1, v3, shift);
+ break;
+ case 0x38:
+ gen_gvec_fn_2s(shrs, es, v1, v3, shift);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_i32(shift);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
+ if (s->fields.op2 == 0x74) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
+ shift, 0, gen_helper_gvec_vsl);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
+{
+ const uint8_t i4 = get_field(s, i4) & 0xf;
+ const int left_shift = (i4 & 7) * 8;
+ const int right_shift = 64 - left_shift;
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ if ((i4 & 8) == 0) {
+ read_vec_element_i64(t0, get_field(s, v2), 0, ES_64);
+ read_vec_element_i64(t1, get_field(s, v2), 1, ES_64);
+ read_vec_element_i64(t2, get_field(s, v3), 0, ES_64);
+ } else {
+ read_vec_element_i64(t0, get_field(s, v2), 1, ES_64);
+ read_vec_element_i64(t1, get_field(s, v3), 0, ES_64);
+ read_vec_element_i64(t2, get_field(s, v3), 1, ES_64);
+ }
+ tcg_gen_extract2_i64(t0, t1, t0, right_shift);
+ tcg_gen_extract2_i64(t1, t2, t1, right_shift);
+ write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsra(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
+ if (s->fields.op2 == 0x7e) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
+ shift, 0, gen_helper_gvec_vsra);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
+ if (s->fields.op2 == 0x7c) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
+ shift, 0, gen_helper_gvec_vsrl);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_fn_3(sub, es, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
+ return DISAS_NEXT;
+}
+
+static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_setcond_i32(TCG_COND_GEU, d, a, b);
+}
+
+static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_setcond_i64(TCG_COND_GEU, d, a, b);
+}
+
+static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_sub2_i64(tl, th, al, zero, bl, zero);
+ tcg_gen_andi_i64(th, th, 1);
+ tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
+ /* "invert" the result: -1 -> 0; 0 -> 1 */
+ tcg_gen_addi_i64(dl, th, 1);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vscbi8, },
+ { .fno = gen_helper_gvec_vscbi16, },
+ { .fni4 = gen_scbi_i32, },
+ { .fni8 = gen_scbi_i64, },
+ };
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(gen_scbi2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_temp_new_i64();
+
+ tcg_gen_not_i64(tl, bl);
+ tcg_gen_not_i64(th, bh);
+ gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+}
+
+static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_sbi2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
+ return DISAS_NEXT;
+}
+
+static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+
+ tcg_gen_not_i64(tl, bl);
+ tcg_gen_not_i64(th, bh);
+ gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+}
+
+static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ TCGv_i64 sum, tmp;
+ uint8_t dst_idx;
+
+ if (es == ES_8 || es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sum = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+ for (dst_idx = 0; dst_idx < 2; dst_idx++) {
+ uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2;
+ const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1;
+
+ read_vec_element_i64(sum, get_field(s, v3), max_idx, es);
+ for (; idx <= max_idx; idx++) {
+ read_vec_element_i64(tmp, get_field(s, v2), idx, es);
+ tcg_gen_add_i64(sum, sum, tmp);
+ }
+ write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64);
+ }
+ tcg_temp_free_i64(sum);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1;
+ TCGv_i64 sumh, suml, zero, tmpl;
+ uint8_t idx;
+
+ if (es < ES_32 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sumh = tcg_const_i64(0);
+ suml = tcg_temp_new_i64();
+ zero = tcg_const_i64(0);
+ tmpl = tcg_temp_new_i64();
+
+ read_vec_element_i64(suml, get_field(s, v3), max_idx, es);
+ for (idx = 0; idx <= max_idx; idx++) {
+ read_vec_element_i64(tmpl, get_field(s, v2), idx, es);
+ tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero);
+ }
+ write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(suml, get_field(s, v1), 1, ES_64);
+
+ tcg_temp_free_i64(sumh);
+ tcg_temp_free_i64(suml);
+ tcg_temp_free_i64(zero);
+ tcg_temp_free_i64(tmpl);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ TCGv_i32 sum, tmp;
+ uint8_t dst_idx;
+
+ if (es > ES_16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sum = tcg_temp_new_i32();
+ tmp = tcg_temp_new_i32();
+ for (dst_idx = 0; dst_idx < 4; dst_idx++) {
+ uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4;
+ const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1;
+
+ read_vec_element_i32(sum, get_field(s, v3), max_idx, es);
+ for (; idx <= max_idx; idx++) {
+ read_vec_element_i32(tmp, get_field(s, v2), idx, es);
+ tcg_gen_add_i32(sum, sum, tmp);
+ }
+ write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32);
+ }
+ tcg_temp_free_i32(sum);
+ tcg_temp_free_i32(tmp);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
+ cpu_env, 0, gen_helper_gvec_vtm);
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfae(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ static gen_helper_gvec_3 * const g[3] = {
+ gen_helper_gvec_vfae8,
+ gen_helper_gvec_vfae16,
+ gen_helper_gvec_vfae32,
+ };
+ static gen_helper_gvec_3_ptr * const g_cc[3] = {
+ gen_helper_gvec_vfae_cc8,
+ gen_helper_gvec_vfae_cc16,
+ gen_helper_gvec_vfae_cc32,
+ };
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m5, 0, 1)) {
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, m5, g_cc[es]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), m5, g[es]);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfee(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ static gen_helper_gvec_3 * const g[3] = {
+ gen_helper_gvec_vfee8,
+ gen_helper_gvec_vfee16,
+ gen_helper_gvec_vfee32,
+ };
+ static gen_helper_gvec_3_ptr * const g_cc[3] = {
+ gen_helper_gvec_vfee_cc8,
+ gen_helper_gvec_vfee_cc16,
+ gen_helper_gvec_vfee_cc32,
+ };
+
+ if (es > ES_32 || m5 & ~0x3) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m5, 0, 1)) {
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, m5, g_cc[es]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), m5, g[es]);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfene(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ static gen_helper_gvec_3 * const g[3] = {
+ gen_helper_gvec_vfene8,
+ gen_helper_gvec_vfene16,
+ gen_helper_gvec_vfene32,
+ };
+ static gen_helper_gvec_3_ptr * const g_cc[3] = {
+ gen_helper_gvec_vfene_cc8,
+ gen_helper_gvec_vfene_cc16,
+ gen_helper_gvec_vfene_cc32,
+ };
+
+ if (es > ES_32 || m5 & ~0x3) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m5, 0, 1)) {
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, m5, g_cc[es]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), m5, g[es]);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vistr(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ static gen_helper_gvec_2 * const g[3] = {
+ gen_helper_gvec_vistr8,
+ gen_helper_gvec_vistr16,
+ gen_helper_gvec_vistr32,
+ };
+ static gen_helper_gvec_2_ptr * const g_cc[3] = {
+ gen_helper_gvec_vistr_cc8,
+ gen_helper_gvec_vistr_cc16,
+ gen_helper_gvec_vistr_cc32,
+ };
+
+ if (es > ES_32 || m5 & ~0x1) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m5, 0, 1)) {
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
+ cpu_env, 0, g_cc[es]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0,
+ g[es]);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s, m5);
+ const uint8_t m6 = get_field(s, m6);
+ static gen_helper_gvec_4 * const g[3] = {
+ gen_helper_gvec_vstrc8,
+ gen_helper_gvec_vstrc16,
+ gen_helper_gvec_vstrc32,
+ };
+ static gen_helper_gvec_4 * const g_rt[3] = {
+ gen_helper_gvec_vstrc_rt8,
+ gen_helper_gvec_vstrc_rt16,
+ gen_helper_gvec_vstrc_rt32,
+ };
+ static gen_helper_gvec_4_ptr * const g_cc[3] = {
+ gen_helper_gvec_vstrc_cc8,
+ gen_helper_gvec_vstrc_cc16,
+ gen_helper_gvec_vstrc_cc32,
+ };
+ static gen_helper_gvec_4_ptr * const g_cc_rt[3] = {
+ gen_helper_gvec_vstrc_cc_rt8,
+ gen_helper_gvec_vstrc_cc_rt16,
+ gen_helper_gvec_vstrc_cc_rt32,
+ };
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m6, 0, 1)) {
+ if (extract32(m6, 2, 1)) {
+ gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
+ cpu_env, m6, g_cc_rt[es]);
+ } else {
+ gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
+ cpu_env, m6, g_cc[es]);
+ }
+ set_cc_static(s);
+ } else {
+ if (extract32(m6, 2, 1)) {
+ gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
+ m6, g_rt[es]);
+ } else {
+ gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
+ m6, g[es]);
+ }
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ const bool se = extract32(m5, 3, 1);
+ gen_helper_gvec_3_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0xe3:
+ fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64;
+ break;
+ case 0xe5:
+ fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64;
+ break;
+ case 0xe7:
+ fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
+ break;
+ case 0xe2:
+ fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, 0, fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+
+ if (fpf != FPF_LONG || m4) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (s->fields.op2 == 0xcb) {
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
+ cpu_env, 0, gen_helper_gvec_wfc64);
+ } else {
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
+ cpu_env, 0, gen_helper_gvec_wfk64);
+ }
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ const uint8_t m6 = get_field(s, m6);
+ const bool se = extract32(m5, 3, 1);
+ const bool cs = extract32(m6, 0, 1);
+ gen_helper_gvec_3_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (cs) {
+ switch (s->fields.op2) {
+ case 0xe8:
+ fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc;
+ break;
+ case 0xeb:
+ fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc;
+ break;
+ case 0xea:
+ fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ switch (s->fields.op2) {
+ case 0xe8:
+ fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64;
+ break;
+ case 0xeb:
+ fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64;
+ break;
+ case 0xea:
+ fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, 0, fn);
+ if (cs) {
+ set_cc_static(s);
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+ const uint8_t erm = get_field(s, m5);
+ const bool se = extract32(m4, 3, 1);
+ gen_helper_gvec_2_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields.op2) {
+ case 0xc3:
+ fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64;
+ break;
+ case 0xc1:
+ fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64;
+ break;
+ case 0xc2:
+ fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64;
+ break;
+ case 0xc0:
+ fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64;
+ break;
+ case 0xc7:
+ fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64;
+ break;
+ case 0xc5:
+ fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
+ deposit32(m4, 4, 4, erm), fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfll(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+ gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32;
+
+ if (fpf != FPF_SHORT || extract32(m4, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m4, 3, 1)) {
+ fn = gen_helper_gvec_vfll32s;
+ }
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
+ 0, fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t m5 = get_field(s, m5);
+ const uint8_t fpf = get_field(s, m6);
+ const bool se = extract32(m5, 3, 1);
+ gen_helper_gvec_4_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (s->fields.op2 == 0x8f) {
+ fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64;
+ } else {
+ fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64;
+ }
+ gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4), cpu_env,
+ 0, fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ TCGv_i64 tmp;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m4, 3, 1)) {
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, v2, 0, ES_64);
+ switch (m5) {
+ case 0:
+ /* sign bit is inverted (complement) */
+ tcg_gen_xori_i64(tmp, tmp, 1ull << 63);
+ break;
+ case 1:
+ /* sign bit is set to one (negative) */
+ tcg_gen_ori_i64(tmp, tmp, 1ull << 63);
+ break;
+ case 2:
+ /* sign bit is set to zero (positive) */
+ tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1);
+ break;
+ }
+ write_vec_element_i64(tmp, v1, 0, ES_64);
+ tcg_temp_free_i64(tmp);
+ } else {
+ switch (m5) {
+ case 0:
+ /* sign bit is inverted (complement) */
+ gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63);
+ break;
+ case 1:
+ /* sign bit is set to one (negative) */
+ gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63);
+ break;
+ case 2:
+ /* sign bit is set to zero (positive) */
+ gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1);
+ break;
+ }
+ }
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+ gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m4, 3, 1)) {
+ fn = gen_helper_gvec_vfsq64s;
+ }
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
+ 0, fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vftci(DisasContext *s, DisasOps *o)
+{
+ const uint16_t i3 = get_field(s, i3);
+ const uint8_t fpf = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m5, 3, 1)) {
+ fn = gen_helper_gvec_vftci64s;
+ }
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn);
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
+++ /dev/null
-/*
- * QEMU TCG support -- s390x vector instruction translation functions
- *
- * Copyright (C) 2019 Red Hat Inc
- *
- * Authors:
- * David Hildenbrand <david@redhat.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-/*
- * For most instructions that use the same element size for reads and
- * writes, we can use real gvec vector expansion, which potantially uses
- * real host vector instructions. As they only work up to 64 bit elements,
- * 128 bit elements (vector is a single element) have to be handled
- * differently. Operations that are too complicated to encode via TCG ops
- * are handled via gvec ool (out-of-line) handlers.
- *
- * As soon as instructions use different element sizes for reads and writes
- * or access elements "out of their element scope" we expand them manually
- * in fancy loops, as gvec expansion does not deal with actual element
- * numbers and does also not support access to other elements.
- *
- * 128 bit elements:
- * As we only have i32/i64, such elements have to be loaded into two
- * i64 values and can then be processed e.g. by tcg_gen_add2_i64.
- *
- * Sizes:
- * On s390x, the operand size (oprsz) and the maximum size (maxsz) are
- * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",
- * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only
- * 128 bit element size has to be treated in a special way (MO_64 + 1).
- * We will use ES_* instead of MO_* for this reason in this file.
- *
- * CC handling:
- * As gvec ool-helpers can currently not return values (besides via
- * pointers like vectors or cpu_env), whenever we have to set the CC and
- * can't conclude the value from the result vector, we will directly
- * set it in "env->cc_op" and mark it as static via set_cc_static()".
- * Whenever this is done, the helper writes globals (cc_op).
- */
-
-#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es))
-#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))
-#define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)
-
-#define ES_8 MO_8
-#define ES_16 MO_16
-#define ES_32 MO_32
-#define ES_64 MO_64
-#define ES_128 4
-
-/* Floating-Point Format */
-#define FPF_SHORT 2
-#define FPF_LONG 3
-#define FPF_EXT 4
-
-static inline bool valid_vec_element(uint8_t enr, MemOp es)
-{
- return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));
-}
-
-static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
- MemOp memop)
-{
- const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
-
- switch (memop) {
- case ES_8:
- tcg_gen_ld8u_i64(dst, cpu_env, offs);
- break;
- case ES_16:
- tcg_gen_ld16u_i64(dst, cpu_env, offs);
- break;
- case ES_32:
- tcg_gen_ld32u_i64(dst, cpu_env, offs);
- break;
- case ES_8 | MO_SIGN:
- tcg_gen_ld8s_i64(dst, cpu_env, offs);
- break;
- case ES_16 | MO_SIGN:
- tcg_gen_ld16s_i64(dst, cpu_env, offs);
- break;
- case ES_32 | MO_SIGN:
- tcg_gen_ld32s_i64(dst, cpu_env, offs);
- break;
- case ES_64:
- case ES_64 | MO_SIGN:
- tcg_gen_ld_i64(dst, cpu_env, offs);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
- MemOp memop)
-{
- const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
-
- switch (memop) {
- case ES_8:
- tcg_gen_ld8u_i32(dst, cpu_env, offs);
- break;
- case ES_16:
- tcg_gen_ld16u_i32(dst, cpu_env, offs);
- break;
- case ES_8 | MO_SIGN:
- tcg_gen_ld8s_i32(dst, cpu_env, offs);
- break;
- case ES_16 | MO_SIGN:
- tcg_gen_ld16s_i32(dst, cpu_env, offs);
- break;
- case ES_32:
- case ES_32 | MO_SIGN:
- tcg_gen_ld_i32(dst, cpu_env, offs);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
- MemOp memop)
-{
- const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
-
- switch (memop) {
- case ES_8:
- tcg_gen_st8_i64(src, cpu_env, offs);
- break;
- case ES_16:
- tcg_gen_st16_i64(src, cpu_env, offs);
- break;
- case ES_32:
- tcg_gen_st32_i64(src, cpu_env, offs);
- break;
- case ES_64:
- tcg_gen_st_i64(src, cpu_env, offs);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
- MemOp memop)
-{
- const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
-
- switch (memop) {
- case ES_8:
- tcg_gen_st8_i32(src, cpu_env, offs);
- break;
- case ES_16:
- tcg_gen_st16_i32(src, cpu_env, offs);
- break;
- case ES_32:
- tcg_gen_st_i32(src, cpu_env, offs);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
- uint8_t es)
-{
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- /* mask off invalid parts from the element nr */
- tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1);
-
- /* convert it to an element offset relative to cpu_env (vec_reg_offset() */
- tcg_gen_shli_i64(tmp, tmp, es);
-#ifndef HOST_WORDS_BIGENDIAN
- tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
-#endif
- tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
-
- /* generate the final ptr by adding cpu_env */
- tcg_gen_trunc_i64_ptr(ptr, tmp);
- tcg_gen_add_ptr(ptr, ptr, cpu_env);
-
- tcg_temp_free_i64(tmp);
-}
-
-#define gen_gvec_2(v1, v2, gen) \
- tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- 16, 16, gen)
-#define gen_gvec_2s(v1, v2, c, gen) \
- tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- 16, 16, c, gen)
-#define gen_gvec_2_ool(v1, v2, data, fn) \
- tcg_gen_gvec_2_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- 16, 16, data, fn)
-#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
- tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- c, 16, 16, data, fn)
-#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
- tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- ptr, 16, 16, data, fn)
-#define gen_gvec_3(v1, v2, v3, gen) \
- tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), 16, 16, gen)
-#define gen_gvec_3_ool(v1, v2, v3, data, fn) \
- tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), 16, 16, data, fn)
-#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
-#define gen_gvec_3i(v1, v2, v3, c, gen) \
- tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), 16, 16, c, gen)
-#define gen_gvec_4(v1, v2, v3, v4, gen) \
- tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
- 16, 16, gen)
-#define gen_gvec_4_ool(v1, v2, v3, v4, data, fn) \
- tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
- 16, 16, data, fn)
-#define gen_gvec_4_ptr(v1, v2, v3, v4, ptr, data, fn) \
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
- ptr, 16, 16, data, fn)
-#define gen_gvec_dup_i64(es, v1, c) \
- tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
-#define gen_gvec_mov(v1, v2) \
- tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
- 16)
-#define gen_gvec_dup_imm(es, v1, c) \
- tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
-#define gen_gvec_fn_2(fn, es, v1, v2) \
- tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- 16, 16)
-#define gen_gvec_fn_2i(fn, es, v1, v2, c) \
- tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- c, 16, 16)
-#define gen_gvec_fn_2s(fn, es, v1, v2, s) \
- tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- s, 16, 16)
-#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
- tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), 16, 16)
-#define gen_gvec_fn_4(fn, es, v1, v2, v3, v4) \
- tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
- vec_full_reg_offset(v3), vec_full_reg_offset(v4), 16, 16)
-
-/*
- * Helper to carry out a 128 bit vector computation using 2 i64 values per
- * vector.
- */
-typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
- TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
-static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
- uint8_t b)
-{
- TCGv_i64 dh = tcg_temp_new_i64();
- TCGv_i64 dl = tcg_temp_new_i64();
- TCGv_i64 ah = tcg_temp_new_i64();
- TCGv_i64 al = tcg_temp_new_i64();
- TCGv_i64 bh = tcg_temp_new_i64();
- TCGv_i64 bl = tcg_temp_new_i64();
-
- read_vec_element_i64(ah, a, 0, ES_64);
- read_vec_element_i64(al, a, 1, ES_64);
- read_vec_element_i64(bh, b, 0, ES_64);
- read_vec_element_i64(bl, b, 1, ES_64);
- fn(dl, dh, al, ah, bl, bh);
- write_vec_element_i64(dh, d, 0, ES_64);
- write_vec_element_i64(dl, d, 1, ES_64);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(dl);
- tcg_temp_free_i64(ah);
- tcg_temp_free_i64(al);
- tcg_temp_free_i64(bh);
- tcg_temp_free_i64(bl);
-}
-
-typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
- TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh,
- TCGv_i64 cl, TCGv_i64 ch);
-static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
- uint8_t b, uint8_t c)
-{
- TCGv_i64 dh = tcg_temp_new_i64();
- TCGv_i64 dl = tcg_temp_new_i64();
- TCGv_i64 ah = tcg_temp_new_i64();
- TCGv_i64 al = tcg_temp_new_i64();
- TCGv_i64 bh = tcg_temp_new_i64();
- TCGv_i64 bl = tcg_temp_new_i64();
- TCGv_i64 ch = tcg_temp_new_i64();
- TCGv_i64 cl = tcg_temp_new_i64();
-
- read_vec_element_i64(ah, a, 0, ES_64);
- read_vec_element_i64(al, a, 1, ES_64);
- read_vec_element_i64(bh, b, 0, ES_64);
- read_vec_element_i64(bl, b, 1, ES_64);
- read_vec_element_i64(ch, c, 0, ES_64);
- read_vec_element_i64(cl, c, 1, ES_64);
- fn(dl, dh, al, ah, bl, bh, cl, ch);
- write_vec_element_i64(dh, d, 0, ES_64);
- write_vec_element_i64(dl, d, 1, ES_64);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(dl);
- tcg_temp_free_i64(ah);
- tcg_temp_free_i64(al);
- tcg_temp_free_i64(bh);
- tcg_temp_free_i64(bl);
- tcg_temp_free_i64(ch);
- tcg_temp_free_i64(cl);
-}
-
-static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
- uint64_t b)
-{
- TCGv_i64 bl = tcg_const_i64(b);
- TCGv_i64 bh = tcg_const_i64(0);
-
- tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
- tcg_temp_free_i64(bl);
- tcg_temp_free_i64(bh);
-}
-
-static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s, m3);
- TCGv_i64 tmp;
-
- if (!valid_vec_element(enr, es)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s, v2), enr, es);
- tcg_gen_add_i64(o->addr1, o->addr1, tmp);
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
-
- tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static uint64_t generate_byte_mask(uint8_t mask)
-{
- uint64_t r = 0;
- int i;
-
- for (i = 0; i < 8; i++) {
- if ((mask >> i) & 1) {
- r |= 0xffull << (i * 8);
- }
- }
- return r;
-}
-
-static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
-{
- const uint16_t i2 = get_field(s, i2);
-
- if (i2 == (i2 & 0xff) * 0x0101) {
- /*
- * Masks for both 64 bit elements of the vector are the same.
- * Trust tcg to produce a good constant loading.
- */
- gen_gvec_dup_imm(ES_64, get_field(s, v1),
- generate_byte_mask(i2 & 0xff));
- } else {
- TCGv_i64 t = tcg_temp_new_i64();
-
- tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8));
- write_vec_element_i64(t, get_field(s, v1), 0, ES_64);
- tcg_gen_movi_i64(t, generate_byte_mask(i2));
- write_vec_element_i64(t, get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(t);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t bits = NUM_VEC_ELEMENT_BITS(es);
- const uint8_t i2 = get_field(s, i2) & (bits - 1);
- const uint8_t i3 = get_field(s, i3) & (bits - 1);
- uint64_t mask = 0;
- int i;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- /* generate the mask - take care of wrapping */
- for (i = i2; ; i = (i + 1) % bits) {
- mask |= 1ull << (bits - i - 1);
- if (i == i3) {
- break;
- }
- }
-
- gen_gvec_dup_imm(es, get_field(s, v1), mask);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ);
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
- write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
- write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlr(DisasContext *s, DisasOps *o)
-{
- gen_gvec_mov(get_field(s, v1), get_field(s, v2));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
- TCGv_i64 tmp;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- gen_gvec_dup_i64(es, get_field(s, v1), tmp);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s, m3);
- TCGv_i64 tmp;
-
- if (!valid_vec_element(enr, es)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s, m3);
- TCGv_i64 tmp;
-
- if (!valid_vec_element(enr, es)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_const_i64((int16_t)get_field(s, i2));
- write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- TCGv_ptr ptr;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- /* fast path if we don't need the register content */
- if (!get_field(s, b2)) {
- uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1);
-
- read_vec_element_i64(o->out, get_field(s, v3), enr, es);
- return DISAS_NEXT;
- }
-
- ptr = tcg_temp_new_ptr();
- get_vec_element_ptr_i64(ptr, get_field(s, v3), o->addr1, es);
- switch (es) {
- case ES_8:
- tcg_gen_ld8u_i64(o->out, ptr, 0);
- break;
- case ES_16:
- tcg_gen_ld16u_i64(o->out, ptr, 0);
- break;
- case ES_32:
- tcg_gen_ld32u_i64(o->out, ptr, 0);
- break;
- case ES_64:
- tcg_gen_ld_i64(o->out, ptr, 0);
- break;
- default:
- g_assert_not_reached();
- }
- tcg_temp_free_ptr(ptr);
-
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
-{
- uint8_t es = get_field(s, m3);
- uint8_t enr;
- TCGv_i64 t;
-
- switch (es) {
- /* rightmost sub-element of leftmost doubleword */
- case ES_8:
- enr = 7;
- break;
- case ES_16:
- enr = 3;
- break;
- case ES_32:
- enr = 1;
- break;
- case ES_64:
- enr = 0;
- break;
- /* leftmost sub-element of leftmost doubleword */
- case 6:
- if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
- es = ES_32;
- enr = 0;
- break;
- }
- /* fallthrough */
- default:
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- t = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
- gen_gvec_dup_imm(es, get_field(s, v1), 0);
- write_vec_element_i64(t, get_field(s, v1), enr, es);
- tcg_temp_free_i64(t);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
-{
- const uint8_t v3 = get_field(s, v3);
- uint8_t v1 = get_field(s, v1);
- TCGv_i64 t0, t1;
-
- if (v3 < v1 || (v3 - v1 + 1) > 16) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- /*
- * Check for possible access exceptions by trying to load the last
- * element. The first element will be checked first next.
- */
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8);
- tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEQ);
-
- for (;; v1++) {
- tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
- write_vec_element_i64(t1, v1, 0, ES_64);
- if (v1 == v3) {
- break;
- }
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
- write_vec_element_i64(t1, v1, 1, ES_64);
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- }
-
- /* Store the last element, loaded first */
- write_vec_element_i64(t0, v1, 1, ES_64);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
-{
- const int64_t block_size = (1ull << (get_field(s, m3) + 6));
- const int v1_offs = vec_full_reg_offset(get_field(s, v1));
- TCGv_ptr a0;
- TCGv_i64 bytes;
-
- if (get_field(s, m3) > 6) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- bytes = tcg_temp_new_i64();
- a0 = tcg_temp_new_ptr();
- /* calculate the number of bytes until the next block boundary */
- tcg_gen_ori_i64(bytes, o->addr1, -block_size);
- tcg_gen_neg_i64(bytes, bytes);
-
- tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
- gen_helper_vll(cpu_env, a0, o->addr1, bytes);
- tcg_temp_free_i64(bytes);
- tcg_temp_free_ptr(a0);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- TCGv_ptr ptr;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- /* fast path if we don't need the register content */
- if (!get_field(s, b2)) {
- uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1);
-
- write_vec_element_i64(o->in2, get_field(s, v1), enr, es);
- return DISAS_NEXT;
- }
-
- ptr = tcg_temp_new_ptr();
- get_vec_element_ptr_i64(ptr, get_field(s, v1), o->addr1, es);
- switch (es) {
- case ES_8:
- tcg_gen_st8_i64(o->in2, ptr, 0);
- break;
- case ES_16:
- tcg_gen_st16_i64(o->in2, ptr, 0);
- break;
- case ES_32:
- tcg_gen_st32_i64(o->in2, ptr, 0);
- break;
- case ES_64:
- tcg_gen_st_i64(o->in2, ptr, 0);
- break;
- default:
- g_assert_not_reached();
- }
- tcg_temp_free_ptr(ptr);
-
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o)
-{
- write_vec_element_i64(o->in1, get_field(s, v1), 0, ES_64);
- write_vec_element_i64(o->in2, get_field(s, v1), 1, ES_64);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
-{
- const int v1_offs = vec_full_reg_offset(get_field(s, v1));
- TCGv_ptr a0 = tcg_temp_new_ptr();
-
- /* convert highest index into an actual length */
- tcg_gen_addi_i64(o->in2, o->in2, 1);
- tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
- gen_helper_vll(cpu_env, a0, o->addr1, o->in2);
- tcg_temp_free_ptr(a0);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
-{
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v2 = get_field(s, v2);
- const uint8_t v3 = get_field(s, v3);
- const uint8_t es = get_field(s, m4);
- int dst_idx, src_idx;
- TCGv_i64 tmp;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- if (s->fields.op2 == 0x61) {
- /* iterate backwards to avoid overwriting data we might need later */
- for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) {
- src_idx = dst_idx / 2;
- if (dst_idx % 2 == 0) {
- read_vec_element_i64(tmp, v2, src_idx, es);
- } else {
- read_vec_element_i64(tmp, v3, src_idx, es);
- }
- write_vec_element_i64(tmp, v1, dst_idx, es);
- }
- } else {
- /* iterate forward to avoid overwriting data we might need later */
- for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) {
- src_idx = (dst_idx + NUM_VEC_ELEMENTS(es)) / 2;
- if (dst_idx % 2 == 0) {
- read_vec_element_i64(tmp, v2, src_idx, es);
- } else {
- read_vec_element_i64(tmp, v3, src_idx, es);
- }
- write_vec_element_i64(tmp, v1, dst_idx, es);
- }
- }
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
-{
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v2 = get_field(s, v2);
- const uint8_t v3 = get_field(s, v3);
- const uint8_t es = get_field(s, m4);
- static gen_helper_gvec_3 * const vpk[3] = {
- gen_helper_gvec_vpk16,
- gen_helper_gvec_vpk32,
- gen_helper_gvec_vpk64,
- };
- static gen_helper_gvec_3 * const vpks[3] = {
- gen_helper_gvec_vpks16,
- gen_helper_gvec_vpks32,
- gen_helper_gvec_vpks64,
- };
- static gen_helper_gvec_3_ptr * const vpks_cc[3] = {
- gen_helper_gvec_vpks_cc16,
- gen_helper_gvec_vpks_cc32,
- gen_helper_gvec_vpks_cc64,
- };
- static gen_helper_gvec_3 * const vpkls[3] = {
- gen_helper_gvec_vpkls16,
- gen_helper_gvec_vpkls32,
- gen_helper_gvec_vpkls64,
- };
- static gen_helper_gvec_3_ptr * const vpkls_cc[3] = {
- gen_helper_gvec_vpkls_cc16,
- gen_helper_gvec_vpkls_cc32,
- gen_helper_gvec_vpkls_cc64,
- };
-
- if (es == ES_8 || es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0x97:
- if (get_field(s, m5) & 0x1) {
- gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]);
- set_cc_static(s);
- } else {
- gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]);
- }
- break;
- case 0x95:
- if (get_field(s, m5) & 0x1) {
- gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]);
- set_cc_static(s);
- } else {
- gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]);
- }
- break;
- case 0x94:
- /* If sources and destination dont't overlap -> fast path */
- if (v1 != v2 && v1 != v3) {
- const uint8_t src_es = get_field(s, m4);
- const uint8_t dst_es = src_es - 1;
- TCGv_i64 tmp = tcg_temp_new_i64();
- int dst_idx, src_idx;
-
- for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) {
- src_idx = dst_idx;
- if (src_idx < NUM_VEC_ELEMENTS(src_es)) {
- read_vec_element_i64(tmp, v2, src_idx, src_es);
- } else {
- src_idx -= NUM_VEC_ELEMENTS(src_es);
- read_vec_element_i64(tmp, v3, src_idx, src_es);
- }
- write_vec_element_i64(tmp, v1, dst_idx, dst_es);
- }
- tcg_temp_free_i64(tmp);
- } else {
- gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]);
- }
- break;
- default:
- g_assert_not_reached();
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vperm(DisasContext *s, DisasOps *o)
-{
- gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4),
- 0, gen_helper_gvec_vperm);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
-{
- const uint8_t i2 = extract32(get_field(s, m4), 2, 1);
- const uint8_t i3 = extract32(get_field(s, m4), 0, 1);
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- read_vec_element_i64(t0, get_field(s, v2), i2, ES_64);
- read_vec_element_i64(t1, get_field(s, v3), i3, ES_64);
- write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
- write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vrep(DisasContext *s, DisasOps *o)
-{
- const uint8_t enr = get_field(s, i2);
- const uint8_t es = get_field(s, m4);
-
- if (es > ES_64 || !valid_vec_element(enr, es)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s, v1)),
- vec_reg_offset(get_field(s, v3), enr, es),
- 16, 16);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
-{
- const int64_t data = (int16_t)get_field(s, i2);
- const uint8_t es = get_field(s, m3);
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec_dup_imm(es, get_field(s, v1), data);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s, m3);
- TCGv_i64 tmp;
-
- if (!valid_vec_element(enr, es)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s, v2), enr, es);
- tcg_gen_add_i64(o->addr1, o->addr1, tmp);
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
-
- read_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsel(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_4(bitsel, ES_8, get_field(s, v1),
- get_field(s, v4), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
- int idx1, idx2;
- TCGv_i64 tmp;
-
- switch (es) {
- case ES_8:
- idx1 = 7;
- idx2 = 15;
- break;
- case ES_16:
- idx1 = 3;
- idx2 = 7;
- break;
- case ES_32:
- idx1 = 1;
- idx2 = 3;
- break;
- default:
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s, v2), idx1, es | MO_SIGN);
- write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
- read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN);
- write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
-{
- TCGv_i64 tmp = tcg_const_i64(16);
-
- /* Probe write access before actually modifying memory */
- gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
-
- read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
- tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
- tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s, m3);
- TCGv_i64 tmp;
-
- if (!valid_vec_element(enr, es)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
-{
- const uint8_t v3 = get_field(s, v3);
- uint8_t v1 = get_field(s, v1);
- TCGv_i64 tmp;
-
- while (v3 < v1 || (v3 - v1 + 1) > 16) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- /* Probe write access before actually modifying memory */
- tmp = tcg_const_i64((v3 - v1 + 1) * 16);
- gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
-
- for (;; v1++) {
- read_vec_element_i64(tmp, v1, 0, ES_64);
- tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- read_vec_element_i64(tmp, v1, 1, ES_64);
- tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
- if (v1 == v3) {
- break;
- }
- gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- }
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
-{
- const int v1_offs = vec_full_reg_offset(get_field(s, v1));
- TCGv_ptr a0 = tcg_temp_new_ptr();
-
- /* convert highest index into an actual length */
- tcg_gen_addi_i64(o->in2, o->in2, 1);
- tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
- gen_helper_vstl(cpu_env, a0, o->addr1, o->in2);
- tcg_temp_free_ptr(a0);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
-{
- const bool logical = s->fields.op2 == 0xd4 || s->fields.op2 == 0xd5;
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v2 = get_field(s, v2);
- const uint8_t src_es = get_field(s, m3);
- const uint8_t dst_es = src_es + 1;
- int dst_idx, src_idx;
- TCGv_i64 tmp;
-
- if (src_es > ES_32) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tmp = tcg_temp_new_i64();
- if (s->fields.op2 == 0xd7 || s->fields.op2 == 0xd5) {
- /* iterate backwards to avoid overwriting data we might need later */
- for (dst_idx = NUM_VEC_ELEMENTS(dst_es) - 1; dst_idx >= 0; dst_idx--) {
- src_idx = dst_idx;
- read_vec_element_i64(tmp, v2, src_idx,
- src_es | (logical ? 0 : MO_SIGN));
- write_vec_element_i64(tmp, v1, dst_idx, dst_es);
- }
-
- } else {
- /* iterate forward to avoid overwriting data we might need later */
- for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) {
- src_idx = dst_idx + NUM_VEC_ELEMENTS(src_es) / 2;
- read_vec_element_i64(tmp, v2, src_idx,
- src_es | (logical ? 0 : MO_SIGN));
- write_vec_element_i64(tmp, v1, dst_idx, dst_es);
- }
- }
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_va(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
-
- if (es > ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- } else if (es == ES_128) {
- gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
- }
- gen_gvec_fn_3(add, es, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
-{
- const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
- TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
- TCGv_i64 t3 = tcg_temp_new_i64();
-
- /* Calculate the carry into the MSB, ignoring the old MSBs */
- tcg_gen_andc_i64(t1, a, msb_mask);
- tcg_gen_andc_i64(t2, b, msb_mask);
- tcg_gen_add_i64(t1, t1, t2);
- /* Calculate the MSB without any carry into it */
- tcg_gen_xor_i64(t3, a, b);
- /* Calculate the carry out of the MSB in the MSB bit position */
- tcg_gen_and_i64(d, a, b);
- tcg_gen_and_i64(t1, t1, t3);
- tcg_gen_or_i64(d, d, t1);
- /* Isolate and shift the carry into position */
- tcg_gen_and_i64(d, d, msb_mask);
- tcg_gen_shri_i64(d, d, msb_bit_nr);
-
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
- tcg_temp_free_i64(t3);
-}
-
-static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- gen_acc(d, a, b, ES_8);
-}
-
-static void gen_acc16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- gen_acc(d, a, b, ES_16);
-}
-
-static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_i32 t = tcg_temp_new_i32();
-
- tcg_gen_add_i32(t, a, b);
- tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b);
- tcg_temp_free_i32(t);
-}
-
-static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- TCGv_i64 t = tcg_temp_new_i64();
-
- tcg_gen_add_i64(t, a, b);
- tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b);
- tcg_temp_free_i64(t);
-}
-
-static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
- TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
-{
- TCGv_i64 th = tcg_temp_new_i64();
- TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
-
- tcg_gen_add2_i64(tl, th, al, zero, bl, zero);
- tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
- tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
- tcg_gen_mov_i64(dh, zero);
-
- tcg_temp_free_i64(th);
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(zero);
-}
-
-static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g[4] = {
- { .fni8 = gen_acc8_i64, },
- { .fni8 = gen_acc16_i64, },
- { .fni4 = gen_acc_i32, },
- { .fni8 = gen_acc_i64, },
- };
-
- if (es > ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- } else if (es == ES_128) {
- gen_gvec128_3_i64(gen_acc2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
- }
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), &g[es]);
- return DISAS_NEXT;
-}
-
-static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
- TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
-{
- TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 th = tcg_const_i64(0);
-
- /* extract the carry only */
- tcg_gen_extract_i64(tl, cl, 0, 1);
- tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
- tcg_gen_add2_i64(dl, dh, dl, dh, tl, th);
-
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
-}
-
-static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
-{
- if (get_field(s, m5) != ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec128_4_i64(gen_ac2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3),
- get_field(s, v4));
- return DISAS_NEXT;
-}
-
-static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
- TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
-{
- TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 th = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
-
- tcg_gen_andi_i64(tl, cl, 1);
- tcg_gen_add2_i64(tl, th, tl, zero, al, zero);
- tcg_gen_add2_i64(tl, th, tl, th, bl, zero);
- tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
- tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
- tcg_gen_mov_i64(dh, zero);
-
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
- tcg_temp_free_i64(zero);
-}
-
-static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
-{
- if (get_field(s, m5) != ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec128_4_i64(gen_accc2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3),
- get_field(s, v4));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vn(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(and, ES_8, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(andc, ES_8, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- tcg_gen_ext_i32_i64(t0, a);
- tcg_gen_ext_i32_i64(t1, b);
- tcg_gen_add_i64(t0, t0, t1);
- tcg_gen_addi_i64(t0, t0, 1);
- tcg_gen_shri_i64(t0, t0, 1);
- tcg_gen_extrl_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
-{
- TCGv_i64 dh = tcg_temp_new_i64();
- TCGv_i64 ah = tcg_temp_new_i64();
- TCGv_i64 bh = tcg_temp_new_i64();
-
- /* extending the sign by one bit is sufficient */
- tcg_gen_extract_i64(ah, al, 63, 1);
- tcg_gen_extract_i64(bh, bl, 63, 1);
- tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
- gen_addi2_i64(dl, dh, dl, dh, 1);
- tcg_gen_extract2_i64(dl, dl, dh, 1);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(ah);
- tcg_temp_free_i64(bh);
-}
-
-static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g[4] = {
- { .fno = gen_helper_gvec_vavg8, },
- { .fno = gen_helper_gvec_vavg16, },
- { .fni4 = gen_avg_i32, },
- { .fni8 = gen_avg_i64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), &g[es]);
- return DISAS_NEXT;
-}
-
-static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
-
- tcg_gen_extu_i32_i64(t0, a);
- tcg_gen_extu_i32_i64(t1, b);
- tcg_gen_add_i64(t0, t0, t1);
- tcg_gen_addi_i64(t0, t0, 1);
- tcg_gen_shri_i64(t0, t0, 1);
- tcg_gen_extrl_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
-{
- TCGv_i64 dh = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
-
- tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
- gen_addi2_i64(dl, dh, dl, dh, 1);
- tcg_gen_extract2_i64(dl, dl, dh, 1);
-
- tcg_temp_free_i64(dh);
- tcg_temp_free_i64(zero);
-}
-
-static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g[4] = {
- { .fno = gen_helper_gvec_vavgl8, },
- { .fno = gen_helper_gvec_vavgl16, },
- { .fni4 = gen_avgl_i32, },
- { .fni8 = gen_avgl_i64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), &g[es]);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- TCGv_i32 sum = tcg_temp_new_i32();
- int i;
-
- read_vec_element_i32(sum, get_field(s, v3), 1, ES_32);
- for (i = 0; i < 4; i++) {
- read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
- tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
- }
- gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
- write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
-
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(sum);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
-{
- uint8_t es = get_field(s, m3);
- const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- if (s->fields.op2 == 0xdb) {
- es |= MO_SIGN;
- }
-
- o->in1 = tcg_temp_new_i64();
- o->in2 = tcg_temp_new_i64();
- read_vec_element_i64(o->in1, get_field(s, v1), enr, es);
- read_vec_element_i64(o->in2, get_field(s, v2), enr, es);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- TCGCond cond = s->insn->data;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- tcg_gen_gvec_cmp(cond, es,
- vec_full_reg_offset(get_field(s, v1)),
- vec_full_reg_offset(get_field(s, v2)),
- vec_full_reg_offset(get_field(s, v3)), 16, 16);
- if (get_field(s, m5) & 0x1) {
- TCGv_i64 low = tcg_temp_new_i64();
- TCGv_i64 high = tcg_temp_new_i64();
-
- read_vec_element_i64(high, get_field(s, v1), 0, ES_64);
- read_vec_element_i64(low, get_field(s, v1), 1, ES_64);
- gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
-
- tcg_temp_free_i64(low);
- tcg_temp_free_i64(high);
- }
- return DISAS_NEXT;
-}
-
-static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a)
-{
- tcg_gen_clzi_i32(d, a, 32);
-}
-
-static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a)
-{
- tcg_gen_clzi_i64(d, a, 64);
-}
-
-static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
- static const GVecGen2 g[4] = {
- { .fno = gen_helper_gvec_vclz8, },
- { .fno = gen_helper_gvec_vclz16, },
- { .fni4 = gen_clz_i32, },
- { .fni8 = gen_clz_i64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
- return DISAS_NEXT;
-}
-
-static void gen_ctz_i32(TCGv_i32 d, TCGv_i32 a)
-{
- tcg_gen_ctzi_i32(d, a, 32);
-}
-
-static void gen_ctz_i64(TCGv_i64 d, TCGv_i64 a)
-{
- tcg_gen_ctzi_i64(d, a, 64);
-}
-
-static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
- static const GVecGen2 g[4] = {
- { .fno = gen_helper_gvec_vctz8, },
- { .fno = gen_helper_gvec_vctz16, },
- { .fni4 = gen_ctz_i32, },
- { .fni8 = gen_ctz_i64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(xor, ES_8, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g[4] = {
- { .fno = gen_helper_gvec_vgfm8, },
- { .fno = gen_helper_gvec_vgfm16, },
- { .fno = gen_helper_gvec_vgfm32, },
- { .fno = gen_helper_gvec_vgfm64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), &g[es]);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m5);
- static const GVecGen4 g[4] = {
- { .fno = gen_helper_gvec_vgfma8, },
- { .fno = gen_helper_gvec_vgfma16, },
- { .fno = gen_helper_gvec_vgfma32, },
- { .fno = gen_helper_gvec_vgfma64, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- gen_gvec_4(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4), &g[es]);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec_fn_2(neg, es, get_field(s, v1), get_field(s, v2));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec_fn_2(abs, es, get_field(s, v1), get_field(s, v2));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
-{
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v2 = get_field(s, v2);
- const uint8_t v3 = get_field(s, v3);
- const uint8_t es = get_field(s, m4);
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0xff:
- gen_gvec_fn_3(smax, es, v1, v2, v3);
- break;
- case 0xfd:
- gen_gvec_fn_3(umax, es, v1, v2, v3);
- break;
- case 0xfe:
- gen_gvec_fn_3(smin, es, v1, v2, v3);
- break;
- case 0xfc:
- gen_gvec_fn_3(umin, es, v1, v2, v3);
- break;
- default:
- g_assert_not_reached();
- }
- return DISAS_NEXT;
-}
-
-static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
-
- tcg_gen_mul_i32(t0, a, b);
- tcg_gen_add_i32(d, t0, c);
-
- tcg_temp_free_i32(t0);
-}
-
-static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
-
- tcg_gen_ext_i32_i64(t0, a);
- tcg_gen_ext_i32_i64(t1, b);
- tcg_gen_ext_i32_i64(t2, c);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_add_i64(t0, t0, t2);
- tcg_gen_extrh_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
-{
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
-
- tcg_gen_extu_i32_i64(t0, a);
- tcg_gen_extu_i32_i64(t1, b);
- tcg_gen_extu_i32_i64(t2, c);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_add_i64(t0, t0, t2);
- tcg_gen_extrh_i64_i32(d, t0);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m5);
- static const GVecGen4 g_vmal[3] = {
- { .fno = gen_helper_gvec_vmal8, },
- { .fno = gen_helper_gvec_vmal16, },
- { .fni4 = gen_mal_i32, },
- };
- static const GVecGen4 g_vmah[3] = {
- { .fno = gen_helper_gvec_vmah8, },
- { .fno = gen_helper_gvec_vmah16, },
- { .fni4 = gen_mah_i32, },
- };
- static const GVecGen4 g_vmalh[3] = {
- { .fno = gen_helper_gvec_vmalh8, },
- { .fno = gen_helper_gvec_vmalh16, },
- { .fni4 = gen_malh_i32, },
- };
- static const GVecGen4 g_vmae[3] = {
- { .fno = gen_helper_gvec_vmae8, },
- { .fno = gen_helper_gvec_vmae16, },
- { .fno = gen_helper_gvec_vmae32, },
- };
- static const GVecGen4 g_vmale[3] = {
- { .fno = gen_helper_gvec_vmale8, },
- { .fno = gen_helper_gvec_vmale16, },
- { .fno = gen_helper_gvec_vmale32, },
- };
- static const GVecGen4 g_vmao[3] = {
- { .fno = gen_helper_gvec_vmao8, },
- { .fno = gen_helper_gvec_vmao16, },
- { .fno = gen_helper_gvec_vmao32, },
- };
- static const GVecGen4 g_vmalo[3] = {
- { .fno = gen_helper_gvec_vmalo8, },
- { .fno = gen_helper_gvec_vmalo16, },
- { .fno = gen_helper_gvec_vmalo32, },
- };
- const GVecGen4 *fn;
-
- if (es > ES_32) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0xaa:
- fn = &g_vmal[es];
- break;
- case 0xab:
- fn = &g_vmah[es];
- break;
- case 0xa9:
- fn = &g_vmalh[es];
- break;
- case 0xae:
- fn = &g_vmae[es];
- break;
- case 0xac:
- fn = &g_vmale[es];
- break;
- case 0xaf:
- fn = &g_vmao[es];
- break;
- case 0xad:
- fn = &g_vmalo[es];
- break;
- default:
- g_assert_not_reached();
- }
-
- gen_gvec_4(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4), fn);
- return DISAS_NEXT;
-}
-
-static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_i32 t = tcg_temp_new_i32();
-
- tcg_gen_muls2_i32(t, d, a, b);
- tcg_temp_free_i32(t);
-}
-
-static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_i32 t = tcg_temp_new_i32();
-
- tcg_gen_mulu2_i32(t, d, a, b);
- tcg_temp_free_i32(t);
-}
-
-static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g_vmh[3] = {
- { .fno = gen_helper_gvec_vmh8, },
- { .fno = gen_helper_gvec_vmh16, },
- { .fni4 = gen_mh_i32, },
- };
- static const GVecGen3 g_vmlh[3] = {
- { .fno = gen_helper_gvec_vmlh8, },
- { .fno = gen_helper_gvec_vmlh16, },
- { .fni4 = gen_mlh_i32, },
- };
- static const GVecGen3 g_vme[3] = {
- { .fno = gen_helper_gvec_vme8, },
- { .fno = gen_helper_gvec_vme16, },
- { .fno = gen_helper_gvec_vme32, },
- };
- static const GVecGen3 g_vmle[3] = {
- { .fno = gen_helper_gvec_vmle8, },
- { .fno = gen_helper_gvec_vmle16, },
- { .fno = gen_helper_gvec_vmle32, },
- };
- static const GVecGen3 g_vmo[3] = {
- { .fno = gen_helper_gvec_vmo8, },
- { .fno = gen_helper_gvec_vmo16, },
- { .fno = gen_helper_gvec_vmo32, },
- };
- static const GVecGen3 g_vmlo[3] = {
- { .fno = gen_helper_gvec_vmlo8, },
- { .fno = gen_helper_gvec_vmlo16, },
- { .fno = gen_helper_gvec_vmlo32, },
- };
- const GVecGen3 *fn;
-
- if (es > ES_32) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0xa2:
- gen_gvec_fn_3(mul, es, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
- case 0xa3:
- fn = &g_vmh[es];
- break;
- case 0xa1:
- fn = &g_vmlh[es];
- break;
- case 0xa6:
- fn = &g_vme[es];
- break;
- case 0xa4:
- fn = &g_vmle[es];
- break;
- case 0xa7:
- fn = &g_vmo[es];
- break;
- case 0xa5:
- fn = &g_vmlo[es];
- break;
- default:
- g_assert_not_reached();
- }
-
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), fn);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(nand, ES_8, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(nor, ES_8, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(eqv, ES_8, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(or, ES_8, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
-{
- gen_gvec_fn_3(orc, ES_8, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m3);
- static const GVecGen2 g[4] = {
- { .fno = gen_helper_gvec_vpopct8, },
- { .fno = gen_helper_gvec_vpopct16, },
- { .fni4 = tcg_gen_ctpop_i32, },
- { .fni8 = tcg_gen_ctpop_i64, },
- };
-
- if (es > ES_64 || (es != ES_8 && !s390_has_feat(S390_FEAT_VECTOR_ENH))) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
- return DISAS_NEXT;
-}
-
-static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
-{
- TCGv_i32 t = tcg_temp_new_i32();
-
- tcg_gen_rotli_i32(t, a, c & 31);
- tcg_gen_and_i32(t, t, b);
- tcg_gen_andc_i32(d, d, b);
- tcg_gen_or_i32(d, d, t);
-
- tcg_temp_free_i32(t);
-}
-
-static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
-{
- TCGv_i64 t = tcg_temp_new_i64();
-
- tcg_gen_rotli_i64(t, a, c & 63);
- tcg_gen_and_i64(t, t, b);
- tcg_gen_andc_i64(d, d, b);
- tcg_gen_or_i64(d, d, t);
-
- tcg_temp_free_i64(t);
-}
-
-static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m5);
- const uint8_t i4 = get_field(s, i4) &
- (NUM_VEC_ELEMENT_BITS(es) - 1);
- static const GVecGen3i g[4] = {
- { .fno = gen_helper_gvec_verim8, },
- { .fno = gen_helper_gvec_verim16, },
- { .fni4 = gen_rim_i32,
- .load_dest = true, },
- { .fni8 = gen_rim_i64,
- .load_dest = true, },
- };
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec_3i(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), i4, &g[es]);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v2 = get_field(s, v2);
- const uint8_t v3 = get_field(s, v3);
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0x70:
- gen_gvec_fn_3(shlv, es, v1, v2, v3);
- break;
- case 0x73:
- gen_gvec_fn_3(rotlv, es, v1, v2, v3);
- break;
- case 0x7a:
- gen_gvec_fn_3(sarv, es, v1, v2, v3);
- break;
- case 0x78:
- gen_gvec_fn_3(shrv, es, v1, v2, v3);
- break;
- default:
- g_assert_not_reached();
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t d2 = get_field(s, d2) &
- (NUM_VEC_ELEMENT_BITS(es) - 1);
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v3 = get_field(s, v3);
- TCGv_i32 shift;
-
- if (es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (likely(!get_field(s, b2))) {
- switch (s->fields.op2) {
- case 0x30:
- gen_gvec_fn_2i(shli, es, v1, v3, d2);
- break;
- case 0x33:
- gen_gvec_fn_2i(rotli, es, v1, v3, d2);
- break;
- case 0x3a:
- gen_gvec_fn_2i(sari, es, v1, v3, d2);
- break;
- case 0x38:
- gen_gvec_fn_2i(shri, es, v1, v3, d2);
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- shift = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(shift, o->addr1);
- tcg_gen_andi_i32(shift, shift, NUM_VEC_ELEMENT_BITS(es) - 1);
- switch (s->fields.op2) {
- case 0x30:
- gen_gvec_fn_2s(shls, es, v1, v3, shift);
- break;
- case 0x33:
- gen_gvec_fn_2s(rotls, es, v1, v3, shift);
- break;
- case 0x3a:
- gen_gvec_fn_2s(sars, es, v1, v3, shift);
- break;
- case 0x38:
- gen_gvec_fn_2s(shrs, es, v1, v3, shift);
- break;
- default:
- g_assert_not_reached();
- }
- tcg_temp_free_i32(shift);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsl(DisasContext *s, DisasOps *o)
-{
- TCGv_i64 shift = tcg_temp_new_i64();
-
- read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
- if (s->fields.op2 == 0x74) {
- tcg_gen_andi_i64(shift, shift, 0x7);
- } else {
- tcg_gen_andi_i64(shift, shift, 0x78);
- }
-
- gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
- shift, 0, gen_helper_gvec_vsl);
- tcg_temp_free_i64(shift);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
-{
- const uint8_t i4 = get_field(s, i4) & 0xf;
- const int left_shift = (i4 & 7) * 8;
- const int right_shift = 64 - left_shift;
- TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
-
- if ((i4 & 8) == 0) {
- read_vec_element_i64(t0, get_field(s, v2), 0, ES_64);
- read_vec_element_i64(t1, get_field(s, v2), 1, ES_64);
- read_vec_element_i64(t2, get_field(s, v3), 0, ES_64);
- } else {
- read_vec_element_i64(t0, get_field(s, v2), 1, ES_64);
- read_vec_element_i64(t1, get_field(s, v3), 0, ES_64);
- read_vec_element_i64(t2, get_field(s, v3), 1, ES_64);
- }
- tcg_gen_extract2_i64(t0, t1, t0, right_shift);
- tcg_gen_extract2_i64(t1, t2, t1, right_shift);
- write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
- write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsra(DisasContext *s, DisasOps *o)
-{
- TCGv_i64 shift = tcg_temp_new_i64();
-
- read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
- if (s->fields.op2 == 0x7e) {
- tcg_gen_andi_i64(shift, shift, 0x7);
- } else {
- tcg_gen_andi_i64(shift, shift, 0x78);
- }
-
- gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
- shift, 0, gen_helper_gvec_vsra);
- tcg_temp_free_i64(shift);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o)
-{
- TCGv_i64 shift = tcg_temp_new_i64();
-
- read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
- if (s->fields.op2 == 0x7c) {
- tcg_gen_andi_i64(shift, shift, 0x7);
- } else {
- tcg_gen_andi_i64(shift, shift, 0x78);
- }
-
- gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
- shift, 0, gen_helper_gvec_vsrl);
- tcg_temp_free_i64(shift);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
-
- if (es > ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- } else if (es == ES_128) {
- gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
- }
- gen_gvec_fn_3(sub, es, get_field(s, v1), get_field(s, v2),
- get_field(s, v3));
- return DISAS_NEXT;
-}
-
-static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
-{
- tcg_gen_setcond_i32(TCG_COND_GEU, d, a, b);
-}
-
-static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
-{
- tcg_gen_setcond_i64(TCG_COND_GEU, d, a, b);
-}
-
-static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
- TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
-{
- TCGv_i64 th = tcg_temp_new_i64();
- TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
-
- tcg_gen_sub2_i64(tl, th, al, zero, bl, zero);
- tcg_gen_andi_i64(th, th, 1);
- tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
- tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
- /* "invert" the result: -1 -> 0; 0 -> 1 */
- tcg_gen_addi_i64(dl, th, 1);
- tcg_gen_mov_i64(dh, zero);
-
- tcg_temp_free_i64(th);
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(zero);
-}
-
-static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- static const GVecGen3 g[4] = {
- { .fno = gen_helper_gvec_vscbi8, },
- { .fno = gen_helper_gvec_vscbi16, },
- { .fni4 = gen_scbi_i32, },
- { .fni8 = gen_scbi_i64, },
- };
-
- if (es > ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- } else if (es == ES_128) {
- gen_gvec128_3_i64(gen_scbi2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3));
- return DISAS_NEXT;
- }
- gen_gvec_3(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), &g[es]);
- return DISAS_NEXT;
-}
-
-static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
- TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
-{
- TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 th = tcg_temp_new_i64();
-
- tcg_gen_not_i64(tl, bl);
- tcg_gen_not_i64(th, bh);
- gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch);
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
-}
-
-static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
-{
- if (get_field(s, m5) != ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec128_4_i64(gen_sbi2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3),
- get_field(s, v4));
- return DISAS_NEXT;
-}
-
-static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
- TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
-{
- TCGv_i64 th = tcg_temp_new_i64();
- TCGv_i64 tl = tcg_temp_new_i64();
-
- tcg_gen_not_i64(tl, bl);
- tcg_gen_not_i64(th, bh);
- gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch);
-
- tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
-}
-
-static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
-{
- if (get_field(s, m5) != ES_128) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s, v1),
- get_field(s, v2), get_field(s, v3),
- get_field(s, v4));
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- TCGv_i64 sum, tmp;
- uint8_t dst_idx;
-
- if (es == ES_8 || es > ES_32) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- sum = tcg_temp_new_i64();
- tmp = tcg_temp_new_i64();
- for (dst_idx = 0; dst_idx < 2; dst_idx++) {
- uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2;
- const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1;
-
- read_vec_element_i64(sum, get_field(s, v3), max_idx, es);
- for (; idx <= max_idx; idx++) {
- read_vec_element_i64(tmp, get_field(s, v2), idx, es);
- tcg_gen_add_i64(sum, sum, tmp);
- }
- write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64);
- }
- tcg_temp_free_i64(sum);
- tcg_temp_free_i64(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1;
- TCGv_i64 sumh, suml, zero, tmpl;
- uint8_t idx;
-
- if (es < ES_32 || es > ES_64) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- sumh = tcg_const_i64(0);
- suml = tcg_temp_new_i64();
- zero = tcg_const_i64(0);
- tmpl = tcg_temp_new_i64();
-
- read_vec_element_i64(suml, get_field(s, v3), max_idx, es);
- for (idx = 0; idx <= max_idx; idx++) {
- read_vec_element_i64(tmpl, get_field(s, v2), idx, es);
- tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero);
- }
- write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64);
- write_vec_element_i64(suml, get_field(s, v1), 1, ES_64);
-
- tcg_temp_free_i64(sumh);
- tcg_temp_free_i64(suml);
- tcg_temp_free_i64(zero);
- tcg_temp_free_i64(tmpl);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- TCGv_i32 sum, tmp;
- uint8_t dst_idx;
-
- if (es > ES_16) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- sum = tcg_temp_new_i32();
- tmp = tcg_temp_new_i32();
- for (dst_idx = 0; dst_idx < 4; dst_idx++) {
- uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4;
- const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1;
-
- read_vec_element_i32(sum, get_field(s, v3), max_idx, es);
- for (; idx <= max_idx; idx++) {
- read_vec_element_i32(tmp, get_field(s, v2), idx, es);
- tcg_gen_add_i32(sum, sum, tmp);
- }
- write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32);
- }
- tcg_temp_free_i32(sum);
- tcg_temp_free_i32(tmp);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
-{
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
- cpu_env, 0, gen_helper_gvec_vtm);
- set_cc_static(s);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfae(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- static gen_helper_gvec_3 * const g[3] = {
- gen_helper_gvec_vfae8,
- gen_helper_gvec_vfae16,
- gen_helper_gvec_vfae32,
- };
- static gen_helper_gvec_3_ptr * const g_cc[3] = {
- gen_helper_gvec_vfae_cc8,
- gen_helper_gvec_vfae_cc16,
- gen_helper_gvec_vfae_cc32,
- };
- if (es > ES_32) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m5, 0, 1)) {
- gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, g_cc[es]);
- set_cc_static(s);
- } else {
- gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), m5, g[es]);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfee(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- static gen_helper_gvec_3 * const g[3] = {
- gen_helper_gvec_vfee8,
- gen_helper_gvec_vfee16,
- gen_helper_gvec_vfee32,
- };
- static gen_helper_gvec_3_ptr * const g_cc[3] = {
- gen_helper_gvec_vfee_cc8,
- gen_helper_gvec_vfee_cc16,
- gen_helper_gvec_vfee_cc32,
- };
-
- if (es > ES_32 || m5 & ~0x3) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m5, 0, 1)) {
- gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, g_cc[es]);
- set_cc_static(s);
- } else {
- gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), m5, g[es]);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfene(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- static gen_helper_gvec_3 * const g[3] = {
- gen_helper_gvec_vfene8,
- gen_helper_gvec_vfene16,
- gen_helper_gvec_vfene32,
- };
- static gen_helper_gvec_3_ptr * const g_cc[3] = {
- gen_helper_gvec_vfene_cc8,
- gen_helper_gvec_vfene_cc16,
- gen_helper_gvec_vfene_cc32,
- };
-
- if (es > ES_32 || m5 & ~0x3) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m5, 0, 1)) {
- gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, g_cc[es]);
- set_cc_static(s);
- } else {
- gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), m5, g[es]);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vistr(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- static gen_helper_gvec_2 * const g[3] = {
- gen_helper_gvec_vistr8,
- gen_helper_gvec_vistr16,
- gen_helper_gvec_vistr32,
- };
- static gen_helper_gvec_2_ptr * const g_cc[3] = {
- gen_helper_gvec_vistr_cc8,
- gen_helper_gvec_vistr_cc16,
- gen_helper_gvec_vistr_cc32,
- };
-
- if (es > ES_32 || m5 & ~0x1) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m5, 0, 1)) {
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
- cpu_env, 0, g_cc[es]);
- set_cc_static(s);
- } else {
- gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0,
- g[es]);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o)
-{
- const uint8_t es = get_field(s, m5);
- const uint8_t m6 = get_field(s, m6);
- static gen_helper_gvec_4 * const g[3] = {
- gen_helper_gvec_vstrc8,
- gen_helper_gvec_vstrc16,
- gen_helper_gvec_vstrc32,
- };
- static gen_helper_gvec_4 * const g_rt[3] = {
- gen_helper_gvec_vstrc_rt8,
- gen_helper_gvec_vstrc_rt16,
- gen_helper_gvec_vstrc_rt32,
- };
- static gen_helper_gvec_4_ptr * const g_cc[3] = {
- gen_helper_gvec_vstrc_cc8,
- gen_helper_gvec_vstrc_cc16,
- gen_helper_gvec_vstrc_cc32,
- };
- static gen_helper_gvec_4_ptr * const g_cc_rt[3] = {
- gen_helper_gvec_vstrc_cc_rt8,
- gen_helper_gvec_vstrc_cc_rt16,
- gen_helper_gvec_vstrc_cc_rt32,
- };
-
- if (es > ES_32) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m6, 0, 1)) {
- if (extract32(m6, 2, 1)) {
- gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4),
- cpu_env, m6, g_cc_rt[es]);
- } else {
- gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4),
- cpu_env, m6, g_cc[es]);
- }
- set_cc_static(s);
- } else {
- if (extract32(m6, 2, 1)) {
- gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4),
- m6, g_rt[es]);
- } else {
- gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4),
- m6, g[es]);
- }
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
-{
- const uint8_t fpf = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- const bool se = extract32(m5, 3, 1);
- gen_helper_gvec_3_ptr *fn;
-
- if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0xe3:
- fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64;
- break;
- case 0xe5:
- fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64;
- break;
- case 0xe7:
- fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
- break;
- case 0xe2:
- fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64;
- break;
- default:
- g_assert_not_reached();
- }
- gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, 0, fn);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
-{
- const uint8_t fpf = get_field(s, m3);
- const uint8_t m4 = get_field(s, m4);
-
- if (fpf != FPF_LONG || m4) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (s->fields.op2 == 0xcb) {
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
- cpu_env, 0, gen_helper_gvec_wfc64);
- } else {
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
- cpu_env, 0, gen_helper_gvec_wfk64);
- }
- set_cc_static(s);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
-{
- const uint8_t fpf = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- const uint8_t m6 = get_field(s, m6);
- const bool se = extract32(m5, 3, 1);
- const bool cs = extract32(m6, 0, 1);
- gen_helper_gvec_3_ptr *fn;
-
- if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (cs) {
- switch (s->fields.op2) {
- case 0xe8:
- fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc;
- break;
- case 0xeb:
- fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc;
- break;
- case 0xea:
- fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc;
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- switch (s->fields.op2) {
- case 0xe8:
- fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64;
- break;
- case 0xeb:
- fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64;
- break;
- case 0xea:
- fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64;
- break;
- default:
- g_assert_not_reached();
- }
- }
- gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, 0, fn);
- if (cs) {
- set_cc_static(s);
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
-{
- const uint8_t fpf = get_field(s, m3);
- const uint8_t m4 = get_field(s, m4);
- const uint8_t erm = get_field(s, m5);
- const bool se = extract32(m4, 3, 1);
- gen_helper_gvec_2_ptr *fn;
-
- if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- switch (s->fields.op2) {
- case 0xc3:
- fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64;
- break;
- case 0xc1:
- fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64;
- break;
- case 0xc2:
- fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64;
- break;
- case 0xc0:
- fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64;
- break;
- case 0xc7:
- fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64;
- break;
- case 0xc5:
- fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64;
- break;
- default:
- g_assert_not_reached();
- }
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
- deposit32(m4, 4, 4, erm), fn);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfll(DisasContext *s, DisasOps *o)
-{
- const uint8_t fpf = get_field(s, m3);
- const uint8_t m4 = get_field(s, m4);
- gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32;
-
- if (fpf != FPF_SHORT || extract32(m4, 0, 3)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m4, 3, 1)) {
- fn = gen_helper_gvec_vfll32s;
- }
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
- 0, fn);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
-{
- const uint8_t m5 = get_field(s, m5);
- const uint8_t fpf = get_field(s, m6);
- const bool se = extract32(m5, 3, 1);
- gen_helper_gvec_4_ptr *fn;
-
- if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (s->fields.op2 == 0x8f) {
- fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64;
- } else {
- fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64;
- }
- gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4), cpu_env,
- 0, fn);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
-{
- const uint8_t v1 = get_field(s, v1);
- const uint8_t v2 = get_field(s, v2);
- const uint8_t fpf = get_field(s, m3);
- const uint8_t m4 = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- TCGv_i64 tmp;
-
- if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m4, 3, 1)) {
- tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, v2, 0, ES_64);
- switch (m5) {
- case 0:
- /* sign bit is inverted (complement) */
- tcg_gen_xori_i64(tmp, tmp, 1ull << 63);
- break;
- case 1:
- /* sign bit is set to one (negative) */
- tcg_gen_ori_i64(tmp, tmp, 1ull << 63);
- break;
- case 2:
- /* sign bit is set to zero (positive) */
- tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1);
- break;
- }
- write_vec_element_i64(tmp, v1, 0, ES_64);
- tcg_temp_free_i64(tmp);
- } else {
- switch (m5) {
- case 0:
- /* sign bit is inverted (complement) */
- gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63);
- break;
- case 1:
- /* sign bit is set to one (negative) */
- gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63);
- break;
- case 2:
- /* sign bit is set to zero (positive) */
- gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1);
- break;
- }
- }
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o)
-{
- const uint8_t fpf = get_field(s, m3);
- const uint8_t m4 = get_field(s, m4);
- gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64;
-
- if (fpf != FPF_LONG || extract32(m4, 0, 3)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m4, 3, 1)) {
- fn = gen_helper_gvec_vfsq64s;
- }
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
- 0, fn);
- return DISAS_NEXT;
-}
-
-static DisasJumpType op_vftci(DisasContext *s, DisasOps *o)
-{
- const uint16_t i3 = get_field(s, i3);
- const uint8_t fpf = get_field(s, m4);
- const uint8_t m5 = get_field(s, m5);
- gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64;
-
- if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
-
- if (extract32(m5, 3, 1)) {
- fn = gen_helper_gvec_vftci64s;
- }
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn);
- set_cc_static(s);
- return DISAS_NEXT;
-}
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_dc232b
-#include "core-dc232b/xtensa-modules.inc.c"
+#include "core-dc232b/xtensa-modules.c.inc"
static XtensaConfig dc232b __attribute__((unused)) = {
.name = "dc232b",
.gdb_regmap = {
.reg = {
-#include "core-dc232b/gdb-config.inc.c"
+#include "core-dc232b/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
--- /dev/null
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+ XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(55, 220, 18, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(56, 224, 18, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(58, 232, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(59, 236, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(60, 240, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(61, 244, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(62, 248, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(63, 252, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(64, 256, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(65, 260, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(66, 264, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(67, 268, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(68, 272, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(69, 276, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(70, 280, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(71, 284, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(72, 288, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(73, 292, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(74, 296, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(75, 300, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(76, 304, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(77, 308, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(78, 312, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(79, 316, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(80, 320, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(81, 324, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(82, 328, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(83, 332, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(84, 336, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(85, 340, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(86, 344, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(87, 348, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(89, 356, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(90, 360, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(92, 368, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(93, 372, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(94, 376, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(95, 380, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(96, 384, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(97, 388, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(98, 392, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(99, 396, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(100, 400, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(101, 404, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(102, 408, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(103, 412, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(104, 416, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(105, 420, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(106, 424, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(107, 428, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(108, 432, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(109, 436, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(110, 440, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(111, 444, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(112, 448, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(113, 452, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(114, 456, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(115, 460, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(116, 464, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(117, 468, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(118, 472, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14,
+ 0, 0, 0, 0, 0, 0)
+ XTREG(119, 476, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15,
+ 0, 0, 0, 0, 0, 0)
+ XTREG_END
+++ /dev/null
-/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
-
- Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
- XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
- 0, 0, 0, 0, 0, 0)
- XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
- 0, 0, 0, 0, 0, 0)
- XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
- 0, 0, 0, 0, 0, 0)
- XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
- 0, 0, 0, 0, 0, 0)
- XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3,
- 0, 0, 0, 0, 0, 0)
- XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4,
- 0, 0, 0, 0, 0, 0)
- XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5,
- 0, 0, 0, 0, 0, 0)
- XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6,
- 0, 0, 0, 0, 0, 0)
- XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7,
- 0, 0, 0, 0, 0, 0)
- XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8,
- 0, 0, 0, 0, 0, 0)
- XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9,
- 0, 0, 0, 0, 0, 0)
- XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10,
- 0, 0, 0, 0, 0, 0)
- XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11,
- 0, 0, 0, 0, 0, 0)
- XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12,
- 0, 0, 0, 0, 0, 0)
- XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13,
- 0, 0, 0, 0, 0, 0)
- XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14,
- 0, 0, 0, 0, 0, 0)
- XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15,
- 0, 0, 0, 0, 0, 0)
- XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16,
- 0, 0, 0, 0, 0, 0)
- XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17,
- 0, 0, 0, 0, 0, 0)
- XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18,
- 0, 0, 0, 0, 0, 0)
- XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19,
- 0, 0, 0, 0, 0, 0)
- XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20,
- 0, 0, 0, 0, 0, 0)
- XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21,
- 0, 0, 0, 0, 0, 0)
- XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22,
- 0, 0, 0, 0, 0, 0)
- XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23,
- 0, 0, 0, 0, 0, 0)
- XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24,
- 0, 0, 0, 0, 0, 0)
- XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25,
- 0, 0, 0, 0, 0, 0)
- XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26,
- 0, 0, 0, 0, 0, 0)
- XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27,
- 0, 0, 0, 0, 0, 0)
- XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28,
- 0, 0, 0, 0, 0, 0)
- XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29,
- 0, 0, 0, 0, 0, 0)
- XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30,
- 0, 0, 0, 0, 0, 0)
- XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31,
- 0, 0, 0, 0, 0, 0)
- XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg,
- 0, 0, 0, 0, 0, 0)
- XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend,
- 0, 0, 0, 0, 0, 0)
- XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount,
- 0, 0, 0, 0, 0, 0)
- XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar,
- 0, 0, 0, 0, 0, 0)
- XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase,
- 0, 0, 0, 0, 0, 0)
- XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase,
- 0, 0, 0, 0, 0, 0)
- XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart,
- 0, 0, 0, 0, 0, 0)
- XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176,
- 0, 0, 0, 0, 0, 0)
- XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208,
- 0, 0, 0, 0, 0, 0)
- XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps,
- 0, 0, 0, 0, 0, 0)
- XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr,
- 0, 0, 0, 0, 0, 0)
- XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1,
- 0, 0, 0, 0, 0, 0)
- XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo,
- 0, 0, 0, 0, 0, 0)
- XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi,
- 0, 0, 0, 0, 0, 0)
- XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0,
- 0, 0, 0, 0, 0, 0)
- XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1,
- 0, 0, 0, 0, 0, 0)
- XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2,
- 0, 0, 0, 0, 0, 0)
- XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3,
- 0, 0, 0, 0, 0, 0)
- XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate,
- 0, 0, 0, 0, 0, 0)
- XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr,
- 0, 0, 0, 0, 0, 0)
- XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid,
- 0, 0, 0, 0, 0, 0)
- XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid,
- 0, 0, 0, 0, 0, 0)
- XTREG(55, 220, 18, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg,
- 0, 0, 0, 0, 0, 0)
- XTREG(56, 224, 18, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg,
- 0, 0, 0, 0, 0, 0)
- XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable,
- 0, 0, 0, 0, 0, 0)
- XTREG(58, 232, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr,
- 0, 0, 0, 0, 0, 0)
- XTREG(59, 236, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0,
- 0, 0, 0, 0, 0, 0)
- XTREG(60, 240, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1,
- 0, 0, 0, 0, 0, 0)
- XTREG(61, 244, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0,
- 0, 0, 0, 0, 0, 0)
- XTREG(62, 248, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1,
- 0, 0, 0, 0, 0, 0)
- XTREG(63, 252, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0,
- 0, 0, 0, 0, 0, 0)
- XTREG(64, 256, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1,
- 0, 0, 0, 0, 0, 0)
- XTREG(65, 260, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1,
- 0, 0, 0, 0, 0, 0)
- XTREG(66, 264, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2,
- 0, 0, 0, 0, 0, 0)
- XTREG(67, 268, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3,
- 0, 0, 0, 0, 0, 0)
- XTREG(68, 272, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4,
- 0, 0, 0, 0, 0, 0)
- XTREG(69, 276, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5,
- 0, 0, 0, 0, 0, 0)
- XTREG(70, 280, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6,
- 0, 0, 0, 0, 0, 0)
- XTREG(71, 284, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7,
- 0, 0, 0, 0, 0, 0)
- XTREG(72, 288, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc,
- 0, 0, 0, 0, 0, 0)
- XTREG(73, 292, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2,
- 0, 0, 0, 0, 0, 0)
- XTREG(74, 296, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3,
- 0, 0, 0, 0, 0, 0)
- XTREG(75, 300, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4,
- 0, 0, 0, 0, 0, 0)
- XTREG(76, 304, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5,
- 0, 0, 0, 0, 0, 0)
- XTREG(77, 308, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6,
- 0, 0, 0, 0, 0, 0)
- XTREG(78, 312, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7,
- 0, 0, 0, 0, 0, 0)
- XTREG(79, 316, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1,
- 0, 0, 0, 0, 0, 0)
- XTREG(80, 320, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2,
- 0, 0, 0, 0, 0, 0)
- XTREG(81, 324, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3,
- 0, 0, 0, 0, 0, 0)
- XTREG(82, 328, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4,
- 0, 0, 0, 0, 0, 0)
- XTREG(83, 332, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5,
- 0, 0, 0, 0, 0, 0)
- XTREG(84, 336, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6,
- 0, 0, 0, 0, 0, 0)
- XTREG(85, 340, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7,
- 0, 0, 0, 0, 0, 0)
- XTREG(86, 344, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable,
- 0, 0, 0, 0, 0, 0)
- XTREG(87, 348, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt,
- 0, 0, 0, 0, 0, 0)
- XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset,
- 0, 0, 0, 0, 0, 0)
- XTREG(89, 356, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear,
- 0, 0, 0, 0, 0, 0)
- XTREG(90, 360, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable,
- 0, 0, 0, 0, 0, 0)
- XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase,
- 0, 0, 0, 0, 0, 0)
- XTREG(92, 368, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause,
- 0, 0, 0, 0, 0, 0)
- XTREG(93, 372, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause,
- 0, 0, 0, 0, 0, 0)
- XTREG(94, 376, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount,
- 0, 0, 0, 0, 0, 0)
- XTREG(95, 380, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid,
- 0, 0, 0, 0, 0, 0)
- XTREG(96, 384, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount,
- 0, 0, 0, 0, 0, 0)
- XTREG(97, 388, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel,
- 0, 0, 0, 0, 0, 0)
- XTREG(98, 392, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr,
- 0, 0, 0, 0, 0, 0)
- XTREG(99, 396, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0,
- 0, 0, 0, 0, 0, 0)
- XTREG(100, 400, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1,
- 0, 0, 0, 0, 0, 0)
- XTREG(101, 404, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2,
- 0, 0, 0, 0, 0, 0)
- XTREG(102, 408, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0,
- 0, 0, 0, 0, 0, 0)
- XTREG(103, 412, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1,
- 0, 0, 0, 0, 0, 0)
- XTREG(104, 416, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0,
- 0, 0, 0, 0, 0, 0)
- XTREG(105, 420, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1,
- 0, 0, 0, 0, 0, 0)
- XTREG(106, 424, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2,
- 0, 0, 0, 0, 0, 0)
- XTREG(107, 428, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3,
- 0, 0, 0, 0, 0, 0)
- XTREG(108, 432, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4,
- 0, 0, 0, 0, 0, 0)
- XTREG(109, 436, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5,
- 0, 0, 0, 0, 0, 0)
- XTREG(110, 440, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6,
- 0, 0, 0, 0, 0, 0)
- XTREG(111, 444, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7,
- 0, 0, 0, 0, 0, 0)
- XTREG(112, 448, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8,
- 0, 0, 0, 0, 0, 0)
- XTREG(113, 452, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9,
- 0, 0, 0, 0, 0, 0)
- XTREG(114, 456, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10,
- 0, 0, 0, 0, 0, 0)
- XTREG(115, 460, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11,
- 0, 0, 0, 0, 0, 0)
- XTREG(116, 464, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12,
- 0, 0, 0, 0, 0, 0)
- XTREG(117, 468, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13,
- 0, 0, 0, 0, 0, 0)
- XTREG(118, 472, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14,
- 0, 0, 0, 0, 0, 0)
- XTREG(119, 476, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15,
- 0, 0, 0, 0, 0, 0)
- XTREG_END
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+ Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#include "qemu/osdep.h"
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "ACCLO", 16, 0 },
+ { "ACCHI", 17, 0 },
+ { "M0", 32, 0 },
+ { "M1", 33, 0 },
+ { "M2", 34, 0 },
+ { "M3", 35, 0 },
+ { "PTEVADDR", 83, 0 },
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "176", 176, 0 },
+ { "208", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "LITBASE", 5, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "RASID", 90, 0 },
+ { "ITLBCFG", 91, 0 },
+ { "DTLBCFG", 92, 0 },
+ { "CPENABLE", 224, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "THREADPTR", 231, 1 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 70
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 231
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 15, 0 },
+ { "EPS3", 15, 0 },
+ { "EPS4", 15, 0 },
+ { "EPS5", 15, 0 },
+ { "EPS6", 15, 0 },
+ { "EPS7", 15, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSRING", 2, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "THREADPTR", 32, 0 },
+ { "LITBADDR", 20, 0 },
+ { "LITBEN", 1, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "ACC", 40, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "ASID3", 8, 0 },
+ { "ASID2", 8, 0 },
+ { "ASID1", 8, 0 },
+ { "INSTPGSZID4", 2, 0 },
+ { "DATAPGSZID4", 2, 0 },
+ { "PTBASE", 10, 0 },
+ { "CPENABLE", 8, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 73
+
+/* Macros for xtensa_state numbers (for use in iclasses because the
+ state numbers are not available when the iclass table is generated). */
+
+#define STATE_LCOUNT 0
+#define STATE_PC 1
+#define STATE_ICOUNT 2
+#define STATE_DDR 3
+#define STATE_INTERRUPT 4
+#define STATE_CCOUNT 5
+#define STATE_XTSYNC 6
+#define STATE_VECBASE 7
+#define STATE_EPC1 8
+#define STATE_EPC2 9
+#define STATE_EPC3 10
+#define STATE_EPC4 11
+#define STATE_EPC5 12
+#define STATE_EPC6 13
+#define STATE_EPC7 14
+#define STATE_EXCSAVE1 15
+#define STATE_EXCSAVE2 16
+#define STATE_EXCSAVE3 17
+#define STATE_EXCSAVE4 18
+#define STATE_EXCSAVE5 19
+#define STATE_EXCSAVE6 20
+#define STATE_EXCSAVE7 21
+#define STATE_EPS2 22
+#define STATE_EPS3 23
+#define STATE_EPS4 24
+#define STATE_EPS5 25
+#define STATE_EPS6 26
+#define STATE_EPS7 27
+#define STATE_EXCCAUSE 28
+#define STATE_PSINTLEVEL 29
+#define STATE_PSUM 30
+#define STATE_PSWOE 31
+#define STATE_PSRING 32
+#define STATE_PSEXCM 33
+#define STATE_DEPC 34
+#define STATE_EXCVADDR 35
+#define STATE_WindowBase 36
+#define STATE_WindowStart 37
+#define STATE_PSCALLINC 38
+#define STATE_PSOWB 39
+#define STATE_LBEG 40
+#define STATE_LEND 41
+#define STATE_SAR 42
+#define STATE_THREADPTR 43
+#define STATE_LITBADDR 44
+#define STATE_LITBEN 45
+#define STATE_MISC0 46
+#define STATE_MISC1 47
+#define STATE_ACC 48
+#define STATE_InOCDMode 49
+#define STATE_INTENABLE 50
+#define STATE_DBREAKA0 51
+#define STATE_DBREAKC0 52
+#define STATE_DBREAKA1 53
+#define STATE_DBREAKC1 54
+#define STATE_IBREAKA0 55
+#define STATE_IBREAKA1 56
+#define STATE_IBREAKENABLE 57
+#define STATE_ICOUNTLEVEL 58
+#define STATE_DEBUGCAUSE 59
+#define STATE_DBNUM 60
+#define STATE_CCOMPARE0 61
+#define STATE_CCOMPARE1 62
+#define STATE_CCOMPARE2 63
+#define STATE_ASID3 64
+#define STATE_ASID2 65
+#define STATE_ASID1 66
+#define STATE_INSTPGSZID4 67
+#define STATE_DATAPGSZID4 68
+#define STATE_PTBASE 69
+#define STATE_CPENABLE 70
+#define STATE_SCOMPARE1 71
+#define STATE_EXPSTATE 72
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+\f
+/* Functional units. */
+
+static xtensa_funcUnit_internal funcUnits[] = {
+
+};
+
+\f
+/* Register files. */
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", 0, 32, 32 },
+ { "MR", "m", 1, 32, 4 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "IMPWIRE", 32, 0, 0, 'i' }
+};
+
+\f
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+Operand_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_0, offset_0;
+ offset_0 = *valp & 0x3ffff;
+ soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_encode (uint32 *valp)
+{
+ unsigned offset_0, soffsetx4_0;
+ soffsetx4_0 = *valp;
+ offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = offset_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_0, imm12_0;
+ imm12_0 = *valp & 0xfff;
+ uimm12x8_0 = imm12_0 << 3;
+ *valp = uimm12x8_0;
+ return 0;
+}
+
+static int
+Operand_uimm12x8_encode (uint32 *valp)
+{
+ unsigned imm12_0, uimm12x8_0;
+ uimm12x8_0 = *valp;
+ imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
+ *valp = imm12_0;
+ return 0;
+}
+
+static int
+Operand_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_0, mn_0;
+ mn_0 = *valp & 0xf;
+ simm4_0 = ((int) mn_0 << 28) >> 28;
+ *valp = simm4_0;
+ return 0;
+}
+
+static int
+Operand_simm4_encode (uint32 *valp)
+{
+ unsigned mn_0, simm4_0;
+ simm4_0 = *valp;
+ mn_0 = (simm4_0 & 0xf);
+ *valp = mn_0;
+ return 0;
+}
+
+static int
+Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_arr_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ars_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_art_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar0_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar4_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar8_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar12_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ars_entry_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_0, r_0;
+ r_0 = *valp & 0xf;
+ immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
+ *valp = immrx4_0;
+ return 0;
+}
+
+static int
+Operand_immrx4_encode (uint32 *valp)
+{
+ unsigned r_0, immrx4_0;
+ immrx4_0 = *valp;
+ r_0 = ((immrx4_0 >> 2) & 0xf);
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_0, r_0;
+ r_0 = *valp & 0xf;
+ lsi4x4_0 = r_0 << 2;
+ *valp = lsi4x4_0;
+ return 0;
+}
+
+static int
+Operand_lsi4x4_encode (uint32 *valp)
+{
+ unsigned r_0, lsi4x4_0;
+ lsi4x4_0 = *valp;
+ r_0 = ((lsi4x4_0 >> 2) & 0xf);
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_0, imm7_0;
+ imm7_0 = *valp & 0x7f;
+ simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
+ *valp = simm7_0;
+ return 0;
+}
+
+static int
+Operand_simm7_encode (uint32 *valp)
+{
+ unsigned imm7_0, simm7_0;
+ simm7_0 = *valp;
+ imm7_0 = (simm7_0 & 0x7f);
+ *valp = imm7_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_0, imm6_0;
+ imm6_0 = *valp & 0x3f;
+ uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
+ *valp = uimm6_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_encode (uint32 *valp)
+{
+ unsigned imm6_0, uimm6_0;
+ uimm6_0 = *valp;
+ imm6_0 = (uimm6_0 - 0x4) & 0x3f;
+ *valp = imm6_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_0, t_0;
+ t_0 = *valp & 0xf;
+ ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
+ *valp = ai4const_0;
+ return 0;
+}
+
+static int
+Operand_ai4const_encode (uint32 *valp)
+{
+ unsigned t_0, ai4const_0;
+ ai4const_0 = *valp;
+ switch (ai4const_0)
+ {
+ case 0xffffffff: t_0 = 0; break;
+ case 0x1: t_0 = 0x1; break;
+ case 0x2: t_0 = 0x2; break;
+ case 0x3: t_0 = 0x3; break;
+ case 0x4: t_0 = 0x4; break;
+ case 0x5: t_0 = 0x5; break;
+ case 0x6: t_0 = 0x6; break;
+ case 0x7: t_0 = 0x7; break;
+ case 0x8: t_0 = 0x8; break;
+ case 0x9: t_0 = 0x9; break;
+ case 0xa: t_0 = 0xa; break;
+ case 0xb: t_0 = 0xb; break;
+ case 0xc: t_0 = 0xc; break;
+ case 0xd: t_0 = 0xd; break;
+ case 0xe: t_0 = 0xe; break;
+ default: t_0 = 0xf; break;
+ }
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_0, r_0;
+ r_0 = *valp & 0xf;
+ b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
+ *valp = b4const_0;
+ return 0;
+}
+
+static int
+Operand_b4const_encode (uint32 *valp)
+{
+ unsigned r_0, b4const_0;
+ b4const_0 = *valp;
+ switch (b4const_0)
+ {
+ case 0xffffffff: r_0 = 0; break;
+ case 0x1: r_0 = 0x1; break;
+ case 0x2: r_0 = 0x2; break;
+ case 0x3: r_0 = 0x3; break;
+ case 0x4: r_0 = 0x4; break;
+ case 0x5: r_0 = 0x5; break;
+ case 0x6: r_0 = 0x6; break;
+ case 0x7: r_0 = 0x7; break;
+ case 0x8: r_0 = 0x8; break;
+ case 0xa: r_0 = 0x9; break;
+ case 0xc: r_0 = 0xa; break;
+ case 0x10: r_0 = 0xb; break;
+ case 0x20: r_0 = 0xc; break;
+ case 0x40: r_0 = 0xd; break;
+ case 0x80: r_0 = 0xe; break;
+ default: r_0 = 0xf; break;
+ }
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_0, r_0;
+ r_0 = *valp & 0xf;
+ b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
+ *valp = b4constu_0;
+ return 0;
+}
+
+static int
+Operand_b4constu_encode (uint32 *valp)
+{
+ unsigned r_0, b4constu_0;
+ b4constu_0 = *valp;
+ switch (b4constu_0)
+ {
+ case 0x8000: r_0 = 0; break;
+ case 0x10000: r_0 = 0x1; break;
+ case 0x2: r_0 = 0x2; break;
+ case 0x3: r_0 = 0x3; break;
+ case 0x4: r_0 = 0x4; break;
+ case 0x5: r_0 = 0x5; break;
+ case 0x6: r_0 = 0x6; break;
+ case 0x7: r_0 = 0x7; break;
+ case 0x8: r_0 = 0x8; break;
+ case 0xa: r_0 = 0x9; break;
+ case 0xc: r_0 = 0xa; break;
+ case 0x10: r_0 = 0xb; break;
+ case 0x20: r_0 = 0xc; break;
+ case 0x40: r_0 = 0xd; break;
+ case 0x80: r_0 = 0xe; break;
+ default: r_0 = 0xf; break;
+ }
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8_0 = imm8_0;
+ *valp = uimm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8_0;
+ uimm8_0 = *valp;
+ imm8_0 = (uimm8_0 & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8x2_0 = imm8_0 << 1;
+ *valp = uimm8x2_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x2_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8x2_0;
+ uimm8x2_0 = *valp;
+ imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8x4_0 = imm8_0 << 2;
+ *valp = uimm8x4_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x4_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8x4_0;
+ uimm8x4_0 = *valp;
+ imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_0, op2_0;
+ op2_0 = *valp & 0xf;
+ uimm4x16_0 = op2_0 << 4;
+ *valp = uimm4x16_0;
+ return 0;
+}
+
+static int
+Operand_uimm4x16_encode (uint32 *valp)
+{
+ unsigned op2_0, uimm4x16_0;
+ uimm4x16_0 = *valp;
+ op2_0 = ((uimm4x16_0 >> 4) & 0xf);
+ *valp = op2_0;
+ return 0;
+}
+
+static int
+Operand_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ simm8_0 = ((int) imm8_0 << 24) >> 24;
+ *valp = simm8_0;
+ return 0;
+}
+
+static int
+Operand_simm8_encode (uint32 *valp)
+{
+ unsigned imm8_0, simm8_0;
+ simm8_0 = *valp;
+ imm8_0 = (simm8_0 & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
+ *valp = simm8x256_0;
+ return 0;
+}
+
+static int
+Operand_simm8x256_encode (uint32 *valp)
+{
+ unsigned imm8_0, simm8x256_0;
+ simm8x256_0 = *valp;
+ imm8_0 = ((simm8x256_0 >> 8) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_0, imm12b_0;
+ imm12b_0 = *valp & 0xfff;
+ simm12b_0 = ((int) imm12b_0 << 20) >> 20;
+ *valp = simm12b_0;
+ return 0;
+}
+
+static int
+Operand_simm12b_encode (uint32 *valp)
+{
+ unsigned imm12b_0, simm12b_0;
+ simm12b_0 = *valp;
+ imm12b_0 = (simm12b_0 & 0xfff);
+ *valp = imm12b_0;
+ return 0;
+}
+
+static int
+Operand_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_0, sal_0;
+ sal_0 = *valp & 0x1f;
+ msalp32_0 = 0x20 - sal_0;
+ *valp = msalp32_0;
+ return 0;
+}
+
+static int
+Operand_msalp32_encode (uint32 *valp)
+{
+ unsigned sal_0, msalp32_0;
+ msalp32_0 = *valp;
+ sal_0 = (0x20 - msalp32_0) & 0x1f;
+ *valp = sal_0;
+ return 0;
+}
+
+static int
+Operand_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_0, op2_0;
+ op2_0 = *valp & 0xf;
+ op2p1_0 = op2_0 + 0x1;
+ *valp = op2p1_0;
+ return 0;
+}
+
+static int
+Operand_op2p1_encode (uint32 *valp)
+{
+ unsigned op2_0, op2p1_0;
+ op2p1_0 = *valp;
+ op2_0 = (op2p1_0 - 0x1) & 0xf;
+ *valp = op2_0;
+ return 0;
+}
+
+static int
+Operand_label8_decode (uint32 *valp)
+{
+ unsigned label8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
+ *valp = label8_0;
+ return 0;
+}
+
+static int
+Operand_label8_encode (uint32 *valp)
+{
+ unsigned imm8_0, label8_0;
+ label8_0 = *valp;
+ imm8_0 = (label8_0 - 0x4) & 0xff;
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
+ *valp = ulabel8_0;
+ return 0;
+}
+
+static int
+Operand_ulabel8_encode (uint32 *valp)
+{
+ unsigned imm8_0, ulabel8_0;
+ ulabel8_0 = *valp;
+ imm8_0 = (ulabel8_0 - 0x4) & 0xff;
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_decode (uint32 *valp)
+{
+ unsigned label12_0, imm12_0;
+ imm12_0 = *valp & 0xfff;
+ label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
+ *valp = label12_0;
+ return 0;
+}
+
+static int
+Operand_label12_encode (uint32 *valp)
+{
+ unsigned imm12_0, label12_0;
+ label12_0 = *valp;
+ imm12_0 = (label12_0 - 0x4) & 0xfff;
+ *valp = imm12_0;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_0, offset_0;
+ offset_0 = *valp & 0x3ffff;
+ soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
+ *valp = soffset_0;
+ return 0;
+}
+
+static int
+Operand_soffset_encode (uint32 *valp)
+{
+ unsigned offset_0, soffset_0;
+ soffset_0 = *valp;
+ offset_0 = (soffset_0 - 0x4) & 0x3ffff;
+ *valp = offset_0;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_0, imm16_0;
+ imm16_0 = *valp & 0xffff;
+ uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
+ *valp = uimm16x4_0;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_encode (uint32 *valp)
+{
+ unsigned imm16_0, uimm16x4_0;
+ uimm16x4_0 = *valp;
+ imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
+ *valp = imm16_0;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mx_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_my_decode (uint32 *valp)
+{
+ *valp += 2;
+ return 0;
+}
+
+static int
+Operand_my_encode (uint32 *valp)
+{
+ int error;
+ error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+ *valp = *valp & 1;
+ return error;
+}
+
+static int
+Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mw_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr0_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr1_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr2_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr3_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_immt_decode (uint32 *valp)
+{
+ unsigned immt_0, t_0;
+ t_0 = *valp & 0xf;
+ immt_0 = t_0;
+ *valp = immt_0;
+ return 0;
+}
+
+static int
+Operand_immt_encode (uint32 *valp)
+{
+ unsigned t_0, immt_0;
+ immt_0 = *valp;
+ t_0 = immt_0 & 0xf;
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_imms_decode (uint32 *valp)
+{
+ unsigned imms_0, s_0;
+ s_0 = *valp & 0xf;
+ imms_0 = s_0;
+ *valp = imms_0;
+ return 0;
+}
+
+static int
+Operand_imms_encode (uint32 *valp)
+{
+ unsigned s_0, imms_0;
+ imms_0 = *valp;
+ s_0 = imms_0 & 0xf;
+ *valp = s_0;
+ return 0;
+}
+
+static int
+Operand_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_0, t_0;
+ t_0 = *valp & 0xf;
+ tp7_0 = t_0 + 0x7;
+ *valp = tp7_0;
+ return 0;
+}
+
+static int
+Operand_tp7_encode (uint32 *valp)
+{
+ unsigned t_0, tp7_0;
+ tp7_0 = *valp;
+ t_0 = (tp7_0 - 0x7) & 0xf;
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
+ xt_wbr15_imm_0 = *valp & 0x7fff;
+ xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
+ *valp = xt_wbr15_label_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
+ xt_wbr15_label_0 = *valp;
+ xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_imm_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
+ xt_wbr18_imm_0 = *valp & 0x3ffff;
+ xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
+ *valp = xt_wbr18_label_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
+ xt_wbr18_label_0 = *valp;
+ xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
+ *valp = xt_wbr18_imm_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", 10, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_soffsetx4_encode, Operand_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", 3, -1, 0,
+ 0,
+ Operand_uimm12x8_encode, Operand_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", 26, -1, 0,
+ 0,
+ Operand_simm4_encode, Operand_simm4_decode,
+ 0, 0 },
+ { "arr", 14, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_arr_encode, Operand_arr_decode,
+ 0, 0 },
+ { "ars", 5, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_ars_encode, Operand_ars_decode,
+ 0, 0 },
+ { "*ars_invisible", 5, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ars_encode, Operand_ars_decode,
+ 0, 0 },
+ { "art", 0, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_art_encode, Operand_art_decode,
+ 0, 0 },
+ { "ar0", 48, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar0_encode, Operand_ar0_decode,
+ 0, 0 },
+ { "ar4", 49, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar4_encode, Operand_ar4_decode,
+ 0, 0 },
+ { "ar8", 50, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar8_encode, Operand_ar8_decode,
+ 0, 0 },
+ { "ar12", 51, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar12_encode, Operand_ar12_decode,
+ 0, 0 },
+ { "ars_entry", 5, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_ars_entry_encode, Operand_ars_entry_decode,
+ 0, 0 },
+ { "immrx4", 14, -1, 0,
+ 0,
+ Operand_immrx4_encode, Operand_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", 14, -1, 0,
+ 0,
+ Operand_lsi4x4_encode, Operand_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", 34, -1, 0,
+ 0,
+ Operand_simm7_encode, Operand_simm7_decode,
+ 0, 0 },
+ { "uimm6", 33, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_uimm6_encode, Operand_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", 0, -1, 0,
+ 0,
+ Operand_ai4const_encode, Operand_ai4const_decode,
+ 0, 0 },
+ { "b4const", 14, -1, 0,
+ 0,
+ Operand_b4const_encode, Operand_b4const_decode,
+ 0, 0 },
+ { "b4constu", 14, -1, 0,
+ 0,
+ Operand_b4constu_encode, Operand_b4constu_decode,
+ 0, 0 },
+ { "uimm8", 4, -1, 0,
+ 0,
+ Operand_uimm8_encode, Operand_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", 4, -1, 0,
+ 0,
+ Operand_uimm8x2_encode, Operand_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", 4, -1, 0,
+ 0,
+ Operand_uimm8x4_encode, Operand_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", 13, -1, 0,
+ 0,
+ Operand_uimm4x16_encode, Operand_uimm4x16_decode,
+ 0, 0 },
+ { "simm8", 4, -1, 0,
+ 0,
+ Operand_simm8_encode, Operand_simm8_decode,
+ 0, 0 },
+ { "simm8x256", 4, -1, 0,
+ 0,
+ Operand_simm8x256_encode, Operand_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", 6, -1, 0,
+ 0,
+ Operand_simm12b_encode, Operand_simm12b_decode,
+ 0, 0 },
+ { "msalp32", 18, -1, 0,
+ 0,
+ Operand_msalp32_encode, Operand_msalp32_decode,
+ 0, 0 },
+ { "op2p1", 13, -1, 0,
+ 0,
+ Operand_op2p1_encode, Operand_op2p1_decode,
+ 0, 0 },
+ { "label8", 4, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_label8_encode, Operand_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", 4, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_ulabel8_encode, Operand_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", 3, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_label12_encode, Operand_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", 10, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_soffset_encode, Operand_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", 7, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_uimm16x4_encode, Operand_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "mx", 43, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ Operand_mx_encode, Operand_mx_decode,
+ 0, 0 },
+ { "my", 42, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ Operand_my_encode, Operand_my_decode,
+ 0, 0 },
+ { "mw", 41, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_mw_encode, Operand_mw_decode,
+ 0, 0 },
+ { "mr0", 52, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr0_encode, Operand_mr0_decode,
+ 0, 0 },
+ { "mr1", 53, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr1_encode, Operand_mr1_decode,
+ 0, 0 },
+ { "mr2", 54, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr2_encode, Operand_mr2_decode,
+ 0, 0 },
+ { "mr3", 55, 1, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr3_encode, Operand_mr3_decode,
+ 0, 0 },
+ { "immt", 0, -1, 0,
+ 0,
+ Operand_immt_encode, Operand_immt_decode,
+ 0, 0 },
+ { "imms", 5, -1, 0,
+ 0,
+ Operand_imms_encode, Operand_imms_decode,
+ 0, 0 },
+ { "tp7", 0, -1, 0,
+ 0,
+ Operand_tp7_encode, Operand_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", 44, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", 45, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
+ { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
+ { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
+ { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
+ { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
+ { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
+ { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
+ { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
+ { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
+ { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
+ { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
+ { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 },
+ { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 10 /* ar12 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 9 /* ar8 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 8 /* ar4 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 10 /* ar12 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 9 /* ar8 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 8 /* ar4 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { 11 /* ars_entry */ }, 's' },
+ { { 4 /* ars */ }, 'i' },
+ { { 1 /* uimm12x8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { 2 /* simm4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { 5 /* *ars_invisible */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 12 /* immrx4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 12 /* immrx4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 16 /* ai4const */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 15 /* uimm6 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 13 /* lsi4x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { 4 /* ars */ }, 'o' },
+ { { 14 /* simm7 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { 5 /* *ars_invisible */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 13 /* lsi4x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+ { { 3 /* arr */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 23 /* simm8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 24 /* simm8x256 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 17 /* b4const */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 47 /* bbi */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 18 /* b4constu */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 30 /* label12 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 7 /* ar0 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 7 /* ar0 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' },
+ { { 62 /* sae */ }, 'i' },
+ { { 27 /* op2p1 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { 31 /* soffset */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 20 /* uimm8x2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 20 /* uimm8x2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 32 /* uimm16x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 19 /* uimm8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 29 /* ulabel8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 29 /* ulabel8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 25 /* simm12b */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { 3 /* arr */ }, 'm' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { 5 /* *ars_invisible */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 20 /* uimm8x2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 19 /* uimm8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { 66 /* sas */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 26 /* msalp32 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' },
+ { { 64 /* sargt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' },
+ { { 50 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 50 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'o' },
+ { { STATE_LITBEN }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'm' },
+ { { STATE_LITBEN }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 34 /* my */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+ { { 33 /* mx */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+ { { 33 /* mx */ }, 'i' },
+ { { 34 /* my */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 34 /* my */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+ { { 33 /* mx */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+ { { 33 /* mx */ }, 'i' },
+ { { 34 /* my */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+ { { 35 /* mw */ }, 'o' },
+ { { 4 /* ars */ }, 'm' },
+ { { 33 /* mx */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+ { { 35 /* mw */ }, 'o' },
+ { { 4 /* ars */ }, 'm' },
+ { { 33 /* mx */ }, 'i' },
+ { { 34 /* my */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+ { { 35 /* mw */ }, 'o' },
+ { { 4 /* ars */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 36 /* mr0 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 36 /* mr0 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+ { { 6 /* art */ }, 'm' },
+ { { 36 /* mr0 */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 37 /* mr1 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 37 /* mr1 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+ { { 6 /* art */ }, 'm' },
+ { { 37 /* mr1 */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 38 /* mr2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 38 /* mr2 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+ { { 6 /* art */ }, 'm' },
+ { { 38 /* mr2 */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 39 /* mr3 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 39 /* mr3 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+ { { 6 /* art */ }, 'm' },
+ { { 39 /* mr3 */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { 50 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { 50 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { 41 /* imms */ }, 'i' },
+ { { 40 /* immt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { 41 /* imms */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { 41 /* imms */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 22 /* uimm4x16 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 22 /* uimm4x16 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 22 /* uimm4x16 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'm' },
+ { { STATE_EXCVADDR }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'i' },
+ { { STATE_ASID2 }, 'i' },
+ { { STATE_ASID1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'o' },
+ { { STATE_ASID2 }, 'o' },
+ { { STATE_ASID1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'm' },
+ { { STATE_ASID2 }, 'm' },
+ { { STATE_ASID1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 42 /* tp7 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 42 /* tp7 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { 6 /* art */ }, 'm' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { 3 /* arr */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ 0 /* IMPWIRE */
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { 91 /* bitindex */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { 91 /* bitindex */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_threadptr_args,
+ 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_threadptr_args,
+ 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_176_args,
+ 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_208_args,
+ 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_aa_args,
+ 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_ad_args,
+ 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_da_args,
+ 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_dd_args,
+ 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_aa_args,
+ 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_ad_args,
+ 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_da_args,
+ 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_dd_args,
+ 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_da_args,
+ 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_dd_args,
+ 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_l_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_mul16_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m3_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acclo_args,
+ 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acclo_args,
+ 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acclo_args,
+ 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acchi_args,
+ 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acchi_args,
+ 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acchi_args,
+ 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_lock_args,
+ 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_lock_args,
+ 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
+ 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_rasid_args,
+ 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_rasid_args,
+ 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_rasid_args,
+ 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_ldpte */,
+ 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwitlba */,
+ 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwdtlba */,
+ 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_cpenable_args,
+ 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_cpenable_args,
+ 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_cpenable_args,
+ 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_expstate_args,
+ 2, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 2, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70c2;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e2;
+}
+
+static void
+Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70d2;
+}
+
+static void
+Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270d2;
+}
+
+static void
+Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370d2;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f2;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf10000;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf12000;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11000;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13000;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7042;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7052;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x47082;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x57082;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7062;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7072;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7002;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7012;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7022;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7032;
+}
+
+static void
+Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7082;
+}
+
+static void
+Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x27082;
+}
+
+static void
+Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x37082;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf19000;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf18000;
+}
+
+static void
+Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135300;
+}
+
+static void
+Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35300;
+}
+
+static void
+Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615300;
+}
+
+static void
+Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35a00;
+}
+
+static void
+Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135a00;
+}
+
+static void
+Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615a00;
+}
+
+static void
+Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35b00;
+}
+
+static void
+Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135b00;
+}
+
+static void
+Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615b00;
+}
+
+static void
+Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35c00;
+}
+
+static void
+Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135c00;
+}
+
+static void
+Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615c00;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1f000;
+}
+
+static void
+Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x501000;
+}
+
+static void
+Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x509000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe2000;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+ Opcode_rur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+ Opcode_wur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
+ Opcode_rsr_176_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
+ Opcode_rsr_208_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+ Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+ Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+ Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+ Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+ Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+ Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+ Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+ Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+ Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+ Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+ Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+ Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+ Opcode_mul_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+ Opcode_mul_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+ Opcode_mul_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+ Opcode_mul_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+ Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+ Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+ Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+ Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+ Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+ Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+ Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+ Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+ Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+ Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+ Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+ Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+ Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+ Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+ Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+ Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+ Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+ Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+ Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+ Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+ Opcode_mula_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+ Opcode_mula_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+ Opcode_mula_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+ Opcode_mula_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+ Opcode_muls_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+ Opcode_muls_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+ Opcode_muls_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+ Opcode_muls_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+ Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+ Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+ Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+ Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+ Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+ Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+ Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+ Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+ Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+ Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+ Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+ Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+ Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+ Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+ Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+ Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+ Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+ Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+ Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+ Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+ Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+ Opcode_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+ Opcode_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+ Opcode_rsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+ Opcode_wsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+ Opcode_xsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+ Opcode_rsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+ Opcode_wsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+ Opcode_xsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+ Opcode_rsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+ Opcode_wsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+ Opcode_xsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+ Opcode_rsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+ Opcode_wsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+ Opcode_xsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+ Opcode_rsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+ Opcode_wsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+ Opcode_xsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+ Opcode_rsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+ Opcode_wsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+ Opcode_xsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
+ Opcode_ipfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
+ Opcode_ihu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
+ Opcode_iiu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
+ Opcode_dpfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
+ Opcode_dhu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
+ Opcode_diu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
+ Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
+ Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
+ Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
+ Opcode_rsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
+ Opcode_wsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
+ Opcode_xsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
+ Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
+ Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
+ Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
+ Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
+ Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
+ Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
+ Opcode_ldpte_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
+ Opcode_hwwitlba_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
+ Opcode_hwwdtlba_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+ Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+ Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+ Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+\f
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", 0 /* xt_iclass_excw */,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", 1 /* xt_iclass_rfe */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", 2 /* xt_iclass_rfde */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", 3 /* xt_iclass_syscall */,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "simcall", 4 /* xt_iclass_simcall */,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "call12", 5 /* xt_iclass_call12 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", 6 /* xt_iclass_call8 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", 7 /* xt_iclass_call4 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", 8 /* xt_iclass_callx12 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", 9 /* xt_iclass_callx8 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", 10 /* xt_iclass_callx4 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", 11 /* xt_iclass_entry */,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", 12 /* xt_iclass_movsp */,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", 13 /* xt_iclass_rotw */,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", 14 /* xt_iclass_retw */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", 14 /* xt_iclass_retw */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", 15 /* xt_iclass_rfwou */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", 15 /* xt_iclass_rfwou */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", 16 /* xt_iclass_l32e */,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", 17 /* xt_iclass_s32e */,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", 24 /* xt_iclass_add.n */,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", 25 /* xt_iclass_addi.n */,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", 26 /* xt_iclass_bz6 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", 26 /* xt_iclass_bz6 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", 27 /* xt_iclass_ill.n */,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", 28 /* xt_iclass_loadi4 */,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", 29 /* xt_iclass_mov.n */,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", 30 /* xt_iclass_movi.n */,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", 31 /* xt_iclass_nopn */,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", 32 /* xt_iclass_retn */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", 33 /* xt_iclass_storei4 */,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "rur.threadptr", 34 /* rur_threadptr */,
+ 0,
+ Opcode_rur_threadptr_encode_fns, 0, 0 },
+ { "wur.threadptr", 35 /* wur_threadptr */,
+ 0,
+ Opcode_wur_threadptr_encode_fns, 0, 0 },
+ { "addi", 36 /* xt_iclass_addi */,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", 37 /* xt_iclass_addmi */,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", 38 /* xt_iclass_addsub */,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", 39 /* xt_iclass_bit */,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", 39 /* xt_iclass_bit */,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", 39 /* xt_iclass_bit */,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", 40 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", 40 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", 40 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", 40 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", 41 /* xt_iclass_bsi8b */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", 41 /* xt_iclass_bsi8b */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", 42 /* xt_iclass_bsi8u */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", 42 /* xt_iclass_bsi8u */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", 43 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", 44 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", 44 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", 44 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", 44 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", 45 /* xt_iclass_call0 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", 46 /* xt_iclass_callx0 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", 47 /* xt_iclass_exti */,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", 48 /* xt_iclass_ill */,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", 49 /* xt_iclass_jump */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", 50 /* xt_iclass_jumpx */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", 51 /* xt_iclass_l16ui */,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", 52 /* xt_iclass_l16si */,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", 53 /* xt_iclass_l32i */,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", 54 /* xt_iclass_l32r */,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", 55 /* xt_iclass_l8i */,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", 56 /* xt_iclass_loop */,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", 57 /* xt_iclass_loopz */,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", 57 /* xt_iclass_loopz */,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", 58 /* xt_iclass_movi */,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", 59 /* xt_iclass_movz */,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", 59 /* xt_iclass_movz */,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", 59 /* xt_iclass_movz */,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", 59 /* xt_iclass_movz */,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", 60 /* xt_iclass_neg */,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", 60 /* xt_iclass_neg */,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", 61 /* xt_iclass_nop */,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", 62 /* xt_iclass_return */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "s16i", 63 /* xt_iclass_s16i */,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", 64 /* xt_iclass_s32i */,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s8i", 65 /* xt_iclass_s8i */,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", 66 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", 66 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", 66 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", 66 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", 67 /* xt_iclass_sari */,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", 68 /* xt_iclass_shifts */,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", 69 /* xt_iclass_shiftst */,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", 70 /* xt_iclass_shiftt */,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", 70 /* xt_iclass_shiftt */,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", 71 /* xt_iclass_slli */,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", 72 /* xt_iclass_srai */,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", 73 /* xt_iclass_srli */,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", 74 /* xt_iclass_memw */,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", 75 /* xt_iclass_extw */,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", 76 /* xt_iclass_isync */,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", 77 /* xt_iclass_sync */,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", 77 /* xt_iclass_sync */,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", 77 /* xt_iclass_sync */,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", 78 /* xt_iclass_rsil */,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.176", 94 /* xt_iclass_rsr.176 */,
+ 0,
+ Opcode_rsr_176_encode_fns, 0, 0 },
+ { "rsr.208", 95 /* xt_iclass_rsr.208 */,
+ 0,
+ Opcode_rsr_208_encode_fns, 0, 0 },
+ { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", 174 /* xt_iclass_rsr.prid */,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_mul_aa_ll_encode_fns, 0, 0 },
+ { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_mul_aa_hl_encode_fns, 0, 0 },
+ { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_mul_aa_lh_encode_fns, 0, 0 },
+ { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_mul_aa_hh_encode_fns, 0, 0 },
+ { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_umul_aa_ll_encode_fns, 0, 0 },
+ { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_umul_aa_hl_encode_fns, 0, 0 },
+ { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_umul_aa_lh_encode_fns, 0, 0 },
+ { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */,
+ 0,
+ Opcode_umul_aa_hh_encode_fns, 0, 0 },
+ { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */,
+ 0,
+ Opcode_mul_ad_ll_encode_fns, 0, 0 },
+ { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */,
+ 0,
+ Opcode_mul_ad_hl_encode_fns, 0, 0 },
+ { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */,
+ 0,
+ Opcode_mul_ad_lh_encode_fns, 0, 0 },
+ { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */,
+ 0,
+ Opcode_mul_ad_hh_encode_fns, 0, 0 },
+ { "mul.da.ll", 180 /* xt_iclass_mac16_da */,
+ 0,
+ Opcode_mul_da_ll_encode_fns, 0, 0 },
+ { "mul.da.hl", 180 /* xt_iclass_mac16_da */,
+ 0,
+ Opcode_mul_da_hl_encode_fns, 0, 0 },
+ { "mul.da.lh", 180 /* xt_iclass_mac16_da */,
+ 0,
+ Opcode_mul_da_lh_encode_fns, 0, 0 },
+ { "mul.da.hh", 180 /* xt_iclass_mac16_da */,
+ 0,
+ Opcode_mul_da_hh_encode_fns, 0, 0 },
+ { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */,
+ 0,
+ Opcode_mul_dd_ll_encode_fns, 0, 0 },
+ { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */,
+ 0,
+ Opcode_mul_dd_hl_encode_fns, 0, 0 },
+ { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */,
+ 0,
+ Opcode_mul_dd_lh_encode_fns, 0, 0 },
+ { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */,
+ 0,
+ Opcode_mul_dd_hh_encode_fns, 0, 0 },
+ { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_mula_aa_ll_encode_fns, 0, 0 },
+ { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_mula_aa_hl_encode_fns, 0, 0 },
+ { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_mula_aa_lh_encode_fns, 0, 0 },
+ { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_mula_aa_hh_encode_fns, 0, 0 },
+ { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_muls_aa_ll_encode_fns, 0, 0 },
+ { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_muls_aa_hl_encode_fns, 0, 0 },
+ { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_muls_aa_lh_encode_fns, 0, 0 },
+ { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */,
+ 0,
+ Opcode_muls_aa_hh_encode_fns, 0, 0 },
+ { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_mula_ad_ll_encode_fns, 0, 0 },
+ { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_mula_ad_hl_encode_fns, 0, 0 },
+ { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_mula_ad_lh_encode_fns, 0, 0 },
+ { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_mula_ad_hh_encode_fns, 0, 0 },
+ { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_muls_ad_ll_encode_fns, 0, 0 },
+ { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_muls_ad_hl_encode_fns, 0, 0 },
+ { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_muls_ad_lh_encode_fns, 0, 0 },
+ { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */,
+ 0,
+ Opcode_muls_ad_hh_encode_fns, 0, 0 },
+ { "mula.da.ll", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_mula_da_ll_encode_fns, 0, 0 },
+ { "mula.da.hl", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_mula_da_hl_encode_fns, 0, 0 },
+ { "mula.da.lh", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_mula_da_lh_encode_fns, 0, 0 },
+ { "mula.da.hh", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_mula_da_hh_encode_fns, 0, 0 },
+ { "muls.da.ll", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_muls_da_ll_encode_fns, 0, 0 },
+ { "muls.da.hl", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_muls_da_hl_encode_fns, 0, 0 },
+ { "muls.da.lh", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_muls_da_lh_encode_fns, 0, 0 },
+ { "muls.da.hh", 184 /* xt_iclass_mac16a_da */,
+ 0,
+ Opcode_muls_da_hh_encode_fns, 0, 0 },
+ { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_mula_dd_ll_encode_fns, 0, 0 },
+ { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_mula_dd_hl_encode_fns, 0, 0 },
+ { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_mula_dd_lh_encode_fns, 0, 0 },
+ { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_mula_dd_hh_encode_fns, 0, 0 },
+ { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_muls_dd_ll_encode_fns, 0, 0 },
+ { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_muls_dd_hl_encode_fns, 0, 0 },
+ { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_muls_dd_lh_encode_fns, 0, 0 },
+ { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */,
+ 0,
+ Opcode_muls_dd_hh_encode_fns, 0, 0 },
+ { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+ { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+ { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+ { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+ { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */,
+ 0,
+ Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+ { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */,
+ 0,
+ Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+ { "lddec", 188 /* xt_iclass_mac16_l */,
+ 0,
+ Opcode_lddec_encode_fns, 0, 0 },
+ { "ldinc", 188 /* xt_iclass_mac16_l */,
+ 0,
+ Opcode_ldinc_encode_fns, 0, 0 },
+ { "mul16u", 189 /* xt_iclass_mul16 */,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", 189 /* xt_iclass_mul16 */,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "rsr.m0", 190 /* xt_iclass_rsr.m0 */,
+ 0,
+ Opcode_rsr_m0_encode_fns, 0, 0 },
+ { "wsr.m0", 191 /* xt_iclass_wsr.m0 */,
+ 0,
+ Opcode_wsr_m0_encode_fns, 0, 0 },
+ { "xsr.m0", 192 /* xt_iclass_xsr.m0 */,
+ 0,
+ Opcode_xsr_m0_encode_fns, 0, 0 },
+ { "rsr.m1", 193 /* xt_iclass_rsr.m1 */,
+ 0,
+ Opcode_rsr_m1_encode_fns, 0, 0 },
+ { "wsr.m1", 194 /* xt_iclass_wsr.m1 */,
+ 0,
+ Opcode_wsr_m1_encode_fns, 0, 0 },
+ { "xsr.m1", 195 /* xt_iclass_xsr.m1 */,
+ 0,
+ Opcode_xsr_m1_encode_fns, 0, 0 },
+ { "rsr.m2", 196 /* xt_iclass_rsr.m2 */,
+ 0,
+ Opcode_rsr_m2_encode_fns, 0, 0 },
+ { "wsr.m2", 197 /* xt_iclass_wsr.m2 */,
+ 0,
+ Opcode_wsr_m2_encode_fns, 0, 0 },
+ { "xsr.m2", 198 /* xt_iclass_xsr.m2 */,
+ 0,
+ Opcode_xsr_m2_encode_fns, 0, 0 },
+ { "rsr.m3", 199 /* xt_iclass_rsr.m3 */,
+ 0,
+ Opcode_rsr_m3_encode_fns, 0, 0 },
+ { "wsr.m3", 200 /* xt_iclass_wsr.m3 */,
+ 0,
+ Opcode_wsr_m3_encode_fns, 0, 0 },
+ { "xsr.m3", 201 /* xt_iclass_xsr.m3 */,
+ 0,
+ Opcode_xsr_m3_encode_fns, 0, 0 },
+ { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */,
+ 0,
+ Opcode_rsr_acclo_encode_fns, 0, 0 },
+ { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */,
+ 0,
+ Opcode_wsr_acclo_encode_fns, 0, 0 },
+ { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */,
+ 0,
+ Opcode_xsr_acclo_encode_fns, 0, 0 },
+ { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */,
+ 0,
+ Opcode_rsr_acchi_encode_fns, 0, 0 },
+ { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */,
+ 0,
+ Opcode_wsr_acchi_encode_fns, 0, 0 },
+ { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */,
+ 0,
+ Opcode_xsr_acchi_encode_fns, 0, 0 },
+ { "rfi", 208 /* xt_iclass_rfi */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", 209 /* xt_iclass_wait */,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", 211 /* xt_iclass_wsr.intset */,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", 216 /* xt_iclass_break */,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", 217 /* xt_iclass_break.n */,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", 242 /* xt_iclass_rsr.icount */,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", 243 /* xt_iclass_wsr.icount */,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", 244 /* xt_iclass_xsr.icount */,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "rfdo", 251 /* xt_iclass_rfdo */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", 252 /* xt_iclass_rfdd */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "ipf", 266 /* xt_iclass_icache */,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", 266 /* xt_iclass_icache */,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "ipfl", 267 /* xt_iclass_icache_lock */,
+ 0,
+ Opcode_ipfl_encode_fns, 0, 0 },
+ { "ihu", 267 /* xt_iclass_icache_lock */,
+ 0,
+ Opcode_ihu_encode_fns, 0, 0 },
+ { "iiu", 267 /* xt_iclass_icache_lock */,
+ 0,
+ Opcode_iiu_encode_fns, 0, 0 },
+ { "iii", 268 /* xt_iclass_icache_inv */,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", 269 /* xt_iclass_licx */,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", 269 /* xt_iclass_licx */,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", 270 /* xt_iclass_sicx */,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", 270 /* xt_iclass_sicx */,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", 271 /* xt_iclass_dcache */,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", 271 /* xt_iclass_dcache */,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwb", 272 /* xt_iclass_dcache_ind */,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", 272 /* xt_iclass_dcache_ind */,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", 273 /* xt_iclass_dcache_inv */,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", 273 /* xt_iclass_dcache_inv */,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", 274 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", 274 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", 274 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", 274 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "dpfl", 275 /* xt_iclass_dcache_lock */,
+ 0,
+ Opcode_dpfl_encode_fns, 0, 0 },
+ { "dhu", 275 /* xt_iclass_dcache_lock */,
+ 0,
+ Opcode_dhu_encode_fns, 0, 0 },
+ { "diu", 275 /* xt_iclass_dcache_lock */,
+ 0,
+ Opcode_diu_encode_fns, 0, 0 },
+ { "sdct", 276 /* xt_iclass_sdct */,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", 277 /* xt_iclass_ldct */,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */,
+ 0,
+ Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */,
+ 0,
+ Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
+ { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */,
+ 0,
+ Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */,
+ 0,
+ Opcode_rsr_rasid_encode_fns, 0, 0 },
+ { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */,
+ 0,
+ Opcode_wsr_rasid_encode_fns, 0, 0 },
+ { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */,
+ 0,
+ Opcode_xsr_rasid_encode_fns, 0, 0 },
+ { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */,
+ 0,
+ Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
+ { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */,
+ 0,
+ Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
+ { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */,
+ 0,
+ Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
+ { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */,
+ 0,
+ Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
+ { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */,
+ 0,
+ Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
+ { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */,
+ 0,
+ Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
+ { "idtlb", 290 /* xt_iclass_idtlb */,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", 291 /* xt_iclass_rdtlb */,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", 291 /* xt_iclass_rdtlb */,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", 291 /* xt_iclass_rdtlb */,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", 292 /* xt_iclass_wdtlb */,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", 293 /* xt_iclass_iitlb */,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", 294 /* xt_iclass_ritlb */,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", 294 /* xt_iclass_ritlb */,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", 294 /* xt_iclass_ritlb */,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", 295 /* xt_iclass_witlb */,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "ldpte", 296 /* xt_iclass_ldpte */,
+ 0,
+ Opcode_ldpte_encode_fns, 0, 0 },
+ { "hwwitlba", 297 /* xt_iclass_hwwitlba */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_hwwitlba_encode_fns, 0, 0 },
+ { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */,
+ 0,
+ Opcode_hwwdtlba_encode_fns, 0, 0 },
+ { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */,
+ 0,
+ Opcode_rsr_cpenable_encode_fns, 0, 0 },
+ { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */,
+ 0,
+ Opcode_wsr_cpenable_encode_fns, 0, 0 },
+ { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */,
+ 0,
+ Opcode_xsr_cpenable_encode_fns, 0, 0 },
+ { "clamps", 302 /* xt_iclass_clamp */,
+ 0,
+ Opcode_clamps_encode_fns, 0, 0 },
+ { "min", 303 /* xt_iclass_minmax */,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", 303 /* xt_iclass_minmax */,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", 303 /* xt_iclass_minmax */,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", 303 /* xt_iclass_minmax */,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", 304 /* xt_iclass_nsa */,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", 304 /* xt_iclass_nsa */,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", 305 /* xt_iclass_sx */,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", 306 /* xt_iclass_l32ai */,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", 307 /* xt_iclass_s32ri */,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", 308 /* xt_iclass_s32c1i */,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "quou", 312 /* xt_iclass_div */,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", 312 /* xt_iclass_div */,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", 312 /* xt_iclass_div */,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", 312 /* xt_iclass_div */,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "mull", 313 /* xt_mul32 */,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "rur.expstate", 314 /* rur_expstate */,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", 315 /* wur_expstate */,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", 316 /* iclass_READ_IMPWIRE */,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return 79; /* ill */
+ break;
+ case 2:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 98; /* ret */
+ case 1:
+ return 14; /* retw */
+ case 2:
+ return 81; /* jx */
+ }
+ break;
+ case 3:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 77; /* callx0 */
+ case 1:
+ return 10; /* callx4 */
+ case 2:
+ return 9; /* callx8 */
+ case 3:
+ return 8; /* callx12 */
+ }
+ break;
+ }
+ break;
+ case 1:
+ return 12; /* movsp */
+ case 2:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ return 116; /* isync */
+ case 1:
+ return 117; /* rsync */
+ case 2:
+ return 118; /* esync */
+ case 3:
+ return 119; /* dsync */
+ case 8:
+ return 0; /* excw */
+ case 12:
+ return 114; /* memw */
+ case 13:
+ return 115; /* extw */
+ case 15:
+ return 97; /* nop */
+ }
+ }
+ break;
+ case 3:
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ return 1; /* rfe */
+ case 2:
+ return 2; /* rfde */
+ case 4:
+ return 16; /* rfwo */
+ case 5:
+ return 17; /* rfwu */
+ }
+ break;
+ case 1:
+ return 310; /* rfi */
+ }
+ break;
+ case 4:
+ return 318; /* break */
+ case 5:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 3; /* syscall */
+ break;
+ case 1:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 4; /* simcall */
+ break;
+ }
+ break;
+ case 6:
+ return 120; /* rsil */
+ case 7:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 311; /* waiti */
+ break;
+ }
+ break;
+ case 1:
+ return 49; /* and */
+ case 2:
+ return 50; /* or */
+ case 3:
+ return 51; /* xor */
+ case 4:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 102; /* ssr */
+ break;
+ case 1:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 103; /* ssl */
+ break;
+ case 2:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 104; /* ssa8l */
+ break;
+ case 3:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 105; /* ssa8b */
+ break;
+ case 4:
+ if (Field_thi3_Slot_inst_get (insn) == 0)
+ return 106; /* ssai */
+ break;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return 13; /* rotw */
+ break;
+ case 14:
+ return 426; /* nsa */
+ case 15:
+ return 427; /* nsau */
+ }
+ break;
+ case 5:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 1:
+ return 416; /* hwwitlba */
+ case 3:
+ return 412; /* ritlb0 */
+ case 4:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 410; /* iitlb */
+ break;
+ case 5:
+ return 411; /* pitlb */
+ case 6:
+ return 414; /* witlb */
+ case 7:
+ return 413; /* ritlb1 */
+ case 9:
+ return 417; /* hwwdtlba */
+ case 11:
+ return 407; /* rdtlb0 */
+ case 12:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 405; /* idtlb */
+ break;
+ case 13:
+ return 406; /* pdtlb */
+ case 14:
+ return 409; /* wdtlb */
+ case 15:
+ return 408; /* rdtlb1 */
+ }
+ break;
+ case 6:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ return 95; /* neg */
+ case 1:
+ return 96; /* abs */
+ }
+ break;
+ case 8:
+ return 41; /* add */
+ case 9:
+ return 43; /* addx2 */
+ case 10:
+ return 44; /* addx4 */
+ case 11:
+ return 45; /* addx8 */
+ case 12:
+ return 42; /* sub */
+ case 13:
+ return 46; /* subx2 */
+ case 14:
+ return 47; /* subx4 */
+ case 15:
+ return 48; /* subx8 */
+ }
+ break;
+ case 1:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ case 1:
+ return 111; /* slli */
+ case 2:
+ case 3:
+ return 112; /* srai */
+ case 4:
+ return 113; /* srli */
+ case 6:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return 129; /* xsr.lbeg */
+ case 1:
+ return 123; /* xsr.lend */
+ case 2:
+ return 126; /* xsr.lcount */
+ case 3:
+ return 132; /* xsr.sar */
+ case 5:
+ return 135; /* xsr.litbase */
+ case 12:
+ return 434; /* xsr.scompare1 */
+ case 16:
+ return 306; /* xsr.acclo */
+ case 17:
+ return 309; /* xsr.acchi */
+ case 32:
+ return 294; /* xsr.m0 */
+ case 33:
+ return 297; /* xsr.m1 */
+ case 34:
+ return 300; /* xsr.m2 */
+ case 35:
+ return 303; /* xsr.m3 */
+ case 72:
+ return 22; /* xsr.windowbase */
+ case 73:
+ return 25; /* xsr.windowstart */
+ case 83:
+ return 395; /* xsr.ptevaddr */
+ case 90:
+ return 398; /* xsr.rasid */
+ case 91:
+ return 401; /* xsr.itlbcfg */
+ case 92:
+ return 404; /* xsr.dtlbcfg */
+ case 96:
+ return 340; /* xsr.ibreakenable */
+ case 104:
+ return 352; /* xsr.ddr */
+ case 128:
+ return 334; /* xsr.ibreaka0 */
+ case 129:
+ return 337; /* xsr.ibreaka1 */
+ case 144:
+ return 322; /* xsr.dbreaka0 */
+ case 145:
+ return 328; /* xsr.dbreaka1 */
+ case 160:
+ return 325; /* xsr.dbreakc0 */
+ case 161:
+ return 331; /* xsr.dbreakc1 */
+ case 177:
+ return 143; /* xsr.epc1 */
+ case 178:
+ return 149; /* xsr.epc2 */
+ case 179:
+ return 155; /* xsr.epc3 */
+ case 180:
+ return 161; /* xsr.epc4 */
+ case 181:
+ return 167; /* xsr.epc5 */
+ case 182:
+ return 173; /* xsr.epc6 */
+ case 183:
+ return 179; /* xsr.epc7 */
+ case 192:
+ return 206; /* xsr.depc */
+ case 194:
+ return 185; /* xsr.eps2 */
+ case 195:
+ return 188; /* xsr.eps3 */
+ case 196:
+ return 191; /* xsr.eps4 */
+ case 197:
+ return 194; /* xsr.eps5 */
+ case 198:
+ return 197; /* xsr.eps6 */
+ case 199:
+ return 200; /* xsr.eps7 */
+ case 209:
+ return 146; /* xsr.excsave1 */
+ case 210:
+ return 152; /* xsr.excsave2 */
+ case 211:
+ return 158; /* xsr.excsave3 */
+ case 212:
+ return 164; /* xsr.excsave4 */
+ case 213:
+ return 170; /* xsr.excsave5 */
+ case 214:
+ return 176; /* xsr.excsave6 */
+ case 215:
+ return 182; /* xsr.excsave7 */
+ case 224:
+ return 420; /* xsr.cpenable */
+ case 228:
+ return 317; /* xsr.intenable */
+ case 230:
+ return 140; /* xsr.ps */
+ case 231:
+ return 219; /* xsr.vecbase */
+ case 232:
+ return 209; /* xsr.exccause */
+ case 233:
+ return 343; /* xsr.debugcause */
+ case 234:
+ return 358; /* xsr.ccount */
+ case 236:
+ return 346; /* xsr.icount */
+ case 237:
+ return 349; /* xsr.icountlevel */
+ case 238:
+ return 203; /* xsr.excvaddr */
+ case 240:
+ return 361; /* xsr.ccompare0 */
+ case 241:
+ return 364; /* xsr.ccompare1 */
+ case 242:
+ return 367; /* xsr.ccompare2 */
+ case 244:
+ return 212; /* xsr.misc0 */
+ case 245:
+ return 215; /* xsr.misc1 */
+ }
+ break;
+ case 8:
+ return 108; /* src */
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return 109; /* srl */
+ break;
+ case 10:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 107; /* sll */
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return 110; /* sra */
+ break;
+ case 12:
+ return 290; /* mul16u */
+ case 13:
+ return 291; /* mul16s */
+ case 15:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return 374; /* lict */
+ case 1:
+ return 376; /* sict */
+ case 2:
+ return 375; /* licw */
+ case 3:
+ return 377; /* sicw */
+ case 8:
+ return 392; /* ldct */
+ case 9:
+ return 391; /* sdct */
+ case 14:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 353; /* rfdo */
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return 354; /* rfdd */
+ break;
+ case 15:
+ return 415; /* ldpte */
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 8:
+ return 439; /* mull */
+ case 12:
+ return 435; /* quou */
+ case 13:
+ return 436; /* quos */
+ case 14:
+ return 437; /* remu */
+ case 15:
+ return 438; /* rems */
+ }
+ break;
+ case 3:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return 127; /* rsr.lbeg */
+ case 1:
+ return 121; /* rsr.lend */
+ case 2:
+ return 124; /* rsr.lcount */
+ case 3:
+ return 130; /* rsr.sar */
+ case 5:
+ return 133; /* rsr.litbase */
+ case 12:
+ return 432; /* rsr.scompare1 */
+ case 16:
+ return 304; /* rsr.acclo */
+ case 17:
+ return 307; /* rsr.acchi */
+ case 32:
+ return 292; /* rsr.m0 */
+ case 33:
+ return 295; /* rsr.m1 */
+ case 34:
+ return 298; /* rsr.m2 */
+ case 35:
+ return 301; /* rsr.m3 */
+ case 72:
+ return 20; /* rsr.windowbase */
+ case 73:
+ return 23; /* rsr.windowstart */
+ case 83:
+ return 394; /* rsr.ptevaddr */
+ case 90:
+ return 396; /* rsr.rasid */
+ case 91:
+ return 399; /* rsr.itlbcfg */
+ case 92:
+ return 402; /* rsr.dtlbcfg */
+ case 96:
+ return 338; /* rsr.ibreakenable */
+ case 104:
+ return 350; /* rsr.ddr */
+ case 128:
+ return 332; /* rsr.ibreaka0 */
+ case 129:
+ return 335; /* rsr.ibreaka1 */
+ case 144:
+ return 320; /* rsr.dbreaka0 */
+ case 145:
+ return 326; /* rsr.dbreaka1 */
+ case 160:
+ return 323; /* rsr.dbreakc0 */
+ case 161:
+ return 329; /* rsr.dbreakc1 */
+ case 176:
+ return 136; /* rsr.176 */
+ case 177:
+ return 141; /* rsr.epc1 */
+ case 178:
+ return 147; /* rsr.epc2 */
+ case 179:
+ return 153; /* rsr.epc3 */
+ case 180:
+ return 159; /* rsr.epc4 */
+ case 181:
+ return 165; /* rsr.epc5 */
+ case 182:
+ return 171; /* rsr.epc6 */
+ case 183:
+ return 177; /* rsr.epc7 */
+ case 192:
+ return 204; /* rsr.depc */
+ case 194:
+ return 183; /* rsr.eps2 */
+ case 195:
+ return 186; /* rsr.eps3 */
+ case 196:
+ return 189; /* rsr.eps4 */
+ case 197:
+ return 192; /* rsr.eps5 */
+ case 198:
+ return 195; /* rsr.eps6 */
+ case 199:
+ return 198; /* rsr.eps7 */
+ case 208:
+ return 137; /* rsr.208 */
+ case 209:
+ return 144; /* rsr.excsave1 */
+ case 210:
+ return 150; /* rsr.excsave2 */
+ case 211:
+ return 156; /* rsr.excsave3 */
+ case 212:
+ return 162; /* rsr.excsave4 */
+ case 213:
+ return 168; /* rsr.excsave5 */
+ case 214:
+ return 174; /* rsr.excsave6 */
+ case 215:
+ return 180; /* rsr.excsave7 */
+ case 224:
+ return 418; /* rsr.cpenable */
+ case 226:
+ return 312; /* rsr.interrupt */
+ case 228:
+ return 315; /* rsr.intenable */
+ case 230:
+ return 138; /* rsr.ps */
+ case 231:
+ return 217; /* rsr.vecbase */
+ case 232:
+ return 207; /* rsr.exccause */
+ case 233:
+ return 341; /* rsr.debugcause */
+ case 234:
+ return 356; /* rsr.ccount */
+ case 235:
+ return 216; /* rsr.prid */
+ case 236:
+ return 344; /* rsr.icount */
+ case 237:
+ return 347; /* rsr.icountlevel */
+ case 238:
+ return 201; /* rsr.excvaddr */
+ case 240:
+ return 359; /* rsr.ccompare0 */
+ case 241:
+ return 362; /* rsr.ccompare1 */
+ case 242:
+ return 365; /* rsr.ccompare2 */
+ case 244:
+ return 210; /* rsr.misc0 */
+ case 245:
+ return 213; /* rsr.misc1 */
+ }
+ break;
+ case 1:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return 128; /* wsr.lbeg */
+ case 1:
+ return 122; /* wsr.lend */
+ case 2:
+ return 125; /* wsr.lcount */
+ case 3:
+ return 131; /* wsr.sar */
+ case 5:
+ return 134; /* wsr.litbase */
+ case 12:
+ return 433; /* wsr.scompare1 */
+ case 16:
+ return 305; /* wsr.acclo */
+ case 17:
+ return 308; /* wsr.acchi */
+ case 32:
+ return 293; /* wsr.m0 */
+ case 33:
+ return 296; /* wsr.m1 */
+ case 34:
+ return 299; /* wsr.m2 */
+ case 35:
+ return 302; /* wsr.m3 */
+ case 72:
+ return 21; /* wsr.windowbase */
+ case 73:
+ return 24; /* wsr.windowstart */
+ case 83:
+ return 393; /* wsr.ptevaddr */
+ case 89:
+ return 355; /* wsr.mmid */
+ case 90:
+ return 397; /* wsr.rasid */
+ case 91:
+ return 400; /* wsr.itlbcfg */
+ case 92:
+ return 403; /* wsr.dtlbcfg */
+ case 96:
+ return 339; /* wsr.ibreakenable */
+ case 104:
+ return 351; /* wsr.ddr */
+ case 128:
+ return 333; /* wsr.ibreaka0 */
+ case 129:
+ return 336; /* wsr.ibreaka1 */
+ case 144:
+ return 321; /* wsr.dbreaka0 */
+ case 145:
+ return 327; /* wsr.dbreaka1 */
+ case 160:
+ return 324; /* wsr.dbreakc0 */
+ case 161:
+ return 330; /* wsr.dbreakc1 */
+ case 177:
+ return 142; /* wsr.epc1 */
+ case 178:
+ return 148; /* wsr.epc2 */
+ case 179:
+ return 154; /* wsr.epc3 */
+ case 180:
+ return 160; /* wsr.epc4 */
+ case 181:
+ return 166; /* wsr.epc5 */
+ case 182:
+ return 172; /* wsr.epc6 */
+ case 183:
+ return 178; /* wsr.epc7 */
+ case 192:
+ return 205; /* wsr.depc */
+ case 194:
+ return 184; /* wsr.eps2 */
+ case 195:
+ return 187; /* wsr.eps3 */
+ case 196:
+ return 190; /* wsr.eps4 */
+ case 197:
+ return 193; /* wsr.eps5 */
+ case 198:
+ return 196; /* wsr.eps6 */
+ case 199:
+ return 199; /* wsr.eps7 */
+ case 209:
+ return 145; /* wsr.excsave1 */
+ case 210:
+ return 151; /* wsr.excsave2 */
+ case 211:
+ return 157; /* wsr.excsave3 */
+ case 212:
+ return 163; /* wsr.excsave4 */
+ case 213:
+ return 169; /* wsr.excsave5 */
+ case 214:
+ return 175; /* wsr.excsave6 */
+ case 215:
+ return 181; /* wsr.excsave7 */
+ case 224:
+ return 419; /* wsr.cpenable */
+ case 226:
+ return 313; /* wsr.intset */
+ case 227:
+ return 314; /* wsr.intclear */
+ case 228:
+ return 316; /* wsr.intenable */
+ case 230:
+ return 139; /* wsr.ps */
+ case 231:
+ return 218; /* wsr.vecbase */
+ case 232:
+ return 208; /* wsr.exccause */
+ case 233:
+ return 342; /* wsr.debugcause */
+ case 234:
+ return 357; /* wsr.ccount */
+ case 236:
+ return 345; /* wsr.icount */
+ case 237:
+ return 348; /* wsr.icountlevel */
+ case 238:
+ return 202; /* wsr.excvaddr */
+ case 240:
+ return 360; /* wsr.ccompare0 */
+ case 241:
+ return 363; /* wsr.ccompare1 */
+ case 242:
+ return 366; /* wsr.ccompare2 */
+ case 244:
+ return 211; /* wsr.misc0 */
+ case 245:
+ return 214; /* wsr.misc1 */
+ }
+ break;
+ case 2:
+ return 428; /* sext */
+ case 3:
+ return 421; /* clamps */
+ case 4:
+ return 422; /* min */
+ case 5:
+ return 423; /* max */
+ case 6:
+ return 424; /* minu */
+ case 7:
+ return 425; /* maxu */
+ case 8:
+ return 91; /* moveqz */
+ case 9:
+ return 92; /* movnez */
+ case 10:
+ return 93; /* movltz */
+ case 11:
+ return 94; /* movgez */
+ case 14:
+ switch (Field_st_Slot_inst_get (insn))
+ {
+ case 230:
+ return 440; /* rur.expstate */
+ case 231:
+ return 37; /* rur.threadptr */
+ }
+ break;
+ case 15:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 230:
+ return 441; /* wur.expstate */
+ case 231:
+ return 38; /* wur.threadptr */
+ }
+ break;
+ }
+ break;
+ case 4:
+ case 5:
+ return 78; /* extui */
+ case 9:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ return 18; /* l32e */
+ case 4:
+ return 19; /* s32e */
+ }
+ break;
+ }
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return 442; /* read_impwire */
+ break;
+ case 1:
+ if (Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return 443; /* setb_expstate */
+ if (Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return 444; /* clrb_expstate */
+ break;
+ case 2:
+ if (Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return 445; /* wrmsk_expstate */
+ break;
+ }
+ break;
+ case 1:
+ return 85; /* l32r */
+ case 2:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return 86; /* l8ui */
+ case 1:
+ return 82; /* l16ui */
+ case 2:
+ return 84; /* l32i */
+ case 4:
+ return 101; /* s8i */
+ case 5:
+ return 99; /* s16i */
+ case 6:
+ return 100; /* s32i */
+ case 7:
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ return 384; /* dpfr */
+ case 1:
+ return 385; /* dpfw */
+ case 2:
+ return 386; /* dpfro */
+ case 3:
+ return 387; /* dpfwo */
+ case 4:
+ return 378; /* dhwb */
+ case 5:
+ return 379; /* dhwbi */
+ case 6:
+ return 382; /* dhi */
+ case 7:
+ return 383; /* dii */
+ case 8:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ return 388; /* dpfl */
+ case 2:
+ return 389; /* dhu */
+ case 3:
+ return 390; /* diu */
+ case 4:
+ return 380; /* diwb */
+ case 5:
+ return 381; /* diwbi */
+ }
+ break;
+ case 12:
+ return 368; /* ipf */
+ case 13:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ return 370; /* ipfl */
+ case 2:
+ return 371; /* ihu */
+ case 3:
+ return 372; /* iiu */
+ }
+ break;
+ case 14:
+ return 369; /* ihi */
+ case 15:
+ return 373; /* iii */
+ }
+ break;
+ case 9:
+ return 83; /* l16si */
+ case 10:
+ return 90; /* movi */
+ case 11:
+ return 429; /* l32ai */
+ case 12:
+ return 39; /* addi */
+ case 13:
+ return 40; /* addmi */
+ case 14:
+ return 431; /* s32c1i */
+ case 15:
+ return 430; /* s32ri */
+ }
+ break;
+ case 4:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 281; /* mula.dd.ll.ldinc */
+ break;
+ case 9:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 283; /* mula.dd.hl.ldinc */
+ break;
+ case 10:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 285; /* mula.dd.lh.ldinc */
+ break;
+ case 11:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 287; /* mula.dd.hh.ldinc */
+ break;
+ }
+ break;
+ case 1:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 280; /* mula.dd.ll.lddec */
+ break;
+ case 9:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 282; /* mula.dd.hl.lddec */
+ break;
+ case 10:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 284; /* mula.dd.lh.lddec */
+ break;
+ case 11:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 286; /* mula.dd.hh.lddec */
+ break;
+ }
+ break;
+ case 2:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 236; /* mul.dd.ll */
+ break;
+ case 5:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 237; /* mul.dd.hl */
+ break;
+ case 6:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 238; /* mul.dd.lh */
+ break;
+ case 7:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 239; /* mul.dd.hh */
+ break;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 264; /* mula.dd.ll */
+ break;
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 265; /* mula.dd.hl */
+ break;
+ case 10:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 266; /* mula.dd.lh */
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 267; /* mula.dd.hh */
+ break;
+ case 12:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 268; /* muls.dd.ll */
+ break;
+ case 13:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 269; /* muls.dd.hl */
+ break;
+ case 14:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 270; /* muls.dd.lh */
+ break;
+ case 15:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 271; /* muls.dd.hh */
+ break;
+ }
+ break;
+ case 3:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 228; /* mul.ad.ll */
+ break;
+ case 5:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 229; /* mul.ad.hl */
+ break;
+ case 6:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 230; /* mul.ad.lh */
+ break;
+ case 7:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 231; /* mul.ad.hh */
+ break;
+ case 8:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 248; /* mula.ad.ll */
+ break;
+ case 9:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 249; /* mula.ad.hl */
+ break;
+ case 10:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 250; /* mula.ad.lh */
+ break;
+ case 11:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 251; /* mula.ad.hh */
+ break;
+ case 12:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 252; /* muls.ad.ll */
+ break;
+ case 13:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 253; /* muls.ad.hl */
+ break;
+ case 14:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 254; /* muls.ad.lh */
+ break;
+ case 15:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return 255; /* muls.ad.hh */
+ break;
+ }
+ break;
+ case 4:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 273; /* mula.da.ll.ldinc */
+ break;
+ case 9:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 275; /* mula.da.hl.ldinc */
+ break;
+ case 10:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 277; /* mula.da.lh.ldinc */
+ break;
+ case 11:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 279; /* mula.da.hh.ldinc */
+ break;
+ }
+ break;
+ case 5:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 272; /* mula.da.ll.lddec */
+ break;
+ case 9:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 274; /* mula.da.hl.lddec */
+ break;
+ case 10:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 276; /* mula.da.lh.lddec */
+ break;
+ case 11:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return 278; /* mula.da.hh.lddec */
+ break;
+ }
+ break;
+ case 6:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 232; /* mul.da.ll */
+ break;
+ case 5:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 233; /* mul.da.hl */
+ break;
+ case 6:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 234; /* mul.da.lh */
+ break;
+ case 7:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 235; /* mul.da.hh */
+ break;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 256; /* mula.da.ll */
+ break;
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 257; /* mula.da.hl */
+ break;
+ case 10:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 258; /* mula.da.lh */
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 259; /* mula.da.hh */
+ break;
+ case 12:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 260; /* muls.da.ll */
+ break;
+ case 13:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 261; /* muls.da.hl */
+ break;
+ case 14:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 262; /* muls.da.lh */
+ break;
+ case 15:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return 263; /* muls.da.hh */
+ break;
+ }
+ break;
+ case 7:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 224; /* umul.aa.ll */
+ break;
+ case 1:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 225; /* umul.aa.hl */
+ break;
+ case 2:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 226; /* umul.aa.lh */
+ break;
+ case 3:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 227; /* umul.aa.hh */
+ break;
+ case 4:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 220; /* mul.aa.ll */
+ break;
+ case 5:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 221; /* mul.aa.hl */
+ break;
+ case 6:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 222; /* mul.aa.lh */
+ break;
+ case 7:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 223; /* mul.aa.hh */
+ break;
+ case 8:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 240; /* mula.aa.ll */
+ break;
+ case 9:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 241; /* mula.aa.hl */
+ break;
+ case 10:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 242; /* mula.aa.lh */
+ break;
+ case 11:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 243; /* mula.aa.hh */
+ break;
+ case 12:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 244; /* muls.aa.ll */
+ break;
+ case 13:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 245; /* muls.aa.hl */
+ break;
+ case 14:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 246; /* muls.aa.lh */
+ break;
+ case 15:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return 247; /* muls.aa.hh */
+ break;
+ }
+ break;
+ case 8:
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return 289; /* ldinc */
+ break;
+ case 9:
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return 288; /* lddec */
+ break;
+ }
+ break;
+ case 5:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 76; /* call0 */
+ case 1:
+ return 7; /* call4 */
+ case 2:
+ return 6; /* call8 */
+ case 3:
+ return 5; /* call12 */
+ }
+ break;
+ case 6:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 80; /* j */
+ case 1:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return 72; /* beqz */
+ case 1:
+ return 73; /* bnez */
+ case 2:
+ return 75; /* bltz */
+ case 3:
+ return 74; /* bgez */
+ }
+ break;
+ case 2:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return 52; /* beqi */
+ case 1:
+ return 53; /* bnei */
+ case 2:
+ return 55; /* blti */
+ case 3:
+ return 54; /* bgei */
+ }
+ break;
+ case 3:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return 11; /* entry */
+ case 1:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 8:
+ return 87; /* loop */
+ case 9:
+ return 88; /* loopnez */
+ case 10:
+ return 89; /* loopgtz */
+ }
+ break;
+ case 2:
+ return 59; /* bltui */
+ case 3:
+ return 58; /* bgeui */
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return 67; /* bnone */
+ case 1:
+ return 60; /* beq */
+ case 2:
+ return 63; /* blt */
+ case 3:
+ return 65; /* bltu */
+ case 4:
+ return 68; /* ball */
+ case 5:
+ return 70; /* bbc */
+ case 6:
+ case 7:
+ return 56; /* bbci */
+ case 8:
+ return 66; /* bany */
+ case 9:
+ return 61; /* bne */
+ case 10:
+ return 62; /* bge */
+ case 11:
+ return 64; /* bgeu */
+ case 12:
+ return 69; /* bnall */
+ case 13:
+ return 71; /* bbs */
+ case 14:
+ case 15:
+ return 57; /* bbsi */
+ }
+ break;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst16b_get (insn))
+ {
+ case 12:
+ switch (Field_i_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 33; /* movi.n */
+ case 1:
+ switch (Field_z_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 28; /* beqz.n */
+ case 1:
+ return 29; /* bnez.n */
+ }
+ break;
+ }
+ break;
+ case 13:
+ switch (Field_r_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 32; /* mov.n */
+ case 15:
+ switch (Field_t_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 35; /* ret.n */
+ case 1:
+ return 15; /* retw.n */
+ case 2:
+ return 319; /* break.n */
+ case 3:
+ if (Field_s_Slot_inst16b_get (insn) == 0)
+ return 34; /* nop.n */
+ break;
+ case 6:
+ if (Field_s_Slot_inst16b_get (insn) == 0)
+ return 30; /* ill.n */
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst16a_get (insn))
+ {
+ case 8:
+ return 31; /* l32i.n */
+ case 9:
+ return 36; /* s32i.n */
+ case 10:
+ return 26; /* add.n */
+ case 11:
+ return 27; /* addi.n */
+ }
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_get,
+ Field_rbit2_Slot_inst_get,
+ Field_rhi_Slot_inst_get,
+ Field_t3_Slot_inst_get,
+ Field_tbit2_Slot_inst_get,
+ Field_tlo_Slot_inst_get,
+ Field_w_Slot_inst_get,
+ Field_y_Slot_inst_get,
+ Field_x_Slot_inst_get,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_set,
+ Field_rbit2_Slot_inst_set,
+ Field_rhi_Slot_inst_set,
+ Field_t3_Slot_inst_set,
+ Field_tbit2_Slot_inst_set,
+ Field_tlo_Slot_inst_set,
+ Field_w_Slot_inst_set,
+ Field_y_Slot_inst_set,
+ Field_x_Slot_inst_set,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[16] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int op0 = insn[0] & 0xf;
+ return length_table[op0];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 56 /* num_fields */,
+ 93, operands,
+ 320, iclasses,
+ 446, opcodes, 0,
+ 2, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 1, interfaces, 0,
+ 0, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
- Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#include "qemu/osdep.h"
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "ACCLO", 16, 0 },
- { "ACCHI", 17, 0 },
- { "M0", 32, 0 },
- { "M1", 33, 0 },
- { "M2", 34, 0 },
- { "M3", 35, 0 },
- { "PTEVADDR", 83, 0 },
- { "MMID", 89, 0 },
- { "DDR", 104, 0 },
- { "176", 176, 0 },
- { "208", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EPC5", 181, 0 },
- { "EPC6", 182, 0 },
- { "EPC7", 183, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EXCSAVE5", 213, 0 },
- { "EXCSAVE6", 214, 0 },
- { "EXCSAVE7", 215, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EPS5", 197, 0 },
- { "EPS6", 198, 0 },
- { "EPS7", 199, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "LITBASE", 5, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "RASID", 90, 0 },
- { "ITLBCFG", 91, 0 },
- { "DTLBCFG", 92, 0 },
- { "CPENABLE", 224, 0 },
- { "SCOMPARE1", 12, 0 },
- { "THREADPTR", 231, 1 },
- { "EXPSTATE", 230, 1 }
-};
-
-#define NUM_SYSREGS 70
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 231
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 22, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EPC5", 32, 0 },
- { "EPC6", 32, 0 },
- { "EPC7", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EXCSAVE5", 32, 0 },
- { "EXCSAVE6", 32, 0 },
- { "EXCSAVE7", 32, 0 },
- { "EPS2", 15, 0 },
- { "EPS3", 15, 0 },
- { "EPS4", 15, 0 },
- { "EPS5", 15, 0 },
- { "EPS6", 15, 0 },
- { "EPS7", 15, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSRING", 2, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 3, 0 },
- { "WindowStart", 8, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "THREADPTR", 32, 0 },
- { "LITBADDR", 20, 0 },
- { "LITBEN", 1, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "ACC", 40, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 22, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "ASID3", 8, 0 },
- { "ASID2", 8, 0 },
- { "ASID1", 8, 0 },
- { "INSTPGSZID4", 2, 0 },
- { "DATAPGSZID4", 2, 0 },
- { "PTBASE", 10, 0 },
- { "CPENABLE", 8, 0 },
- { "SCOMPARE1", 32, 0 },
- { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
-};
-
-#define NUM_STATES 73
-
-/* Macros for xtensa_state numbers (for use in iclasses because the
- state numbers are not available when the iclass table is generated). */
-
-#define STATE_LCOUNT 0
-#define STATE_PC 1
-#define STATE_ICOUNT 2
-#define STATE_DDR 3
-#define STATE_INTERRUPT 4
-#define STATE_CCOUNT 5
-#define STATE_XTSYNC 6
-#define STATE_VECBASE 7
-#define STATE_EPC1 8
-#define STATE_EPC2 9
-#define STATE_EPC3 10
-#define STATE_EPC4 11
-#define STATE_EPC5 12
-#define STATE_EPC6 13
-#define STATE_EPC7 14
-#define STATE_EXCSAVE1 15
-#define STATE_EXCSAVE2 16
-#define STATE_EXCSAVE3 17
-#define STATE_EXCSAVE4 18
-#define STATE_EXCSAVE5 19
-#define STATE_EXCSAVE6 20
-#define STATE_EXCSAVE7 21
-#define STATE_EPS2 22
-#define STATE_EPS3 23
-#define STATE_EPS4 24
-#define STATE_EPS5 25
-#define STATE_EPS6 26
-#define STATE_EPS7 27
-#define STATE_EXCCAUSE 28
-#define STATE_PSINTLEVEL 29
-#define STATE_PSUM 30
-#define STATE_PSWOE 31
-#define STATE_PSRING 32
-#define STATE_PSEXCM 33
-#define STATE_DEPC 34
-#define STATE_EXCVADDR 35
-#define STATE_WindowBase 36
-#define STATE_WindowStart 37
-#define STATE_PSCALLINC 38
-#define STATE_PSOWB 39
-#define STATE_LBEG 40
-#define STATE_LEND 41
-#define STATE_SAR 42
-#define STATE_THREADPTR 43
-#define STATE_LITBADDR 44
-#define STATE_LITBEN 45
-#define STATE_MISC0 46
-#define STATE_MISC1 47
-#define STATE_ACC 48
-#define STATE_InOCDMode 49
-#define STATE_INTENABLE 50
-#define STATE_DBREAKA0 51
-#define STATE_DBREAKC0 52
-#define STATE_DBREAKA1 53
-#define STATE_DBREAKC1 54
-#define STATE_IBREAKA0 55
-#define STATE_IBREAKA1 56
-#define STATE_IBREAKENABLE 57
-#define STATE_ICOUNTLEVEL 58
-#define STATE_DEBUGCAUSE 59
-#define STATE_DBNUM 60
-#define STATE_CCOMPARE0 61
-#define STATE_CCOMPARE1 62
-#define STATE_CCOMPARE2 63
-#define STATE_ASID3 64
-#define STATE_ASID2 65
-#define STATE_ASID1 66
-#define STATE_INSTPGSZID4 67
-#define STATE_DATAPGSZID4 68
-#define STATE_PTBASE 69
-#define STATE_CPENABLE 70
-#define STATE_SCOMPARE1 71
-#define STATE_EXPSTATE 72
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_w_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_y_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_x_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
- return tie_t;
-}
-
-static void
-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 17) >> 17;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-static unsigned
-Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 1;
-}
-
-static unsigned
-Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 2;
-}
-
-static unsigned
-Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 3;
-}
-
-\f
-/* Functional units. */
-
-static xtensa_funcUnit_internal funcUnits[] = {
-
-};
-
-\f
-/* Register files. */
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", 0, 32, 32 },
- { "MR", "m", 1, 32, 4 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
- { "IMPWIRE", 32, 0, 0, 'i' }
-};
-
-\f
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-Operand_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
- *valp = soffsetx4_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_encode (uint32 *valp)
-{
- unsigned offset_0, soffsetx4_0;
- soffsetx4_0 = *valp;
- offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
- *valp = offset_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- uimm12x8_0 = imm12_0 << 3;
- *valp = uimm12x8_0;
- return 0;
-}
-
-static int
-Operand_uimm12x8_encode (uint32 *valp)
-{
- unsigned imm12_0, uimm12x8_0;
- uimm12x8_0 = *valp;
- imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
- *valp = imm12_0;
- return 0;
-}
-
-static int
-Operand_simm4_decode (uint32 *valp)
-{
- unsigned simm4_0, mn_0;
- mn_0 = *valp & 0xf;
- simm4_0 = ((int) mn_0 << 28) >> 28;
- *valp = simm4_0;
- return 0;
-}
-
-static int
-Operand_simm4_encode (uint32 *valp)
-{
- unsigned mn_0, simm4_0;
- simm4_0 = *valp;
- mn_0 = (simm4_0 & 0xf);
- *valp = mn_0;
- return 0;
-}
-
-static int
-Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_arr_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ars_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_art_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar0_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar4_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar8_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar12_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ars_entry_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_0, r_0;
- r_0 = *valp & 0xf;
- immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
- *valp = immrx4_0;
- return 0;
-}
-
-static int
-Operand_immrx4_encode (uint32 *valp)
-{
- unsigned r_0, immrx4_0;
- immrx4_0 = *valp;
- r_0 = ((immrx4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_0, r_0;
- r_0 = *valp & 0xf;
- lsi4x4_0 = r_0 << 2;
- *valp = lsi4x4_0;
- return 0;
-}
-
-static int
-Operand_lsi4x4_encode (uint32 *valp)
-{
- unsigned r_0, lsi4x4_0;
- lsi4x4_0 = *valp;
- r_0 = ((lsi4x4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_simm7_decode (uint32 *valp)
-{
- unsigned simm7_0, imm7_0;
- imm7_0 = *valp & 0x7f;
- simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
- *valp = simm7_0;
- return 0;
-}
-
-static int
-Operand_simm7_encode (uint32 *valp)
-{
- unsigned imm7_0, simm7_0;
- simm7_0 = *valp;
- imm7_0 = (simm7_0 & 0x7f);
- *valp = imm7_0;
- return 0;
-}
-
-static int
-Operand_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_0, imm6_0;
- imm6_0 = *valp & 0x3f;
- uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
- *valp = uimm6_0;
- return 0;
-}
-
-static int
-Operand_uimm6_encode (uint32 *valp)
-{
- unsigned imm6_0, uimm6_0;
- uimm6_0 = *valp;
- imm6_0 = (uimm6_0 - 0x4) & 0x3f;
- *valp = imm6_0;
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_0, t_0;
- t_0 = *valp & 0xf;
- ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
- *valp = ai4const_0;
- return 0;
-}
-
-static int
-Operand_ai4const_encode (uint32 *valp)
-{
- unsigned t_0, ai4const_0;
- ai4const_0 = *valp;
- switch (ai4const_0)
- {
- case 0xffffffff: t_0 = 0; break;
- case 0x1: t_0 = 0x1; break;
- case 0x2: t_0 = 0x2; break;
- case 0x3: t_0 = 0x3; break;
- case 0x4: t_0 = 0x4; break;
- case 0x5: t_0 = 0x5; break;
- case 0x6: t_0 = 0x6; break;
- case 0x7: t_0 = 0x7; break;
- case 0x8: t_0 = 0x8; break;
- case 0x9: t_0 = 0x9; break;
- case 0xa: t_0 = 0xa; break;
- case 0xb: t_0 = 0xb; break;
- case 0xc: t_0 = 0xc; break;
- case 0xd: t_0 = 0xd; break;
- case 0xe: t_0 = 0xe; break;
- default: t_0 = 0xf; break;
- }
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_b4const_decode (uint32 *valp)
-{
- unsigned b4const_0, r_0;
- r_0 = *valp & 0xf;
- b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
- *valp = b4const_0;
- return 0;
-}
-
-static int
-Operand_b4const_encode (uint32 *valp)
-{
- unsigned r_0, b4const_0;
- b4const_0 = *valp;
- switch (b4const_0)
- {
- case 0xffffffff: r_0 = 0; break;
- case 0x1: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_0, r_0;
- r_0 = *valp & 0xf;
- b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
- *valp = b4constu_0;
- return 0;
-}
-
-static int
-Operand_b4constu_encode (uint32 *valp)
-{
- unsigned r_0, b4constu_0;
- b4constu_0 = *valp;
- switch (b4constu_0)
- {
- case 0x8000: r_0 = 0; break;
- case 0x10000: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8_0 = imm8_0;
- *valp = uimm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8_0;
- uimm8_0 = *valp;
- imm8_0 = (uimm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x2_0 = imm8_0 << 1;
- *valp = uimm8x2_0;
- return 0;
-}
-
-static int
-Operand_uimm8x2_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8x2_0;
- uimm8x2_0 = *valp;
- imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x4_0 = imm8_0 << 2;
- *valp = uimm8x4_0;
- return 0;
-}
-
-static int
-Operand_uimm8x4_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8x4_0;
- uimm8x4_0 = *valp;
- imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_0, op2_0;
- op2_0 = *valp & 0xf;
- uimm4x16_0 = op2_0 << 4;
- *valp = uimm4x16_0;
- return 0;
-}
-
-static int
-Operand_uimm4x16_encode (uint32 *valp)
-{
- unsigned op2_0, uimm4x16_0;
- uimm4x16_0 = *valp;
- op2_0 = ((uimm4x16_0 >> 4) & 0xf);
- *valp = op2_0;
- return 0;
-}
-
-static int
-Operand_simm8_decode (uint32 *valp)
-{
- unsigned simm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8_0 = ((int) imm8_0 << 24) >> 24;
- *valp = simm8_0;
- return 0;
-}
-
-static int
-Operand_simm8_encode (uint32 *valp)
-{
- unsigned imm8_0, simm8_0;
- simm8_0 = *valp;
- imm8_0 = (simm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
- *valp = simm8x256_0;
- return 0;
-}
-
-static int
-Operand_simm8x256_encode (uint32 *valp)
-{
- unsigned imm8_0, simm8x256_0;
- simm8x256_0 = *valp;
- imm8_0 = ((simm8x256_0 >> 8) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_0, imm12b_0;
- imm12b_0 = *valp & 0xfff;
- simm12b_0 = ((int) imm12b_0 << 20) >> 20;
- *valp = simm12b_0;
- return 0;
-}
-
-static int
-Operand_simm12b_encode (uint32 *valp)
-{
- unsigned imm12b_0, simm12b_0;
- simm12b_0 = *valp;
- imm12b_0 = (simm12b_0 & 0xfff);
- *valp = imm12b_0;
- return 0;
-}
-
-static int
-Operand_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_0, sal_0;
- sal_0 = *valp & 0x1f;
- msalp32_0 = 0x20 - sal_0;
- *valp = msalp32_0;
- return 0;
-}
-
-static int
-Operand_msalp32_encode (uint32 *valp)
-{
- unsigned sal_0, msalp32_0;
- msalp32_0 = *valp;
- sal_0 = (0x20 - msalp32_0) & 0x1f;
- *valp = sal_0;
- return 0;
-}
-
-static int
-Operand_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_0, op2_0;
- op2_0 = *valp & 0xf;
- op2p1_0 = op2_0 + 0x1;
- *valp = op2p1_0;
- return 0;
-}
-
-static int
-Operand_op2p1_encode (uint32 *valp)
-{
- unsigned op2_0, op2p1_0;
- op2p1_0 = *valp;
- op2_0 = (op2p1_0 - 0x1) & 0xf;
- *valp = op2_0;
- return 0;
-}
-
-static int
-Operand_label8_decode (uint32 *valp)
-{
- unsigned label8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
- *valp = label8_0;
- return 0;
-}
-
-static int
-Operand_label8_encode (uint32 *valp)
-{
- unsigned imm8_0, label8_0;
- label8_0 = *valp;
- imm8_0 = (label8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_decode (uint32 *valp)
-{
- unsigned ulabel8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
- *valp = ulabel8_0;
- return 0;
-}
-
-static int
-Operand_ulabel8_encode (uint32 *valp)
-{
- unsigned imm8_0, ulabel8_0;
- ulabel8_0 = *valp;
- imm8_0 = (ulabel8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_ulabel8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_decode (uint32 *valp)
-{
- unsigned label12_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
- *valp = label12_0;
- return 0;
-}
-
-static int
-Operand_label12_encode (uint32 *valp)
-{
- unsigned imm12_0, label12_0;
- label12_0 = *valp;
- imm12_0 = (label12_0 - 0x4) & 0xfff;
- *valp = imm12_0;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_decode (uint32 *valp)
-{
- unsigned soffset_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
- *valp = soffset_0;
- return 0;
-}
-
-static int
-Operand_soffset_encode (uint32 *valp)
-{
- unsigned offset_0, soffset_0;
- soffset_0 = *valp;
- offset_0 = (soffset_0 - 0x4) & 0x3ffff;
- *valp = offset_0;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_0, imm16_0;
- imm16_0 = *valp & 0xffff;
- uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
- *valp = uimm16x4_0;
- return 0;
-}
-
-static int
-Operand_uimm16x4_encode (uint32 *valp)
-{
- unsigned imm16_0, uimm16x4_0;
- uimm16x4_0 = *valp;
- imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
- *valp = imm16_0;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mx_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_my_decode (uint32 *valp)
-{
- *valp += 2;
- return 0;
-}
-
-static int
-Operand_my_encode (uint32 *valp)
-{
- int error;
- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
- *valp = *valp & 1;
- return error;
-}
-
-static int
-Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mw_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr0_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr1_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr2_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr3_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_immt_decode (uint32 *valp)
-{
- unsigned immt_0, t_0;
- t_0 = *valp & 0xf;
- immt_0 = t_0;
- *valp = immt_0;
- return 0;
-}
-
-static int
-Operand_immt_encode (uint32 *valp)
-{
- unsigned t_0, immt_0;
- immt_0 = *valp;
- t_0 = immt_0 & 0xf;
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_imms_decode (uint32 *valp)
-{
- unsigned imms_0, s_0;
- s_0 = *valp & 0xf;
- imms_0 = s_0;
- *valp = imms_0;
- return 0;
-}
-
-static int
-Operand_imms_encode (uint32 *valp)
-{
- unsigned s_0, imms_0;
- imms_0 = *valp;
- s_0 = imms_0 & 0xf;
- *valp = s_0;
- return 0;
-}
-
-static int
-Operand_tp7_decode (uint32 *valp)
-{
- unsigned tp7_0, t_0;
- t_0 = *valp & 0xf;
- tp7_0 = t_0 + 0x7;
- *valp = tp7_0;
- return 0;
-}
-
-static int
-Operand_tp7_encode (uint32 *valp)
-{
- unsigned t_0, tp7_0;
- tp7_0 = *valp;
- t_0 = (tp7_0 - 0x7) & 0xf;
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_decode (uint32 *valp)
-{
- unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
- xt_wbr15_imm_0 = *valp & 0x7fff;
- xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
- *valp = xt_wbr15_label_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_encode (uint32 *valp)
-{
- unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
- xt_wbr15_label_0 = *valp;
- xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_imm_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_decode (uint32 *valp)
-{
- unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
- xt_wbr18_imm_0 = *valp & 0x3ffff;
- xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
- *valp = xt_wbr18_label_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_encode (uint32 *valp)
-{
- unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
- xt_wbr18_label_0 = *valp;
- xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
- *valp = xt_wbr18_imm_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", 10, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffsetx4_encode, Operand_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", 3, -1, 0,
- 0,
- Operand_uimm12x8_encode, Operand_uimm12x8_decode,
- 0, 0 },
- { "simm4", 26, -1, 0,
- 0,
- Operand_simm4_encode, Operand_simm4_decode,
- 0, 0 },
- { "arr", 14, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_arr_encode, Operand_arr_decode,
- 0, 0 },
- { "ars", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "*ars_invisible", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "art", 0, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_art_encode, Operand_art_decode,
- 0, 0 },
- { "ar0", 48, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar0_encode, Operand_ar0_decode,
- 0, 0 },
- { "ar4", 49, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar4_encode, Operand_ar4_decode,
- 0, 0 },
- { "ar8", 50, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar8_encode, Operand_ar8_decode,
- 0, 0 },
- { "ar12", 51, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar12_encode, Operand_ar12_decode,
- 0, 0 },
- { "ars_entry", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_entry_encode, Operand_ars_entry_decode,
- 0, 0 },
- { "immrx4", 14, -1, 0,
- 0,
- Operand_immrx4_encode, Operand_immrx4_decode,
- 0, 0 },
- { "lsi4x4", 14, -1, 0,
- 0,
- Operand_lsi4x4_encode, Operand_lsi4x4_decode,
- 0, 0 },
- { "simm7", 34, -1, 0,
- 0,
- Operand_simm7_encode, Operand_simm7_decode,
- 0, 0 },
- { "uimm6", 33, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm6_encode, Operand_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", 0, -1, 0,
- 0,
- Operand_ai4const_encode, Operand_ai4const_decode,
- 0, 0 },
- { "b4const", 14, -1, 0,
- 0,
- Operand_b4const_encode, Operand_b4const_decode,
- 0, 0 },
- { "b4constu", 14, -1, 0,
- 0,
- Operand_b4constu_encode, Operand_b4constu_decode,
- 0, 0 },
- { "uimm8", 4, -1, 0,
- 0,
- Operand_uimm8_encode, Operand_uimm8_decode,
- 0, 0 },
- { "uimm8x2", 4, -1, 0,
- 0,
- Operand_uimm8x2_encode, Operand_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", 4, -1, 0,
- 0,
- Operand_uimm8x4_encode, Operand_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", 13, -1, 0,
- 0,
- Operand_uimm4x16_encode, Operand_uimm4x16_decode,
- 0, 0 },
- { "simm8", 4, -1, 0,
- 0,
- Operand_simm8_encode, Operand_simm8_decode,
- 0, 0 },
- { "simm8x256", 4, -1, 0,
- 0,
- Operand_simm8x256_encode, Operand_simm8x256_decode,
- 0, 0 },
- { "simm12b", 6, -1, 0,
- 0,
- Operand_simm12b_encode, Operand_simm12b_decode,
- 0, 0 },
- { "msalp32", 18, -1, 0,
- 0,
- Operand_msalp32_encode, Operand_msalp32_decode,
- 0, 0 },
- { "op2p1", 13, -1, 0,
- 0,
- Operand_op2p1_encode, Operand_op2p1_decode,
- 0, 0 },
- { "label8", 4, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label8_encode, Operand_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", 4, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_ulabel8_encode, Operand_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", 3, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label12_encode, Operand_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", 10, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffset_encode, Operand_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", 7, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm16x4_encode, Operand_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "mx", 43, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- Operand_mx_encode, Operand_mx_decode,
- 0, 0 },
- { "my", 42, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- Operand_my_encode, Operand_my_decode,
- 0, 0 },
- { "mw", 41, 1, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_mw_encode, Operand_mw_decode,
- 0, 0 },
- { "mr0", 52, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr0_encode, Operand_mr0_decode,
- 0, 0 },
- { "mr1", 53, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr1_encode, Operand_mr1_decode,
- 0, 0 },
- { "mr2", 54, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr2_encode, Operand_mr2_decode,
- 0, 0 },
- { "mr3", 55, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr3_encode, Operand_mr3_decode,
- 0, 0 },
- { "immt", 0, -1, 0,
- 0,
- Operand_immt_encode, Operand_immt_decode,
- 0, 0 },
- { "imms", 5, -1, 0,
- 0,
- Operand_imms_encode, Operand_imms_decode,
- 0, 0 },
- { "tp7", 0, -1, 0,
- 0,
- Operand_tp7_encode, Operand_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", 44, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", 45, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
- { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
- { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
- { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
- { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
- { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
- { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
- { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
- { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
- { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
- { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
- { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
- { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
- { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
- { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
- { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
- { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
- { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
- { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
- { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 },
- { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 },
- { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSRING }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 10 /* ar12 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 9 /* ar8 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 8 /* ar4 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 10 /* ar12 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 9 /* ar8 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 8 /* ar4 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { 11 /* ars_entry */ }, 's' },
- { { 4 /* ars */ }, 'i' },
- { { 1 /* uimm12x8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { 2 /* simm4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 12 /* immrx4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 12 /* immrx4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 16 /* ai4const */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 15 /* uimm6 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 13 /* lsi4x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { 4 /* ars */ }, 'o' },
- { { 14 /* simm7 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 13 /* lsi4x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
- { { 3 /* arr */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 23 /* simm8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 24 /* simm8x256 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 17 /* b4const */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 47 /* bbi */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 18 /* b4constu */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 30 /* label12 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 7 /* ar0 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 7 /* ar0 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 62 /* sae */ }, 'i' },
- { { 27 /* op2p1 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { 31 /* soffset */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 32 /* uimm16x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 19 /* uimm8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 29 /* ulabel8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 29 /* ulabel8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 25 /* simm12b */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { 3 /* arr */ }, 'm' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 19 /* uimm8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { 66 /* sas */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 26 /* msalp32 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 64 /* sargt */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 50 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 50 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'o' },
- { { STATE_LITBEN }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'm' },
- { { STATE_LITBEN }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 34 /* my */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 34 /* my */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 34 /* my */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 34 /* my */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
- { { 35 /* mw */ }, 'o' },
- { { 4 /* ars */ }, 'm' },
- { { 33 /* mx */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
- { { 35 /* mw */ }, 'o' },
- { { 4 /* ars */ }, 'm' },
- { { 33 /* mx */ }, 'i' },
- { { 34 /* my */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
- { { 35 /* mw */ }, 'o' },
- { { 4 /* ars */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 36 /* mr0 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 36 /* mr0 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 36 /* mr0 */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 37 /* mr1 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 37 /* mr1 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 37 /* mr1 */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 38 /* mr2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 38 /* mr2 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 38 /* mr2 */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 39 /* mr3 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 39 /* mr3 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 39 /* mr3 */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { 50 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPC5 }, 'i' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_EPC7 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_EPS5 }, 'i' },
- { { STATE_EPS6 }, 'i' },
- { { STATE_EPS7 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { 50 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { 41 /* imms */ }, 'i' },
- { { 40 /* immt */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { 41 /* imms */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { 41 /* imms */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'm' },
- { { STATE_EXCVADDR }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'i' },
- { { STATE_ASID2 }, 'i' },
- { { STATE_ASID1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'o' },
- { { STATE_ASID2 }, 'o' },
- { { STATE_ASID1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'm' },
- { { STATE_ASID2 }, 'm' },
- { { STATE_ASID1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 42 /* tp7 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 42 /* tp7 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_args[] = {
- { { 3 /* arr */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
- 0 /* IMPWIRE */
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
- { { 91 /* bitindex */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
- { { 91 /* bitindex */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_threadptr_args,
- 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
- { 1, Iclass_wur_threadptr_args,
- 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_176_args,
- 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_208_args,
- 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc5_args,
- 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc5_args,
- 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc5_args,
- 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave5_args,
- 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave5_args,
- 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave5_args,
- 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc6_args,
- 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc6_args,
- 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc6_args,
- 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave6_args,
- 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave6_args,
- 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave6_args,
- 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc7_args,
- 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc7_args,
- 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc7_args,
- 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave7_args,
- 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave7_args,
- 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave7_args,
- 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps5_args,
- 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps5_args,
- 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps5_args,
- 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps6_args,
- 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps6_args,
- 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps6_args,
- 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps7_args,
- 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps7_args,
- 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps7_args,
- 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_aa_args,
- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_ad_args,
- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_da_args,
- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_dd_args,
- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_aa_args,
- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_ad_args,
- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_da_args,
- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_dd_args,
- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_da_args,
- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_dd_args,
- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_l_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_mul16_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m3_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acclo_args,
- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acclo_args,
- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acclo_args,
- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acchi_args,
- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acchi_args,
- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acchi_args,
- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_mmid_args,
- 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_lock_args,
- 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_lock_args,
- 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_rasid_args,
- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_rasid_args,
- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_rasid_args,
- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
- 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
- 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
- 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
- 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_ldpte */,
- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwitlba */,
- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwdtlba */,
- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_cpenable_args,
- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_cpenable_args,
- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_cpenable_args,
- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_clamp_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_div_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_expstate_args,
- 2, Iclass_rur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_wur_expstate_args,
- 2, Iclass_wur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_iclass_READ_IMPWIRE_args,
- 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
- { 1, Iclass_iclass_SETB_EXPSTATE_args,
- 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
- { 1, Iclass_iclass_CLRB_EXPSTATE_args,
- 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
- { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
- 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2080;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3200;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5000;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5100;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x25;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1000;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x408000;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01d;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3400;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3500;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90000;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490000;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34800;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134800;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614800;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34900;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134900;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614900;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf06d;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03d;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00d;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e70;
-}
-
-static void
-Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e700;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc002;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd002;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800000;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc00000;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900000;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00000;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00000;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00000;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00000;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00000;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300000;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x26;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x66;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe6;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa6;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6007;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe007;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf6;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb6;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1007;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9007;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa007;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2007;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb007;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3007;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8007;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4007;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc007;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5007;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd007;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x56;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd6;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x96;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1002;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9002;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2002;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8076;
-}
-
-static void
-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9076;
-}
-
-static void
-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa076;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa002;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x830000;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x930000;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa30000;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb30000;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600100;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20f0;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5002;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6002;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4002;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400000;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x401000;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x402000;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x403000;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404000;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa10000;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x810000;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x910000;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb10000;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10000;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210000;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410000;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c0;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20d0;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2010;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2020;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2030;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000;
-}
-
-static void
-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30100;
-}
-
-static void
-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130100;
-}
-
-static void
-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610100;
-}
-
-static void
-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30200;
-}
-
-static void
-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130200;
-}
-
-static void
-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610200;
-}
-
-static void
-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130000;
-}
-
-static void
-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610000;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30300;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130300;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610300;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30500;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130500;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610500;
-}
-
-static void
-Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b000;
-}
-
-static void
-Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d000;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e600;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e600;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e600;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b100;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b100;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b100;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d100;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d100;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d100;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b200;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b200;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b200;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d200;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d200;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d200;
-}
-
-static void
-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b300;
-}
-
-static void
-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b300;
-}
-
-static void
-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b300;
-}
-
-static void
-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d300;
-}
-
-static void
-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d300;
-}
-
-static void
-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d300;
-}
-
-static void
-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b400;
-}
-
-static void
-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b400;
-}
-
-static void
-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b400;
-}
-
-static void
-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d400;
-}
-
-static void
-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d400;
-}
-
-static void
-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d400;
-}
-
-static void
-Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b500;
-}
-
-static void
-Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b500;
-}
-
-static void
-Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b500;
-}
-
-static void
-Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d500;
-}
-
-static void
-Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d500;
-}
-
-static void
-Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d500;
-}
-
-static void
-Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b600;
-}
-
-static void
-Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b600;
-}
-
-static void
-Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b600;
-}
-
-static void
-Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d600;
-}
-
-static void
-Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d600;
-}
-
-static void
-Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d600;
-}
-
-static void
-Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b700;
-}
-
-static void
-Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b700;
-}
-
-static void
-Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b700;
-}
-
-static void
-Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d700;
-}
-
-static void
-Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d700;
-}
-
-static void
-Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d700;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c200;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c200;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c200;
-}
-
-static void
-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c300;
-}
-
-static void
-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c300;
-}
-
-static void
-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c300;
-}
-
-static void
-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c400;
-}
-
-static void
-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c400;
-}
-
-static void
-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c400;
-}
-
-static void
-Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c500;
-}
-
-static void
-Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c500;
-}
-
-static void
-Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c500;
-}
-
-static void
-Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c600;
-}
-
-static void
-Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c600;
-}
-
-static void
-Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c600;
-}
-
-static void
-Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c700;
-}
-
-static void
-Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c700;
-}
-
-static void
-Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c700;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ee00;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ee00;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ee00;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c000;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c000;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c000;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e800;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e800;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e800;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f400;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f400;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f400;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f500;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f500;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f500;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3eb00;
-}
-
-static void
-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e700;
-}
-
-static void
-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e700;
-}
-
-static void
-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e700;
-}
-
-static void
-Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x740004;
-}
-
-static void
-Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x750004;
-}
-
-static void
-Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x760004;
-}
-
-static void
-Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x770004;
-}
-
-static void
-Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700004;
-}
-
-static void
-Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x710004;
-}
-
-static void
-Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x720004;
-}
-
-static void
-Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730004;
-}
-
-static void
-Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x340004;
-}
-
-static void
-Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x350004;
-}
-
-static void
-Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x360004;
-}
-
-static void
-Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x370004;
-}
-
-static void
-Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x640004;
-}
-
-static void
-Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x650004;
-}
-
-static void
-Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x660004;
-}
-
-static void
-Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x670004;
-}
-
-static void
-Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x240004;
-}
-
-static void
-Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x250004;
-}
-
-static void
-Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x260004;
-}
-
-static void
-Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270004;
-}
-
-static void
-Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780004;
-}
-
-static void
-Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x790004;
-}
-
-static void
-Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7a0004;
-}
-
-static void
-Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7b0004;
-}
-
-static void
-Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7c0004;
-}
-
-static void
-Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7d0004;
-}
-
-static void
-Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7e0004;
-}
-
-static void
-Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7f0004;
-}
-
-static void
-Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380004;
-}
-
-static void
-Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x390004;
-}
-
-static void
-Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a0004;
-}
-
-static void
-Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b0004;
-}
-
-static void
-Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c0004;
-}
-
-static void
-Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d0004;
-}
-
-static void
-Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e0004;
-}
-
-static void
-Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f0004;
-}
-
-static void
-Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680004;
-}
-
-static void
-Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x690004;
-}
-
-static void
-Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6a0004;
-}
-
-static void
-Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6b0004;
-}
-
-static void
-Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6c0004;
-}
-
-static void
-Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0004;
-}
-
-static void
-Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6e0004;
-}
-
-static void
-Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f0004;
-}
-
-static void
-Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280004;
-}
-
-static void
-Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x290004;
-}
-
-static void
-Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2a0004;
-}
-
-static void
-Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2b0004;
-}
-
-static void
-Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2c0004;
-}
-
-static void
-Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d0004;
-}
-
-static void
-Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e0004;
-}
-
-static void
-Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f0004;
-}
-
-static void
-Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580004;
-}
-
-static void
-Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480004;
-}
-
-static void
-Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x590004;
-}
-
-static void
-Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490004;
-}
-
-static void
-Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a0004;
-}
-
-static void
-Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4a0004;
-}
-
-static void
-Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b0004;
-}
-
-static void
-Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4b0004;
-}
-
-static void
-Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180004;
-}
-
-static void
-Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80004;
-}
-
-static void
-Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x190004;
-}
-
-static void
-Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90004;
-}
-
-static void
-Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1a0004;
-}
-
-static void
-Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0004;
-}
-
-static void
-Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b0004;
-}
-
-static void
-Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb0004;
-}
-
-static void
-Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900004;
-}
-
-static void
-Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800004;
-}
-
-static void
-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc10000;
-}
-
-static void
-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10000;
-}
-
-static void
-Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32000;
-}
-
-static void
-Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132000;
-}
-
-static void
-Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612000;
-}
-
-static void
-Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32100;
-}
-
-static void
-Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132100;
-}
-
-static void
-Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612100;
-}
-
-static void
-Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32200;
-}
-
-static void
-Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132200;
-}
-
-static void
-Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612200;
-}
-
-static void
-Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32300;
-}
-
-static void
-Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132300;
-}
-
-static void
-Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612300;
-}
-
-static void
-Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31000;
-}
-
-static void
-Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131000;
-}
-
-static void
-Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x611000;
-}
-
-static void
-Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31100;
-}
-
-static void
-Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131100;
-}
-
-static void
-Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x611100;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3010;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7000;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e200;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e200;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e300;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e400;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e400;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e400;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf02d;
-}
-
-static void
-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39000;
-}
-
-static void
-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139000;
-}
-
-static void
-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619000;
-}
-
-static void
-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a000;
-}
-
-static void
-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a000;
-}
-
-static void
-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a000;
-}
-
-static void
-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39100;
-}
-
-static void
-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139100;
-}
-
-static void
-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619100;
-}
-
-static void
-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a100;
-}
-
-static void
-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a100;
-}
-
-static void
-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a100;
-}
-
-static void
-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38000;
-}
-
-static void
-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138000;
-}
-
-static void
-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618000;
-}
-
-static void
-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38100;
-}
-
-static void
-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138100;
-}
-
-static void
-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618100;
-}
-
-static void
-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36000;
-}
-
-static void
-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136000;
-}
-
-static void
-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616000;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e900;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e900;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e900;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ec00;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ec00;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ec00;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ed00;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ed00;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ed00;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36800;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136800;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616800;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e000;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e010;
-}
-
-static void
-Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135900;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ea00;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ea00;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ea00;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f000;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f000;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f000;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f100;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f100;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f100;
-}
-
-static void
-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f200;
-}
-
-static void
-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f200;
-}
-
-static void
-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f200;
-}
-
-static void
-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70c2;
-}
-
-static void
-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70e2;
-}
-
-static void
-Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70d2;
-}
-
-static void
-Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270d2;
-}
-
-static void
-Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x370d2;
-}
-
-static void
-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70f2;
-}
-
-static void
-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf10000;
-}
-
-static void
-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf12000;
-}
-
-static void
-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf11000;
-}
-
-static void
-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf13000;
-}
-
-static void
-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7042;
-}
-
-static void
-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7052;
-}
-
-static void
-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x47082;
-}
-
-static void
-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x57082;
-}
-
-static void
-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7062;
-}
-
-static void
-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7072;
-}
-
-static void
-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7002;
-}
-
-static void
-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7012;
-}
-
-static void
-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7022;
-}
-
-static void
-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7032;
-}
-
-static void
-Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7082;
-}
-
-static void
-Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x27082;
-}
-
-static void
-Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x37082;
-}
-
-static void
-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf19000;
-}
-
-static void
-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf18000;
-}
-
-static void
-Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135300;
-}
-
-static void
-Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35300;
-}
-
-static void
-Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615300;
-}
-
-static void
-Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35a00;
-}
-
-static void
-Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135a00;
-}
-
-static void
-Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615a00;
-}
-
-static void
-Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35b00;
-}
-
-static void
-Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135b00;
-}
-
-static void
-Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615b00;
-}
-
-static void
-Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35c00;
-}
-
-static void
-Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135c00;
-}
-
-static void
-Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615c00;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50c000;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50d000;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50b000;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50f000;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50e000;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x504000;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505000;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x503000;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x507000;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x506000;
-}
-
-static void
-Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1f000;
-}
-
-static void
-Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x501000;
-}
-
-static void
-Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x509000;
-}
-
-static void
-Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e000;
-}
-
-static void
-Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e000;
-}
-
-static void
-Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e000;
-}
-
-static void
-Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x330000;
-}
-
-static void
-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x430000;
-}
-
-static void
-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530000;
-}
-
-static void
-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x630000;
-}
-
-static void
-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730000;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40e000;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40f000;
-}
-
-static void
-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230000;
-}
-
-static void
-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb002;
-}
-
-static void
-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf002;
-}
-
-static void
-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe002;
-}
-
-static void
-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30c00;
-}
-
-static void
-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130c00;
-}
-
-static void
-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610c00;
-}
-
-static void
-Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc20000;
-}
-
-static void
-Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd20000;
-}
-
-static void
-Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe20000;
-}
-
-static void
-Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf20000;
-}
-
-static void
-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x820000;
-}
-
-static void
-Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e60;
-}
-
-static void
-Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e600;
-}
-
-static void
-Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0000;
-}
-
-static void
-Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1000;
-}
-
-static void
-Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1200;
-}
-
-static void
-Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe2000;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
- Opcode_rur_threadptr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
- Opcode_wur_threadptr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
- Opcode_rsr_176_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
- Opcode_rsr_208_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
- Opcode_rsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
- Opcode_wsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
- Opcode_xsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
- Opcode_rsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
- Opcode_wsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
- Opcode_xsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
- Opcode_rsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
- Opcode_wsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
- Opcode_xsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
- Opcode_rsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
- Opcode_wsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
- Opcode_xsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
- Opcode_rsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
- Opcode_wsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
- Opcode_xsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
- Opcode_rsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
- Opcode_wsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
- Opcode_xsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
- Opcode_mul_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
- Opcode_mul_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
- Opcode_mul_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
- Opcode_mul_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
- Opcode_mula_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
- Opcode_mula_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
- Opcode_mula_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
- Opcode_mula_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
- Opcode_muls_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
- Opcode_muls_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
- Opcode_muls_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
- Opcode_muls_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
- Opcode_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
- Opcode_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
- Opcode_rsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
- Opcode_wsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
- Opcode_xsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
- Opcode_rsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
- Opcode_wsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
- Opcode_xsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
- Opcode_rsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
- Opcode_wsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
- Opcode_xsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
- Opcode_rsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
- Opcode_wsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
- Opcode_xsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
- Opcode_rsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
- Opcode_wsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
- Opcode_xsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
- Opcode_rsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
- Opcode_wsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
- Opcode_xsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
- Opcode_wsr_mmid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
- Opcode_ipfl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
- Opcode_ihu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
- Opcode_iiu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
- Opcode_dpfl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
- Opcode_dhu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
- Opcode_diu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
- Opcode_rsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
- Opcode_wsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
- Opcode_xsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
- Opcode_ldpte_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
- Opcode_hwwitlba_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
- Opcode_hwwdtlba_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
- Opcode_clamps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
- Opcode_quou_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
- Opcode_quos_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
- Opcode_remu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
- Opcode_rems_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
- Opcode_rur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
- Opcode_wur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
- Opcode_read_impwire_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
- Opcode_setb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
- Opcode_clrb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
- Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
-};
-
-\f
-/* Opcode table. */
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", 0 /* xt_iclass_excw */,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", 1 /* xt_iclass_rfe */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", 2 /* xt_iclass_rfde */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", 3 /* xt_iclass_syscall */,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "simcall", 4 /* xt_iclass_simcall */,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "call12", 5 /* xt_iclass_call12 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", 6 /* xt_iclass_call8 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", 7 /* xt_iclass_call4 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", 8 /* xt_iclass_callx12 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", 9 /* xt_iclass_callx8 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", 10 /* xt_iclass_callx4 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", 11 /* xt_iclass_entry */,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", 12 /* xt_iclass_movsp */,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", 13 /* xt_iclass_rotw */,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", 14 /* xt_iclass_retw */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", 14 /* xt_iclass_retw */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", 15 /* xt_iclass_rfwou */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", 15 /* xt_iclass_rfwou */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", 16 /* xt_iclass_l32e */,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", 17 /* xt_iclass_s32e */,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", 24 /* xt_iclass_add.n */,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", 25 /* xt_iclass_addi.n */,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", 26 /* xt_iclass_bz6 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", 26 /* xt_iclass_bz6 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", 27 /* xt_iclass_ill.n */,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", 28 /* xt_iclass_loadi4 */,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", 29 /* xt_iclass_mov.n */,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", 30 /* xt_iclass_movi.n */,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", 31 /* xt_iclass_nopn */,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", 32 /* xt_iclass_retn */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", 33 /* xt_iclass_storei4 */,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "rur.threadptr", 34 /* rur_threadptr */,
- 0,
- Opcode_rur_threadptr_encode_fns, 0, 0 },
- { "wur.threadptr", 35 /* wur_threadptr */,
- 0,
- Opcode_wur_threadptr_encode_fns, 0, 0 },
- { "addi", 36 /* xt_iclass_addi */,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", 37 /* xt_iclass_addmi */,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", 39 /* xt_iclass_bit */,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", 39 /* xt_iclass_bit */,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", 39 /* xt_iclass_bit */,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", 41 /* xt_iclass_bsi8b */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", 41 /* xt_iclass_bsi8b */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", 42 /* xt_iclass_bsi8u */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", 42 /* xt_iclass_bsi8u */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", 45 /* xt_iclass_call0 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", 46 /* xt_iclass_callx0 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", 47 /* xt_iclass_exti */,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", 48 /* xt_iclass_ill */,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", 49 /* xt_iclass_jump */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", 50 /* xt_iclass_jumpx */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", 51 /* xt_iclass_l16ui */,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", 52 /* xt_iclass_l16si */,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", 53 /* xt_iclass_l32i */,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", 54 /* xt_iclass_l32r */,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", 55 /* xt_iclass_l8i */,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", 56 /* xt_iclass_loop */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", 57 /* xt_iclass_loopz */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", 57 /* xt_iclass_loopz */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", 58 /* xt_iclass_movi */,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", 59 /* xt_iclass_movz */,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", 59 /* xt_iclass_movz */,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", 59 /* xt_iclass_movz */,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", 59 /* xt_iclass_movz */,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", 60 /* xt_iclass_neg */,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", 60 /* xt_iclass_neg */,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", 61 /* xt_iclass_nop */,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", 62 /* xt_iclass_return */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "s16i", 63 /* xt_iclass_s16i */,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", 64 /* xt_iclass_s32i */,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s8i", 65 /* xt_iclass_s8i */,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", 67 /* xt_iclass_sari */,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", 68 /* xt_iclass_shifts */,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", 69 /* xt_iclass_shiftst */,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", 70 /* xt_iclass_shiftt */,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", 70 /* xt_iclass_shiftt */,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", 71 /* xt_iclass_slli */,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", 72 /* xt_iclass_srai */,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", 73 /* xt_iclass_srli */,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", 74 /* xt_iclass_memw */,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", 75 /* xt_iclass_extw */,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", 76 /* xt_iclass_isync */,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", 77 /* xt_iclass_sync */,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", 77 /* xt_iclass_sync */,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", 77 /* xt_iclass_sync */,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", 78 /* xt_iclass_rsil */,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.176", 94 /* xt_iclass_rsr.176 */,
- 0,
- Opcode_rsr_176_encode_fns, 0, 0 },
- { "rsr.208", 95 /* xt_iclass_rsr.208 */,
- 0,
- Opcode_rsr_208_encode_fns, 0, 0 },
- { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
- 0,
- Opcode_rsr_epc5_encode_fns, 0, 0 },
- { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
- 0,
- Opcode_wsr_epc5_encode_fns, 0, 0 },
- { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
- 0,
- Opcode_xsr_epc5_encode_fns, 0, 0 },
- { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
- 0,
- Opcode_rsr_excsave5_encode_fns, 0, 0 },
- { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
- 0,
- Opcode_wsr_excsave5_encode_fns, 0, 0 },
- { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
- 0,
- Opcode_xsr_excsave5_encode_fns, 0, 0 },
- { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
- 0,
- Opcode_rsr_epc6_encode_fns, 0, 0 },
- { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
- 0,
- Opcode_wsr_epc6_encode_fns, 0, 0 },
- { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
- 0,
- Opcode_xsr_epc6_encode_fns, 0, 0 },
- { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
- 0,
- Opcode_rsr_excsave6_encode_fns, 0, 0 },
- { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
- 0,
- Opcode_wsr_excsave6_encode_fns, 0, 0 },
- { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
- 0,
- Opcode_xsr_excsave6_encode_fns, 0, 0 },
- { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
- 0,
- Opcode_rsr_epc7_encode_fns, 0, 0 },
- { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
- 0,
- Opcode_wsr_epc7_encode_fns, 0, 0 },
- { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
- 0,
- Opcode_xsr_epc7_encode_fns, 0, 0 },
- { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
- 0,
- Opcode_rsr_excsave7_encode_fns, 0, 0 },
- { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
- 0,
- Opcode_wsr_excsave7_encode_fns, 0, 0 },
- { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
- 0,
- Opcode_xsr_excsave7_encode_fns, 0, 0 },
- { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
- 0,
- Opcode_rsr_eps5_encode_fns, 0, 0 },
- { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
- 0,
- Opcode_wsr_eps5_encode_fns, 0, 0 },
- { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
- 0,
- Opcode_xsr_eps5_encode_fns, 0, 0 },
- { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
- 0,
- Opcode_rsr_eps6_encode_fns, 0, 0 },
- { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
- 0,
- Opcode_wsr_eps6_encode_fns, 0, 0 },
- { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
- 0,
- Opcode_xsr_eps6_encode_fns, 0, 0 },
- { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
- 0,
- Opcode_rsr_eps7_encode_fns, 0, 0 },
- { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
- 0,
- Opcode_wsr_eps7_encode_fns, 0, 0 },
- { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
- 0,
- Opcode_xsr_eps7_encode_fns, 0, 0 },
- { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", 174 /* xt_iclass_rsr.prid */,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_ll_encode_fns, 0, 0 },
- { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_hl_encode_fns, 0, 0 },
- { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_lh_encode_fns, 0, 0 },
- { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_hh_encode_fns, 0, 0 },
- { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_ll_encode_fns, 0, 0 },
- { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_hl_encode_fns, 0, 0 },
- { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_lh_encode_fns, 0, 0 },
- { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_hh_encode_fns, 0, 0 },
- { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_ll_encode_fns, 0, 0 },
- { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_hl_encode_fns, 0, 0 },
- { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_lh_encode_fns, 0, 0 },
- { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_hh_encode_fns, 0, 0 },
- { "mul.da.ll", 180 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_ll_encode_fns, 0, 0 },
- { "mul.da.hl", 180 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_hl_encode_fns, 0, 0 },
- { "mul.da.lh", 180 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_lh_encode_fns, 0, 0 },
- { "mul.da.hh", 180 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_hh_encode_fns, 0, 0 },
- { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_ll_encode_fns, 0, 0 },
- { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_hl_encode_fns, 0, 0 },
- { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_lh_encode_fns, 0, 0 },
- { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_hh_encode_fns, 0, 0 },
- { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_ll_encode_fns, 0, 0 },
- { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_hl_encode_fns, 0, 0 },
- { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_lh_encode_fns, 0, 0 },
- { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_hh_encode_fns, 0, 0 },
- { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_ll_encode_fns, 0, 0 },
- { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_hl_encode_fns, 0, 0 },
- { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_lh_encode_fns, 0, 0 },
- { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_hh_encode_fns, 0, 0 },
- { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_ll_encode_fns, 0, 0 },
- { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_hl_encode_fns, 0, 0 },
- { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_lh_encode_fns, 0, 0 },
- { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_hh_encode_fns, 0, 0 },
- { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_ll_encode_fns, 0, 0 },
- { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_hl_encode_fns, 0, 0 },
- { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_lh_encode_fns, 0, 0 },
- { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_hh_encode_fns, 0, 0 },
- { "mula.da.ll", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_ll_encode_fns, 0, 0 },
- { "mula.da.hl", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_hl_encode_fns, 0, 0 },
- { "mula.da.lh", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_lh_encode_fns, 0, 0 },
- { "mula.da.hh", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_hh_encode_fns, 0, 0 },
- { "muls.da.ll", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_ll_encode_fns, 0, 0 },
- { "muls.da.hl", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_hl_encode_fns, 0, 0 },
- { "muls.da.lh", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_lh_encode_fns, 0, 0 },
- { "muls.da.hh", 184 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_hh_encode_fns, 0, 0 },
- { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_ll_encode_fns, 0, 0 },
- { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_hl_encode_fns, 0, 0 },
- { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_lh_encode_fns, 0, 0 },
- { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_hh_encode_fns, 0, 0 },
- { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_ll_encode_fns, 0, 0 },
- { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_hl_encode_fns, 0, 0 },
- { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_lh_encode_fns, 0, 0 },
- { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_hh_encode_fns, 0, 0 },
- { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
- { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
- { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
- { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
- { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
- { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
- { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
- { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
- { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
- { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
- { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
- { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
- { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
- { "lddec", 188 /* xt_iclass_mac16_l */,
- 0,
- Opcode_lddec_encode_fns, 0, 0 },
- { "ldinc", 188 /* xt_iclass_mac16_l */,
- 0,
- Opcode_ldinc_encode_fns, 0, 0 },
- { "mul16u", 189 /* xt_iclass_mul16 */,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", 189 /* xt_iclass_mul16 */,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "rsr.m0", 190 /* xt_iclass_rsr.m0 */,
- 0,
- Opcode_rsr_m0_encode_fns, 0, 0 },
- { "wsr.m0", 191 /* xt_iclass_wsr.m0 */,
- 0,
- Opcode_wsr_m0_encode_fns, 0, 0 },
- { "xsr.m0", 192 /* xt_iclass_xsr.m0 */,
- 0,
- Opcode_xsr_m0_encode_fns, 0, 0 },
- { "rsr.m1", 193 /* xt_iclass_rsr.m1 */,
- 0,
- Opcode_rsr_m1_encode_fns, 0, 0 },
- { "wsr.m1", 194 /* xt_iclass_wsr.m1 */,
- 0,
- Opcode_wsr_m1_encode_fns, 0, 0 },
- { "xsr.m1", 195 /* xt_iclass_xsr.m1 */,
- 0,
- Opcode_xsr_m1_encode_fns, 0, 0 },
- { "rsr.m2", 196 /* xt_iclass_rsr.m2 */,
- 0,
- Opcode_rsr_m2_encode_fns, 0, 0 },
- { "wsr.m2", 197 /* xt_iclass_wsr.m2 */,
- 0,
- Opcode_wsr_m2_encode_fns, 0, 0 },
- { "xsr.m2", 198 /* xt_iclass_xsr.m2 */,
- 0,
- Opcode_xsr_m2_encode_fns, 0, 0 },
- { "rsr.m3", 199 /* xt_iclass_rsr.m3 */,
- 0,
- Opcode_rsr_m3_encode_fns, 0, 0 },
- { "wsr.m3", 200 /* xt_iclass_wsr.m3 */,
- 0,
- Opcode_wsr_m3_encode_fns, 0, 0 },
- { "xsr.m3", 201 /* xt_iclass_xsr.m3 */,
- 0,
- Opcode_xsr_m3_encode_fns, 0, 0 },
- { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */,
- 0,
- Opcode_rsr_acclo_encode_fns, 0, 0 },
- { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */,
- 0,
- Opcode_wsr_acclo_encode_fns, 0, 0 },
- { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */,
- 0,
- Opcode_xsr_acclo_encode_fns, 0, 0 },
- { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */,
- 0,
- Opcode_rsr_acchi_encode_fns, 0, 0 },
- { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */,
- 0,
- Opcode_wsr_acchi_encode_fns, 0, 0 },
- { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */,
- 0,
- Opcode_xsr_acchi_encode_fns, 0, 0 },
- { "rfi", 208 /* xt_iclass_rfi */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", 209 /* xt_iclass_wait */,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", 211 /* xt_iclass_wsr.intset */,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", 216 /* xt_iclass_break */,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", 217 /* xt_iclass_break.n */,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", 242 /* xt_iclass_rsr.icount */,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", 243 /* xt_iclass_wsr.icount */,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", 244 /* xt_iclass_xsr.icount */,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "rfdo", 251 /* xt_iclass_rfdo */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", 252 /* xt_iclass_rfdd */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */,
- 0,
- Opcode_wsr_mmid_encode_fns, 0, 0 },
- { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "ipf", 266 /* xt_iclass_icache */,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", 266 /* xt_iclass_icache */,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "ipfl", 267 /* xt_iclass_icache_lock */,
- 0,
- Opcode_ipfl_encode_fns, 0, 0 },
- { "ihu", 267 /* xt_iclass_icache_lock */,
- 0,
- Opcode_ihu_encode_fns, 0, 0 },
- { "iiu", 267 /* xt_iclass_icache_lock */,
- 0,
- Opcode_iiu_encode_fns, 0, 0 },
- { "iii", 268 /* xt_iclass_icache_inv */,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", 269 /* xt_iclass_licx */,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", 269 /* xt_iclass_licx */,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", 270 /* xt_iclass_sicx */,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", 270 /* xt_iclass_sicx */,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", 271 /* xt_iclass_dcache */,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", 271 /* xt_iclass_dcache */,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwb", 272 /* xt_iclass_dcache_ind */,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", 272 /* xt_iclass_dcache_ind */,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", 273 /* xt_iclass_dcache_inv */,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", 273 /* xt_iclass_dcache_inv */,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", 274 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", 274 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", 274 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", 274 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "dpfl", 275 /* xt_iclass_dcache_lock */,
- 0,
- Opcode_dpfl_encode_fns, 0, 0 },
- { "dhu", 275 /* xt_iclass_dcache_lock */,
- 0,
- Opcode_dhu_encode_fns, 0, 0 },
- { "diu", 275 /* xt_iclass_dcache_lock */,
- 0,
- Opcode_diu_encode_fns, 0, 0 },
- { "sdct", 276 /* xt_iclass_sdct */,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", 277 /* xt_iclass_ldct */,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */,
- 0,
- Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */,
- 0,
- Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
- { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */,
- 0,
- Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */,
- 0,
- Opcode_rsr_rasid_encode_fns, 0, 0 },
- { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */,
- 0,
- Opcode_wsr_rasid_encode_fns, 0, 0 },
- { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */,
- 0,
- Opcode_xsr_rasid_encode_fns, 0, 0 },
- { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */,
- 0,
- Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
- { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */,
- 0,
- Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
- { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */,
- 0,
- Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
- { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */,
- 0,
- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
- { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */,
- 0,
- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
- { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */,
- 0,
- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
- { "idtlb", 290 /* xt_iclass_idtlb */,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", 291 /* xt_iclass_rdtlb */,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", 291 /* xt_iclass_rdtlb */,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", 291 /* xt_iclass_rdtlb */,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", 292 /* xt_iclass_wdtlb */,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", 293 /* xt_iclass_iitlb */,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", 294 /* xt_iclass_ritlb */,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", 294 /* xt_iclass_ritlb */,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", 294 /* xt_iclass_ritlb */,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", 295 /* xt_iclass_witlb */,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "ldpte", 296 /* xt_iclass_ldpte */,
- 0,
- Opcode_ldpte_encode_fns, 0, 0 },
- { "hwwitlba", 297 /* xt_iclass_hwwitlba */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_hwwitlba_encode_fns, 0, 0 },
- { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */,
- 0,
- Opcode_hwwdtlba_encode_fns, 0, 0 },
- { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */,
- 0,
- Opcode_rsr_cpenable_encode_fns, 0, 0 },
- { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */,
- 0,
- Opcode_wsr_cpenable_encode_fns, 0, 0 },
- { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */,
- 0,
- Opcode_xsr_cpenable_encode_fns, 0, 0 },
- { "clamps", 302 /* xt_iclass_clamp */,
- 0,
- Opcode_clamps_encode_fns, 0, 0 },
- { "min", 303 /* xt_iclass_minmax */,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", 303 /* xt_iclass_minmax */,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", 303 /* xt_iclass_minmax */,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", 303 /* xt_iclass_minmax */,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", 304 /* xt_iclass_nsa */,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", 304 /* xt_iclass_nsa */,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", 305 /* xt_iclass_sx */,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", 306 /* xt_iclass_l32ai */,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", 307 /* xt_iclass_s32ri */,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", 308 /* xt_iclass_s32c1i */,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "quou", 312 /* xt_iclass_div */,
- 0,
- Opcode_quou_encode_fns, 0, 0 },
- { "quos", 312 /* xt_iclass_div */,
- 0,
- Opcode_quos_encode_fns, 0, 0 },
- { "remu", 312 /* xt_iclass_div */,
- 0,
- Opcode_remu_encode_fns, 0, 0 },
- { "rems", 312 /* xt_iclass_div */,
- 0,
- Opcode_rems_encode_fns, 0, 0 },
- { "mull", 313 /* xt_mul32 */,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "rur.expstate", 314 /* rur_expstate */,
- 0,
- Opcode_rur_expstate_encode_fns, 0, 0 },
- { "wur.expstate", 315 /* wur_expstate */,
- 0,
- Opcode_wur_expstate_encode_fns, 0, 0 },
- { "read_impwire", 316 /* iclass_READ_IMPWIRE */,
- 0,
- Opcode_read_impwire_encode_fns, 0, 0 },
- { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */,
- 0,
- Opcode_setb_expstate_encode_fns, 0, 0 },
- { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */,
- 0,
- Opcode_clrb_expstate_encode_fns, 0, 0 },
- { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */,
- 0,
- Opcode_wrmsk_expstate_encode_fns, 0, 0 }
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return 79; /* ill */
- break;
- case 2:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 98; /* ret */
- case 1:
- return 14; /* retw */
- case 2:
- return 81; /* jx */
- }
- break;
- case 3:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 77; /* callx0 */
- case 1:
- return 10; /* callx4 */
- case 2:
- return 9; /* callx8 */
- case 3:
- return 8; /* callx12 */
- }
- break;
- }
- break;
- case 1:
- return 12; /* movsp */
- case 2:
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 116; /* isync */
- case 1:
- return 117; /* rsync */
- case 2:
- return 118; /* esync */
- case 3:
- return 119; /* dsync */
- case 8:
- return 0; /* excw */
- case 12:
- return 114; /* memw */
- case 13:
- return 115; /* extw */
- case 15:
- return 97; /* nop */
- }
- }
- break;
- case 3:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return 1; /* rfe */
- case 2:
- return 2; /* rfde */
- case 4:
- return 16; /* rfwo */
- case 5:
- return 17; /* rfwu */
- }
- break;
- case 1:
- return 310; /* rfi */
- }
- break;
- case 4:
- return 318; /* break */
- case 5:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 3; /* syscall */
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 4; /* simcall */
- break;
- }
- break;
- case 6:
- return 120; /* rsil */
- case 7:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 311; /* waiti */
- break;
- }
- break;
- case 1:
- return 49; /* and */
- case 2:
- return 50; /* or */
- case 3:
- return 51; /* xor */
- case 4:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 102; /* ssr */
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 103; /* ssl */
- break;
- case 2:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 104; /* ssa8l */
- break;
- case 3:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 105; /* ssa8b */
- break;
- case 4:
- if (Field_thi3_Slot_inst_get (insn) == 0)
- return 106; /* ssai */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 13; /* rotw */
- break;
- case 14:
- return 426; /* nsa */
- case 15:
- return 427; /* nsau */
- }
- break;
- case 5:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 1:
- return 416; /* hwwitlba */
- case 3:
- return 412; /* ritlb0 */
- case 4:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 410; /* iitlb */
- break;
- case 5:
- return 411; /* pitlb */
- case 6:
- return 414; /* witlb */
- case 7:
- return 413; /* ritlb1 */
- case 9:
- return 417; /* hwwdtlba */
- case 11:
- return 407; /* rdtlb0 */
- case 12:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 405; /* idtlb */
- break;
- case 13:
- return 406; /* pdtlb */
- case 14:
- return 409; /* wdtlb */
- case 15:
- return 408; /* rdtlb1 */
- }
- break;
- case 6:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return 95; /* neg */
- case 1:
- return 96; /* abs */
- }
- break;
- case 8:
- return 41; /* add */
- case 9:
- return 43; /* addx2 */
- case 10:
- return 44; /* addx4 */
- case 11:
- return 45; /* addx8 */
- case 12:
- return 42; /* sub */
- case 13:
- return 46; /* subx2 */
- case 14:
- return 47; /* subx4 */
- case 15:
- return 48; /* subx8 */
- }
- break;
- case 1:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- case 1:
- return 111; /* slli */
- case 2:
- case 3:
- return 112; /* srai */
- case 4:
- return 113; /* srli */
- case 6:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 129; /* xsr.lbeg */
- case 1:
- return 123; /* xsr.lend */
- case 2:
- return 126; /* xsr.lcount */
- case 3:
- return 132; /* xsr.sar */
- case 5:
- return 135; /* xsr.litbase */
- case 12:
- return 434; /* xsr.scompare1 */
- case 16:
- return 306; /* xsr.acclo */
- case 17:
- return 309; /* xsr.acchi */
- case 32:
- return 294; /* xsr.m0 */
- case 33:
- return 297; /* xsr.m1 */
- case 34:
- return 300; /* xsr.m2 */
- case 35:
- return 303; /* xsr.m3 */
- case 72:
- return 22; /* xsr.windowbase */
- case 73:
- return 25; /* xsr.windowstart */
- case 83:
- return 395; /* xsr.ptevaddr */
- case 90:
- return 398; /* xsr.rasid */
- case 91:
- return 401; /* xsr.itlbcfg */
- case 92:
- return 404; /* xsr.dtlbcfg */
- case 96:
- return 340; /* xsr.ibreakenable */
- case 104:
- return 352; /* xsr.ddr */
- case 128:
- return 334; /* xsr.ibreaka0 */
- case 129:
- return 337; /* xsr.ibreaka1 */
- case 144:
- return 322; /* xsr.dbreaka0 */
- case 145:
- return 328; /* xsr.dbreaka1 */
- case 160:
- return 325; /* xsr.dbreakc0 */
- case 161:
- return 331; /* xsr.dbreakc1 */
- case 177:
- return 143; /* xsr.epc1 */
- case 178:
- return 149; /* xsr.epc2 */
- case 179:
- return 155; /* xsr.epc3 */
- case 180:
- return 161; /* xsr.epc4 */
- case 181:
- return 167; /* xsr.epc5 */
- case 182:
- return 173; /* xsr.epc6 */
- case 183:
- return 179; /* xsr.epc7 */
- case 192:
- return 206; /* xsr.depc */
- case 194:
- return 185; /* xsr.eps2 */
- case 195:
- return 188; /* xsr.eps3 */
- case 196:
- return 191; /* xsr.eps4 */
- case 197:
- return 194; /* xsr.eps5 */
- case 198:
- return 197; /* xsr.eps6 */
- case 199:
- return 200; /* xsr.eps7 */
- case 209:
- return 146; /* xsr.excsave1 */
- case 210:
- return 152; /* xsr.excsave2 */
- case 211:
- return 158; /* xsr.excsave3 */
- case 212:
- return 164; /* xsr.excsave4 */
- case 213:
- return 170; /* xsr.excsave5 */
- case 214:
- return 176; /* xsr.excsave6 */
- case 215:
- return 182; /* xsr.excsave7 */
- case 224:
- return 420; /* xsr.cpenable */
- case 228:
- return 317; /* xsr.intenable */
- case 230:
- return 140; /* xsr.ps */
- case 231:
- return 219; /* xsr.vecbase */
- case 232:
- return 209; /* xsr.exccause */
- case 233:
- return 343; /* xsr.debugcause */
- case 234:
- return 358; /* xsr.ccount */
- case 236:
- return 346; /* xsr.icount */
- case 237:
- return 349; /* xsr.icountlevel */
- case 238:
- return 203; /* xsr.excvaddr */
- case 240:
- return 361; /* xsr.ccompare0 */
- case 241:
- return 364; /* xsr.ccompare1 */
- case 242:
- return 367; /* xsr.ccompare2 */
- case 244:
- return 212; /* xsr.misc0 */
- case 245:
- return 215; /* xsr.misc1 */
- }
- break;
- case 8:
- return 108; /* src */
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 109; /* srl */
- break;
- case 10:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 107; /* sll */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 110; /* sra */
- break;
- case 12:
- return 290; /* mul16u */
- case 13:
- return 291; /* mul16s */
- case 15:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 374; /* lict */
- case 1:
- return 376; /* sict */
- case 2:
- return 375; /* licw */
- case 3:
- return 377; /* sicw */
- case 8:
- return 392; /* ldct */
- case 9:
- return 391; /* sdct */
- case 14:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 353; /* rfdo */
- if (Field_t_Slot_inst_get (insn) == 1)
- return 354; /* rfdd */
- break;
- case 15:
- return 415; /* ldpte */
- }
- break;
- }
- break;
- case 2:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 8:
- return 439; /* mull */
- case 12:
- return 435; /* quou */
- case 13:
- return 436; /* quos */
- case 14:
- return 437; /* remu */
- case 15:
- return 438; /* rems */
- }
- break;
- case 3:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 127; /* rsr.lbeg */
- case 1:
- return 121; /* rsr.lend */
- case 2:
- return 124; /* rsr.lcount */
- case 3:
- return 130; /* rsr.sar */
- case 5:
- return 133; /* rsr.litbase */
- case 12:
- return 432; /* rsr.scompare1 */
- case 16:
- return 304; /* rsr.acclo */
- case 17:
- return 307; /* rsr.acchi */
- case 32:
- return 292; /* rsr.m0 */
- case 33:
- return 295; /* rsr.m1 */
- case 34:
- return 298; /* rsr.m2 */
- case 35:
- return 301; /* rsr.m3 */
- case 72:
- return 20; /* rsr.windowbase */
- case 73:
- return 23; /* rsr.windowstart */
- case 83:
- return 394; /* rsr.ptevaddr */
- case 90:
- return 396; /* rsr.rasid */
- case 91:
- return 399; /* rsr.itlbcfg */
- case 92:
- return 402; /* rsr.dtlbcfg */
- case 96:
- return 338; /* rsr.ibreakenable */
- case 104:
- return 350; /* rsr.ddr */
- case 128:
- return 332; /* rsr.ibreaka0 */
- case 129:
- return 335; /* rsr.ibreaka1 */
- case 144:
- return 320; /* rsr.dbreaka0 */
- case 145:
- return 326; /* rsr.dbreaka1 */
- case 160:
- return 323; /* rsr.dbreakc0 */
- case 161:
- return 329; /* rsr.dbreakc1 */
- case 176:
- return 136; /* rsr.176 */
- case 177:
- return 141; /* rsr.epc1 */
- case 178:
- return 147; /* rsr.epc2 */
- case 179:
- return 153; /* rsr.epc3 */
- case 180:
- return 159; /* rsr.epc4 */
- case 181:
- return 165; /* rsr.epc5 */
- case 182:
- return 171; /* rsr.epc6 */
- case 183:
- return 177; /* rsr.epc7 */
- case 192:
- return 204; /* rsr.depc */
- case 194:
- return 183; /* rsr.eps2 */
- case 195:
- return 186; /* rsr.eps3 */
- case 196:
- return 189; /* rsr.eps4 */
- case 197:
- return 192; /* rsr.eps5 */
- case 198:
- return 195; /* rsr.eps6 */
- case 199:
- return 198; /* rsr.eps7 */
- case 208:
- return 137; /* rsr.208 */
- case 209:
- return 144; /* rsr.excsave1 */
- case 210:
- return 150; /* rsr.excsave2 */
- case 211:
- return 156; /* rsr.excsave3 */
- case 212:
- return 162; /* rsr.excsave4 */
- case 213:
- return 168; /* rsr.excsave5 */
- case 214:
- return 174; /* rsr.excsave6 */
- case 215:
- return 180; /* rsr.excsave7 */
- case 224:
- return 418; /* rsr.cpenable */
- case 226:
- return 312; /* rsr.interrupt */
- case 228:
- return 315; /* rsr.intenable */
- case 230:
- return 138; /* rsr.ps */
- case 231:
- return 217; /* rsr.vecbase */
- case 232:
- return 207; /* rsr.exccause */
- case 233:
- return 341; /* rsr.debugcause */
- case 234:
- return 356; /* rsr.ccount */
- case 235:
- return 216; /* rsr.prid */
- case 236:
- return 344; /* rsr.icount */
- case 237:
- return 347; /* rsr.icountlevel */
- case 238:
- return 201; /* rsr.excvaddr */
- case 240:
- return 359; /* rsr.ccompare0 */
- case 241:
- return 362; /* rsr.ccompare1 */
- case 242:
- return 365; /* rsr.ccompare2 */
- case 244:
- return 210; /* rsr.misc0 */
- case 245:
- return 213; /* rsr.misc1 */
- }
- break;
- case 1:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 128; /* wsr.lbeg */
- case 1:
- return 122; /* wsr.lend */
- case 2:
- return 125; /* wsr.lcount */
- case 3:
- return 131; /* wsr.sar */
- case 5:
- return 134; /* wsr.litbase */
- case 12:
- return 433; /* wsr.scompare1 */
- case 16:
- return 305; /* wsr.acclo */
- case 17:
- return 308; /* wsr.acchi */
- case 32:
- return 293; /* wsr.m0 */
- case 33:
- return 296; /* wsr.m1 */
- case 34:
- return 299; /* wsr.m2 */
- case 35:
- return 302; /* wsr.m3 */
- case 72:
- return 21; /* wsr.windowbase */
- case 73:
- return 24; /* wsr.windowstart */
- case 83:
- return 393; /* wsr.ptevaddr */
- case 89:
- return 355; /* wsr.mmid */
- case 90:
- return 397; /* wsr.rasid */
- case 91:
- return 400; /* wsr.itlbcfg */
- case 92:
- return 403; /* wsr.dtlbcfg */
- case 96:
- return 339; /* wsr.ibreakenable */
- case 104:
- return 351; /* wsr.ddr */
- case 128:
- return 333; /* wsr.ibreaka0 */
- case 129:
- return 336; /* wsr.ibreaka1 */
- case 144:
- return 321; /* wsr.dbreaka0 */
- case 145:
- return 327; /* wsr.dbreaka1 */
- case 160:
- return 324; /* wsr.dbreakc0 */
- case 161:
- return 330; /* wsr.dbreakc1 */
- case 177:
- return 142; /* wsr.epc1 */
- case 178:
- return 148; /* wsr.epc2 */
- case 179:
- return 154; /* wsr.epc3 */
- case 180:
- return 160; /* wsr.epc4 */
- case 181:
- return 166; /* wsr.epc5 */
- case 182:
- return 172; /* wsr.epc6 */
- case 183:
- return 178; /* wsr.epc7 */
- case 192:
- return 205; /* wsr.depc */
- case 194:
- return 184; /* wsr.eps2 */
- case 195:
- return 187; /* wsr.eps3 */
- case 196:
- return 190; /* wsr.eps4 */
- case 197:
- return 193; /* wsr.eps5 */
- case 198:
- return 196; /* wsr.eps6 */
- case 199:
- return 199; /* wsr.eps7 */
- case 209:
- return 145; /* wsr.excsave1 */
- case 210:
- return 151; /* wsr.excsave2 */
- case 211:
- return 157; /* wsr.excsave3 */
- case 212:
- return 163; /* wsr.excsave4 */
- case 213:
- return 169; /* wsr.excsave5 */
- case 214:
- return 175; /* wsr.excsave6 */
- case 215:
- return 181; /* wsr.excsave7 */
- case 224:
- return 419; /* wsr.cpenable */
- case 226:
- return 313; /* wsr.intset */
- case 227:
- return 314; /* wsr.intclear */
- case 228:
- return 316; /* wsr.intenable */
- case 230:
- return 139; /* wsr.ps */
- case 231:
- return 218; /* wsr.vecbase */
- case 232:
- return 208; /* wsr.exccause */
- case 233:
- return 342; /* wsr.debugcause */
- case 234:
- return 357; /* wsr.ccount */
- case 236:
- return 345; /* wsr.icount */
- case 237:
- return 348; /* wsr.icountlevel */
- case 238:
- return 202; /* wsr.excvaddr */
- case 240:
- return 360; /* wsr.ccompare0 */
- case 241:
- return 363; /* wsr.ccompare1 */
- case 242:
- return 366; /* wsr.ccompare2 */
- case 244:
- return 211; /* wsr.misc0 */
- case 245:
- return 214; /* wsr.misc1 */
- }
- break;
- case 2:
- return 428; /* sext */
- case 3:
- return 421; /* clamps */
- case 4:
- return 422; /* min */
- case 5:
- return 423; /* max */
- case 6:
- return 424; /* minu */
- case 7:
- return 425; /* maxu */
- case 8:
- return 91; /* moveqz */
- case 9:
- return 92; /* movnez */
- case 10:
- return 93; /* movltz */
- case 11:
- return 94; /* movgez */
- case 14:
- switch (Field_st_Slot_inst_get (insn))
- {
- case 230:
- return 440; /* rur.expstate */
- case 231:
- return 37; /* rur.threadptr */
- }
- break;
- case 15:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 230:
- return 441; /* wur.expstate */
- case 231:
- return 38; /* wur.threadptr */
- }
- break;
- }
- break;
- case 4:
- case 5:
- return 78; /* extui */
- case 9:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return 18; /* l32e */
- case 4:
- return 19; /* s32e */
- }
- break;
- }
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return 442; /* read_impwire */
- break;
- case 1:
- if (Field_s3to1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return 443; /* setb_expstate */
- if (Field_s3to1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return 444; /* clrb_expstate */
- break;
- case 2:
- if (Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return 445; /* wrmsk_expstate */
- break;
- }
- break;
- case 1:
- return 85; /* l32r */
- case 2:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 86; /* l8ui */
- case 1:
- return 82; /* l16ui */
- case 2:
- return 84; /* l32i */
- case 4:
- return 101; /* s8i */
- case 5:
- return 99; /* s16i */
- case 6:
- return 100; /* s32i */
- case 7:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 384; /* dpfr */
- case 1:
- return 385; /* dpfw */
- case 2:
- return 386; /* dpfro */
- case 3:
- return 387; /* dpfwo */
- case 4:
- return 378; /* dhwb */
- case 5:
- return 379; /* dhwbi */
- case 6:
- return 382; /* dhi */
- case 7:
- return 383; /* dii */
- case 8:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- return 388; /* dpfl */
- case 2:
- return 389; /* dhu */
- case 3:
- return 390; /* diu */
- case 4:
- return 380; /* diwb */
- case 5:
- return 381; /* diwbi */
- }
- break;
- case 12:
- return 368; /* ipf */
- case 13:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- return 370; /* ipfl */
- case 2:
- return 371; /* ihu */
- case 3:
- return 372; /* iiu */
- }
- break;
- case 14:
- return 369; /* ihi */
- case 15:
- return 373; /* iii */
- }
- break;
- case 9:
- return 83; /* l16si */
- case 10:
- return 90; /* movi */
- case 11:
- return 429; /* l32ai */
- case 12:
- return 39; /* addi */
- case 13:
- return 40; /* addmi */
- case 14:
- return 431; /* s32c1i */
- case 15:
- return 430; /* s32ri */
- }
- break;
- case 4:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 281; /* mula.dd.ll.ldinc */
- break;
- case 9:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 283; /* mula.dd.hl.ldinc */
- break;
- case 10:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 285; /* mula.dd.lh.ldinc */
- break;
- case 11:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 287; /* mula.dd.hh.ldinc */
- break;
- }
- break;
- case 1:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 280; /* mula.dd.ll.lddec */
- break;
- case 9:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 282; /* mula.dd.hl.lddec */
- break;
- case 10:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 284; /* mula.dd.lh.lddec */
- break;
- case 11:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 286; /* mula.dd.hh.lddec */
- break;
- }
- break;
- case 2:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 236; /* mul.dd.ll */
- break;
- case 5:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 237; /* mul.dd.hl */
- break;
- case 6:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 238; /* mul.dd.lh */
- break;
- case 7:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 239; /* mul.dd.hh */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 264; /* mula.dd.ll */
- break;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 265; /* mula.dd.hl */
- break;
- case 10:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 266; /* mula.dd.lh */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 267; /* mula.dd.hh */
- break;
- case 12:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 268; /* muls.dd.ll */
- break;
- case 13:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 269; /* muls.dd.hl */
- break;
- case 14:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 270; /* muls.dd.lh */
- break;
- case 15:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 271; /* muls.dd.hh */
- break;
- }
- break;
- case 3:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 228; /* mul.ad.ll */
- break;
- case 5:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 229; /* mul.ad.hl */
- break;
- case 6:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 230; /* mul.ad.lh */
- break;
- case 7:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 231; /* mul.ad.hh */
- break;
- case 8:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 248; /* mula.ad.ll */
- break;
- case 9:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 249; /* mula.ad.hl */
- break;
- case 10:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 250; /* mula.ad.lh */
- break;
- case 11:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 251; /* mula.ad.hh */
- break;
- case 12:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 252; /* muls.ad.ll */
- break;
- case 13:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 253; /* muls.ad.hl */
- break;
- case 14:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 254; /* muls.ad.lh */
- break;
- case 15:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 255; /* muls.ad.hh */
- break;
- }
- break;
- case 4:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 273; /* mula.da.ll.ldinc */
- break;
- case 9:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 275; /* mula.da.hl.ldinc */
- break;
- case 10:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 277; /* mula.da.lh.ldinc */
- break;
- case 11:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 279; /* mula.da.hh.ldinc */
- break;
- }
- break;
- case 5:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 272; /* mula.da.ll.lddec */
- break;
- case 9:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 274; /* mula.da.hl.lddec */
- break;
- case 10:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 276; /* mula.da.lh.lddec */
- break;
- case 11:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 278; /* mula.da.hh.lddec */
- break;
- }
- break;
- case 6:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 232; /* mul.da.ll */
- break;
- case 5:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 233; /* mul.da.hl */
- break;
- case 6:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 234; /* mul.da.lh */
- break;
- case 7:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 235; /* mul.da.hh */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 256; /* mula.da.ll */
- break;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 257; /* mula.da.hl */
- break;
- case 10:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 258; /* mula.da.lh */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 259; /* mula.da.hh */
- break;
- case 12:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 260; /* muls.da.ll */
- break;
- case 13:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 261; /* muls.da.hl */
- break;
- case 14:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 262; /* muls.da.lh */
- break;
- case 15:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 263; /* muls.da.hh */
- break;
- }
- break;
- case 7:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 224; /* umul.aa.ll */
- break;
- case 1:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 225; /* umul.aa.hl */
- break;
- case 2:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 226; /* umul.aa.lh */
- break;
- case 3:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 227; /* umul.aa.hh */
- break;
- case 4:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 220; /* mul.aa.ll */
- break;
- case 5:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 221; /* mul.aa.hl */
- break;
- case 6:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 222; /* mul.aa.lh */
- break;
- case 7:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 223; /* mul.aa.hh */
- break;
- case 8:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 240; /* mula.aa.ll */
- break;
- case 9:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 241; /* mula.aa.hl */
- break;
- case 10:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 242; /* mula.aa.lh */
- break;
- case 11:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 243; /* mula.aa.hh */
- break;
- case 12:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 244; /* muls.aa.ll */
- break;
- case 13:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 245; /* muls.aa.hl */
- break;
- case 14:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 246; /* muls.aa.lh */
- break;
- case 15:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 247; /* muls.aa.hh */
- break;
- }
- break;
- case 8:
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return 289; /* ldinc */
- break;
- case 9:
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return 288; /* lddec */
- break;
- }
- break;
- case 5:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 76; /* call0 */
- case 1:
- return 7; /* call4 */
- case 2:
- return 6; /* call8 */
- case 3:
- return 5; /* call12 */
- }
- break;
- case 6:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 80; /* j */
- case 1:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 72; /* beqz */
- case 1:
- return 73; /* bnez */
- case 2:
- return 75; /* bltz */
- case 3:
- return 74; /* bgez */
- }
- break;
- case 2:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 52; /* beqi */
- case 1:
- return 53; /* bnei */
- case 2:
- return 55; /* blti */
- case 3:
- return 54; /* bgei */
- }
- break;
- case 3:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 11; /* entry */
- case 1:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 8:
- return 87; /* loop */
- case 9:
- return 88; /* loopnez */
- case 10:
- return 89; /* loopgtz */
- }
- break;
- case 2:
- return 59; /* bltui */
- case 3:
- return 58; /* bgeui */
- }
- break;
- }
- break;
- case 7:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 67; /* bnone */
- case 1:
- return 60; /* beq */
- case 2:
- return 63; /* blt */
- case 3:
- return 65; /* bltu */
- case 4:
- return 68; /* ball */
- case 5:
- return 70; /* bbc */
- case 6:
- case 7:
- return 56; /* bbci */
- case 8:
- return 66; /* bany */
- case 9:
- return 61; /* bne */
- case 10:
- return 62; /* bge */
- case 11:
- return 64; /* bgeu */
- case 12:
- return 69; /* bnall */
- case 13:
- return 71; /* bbs */
- case 14:
- case 15:
- return 57; /* bbsi */
- }
- break;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst16b_get (insn))
- {
- case 12:
- switch (Field_i_Slot_inst16b_get (insn))
- {
- case 0:
- return 33; /* movi.n */
- case 1:
- switch (Field_z_Slot_inst16b_get (insn))
- {
- case 0:
- return 28; /* beqz.n */
- case 1:
- return 29; /* bnez.n */
- }
- break;
- }
- break;
- case 13:
- switch (Field_r_Slot_inst16b_get (insn))
- {
- case 0:
- return 32; /* mov.n */
- case 15:
- switch (Field_t_Slot_inst16b_get (insn))
- {
- case 0:
- return 35; /* ret.n */
- case 1:
- return 15; /* retw.n */
- case 2:
- return 319; /* break.n */
- case 3:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return 34; /* nop.n */
- break;
- case 6:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return 30; /* ill.n */
- break;
- }
- break;
- }
- break;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst16a_get (insn))
- {
- case 8:
- return 31; /* l32i.n */
- case 9:
- return 36; /* s32i.n */
- case 10:
- return 26; /* add.n */
- case 11:
- return 27; /* addi.n */
- }
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffffff);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_get,
- Field_rbit2_Slot_inst_get,
- Field_rhi_Slot_inst_get,
- Field_t3_Slot_inst_get,
- Field_tbit2_Slot_inst_get,
- Field_tlo_Slot_inst_get,
- Field_w_Slot_inst_get,
- Field_y_Slot_inst_get,
- Field_x_Slot_inst_get,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- Field_bitindex_Slot_inst_get,
- Field_s3to1_Slot_inst_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_set,
- Field_rbit2_Slot_inst_set,
- Field_rhi_Slot_inst_set,
- Field_t3_Slot_inst_set,
- Field_tbit2_Slot_inst_set,
- Field_tlo_Slot_inst_set,
- Field_w_Slot_inst_set,
- Field_y_Slot_inst_set,
- Field_x_Slot_inst_set,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- Field_bitindex_Slot_inst_set,
- Field_s3to1_Slot_inst_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_get,
- Field_s3to1_Slot_inst16a_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_set,
- Field_s3to1_Slot_inst16a_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_get,
- Field_s3to1_Slot_inst16b_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_set,
- Field_s3to1_Slot_inst16b_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0x8;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xc;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0x8) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc) == 0x8)
- return 1; /* x16a */
- if ((insn[0] & 0xe) == 0xc)
- return 2; /* x16b */
- return -1;
-}
-
-static int length_table[16] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int op0 = insn[0] & 0xf;
- return length_table[op0];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 0 /* little-endian */,
- 3 /* insn_size */, 0,
- 3, formats, format_decoder, length_decoder,
- 3, slots,
- 56 /* num_fields */,
- 93, operands,
- 320, iclasses,
- 446, opcodes, 0,
- 2, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 1, interfaces, 0,
- 0, funcUnits, 0
-};
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_dc233c
-#include "core-dc233c/xtensa-modules.inc.c"
+#include "core-dc233c/xtensa-modules.c.inc"
static XtensaConfig dc233c __attribute__((unused)) = {
.name = "dc233c",
.gdb_regmap = {
.reg = {
-#include "core-dc233c/gdb-config.inc.c"
+#include "core-dc233c/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
--- /dev/null
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2010 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+/* idx ofs bi sz al targno flags cp typ group name */
+XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0)
+XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0)
+XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0)
+XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0)
+XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0)
+XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0)
+XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0)
+XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0)
+XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0)
+XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0)
+XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, 0, 0, 0, 0, 0, 0)
+XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, 0, 0, 0, 0, 0, 0)
+XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, 0, 0, 0, 0, 0, 0)
+XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, 0, 0, 0, 0, 0, 0)
+XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, 0, 0, 0, 0, 0, 0)
+XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, 0, 0, 0, 0, 0, 0)
+XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, 0, 0, 0, 0, 0, 0)
+XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, 0, 0, 0, 0, 0, 0)
+XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, 0, 0, 0, 0, 0, 0)
+XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, 0, 0, 0, 0, 0, 0)
+XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, 0, 0, 0, 0, 0, 0)
+XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, 0, 0, 0, 0, 0, 0)
+XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, 0, 0, 0, 0, 0, 0)
+XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, 0, 0, 0, 0, 0, 0)
+XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, 0, 0, 0, 0, 0, 0)
+XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, 0, 0, 0, 0, 0, 0)
+XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, 0, 0, 0, 0, 0, 0)
+XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, 0, 0, 0, 0, 0, 0)
+XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, 0, 0, 0, 0, 0, 0)
+XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, 0, 0, 0, 0, 0, 0)
+XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, 0, 0, 0, 0, 0, 0)
+XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, 0, 0, 0, 0, 0, 0)
+XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, 0, 0, 0, 0, 0, 0)
+XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, 0, 0, 0, 0, 0, 0)
+XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, 0, 0, 0, 0, 0, 0)
+XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, 0, 0, 0, 0, 0, 0)
+XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, 0, 0, 0, 0, 0, 0)
+XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, 0, 0, 0, 0, 0, 0)
+XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, 0, 0, 0, 0, 0, 0)
+XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, 0, 0, 0, 0, 0, 0)
+XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, 0, 0, 0, 0, 0, 0)
+XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, 0, 0, 0, 0, 0, 0)
+XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, 0, 0, 0, 0, 0, 0)
+XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, 0, 0, 0, 0, 0, 0)
+XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, 0, 0, 0, 0, 0, 0)
+XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo, 0, 0, 0, 0, 0, 0)
+XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi, 0, 0, 0, 0, 0, 0)
+XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0, 0, 0, 0, 0, 0, 0)
+XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1, 0, 0, 0, 0, 0, 0)
+XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, 0, 0, 0, 0, 0, 0)
+XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3, 0, 0, 0, 0, 0, 0)
+XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate, 0, 0, 0, 0, 0, 0)
+XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, 0, 0, 0, 0, 0, 0)
+XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, 0, 0, 0, 0, 0, 0)
+XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, 0, 0, 0, 0, 0, 0)
+XTREG(55, 220, 25, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, 0, 0, 0, 0, 0, 0)
+XTREG(56, 224, 25, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, 0, 0, 0, 0, 0, 0)
+XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, 0, 0, 0, 0, 0, 0)
+XTREG(58, 232, 6, 4, 4, 0x0263, 0x0007, -2, 2, 0x1000, atomctl, 0, 0, 0, 0, 0, 0)
+XTREG(59, 236, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, 0, 0, 0, 0, 0, 0)
+XTREG(60, 240, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, 0, 0, 0, 0, 0, 0)
+XTREG(61, 244, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, 0, 0, 0, 0, 0, 0)
+XTREG(62, 248, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, 0, 0, 0, 0, 0, 0)
+XTREG(63, 252, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, 0, 0, 0, 0, 0, 0)
+XTREG(64, 256, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, 0, 0, 0, 0, 0, 0)
+XTREG(65, 260, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, 0, 0, 0, 0, 0, 0)
+XTREG(66, 264, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, 0, 0, 0, 0, 0, 0)
+XTREG(67, 268, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, 0, 0, 0, 0, 0, 0)
+XTREG(68, 272, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, 0, 0, 0, 0, 0, 0)
+XTREG(69, 276, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, 0, 0, 0, 0, 0, 0)
+XTREG(70, 280, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, 0, 0, 0, 0, 0, 0)
+XTREG(71, 284, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, 0, 0, 0, 0, 0, 0)
+XTREG(72, 288, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7, 0, 0, 0, 0, 0, 0)
+XTREG(73, 292, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, 0, 0, 0, 0, 0, 0)
+XTREG(74, 296, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, 0, 0, 0, 0, 0, 0)
+XTREG(75, 300, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, 0, 0, 0, 0, 0, 0)
+XTREG(76, 304, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, 0, 0, 0, 0, 0, 0)
+XTREG(77, 308, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, 0, 0, 0, 0, 0, 0)
+XTREG(78, 312, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, 0, 0, 0, 0, 0, 0)
+XTREG(79, 316, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7, 0, 0, 0, 0, 0, 0)
+XTREG(80, 320, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, 0, 0, 0, 0, 0, 0)
+XTREG(81, 324, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, 0, 0, 0, 0, 0, 0)
+XTREG(82, 328, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, 0, 0, 0, 0, 0, 0)
+XTREG(83, 332, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, 0, 0, 0, 0, 0, 0)
+XTREG(84, 336, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, 0, 0, 0, 0, 0, 0)
+XTREG(85, 340, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, 0, 0, 0, 0, 0, 0)
+XTREG(86, 344, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7, 0, 0, 0, 0, 0, 0)
+XTREG(87, 348, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, 0, 0, 0, 0, 0, 0)
+XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, 0, 0, 0, 0, 0, 0)
+XTREG(89, 356, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, 0, 0, 0, 0, 0, 0)
+XTREG(90, 360, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, 0, 0, 0, 0, 0, 0)
+XTREG(91, 364, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, 0, 0, 0, 0, 0, 0)
+XTREG(92, 368, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, 0, 0, 0, 0, 0, 0)
+XTREG(93, 372, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, 0, 0, 0, 0, 0, 0)
+XTREG(94, 376, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, 0, 0, 0, 0, 0, 0)
+XTREG(95, 380, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, 0, 0, 0, 0, 0, 0)
+XTREG(96, 384, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, 0, 0, 0, 0, 0, 0)
+XTREG(97, 388, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, 0, 0, 0, 0, 0, 0)
+XTREG(98, 392, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, 0, 0, 0, 0, 0, 0)
+XTREG(99, 396, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, 0, 0, 0, 0, 0, 0)
+XTREG(100, 400, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, 0, 0, 0, 0, 0, 0)
+XTREG(101, 404, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, 0, 0, 0, 0, 0, 0)
+XTREG(102, 408, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2, 0, 0, 0, 0, 0, 0)
+XTREG(103, 412, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0, 0, 0, 0, 0, 0, 0)
+XTREG(104, 416, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, 0, 0, 0, 0, 0, 0)
+XTREG(105, 420, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, 0, 0, 0, 0, 0, 0)
+XTREG(106, 424, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, 0, 0, 0, 0, 0, 0)
+XTREG(107, 428, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, 0, 0, 0, 0, 0, 0)
+XTREG(108, 432, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, 0, 0, 0, 0, 0, 0)
+XTREG(109, 436, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, 0, 0, 0, 0, 0, 0)
+XTREG(110, 440, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, 0, 0, 0, 0, 0, 0)
+XTREG(111, 444, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, 0, 0, 0, 0, 0, 0)
+XTREG(112, 448, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, 0, 0, 0, 0, 0, 0)
+XTREG(113, 452, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, 0, 0, 0, 0, 0, 0)
+XTREG(114, 456, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, 0, 0, 0, 0, 0, 0)
+XTREG(115, 460, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, 0, 0, 0, 0, 0, 0)
+XTREG(116, 464, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, 0, 0, 0, 0, 0, 0)
+XTREG(117, 468, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, 0, 0, 0, 0, 0, 0)
+XTREG(118, 472, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, 0, 0, 0, 0, 0, 0)
+XTREG(119, 476, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, 0, 0, 0, 0, 0, 0)
+XTREG(120, 480, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, 0, 0, 0, 0, 0, 0)
+XTREG_END
+++ /dev/null
-/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
-
- Copyright (c) 2003-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-/* idx ofs bi sz al targno flags cp typ group name */
-XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0)
-XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0)
-XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0)
-XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0)
-XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0)
-XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0)
-XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0)
-XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0)
-XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0)
-XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0)
-XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, 0, 0, 0, 0, 0, 0)
-XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, 0, 0, 0, 0, 0, 0)
-XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, 0, 0, 0, 0, 0, 0)
-XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, 0, 0, 0, 0, 0, 0)
-XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, 0, 0, 0, 0, 0, 0)
-XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, 0, 0, 0, 0, 0, 0)
-XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, 0, 0, 0, 0, 0, 0)
-XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, 0, 0, 0, 0, 0, 0)
-XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, 0, 0, 0, 0, 0, 0)
-XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, 0, 0, 0, 0, 0, 0)
-XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, 0, 0, 0, 0, 0, 0)
-XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, 0, 0, 0, 0, 0, 0)
-XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, 0, 0, 0, 0, 0, 0)
-XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, 0, 0, 0, 0, 0, 0)
-XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, 0, 0, 0, 0, 0, 0)
-XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, 0, 0, 0, 0, 0, 0)
-XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, 0, 0, 0, 0, 0, 0)
-XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, 0, 0, 0, 0, 0, 0)
-XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, 0, 0, 0, 0, 0, 0)
-XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, 0, 0, 0, 0, 0, 0)
-XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, 0, 0, 0, 0, 0, 0)
-XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, 0, 0, 0, 0, 0, 0)
-XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, 0, 0, 0, 0, 0, 0)
-XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, 0, 0, 0, 0, 0, 0)
-XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, 0, 0, 0, 0, 0, 0)
-XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, 0, 0, 0, 0, 0, 0)
-XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, 0, 0, 0, 0, 0, 0)
-XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, 0, 0, 0, 0, 0, 0)
-XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, 0, 0, 0, 0, 0, 0)
-XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, 0, 0, 0, 0, 0, 0)
-XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, 0, 0, 0, 0, 0, 0)
-XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, 0, 0, 0, 0, 0, 0)
-XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, 0, 0, 0, 0, 0, 0)
-XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, 0, 0, 0, 0, 0, 0)
-XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, 0, 0, 0, 0, 0, 0)
-XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo, 0, 0, 0, 0, 0, 0)
-XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi, 0, 0, 0, 0, 0, 0)
-XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0, 0, 0, 0, 0, 0, 0)
-XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1, 0, 0, 0, 0, 0, 0)
-XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, 0, 0, 0, 0, 0, 0)
-XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3, 0, 0, 0, 0, 0, 0)
-XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate, 0, 0, 0, 0, 0, 0)
-XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, 0, 0, 0, 0, 0, 0)
-XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, 0, 0, 0, 0, 0, 0)
-XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, 0, 0, 0, 0, 0, 0)
-XTREG(55, 220, 25, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, 0, 0, 0, 0, 0, 0)
-XTREG(56, 224, 25, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, 0, 0, 0, 0, 0, 0)
-XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, 0, 0, 0, 0, 0, 0)
-XTREG(58, 232, 6, 4, 4, 0x0263, 0x0007, -2, 2, 0x1000, atomctl, 0, 0, 0, 0, 0, 0)
-XTREG(59, 236, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, 0, 0, 0, 0, 0, 0)
-XTREG(60, 240, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, 0, 0, 0, 0, 0, 0)
-XTREG(61, 244, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, 0, 0, 0, 0, 0, 0)
-XTREG(62, 248, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, 0, 0, 0, 0, 0, 0)
-XTREG(63, 252, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, 0, 0, 0, 0, 0, 0)
-XTREG(64, 256, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, 0, 0, 0, 0, 0, 0)
-XTREG(65, 260, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, 0, 0, 0, 0, 0, 0)
-XTREG(66, 264, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, 0, 0, 0, 0, 0, 0)
-XTREG(67, 268, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, 0, 0, 0, 0, 0, 0)
-XTREG(68, 272, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, 0, 0, 0, 0, 0, 0)
-XTREG(69, 276, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, 0, 0, 0, 0, 0, 0)
-XTREG(70, 280, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, 0, 0, 0, 0, 0, 0)
-XTREG(71, 284, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, 0, 0, 0, 0, 0, 0)
-XTREG(72, 288, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7, 0, 0, 0, 0, 0, 0)
-XTREG(73, 292, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, 0, 0, 0, 0, 0, 0)
-XTREG(74, 296, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, 0, 0, 0, 0, 0, 0)
-XTREG(75, 300, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, 0, 0, 0, 0, 0, 0)
-XTREG(76, 304, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, 0, 0, 0, 0, 0, 0)
-XTREG(77, 308, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, 0, 0, 0, 0, 0, 0)
-XTREG(78, 312, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, 0, 0, 0, 0, 0, 0)
-XTREG(79, 316, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7, 0, 0, 0, 0, 0, 0)
-XTREG(80, 320, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, 0, 0, 0, 0, 0, 0)
-XTREG(81, 324, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, 0, 0, 0, 0, 0, 0)
-XTREG(82, 328, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, 0, 0, 0, 0, 0, 0)
-XTREG(83, 332, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, 0, 0, 0, 0, 0, 0)
-XTREG(84, 336, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, 0, 0, 0, 0, 0, 0)
-XTREG(85, 340, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, 0, 0, 0, 0, 0, 0)
-XTREG(86, 344, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7, 0, 0, 0, 0, 0, 0)
-XTREG(87, 348, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, 0, 0, 0, 0, 0, 0)
-XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, 0, 0, 0, 0, 0, 0)
-XTREG(89, 356, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, 0, 0, 0, 0, 0, 0)
-XTREG(90, 360, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, 0, 0, 0, 0, 0, 0)
-XTREG(91, 364, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, 0, 0, 0, 0, 0, 0)
-XTREG(92, 368, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, 0, 0, 0, 0, 0, 0)
-XTREG(93, 372, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, 0, 0, 0, 0, 0, 0)
-XTREG(94, 376, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, 0, 0, 0, 0, 0, 0)
-XTREG(95, 380, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, 0, 0, 0, 0, 0, 0)
-XTREG(96, 384, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, 0, 0, 0, 0, 0, 0)
-XTREG(97, 388, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, 0, 0, 0, 0, 0, 0)
-XTREG(98, 392, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, 0, 0, 0, 0, 0, 0)
-XTREG(99, 396, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, 0, 0, 0, 0, 0, 0)
-XTREG(100, 400, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, 0, 0, 0, 0, 0, 0)
-XTREG(101, 404, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, 0, 0, 0, 0, 0, 0)
-XTREG(102, 408, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2, 0, 0, 0, 0, 0, 0)
-XTREG(103, 412, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0, 0, 0, 0, 0, 0, 0)
-XTREG(104, 416, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, 0, 0, 0, 0, 0, 0)
-XTREG(105, 420, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, 0, 0, 0, 0, 0, 0)
-XTREG(106, 424, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, 0, 0, 0, 0, 0, 0)
-XTREG(107, 428, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, 0, 0, 0, 0, 0, 0)
-XTREG(108, 432, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, 0, 0, 0, 0, 0, 0)
-XTREG(109, 436, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, 0, 0, 0, 0, 0, 0)
-XTREG(110, 440, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, 0, 0, 0, 0, 0, 0)
-XTREG(111, 444, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, 0, 0, 0, 0, 0, 0)
-XTREG(112, 448, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, 0, 0, 0, 0, 0, 0)
-XTREG(113, 452, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, 0, 0, 0, 0, 0, 0)
-XTREG(114, 456, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, 0, 0, 0, 0, 0, 0)
-XTREG(115, 460, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, 0, 0, 0, 0, 0, 0)
-XTREG(116, 464, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, 0, 0, 0, 0, 0, 0)
-XTREG(117, 468, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, 0, 0, 0, 0, 0, 0)
-XTREG(118, 472, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, 0, 0, 0, 0, 0, 0)
-XTREG(119, 476, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, 0, 0, 0, 0, 0, 0)
-XTREG(120, 480, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, 0, 0, 0, 0, 0, 0)
-XTREG_END
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+
+ Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "qemu/osdep.h"
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "ACCLO", 16, 0 },
+ { "ACCHI", 17, 0 },
+ { "M0", 32, 0 },
+ { "M1", 33, 0 },
+ { "M2", 34, 0 },
+ { "M3", 35, 0 },
+ { "PTEVADDR", 83, 0 },
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "176", 176, 0 },
+ { "208", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "LITBASE", 5, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "RASID", 90, 0 },
+ { "ITLBCFG", 91, 0 },
+ { "DTLBCFG", 92, 0 },
+ { "CPENABLE", 224, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "THREADPTR", 231, 1 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 71
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 231
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 15, 0 },
+ { "EPS3", 15, 0 },
+ { "EPS4", 15, 0 },
+ { "EPS5", 15, 0 },
+ { "EPS6", 15, 0 },
+ { "EPS7", 15, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSRING", 2, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "THREADPTR", 32, 0 },
+ { "LITBADDR", 20, 0 },
+ { "LITBEN", 1, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "ACC", 40, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "ASID3", 8, 0 },
+ { "ASID2", 8, 0 },
+ { "ASID1", 8, 0 },
+ { "INSTPGSZID6", 1, 0 },
+ { "INSTPGSZID5", 1, 0 },
+ { "INSTPGSZID4", 2, 0 },
+ { "DATAPGSZID6", 1, 0 },
+ { "DATAPGSZID5", 1, 0 },
+ { "DATAPGSZID4", 2, 0 },
+ { "PTBASE", 10, 0 },
+ { "CPENABLE", 8, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 78
+
+enum xtensa_state_id {
+ STATE_LCOUNT,
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EPC3,
+ STATE_EPC4,
+ STATE_EPC5,
+ STATE_EPC6,
+ STATE_EPC7,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EXCSAVE3,
+ STATE_EXCSAVE4,
+ STATE_EXCSAVE5,
+ STATE_EXCSAVE6,
+ STATE_EXCSAVE7,
+ STATE_EPS2,
+ STATE_EPS3,
+ STATE_EPS4,
+ STATE_EPS5,
+ STATE_EPS6,
+ STATE_EPS7,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSRING,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_LBEG,
+ STATE_LEND,
+ STATE_SAR,
+ STATE_THREADPTR,
+ STATE_LITBADDR,
+ STATE_LITBEN,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_ACC,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_DBREAKA0,
+ STATE_DBREAKC0,
+ STATE_DBREAKA1,
+ STATE_DBREAKC1,
+ STATE_IBREAKA0,
+ STATE_IBREAKA1,
+ STATE_IBREAKENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_CCOMPARE2,
+ STATE_ASID3,
+ STATE_ASID2,
+ STATE_ASID1,
+ STATE_INSTPGSZID6,
+ STATE_INSTPGSZID5,
+ STATE_INSTPGSZID4,
+ STATE_DATAPGSZID6,
+ STATE_DATAPGSZID5,
+ STATE_DATAPGSZID4,
+ STATE_PTBASE,
+ STATE_CPENABLE,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_EXPSTATE
+};
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_r3,
+ FIELD_rbit2,
+ FIELD_rhi,
+ FIELD_t3,
+ FIELD_tbit2,
+ FIELD_tlo,
+ FIELD_w,
+ FIELD_y,
+ FIELD_x,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_bitindex,
+ FIELD_s3to1,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12,
+ FIELD__mr0,
+ FIELD__mr1,
+ FIELD__mr2,
+ FIELD__mr3
+};
+
+\f
+/* Functional units. */
+
+static xtensa_funcUnit_internal funcUnits[] = {
+
+};
+
+\f
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR,
+ REGFILE_MR
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 },
+ { "MR", "m", REGFILE_MR, 32, 4 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "IMPWIRE", 32, 0, 0, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_IMPWIRE
+};
+
+\f
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+Operand_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_0, offset_0;
+ offset_0 = *valp & 0x3ffff;
+ soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_encode (uint32 *valp)
+{
+ unsigned offset_0, soffsetx4_0;
+ soffsetx4_0 = *valp;
+ offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = offset_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_0, imm12_0;
+ imm12_0 = *valp & 0xfff;
+ uimm12x8_0 = imm12_0 << 3;
+ *valp = uimm12x8_0;
+ return 0;
+}
+
+static int
+Operand_uimm12x8_encode (uint32 *valp)
+{
+ unsigned imm12_0, uimm12x8_0;
+ uimm12x8_0 = *valp;
+ imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
+ *valp = imm12_0;
+ return 0;
+}
+
+static int
+Operand_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_0, mn_0;
+ mn_0 = *valp & 0xf;
+ simm4_0 = ((int) mn_0 << 28) >> 28;
+ *valp = simm4_0;
+ return 0;
+}
+
+static int
+Operand_simm4_encode (uint32 *valp)
+{
+ unsigned mn_0, simm4_0;
+ simm4_0 = *valp;
+ mn_0 = (simm4_0 & 0xf);
+ *valp = mn_0;
+ return 0;
+}
+
+static int
+Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_arr_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ars_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_art_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar0_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar4_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar8_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar12_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ars_entry_encode (uint32 *valp)
+{
+ return (*valp & ~0x1f) != 0;
+}
+
+static int
+Operand_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_0, r_0;
+ r_0 = *valp & 0xf;
+ immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
+ *valp = immrx4_0;
+ return 0;
+}
+
+static int
+Operand_immrx4_encode (uint32 *valp)
+{
+ unsigned r_0, immrx4_0;
+ immrx4_0 = *valp;
+ r_0 = ((immrx4_0 >> 2) & 0xf);
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_0, r_0;
+ r_0 = *valp & 0xf;
+ lsi4x4_0 = r_0 << 2;
+ *valp = lsi4x4_0;
+ return 0;
+}
+
+static int
+Operand_lsi4x4_encode (uint32 *valp)
+{
+ unsigned r_0, lsi4x4_0;
+ lsi4x4_0 = *valp;
+ r_0 = ((lsi4x4_0 >> 2) & 0xf);
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_0, imm7_0;
+ imm7_0 = *valp & 0x7f;
+ simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
+ *valp = simm7_0;
+ return 0;
+}
+
+static int
+Operand_simm7_encode (uint32 *valp)
+{
+ unsigned imm7_0, simm7_0;
+ simm7_0 = *valp;
+ imm7_0 = (simm7_0 & 0x7f);
+ *valp = imm7_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_0, imm6_0;
+ imm6_0 = *valp & 0x3f;
+ uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
+ *valp = uimm6_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_encode (uint32 *valp)
+{
+ unsigned imm6_0, uimm6_0;
+ uimm6_0 = *valp;
+ imm6_0 = (uimm6_0 - 0x4) & 0x3f;
+ *valp = imm6_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_0, t_0;
+ t_0 = *valp & 0xf;
+ ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
+ *valp = ai4const_0;
+ return 0;
+}
+
+static int
+Operand_ai4const_encode (uint32 *valp)
+{
+ unsigned t_0, ai4const_0;
+ ai4const_0 = *valp;
+ switch (ai4const_0)
+ {
+ case 0xffffffff: t_0 = 0; break;
+ case 0x1: t_0 = 0x1; break;
+ case 0x2: t_0 = 0x2; break;
+ case 0x3: t_0 = 0x3; break;
+ case 0x4: t_0 = 0x4; break;
+ case 0x5: t_0 = 0x5; break;
+ case 0x6: t_0 = 0x6; break;
+ case 0x7: t_0 = 0x7; break;
+ case 0x8: t_0 = 0x8; break;
+ case 0x9: t_0 = 0x9; break;
+ case 0xa: t_0 = 0xa; break;
+ case 0xb: t_0 = 0xb; break;
+ case 0xc: t_0 = 0xc; break;
+ case 0xd: t_0 = 0xd; break;
+ case 0xe: t_0 = 0xe; break;
+ default: t_0 = 0xf; break;
+ }
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_0, r_0;
+ r_0 = *valp & 0xf;
+ b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
+ *valp = b4const_0;
+ return 0;
+}
+
+static int
+Operand_b4const_encode (uint32 *valp)
+{
+ unsigned r_0, b4const_0;
+ b4const_0 = *valp;
+ switch (b4const_0)
+ {
+ case 0xffffffff: r_0 = 0; break;
+ case 0x1: r_0 = 0x1; break;
+ case 0x2: r_0 = 0x2; break;
+ case 0x3: r_0 = 0x3; break;
+ case 0x4: r_0 = 0x4; break;
+ case 0x5: r_0 = 0x5; break;
+ case 0x6: r_0 = 0x6; break;
+ case 0x7: r_0 = 0x7; break;
+ case 0x8: r_0 = 0x8; break;
+ case 0xa: r_0 = 0x9; break;
+ case 0xc: r_0 = 0xa; break;
+ case 0x10: r_0 = 0xb; break;
+ case 0x20: r_0 = 0xc; break;
+ case 0x40: r_0 = 0xd; break;
+ case 0x80: r_0 = 0xe; break;
+ default: r_0 = 0xf; break;
+ }
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_0, r_0;
+ r_0 = *valp & 0xf;
+ b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
+ *valp = b4constu_0;
+ return 0;
+}
+
+static int
+Operand_b4constu_encode (uint32 *valp)
+{
+ unsigned r_0, b4constu_0;
+ b4constu_0 = *valp;
+ switch (b4constu_0)
+ {
+ case 0x8000: r_0 = 0; break;
+ case 0x10000: r_0 = 0x1; break;
+ case 0x2: r_0 = 0x2; break;
+ case 0x3: r_0 = 0x3; break;
+ case 0x4: r_0 = 0x4; break;
+ case 0x5: r_0 = 0x5; break;
+ case 0x6: r_0 = 0x6; break;
+ case 0x7: r_0 = 0x7; break;
+ case 0x8: r_0 = 0x8; break;
+ case 0xa: r_0 = 0x9; break;
+ case 0xc: r_0 = 0xa; break;
+ case 0x10: r_0 = 0xb; break;
+ case 0x20: r_0 = 0xc; break;
+ case 0x40: r_0 = 0xd; break;
+ case 0x80: r_0 = 0xe; break;
+ default: r_0 = 0xf; break;
+ }
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8_0 = imm8_0;
+ *valp = uimm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8_0;
+ uimm8_0 = *valp;
+ imm8_0 = (uimm8_0 & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8x2_0 = imm8_0 << 1;
+ *valp = uimm8x2_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x2_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8x2_0;
+ uimm8x2_0 = *valp;
+ imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8x4_0 = imm8_0 << 2;
+ *valp = uimm8x4_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x4_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8x4_0;
+ uimm8x4_0 = *valp;
+ imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_0, op2_0;
+ op2_0 = *valp & 0xf;
+ uimm4x16_0 = op2_0 << 4;
+ *valp = uimm4x16_0;
+ return 0;
+}
+
+static int
+Operand_uimm4x16_encode (uint32 *valp)
+{
+ unsigned op2_0, uimm4x16_0;
+ uimm4x16_0 = *valp;
+ op2_0 = ((uimm4x16_0 >> 4) & 0xf);
+ *valp = op2_0;
+ return 0;
+}
+
+static int
+Operand_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ simm8_0 = ((int) imm8_0 << 24) >> 24;
+ *valp = simm8_0;
+ return 0;
+}
+
+static int
+Operand_simm8_encode (uint32 *valp)
+{
+ unsigned imm8_0, simm8_0;
+ simm8_0 = *valp;
+ imm8_0 = (simm8_0 & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
+ *valp = simm8x256_0;
+ return 0;
+}
+
+static int
+Operand_simm8x256_encode (uint32 *valp)
+{
+ unsigned imm8_0, simm8x256_0;
+ simm8x256_0 = *valp;
+ imm8_0 = ((simm8x256_0 >> 8) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_0, imm12b_0;
+ imm12b_0 = *valp & 0xfff;
+ simm12b_0 = ((int) imm12b_0 << 20) >> 20;
+ *valp = simm12b_0;
+ return 0;
+}
+
+static int
+Operand_simm12b_encode (uint32 *valp)
+{
+ unsigned imm12b_0, simm12b_0;
+ simm12b_0 = *valp;
+ imm12b_0 = (simm12b_0 & 0xfff);
+ *valp = imm12b_0;
+ return 0;
+}
+
+static int
+Operand_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_0, sal_0;
+ sal_0 = *valp & 0x1f;
+ msalp32_0 = 0x20 - sal_0;
+ *valp = msalp32_0;
+ return 0;
+}
+
+static int
+Operand_msalp32_encode (uint32 *valp)
+{
+ unsigned sal_0, msalp32_0;
+ msalp32_0 = *valp;
+ sal_0 = (0x20 - msalp32_0) & 0x1f;
+ *valp = sal_0;
+ return 0;
+}
+
+static int
+Operand_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_0, op2_0;
+ op2_0 = *valp & 0xf;
+ op2p1_0 = op2_0 + 0x1;
+ *valp = op2p1_0;
+ return 0;
+}
+
+static int
+Operand_op2p1_encode (uint32 *valp)
+{
+ unsigned op2_0, op2p1_0;
+ op2p1_0 = *valp;
+ op2_0 = (op2p1_0 - 0x1) & 0xf;
+ *valp = op2_0;
+ return 0;
+}
+
+static int
+Operand_label8_decode (uint32 *valp)
+{
+ unsigned label8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
+ *valp = label8_0;
+ return 0;
+}
+
+static int
+Operand_label8_encode (uint32 *valp)
+{
+ unsigned imm8_0, label8_0;
+ label8_0 = *valp;
+ imm8_0 = (label8_0 - 0x4) & 0xff;
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
+ *valp = ulabel8_0;
+ return 0;
+}
+
+static int
+Operand_ulabel8_encode (uint32 *valp)
+{
+ unsigned imm8_0, ulabel8_0;
+ ulabel8_0 = *valp;
+ imm8_0 = (ulabel8_0 - 0x4) & 0xff;
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_decode (uint32 *valp)
+{
+ unsigned label12_0, imm12_0;
+ imm12_0 = *valp & 0xfff;
+ label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
+ *valp = label12_0;
+ return 0;
+}
+
+static int
+Operand_label12_encode (uint32 *valp)
+{
+ unsigned imm12_0, label12_0;
+ label12_0 = *valp;
+ imm12_0 = (label12_0 - 0x4) & 0xfff;
+ *valp = imm12_0;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_0, offset_0;
+ offset_0 = *valp & 0x3ffff;
+ soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
+ *valp = soffset_0;
+ return 0;
+}
+
+static int
+Operand_soffset_encode (uint32 *valp)
+{
+ unsigned offset_0, soffset_0;
+ soffset_0 = *valp;
+ offset_0 = (soffset_0 - 0x4) & 0x3ffff;
+ *valp = offset_0;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_0, imm16_0;
+ imm16_0 = *valp & 0xffff;
+ uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
+ *valp = uimm16x4_0;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_encode (uint32 *valp)
+{
+ unsigned imm16_0, uimm16x4_0;
+ uimm16x4_0 = *valp;
+ imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
+ *valp = imm16_0;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mx_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_my_decode (uint32 *valp)
+{
+ *valp += 2;
+ return 0;
+}
+
+static int
+Operand_my_encode (uint32 *valp)
+{
+ int error;
+ error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+ *valp = *valp & 1;
+ return error;
+}
+
+static int
+Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mw_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr0_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr1_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr2_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_mr3_encode (uint32 *valp)
+{
+ return (*valp & ~0x3) != 0;
+}
+
+static int
+Operand_immt_decode (uint32 *valp)
+{
+ unsigned immt_0, t_0;
+ t_0 = *valp & 0xf;
+ immt_0 = t_0;
+ *valp = immt_0;
+ return 0;
+}
+
+static int
+Operand_immt_encode (uint32 *valp)
+{
+ unsigned t_0, immt_0;
+ immt_0 = *valp;
+ t_0 = immt_0 & 0xf;
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_imms_decode (uint32 *valp)
+{
+ unsigned imms_0, s_0;
+ s_0 = *valp & 0xf;
+ imms_0 = s_0;
+ *valp = imms_0;
+ return 0;
+}
+
+static int
+Operand_imms_encode (uint32 *valp)
+{
+ unsigned s_0, imms_0;
+ imms_0 = *valp;
+ s_0 = imms_0 & 0xf;
+ *valp = s_0;
+ return 0;
+}
+
+static int
+Operand_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_0, t_0;
+ t_0 = *valp & 0xf;
+ tp7_0 = t_0 + 0x7;
+ *valp = tp7_0;
+ return 0;
+}
+
+static int
+Operand_tp7_encode (uint32 *valp)
+{
+ unsigned t_0, tp7_0;
+ tp7_0 = *valp;
+ t_0 = (tp7_0 - 0x7) & 0xf;
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
+ xt_wbr15_imm_0 = *valp & 0x7fff;
+ xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
+ *valp = xt_wbr15_label_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
+ xt_wbr15_label_0 = *valp;
+ xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_imm_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
+ xt_wbr18_imm_0 = *valp & 0x3ffff;
+ xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
+ *valp = xt_wbr18_label_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
+ xt_wbr18_label_0 = *valp;
+ xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
+ *valp = xt_wbr18_imm_0;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_soffsetx4_encode, Operand_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ Operand_uimm12x8_encode, Operand_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ Operand_simm4_encode, Operand_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_arr_encode, Operand_arr_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_ars_encode, Operand_ars_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ars_encode, Operand_ars_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_art_encode, Operand_art_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar0_encode, Operand_ar0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar4_encode, Operand_ar4_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar8_encode, Operand_ar8_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar12_encode, Operand_ar12_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_ars_entry_encode, Operand_ars_entry_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ Operand_immrx4_encode, Operand_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ Operand_lsi4x4_encode, Operand_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ Operand_simm7_encode, Operand_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_uimm6_encode, Operand_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ Operand_ai4const_encode, Operand_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ Operand_b4const_encode, Operand_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ Operand_b4constu_encode, Operand_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ Operand_uimm8_encode, Operand_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ Operand_uimm8x2_encode, Operand_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ Operand_uimm8x4_encode, Operand_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ Operand_uimm4x16_encode, Operand_uimm4x16_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ Operand_simm8_encode, Operand_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ Operand_simm8x256_encode, Operand_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ Operand_simm12b_encode, Operand_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ Operand_msalp32_encode, Operand_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ Operand_op2p1_encode, Operand_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_label8_encode, Operand_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_ulabel8_encode, Operand_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_label12_encode, Operand_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_soffset_encode, Operand_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_uimm16x4_encode, Operand_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "mx", FIELD_x, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ Operand_mx_encode, Operand_mx_decode,
+ 0, 0 },
+ { "my", FIELD_y, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ Operand_my_encode, Operand_my_decode,
+ 0, 0 },
+ { "mw", FIELD_w, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_mw_encode, Operand_mw_decode,
+ 0, 0 },
+ { "mr0", FIELD__mr0, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr0_encode, Operand_mr0_decode,
+ 0, 0 },
+ { "mr1", FIELD__mr1, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr1_encode, Operand_mr1_decode,
+ 0, 0 },
+ { "mr2", FIELD__mr2, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr2_encode, Operand_mr2_decode,
+ 0, 0 },
+ { "mr3", FIELD__mr3, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_mr3_encode, Operand_mr3_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ Operand_immt_encode, Operand_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ Operand_imms_encode, Operand_imms_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ Operand_tp7_encode, Operand_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
+ { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
+ { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
+ { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
+ { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
+ { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
+ { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_ulabel8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_mx,
+ OPERAND_my,
+ OPERAND_mw,
+ OPERAND_mr0,
+ OPERAND_mr1,
+ OPERAND_mr2,
+ OPERAND_mr3,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_bbi,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_s,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sae,
+ OPERAND_sal,
+ OPERAND_sargt,
+ OPERAND_sas4,
+ OPERAND_sas,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_r3,
+ OPERAND_rbit2,
+ OPERAND_rhi,
+ OPERAND_t3,
+ OPERAND_tbit2,
+ OPERAND_tlo,
+ OPERAND_w,
+ OPERAND_y,
+ OPERAND_x,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_bitindex,
+ OPERAND_s3to1
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'o' },
+ { { STATE_LITBEN }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'm' },
+ { { STATE_LITBEN }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'm' },
+ { { STATE_EXCVADDR }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'i' },
+ { { STATE_ASID2 }, 'i' },
+ { { STATE_ASID1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'o' },
+ { { STATE_ASID2 }, 'o' },
+ { { STATE_ASID1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'm' },
+ { { STATE_ASID2 }, 'm' },
+ { { STATE_ASID1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID6 }, 'i' },
+ { { STATE_INSTPGSZID5 }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID6 }, 'o' },
+ { { STATE_INSTPGSZID5 }, 'o' },
+ { { STATE_INSTPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID6 }, 'm' },
+ { { STATE_INSTPGSZID5 }, 'm' },
+ { { STATE_INSTPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID6 }, 'i' },
+ { { STATE_DATAPGSZID5 }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID6 }, 'o' },
+ { { STATE_DATAPGSZID5 }, 'o' },
+ { { STATE_DATAPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID6 }, 'm' },
+ { { STATE_DATAPGSZID5 }, 'm' },
+ { { STATE_DATAPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_threadptr_args,
+ 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_threadptr_args,
+ 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_176_args,
+ 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_176_args,
+ 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_208_args,
+ 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_aa_args,
+ 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_ad_args,
+ 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_da_args,
+ 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_dd_args,
+ 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_aa_args,
+ 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_ad_args,
+ 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_da_args,
+ 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_dd_args,
+ 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_da_args,
+ 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_dd_args,
+ 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_l_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m3_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acclo_args,
+ 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acclo_args,
+ 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acclo_args,
+ 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acchi_args,
+ 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acchi_args,
+ 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acchi_args,
+ 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_lock_args,
+ 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_lock_args,
+ 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
+ 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_rasid_args,
+ 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_rasid_args,
+ 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_rasid_args,
+ 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
+ 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
+ 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
+ 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
+ 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
+ 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
+ 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_ldpte */,
+ 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwitlba */,
+ 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwdtlba */,
+ 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_cpenable_args,
+ 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_cpenable_args,
+ 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_cpenable_args,
+ 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rer */,
+ 2, Iclass_xt_iclass_rer_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_wer */,
+ 2, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
+ { 1, Iclass_rur_expstate_args,
+ 2, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 2, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_rur_threadptr,
+ ICLASS_wur_threadptr,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_loop,
+ ICLASS_xt_iclass_loopz,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_lend,
+ ICLASS_xt_iclass_wsr_lend,
+ ICLASS_xt_iclass_xsr_lend,
+ ICLASS_xt_iclass_rsr_lcount,
+ ICLASS_xt_iclass_wsr_lcount,
+ ICLASS_xt_iclass_xsr_lcount,
+ ICLASS_xt_iclass_rsr_lbeg,
+ ICLASS_xt_iclass_wsr_lbeg,
+ ICLASS_xt_iclass_xsr_lbeg,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_176,
+ ICLASS_xt_iclass_wsr_176,
+ ICLASS_xt_iclass_rsr_208,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_epc3,
+ ICLASS_xt_iclass_wsr_epc3,
+ ICLASS_xt_iclass_xsr_epc3,
+ ICLASS_xt_iclass_rsr_excsave3,
+ ICLASS_xt_iclass_wsr_excsave3,
+ ICLASS_xt_iclass_xsr_excsave3,
+ ICLASS_xt_iclass_rsr_epc4,
+ ICLASS_xt_iclass_wsr_epc4,
+ ICLASS_xt_iclass_xsr_epc4,
+ ICLASS_xt_iclass_rsr_excsave4,
+ ICLASS_xt_iclass_wsr_excsave4,
+ ICLASS_xt_iclass_xsr_excsave4,
+ ICLASS_xt_iclass_rsr_epc5,
+ ICLASS_xt_iclass_wsr_epc5,
+ ICLASS_xt_iclass_xsr_epc5,
+ ICLASS_xt_iclass_rsr_excsave5,
+ ICLASS_xt_iclass_wsr_excsave5,
+ ICLASS_xt_iclass_xsr_excsave5,
+ ICLASS_xt_iclass_rsr_epc6,
+ ICLASS_xt_iclass_wsr_epc6,
+ ICLASS_xt_iclass_xsr_epc6,
+ ICLASS_xt_iclass_rsr_excsave6,
+ ICLASS_xt_iclass_wsr_excsave6,
+ ICLASS_xt_iclass_xsr_excsave6,
+ ICLASS_xt_iclass_rsr_epc7,
+ ICLASS_xt_iclass_wsr_epc7,
+ ICLASS_xt_iclass_xsr_epc7,
+ ICLASS_xt_iclass_rsr_excsave7,
+ ICLASS_xt_iclass_wsr_excsave7,
+ ICLASS_xt_iclass_xsr_excsave7,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_eps3,
+ ICLASS_xt_iclass_wsr_eps3,
+ ICLASS_xt_iclass_xsr_eps3,
+ ICLASS_xt_iclass_rsr_eps4,
+ ICLASS_xt_iclass_wsr_eps4,
+ ICLASS_xt_iclass_xsr_eps4,
+ ICLASS_xt_iclass_rsr_eps5,
+ ICLASS_xt_iclass_wsr_eps5,
+ ICLASS_xt_iclass_xsr_eps5,
+ ICLASS_xt_iclass_rsr_eps6,
+ ICLASS_xt_iclass_wsr_eps6,
+ ICLASS_xt_iclass_xsr_eps6,
+ ICLASS_xt_iclass_rsr_eps7,
+ ICLASS_xt_iclass_wsr_eps7,
+ ICLASS_xt_iclass_xsr_eps7,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_iclass_mac16_aa,
+ ICLASS_xt_iclass_mac16_ad,
+ ICLASS_xt_iclass_mac16_da,
+ ICLASS_xt_iclass_mac16_dd,
+ ICLASS_xt_iclass_mac16a_aa,
+ ICLASS_xt_iclass_mac16a_ad,
+ ICLASS_xt_iclass_mac16a_da,
+ ICLASS_xt_iclass_mac16a_dd,
+ ICLASS_xt_iclass_mac16al_da,
+ ICLASS_xt_iclass_mac16al_dd,
+ ICLASS_xt_iclass_mac16_l,
+ ICLASS_xt_iclass_rsr_m0,
+ ICLASS_xt_iclass_wsr_m0,
+ ICLASS_xt_iclass_xsr_m0,
+ ICLASS_xt_iclass_rsr_m1,
+ ICLASS_xt_iclass_wsr_m1,
+ ICLASS_xt_iclass_xsr_m1,
+ ICLASS_xt_iclass_rsr_m2,
+ ICLASS_xt_iclass_wsr_m2,
+ ICLASS_xt_iclass_xsr_m2,
+ ICLASS_xt_iclass_rsr_m3,
+ ICLASS_xt_iclass_wsr_m3,
+ ICLASS_xt_iclass_xsr_m3,
+ ICLASS_xt_iclass_rsr_acclo,
+ ICLASS_xt_iclass_wsr_acclo,
+ ICLASS_xt_iclass_xsr_acclo,
+ ICLASS_xt_iclass_rsr_acchi,
+ ICLASS_xt_iclass_wsr_acchi,
+ ICLASS_xt_iclass_xsr_acchi,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_dbreaka0,
+ ICLASS_xt_iclass_wsr_dbreaka0,
+ ICLASS_xt_iclass_xsr_dbreaka0,
+ ICLASS_xt_iclass_rsr_dbreakc0,
+ ICLASS_xt_iclass_wsr_dbreakc0,
+ ICLASS_xt_iclass_xsr_dbreakc0,
+ ICLASS_xt_iclass_rsr_dbreaka1,
+ ICLASS_xt_iclass_wsr_dbreaka1,
+ ICLASS_xt_iclass_xsr_dbreaka1,
+ ICLASS_xt_iclass_rsr_dbreakc1,
+ ICLASS_xt_iclass_wsr_dbreakc1,
+ ICLASS_xt_iclass_xsr_dbreakc1,
+ ICLASS_xt_iclass_rsr_ibreaka0,
+ ICLASS_xt_iclass_wsr_ibreaka0,
+ ICLASS_xt_iclass_xsr_ibreaka0,
+ ICLASS_xt_iclass_rsr_ibreaka1,
+ ICLASS_xt_iclass_wsr_ibreaka1,
+ ICLASS_xt_iclass_xsr_ibreaka1,
+ ICLASS_xt_iclass_rsr_ibreakenable,
+ ICLASS_xt_iclass_wsr_ibreakenable,
+ ICLASS_xt_iclass_xsr_ibreakenable,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_wsr_mmid,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_rsr_ccompare2,
+ ICLASS_xt_iclass_wsr_ccompare2,
+ ICLASS_xt_iclass_xsr_ccompare2,
+ ICLASS_xt_iclass_icache,
+ ICLASS_xt_iclass_icache_lock,
+ ICLASS_xt_iclass_icache_inv,
+ ICLASS_xt_iclass_licx,
+ ICLASS_xt_iclass_sicx,
+ ICLASS_xt_iclass_dcache,
+ ICLASS_xt_iclass_dcache_ind,
+ ICLASS_xt_iclass_dcache_inv,
+ ICLASS_xt_iclass_dpf,
+ ICLASS_xt_iclass_dcache_lock,
+ ICLASS_xt_iclass_sdct,
+ ICLASS_xt_iclass_ldct,
+ ICLASS_xt_iclass_wsr_ptevaddr,
+ ICLASS_xt_iclass_rsr_ptevaddr,
+ ICLASS_xt_iclass_xsr_ptevaddr,
+ ICLASS_xt_iclass_rsr_rasid,
+ ICLASS_xt_iclass_wsr_rasid,
+ ICLASS_xt_iclass_xsr_rasid,
+ ICLASS_xt_iclass_rsr_itlbcfg,
+ ICLASS_xt_iclass_wsr_itlbcfg,
+ ICLASS_xt_iclass_xsr_itlbcfg,
+ ICLASS_xt_iclass_rsr_dtlbcfg,
+ ICLASS_xt_iclass_wsr_dtlbcfg,
+ ICLASS_xt_iclass_xsr_dtlbcfg,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_ldpte,
+ ICLASS_xt_iclass_hwwitlba,
+ ICLASS_xt_iclass_hwwdtlba,
+ ICLASS_xt_iclass_rsr_cpenable,
+ ICLASS_xt_iclass_wsr_cpenable,
+ ICLASS_xt_iclass_xsr_cpenable,
+ ICLASS_xt_iclass_clamp,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_div,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_expstate,
+ ICLASS_wur_expstate,
+ ICLASS_iclass_READ_IMPWIRE,
+ ICLASS_iclass_SETB_EXPSTATE,
+ ICLASS_iclass_CLRB_EXPSTATE,
+ ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70c2;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e2;
+}
+
+static void
+Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70d2;
+}
+
+static void
+Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270d2;
+}
+
+static void
+Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370d2;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f2;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf10000;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf12000;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11000;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13000;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7042;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7052;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x47082;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x57082;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7062;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7072;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7002;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7012;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7022;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7032;
+}
+
+static void
+Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7082;
+}
+
+static void
+Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x27082;
+}
+
+static void
+Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x37082;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf19000;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf18000;
+}
+
+static void
+Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135300;
+}
+
+static void
+Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35300;
+}
+
+static void
+Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615300;
+}
+
+static void
+Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35a00;
+}
+
+static void
+Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135a00;
+}
+
+static void
+Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615a00;
+}
+
+static void
+Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35b00;
+}
+
+static void
+Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135b00;
+}
+
+static void
+Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615b00;
+}
+
+static void
+Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35c00;
+}
+
+static void
+Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135c00;
+}
+
+static void
+Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615c00;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1f000;
+}
+
+static void
+Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x501000;
+}
+
+static void
+Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x509000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe2000;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+ Opcode_rur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+ Opcode_wur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
+ Opcode_rsr_176_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
+ Opcode_wsr_176_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
+ Opcode_rsr_208_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+ Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+ Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+ Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+ Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+ Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+ Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+ Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+ Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+ Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+ Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+ Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+ Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+ Opcode_mul_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+ Opcode_mul_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+ Opcode_mul_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+ Opcode_mul_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+ Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+ Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+ Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+ Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+ Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+ Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+ Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+ Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+ Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+ Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+ Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+ Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+ Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+ Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+ Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+ Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+ Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+ Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+ Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+ Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+ Opcode_mula_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+ Opcode_mula_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+ Opcode_mula_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+ Opcode_mula_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+ Opcode_muls_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+ Opcode_muls_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+ Opcode_muls_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+ Opcode_muls_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+ Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+ Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+ Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+ Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+ Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+ Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+ Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+ Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+ Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+ Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+ Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+ Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+ Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+ Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+ Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+ Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+ Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+ Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+ Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+ Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+ Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+ Opcode_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+ Opcode_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+ Opcode_rsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+ Opcode_wsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+ Opcode_xsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+ Opcode_rsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+ Opcode_wsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+ Opcode_xsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+ Opcode_rsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+ Opcode_wsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+ Opcode_xsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+ Opcode_rsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+ Opcode_wsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+ Opcode_xsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+ Opcode_rsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+ Opcode_wsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+ Opcode_xsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+ Opcode_rsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+ Opcode_wsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+ Opcode_xsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
+ Opcode_ipfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
+ Opcode_ihu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
+ Opcode_iiu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
+ Opcode_dpfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
+ Opcode_dhu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
+ Opcode_diu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
+ Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
+ Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
+ Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
+ Opcode_rsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
+ Opcode_wsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
+ Opcode_xsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
+ Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
+ Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
+ Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
+ Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
+ Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
+ Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
+ Opcode_ldpte_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
+ Opcode_hwwitlba_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
+ Opcode_hwwdtlba_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+ Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+ Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+ Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+\f
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "rur.threadptr", ICLASS_rur_threadptr,
+ 0,
+ Opcode_rur_threadptr_encode_fns, 0, 0 },
+ { "wur.threadptr", ICLASS_wur_threadptr,
+ 0,
+ Opcode_wur_threadptr_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", ICLASS_xt_iclass_loop,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.176", ICLASS_xt_iclass_rsr_176,
+ 0,
+ Opcode_rsr_176_encode_fns, 0, 0 },
+ { "wsr.176", ICLASS_xt_iclass_wsr_176,
+ 0,
+ Opcode_wsr_176_encode_fns, 0, 0 },
+ { "rsr.208", ICLASS_xt_iclass_rsr_208,
+ 0,
+ Opcode_rsr_208_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_ll_encode_fns, 0, 0 },
+ { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hl_encode_fns, 0, 0 },
+ { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_lh_encode_fns, 0, 0 },
+ { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hh_encode_fns, 0, 0 },
+ { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_ll_encode_fns, 0, 0 },
+ { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hl_encode_fns, 0, 0 },
+ { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_lh_encode_fns, 0, 0 },
+ { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hh_encode_fns, 0, 0 },
+ { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_ll_encode_fns, 0, 0 },
+ { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hl_encode_fns, 0, 0 },
+ { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_lh_encode_fns, 0, 0 },
+ { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hh_encode_fns, 0, 0 },
+ { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_ll_encode_fns, 0, 0 },
+ { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hl_encode_fns, 0, 0 },
+ { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_lh_encode_fns, 0, 0 },
+ { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hh_encode_fns, 0, 0 },
+ { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_ll_encode_fns, 0, 0 },
+ { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hl_encode_fns, 0, 0 },
+ { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_lh_encode_fns, 0, 0 },
+ { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hh_encode_fns, 0, 0 },
+ { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_ll_encode_fns, 0, 0 },
+ { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hl_encode_fns, 0, 0 },
+ { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_lh_encode_fns, 0, 0 },
+ { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hh_encode_fns, 0, 0 },
+ { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_ll_encode_fns, 0, 0 },
+ { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hl_encode_fns, 0, 0 },
+ { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_lh_encode_fns, 0, 0 },
+ { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hh_encode_fns, 0, 0 },
+ { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_ll_encode_fns, 0, 0 },
+ { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hl_encode_fns, 0, 0 },
+ { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_lh_encode_fns, 0, 0 },
+ { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hh_encode_fns, 0, 0 },
+ { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_ll_encode_fns, 0, 0 },
+ { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hl_encode_fns, 0, 0 },
+ { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_lh_encode_fns, 0, 0 },
+ { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hh_encode_fns, 0, 0 },
+ { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_ll_encode_fns, 0, 0 },
+ { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hl_encode_fns, 0, 0 },
+ { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_lh_encode_fns, 0, 0 },
+ { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hh_encode_fns, 0, 0 },
+ { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_ll_encode_fns, 0, 0 },
+ { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hl_encode_fns, 0, 0 },
+ { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_lh_encode_fns, 0, 0 },
+ { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hh_encode_fns, 0, 0 },
+ { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_ll_encode_fns, 0, 0 },
+ { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hl_encode_fns, 0, 0 },
+ { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_lh_encode_fns, 0, 0 },
+ { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hh_encode_fns, 0, 0 },
+ { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_ll_encode_fns, 0, 0 },
+ { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hl_encode_fns, 0, 0 },
+ { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_lh_encode_fns, 0, 0 },
+ { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hh_encode_fns, 0, 0 },
+ { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+ { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+ { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+ { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+ { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+ { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+ { "lddec", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_lddec_encode_fns, 0, 0 },
+ { "ldinc", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_ldinc_encode_fns, 0, 0 },
+ { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
+ 0,
+ Opcode_rsr_m0_encode_fns, 0, 0 },
+ { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
+ 0,
+ Opcode_wsr_m0_encode_fns, 0, 0 },
+ { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
+ 0,
+ Opcode_xsr_m0_encode_fns, 0, 0 },
+ { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
+ 0,
+ Opcode_rsr_m1_encode_fns, 0, 0 },
+ { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
+ 0,
+ Opcode_wsr_m1_encode_fns, 0, 0 },
+ { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
+ 0,
+ Opcode_xsr_m1_encode_fns, 0, 0 },
+ { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
+ 0,
+ Opcode_rsr_m2_encode_fns, 0, 0 },
+ { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
+ 0,
+ Opcode_wsr_m2_encode_fns, 0, 0 },
+ { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
+ 0,
+ Opcode_xsr_m2_encode_fns, 0, 0 },
+ { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
+ 0,
+ Opcode_rsr_m3_encode_fns, 0, 0 },
+ { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
+ 0,
+ Opcode_wsr_m3_encode_fns, 0, 0 },
+ { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
+ 0,
+ Opcode_xsr_m3_encode_fns, 0, 0 },
+ { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
+ 0,
+ Opcode_rsr_acclo_encode_fns, 0, 0 },
+ { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
+ 0,
+ Opcode_wsr_acclo_encode_fns, 0, 0 },
+ { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
+ 0,
+ Opcode_xsr_acclo_encode_fns, 0, 0 },
+ { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
+ 0,
+ Opcode_rsr_acchi_encode_fns, 0, 0 },
+ { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
+ 0,
+ Opcode_wsr_acchi_encode_fns, 0, 0 },
+ { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
+ 0,
+ Opcode_xsr_acchi_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "ipf", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "ipfl", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ipfl_encode_fns, 0, 0 },
+ { "ihu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ihu_encode_fns, 0, 0 },
+ { "iiu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_iiu_encode_fns, 0, 0 },
+ { "iii", ICLASS_xt_iclass_icache_inv,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwb", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "dpfl", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dpfl_encode_fns, 0, 0 },
+ { "dhu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dhu_encode_fns, 0, 0 },
+ { "diu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_diu_encode_fns, 0, 0 },
+ { "sdct", ICLASS_xt_iclass_sdct,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", ICLASS_xt_iclass_ldct,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
+ 0,
+ Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
+ 0,
+ Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
+ { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
+ 0,
+ Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
+ 0,
+ Opcode_rsr_rasid_encode_fns, 0, 0 },
+ { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
+ 0,
+ Opcode_wsr_rasid_encode_fns, 0, 0 },
+ { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
+ 0,
+ Opcode_xsr_rasid_encode_fns, 0, 0 },
+ { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
+ 0,
+ Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
+ { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
+ 0,
+ Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
+ { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
+ 0,
+ Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
+ { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
+ 0,
+ Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
+ { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
+ 0,
+ Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
+ { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
+ 0,
+ Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "ldpte", ICLASS_xt_iclass_ldpte,
+ 0,
+ Opcode_ldpte_encode_fns, 0, 0 },
+ { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_hwwitlba_encode_fns, 0, 0 },
+ { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
+ 0,
+ Opcode_hwwdtlba_encode_fns, 0, 0 },
+ { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
+ 0,
+ Opcode_rsr_cpenable_encode_fns, 0, 0 },
+ { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
+ 0,
+ Opcode_wsr_cpenable_encode_fns, 0, 0 },
+ { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
+ 0,
+ Opcode_xsr_cpenable_encode_fns, 0, 0 },
+ { "clamps", ICLASS_xt_iclass_clamp,
+ 0,
+ Opcode_clamps_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "quou", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.expstate", ICLASS_rur_expstate,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", ICLASS_wur_expstate,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_SIMCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_RUR_THREADPTR,
+ OPCODE_WUR_THREADPTR,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_LOOP,
+ OPCODE_LOOPNEZ,
+ OPCODE_LOOPGTZ,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_LEND,
+ OPCODE_WSR_LEND,
+ OPCODE_XSR_LEND,
+ OPCODE_RSR_LCOUNT,
+ OPCODE_WSR_LCOUNT,
+ OPCODE_XSR_LCOUNT,
+ OPCODE_RSR_LBEG,
+ OPCODE_WSR_LBEG,
+ OPCODE_XSR_LBEG,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_176,
+ OPCODE_WSR_176,
+ OPCODE_RSR_208,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPC3,
+ OPCODE_WSR_EPC3,
+ OPCODE_XSR_EPC3,
+ OPCODE_RSR_EXCSAVE3,
+ OPCODE_WSR_EXCSAVE3,
+ OPCODE_XSR_EXCSAVE3,
+ OPCODE_RSR_EPC4,
+ OPCODE_WSR_EPC4,
+ OPCODE_XSR_EPC4,
+ OPCODE_RSR_EXCSAVE4,
+ OPCODE_WSR_EXCSAVE4,
+ OPCODE_XSR_EXCSAVE4,
+ OPCODE_RSR_EPC5,
+ OPCODE_WSR_EPC5,
+ OPCODE_XSR_EPC5,
+ OPCODE_RSR_EXCSAVE5,
+ OPCODE_WSR_EXCSAVE5,
+ OPCODE_XSR_EXCSAVE5,
+ OPCODE_RSR_EPC6,
+ OPCODE_WSR_EPC6,
+ OPCODE_XSR_EPC6,
+ OPCODE_RSR_EXCSAVE6,
+ OPCODE_WSR_EXCSAVE6,
+ OPCODE_XSR_EXCSAVE6,
+ OPCODE_RSR_EPC7,
+ OPCODE_WSR_EPC7,
+ OPCODE_XSR_EPC7,
+ OPCODE_RSR_EXCSAVE7,
+ OPCODE_WSR_EXCSAVE7,
+ OPCODE_XSR_EXCSAVE7,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EPS3,
+ OPCODE_WSR_EPS3,
+ OPCODE_XSR_EPS3,
+ OPCODE_RSR_EPS4,
+ OPCODE_WSR_EPS4,
+ OPCODE_XSR_EPS4,
+ OPCODE_RSR_EPS5,
+ OPCODE_WSR_EPS5,
+ OPCODE_XSR_EPS5,
+ OPCODE_RSR_EPS6,
+ OPCODE_WSR_EPS6,
+ OPCODE_XSR_EPS6,
+ OPCODE_RSR_EPS7,
+ OPCODE_WSR_EPS7,
+ OPCODE_XSR_EPS7,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_MUL_AA_LL,
+ OPCODE_MUL_AA_HL,
+ OPCODE_MUL_AA_LH,
+ OPCODE_MUL_AA_HH,
+ OPCODE_UMUL_AA_LL,
+ OPCODE_UMUL_AA_HL,
+ OPCODE_UMUL_AA_LH,
+ OPCODE_UMUL_AA_HH,
+ OPCODE_MUL_AD_LL,
+ OPCODE_MUL_AD_HL,
+ OPCODE_MUL_AD_LH,
+ OPCODE_MUL_AD_HH,
+ OPCODE_MUL_DA_LL,
+ OPCODE_MUL_DA_HL,
+ OPCODE_MUL_DA_LH,
+ OPCODE_MUL_DA_HH,
+ OPCODE_MUL_DD_LL,
+ OPCODE_MUL_DD_HL,
+ OPCODE_MUL_DD_LH,
+ OPCODE_MUL_DD_HH,
+ OPCODE_MULA_AA_LL,
+ OPCODE_MULA_AA_HL,
+ OPCODE_MULA_AA_LH,
+ OPCODE_MULA_AA_HH,
+ OPCODE_MULS_AA_LL,
+ OPCODE_MULS_AA_HL,
+ OPCODE_MULS_AA_LH,
+ OPCODE_MULS_AA_HH,
+ OPCODE_MULA_AD_LL,
+ OPCODE_MULA_AD_HL,
+ OPCODE_MULA_AD_LH,
+ OPCODE_MULA_AD_HH,
+ OPCODE_MULS_AD_LL,
+ OPCODE_MULS_AD_HL,
+ OPCODE_MULS_AD_LH,
+ OPCODE_MULS_AD_HH,
+ OPCODE_MULA_DA_LL,
+ OPCODE_MULA_DA_HL,
+ OPCODE_MULA_DA_LH,
+ OPCODE_MULA_DA_HH,
+ OPCODE_MULS_DA_LL,
+ OPCODE_MULS_DA_HL,
+ OPCODE_MULS_DA_LH,
+ OPCODE_MULS_DA_HH,
+ OPCODE_MULA_DD_LL,
+ OPCODE_MULA_DD_HL,
+ OPCODE_MULA_DD_LH,
+ OPCODE_MULA_DD_HH,
+ OPCODE_MULS_DD_LL,
+ OPCODE_MULS_DD_HL,
+ OPCODE_MULS_DD_LH,
+ OPCODE_MULS_DD_HH,
+ OPCODE_MULA_DA_LL_LDDEC,
+ OPCODE_MULA_DA_LL_LDINC,
+ OPCODE_MULA_DA_HL_LDDEC,
+ OPCODE_MULA_DA_HL_LDINC,
+ OPCODE_MULA_DA_LH_LDDEC,
+ OPCODE_MULA_DA_LH_LDINC,
+ OPCODE_MULA_DA_HH_LDDEC,
+ OPCODE_MULA_DA_HH_LDINC,
+ OPCODE_MULA_DD_LL_LDDEC,
+ OPCODE_MULA_DD_LL_LDINC,
+ OPCODE_MULA_DD_HL_LDDEC,
+ OPCODE_MULA_DD_HL_LDINC,
+ OPCODE_MULA_DD_LH_LDDEC,
+ OPCODE_MULA_DD_LH_LDINC,
+ OPCODE_MULA_DD_HH_LDDEC,
+ OPCODE_MULA_DD_HH_LDINC,
+ OPCODE_LDDEC,
+ OPCODE_LDINC,
+ OPCODE_RSR_M0,
+ OPCODE_WSR_M0,
+ OPCODE_XSR_M0,
+ OPCODE_RSR_M1,
+ OPCODE_WSR_M1,
+ OPCODE_XSR_M1,
+ OPCODE_RSR_M2,
+ OPCODE_WSR_M2,
+ OPCODE_XSR_M2,
+ OPCODE_RSR_M3,
+ OPCODE_WSR_M3,
+ OPCODE_XSR_M3,
+ OPCODE_RSR_ACCLO,
+ OPCODE_WSR_ACCLO,
+ OPCODE_XSR_ACCLO,
+ OPCODE_RSR_ACCHI,
+ OPCODE_WSR_ACCHI,
+ OPCODE_XSR_ACCHI,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DBREAKA0,
+ OPCODE_WSR_DBREAKA0,
+ OPCODE_XSR_DBREAKA0,
+ OPCODE_RSR_DBREAKC0,
+ OPCODE_WSR_DBREAKC0,
+ OPCODE_XSR_DBREAKC0,
+ OPCODE_RSR_DBREAKA1,
+ OPCODE_WSR_DBREAKA1,
+ OPCODE_XSR_DBREAKA1,
+ OPCODE_RSR_DBREAKC1,
+ OPCODE_WSR_DBREAKC1,
+ OPCODE_XSR_DBREAKC1,
+ OPCODE_RSR_IBREAKA0,
+ OPCODE_WSR_IBREAKA0,
+ OPCODE_XSR_IBREAKA0,
+ OPCODE_RSR_IBREAKA1,
+ OPCODE_WSR_IBREAKA1,
+ OPCODE_XSR_IBREAKA1,
+ OPCODE_RSR_IBREAKENABLE,
+ OPCODE_WSR_IBREAKENABLE,
+ OPCODE_XSR_IBREAKENABLE,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_WSR_MMID,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_RSR_CCOMPARE2,
+ OPCODE_WSR_CCOMPARE2,
+ OPCODE_XSR_CCOMPARE2,
+ OPCODE_IPF,
+ OPCODE_IHI,
+ OPCODE_IPFL,
+ OPCODE_IHU,
+ OPCODE_IIU,
+ OPCODE_III,
+ OPCODE_LICT,
+ OPCODE_LICW,
+ OPCODE_SICT,
+ OPCODE_SICW,
+ OPCODE_DHWB,
+ OPCODE_DHWBI,
+ OPCODE_DIWB,
+ OPCODE_DIWBI,
+ OPCODE_DHI,
+ OPCODE_DII,
+ OPCODE_DPFR,
+ OPCODE_DPFW,
+ OPCODE_DPFRO,
+ OPCODE_DPFWO,
+ OPCODE_DPFL,
+ OPCODE_DHU,
+ OPCODE_DIU,
+ OPCODE_SDCT,
+ OPCODE_LDCT,
+ OPCODE_WSR_PTEVADDR,
+ OPCODE_RSR_PTEVADDR,
+ OPCODE_XSR_PTEVADDR,
+ OPCODE_RSR_RASID,
+ OPCODE_WSR_RASID,
+ OPCODE_XSR_RASID,
+ OPCODE_RSR_ITLBCFG,
+ OPCODE_WSR_ITLBCFG,
+ OPCODE_XSR_ITLBCFG,
+ OPCODE_RSR_DTLBCFG,
+ OPCODE_WSR_DTLBCFG,
+ OPCODE_XSR_DTLBCFG,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_LDPTE,
+ OPCODE_HWWITLBA,
+ OPCODE_HWWDTLBA,
+ OPCODE_RSR_CPENABLE,
+ OPCODE_WSR_CPENABLE,
+ OPCODE_XSR_CPENABLE,
+ OPCODE_CLAMPS,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_QUOU,
+ OPCODE_QUOS,
+ OPCODE_REMU,
+ OPCODE_REMS,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_EXPSTATE,
+ OPCODE_WUR_EXPSTATE,
+ OPCODE_READ_IMPWIRE,
+ OPCODE_SETB_EXPSTATE,
+ OPCODE_CLRB_EXPSTATE,
+ OPCODE_WRMSK_EXPSTATE
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ break;
+ case 2:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_RET;
+ case 1:
+ return OPCODE_RETW;
+ case 2:
+ return OPCODE_JX;
+ }
+ break;
+ case 3:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_CALLX0;
+ case 1:
+ return OPCODE_CALLX4;
+ case 2:
+ return OPCODE_CALLX8;
+ case 3:
+ return OPCODE_CALLX12;
+ }
+ break;
+ }
+ break;
+ case 1:
+ return OPCODE_MOVSP;
+ case 2:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_ISYNC;
+ case 1:
+ return OPCODE_RSYNC;
+ case 2:
+ return OPCODE_ESYNC;
+ case 3:
+ return OPCODE_DSYNC;
+ case 8:
+ return OPCODE_EXCW;
+ case 12:
+ return OPCODE_MEMW;
+ case 13:
+ return OPCODE_EXTW;
+ case 15:
+ return OPCODE_NOP;
+ }
+ }
+ break;
+ case 3:
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_RFE;
+ case 2:
+ return OPCODE_RFDE;
+ case 4:
+ return OPCODE_RFWO;
+ case 5:
+ return OPCODE_RFWU;
+ }
+ break;
+ case 1:
+ return OPCODE_RFI;
+ }
+ break;
+ case 4:
+ return OPCODE_BREAK;
+ case 5:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ break;
+ case 1:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ break;
+ }
+ break;
+ case 6:
+ return OPCODE_RSIL;
+ case 7:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ break;
+ }
+ break;
+ case 1:
+ return OPCODE_AND;
+ case 2:
+ return OPCODE_OR;
+ case 3:
+ return OPCODE_XOR;
+ case 4:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ break;
+ case 1:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ break;
+ case 2:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ break;
+ case 3:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ break;
+ case 4:
+ if (Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ break;
+ case 6:
+ return OPCODE_RER;
+ case 7:
+ return OPCODE_WER;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ break;
+ case 14:
+ return OPCODE_NSA;
+ case 15:
+ return OPCODE_NSAU;
+ }
+ break;
+ case 5:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 1:
+ return OPCODE_HWWITLBA;
+ case 3:
+ return OPCODE_RITLB0;
+ case 4:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ break;
+ case 5:
+ return OPCODE_PITLB;
+ case 6:
+ return OPCODE_WITLB;
+ case 7:
+ return OPCODE_RITLB1;
+ case 9:
+ return OPCODE_HWWDTLBA;
+ case 11:
+ return OPCODE_RDTLB0;
+ case 12:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ break;
+ case 13:
+ return OPCODE_PDTLB;
+ case 14:
+ return OPCODE_WDTLB;
+ case 15:
+ return OPCODE_RDTLB1;
+ }
+ break;
+ case 6:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_NEG;
+ case 1:
+ return OPCODE_ABS;
+ }
+ break;
+ case 8:
+ return OPCODE_ADD;
+ case 9:
+ return OPCODE_ADDX2;
+ case 10:
+ return OPCODE_ADDX4;
+ case 11:
+ return OPCODE_ADDX8;
+ case 12:
+ return OPCODE_SUB;
+ case 13:
+ return OPCODE_SUBX2;
+ case 14:
+ return OPCODE_SUBX4;
+ case 15:
+ return OPCODE_SUBX8;
+ }
+ break;
+ case 1:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ case 1:
+ return OPCODE_SLLI;
+ case 2:
+ case 3:
+ return OPCODE_SRAI;
+ case 4:
+ return OPCODE_SRLI;
+ case 6:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_XSR_LBEG;
+ case 1:
+ return OPCODE_XSR_LEND;
+ case 2:
+ return OPCODE_XSR_LCOUNT;
+ case 3:
+ return OPCODE_XSR_SAR;
+ case 5:
+ return OPCODE_XSR_LITBASE;
+ case 12:
+ return OPCODE_XSR_SCOMPARE1;
+ case 16:
+ return OPCODE_XSR_ACCLO;
+ case 17:
+ return OPCODE_XSR_ACCHI;
+ case 32:
+ return OPCODE_XSR_M0;
+ case 33:
+ return OPCODE_XSR_M1;
+ case 34:
+ return OPCODE_XSR_M2;
+ case 35:
+ return OPCODE_XSR_M3;
+ case 72:
+ return OPCODE_XSR_WINDOWBASE;
+ case 73:
+ return OPCODE_XSR_WINDOWSTART;
+ case 83:
+ return OPCODE_XSR_PTEVADDR;
+ case 90:
+ return OPCODE_XSR_RASID;
+ case 91:
+ return OPCODE_XSR_ITLBCFG;
+ case 92:
+ return OPCODE_XSR_DTLBCFG;
+ case 96:
+ return OPCODE_XSR_IBREAKENABLE;
+ case 99:
+ return OPCODE_XSR_ATOMCTL;
+ case 104:
+ return OPCODE_XSR_DDR;
+ case 128:
+ return OPCODE_XSR_IBREAKA0;
+ case 129:
+ return OPCODE_XSR_IBREAKA1;
+ case 144:
+ return OPCODE_XSR_DBREAKA0;
+ case 145:
+ return OPCODE_XSR_DBREAKA1;
+ case 160:
+ return OPCODE_XSR_DBREAKC0;
+ case 161:
+ return OPCODE_XSR_DBREAKC1;
+ case 177:
+ return OPCODE_XSR_EPC1;
+ case 178:
+ return OPCODE_XSR_EPC2;
+ case 179:
+ return OPCODE_XSR_EPC3;
+ case 180:
+ return OPCODE_XSR_EPC4;
+ case 181:
+ return OPCODE_XSR_EPC5;
+ case 182:
+ return OPCODE_XSR_EPC6;
+ case 183:
+ return OPCODE_XSR_EPC7;
+ case 192:
+ return OPCODE_XSR_DEPC;
+ case 194:
+ return OPCODE_XSR_EPS2;
+ case 195:
+ return OPCODE_XSR_EPS3;
+ case 196:
+ return OPCODE_XSR_EPS4;
+ case 197:
+ return OPCODE_XSR_EPS5;
+ case 198:
+ return OPCODE_XSR_EPS6;
+ case 199:
+ return OPCODE_XSR_EPS7;
+ case 209:
+ return OPCODE_XSR_EXCSAVE1;
+ case 210:
+ return OPCODE_XSR_EXCSAVE2;
+ case 211:
+ return OPCODE_XSR_EXCSAVE3;
+ case 212:
+ return OPCODE_XSR_EXCSAVE4;
+ case 213:
+ return OPCODE_XSR_EXCSAVE5;
+ case 214:
+ return OPCODE_XSR_EXCSAVE6;
+ case 215:
+ return OPCODE_XSR_EXCSAVE7;
+ case 224:
+ return OPCODE_XSR_CPENABLE;
+ case 228:
+ return OPCODE_XSR_INTENABLE;
+ case 230:
+ return OPCODE_XSR_PS;
+ case 231:
+ return OPCODE_XSR_VECBASE;
+ case 232:
+ return OPCODE_XSR_EXCCAUSE;
+ case 233:
+ return OPCODE_XSR_DEBUGCAUSE;
+ case 234:
+ return OPCODE_XSR_CCOUNT;
+ case 236:
+ return OPCODE_XSR_ICOUNT;
+ case 237:
+ return OPCODE_XSR_ICOUNTLEVEL;
+ case 238:
+ return OPCODE_XSR_EXCVADDR;
+ case 240:
+ return OPCODE_XSR_CCOMPARE0;
+ case 241:
+ return OPCODE_XSR_CCOMPARE1;
+ case 242:
+ return OPCODE_XSR_CCOMPARE2;
+ case 244:
+ return OPCODE_XSR_MISC0;
+ case 245:
+ return OPCODE_XSR_MISC1;
+ }
+ break;
+ case 8:
+ return OPCODE_SRC;
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ break;
+ case 10:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ break;
+ case 12:
+ return OPCODE_MUL16U;
+ case 13:
+ return OPCODE_MUL16S;
+ case 15:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_LICT;
+ case 1:
+ return OPCODE_SICT;
+ case 2:
+ return OPCODE_LICW;
+ case 3:
+ return OPCODE_SICW;
+ case 8:
+ return OPCODE_LDCT;
+ case 9:
+ return OPCODE_SDCT;
+ case 14:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ break;
+ case 15:
+ return OPCODE_LDPTE;
+ }
+ break;
+ }
+ break;
+ case 2:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 8:
+ return OPCODE_MULL;
+ case 12:
+ return OPCODE_QUOU;
+ case 13:
+ return OPCODE_QUOS;
+ case 14:
+ return OPCODE_REMU;
+ case 15:
+ return OPCODE_REMS;
+ }
+ break;
+ case 3:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_RSR_LBEG;
+ case 1:
+ return OPCODE_RSR_LEND;
+ case 2:
+ return OPCODE_RSR_LCOUNT;
+ case 3:
+ return OPCODE_RSR_SAR;
+ case 5:
+ return OPCODE_RSR_LITBASE;
+ case 12:
+ return OPCODE_RSR_SCOMPARE1;
+ case 16:
+ return OPCODE_RSR_ACCLO;
+ case 17:
+ return OPCODE_RSR_ACCHI;
+ case 32:
+ return OPCODE_RSR_M0;
+ case 33:
+ return OPCODE_RSR_M1;
+ case 34:
+ return OPCODE_RSR_M2;
+ case 35:
+ return OPCODE_RSR_M3;
+ case 72:
+ return OPCODE_RSR_WINDOWBASE;
+ case 73:
+ return OPCODE_RSR_WINDOWSTART;
+ case 83:
+ return OPCODE_RSR_PTEVADDR;
+ case 90:
+ return OPCODE_RSR_RASID;
+ case 91:
+ return OPCODE_RSR_ITLBCFG;
+ case 92:
+ return OPCODE_RSR_DTLBCFG;
+ case 96:
+ return OPCODE_RSR_IBREAKENABLE;
+ case 99:
+ return OPCODE_RSR_ATOMCTL;
+ case 104:
+ return OPCODE_RSR_DDR;
+ case 128:
+ return OPCODE_RSR_IBREAKA0;
+ case 129:
+ return OPCODE_RSR_IBREAKA1;
+ case 144:
+ return OPCODE_RSR_DBREAKA0;
+ case 145:
+ return OPCODE_RSR_DBREAKA1;
+ case 160:
+ return OPCODE_RSR_DBREAKC0;
+ case 161:
+ return OPCODE_RSR_DBREAKC1;
+ case 176:
+ return OPCODE_RSR_176;
+ case 177:
+ return OPCODE_RSR_EPC1;
+ case 178:
+ return OPCODE_RSR_EPC2;
+ case 179:
+ return OPCODE_RSR_EPC3;
+ case 180:
+ return OPCODE_RSR_EPC4;
+ case 181:
+ return OPCODE_RSR_EPC5;
+ case 182:
+ return OPCODE_RSR_EPC6;
+ case 183:
+ return OPCODE_RSR_EPC7;
+ case 192:
+ return OPCODE_RSR_DEPC;
+ case 194:
+ return OPCODE_RSR_EPS2;
+ case 195:
+ return OPCODE_RSR_EPS3;
+ case 196:
+ return OPCODE_RSR_EPS4;
+ case 197:
+ return OPCODE_RSR_EPS5;
+ case 198:
+ return OPCODE_RSR_EPS6;
+ case 199:
+ return OPCODE_RSR_EPS7;
+ case 208:
+ return OPCODE_RSR_208;
+ case 209:
+ return OPCODE_RSR_EXCSAVE1;
+ case 210:
+ return OPCODE_RSR_EXCSAVE2;
+ case 211:
+ return OPCODE_RSR_EXCSAVE3;
+ case 212:
+ return OPCODE_RSR_EXCSAVE4;
+ case 213:
+ return OPCODE_RSR_EXCSAVE5;
+ case 214:
+ return OPCODE_RSR_EXCSAVE6;
+ case 215:
+ return OPCODE_RSR_EXCSAVE7;
+ case 224:
+ return OPCODE_RSR_CPENABLE;
+ case 226:
+ return OPCODE_RSR_INTERRUPT;
+ case 228:
+ return OPCODE_RSR_INTENABLE;
+ case 230:
+ return OPCODE_RSR_PS;
+ case 231:
+ return OPCODE_RSR_VECBASE;
+ case 232:
+ return OPCODE_RSR_EXCCAUSE;
+ case 233:
+ return OPCODE_RSR_DEBUGCAUSE;
+ case 234:
+ return OPCODE_RSR_CCOUNT;
+ case 235:
+ return OPCODE_RSR_PRID;
+ case 236:
+ return OPCODE_RSR_ICOUNT;
+ case 237:
+ return OPCODE_RSR_ICOUNTLEVEL;
+ case 238:
+ return OPCODE_RSR_EXCVADDR;
+ case 240:
+ return OPCODE_RSR_CCOMPARE0;
+ case 241:
+ return OPCODE_RSR_CCOMPARE1;
+ case 242:
+ return OPCODE_RSR_CCOMPARE2;
+ case 244:
+ return OPCODE_RSR_MISC0;
+ case 245:
+ return OPCODE_RSR_MISC1;
+ }
+ break;
+ case 1:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_WSR_LBEG;
+ case 1:
+ return OPCODE_WSR_LEND;
+ case 2:
+ return OPCODE_WSR_LCOUNT;
+ case 3:
+ return OPCODE_WSR_SAR;
+ case 5:
+ return OPCODE_WSR_LITBASE;
+ case 12:
+ return OPCODE_WSR_SCOMPARE1;
+ case 16:
+ return OPCODE_WSR_ACCLO;
+ case 17:
+ return OPCODE_WSR_ACCHI;
+ case 32:
+ return OPCODE_WSR_M0;
+ case 33:
+ return OPCODE_WSR_M1;
+ case 34:
+ return OPCODE_WSR_M2;
+ case 35:
+ return OPCODE_WSR_M3;
+ case 72:
+ return OPCODE_WSR_WINDOWBASE;
+ case 73:
+ return OPCODE_WSR_WINDOWSTART;
+ case 83:
+ return OPCODE_WSR_PTEVADDR;
+ case 89:
+ return OPCODE_WSR_MMID;
+ case 90:
+ return OPCODE_WSR_RASID;
+ case 91:
+ return OPCODE_WSR_ITLBCFG;
+ case 92:
+ return OPCODE_WSR_DTLBCFG;
+ case 96:
+ return OPCODE_WSR_IBREAKENABLE;
+ case 99:
+ return OPCODE_WSR_ATOMCTL;
+ case 104:
+ return OPCODE_WSR_DDR;
+ case 128:
+ return OPCODE_WSR_IBREAKA0;
+ case 129:
+ return OPCODE_WSR_IBREAKA1;
+ case 144:
+ return OPCODE_WSR_DBREAKA0;
+ case 145:
+ return OPCODE_WSR_DBREAKA1;
+ case 160:
+ return OPCODE_WSR_DBREAKC0;
+ case 161:
+ return OPCODE_WSR_DBREAKC1;
+ case 176:
+ return OPCODE_WSR_176;
+ case 177:
+ return OPCODE_WSR_EPC1;
+ case 178:
+ return OPCODE_WSR_EPC2;
+ case 179:
+ return OPCODE_WSR_EPC3;
+ case 180:
+ return OPCODE_WSR_EPC4;
+ case 181:
+ return OPCODE_WSR_EPC5;
+ case 182:
+ return OPCODE_WSR_EPC6;
+ case 183:
+ return OPCODE_WSR_EPC7;
+ case 192:
+ return OPCODE_WSR_DEPC;
+ case 194:
+ return OPCODE_WSR_EPS2;
+ case 195:
+ return OPCODE_WSR_EPS3;
+ case 196:
+ return OPCODE_WSR_EPS4;
+ case 197:
+ return OPCODE_WSR_EPS5;
+ case 198:
+ return OPCODE_WSR_EPS6;
+ case 199:
+ return OPCODE_WSR_EPS7;
+ case 209:
+ return OPCODE_WSR_EXCSAVE1;
+ case 210:
+ return OPCODE_WSR_EXCSAVE2;
+ case 211:
+ return OPCODE_WSR_EXCSAVE3;
+ case 212:
+ return OPCODE_WSR_EXCSAVE4;
+ case 213:
+ return OPCODE_WSR_EXCSAVE5;
+ case 214:
+ return OPCODE_WSR_EXCSAVE6;
+ case 215:
+ return OPCODE_WSR_EXCSAVE7;
+ case 224:
+ return OPCODE_WSR_CPENABLE;
+ case 226:
+ return OPCODE_WSR_INTSET;
+ case 227:
+ return OPCODE_WSR_INTCLEAR;
+ case 228:
+ return OPCODE_WSR_INTENABLE;
+ case 230:
+ return OPCODE_WSR_PS;
+ case 231:
+ return OPCODE_WSR_VECBASE;
+ case 232:
+ return OPCODE_WSR_EXCCAUSE;
+ case 233:
+ return OPCODE_WSR_DEBUGCAUSE;
+ case 234:
+ return OPCODE_WSR_CCOUNT;
+ case 236:
+ return OPCODE_WSR_ICOUNT;
+ case 237:
+ return OPCODE_WSR_ICOUNTLEVEL;
+ case 238:
+ return OPCODE_WSR_EXCVADDR;
+ case 240:
+ return OPCODE_WSR_CCOMPARE0;
+ case 241:
+ return OPCODE_WSR_CCOMPARE1;
+ case 242:
+ return OPCODE_WSR_CCOMPARE2;
+ case 244:
+ return OPCODE_WSR_MISC0;
+ case 245:
+ return OPCODE_WSR_MISC1;
+ }
+ break;
+ case 2:
+ return OPCODE_SEXT;
+ case 3:
+ return OPCODE_CLAMPS;
+ case 4:
+ return OPCODE_MIN;
+ case 5:
+ return OPCODE_MAX;
+ case 6:
+ return OPCODE_MINU;
+ case 7:
+ return OPCODE_MAXU;
+ case 8:
+ return OPCODE_MOVEQZ;
+ case 9:
+ return OPCODE_MOVNEZ;
+ case 10:
+ return OPCODE_MOVLTZ;
+ case 11:
+ return OPCODE_MOVGEZ;
+ case 14:
+ switch (Field_st_Slot_inst_get (insn))
+ {
+ case 230:
+ return OPCODE_RUR_EXPSTATE;
+ case 231:
+ return OPCODE_RUR_THREADPTR;
+ }
+ break;
+ case 15:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 230:
+ return OPCODE_WUR_EXPSTATE;
+ case 231:
+ return OPCODE_WUR_THREADPTR;
+ }
+ break;
+ }
+ break;
+ case 4:
+ case 5:
+ return OPCODE_EXTUI;
+ case 9:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_L32E;
+ case 4:
+ return OPCODE_S32E;
+ }
+ break;
+ }
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_READ_IMPWIRE;
+ break;
+ case 1:
+ if (Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_SETB_EXPSTATE;
+ if (Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_CLRB_EXPSTATE;
+ break;
+ case 2:
+ if (Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_WRMSK_EXPSTATE;
+ break;
+ }
+ break;
+ case 1:
+ return OPCODE_L32R;
+ case 2:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_L8UI;
+ case 1:
+ return OPCODE_L16UI;
+ case 2:
+ return OPCODE_L32I;
+ case 4:
+ return OPCODE_S8I;
+ case 5:
+ return OPCODE_S16I;
+ case 6:
+ return OPCODE_S32I;
+ case 7:
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_DPFR;
+ case 1:
+ return OPCODE_DPFW;
+ case 2:
+ return OPCODE_DPFRO;
+ case 3:
+ return OPCODE_DPFWO;
+ case 4:
+ return OPCODE_DHWB;
+ case 5:
+ return OPCODE_DHWBI;
+ case 6:
+ return OPCODE_DHI;
+ case 7:
+ return OPCODE_DII;
+ case 8:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_DPFL;
+ case 2:
+ return OPCODE_DHU;
+ case 3:
+ return OPCODE_DIU;
+ case 4:
+ return OPCODE_DIWB;
+ case 5:
+ return OPCODE_DIWBI;
+ }
+ break;
+ case 12:
+ return OPCODE_IPF;
+ case 13:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_IPFL;
+ case 2:
+ return OPCODE_IHU;
+ case 3:
+ return OPCODE_IIU;
+ }
+ break;
+ case 14:
+ return OPCODE_IHI;
+ case 15:
+ return OPCODE_III;
+ }
+ break;
+ case 9:
+ return OPCODE_L16SI;
+ case 10:
+ return OPCODE_MOVI;
+ case 11:
+ return OPCODE_L32AI;
+ case 12:
+ return OPCODE_ADDI;
+ case 13:
+ return OPCODE_ADDMI;
+ case 14:
+ return OPCODE_S32C1I;
+ case 15:
+ return OPCODE_S32RI;
+ }
+ break;
+ case 4:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDINC;
+ break;
+ case 9:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDINC;
+ break;
+ case 10:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDINC;
+ break;
+ case 11:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDINC;
+ break;
+ }
+ break;
+ case 1:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDDEC;
+ break;
+ case 9:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDDEC;
+ break;
+ case 10:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDDEC;
+ break;
+ case 11:
+ if (Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDDEC;
+ break;
+ }
+ break;
+ case 2:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LL;
+ break;
+ case 5:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HL;
+ break;
+ case 6:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LH;
+ break;
+ case 7:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HH;
+ break;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL;
+ break;
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL;
+ break;
+ case 10:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH;
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH;
+ break;
+ case 12:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LL;
+ break;
+ case 13:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HL;
+ break;
+ case 14:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LH;
+ break;
+ case 15:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HH;
+ break;
+ }
+ break;
+ case 3:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LL;
+ break;
+ case 5:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HL;
+ break;
+ case 6:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LH;
+ break;
+ case 7:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HH;
+ break;
+ case 8:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LL;
+ break;
+ case 9:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HL;
+ break;
+ case 10:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LH;
+ break;
+ case 11:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HH;
+ break;
+ case 12:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LL;
+ break;
+ case 13:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HL;
+ break;
+ case 14:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LH;
+ break;
+ case 15:
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HH;
+ break;
+ }
+ break;
+ case 4:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDINC;
+ break;
+ case 9:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDINC;
+ break;
+ case 10:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDINC;
+ break;
+ case 11:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDINC;
+ break;
+ }
+ break;
+ case 5:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 8:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDDEC;
+ break;
+ case 9:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDDEC;
+ break;
+ case 10:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDDEC;
+ break;
+ case 11:
+ if (Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDDEC;
+ break;
+ }
+ break;
+ case 6:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LL;
+ break;
+ case 5:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HL;
+ break;
+ case 6:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LH;
+ break;
+ case 7:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HH;
+ break;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL;
+ break;
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL;
+ break;
+ case 10:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH;
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH;
+ break;
+ case 12:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LL;
+ break;
+ case 13:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HL;
+ break;
+ case 14:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LH;
+ break;
+ case 15:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HH;
+ break;
+ }
+ break;
+ case 7:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LL;
+ break;
+ case 1:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HL;
+ break;
+ case 2:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LH;
+ break;
+ case 3:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HH;
+ break;
+ case 4:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LL;
+ break;
+ case 5:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HL;
+ break;
+ case 6:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LH;
+ break;
+ case 7:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HH;
+ break;
+ case 8:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LL;
+ break;
+ case 9:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HL;
+ break;
+ case 10:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LH;
+ break;
+ case 11:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HH;
+ break;
+ case 12:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LL;
+ break;
+ case 13:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HL;
+ break;
+ case 14:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LH;
+ break;
+ case 15:
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HH;
+ break;
+ }
+ break;
+ case 8:
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDINC;
+ break;
+ case 9:
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDDEC;
+ break;
+ }
+ break;
+ case 5:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_CALL0;
+ case 1:
+ return OPCODE_CALL4;
+ case 2:
+ return OPCODE_CALL8;
+ case 3:
+ return OPCODE_CALL12;
+ }
+ break;
+ case 6:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_J;
+ case 1:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_BEQZ;
+ case 1:
+ return OPCODE_BNEZ;
+ case 2:
+ return OPCODE_BLTZ;
+ case 3:
+ return OPCODE_BGEZ;
+ }
+ break;
+ case 2:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_BEQI;
+ case 1:
+ return OPCODE_BNEI;
+ case 2:
+ return OPCODE_BLTI;
+ case 3:
+ return OPCODE_BGEI;
+ }
+ break;
+ case 3:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_ENTRY;
+ case 1:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 8:
+ return OPCODE_LOOP;
+ case 9:
+ return OPCODE_LOOPNEZ;
+ case 10:
+ return OPCODE_LOOPGTZ;
+ }
+ break;
+ case 2:
+ return OPCODE_BLTUI;
+ case 3:
+ return OPCODE_BGEUI;
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return OPCODE_BNONE;
+ case 1:
+ return OPCODE_BEQ;
+ case 2:
+ return OPCODE_BLT;
+ case 3:
+ return OPCODE_BLTU;
+ case 4:
+ return OPCODE_BALL;
+ case 5:
+ return OPCODE_BBC;
+ case 6:
+ case 7:
+ return OPCODE_BBCI;
+ case 8:
+ return OPCODE_BANY;
+ case 9:
+ return OPCODE_BNE;
+ case 10:
+ return OPCODE_BGE;
+ case 11:
+ return OPCODE_BGEU;
+ case 12:
+ return OPCODE_BNALL;
+ case 13:
+ return OPCODE_BBS;
+ case 14:
+ case 15:
+ return OPCODE_BBSI;
+ }
+ break;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst16b_get (insn))
+ {
+ case 12:
+ switch (Field_i_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return OPCODE_MOVI_N;
+ case 1:
+ switch (Field_z_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return OPCODE_BEQZ_N;
+ case 1:
+ return OPCODE_BNEZ_N;
+ }
+ break;
+ }
+ break;
+ case 13:
+ switch (Field_r_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return OPCODE_MOV_N;
+ case 15:
+ switch (Field_t_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return OPCODE_RET_N;
+ case 1:
+ return OPCODE_RETW_N;
+ case 2:
+ return OPCODE_BREAK_N;
+ case 3:
+ if (Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ break;
+ case 6:
+ if (Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst16a_get (insn))
+ {
+ case 8:
+ return OPCODE_L32I_N;
+ case 9:
+ return OPCODE_S32I_N;
+ case 10:
+ return OPCODE_ADD_N;
+ case 11:
+ return OPCODE_ADDI_N;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_get,
+ Field_rbit2_Slot_inst_get,
+ Field_rhi_Slot_inst_get,
+ Field_t3_Slot_inst_get,
+ Field_tbit2_Slot_inst_get,
+ Field_tlo_Slot_inst_get,
+ Field_w_Slot_inst_get,
+ Field_y_Slot_inst_get,
+ Field_x_Slot_inst_get,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_set,
+ Field_rbit2_Slot_inst_set,
+ Field_rhi_Slot_inst_set,
+ Field_t3_Slot_inst_set,
+ Field_tbit2_Slot_inst_set,
+ Field_tlo_Slot_inst_set,
+ Field_w_Slot_inst_set,
+ Field_y_Slot_inst_set,
+ Field_x_Slot_inst_set,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[16] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int op0 = insn[0] & 0xf;
+ return length_table[op0];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 56 /* num_fields */,
+ 93, operands,
+ 326, iclasses,
+ 452, opcodes, 0,
+ 2, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 1, interfaces, 0,
+ 0, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
-
- Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#include "qemu/osdep.h"
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "ACCLO", 16, 0 },
- { "ACCHI", 17, 0 },
- { "M0", 32, 0 },
- { "M1", 33, 0 },
- { "M2", 34, 0 },
- { "M3", 35, 0 },
- { "PTEVADDR", 83, 0 },
- { "MMID", 89, 0 },
- { "DDR", 104, 0 },
- { "176", 176, 0 },
- { "208", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EPC5", 181, 0 },
- { "EPC6", 182, 0 },
- { "EPC7", 183, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EXCSAVE5", 213, 0 },
- { "EXCSAVE6", 214, 0 },
- { "EXCSAVE7", 215, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EPS5", 197, 0 },
- { "EPS6", 198, 0 },
- { "EPS7", 199, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "LITBASE", 5, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "RASID", 90, 0 },
- { "ITLBCFG", 91, 0 },
- { "DTLBCFG", 92, 0 },
- { "CPENABLE", 224, 0 },
- { "SCOMPARE1", 12, 0 },
- { "ATOMCTL", 99, 0 },
- { "THREADPTR", 231, 1 },
- { "EXPSTATE", 230, 1 }
-};
-
-#define NUM_SYSREGS 71
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 231
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 22, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EPC5", 32, 0 },
- { "EPC6", 32, 0 },
- { "EPC7", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EXCSAVE5", 32, 0 },
- { "EXCSAVE6", 32, 0 },
- { "EXCSAVE7", 32, 0 },
- { "EPS2", 15, 0 },
- { "EPS3", 15, 0 },
- { "EPS4", 15, 0 },
- { "EPS5", 15, 0 },
- { "EPS6", 15, 0 },
- { "EPS7", 15, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSRING", 2, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 3, 0 },
- { "WindowStart", 8, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "THREADPTR", 32, 0 },
- { "LITBADDR", 20, 0 },
- { "LITBEN", 1, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "ACC", 40, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 22, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "ASID3", 8, 0 },
- { "ASID2", 8, 0 },
- { "ASID1", 8, 0 },
- { "INSTPGSZID6", 1, 0 },
- { "INSTPGSZID5", 1, 0 },
- { "INSTPGSZID4", 2, 0 },
- { "DATAPGSZID6", 1, 0 },
- { "DATAPGSZID5", 1, 0 },
- { "DATAPGSZID4", 2, 0 },
- { "PTBASE", 10, 0 },
- { "CPENABLE", 8, 0 },
- { "SCOMPARE1", 32, 0 },
- { "ATOMCTL", 6, 0 },
- { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
-};
-
-#define NUM_STATES 78
-
-enum xtensa_state_id {
- STATE_LCOUNT,
- STATE_PC,
- STATE_ICOUNT,
- STATE_DDR,
- STATE_INTERRUPT,
- STATE_CCOUNT,
- STATE_XTSYNC,
- STATE_VECBASE,
- STATE_EPC1,
- STATE_EPC2,
- STATE_EPC3,
- STATE_EPC4,
- STATE_EPC5,
- STATE_EPC6,
- STATE_EPC7,
- STATE_EXCSAVE1,
- STATE_EXCSAVE2,
- STATE_EXCSAVE3,
- STATE_EXCSAVE4,
- STATE_EXCSAVE5,
- STATE_EXCSAVE6,
- STATE_EXCSAVE7,
- STATE_EPS2,
- STATE_EPS3,
- STATE_EPS4,
- STATE_EPS5,
- STATE_EPS6,
- STATE_EPS7,
- STATE_EXCCAUSE,
- STATE_PSINTLEVEL,
- STATE_PSUM,
- STATE_PSWOE,
- STATE_PSRING,
- STATE_PSEXCM,
- STATE_DEPC,
- STATE_EXCVADDR,
- STATE_WindowBase,
- STATE_WindowStart,
- STATE_PSCALLINC,
- STATE_PSOWB,
- STATE_LBEG,
- STATE_LEND,
- STATE_SAR,
- STATE_THREADPTR,
- STATE_LITBADDR,
- STATE_LITBEN,
- STATE_MISC0,
- STATE_MISC1,
- STATE_ACC,
- STATE_InOCDMode,
- STATE_INTENABLE,
- STATE_DBREAKA0,
- STATE_DBREAKC0,
- STATE_DBREAKA1,
- STATE_DBREAKC1,
- STATE_IBREAKA0,
- STATE_IBREAKA1,
- STATE_IBREAKENABLE,
- STATE_ICOUNTLEVEL,
- STATE_DEBUGCAUSE,
- STATE_DBNUM,
- STATE_CCOMPARE0,
- STATE_CCOMPARE1,
- STATE_CCOMPARE2,
- STATE_ASID3,
- STATE_ASID2,
- STATE_ASID1,
- STATE_INSTPGSZID6,
- STATE_INSTPGSZID5,
- STATE_INSTPGSZID4,
- STATE_DATAPGSZID6,
- STATE_DATAPGSZID5,
- STATE_DATAPGSZID4,
- STATE_PTBASE,
- STATE_CPENABLE,
- STATE_SCOMPARE1,
- STATE_ATOMCTL,
- STATE_EXPSTATE
-};
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_w_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_y_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_x_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
- return tie_t;
-}
-
-static void
-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 17) >> 17;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-static unsigned
-Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 1;
-}
-
-static unsigned
-Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 2;
-}
-
-static unsigned
-Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 3;
-}
-
-enum xtensa_field_id {
- FIELD_t,
- FIELD_bbi4,
- FIELD_bbi,
- FIELD_imm12,
- FIELD_imm8,
- FIELD_s,
- FIELD_imm12b,
- FIELD_imm16,
- FIELD_m,
- FIELD_n,
- FIELD_offset,
- FIELD_op0,
- FIELD_op1,
- FIELD_op2,
- FIELD_r,
- FIELD_sa4,
- FIELD_sae4,
- FIELD_sae,
- FIELD_sal,
- FIELD_sargt,
- FIELD_sas4,
- FIELD_sas,
- FIELD_sr,
- FIELD_st,
- FIELD_thi3,
- FIELD_imm4,
- FIELD_mn,
- FIELD_i,
- FIELD_imm6lo,
- FIELD_imm6hi,
- FIELD_imm7lo,
- FIELD_imm7hi,
- FIELD_z,
- FIELD_imm6,
- FIELD_imm7,
- FIELD_r3,
- FIELD_rbit2,
- FIELD_rhi,
- FIELD_t3,
- FIELD_tbit2,
- FIELD_tlo,
- FIELD_w,
- FIELD_y,
- FIELD_x,
- FIELD_xt_wbr15_imm,
- FIELD_xt_wbr18_imm,
- FIELD_bitindex,
- FIELD_s3to1,
- FIELD__ar0,
- FIELD__ar4,
- FIELD__ar8,
- FIELD__ar12,
- FIELD__mr0,
- FIELD__mr1,
- FIELD__mr2,
- FIELD__mr3
-};
-
-\f
-/* Functional units. */
-
-static xtensa_funcUnit_internal funcUnits[] = {
-
-};
-
-\f
-/* Register files. */
-
-enum xtensa_regfile_id {
- REGFILE_AR,
- REGFILE_MR
-};
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", REGFILE_AR, 32, 32 },
- { "MR", "m", REGFILE_MR, 32, 4 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
- { "IMPWIRE", 32, 0, 0, 'i' }
-};
-
-enum xtensa_interface_id {
- INTERFACE_IMPWIRE
-};
-
-\f
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-Operand_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
- *valp = soffsetx4_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_encode (uint32 *valp)
-{
- unsigned offset_0, soffsetx4_0;
- soffsetx4_0 = *valp;
- offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
- *valp = offset_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- uimm12x8_0 = imm12_0 << 3;
- *valp = uimm12x8_0;
- return 0;
-}
-
-static int
-Operand_uimm12x8_encode (uint32 *valp)
-{
- unsigned imm12_0, uimm12x8_0;
- uimm12x8_0 = *valp;
- imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
- *valp = imm12_0;
- return 0;
-}
-
-static int
-Operand_simm4_decode (uint32 *valp)
-{
- unsigned simm4_0, mn_0;
- mn_0 = *valp & 0xf;
- simm4_0 = ((int) mn_0 << 28) >> 28;
- *valp = simm4_0;
- return 0;
-}
-
-static int
-Operand_simm4_encode (uint32 *valp)
-{
- unsigned mn_0, simm4_0;
- simm4_0 = *valp;
- mn_0 = (simm4_0 & 0xf);
- *valp = mn_0;
- return 0;
-}
-
-static int
-Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_arr_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ars_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_art_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar0_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar4_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar8_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar12_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ars_entry_encode (uint32 *valp)
-{
- return (*valp & ~0x1f) != 0;
-}
-
-static int
-Operand_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_0, r_0;
- r_0 = *valp & 0xf;
- immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
- *valp = immrx4_0;
- return 0;
-}
-
-static int
-Operand_immrx4_encode (uint32 *valp)
-{
- unsigned r_0, immrx4_0;
- immrx4_0 = *valp;
- r_0 = ((immrx4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_0, r_0;
- r_0 = *valp & 0xf;
- lsi4x4_0 = r_0 << 2;
- *valp = lsi4x4_0;
- return 0;
-}
-
-static int
-Operand_lsi4x4_encode (uint32 *valp)
-{
- unsigned r_0, lsi4x4_0;
- lsi4x4_0 = *valp;
- r_0 = ((lsi4x4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_simm7_decode (uint32 *valp)
-{
- unsigned simm7_0, imm7_0;
- imm7_0 = *valp & 0x7f;
- simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
- *valp = simm7_0;
- return 0;
-}
-
-static int
-Operand_simm7_encode (uint32 *valp)
-{
- unsigned imm7_0, simm7_0;
- simm7_0 = *valp;
- imm7_0 = (simm7_0 & 0x7f);
- *valp = imm7_0;
- return 0;
-}
-
-static int
-Operand_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_0, imm6_0;
- imm6_0 = *valp & 0x3f;
- uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
- *valp = uimm6_0;
- return 0;
-}
-
-static int
-Operand_uimm6_encode (uint32 *valp)
-{
- unsigned imm6_0, uimm6_0;
- uimm6_0 = *valp;
- imm6_0 = (uimm6_0 - 0x4) & 0x3f;
- *valp = imm6_0;
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_0, t_0;
- t_0 = *valp & 0xf;
- ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
- *valp = ai4const_0;
- return 0;
-}
-
-static int
-Operand_ai4const_encode (uint32 *valp)
-{
- unsigned t_0, ai4const_0;
- ai4const_0 = *valp;
- switch (ai4const_0)
- {
- case 0xffffffff: t_0 = 0; break;
- case 0x1: t_0 = 0x1; break;
- case 0x2: t_0 = 0x2; break;
- case 0x3: t_0 = 0x3; break;
- case 0x4: t_0 = 0x4; break;
- case 0x5: t_0 = 0x5; break;
- case 0x6: t_0 = 0x6; break;
- case 0x7: t_0 = 0x7; break;
- case 0x8: t_0 = 0x8; break;
- case 0x9: t_0 = 0x9; break;
- case 0xa: t_0 = 0xa; break;
- case 0xb: t_0 = 0xb; break;
- case 0xc: t_0 = 0xc; break;
- case 0xd: t_0 = 0xd; break;
- case 0xe: t_0 = 0xe; break;
- default: t_0 = 0xf; break;
- }
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_b4const_decode (uint32 *valp)
-{
- unsigned b4const_0, r_0;
- r_0 = *valp & 0xf;
- b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
- *valp = b4const_0;
- return 0;
-}
-
-static int
-Operand_b4const_encode (uint32 *valp)
-{
- unsigned r_0, b4const_0;
- b4const_0 = *valp;
- switch (b4const_0)
- {
- case 0xffffffff: r_0 = 0; break;
- case 0x1: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_0, r_0;
- r_0 = *valp & 0xf;
- b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
- *valp = b4constu_0;
- return 0;
-}
-
-static int
-Operand_b4constu_encode (uint32 *valp)
-{
- unsigned r_0, b4constu_0;
- b4constu_0 = *valp;
- switch (b4constu_0)
- {
- case 0x8000: r_0 = 0; break;
- case 0x10000: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8_0 = imm8_0;
- *valp = uimm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8_0;
- uimm8_0 = *valp;
- imm8_0 = (uimm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x2_0 = imm8_0 << 1;
- *valp = uimm8x2_0;
- return 0;
-}
-
-static int
-Operand_uimm8x2_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8x2_0;
- uimm8x2_0 = *valp;
- imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x4_0 = imm8_0 << 2;
- *valp = uimm8x4_0;
- return 0;
-}
-
-static int
-Operand_uimm8x4_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8x4_0;
- uimm8x4_0 = *valp;
- imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_0, op2_0;
- op2_0 = *valp & 0xf;
- uimm4x16_0 = op2_0 << 4;
- *valp = uimm4x16_0;
- return 0;
-}
-
-static int
-Operand_uimm4x16_encode (uint32 *valp)
-{
- unsigned op2_0, uimm4x16_0;
- uimm4x16_0 = *valp;
- op2_0 = ((uimm4x16_0 >> 4) & 0xf);
- *valp = op2_0;
- return 0;
-}
-
-static int
-Operand_simm8_decode (uint32 *valp)
-{
- unsigned simm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8_0 = ((int) imm8_0 << 24) >> 24;
- *valp = simm8_0;
- return 0;
-}
-
-static int
-Operand_simm8_encode (uint32 *valp)
-{
- unsigned imm8_0, simm8_0;
- simm8_0 = *valp;
- imm8_0 = (simm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
- *valp = simm8x256_0;
- return 0;
-}
-
-static int
-Operand_simm8x256_encode (uint32 *valp)
-{
- unsigned imm8_0, simm8x256_0;
- simm8x256_0 = *valp;
- imm8_0 = ((simm8x256_0 >> 8) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_0, imm12b_0;
- imm12b_0 = *valp & 0xfff;
- simm12b_0 = ((int) imm12b_0 << 20) >> 20;
- *valp = simm12b_0;
- return 0;
-}
-
-static int
-Operand_simm12b_encode (uint32 *valp)
-{
- unsigned imm12b_0, simm12b_0;
- simm12b_0 = *valp;
- imm12b_0 = (simm12b_0 & 0xfff);
- *valp = imm12b_0;
- return 0;
-}
-
-static int
-Operand_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_0, sal_0;
- sal_0 = *valp & 0x1f;
- msalp32_0 = 0x20 - sal_0;
- *valp = msalp32_0;
- return 0;
-}
-
-static int
-Operand_msalp32_encode (uint32 *valp)
-{
- unsigned sal_0, msalp32_0;
- msalp32_0 = *valp;
- sal_0 = (0x20 - msalp32_0) & 0x1f;
- *valp = sal_0;
- return 0;
-}
-
-static int
-Operand_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_0, op2_0;
- op2_0 = *valp & 0xf;
- op2p1_0 = op2_0 + 0x1;
- *valp = op2p1_0;
- return 0;
-}
-
-static int
-Operand_op2p1_encode (uint32 *valp)
-{
- unsigned op2_0, op2p1_0;
- op2p1_0 = *valp;
- op2_0 = (op2p1_0 - 0x1) & 0xf;
- *valp = op2_0;
- return 0;
-}
-
-static int
-Operand_label8_decode (uint32 *valp)
-{
- unsigned label8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
- *valp = label8_0;
- return 0;
-}
-
-static int
-Operand_label8_encode (uint32 *valp)
-{
- unsigned imm8_0, label8_0;
- label8_0 = *valp;
- imm8_0 = (label8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_decode (uint32 *valp)
-{
- unsigned ulabel8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
- *valp = ulabel8_0;
- return 0;
-}
-
-static int
-Operand_ulabel8_encode (uint32 *valp)
-{
- unsigned imm8_0, ulabel8_0;
- ulabel8_0 = *valp;
- imm8_0 = (ulabel8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_ulabel8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_decode (uint32 *valp)
-{
- unsigned label12_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
- *valp = label12_0;
- return 0;
-}
-
-static int
-Operand_label12_encode (uint32 *valp)
-{
- unsigned imm12_0, label12_0;
- label12_0 = *valp;
- imm12_0 = (label12_0 - 0x4) & 0xfff;
- *valp = imm12_0;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_decode (uint32 *valp)
-{
- unsigned soffset_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
- *valp = soffset_0;
- return 0;
-}
-
-static int
-Operand_soffset_encode (uint32 *valp)
-{
- unsigned offset_0, soffset_0;
- soffset_0 = *valp;
- offset_0 = (soffset_0 - 0x4) & 0x3ffff;
- *valp = offset_0;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_0, imm16_0;
- imm16_0 = *valp & 0xffff;
- uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
- *valp = uimm16x4_0;
- return 0;
-}
-
-static int
-Operand_uimm16x4_encode (uint32 *valp)
-{
- unsigned imm16_0, uimm16x4_0;
- uimm16x4_0 = *valp;
- imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
- *valp = imm16_0;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mx_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_my_decode (uint32 *valp)
-{
- *valp += 2;
- return 0;
-}
-
-static int
-Operand_my_encode (uint32 *valp)
-{
- int error;
- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
- *valp = *valp & 1;
- return error;
-}
-
-static int
-Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mw_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr0_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr1_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr2_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_mr3_encode (uint32 *valp)
-{
- return (*valp & ~0x3) != 0;
-}
-
-static int
-Operand_immt_decode (uint32 *valp)
-{
- unsigned immt_0, t_0;
- t_0 = *valp & 0xf;
- immt_0 = t_0;
- *valp = immt_0;
- return 0;
-}
-
-static int
-Operand_immt_encode (uint32 *valp)
-{
- unsigned t_0, immt_0;
- immt_0 = *valp;
- t_0 = immt_0 & 0xf;
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_imms_decode (uint32 *valp)
-{
- unsigned imms_0, s_0;
- s_0 = *valp & 0xf;
- imms_0 = s_0;
- *valp = imms_0;
- return 0;
-}
-
-static int
-Operand_imms_encode (uint32 *valp)
-{
- unsigned s_0, imms_0;
- imms_0 = *valp;
- s_0 = imms_0 & 0xf;
- *valp = s_0;
- return 0;
-}
-
-static int
-Operand_tp7_decode (uint32 *valp)
-{
- unsigned tp7_0, t_0;
- t_0 = *valp & 0xf;
- tp7_0 = t_0 + 0x7;
- *valp = tp7_0;
- return 0;
-}
-
-static int
-Operand_tp7_encode (uint32 *valp)
-{
- unsigned t_0, tp7_0;
- tp7_0 = *valp;
- t_0 = (tp7_0 - 0x7) & 0xf;
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_decode (uint32 *valp)
-{
- unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
- xt_wbr15_imm_0 = *valp & 0x7fff;
- xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
- *valp = xt_wbr15_label_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_encode (uint32 *valp)
-{
- unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
- xt_wbr15_label_0 = *valp;
- xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_imm_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_decode (uint32 *valp)
-{
- unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
- xt_wbr18_imm_0 = *valp & 0x3ffff;
- xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
- *valp = xt_wbr18_label_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_encode (uint32 *valp)
-{
- unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
- xt_wbr18_label_0 = *valp;
- xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
- *valp = xt_wbr18_imm_0;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffsetx4_encode, Operand_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", FIELD_imm12, -1, 0,
- 0,
- Operand_uimm12x8_encode, Operand_uimm12x8_decode,
- 0, 0 },
- { "simm4", FIELD_mn, -1, 0,
- 0,
- Operand_simm4_encode, Operand_simm4_decode,
- 0, 0 },
- { "arr", FIELD_r, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_arr_encode, Operand_arr_decode,
- 0, 0 },
- { "ars", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "art", FIELD_t, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_art_encode, Operand_art_decode,
- 0, 0 },
- { "ar0", FIELD__ar0, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar0_encode, Operand_ar0_decode,
- 0, 0 },
- { "ar4", FIELD__ar4, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar4_encode, Operand_ar4_decode,
- 0, 0 },
- { "ar8", FIELD__ar8, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar8_encode, Operand_ar8_decode,
- 0, 0 },
- { "ar12", FIELD__ar12, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar12_encode, Operand_ar12_decode,
- 0, 0 },
- { "ars_entry", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_entry_encode, Operand_ars_entry_decode,
- 0, 0 },
- { "immrx4", FIELD_r, -1, 0,
- 0,
- Operand_immrx4_encode, Operand_immrx4_decode,
- 0, 0 },
- { "lsi4x4", FIELD_r, -1, 0,
- 0,
- Operand_lsi4x4_encode, Operand_lsi4x4_decode,
- 0, 0 },
- { "simm7", FIELD_imm7, -1, 0,
- 0,
- Operand_simm7_encode, Operand_simm7_decode,
- 0, 0 },
- { "uimm6", FIELD_imm6, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm6_encode, Operand_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", FIELD_t, -1, 0,
- 0,
- Operand_ai4const_encode, Operand_ai4const_decode,
- 0, 0 },
- { "b4const", FIELD_r, -1, 0,
- 0,
- Operand_b4const_encode, Operand_b4const_decode,
- 0, 0 },
- { "b4constu", FIELD_r, -1, 0,
- 0,
- Operand_b4constu_encode, Operand_b4constu_decode,
- 0, 0 },
- { "uimm8", FIELD_imm8, -1, 0,
- 0,
- Operand_uimm8_encode, Operand_uimm8_decode,
- 0, 0 },
- { "uimm8x2", FIELD_imm8, -1, 0,
- 0,
- Operand_uimm8x2_encode, Operand_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", FIELD_imm8, -1, 0,
- 0,
- Operand_uimm8x4_encode, Operand_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", FIELD_op2, -1, 0,
- 0,
- Operand_uimm4x16_encode, Operand_uimm4x16_decode,
- 0, 0 },
- { "simm8", FIELD_imm8, -1, 0,
- 0,
- Operand_simm8_encode, Operand_simm8_decode,
- 0, 0 },
- { "simm8x256", FIELD_imm8, -1, 0,
- 0,
- Operand_simm8x256_encode, Operand_simm8x256_decode,
- 0, 0 },
- { "simm12b", FIELD_imm12b, -1, 0,
- 0,
- Operand_simm12b_encode, Operand_simm12b_decode,
- 0, 0 },
- { "msalp32", FIELD_sal, -1, 0,
- 0,
- Operand_msalp32_encode, Operand_msalp32_decode,
- 0, 0 },
- { "op2p1", FIELD_op2, -1, 0,
- 0,
- Operand_op2p1_encode, Operand_op2p1_decode,
- 0, 0 },
- { "label8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label8_encode, Operand_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_ulabel8_encode, Operand_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", FIELD_imm12, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label12_encode, Operand_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffset_encode, Operand_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", FIELD_imm16, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm16x4_encode, Operand_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "mx", FIELD_x, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- Operand_mx_encode, Operand_mx_decode,
- 0, 0 },
- { "my", FIELD_y, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- Operand_my_encode, Operand_my_decode,
- 0, 0 },
- { "mw", FIELD_w, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_mw_encode, Operand_mw_decode,
- 0, 0 },
- { "mr0", FIELD__mr0, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr0_encode, Operand_mr0_decode,
- 0, 0 },
- { "mr1", FIELD__mr1, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr1_encode, Operand_mr1_decode,
- 0, 0 },
- { "mr2", FIELD__mr2, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr2_encode, Operand_mr2_decode,
- 0, 0 },
- { "mr3", FIELD__mr3, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr3_encode, Operand_mr3_decode,
- 0, 0 },
- { "immt", FIELD_t, -1, 0,
- 0,
- Operand_immt_encode, Operand_immt_decode,
- 0, 0 },
- { "imms", FIELD_s, -1, 0,
- 0,
- Operand_imms_encode, Operand_imms_decode,
- 0, 0 },
- { "tp7", FIELD_t, -1, 0,
- 0,
- Operand_tp7_encode, Operand_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
- { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
- { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
- { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
- { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
- { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
- { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
- { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
- { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
- { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
- { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
- { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
- { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
- { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
- { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
- { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
- { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
- { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
- { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
- { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 },
- { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-enum xtensa_operand_id {
- OPERAND_soffsetx4,
- OPERAND_uimm12x8,
- OPERAND_simm4,
- OPERAND_arr,
- OPERAND_ars,
- OPERAND__ars_invisible,
- OPERAND_art,
- OPERAND_ar0,
- OPERAND_ar4,
- OPERAND_ar8,
- OPERAND_ar12,
- OPERAND_ars_entry,
- OPERAND_immrx4,
- OPERAND_lsi4x4,
- OPERAND_simm7,
- OPERAND_uimm6,
- OPERAND_ai4const,
- OPERAND_b4const,
- OPERAND_b4constu,
- OPERAND_uimm8,
- OPERAND_uimm8x2,
- OPERAND_uimm8x4,
- OPERAND_uimm4x16,
- OPERAND_simm8,
- OPERAND_simm8x256,
- OPERAND_simm12b,
- OPERAND_msalp32,
- OPERAND_op2p1,
- OPERAND_label8,
- OPERAND_ulabel8,
- OPERAND_label12,
- OPERAND_soffset,
- OPERAND_uimm16x4,
- OPERAND_mx,
- OPERAND_my,
- OPERAND_mw,
- OPERAND_mr0,
- OPERAND_mr1,
- OPERAND_mr2,
- OPERAND_mr3,
- OPERAND_immt,
- OPERAND_imms,
- OPERAND_tp7,
- OPERAND_xt_wbr15_label,
- OPERAND_xt_wbr18_label,
- OPERAND_t,
- OPERAND_bbi4,
- OPERAND_bbi,
- OPERAND_imm12,
- OPERAND_imm8,
- OPERAND_s,
- OPERAND_imm12b,
- OPERAND_imm16,
- OPERAND_m,
- OPERAND_n,
- OPERAND_offset,
- OPERAND_op0,
- OPERAND_op1,
- OPERAND_op2,
- OPERAND_r,
- OPERAND_sa4,
- OPERAND_sae4,
- OPERAND_sae,
- OPERAND_sal,
- OPERAND_sargt,
- OPERAND_sas4,
- OPERAND_sas,
- OPERAND_sr,
- OPERAND_st,
- OPERAND_thi3,
- OPERAND_imm4,
- OPERAND_mn,
- OPERAND_i,
- OPERAND_imm6lo,
- OPERAND_imm6hi,
- OPERAND_imm7lo,
- OPERAND_imm7hi,
- OPERAND_z,
- OPERAND_imm6,
- OPERAND_imm7,
- OPERAND_r3,
- OPERAND_rbit2,
- OPERAND_rhi,
- OPERAND_t3,
- OPERAND_tbit2,
- OPERAND_tlo,
- OPERAND_w,
- OPERAND_y,
- OPERAND_x,
- OPERAND_xt_wbr15_imm,
- OPERAND_xt_wbr18_imm,
- OPERAND_bitindex,
- OPERAND_s3to1
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSRING }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { OPERAND_ars_entry }, 's' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm12x8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { OPERAND_simm4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ai4const }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_simm7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8x256 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4const }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bbi }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4constu }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_label12 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sae }, 'i' },
- { { OPERAND_op2p1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { OPERAND_soffset }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_uimm16x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_simm12b }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { OPERAND_sas }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_msalp32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sargt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'o' },
- { { STATE_LITBEN }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'm' },
- { { STATE_LITBEN }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul16_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPC5 }, 'i' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_EPC7 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_EPS5 }, 'i' },
- { { STATE_EPS6 }, 'i' },
- { { STATE_EPS7 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { OPERAND_imms }, 'i' },
- { { OPERAND_immt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'm' },
- { { STATE_EXCVADDR }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'i' },
- { { STATE_ASID2 }, 'i' },
- { { STATE_ASID1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'o' },
- { { STATE_ASID2 }, 'o' },
- { { STATE_ASID1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'm' },
- { { STATE_ASID2 }, 'm' },
- { { STATE_ASID1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID6 }, 'i' },
- { { STATE_INSTPGSZID5 }, 'i' },
- { { STATE_INSTPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID6 }, 'o' },
- { { STATE_INSTPGSZID5 }, 'o' },
- { { STATE_INSTPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID6 }, 'm' },
- { { STATE_INSTPGSZID5 }, 'm' },
- { { STATE_INSTPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID6 }, 'i' },
- { { STATE_DATAPGSZID5 }, 'i' },
- { { STATE_DATAPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID6 }, 'o' },
- { { STATE_DATAPGSZID5 }, 'o' },
- { { STATE_DATAPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID6 }, 'm' },
- { { STATE_DATAPGSZID5 }, 'm' },
- { { STATE_DATAPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_XTSYNC }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
- INTERFACE_IMPWIRE
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_threadptr_args,
- 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
- { 1, Iclass_wur_threadptr_args,
- 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_176_args,
- 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_176_args,
- 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_208_args,
- 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc5_args,
- 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc5_args,
- 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc5_args,
- 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave5_args,
- 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave5_args,
- 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave5_args,
- 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc6_args,
- 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc6_args,
- 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc6_args,
- 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave6_args,
- 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave6_args,
- 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave6_args,
- 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc7_args,
- 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc7_args,
- 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc7_args,
- 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave7_args,
- 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave7_args,
- 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave7_args,
- 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps5_args,
- 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps5_args,
- 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps5_args,
- 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps6_args,
- 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps6_args,
- 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps6_args,
- 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps7_args,
- 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps7_args,
- 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps7_args,
- 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 3, Iclass_xt_mul16_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_aa_args,
- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_ad_args,
- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_da_args,
- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_dd_args,
- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_aa_args,
- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_ad_args,
- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_da_args,
- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_dd_args,
- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_da_args,
- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_dd_args,
- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_l_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m3_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acclo_args,
- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acclo_args,
- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acclo_args,
- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acchi_args,
- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acchi_args,
- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acchi_args,
- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_mmid_args,
- 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_lock_args,
- 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_lock_args,
- 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_rasid_args,
- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_rasid_args,
- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_rasid_args,
- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
- 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
- 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
- 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
- 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
- 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
- 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_ldpte */,
- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwitlba */,
- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwdtlba */,
- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_cpenable_args,
- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_cpenable_args,
- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_cpenable_args,
- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_clamp_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_atomctl_args,
- 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_atomctl_args,
- 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_atomctl_args,
- 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_div_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rer */,
- 2, Iclass_xt_iclass_rer_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_wer */,
- 2, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
- { 1, Iclass_rur_expstate_args,
- 2, Iclass_rur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_wur_expstate_args,
- 2, Iclass_wur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_iclass_READ_IMPWIRE_args,
- 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
- { 1, Iclass_iclass_SETB_EXPSTATE_args,
- 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
- { 1, Iclass_iclass_CLRB_EXPSTATE_args,
- 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
- { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
- 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
-};
-
-enum xtensa_iclass_id {
- ICLASS_xt_iclass_excw,
- ICLASS_xt_iclass_rfe,
- ICLASS_xt_iclass_rfde,
- ICLASS_xt_iclass_syscall,
- ICLASS_xt_iclass_simcall,
- ICLASS_xt_iclass_call12,
- ICLASS_xt_iclass_call8,
- ICLASS_xt_iclass_call4,
- ICLASS_xt_iclass_callx12,
- ICLASS_xt_iclass_callx8,
- ICLASS_xt_iclass_callx4,
- ICLASS_xt_iclass_entry,
- ICLASS_xt_iclass_movsp,
- ICLASS_xt_iclass_rotw,
- ICLASS_xt_iclass_retw,
- ICLASS_xt_iclass_rfwou,
- ICLASS_xt_iclass_l32e,
- ICLASS_xt_iclass_s32e,
- ICLASS_xt_iclass_rsr_windowbase,
- ICLASS_xt_iclass_wsr_windowbase,
- ICLASS_xt_iclass_xsr_windowbase,
- ICLASS_xt_iclass_rsr_windowstart,
- ICLASS_xt_iclass_wsr_windowstart,
- ICLASS_xt_iclass_xsr_windowstart,
- ICLASS_xt_iclass_add_n,
- ICLASS_xt_iclass_addi_n,
- ICLASS_xt_iclass_bz6,
- ICLASS_xt_iclass_ill_n,
- ICLASS_xt_iclass_loadi4,
- ICLASS_xt_iclass_mov_n,
- ICLASS_xt_iclass_movi_n,
- ICLASS_xt_iclass_nopn,
- ICLASS_xt_iclass_retn,
- ICLASS_xt_iclass_storei4,
- ICLASS_rur_threadptr,
- ICLASS_wur_threadptr,
- ICLASS_xt_iclass_addi,
- ICLASS_xt_iclass_addmi,
- ICLASS_xt_iclass_addsub,
- ICLASS_xt_iclass_bit,
- ICLASS_xt_iclass_bsi8,
- ICLASS_xt_iclass_bsi8b,
- ICLASS_xt_iclass_bsi8u,
- ICLASS_xt_iclass_bst8,
- ICLASS_xt_iclass_bsz12,
- ICLASS_xt_iclass_call0,
- ICLASS_xt_iclass_callx0,
- ICLASS_xt_iclass_exti,
- ICLASS_xt_iclass_ill,
- ICLASS_xt_iclass_jump,
- ICLASS_xt_iclass_jumpx,
- ICLASS_xt_iclass_l16ui,
- ICLASS_xt_iclass_l16si,
- ICLASS_xt_iclass_l32i,
- ICLASS_xt_iclass_l32r,
- ICLASS_xt_iclass_l8i,
- ICLASS_xt_iclass_loop,
- ICLASS_xt_iclass_loopz,
- ICLASS_xt_iclass_movi,
- ICLASS_xt_iclass_movz,
- ICLASS_xt_iclass_neg,
- ICLASS_xt_iclass_nop,
- ICLASS_xt_iclass_return,
- ICLASS_xt_iclass_s16i,
- ICLASS_xt_iclass_s32i,
- ICLASS_xt_iclass_s8i,
- ICLASS_xt_iclass_sar,
- ICLASS_xt_iclass_sari,
- ICLASS_xt_iclass_shifts,
- ICLASS_xt_iclass_shiftst,
- ICLASS_xt_iclass_shiftt,
- ICLASS_xt_iclass_slli,
- ICLASS_xt_iclass_srai,
- ICLASS_xt_iclass_srli,
- ICLASS_xt_iclass_memw,
- ICLASS_xt_iclass_extw,
- ICLASS_xt_iclass_isync,
- ICLASS_xt_iclass_sync,
- ICLASS_xt_iclass_rsil,
- ICLASS_xt_iclass_rsr_lend,
- ICLASS_xt_iclass_wsr_lend,
- ICLASS_xt_iclass_xsr_lend,
- ICLASS_xt_iclass_rsr_lcount,
- ICLASS_xt_iclass_wsr_lcount,
- ICLASS_xt_iclass_xsr_lcount,
- ICLASS_xt_iclass_rsr_lbeg,
- ICLASS_xt_iclass_wsr_lbeg,
- ICLASS_xt_iclass_xsr_lbeg,
- ICLASS_xt_iclass_rsr_sar,
- ICLASS_xt_iclass_wsr_sar,
- ICLASS_xt_iclass_xsr_sar,
- ICLASS_xt_iclass_rsr_litbase,
- ICLASS_xt_iclass_wsr_litbase,
- ICLASS_xt_iclass_xsr_litbase,
- ICLASS_xt_iclass_rsr_176,
- ICLASS_xt_iclass_wsr_176,
- ICLASS_xt_iclass_rsr_208,
- ICLASS_xt_iclass_rsr_ps,
- ICLASS_xt_iclass_wsr_ps,
- ICLASS_xt_iclass_xsr_ps,
- ICLASS_xt_iclass_rsr_epc1,
- ICLASS_xt_iclass_wsr_epc1,
- ICLASS_xt_iclass_xsr_epc1,
- ICLASS_xt_iclass_rsr_excsave1,
- ICLASS_xt_iclass_wsr_excsave1,
- ICLASS_xt_iclass_xsr_excsave1,
- ICLASS_xt_iclass_rsr_epc2,
- ICLASS_xt_iclass_wsr_epc2,
- ICLASS_xt_iclass_xsr_epc2,
- ICLASS_xt_iclass_rsr_excsave2,
- ICLASS_xt_iclass_wsr_excsave2,
- ICLASS_xt_iclass_xsr_excsave2,
- ICLASS_xt_iclass_rsr_epc3,
- ICLASS_xt_iclass_wsr_epc3,
- ICLASS_xt_iclass_xsr_epc3,
- ICLASS_xt_iclass_rsr_excsave3,
- ICLASS_xt_iclass_wsr_excsave3,
- ICLASS_xt_iclass_xsr_excsave3,
- ICLASS_xt_iclass_rsr_epc4,
- ICLASS_xt_iclass_wsr_epc4,
- ICLASS_xt_iclass_xsr_epc4,
- ICLASS_xt_iclass_rsr_excsave4,
- ICLASS_xt_iclass_wsr_excsave4,
- ICLASS_xt_iclass_xsr_excsave4,
- ICLASS_xt_iclass_rsr_epc5,
- ICLASS_xt_iclass_wsr_epc5,
- ICLASS_xt_iclass_xsr_epc5,
- ICLASS_xt_iclass_rsr_excsave5,
- ICLASS_xt_iclass_wsr_excsave5,
- ICLASS_xt_iclass_xsr_excsave5,
- ICLASS_xt_iclass_rsr_epc6,
- ICLASS_xt_iclass_wsr_epc6,
- ICLASS_xt_iclass_xsr_epc6,
- ICLASS_xt_iclass_rsr_excsave6,
- ICLASS_xt_iclass_wsr_excsave6,
- ICLASS_xt_iclass_xsr_excsave6,
- ICLASS_xt_iclass_rsr_epc7,
- ICLASS_xt_iclass_wsr_epc7,
- ICLASS_xt_iclass_xsr_epc7,
- ICLASS_xt_iclass_rsr_excsave7,
- ICLASS_xt_iclass_wsr_excsave7,
- ICLASS_xt_iclass_xsr_excsave7,
- ICLASS_xt_iclass_rsr_eps2,
- ICLASS_xt_iclass_wsr_eps2,
- ICLASS_xt_iclass_xsr_eps2,
- ICLASS_xt_iclass_rsr_eps3,
- ICLASS_xt_iclass_wsr_eps3,
- ICLASS_xt_iclass_xsr_eps3,
- ICLASS_xt_iclass_rsr_eps4,
- ICLASS_xt_iclass_wsr_eps4,
- ICLASS_xt_iclass_xsr_eps4,
- ICLASS_xt_iclass_rsr_eps5,
- ICLASS_xt_iclass_wsr_eps5,
- ICLASS_xt_iclass_xsr_eps5,
- ICLASS_xt_iclass_rsr_eps6,
- ICLASS_xt_iclass_wsr_eps6,
- ICLASS_xt_iclass_xsr_eps6,
- ICLASS_xt_iclass_rsr_eps7,
- ICLASS_xt_iclass_wsr_eps7,
- ICLASS_xt_iclass_xsr_eps7,
- ICLASS_xt_iclass_rsr_excvaddr,
- ICLASS_xt_iclass_wsr_excvaddr,
- ICLASS_xt_iclass_xsr_excvaddr,
- ICLASS_xt_iclass_rsr_depc,
- ICLASS_xt_iclass_wsr_depc,
- ICLASS_xt_iclass_xsr_depc,
- ICLASS_xt_iclass_rsr_exccause,
- ICLASS_xt_iclass_wsr_exccause,
- ICLASS_xt_iclass_xsr_exccause,
- ICLASS_xt_iclass_rsr_misc0,
- ICLASS_xt_iclass_wsr_misc0,
- ICLASS_xt_iclass_xsr_misc0,
- ICLASS_xt_iclass_rsr_misc1,
- ICLASS_xt_iclass_wsr_misc1,
- ICLASS_xt_iclass_xsr_misc1,
- ICLASS_xt_iclass_rsr_prid,
- ICLASS_xt_iclass_rsr_vecbase,
- ICLASS_xt_iclass_wsr_vecbase,
- ICLASS_xt_iclass_xsr_vecbase,
- ICLASS_xt_mul16,
- ICLASS_xt_mul32,
- ICLASS_xt_iclass_mac16_aa,
- ICLASS_xt_iclass_mac16_ad,
- ICLASS_xt_iclass_mac16_da,
- ICLASS_xt_iclass_mac16_dd,
- ICLASS_xt_iclass_mac16a_aa,
- ICLASS_xt_iclass_mac16a_ad,
- ICLASS_xt_iclass_mac16a_da,
- ICLASS_xt_iclass_mac16a_dd,
- ICLASS_xt_iclass_mac16al_da,
- ICLASS_xt_iclass_mac16al_dd,
- ICLASS_xt_iclass_mac16_l,
- ICLASS_xt_iclass_rsr_m0,
- ICLASS_xt_iclass_wsr_m0,
- ICLASS_xt_iclass_xsr_m0,
- ICLASS_xt_iclass_rsr_m1,
- ICLASS_xt_iclass_wsr_m1,
- ICLASS_xt_iclass_xsr_m1,
- ICLASS_xt_iclass_rsr_m2,
- ICLASS_xt_iclass_wsr_m2,
- ICLASS_xt_iclass_xsr_m2,
- ICLASS_xt_iclass_rsr_m3,
- ICLASS_xt_iclass_wsr_m3,
- ICLASS_xt_iclass_xsr_m3,
- ICLASS_xt_iclass_rsr_acclo,
- ICLASS_xt_iclass_wsr_acclo,
- ICLASS_xt_iclass_xsr_acclo,
- ICLASS_xt_iclass_rsr_acchi,
- ICLASS_xt_iclass_wsr_acchi,
- ICLASS_xt_iclass_xsr_acchi,
- ICLASS_xt_iclass_rfi,
- ICLASS_xt_iclass_wait,
- ICLASS_xt_iclass_rsr_interrupt,
- ICLASS_xt_iclass_wsr_intset,
- ICLASS_xt_iclass_wsr_intclear,
- ICLASS_xt_iclass_rsr_intenable,
- ICLASS_xt_iclass_wsr_intenable,
- ICLASS_xt_iclass_xsr_intenable,
- ICLASS_xt_iclass_break,
- ICLASS_xt_iclass_break_n,
- ICLASS_xt_iclass_rsr_dbreaka0,
- ICLASS_xt_iclass_wsr_dbreaka0,
- ICLASS_xt_iclass_xsr_dbreaka0,
- ICLASS_xt_iclass_rsr_dbreakc0,
- ICLASS_xt_iclass_wsr_dbreakc0,
- ICLASS_xt_iclass_xsr_dbreakc0,
- ICLASS_xt_iclass_rsr_dbreaka1,
- ICLASS_xt_iclass_wsr_dbreaka1,
- ICLASS_xt_iclass_xsr_dbreaka1,
- ICLASS_xt_iclass_rsr_dbreakc1,
- ICLASS_xt_iclass_wsr_dbreakc1,
- ICLASS_xt_iclass_xsr_dbreakc1,
- ICLASS_xt_iclass_rsr_ibreaka0,
- ICLASS_xt_iclass_wsr_ibreaka0,
- ICLASS_xt_iclass_xsr_ibreaka0,
- ICLASS_xt_iclass_rsr_ibreaka1,
- ICLASS_xt_iclass_wsr_ibreaka1,
- ICLASS_xt_iclass_xsr_ibreaka1,
- ICLASS_xt_iclass_rsr_ibreakenable,
- ICLASS_xt_iclass_wsr_ibreakenable,
- ICLASS_xt_iclass_xsr_ibreakenable,
- ICLASS_xt_iclass_rsr_debugcause,
- ICLASS_xt_iclass_wsr_debugcause,
- ICLASS_xt_iclass_xsr_debugcause,
- ICLASS_xt_iclass_rsr_icount,
- ICLASS_xt_iclass_wsr_icount,
- ICLASS_xt_iclass_xsr_icount,
- ICLASS_xt_iclass_rsr_icountlevel,
- ICLASS_xt_iclass_wsr_icountlevel,
- ICLASS_xt_iclass_xsr_icountlevel,
- ICLASS_xt_iclass_rsr_ddr,
- ICLASS_xt_iclass_wsr_ddr,
- ICLASS_xt_iclass_xsr_ddr,
- ICLASS_xt_iclass_rfdo,
- ICLASS_xt_iclass_rfdd,
- ICLASS_xt_iclass_wsr_mmid,
- ICLASS_xt_iclass_rsr_ccount,
- ICLASS_xt_iclass_wsr_ccount,
- ICLASS_xt_iclass_xsr_ccount,
- ICLASS_xt_iclass_rsr_ccompare0,
- ICLASS_xt_iclass_wsr_ccompare0,
- ICLASS_xt_iclass_xsr_ccompare0,
- ICLASS_xt_iclass_rsr_ccompare1,
- ICLASS_xt_iclass_wsr_ccompare1,
- ICLASS_xt_iclass_xsr_ccompare1,
- ICLASS_xt_iclass_rsr_ccompare2,
- ICLASS_xt_iclass_wsr_ccompare2,
- ICLASS_xt_iclass_xsr_ccompare2,
- ICLASS_xt_iclass_icache,
- ICLASS_xt_iclass_icache_lock,
- ICLASS_xt_iclass_icache_inv,
- ICLASS_xt_iclass_licx,
- ICLASS_xt_iclass_sicx,
- ICLASS_xt_iclass_dcache,
- ICLASS_xt_iclass_dcache_ind,
- ICLASS_xt_iclass_dcache_inv,
- ICLASS_xt_iclass_dpf,
- ICLASS_xt_iclass_dcache_lock,
- ICLASS_xt_iclass_sdct,
- ICLASS_xt_iclass_ldct,
- ICLASS_xt_iclass_wsr_ptevaddr,
- ICLASS_xt_iclass_rsr_ptevaddr,
- ICLASS_xt_iclass_xsr_ptevaddr,
- ICLASS_xt_iclass_rsr_rasid,
- ICLASS_xt_iclass_wsr_rasid,
- ICLASS_xt_iclass_xsr_rasid,
- ICLASS_xt_iclass_rsr_itlbcfg,
- ICLASS_xt_iclass_wsr_itlbcfg,
- ICLASS_xt_iclass_xsr_itlbcfg,
- ICLASS_xt_iclass_rsr_dtlbcfg,
- ICLASS_xt_iclass_wsr_dtlbcfg,
- ICLASS_xt_iclass_xsr_dtlbcfg,
- ICLASS_xt_iclass_idtlb,
- ICLASS_xt_iclass_rdtlb,
- ICLASS_xt_iclass_wdtlb,
- ICLASS_xt_iclass_iitlb,
- ICLASS_xt_iclass_ritlb,
- ICLASS_xt_iclass_witlb,
- ICLASS_xt_iclass_ldpte,
- ICLASS_xt_iclass_hwwitlba,
- ICLASS_xt_iclass_hwwdtlba,
- ICLASS_xt_iclass_rsr_cpenable,
- ICLASS_xt_iclass_wsr_cpenable,
- ICLASS_xt_iclass_xsr_cpenable,
- ICLASS_xt_iclass_clamp,
- ICLASS_xt_iclass_minmax,
- ICLASS_xt_iclass_nsa,
- ICLASS_xt_iclass_sx,
- ICLASS_xt_iclass_l32ai,
- ICLASS_xt_iclass_s32ri,
- ICLASS_xt_iclass_s32c1i,
- ICLASS_xt_iclass_rsr_scompare1,
- ICLASS_xt_iclass_wsr_scompare1,
- ICLASS_xt_iclass_xsr_scompare1,
- ICLASS_xt_iclass_rsr_atomctl,
- ICLASS_xt_iclass_wsr_atomctl,
- ICLASS_xt_iclass_xsr_atomctl,
- ICLASS_xt_iclass_div,
- ICLASS_xt_iclass_rer,
- ICLASS_xt_iclass_wer,
- ICLASS_rur_expstate,
- ICLASS_wur_expstate,
- ICLASS_iclass_READ_IMPWIRE,
- ICLASS_iclass_SETB_EXPSTATE,
- ICLASS_iclass_CLRB_EXPSTATE,
- ICLASS_iclass_WRMSK_EXPSTATE
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2080;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3200;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5000;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5100;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x25;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1000;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x408000;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01d;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3400;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3500;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90000;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490000;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34800;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134800;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614800;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34900;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134900;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614900;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf06d;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03d;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00d;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e70;
-}
-
-static void
-Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e700;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc002;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd002;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800000;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc00000;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900000;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00000;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00000;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00000;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00000;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00000;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300000;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x26;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x66;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe6;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa6;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6007;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe007;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf6;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb6;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1007;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9007;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa007;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2007;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb007;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3007;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8007;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4007;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc007;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5007;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd007;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x56;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd6;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x96;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1002;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9002;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2002;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8076;
-}
-
-static void
-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9076;
-}
-
-static void
-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa076;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa002;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x830000;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x930000;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa30000;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb30000;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600100;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20f0;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5002;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6002;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4002;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400000;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x401000;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x402000;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x403000;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404000;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa10000;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x810000;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x910000;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb10000;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10000;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210000;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410000;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c0;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20d0;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2010;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2020;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2030;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000;
-}
-
-static void
-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30100;
-}
-
-static void
-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130100;
-}
-
-static void
-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610100;
-}
-
-static void
-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30200;
-}
-
-static void
-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130200;
-}
-
-static void
-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610200;
-}
-
-static void
-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130000;
-}
-
-static void
-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610000;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30300;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130300;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610300;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30500;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130500;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610500;
-}
-
-static void
-Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b000;
-}
-
-static void
-Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b000;
-}
-
-static void
-Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d000;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e600;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e600;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e600;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b100;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b100;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b100;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d100;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d100;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d100;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b200;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b200;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b200;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d200;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d200;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d200;
-}
-
-static void
-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b300;
-}
-
-static void
-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b300;
-}
-
-static void
-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b300;
-}
-
-static void
-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d300;
-}
-
-static void
-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d300;
-}
-
-static void
-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d300;
-}
-
-static void
-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b400;
-}
-
-static void
-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b400;
-}
-
-static void
-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b400;
-}
-
-static void
-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d400;
-}
-
-static void
-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d400;
-}
-
-static void
-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d400;
-}
-
-static void
-Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b500;
-}
-
-static void
-Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b500;
-}
-
-static void
-Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b500;
-}
-
-static void
-Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d500;
-}
-
-static void
-Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d500;
-}
-
-static void
-Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d500;
-}
-
-static void
-Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b600;
-}
-
-static void
-Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b600;
-}
-
-static void
-Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b600;
-}
-
-static void
-Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d600;
-}
-
-static void
-Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d600;
-}
-
-static void
-Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d600;
-}
-
-static void
-Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b700;
-}
-
-static void
-Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b700;
-}
-
-static void
-Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b700;
-}
-
-static void
-Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d700;
-}
-
-static void
-Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d700;
-}
-
-static void
-Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d700;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c200;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c200;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c200;
-}
-
-static void
-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c300;
-}
-
-static void
-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c300;
-}
-
-static void
-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c300;
-}
-
-static void
-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c400;
-}
-
-static void
-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c400;
-}
-
-static void
-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c400;
-}
-
-static void
-Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c500;
-}
-
-static void
-Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c500;
-}
-
-static void
-Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c500;
-}
-
-static void
-Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c600;
-}
-
-static void
-Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c600;
-}
-
-static void
-Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c600;
-}
-
-static void
-Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c700;
-}
-
-static void
-Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c700;
-}
-
-static void
-Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c700;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ee00;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ee00;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ee00;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c000;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c000;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c000;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e800;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e800;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e800;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f400;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f400;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f400;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f500;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f500;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f500;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3eb00;
-}
-
-static void
-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e700;
-}
-
-static void
-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e700;
-}
-
-static void
-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e700;
-}
-
-static void
-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc10000;
-}
-
-static void
-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10000;
-}
-
-static void
-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x820000;
-}
-
-static void
-Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x740004;
-}
-
-static void
-Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x750004;
-}
-
-static void
-Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x760004;
-}
-
-static void
-Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x770004;
-}
-
-static void
-Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700004;
-}
-
-static void
-Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x710004;
-}
-
-static void
-Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x720004;
-}
-
-static void
-Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730004;
-}
-
-static void
-Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x340004;
-}
-
-static void
-Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x350004;
-}
-
-static void
-Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x360004;
-}
-
-static void
-Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x370004;
-}
-
-static void
-Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x640004;
-}
-
-static void
-Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x650004;
-}
-
-static void
-Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x660004;
-}
-
-static void
-Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x670004;
-}
-
-static void
-Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x240004;
-}
-
-static void
-Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x250004;
-}
-
-static void
-Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x260004;
-}
-
-static void
-Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270004;
-}
-
-static void
-Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780004;
-}
-
-static void
-Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x790004;
-}
-
-static void
-Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7a0004;
-}
-
-static void
-Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7b0004;
-}
-
-static void
-Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7c0004;
-}
-
-static void
-Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7d0004;
-}
-
-static void
-Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7e0004;
-}
-
-static void
-Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7f0004;
-}
-
-static void
-Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380004;
-}
-
-static void
-Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x390004;
-}
-
-static void
-Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a0004;
-}
-
-static void
-Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b0004;
-}
-
-static void
-Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c0004;
-}
-
-static void
-Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d0004;
-}
-
-static void
-Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e0004;
-}
-
-static void
-Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f0004;
-}
-
-static void
-Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680004;
-}
-
-static void
-Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x690004;
-}
-
-static void
-Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6a0004;
-}
-
-static void
-Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6b0004;
-}
-
-static void
-Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6c0004;
-}
-
-static void
-Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0004;
-}
-
-static void
-Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6e0004;
-}
-
-static void
-Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f0004;
-}
-
-static void
-Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280004;
-}
-
-static void
-Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x290004;
-}
-
-static void
-Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2a0004;
-}
-
-static void
-Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2b0004;
-}
-
-static void
-Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2c0004;
-}
-
-static void
-Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d0004;
-}
-
-static void
-Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e0004;
-}
-
-static void
-Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f0004;
-}
-
-static void
-Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580004;
-}
-
-static void
-Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480004;
-}
-
-static void
-Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x590004;
-}
-
-static void
-Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490004;
-}
-
-static void
-Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a0004;
-}
-
-static void
-Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4a0004;
-}
-
-static void
-Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b0004;
-}
-
-static void
-Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4b0004;
-}
-
-static void
-Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180004;
-}
-
-static void
-Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80004;
-}
-
-static void
-Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x190004;
-}
-
-static void
-Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90004;
-}
-
-static void
-Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1a0004;
-}
-
-static void
-Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0004;
-}
-
-static void
-Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b0004;
-}
-
-static void
-Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb0004;
-}
-
-static void
-Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900004;
-}
-
-static void
-Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800004;
-}
-
-static void
-Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32000;
-}
-
-static void
-Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132000;
-}
-
-static void
-Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612000;
-}
-
-static void
-Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32100;
-}
-
-static void
-Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132100;
-}
-
-static void
-Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612100;
-}
-
-static void
-Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32200;
-}
-
-static void
-Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132200;
-}
-
-static void
-Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612200;
-}
-
-static void
-Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32300;
-}
-
-static void
-Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132300;
-}
-
-static void
-Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612300;
-}
-
-static void
-Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31000;
-}
-
-static void
-Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131000;
-}
-
-static void
-Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x611000;
-}
-
-static void
-Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31100;
-}
-
-static void
-Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131100;
-}
-
-static void
-Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x611100;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3010;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7000;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e200;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e200;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e300;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e400;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e400;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e400;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf02d;
-}
-
-static void
-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39000;
-}
-
-static void
-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139000;
-}
-
-static void
-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619000;
-}
-
-static void
-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a000;
-}
-
-static void
-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a000;
-}
-
-static void
-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a000;
-}
-
-static void
-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39100;
-}
-
-static void
-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139100;
-}
-
-static void
-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619100;
-}
-
-static void
-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a100;
-}
-
-static void
-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a100;
-}
-
-static void
-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a100;
-}
-
-static void
-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38000;
-}
-
-static void
-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138000;
-}
-
-static void
-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618000;
-}
-
-static void
-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38100;
-}
-
-static void
-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138100;
-}
-
-static void
-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618100;
-}
-
-static void
-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36000;
-}
-
-static void
-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136000;
-}
-
-static void
-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616000;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e900;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e900;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e900;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ec00;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ec00;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ec00;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ed00;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ed00;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ed00;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36800;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136800;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616800;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e000;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e010;
-}
-
-static void
-Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135900;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ea00;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ea00;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ea00;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f000;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f000;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f000;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f100;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f100;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f100;
-}
-
-static void
-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f200;
-}
-
-static void
-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f200;
-}
-
-static void
-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f200;
-}
-
-static void
-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70c2;
-}
-
-static void
-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70e2;
-}
-
-static void
-Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70d2;
-}
-
-static void
-Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270d2;
-}
-
-static void
-Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x370d2;
-}
-
-static void
-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70f2;
-}
-
-static void
-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf10000;
-}
-
-static void
-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf12000;
-}
-
-static void
-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf11000;
-}
-
-static void
-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf13000;
-}
-
-static void
-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7042;
-}
-
-static void
-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7052;
-}
-
-static void
-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x47082;
-}
-
-static void
-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x57082;
-}
-
-static void
-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7062;
-}
-
-static void
-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7072;
-}
-
-static void
-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7002;
-}
-
-static void
-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7012;
-}
-
-static void
-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7022;
-}
-
-static void
-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7032;
-}
-
-static void
-Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7082;
-}
-
-static void
-Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x27082;
-}
-
-static void
-Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x37082;
-}
-
-static void
-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf19000;
-}
-
-static void
-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf18000;
-}
-
-static void
-Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135300;
-}
-
-static void
-Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35300;
-}
-
-static void
-Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615300;
-}
-
-static void
-Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35a00;
-}
-
-static void
-Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135a00;
-}
-
-static void
-Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615a00;
-}
-
-static void
-Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35b00;
-}
-
-static void
-Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135b00;
-}
-
-static void
-Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615b00;
-}
-
-static void
-Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35c00;
-}
-
-static void
-Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135c00;
-}
-
-static void
-Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615c00;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50c000;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50d000;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50b000;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50f000;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50e000;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x504000;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505000;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x503000;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x507000;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x506000;
-}
-
-static void
-Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1f000;
-}
-
-static void
-Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x501000;
-}
-
-static void
-Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x509000;
-}
-
-static void
-Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e000;
-}
-
-static void
-Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e000;
-}
-
-static void
-Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e000;
-}
-
-static void
-Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x330000;
-}
-
-static void
-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x430000;
-}
-
-static void
-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530000;
-}
-
-static void
-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x630000;
-}
-
-static void
-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730000;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40e000;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40f000;
-}
-
-static void
-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230000;
-}
-
-static void
-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb002;
-}
-
-static void
-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf002;
-}
-
-static void
-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe002;
-}
-
-static void
-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30c00;
-}
-
-static void
-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130c00;
-}
-
-static void
-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610c00;
-}
-
-static void
-Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36300;
-}
-
-static void
-Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136300;
-}
-
-static void
-Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616300;
-}
-
-static void
-Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc20000;
-}
-
-static void
-Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd20000;
-}
-
-static void
-Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe20000;
-}
-
-static void
-Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf20000;
-}
-
-static void
-Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x406000;
-}
-
-static void
-Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x407000;
-}
-
-static void
-Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e60;
-}
-
-static void
-Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e600;
-}
-
-static void
-Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0000;
-}
-
-static void
-Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1000;
-}
-
-static void
-Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1200;
-}
-
-static void
-Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe2000;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
- Opcode_rur_threadptr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
- Opcode_wur_threadptr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
- Opcode_rsr_176_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
- Opcode_wsr_176_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
- Opcode_rsr_208_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
- Opcode_rsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
- Opcode_wsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
- Opcode_xsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
- Opcode_rsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
- Opcode_wsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
- Opcode_xsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
- Opcode_rsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
- Opcode_wsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
- Opcode_xsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
- Opcode_rsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
- Opcode_wsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
- Opcode_xsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
- Opcode_rsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
- Opcode_wsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
- Opcode_xsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
- Opcode_rsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
- Opcode_wsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
- Opcode_xsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
- Opcode_mul_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
- Opcode_mul_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
- Opcode_mul_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
- Opcode_mul_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
- Opcode_mula_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
- Opcode_mula_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
- Opcode_mula_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
- Opcode_mula_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
- Opcode_muls_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
- Opcode_muls_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
- Opcode_muls_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
- Opcode_muls_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
- Opcode_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
- Opcode_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
- Opcode_rsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
- Opcode_wsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
- Opcode_xsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
- Opcode_rsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
- Opcode_wsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
- Opcode_xsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
- Opcode_rsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
- Opcode_wsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
- Opcode_xsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
- Opcode_rsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
- Opcode_wsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
- Opcode_xsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
- Opcode_rsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
- Opcode_wsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
- Opcode_xsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
- Opcode_rsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
- Opcode_wsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
- Opcode_xsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
- Opcode_wsr_mmid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
- Opcode_ipfl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
- Opcode_ihu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
- Opcode_iiu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
- Opcode_dpfl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
- Opcode_dhu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
- Opcode_diu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
- Opcode_rsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
- Opcode_wsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
- Opcode_xsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
- Opcode_ldpte_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
- Opcode_hwwitlba_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
- Opcode_hwwdtlba_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
- Opcode_clamps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
- Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
- Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
- Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
- Opcode_quou_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
- Opcode_quos_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
- Opcode_remu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
- Opcode_rems_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
- Opcode_rer_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
- Opcode_wer_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
- Opcode_rur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
- Opcode_wur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
- Opcode_read_impwire_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
- Opcode_setb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
- Opcode_clrb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
- Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
-};
-
-\f
-/* Opcode table. */
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", ICLASS_xt_iclass_excw,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", ICLASS_xt_iclass_rfe,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", ICLASS_xt_iclass_rfde,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", ICLASS_xt_iclass_syscall,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "simcall", ICLASS_xt_iclass_simcall,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "call12", ICLASS_xt_iclass_call12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", ICLASS_xt_iclass_call8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", ICLASS_xt_iclass_call4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", ICLASS_xt_iclass_callx12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", ICLASS_xt_iclass_callx8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", ICLASS_xt_iclass_callx4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", ICLASS_xt_iclass_entry,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", ICLASS_xt_iclass_movsp,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", ICLASS_xt_iclass_rotw,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", ICLASS_xt_iclass_l32e,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", ICLASS_xt_iclass_s32e,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", ICLASS_xt_iclass_add_n,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", ICLASS_xt_iclass_addi_n,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", ICLASS_xt_iclass_ill_n,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", ICLASS_xt_iclass_loadi4,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", ICLASS_xt_iclass_mov_n,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", ICLASS_xt_iclass_movi_n,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", ICLASS_xt_iclass_nopn,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", ICLASS_xt_iclass_retn,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", ICLASS_xt_iclass_storei4,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "rur.threadptr", ICLASS_rur_threadptr,
- 0,
- Opcode_rur_threadptr_encode_fns, 0, 0 },
- { "wur.threadptr", ICLASS_wur_threadptr,
- 0,
- Opcode_wur_threadptr_encode_fns, 0, 0 },
- { "addi", ICLASS_xt_iclass_addi,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", ICLASS_xt_iclass_addmi,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", ICLASS_xt_iclass_bit,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", ICLASS_xt_iclass_bit,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", ICLASS_xt_iclass_bit,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", ICLASS_xt_iclass_call0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", ICLASS_xt_iclass_callx0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", ICLASS_xt_iclass_exti,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", ICLASS_xt_iclass_ill,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", ICLASS_xt_iclass_jump,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", ICLASS_xt_iclass_jumpx,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", ICLASS_xt_iclass_l16ui,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", ICLASS_xt_iclass_l16si,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", ICLASS_xt_iclass_l32i,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", ICLASS_xt_iclass_l32r,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", ICLASS_xt_iclass_l8i,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", ICLASS_xt_iclass_loop,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", ICLASS_xt_iclass_movi,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", ICLASS_xt_iclass_neg,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", ICLASS_xt_iclass_neg,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", ICLASS_xt_iclass_nop,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", ICLASS_xt_iclass_return,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "s16i", ICLASS_xt_iclass_s16i,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", ICLASS_xt_iclass_s32i,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s8i", ICLASS_xt_iclass_s8i,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", ICLASS_xt_iclass_sari,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", ICLASS_xt_iclass_shifts,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", ICLASS_xt_iclass_shiftst,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", ICLASS_xt_iclass_slli,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", ICLASS_xt_iclass_srai,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", ICLASS_xt_iclass_srli,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", ICLASS_xt_iclass_memw,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", ICLASS_xt_iclass_extw,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", ICLASS_xt_iclass_isync,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", ICLASS_xt_iclass_rsil,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.176", ICLASS_xt_iclass_rsr_176,
- 0,
- Opcode_rsr_176_encode_fns, 0, 0 },
- { "wsr.176", ICLASS_xt_iclass_wsr_176,
- 0,
- Opcode_wsr_176_encode_fns, 0, 0 },
- { "rsr.208", ICLASS_xt_iclass_rsr_208,
- 0,
- Opcode_rsr_208_encode_fns, 0, 0 },
- { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
- 0,
- Opcode_rsr_epc5_encode_fns, 0, 0 },
- { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
- 0,
- Opcode_wsr_epc5_encode_fns, 0, 0 },
- { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
- 0,
- Opcode_xsr_epc5_encode_fns, 0, 0 },
- { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
- 0,
- Opcode_rsr_excsave5_encode_fns, 0, 0 },
- { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
- 0,
- Opcode_wsr_excsave5_encode_fns, 0, 0 },
- { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
- 0,
- Opcode_xsr_excsave5_encode_fns, 0, 0 },
- { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
- 0,
- Opcode_rsr_epc6_encode_fns, 0, 0 },
- { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
- 0,
- Opcode_wsr_epc6_encode_fns, 0, 0 },
- { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
- 0,
- Opcode_xsr_epc6_encode_fns, 0, 0 },
- { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
- 0,
- Opcode_rsr_excsave6_encode_fns, 0, 0 },
- { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
- 0,
- Opcode_wsr_excsave6_encode_fns, 0, 0 },
- { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
- 0,
- Opcode_xsr_excsave6_encode_fns, 0, 0 },
- { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
- 0,
- Opcode_rsr_epc7_encode_fns, 0, 0 },
- { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
- 0,
- Opcode_wsr_epc7_encode_fns, 0, 0 },
- { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
- 0,
- Opcode_xsr_epc7_encode_fns, 0, 0 },
- { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
- 0,
- Opcode_rsr_excsave7_encode_fns, 0, 0 },
- { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
- 0,
- Opcode_wsr_excsave7_encode_fns, 0, 0 },
- { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
- 0,
- Opcode_xsr_excsave7_encode_fns, 0, 0 },
- { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
- 0,
- Opcode_rsr_eps5_encode_fns, 0, 0 },
- { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
- 0,
- Opcode_wsr_eps5_encode_fns, 0, 0 },
- { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
- 0,
- Opcode_xsr_eps5_encode_fns, 0, 0 },
- { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
- 0,
- Opcode_rsr_eps6_encode_fns, 0, 0 },
- { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
- 0,
- Opcode_wsr_eps6_encode_fns, 0, 0 },
- { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
- 0,
- Opcode_xsr_eps6_encode_fns, 0, 0 },
- { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
- 0,
- Opcode_rsr_eps7_encode_fns, 0, 0 },
- { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
- 0,
- Opcode_wsr_eps7_encode_fns, 0, 0 },
- { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
- 0,
- Opcode_xsr_eps7_encode_fns, 0, 0 },
- { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "mul16u", ICLASS_xt_mul16,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", ICLASS_xt_mul16,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "mull", ICLASS_xt_mul32,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_ll_encode_fns, 0, 0 },
- { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_hl_encode_fns, 0, 0 },
- { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_lh_encode_fns, 0, 0 },
- { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_hh_encode_fns, 0, 0 },
- { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_ll_encode_fns, 0, 0 },
- { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_hl_encode_fns, 0, 0 },
- { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_lh_encode_fns, 0, 0 },
- { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_hh_encode_fns, 0, 0 },
- { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_ll_encode_fns, 0, 0 },
- { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_hl_encode_fns, 0, 0 },
- { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_lh_encode_fns, 0, 0 },
- { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_hh_encode_fns, 0, 0 },
- { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_ll_encode_fns, 0, 0 },
- { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_hl_encode_fns, 0, 0 },
- { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_lh_encode_fns, 0, 0 },
- { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_hh_encode_fns, 0, 0 },
- { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_ll_encode_fns, 0, 0 },
- { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_hl_encode_fns, 0, 0 },
- { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_lh_encode_fns, 0, 0 },
- { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_hh_encode_fns, 0, 0 },
- { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_ll_encode_fns, 0, 0 },
- { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_hl_encode_fns, 0, 0 },
- { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_lh_encode_fns, 0, 0 },
- { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_hh_encode_fns, 0, 0 },
- { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_ll_encode_fns, 0, 0 },
- { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_hl_encode_fns, 0, 0 },
- { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_lh_encode_fns, 0, 0 },
- { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_hh_encode_fns, 0, 0 },
- { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_ll_encode_fns, 0, 0 },
- { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_hl_encode_fns, 0, 0 },
- { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_lh_encode_fns, 0, 0 },
- { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_hh_encode_fns, 0, 0 },
- { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_ll_encode_fns, 0, 0 },
- { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_hl_encode_fns, 0, 0 },
- { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_lh_encode_fns, 0, 0 },
- { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_hh_encode_fns, 0, 0 },
- { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_ll_encode_fns, 0, 0 },
- { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_hl_encode_fns, 0, 0 },
- { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_lh_encode_fns, 0, 0 },
- { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_hh_encode_fns, 0, 0 },
- { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_ll_encode_fns, 0, 0 },
- { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_hl_encode_fns, 0, 0 },
- { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_lh_encode_fns, 0, 0 },
- { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_hh_encode_fns, 0, 0 },
- { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_ll_encode_fns, 0, 0 },
- { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_hl_encode_fns, 0, 0 },
- { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_lh_encode_fns, 0, 0 },
- { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_hh_encode_fns, 0, 0 },
- { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_ll_encode_fns, 0, 0 },
- { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_hl_encode_fns, 0, 0 },
- { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_lh_encode_fns, 0, 0 },
- { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_hh_encode_fns, 0, 0 },
- { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
- { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
- { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
- { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
- { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
- { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
- { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
- { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
- { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
- { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
- { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
- { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
- { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
- { "lddec", ICLASS_xt_iclass_mac16_l,
- 0,
- Opcode_lddec_encode_fns, 0, 0 },
- { "ldinc", ICLASS_xt_iclass_mac16_l,
- 0,
- Opcode_ldinc_encode_fns, 0, 0 },
- { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
- 0,
- Opcode_rsr_m0_encode_fns, 0, 0 },
- { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
- 0,
- Opcode_wsr_m0_encode_fns, 0, 0 },
- { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
- 0,
- Opcode_xsr_m0_encode_fns, 0, 0 },
- { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
- 0,
- Opcode_rsr_m1_encode_fns, 0, 0 },
- { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
- 0,
- Opcode_wsr_m1_encode_fns, 0, 0 },
- { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
- 0,
- Opcode_xsr_m1_encode_fns, 0, 0 },
- { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
- 0,
- Opcode_rsr_m2_encode_fns, 0, 0 },
- { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
- 0,
- Opcode_wsr_m2_encode_fns, 0, 0 },
- { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
- 0,
- Opcode_xsr_m2_encode_fns, 0, 0 },
- { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
- 0,
- Opcode_rsr_m3_encode_fns, 0, 0 },
- { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
- 0,
- Opcode_wsr_m3_encode_fns, 0, 0 },
- { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
- 0,
- Opcode_xsr_m3_encode_fns, 0, 0 },
- { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
- 0,
- Opcode_rsr_acclo_encode_fns, 0, 0 },
- { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
- 0,
- Opcode_wsr_acclo_encode_fns, 0, 0 },
- { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
- 0,
- Opcode_xsr_acclo_encode_fns, 0, 0 },
- { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
- 0,
- Opcode_rsr_acchi_encode_fns, 0, 0 },
- { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
- 0,
- Opcode_wsr_acchi_encode_fns, 0, 0 },
- { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
- 0,
- Opcode_xsr_acchi_encode_fns, 0, 0 },
- { "rfi", ICLASS_xt_iclass_rfi,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", ICLASS_xt_iclass_wait,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", ICLASS_xt_iclass_break,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", ICLASS_xt_iclass_break_n,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "rfdo", ICLASS_xt_iclass_rfdo,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", ICLASS_xt_iclass_rfdd,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
- 0,
- Opcode_wsr_mmid_encode_fns, 0, 0 },
- { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "ipf", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "ipfl", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_ipfl_encode_fns, 0, 0 },
- { "ihu", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_ihu_encode_fns, 0, 0 },
- { "iiu", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_iiu_encode_fns, 0, 0 },
- { "iii", ICLASS_xt_iclass_icache_inv,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", ICLASS_xt_iclass_licx,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", ICLASS_xt_iclass_licx,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwb", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "dpfl", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_dpfl_encode_fns, 0, 0 },
- { "dhu", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_dhu_encode_fns, 0, 0 },
- { "diu", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_diu_encode_fns, 0, 0 },
- { "sdct", ICLASS_xt_iclass_sdct,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", ICLASS_xt_iclass_ldct,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
- 0,
- Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
- 0,
- Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
- { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
- 0,
- Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
- 0,
- Opcode_rsr_rasid_encode_fns, 0, 0 },
- { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
- 0,
- Opcode_wsr_rasid_encode_fns, 0, 0 },
- { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
- 0,
- Opcode_xsr_rasid_encode_fns, 0, 0 },
- { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
- 0,
- Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
- { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
- 0,
- Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
- { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
- 0,
- Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
- { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
- 0,
- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
- { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
- 0,
- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
- { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
- 0,
- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
- { "idtlb", ICLASS_xt_iclass_idtlb,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", ICLASS_xt_iclass_wdtlb,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", ICLASS_xt_iclass_iitlb,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", ICLASS_xt_iclass_witlb,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "ldpte", ICLASS_xt_iclass_ldpte,
- 0,
- Opcode_ldpte_encode_fns, 0, 0 },
- { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_hwwitlba_encode_fns, 0, 0 },
- { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
- 0,
- Opcode_hwwdtlba_encode_fns, 0, 0 },
- { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
- 0,
- Opcode_rsr_cpenable_encode_fns, 0, 0 },
- { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
- 0,
- Opcode_wsr_cpenable_encode_fns, 0, 0 },
- { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
- 0,
- Opcode_xsr_cpenable_encode_fns, 0, 0 },
- { "clamps", ICLASS_xt_iclass_clamp,
- 0,
- Opcode_clamps_encode_fns, 0, 0 },
- { "min", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", ICLASS_xt_iclass_sx,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", ICLASS_xt_iclass_l32ai,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", ICLASS_xt_iclass_s32ri,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", ICLASS_xt_iclass_s32c1i,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
- 0,
- Opcode_rsr_atomctl_encode_fns, 0, 0 },
- { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
- 0,
- Opcode_wsr_atomctl_encode_fns, 0, 0 },
- { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
- 0,
- Opcode_xsr_atomctl_encode_fns, 0, 0 },
- { "quou", ICLASS_xt_iclass_div,
- 0,
- Opcode_quou_encode_fns, 0, 0 },
- { "quos", ICLASS_xt_iclass_div,
- 0,
- Opcode_quos_encode_fns, 0, 0 },
- { "remu", ICLASS_xt_iclass_div,
- 0,
- Opcode_remu_encode_fns, 0, 0 },
- { "rems", ICLASS_xt_iclass_div,
- 0,
- Opcode_rems_encode_fns, 0, 0 },
- { "rer", ICLASS_xt_iclass_rer,
- 0,
- Opcode_rer_encode_fns, 0, 0 },
- { "wer", ICLASS_xt_iclass_wer,
- 0,
- Opcode_wer_encode_fns, 0, 0 },
- { "rur.expstate", ICLASS_rur_expstate,
- 0,
- Opcode_rur_expstate_encode_fns, 0, 0 },
- { "wur.expstate", ICLASS_wur_expstate,
- 0,
- Opcode_wur_expstate_encode_fns, 0, 0 },
- { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
- 0,
- Opcode_read_impwire_encode_fns, 0, 0 },
- { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
- 0,
- Opcode_setb_expstate_encode_fns, 0, 0 },
- { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
- 0,
- Opcode_clrb_expstate_encode_fns, 0, 0 },
- { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
- 0,
- Opcode_wrmsk_expstate_encode_fns, 0, 0 }
-};
-
-enum xtensa_opcode_id {
- OPCODE_EXCW,
- OPCODE_RFE,
- OPCODE_RFDE,
- OPCODE_SYSCALL,
- OPCODE_SIMCALL,
- OPCODE_CALL12,
- OPCODE_CALL8,
- OPCODE_CALL4,
- OPCODE_CALLX12,
- OPCODE_CALLX8,
- OPCODE_CALLX4,
- OPCODE_ENTRY,
- OPCODE_MOVSP,
- OPCODE_ROTW,
- OPCODE_RETW,
- OPCODE_RETW_N,
- OPCODE_RFWO,
- OPCODE_RFWU,
- OPCODE_L32E,
- OPCODE_S32E,
- OPCODE_RSR_WINDOWBASE,
- OPCODE_WSR_WINDOWBASE,
- OPCODE_XSR_WINDOWBASE,
- OPCODE_RSR_WINDOWSTART,
- OPCODE_WSR_WINDOWSTART,
- OPCODE_XSR_WINDOWSTART,
- OPCODE_ADD_N,
- OPCODE_ADDI_N,
- OPCODE_BEQZ_N,
- OPCODE_BNEZ_N,
- OPCODE_ILL_N,
- OPCODE_L32I_N,
- OPCODE_MOV_N,
- OPCODE_MOVI_N,
- OPCODE_NOP_N,
- OPCODE_RET_N,
- OPCODE_S32I_N,
- OPCODE_RUR_THREADPTR,
- OPCODE_WUR_THREADPTR,
- OPCODE_ADDI,
- OPCODE_ADDMI,
- OPCODE_ADD,
- OPCODE_SUB,
- OPCODE_ADDX2,
- OPCODE_ADDX4,
- OPCODE_ADDX8,
- OPCODE_SUBX2,
- OPCODE_SUBX4,
- OPCODE_SUBX8,
- OPCODE_AND,
- OPCODE_OR,
- OPCODE_XOR,
- OPCODE_BEQI,
- OPCODE_BNEI,
- OPCODE_BGEI,
- OPCODE_BLTI,
- OPCODE_BBCI,
- OPCODE_BBSI,
- OPCODE_BGEUI,
- OPCODE_BLTUI,
- OPCODE_BEQ,
- OPCODE_BNE,
- OPCODE_BGE,
- OPCODE_BLT,
- OPCODE_BGEU,
- OPCODE_BLTU,
- OPCODE_BANY,
- OPCODE_BNONE,
- OPCODE_BALL,
- OPCODE_BNALL,
- OPCODE_BBC,
- OPCODE_BBS,
- OPCODE_BEQZ,
- OPCODE_BNEZ,
- OPCODE_BGEZ,
- OPCODE_BLTZ,
- OPCODE_CALL0,
- OPCODE_CALLX0,
- OPCODE_EXTUI,
- OPCODE_ILL,
- OPCODE_J,
- OPCODE_JX,
- OPCODE_L16UI,
- OPCODE_L16SI,
- OPCODE_L32I,
- OPCODE_L32R,
- OPCODE_L8UI,
- OPCODE_LOOP,
- OPCODE_LOOPNEZ,
- OPCODE_LOOPGTZ,
- OPCODE_MOVI,
- OPCODE_MOVEQZ,
- OPCODE_MOVNEZ,
- OPCODE_MOVLTZ,
- OPCODE_MOVGEZ,
- OPCODE_NEG,
- OPCODE_ABS,
- OPCODE_NOP,
- OPCODE_RET,
- OPCODE_S16I,
- OPCODE_S32I,
- OPCODE_S8I,
- OPCODE_SSR,
- OPCODE_SSL,
- OPCODE_SSA8L,
- OPCODE_SSA8B,
- OPCODE_SSAI,
- OPCODE_SLL,
- OPCODE_SRC,
- OPCODE_SRL,
- OPCODE_SRA,
- OPCODE_SLLI,
- OPCODE_SRAI,
- OPCODE_SRLI,
- OPCODE_MEMW,
- OPCODE_EXTW,
- OPCODE_ISYNC,
- OPCODE_RSYNC,
- OPCODE_ESYNC,
- OPCODE_DSYNC,
- OPCODE_RSIL,
- OPCODE_RSR_LEND,
- OPCODE_WSR_LEND,
- OPCODE_XSR_LEND,
- OPCODE_RSR_LCOUNT,
- OPCODE_WSR_LCOUNT,
- OPCODE_XSR_LCOUNT,
- OPCODE_RSR_LBEG,
- OPCODE_WSR_LBEG,
- OPCODE_XSR_LBEG,
- OPCODE_RSR_SAR,
- OPCODE_WSR_SAR,
- OPCODE_XSR_SAR,
- OPCODE_RSR_LITBASE,
- OPCODE_WSR_LITBASE,
- OPCODE_XSR_LITBASE,
- OPCODE_RSR_176,
- OPCODE_WSR_176,
- OPCODE_RSR_208,
- OPCODE_RSR_PS,
- OPCODE_WSR_PS,
- OPCODE_XSR_PS,
- OPCODE_RSR_EPC1,
- OPCODE_WSR_EPC1,
- OPCODE_XSR_EPC1,
- OPCODE_RSR_EXCSAVE1,
- OPCODE_WSR_EXCSAVE1,
- OPCODE_XSR_EXCSAVE1,
- OPCODE_RSR_EPC2,
- OPCODE_WSR_EPC2,
- OPCODE_XSR_EPC2,
- OPCODE_RSR_EXCSAVE2,
- OPCODE_WSR_EXCSAVE2,
- OPCODE_XSR_EXCSAVE2,
- OPCODE_RSR_EPC3,
- OPCODE_WSR_EPC3,
- OPCODE_XSR_EPC3,
- OPCODE_RSR_EXCSAVE3,
- OPCODE_WSR_EXCSAVE3,
- OPCODE_XSR_EXCSAVE3,
- OPCODE_RSR_EPC4,
- OPCODE_WSR_EPC4,
- OPCODE_XSR_EPC4,
- OPCODE_RSR_EXCSAVE4,
- OPCODE_WSR_EXCSAVE4,
- OPCODE_XSR_EXCSAVE4,
- OPCODE_RSR_EPC5,
- OPCODE_WSR_EPC5,
- OPCODE_XSR_EPC5,
- OPCODE_RSR_EXCSAVE5,
- OPCODE_WSR_EXCSAVE5,
- OPCODE_XSR_EXCSAVE5,
- OPCODE_RSR_EPC6,
- OPCODE_WSR_EPC6,
- OPCODE_XSR_EPC6,
- OPCODE_RSR_EXCSAVE6,
- OPCODE_WSR_EXCSAVE6,
- OPCODE_XSR_EXCSAVE6,
- OPCODE_RSR_EPC7,
- OPCODE_WSR_EPC7,
- OPCODE_XSR_EPC7,
- OPCODE_RSR_EXCSAVE7,
- OPCODE_WSR_EXCSAVE7,
- OPCODE_XSR_EXCSAVE7,
- OPCODE_RSR_EPS2,
- OPCODE_WSR_EPS2,
- OPCODE_XSR_EPS2,
- OPCODE_RSR_EPS3,
- OPCODE_WSR_EPS3,
- OPCODE_XSR_EPS3,
- OPCODE_RSR_EPS4,
- OPCODE_WSR_EPS4,
- OPCODE_XSR_EPS4,
- OPCODE_RSR_EPS5,
- OPCODE_WSR_EPS5,
- OPCODE_XSR_EPS5,
- OPCODE_RSR_EPS6,
- OPCODE_WSR_EPS6,
- OPCODE_XSR_EPS6,
- OPCODE_RSR_EPS7,
- OPCODE_WSR_EPS7,
- OPCODE_XSR_EPS7,
- OPCODE_RSR_EXCVADDR,
- OPCODE_WSR_EXCVADDR,
- OPCODE_XSR_EXCVADDR,
- OPCODE_RSR_DEPC,
- OPCODE_WSR_DEPC,
- OPCODE_XSR_DEPC,
- OPCODE_RSR_EXCCAUSE,
- OPCODE_WSR_EXCCAUSE,
- OPCODE_XSR_EXCCAUSE,
- OPCODE_RSR_MISC0,
- OPCODE_WSR_MISC0,
- OPCODE_XSR_MISC0,
- OPCODE_RSR_MISC1,
- OPCODE_WSR_MISC1,
- OPCODE_XSR_MISC1,
- OPCODE_RSR_PRID,
- OPCODE_RSR_VECBASE,
- OPCODE_WSR_VECBASE,
- OPCODE_XSR_VECBASE,
- OPCODE_MUL16U,
- OPCODE_MUL16S,
- OPCODE_MULL,
- OPCODE_MUL_AA_LL,
- OPCODE_MUL_AA_HL,
- OPCODE_MUL_AA_LH,
- OPCODE_MUL_AA_HH,
- OPCODE_UMUL_AA_LL,
- OPCODE_UMUL_AA_HL,
- OPCODE_UMUL_AA_LH,
- OPCODE_UMUL_AA_HH,
- OPCODE_MUL_AD_LL,
- OPCODE_MUL_AD_HL,
- OPCODE_MUL_AD_LH,
- OPCODE_MUL_AD_HH,
- OPCODE_MUL_DA_LL,
- OPCODE_MUL_DA_HL,
- OPCODE_MUL_DA_LH,
- OPCODE_MUL_DA_HH,
- OPCODE_MUL_DD_LL,
- OPCODE_MUL_DD_HL,
- OPCODE_MUL_DD_LH,
- OPCODE_MUL_DD_HH,
- OPCODE_MULA_AA_LL,
- OPCODE_MULA_AA_HL,
- OPCODE_MULA_AA_LH,
- OPCODE_MULA_AA_HH,
- OPCODE_MULS_AA_LL,
- OPCODE_MULS_AA_HL,
- OPCODE_MULS_AA_LH,
- OPCODE_MULS_AA_HH,
- OPCODE_MULA_AD_LL,
- OPCODE_MULA_AD_HL,
- OPCODE_MULA_AD_LH,
- OPCODE_MULA_AD_HH,
- OPCODE_MULS_AD_LL,
- OPCODE_MULS_AD_HL,
- OPCODE_MULS_AD_LH,
- OPCODE_MULS_AD_HH,
- OPCODE_MULA_DA_LL,
- OPCODE_MULA_DA_HL,
- OPCODE_MULA_DA_LH,
- OPCODE_MULA_DA_HH,
- OPCODE_MULS_DA_LL,
- OPCODE_MULS_DA_HL,
- OPCODE_MULS_DA_LH,
- OPCODE_MULS_DA_HH,
- OPCODE_MULA_DD_LL,
- OPCODE_MULA_DD_HL,
- OPCODE_MULA_DD_LH,
- OPCODE_MULA_DD_HH,
- OPCODE_MULS_DD_LL,
- OPCODE_MULS_DD_HL,
- OPCODE_MULS_DD_LH,
- OPCODE_MULS_DD_HH,
- OPCODE_MULA_DA_LL_LDDEC,
- OPCODE_MULA_DA_LL_LDINC,
- OPCODE_MULA_DA_HL_LDDEC,
- OPCODE_MULA_DA_HL_LDINC,
- OPCODE_MULA_DA_LH_LDDEC,
- OPCODE_MULA_DA_LH_LDINC,
- OPCODE_MULA_DA_HH_LDDEC,
- OPCODE_MULA_DA_HH_LDINC,
- OPCODE_MULA_DD_LL_LDDEC,
- OPCODE_MULA_DD_LL_LDINC,
- OPCODE_MULA_DD_HL_LDDEC,
- OPCODE_MULA_DD_HL_LDINC,
- OPCODE_MULA_DD_LH_LDDEC,
- OPCODE_MULA_DD_LH_LDINC,
- OPCODE_MULA_DD_HH_LDDEC,
- OPCODE_MULA_DD_HH_LDINC,
- OPCODE_LDDEC,
- OPCODE_LDINC,
- OPCODE_RSR_M0,
- OPCODE_WSR_M0,
- OPCODE_XSR_M0,
- OPCODE_RSR_M1,
- OPCODE_WSR_M1,
- OPCODE_XSR_M1,
- OPCODE_RSR_M2,
- OPCODE_WSR_M2,
- OPCODE_XSR_M2,
- OPCODE_RSR_M3,
- OPCODE_WSR_M3,
- OPCODE_XSR_M3,
- OPCODE_RSR_ACCLO,
- OPCODE_WSR_ACCLO,
- OPCODE_XSR_ACCLO,
- OPCODE_RSR_ACCHI,
- OPCODE_WSR_ACCHI,
- OPCODE_XSR_ACCHI,
- OPCODE_RFI,
- OPCODE_WAITI,
- OPCODE_RSR_INTERRUPT,
- OPCODE_WSR_INTSET,
- OPCODE_WSR_INTCLEAR,
- OPCODE_RSR_INTENABLE,
- OPCODE_WSR_INTENABLE,
- OPCODE_XSR_INTENABLE,
- OPCODE_BREAK,
- OPCODE_BREAK_N,
- OPCODE_RSR_DBREAKA0,
- OPCODE_WSR_DBREAKA0,
- OPCODE_XSR_DBREAKA0,
- OPCODE_RSR_DBREAKC0,
- OPCODE_WSR_DBREAKC0,
- OPCODE_XSR_DBREAKC0,
- OPCODE_RSR_DBREAKA1,
- OPCODE_WSR_DBREAKA1,
- OPCODE_XSR_DBREAKA1,
- OPCODE_RSR_DBREAKC1,
- OPCODE_WSR_DBREAKC1,
- OPCODE_XSR_DBREAKC1,
- OPCODE_RSR_IBREAKA0,
- OPCODE_WSR_IBREAKA0,
- OPCODE_XSR_IBREAKA0,
- OPCODE_RSR_IBREAKA1,
- OPCODE_WSR_IBREAKA1,
- OPCODE_XSR_IBREAKA1,
- OPCODE_RSR_IBREAKENABLE,
- OPCODE_WSR_IBREAKENABLE,
- OPCODE_XSR_IBREAKENABLE,
- OPCODE_RSR_DEBUGCAUSE,
- OPCODE_WSR_DEBUGCAUSE,
- OPCODE_XSR_DEBUGCAUSE,
- OPCODE_RSR_ICOUNT,
- OPCODE_WSR_ICOUNT,
- OPCODE_XSR_ICOUNT,
- OPCODE_RSR_ICOUNTLEVEL,
- OPCODE_WSR_ICOUNTLEVEL,
- OPCODE_XSR_ICOUNTLEVEL,
- OPCODE_RSR_DDR,
- OPCODE_WSR_DDR,
- OPCODE_XSR_DDR,
- OPCODE_RFDO,
- OPCODE_RFDD,
- OPCODE_WSR_MMID,
- OPCODE_RSR_CCOUNT,
- OPCODE_WSR_CCOUNT,
- OPCODE_XSR_CCOUNT,
- OPCODE_RSR_CCOMPARE0,
- OPCODE_WSR_CCOMPARE0,
- OPCODE_XSR_CCOMPARE0,
- OPCODE_RSR_CCOMPARE1,
- OPCODE_WSR_CCOMPARE1,
- OPCODE_XSR_CCOMPARE1,
- OPCODE_RSR_CCOMPARE2,
- OPCODE_WSR_CCOMPARE2,
- OPCODE_XSR_CCOMPARE2,
- OPCODE_IPF,
- OPCODE_IHI,
- OPCODE_IPFL,
- OPCODE_IHU,
- OPCODE_IIU,
- OPCODE_III,
- OPCODE_LICT,
- OPCODE_LICW,
- OPCODE_SICT,
- OPCODE_SICW,
- OPCODE_DHWB,
- OPCODE_DHWBI,
- OPCODE_DIWB,
- OPCODE_DIWBI,
- OPCODE_DHI,
- OPCODE_DII,
- OPCODE_DPFR,
- OPCODE_DPFW,
- OPCODE_DPFRO,
- OPCODE_DPFWO,
- OPCODE_DPFL,
- OPCODE_DHU,
- OPCODE_DIU,
- OPCODE_SDCT,
- OPCODE_LDCT,
- OPCODE_WSR_PTEVADDR,
- OPCODE_RSR_PTEVADDR,
- OPCODE_XSR_PTEVADDR,
- OPCODE_RSR_RASID,
- OPCODE_WSR_RASID,
- OPCODE_XSR_RASID,
- OPCODE_RSR_ITLBCFG,
- OPCODE_WSR_ITLBCFG,
- OPCODE_XSR_ITLBCFG,
- OPCODE_RSR_DTLBCFG,
- OPCODE_WSR_DTLBCFG,
- OPCODE_XSR_DTLBCFG,
- OPCODE_IDTLB,
- OPCODE_PDTLB,
- OPCODE_RDTLB0,
- OPCODE_RDTLB1,
- OPCODE_WDTLB,
- OPCODE_IITLB,
- OPCODE_PITLB,
- OPCODE_RITLB0,
- OPCODE_RITLB1,
- OPCODE_WITLB,
- OPCODE_LDPTE,
- OPCODE_HWWITLBA,
- OPCODE_HWWDTLBA,
- OPCODE_RSR_CPENABLE,
- OPCODE_WSR_CPENABLE,
- OPCODE_XSR_CPENABLE,
- OPCODE_CLAMPS,
- OPCODE_MIN,
- OPCODE_MAX,
- OPCODE_MINU,
- OPCODE_MAXU,
- OPCODE_NSA,
- OPCODE_NSAU,
- OPCODE_SEXT,
- OPCODE_L32AI,
- OPCODE_S32RI,
- OPCODE_S32C1I,
- OPCODE_RSR_SCOMPARE1,
- OPCODE_WSR_SCOMPARE1,
- OPCODE_XSR_SCOMPARE1,
- OPCODE_RSR_ATOMCTL,
- OPCODE_WSR_ATOMCTL,
- OPCODE_XSR_ATOMCTL,
- OPCODE_QUOU,
- OPCODE_QUOS,
- OPCODE_REMU,
- OPCODE_REMS,
- OPCODE_RER,
- OPCODE_WER,
- OPCODE_RUR_EXPSTATE,
- OPCODE_WUR_EXPSTATE,
- OPCODE_READ_IMPWIRE,
- OPCODE_SETB_EXPSTATE,
- OPCODE_CLRB_EXPSTATE,
- OPCODE_WRMSK_EXPSTATE
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_ILL;
- break;
- case 2:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_RET;
- case 1:
- return OPCODE_RETW;
- case 2:
- return OPCODE_JX;
- }
- break;
- case 3:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_CALLX0;
- case 1:
- return OPCODE_CALLX4;
- case 2:
- return OPCODE_CALLX8;
- case 3:
- return OPCODE_CALLX12;
- }
- break;
- }
- break;
- case 1:
- return OPCODE_MOVSP;
- case 2:
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_ISYNC;
- case 1:
- return OPCODE_RSYNC;
- case 2:
- return OPCODE_ESYNC;
- case 3:
- return OPCODE_DSYNC;
- case 8:
- return OPCODE_EXCW;
- case 12:
- return OPCODE_MEMW;
- case 13:
- return OPCODE_EXTW;
- case 15:
- return OPCODE_NOP;
- }
- }
- break;
- case 3:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_RFE;
- case 2:
- return OPCODE_RFDE;
- case 4:
- return OPCODE_RFWO;
- case 5:
- return OPCODE_RFWU;
- }
- break;
- case 1:
- return OPCODE_RFI;
- }
- break;
- case 4:
- return OPCODE_BREAK;
- case 5:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SYSCALL;
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SIMCALL;
- break;
- }
- break;
- case 6:
- return OPCODE_RSIL;
- case 7:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_WAITI;
- break;
- }
- break;
- case 1:
- return OPCODE_AND;
- case 2:
- return OPCODE_OR;
- case 3:
- return OPCODE_XOR;
- case 4:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSR;
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSL;
- break;
- case 2:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8L;
- break;
- case 3:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8B;
- break;
- case 4:
- if (Field_thi3_Slot_inst_get (insn) == 0)
- return OPCODE_SSAI;
- break;
- case 6:
- return OPCODE_RER;
- case 7:
- return OPCODE_WER;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_ROTW;
- break;
- case 14:
- return OPCODE_NSA;
- case 15:
- return OPCODE_NSAU;
- }
- break;
- case 5:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 1:
- return OPCODE_HWWITLBA;
- case 3:
- return OPCODE_RITLB0;
- case 4:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IITLB;
- break;
- case 5:
- return OPCODE_PITLB;
- case 6:
- return OPCODE_WITLB;
- case 7:
- return OPCODE_RITLB1;
- case 9:
- return OPCODE_HWWDTLBA;
- case 11:
- return OPCODE_RDTLB0;
- case 12:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IDTLB;
- break;
- case 13:
- return OPCODE_PDTLB;
- case 14:
- return OPCODE_WDTLB;
- case 15:
- return OPCODE_RDTLB1;
- }
- break;
- case 6:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_NEG;
- case 1:
- return OPCODE_ABS;
- }
- break;
- case 8:
- return OPCODE_ADD;
- case 9:
- return OPCODE_ADDX2;
- case 10:
- return OPCODE_ADDX4;
- case 11:
- return OPCODE_ADDX8;
- case 12:
- return OPCODE_SUB;
- case 13:
- return OPCODE_SUBX2;
- case 14:
- return OPCODE_SUBX4;
- case 15:
- return OPCODE_SUBX8;
- }
- break;
- case 1:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- case 1:
- return OPCODE_SLLI;
- case 2:
- case 3:
- return OPCODE_SRAI;
- case 4:
- return OPCODE_SRLI;
- case 6:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_XSR_LBEG;
- case 1:
- return OPCODE_XSR_LEND;
- case 2:
- return OPCODE_XSR_LCOUNT;
- case 3:
- return OPCODE_XSR_SAR;
- case 5:
- return OPCODE_XSR_LITBASE;
- case 12:
- return OPCODE_XSR_SCOMPARE1;
- case 16:
- return OPCODE_XSR_ACCLO;
- case 17:
- return OPCODE_XSR_ACCHI;
- case 32:
- return OPCODE_XSR_M0;
- case 33:
- return OPCODE_XSR_M1;
- case 34:
- return OPCODE_XSR_M2;
- case 35:
- return OPCODE_XSR_M3;
- case 72:
- return OPCODE_XSR_WINDOWBASE;
- case 73:
- return OPCODE_XSR_WINDOWSTART;
- case 83:
- return OPCODE_XSR_PTEVADDR;
- case 90:
- return OPCODE_XSR_RASID;
- case 91:
- return OPCODE_XSR_ITLBCFG;
- case 92:
- return OPCODE_XSR_DTLBCFG;
- case 96:
- return OPCODE_XSR_IBREAKENABLE;
- case 99:
- return OPCODE_XSR_ATOMCTL;
- case 104:
- return OPCODE_XSR_DDR;
- case 128:
- return OPCODE_XSR_IBREAKA0;
- case 129:
- return OPCODE_XSR_IBREAKA1;
- case 144:
- return OPCODE_XSR_DBREAKA0;
- case 145:
- return OPCODE_XSR_DBREAKA1;
- case 160:
- return OPCODE_XSR_DBREAKC0;
- case 161:
- return OPCODE_XSR_DBREAKC1;
- case 177:
- return OPCODE_XSR_EPC1;
- case 178:
- return OPCODE_XSR_EPC2;
- case 179:
- return OPCODE_XSR_EPC3;
- case 180:
- return OPCODE_XSR_EPC4;
- case 181:
- return OPCODE_XSR_EPC5;
- case 182:
- return OPCODE_XSR_EPC6;
- case 183:
- return OPCODE_XSR_EPC7;
- case 192:
- return OPCODE_XSR_DEPC;
- case 194:
- return OPCODE_XSR_EPS2;
- case 195:
- return OPCODE_XSR_EPS3;
- case 196:
- return OPCODE_XSR_EPS4;
- case 197:
- return OPCODE_XSR_EPS5;
- case 198:
- return OPCODE_XSR_EPS6;
- case 199:
- return OPCODE_XSR_EPS7;
- case 209:
- return OPCODE_XSR_EXCSAVE1;
- case 210:
- return OPCODE_XSR_EXCSAVE2;
- case 211:
- return OPCODE_XSR_EXCSAVE3;
- case 212:
- return OPCODE_XSR_EXCSAVE4;
- case 213:
- return OPCODE_XSR_EXCSAVE5;
- case 214:
- return OPCODE_XSR_EXCSAVE6;
- case 215:
- return OPCODE_XSR_EXCSAVE7;
- case 224:
- return OPCODE_XSR_CPENABLE;
- case 228:
- return OPCODE_XSR_INTENABLE;
- case 230:
- return OPCODE_XSR_PS;
- case 231:
- return OPCODE_XSR_VECBASE;
- case 232:
- return OPCODE_XSR_EXCCAUSE;
- case 233:
- return OPCODE_XSR_DEBUGCAUSE;
- case 234:
- return OPCODE_XSR_CCOUNT;
- case 236:
- return OPCODE_XSR_ICOUNT;
- case 237:
- return OPCODE_XSR_ICOUNTLEVEL;
- case 238:
- return OPCODE_XSR_EXCVADDR;
- case 240:
- return OPCODE_XSR_CCOMPARE0;
- case 241:
- return OPCODE_XSR_CCOMPARE1;
- case 242:
- return OPCODE_XSR_CCOMPARE2;
- case 244:
- return OPCODE_XSR_MISC0;
- case 245:
- return OPCODE_XSR_MISC1;
- }
- break;
- case 8:
- return OPCODE_SRC;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRL;
- break;
- case 10:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SLL;
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRA;
- break;
- case 12:
- return OPCODE_MUL16U;
- case 13:
- return OPCODE_MUL16S;
- case 15:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_LICT;
- case 1:
- return OPCODE_SICT;
- case 2:
- return OPCODE_LICW;
- case 3:
- return OPCODE_SICW;
- case 8:
- return OPCODE_LDCT;
- case 9:
- return OPCODE_SDCT;
- case 14:
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_RFDO;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFDD;
- break;
- case 15:
- return OPCODE_LDPTE;
- }
- break;
- }
- break;
- case 2:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 8:
- return OPCODE_MULL;
- case 12:
- return OPCODE_QUOU;
- case 13:
- return OPCODE_QUOS;
- case 14:
- return OPCODE_REMU;
- case 15:
- return OPCODE_REMS;
- }
- break;
- case 3:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_RSR_LBEG;
- case 1:
- return OPCODE_RSR_LEND;
- case 2:
- return OPCODE_RSR_LCOUNT;
- case 3:
- return OPCODE_RSR_SAR;
- case 5:
- return OPCODE_RSR_LITBASE;
- case 12:
- return OPCODE_RSR_SCOMPARE1;
- case 16:
- return OPCODE_RSR_ACCLO;
- case 17:
- return OPCODE_RSR_ACCHI;
- case 32:
- return OPCODE_RSR_M0;
- case 33:
- return OPCODE_RSR_M1;
- case 34:
- return OPCODE_RSR_M2;
- case 35:
- return OPCODE_RSR_M3;
- case 72:
- return OPCODE_RSR_WINDOWBASE;
- case 73:
- return OPCODE_RSR_WINDOWSTART;
- case 83:
- return OPCODE_RSR_PTEVADDR;
- case 90:
- return OPCODE_RSR_RASID;
- case 91:
- return OPCODE_RSR_ITLBCFG;
- case 92:
- return OPCODE_RSR_DTLBCFG;
- case 96:
- return OPCODE_RSR_IBREAKENABLE;
- case 99:
- return OPCODE_RSR_ATOMCTL;
- case 104:
- return OPCODE_RSR_DDR;
- case 128:
- return OPCODE_RSR_IBREAKA0;
- case 129:
- return OPCODE_RSR_IBREAKA1;
- case 144:
- return OPCODE_RSR_DBREAKA0;
- case 145:
- return OPCODE_RSR_DBREAKA1;
- case 160:
- return OPCODE_RSR_DBREAKC0;
- case 161:
- return OPCODE_RSR_DBREAKC1;
- case 176:
- return OPCODE_RSR_176;
- case 177:
- return OPCODE_RSR_EPC1;
- case 178:
- return OPCODE_RSR_EPC2;
- case 179:
- return OPCODE_RSR_EPC3;
- case 180:
- return OPCODE_RSR_EPC4;
- case 181:
- return OPCODE_RSR_EPC5;
- case 182:
- return OPCODE_RSR_EPC6;
- case 183:
- return OPCODE_RSR_EPC7;
- case 192:
- return OPCODE_RSR_DEPC;
- case 194:
- return OPCODE_RSR_EPS2;
- case 195:
- return OPCODE_RSR_EPS3;
- case 196:
- return OPCODE_RSR_EPS4;
- case 197:
- return OPCODE_RSR_EPS5;
- case 198:
- return OPCODE_RSR_EPS6;
- case 199:
- return OPCODE_RSR_EPS7;
- case 208:
- return OPCODE_RSR_208;
- case 209:
- return OPCODE_RSR_EXCSAVE1;
- case 210:
- return OPCODE_RSR_EXCSAVE2;
- case 211:
- return OPCODE_RSR_EXCSAVE3;
- case 212:
- return OPCODE_RSR_EXCSAVE4;
- case 213:
- return OPCODE_RSR_EXCSAVE5;
- case 214:
- return OPCODE_RSR_EXCSAVE6;
- case 215:
- return OPCODE_RSR_EXCSAVE7;
- case 224:
- return OPCODE_RSR_CPENABLE;
- case 226:
- return OPCODE_RSR_INTERRUPT;
- case 228:
- return OPCODE_RSR_INTENABLE;
- case 230:
- return OPCODE_RSR_PS;
- case 231:
- return OPCODE_RSR_VECBASE;
- case 232:
- return OPCODE_RSR_EXCCAUSE;
- case 233:
- return OPCODE_RSR_DEBUGCAUSE;
- case 234:
- return OPCODE_RSR_CCOUNT;
- case 235:
- return OPCODE_RSR_PRID;
- case 236:
- return OPCODE_RSR_ICOUNT;
- case 237:
- return OPCODE_RSR_ICOUNTLEVEL;
- case 238:
- return OPCODE_RSR_EXCVADDR;
- case 240:
- return OPCODE_RSR_CCOMPARE0;
- case 241:
- return OPCODE_RSR_CCOMPARE1;
- case 242:
- return OPCODE_RSR_CCOMPARE2;
- case 244:
- return OPCODE_RSR_MISC0;
- case 245:
- return OPCODE_RSR_MISC1;
- }
- break;
- case 1:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_WSR_LBEG;
- case 1:
- return OPCODE_WSR_LEND;
- case 2:
- return OPCODE_WSR_LCOUNT;
- case 3:
- return OPCODE_WSR_SAR;
- case 5:
- return OPCODE_WSR_LITBASE;
- case 12:
- return OPCODE_WSR_SCOMPARE1;
- case 16:
- return OPCODE_WSR_ACCLO;
- case 17:
- return OPCODE_WSR_ACCHI;
- case 32:
- return OPCODE_WSR_M0;
- case 33:
- return OPCODE_WSR_M1;
- case 34:
- return OPCODE_WSR_M2;
- case 35:
- return OPCODE_WSR_M3;
- case 72:
- return OPCODE_WSR_WINDOWBASE;
- case 73:
- return OPCODE_WSR_WINDOWSTART;
- case 83:
- return OPCODE_WSR_PTEVADDR;
- case 89:
- return OPCODE_WSR_MMID;
- case 90:
- return OPCODE_WSR_RASID;
- case 91:
- return OPCODE_WSR_ITLBCFG;
- case 92:
- return OPCODE_WSR_DTLBCFG;
- case 96:
- return OPCODE_WSR_IBREAKENABLE;
- case 99:
- return OPCODE_WSR_ATOMCTL;
- case 104:
- return OPCODE_WSR_DDR;
- case 128:
- return OPCODE_WSR_IBREAKA0;
- case 129:
- return OPCODE_WSR_IBREAKA1;
- case 144:
- return OPCODE_WSR_DBREAKA0;
- case 145:
- return OPCODE_WSR_DBREAKA1;
- case 160:
- return OPCODE_WSR_DBREAKC0;
- case 161:
- return OPCODE_WSR_DBREAKC1;
- case 176:
- return OPCODE_WSR_176;
- case 177:
- return OPCODE_WSR_EPC1;
- case 178:
- return OPCODE_WSR_EPC2;
- case 179:
- return OPCODE_WSR_EPC3;
- case 180:
- return OPCODE_WSR_EPC4;
- case 181:
- return OPCODE_WSR_EPC5;
- case 182:
- return OPCODE_WSR_EPC6;
- case 183:
- return OPCODE_WSR_EPC7;
- case 192:
- return OPCODE_WSR_DEPC;
- case 194:
- return OPCODE_WSR_EPS2;
- case 195:
- return OPCODE_WSR_EPS3;
- case 196:
- return OPCODE_WSR_EPS4;
- case 197:
- return OPCODE_WSR_EPS5;
- case 198:
- return OPCODE_WSR_EPS6;
- case 199:
- return OPCODE_WSR_EPS7;
- case 209:
- return OPCODE_WSR_EXCSAVE1;
- case 210:
- return OPCODE_WSR_EXCSAVE2;
- case 211:
- return OPCODE_WSR_EXCSAVE3;
- case 212:
- return OPCODE_WSR_EXCSAVE4;
- case 213:
- return OPCODE_WSR_EXCSAVE5;
- case 214:
- return OPCODE_WSR_EXCSAVE6;
- case 215:
- return OPCODE_WSR_EXCSAVE7;
- case 224:
- return OPCODE_WSR_CPENABLE;
- case 226:
- return OPCODE_WSR_INTSET;
- case 227:
- return OPCODE_WSR_INTCLEAR;
- case 228:
- return OPCODE_WSR_INTENABLE;
- case 230:
- return OPCODE_WSR_PS;
- case 231:
- return OPCODE_WSR_VECBASE;
- case 232:
- return OPCODE_WSR_EXCCAUSE;
- case 233:
- return OPCODE_WSR_DEBUGCAUSE;
- case 234:
- return OPCODE_WSR_CCOUNT;
- case 236:
- return OPCODE_WSR_ICOUNT;
- case 237:
- return OPCODE_WSR_ICOUNTLEVEL;
- case 238:
- return OPCODE_WSR_EXCVADDR;
- case 240:
- return OPCODE_WSR_CCOMPARE0;
- case 241:
- return OPCODE_WSR_CCOMPARE1;
- case 242:
- return OPCODE_WSR_CCOMPARE2;
- case 244:
- return OPCODE_WSR_MISC0;
- case 245:
- return OPCODE_WSR_MISC1;
- }
- break;
- case 2:
- return OPCODE_SEXT;
- case 3:
- return OPCODE_CLAMPS;
- case 4:
- return OPCODE_MIN;
- case 5:
- return OPCODE_MAX;
- case 6:
- return OPCODE_MINU;
- case 7:
- return OPCODE_MAXU;
- case 8:
- return OPCODE_MOVEQZ;
- case 9:
- return OPCODE_MOVNEZ;
- case 10:
- return OPCODE_MOVLTZ;
- case 11:
- return OPCODE_MOVGEZ;
- case 14:
- switch (Field_st_Slot_inst_get (insn))
- {
- case 230:
- return OPCODE_RUR_EXPSTATE;
- case 231:
- return OPCODE_RUR_THREADPTR;
- }
- break;
- case 15:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 230:
- return OPCODE_WUR_EXPSTATE;
- case 231:
- return OPCODE_WUR_THREADPTR;
- }
- break;
- }
- break;
- case 4:
- case 5:
- return OPCODE_EXTUI;
- case 9:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_L32E;
- case 4:
- return OPCODE_S32E;
- }
- break;
- }
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_READ_IMPWIRE;
- break;
- case 1:
- if (Field_s3to1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_SETB_EXPSTATE;
- if (Field_s3to1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_CLRB_EXPSTATE;
- break;
- case 2:
- if (Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_WRMSK_EXPSTATE;
- break;
- }
- break;
- case 1:
- return OPCODE_L32R;
- case 2:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_L8UI;
- case 1:
- return OPCODE_L16UI;
- case 2:
- return OPCODE_L32I;
- case 4:
- return OPCODE_S8I;
- case 5:
- return OPCODE_S16I;
- case 6:
- return OPCODE_S32I;
- case 7:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_DPFR;
- case 1:
- return OPCODE_DPFW;
- case 2:
- return OPCODE_DPFRO;
- case 3:
- return OPCODE_DPFWO;
- case 4:
- return OPCODE_DHWB;
- case 5:
- return OPCODE_DHWBI;
- case 6:
- return OPCODE_DHI;
- case 7:
- return OPCODE_DII;
- case 8:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_DPFL;
- case 2:
- return OPCODE_DHU;
- case 3:
- return OPCODE_DIU;
- case 4:
- return OPCODE_DIWB;
- case 5:
- return OPCODE_DIWBI;
- }
- break;
- case 12:
- return OPCODE_IPF;
- case 13:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_IPFL;
- case 2:
- return OPCODE_IHU;
- case 3:
- return OPCODE_IIU;
- }
- break;
- case 14:
- return OPCODE_IHI;
- case 15:
- return OPCODE_III;
- }
- break;
- case 9:
- return OPCODE_L16SI;
- case 10:
- return OPCODE_MOVI;
- case 11:
- return OPCODE_L32AI;
- case 12:
- return OPCODE_ADDI;
- case 13:
- return OPCODE_ADDMI;
- case 14:
- return OPCODE_S32C1I;
- case 15:
- return OPCODE_S32RI;
- }
- break;
- case 4:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL_LDINC;
- break;
- case 9:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL_LDINC;
- break;
- case 10:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH_LDINC;
- break;
- case 11:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH_LDINC;
- break;
- }
- break;
- case 1:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL_LDDEC;
- break;
- case 9:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL_LDDEC;
- break;
- case 10:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH_LDDEC;
- break;
- case 11:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH_LDDEC;
- break;
- }
- break;
- case 2:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_LL;
- break;
- case 5:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_HL;
- break;
- case 6:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_LH;
- break;
- case 7:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_HH;
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL;
- break;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL;
- break;
- case 10:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH;
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH;
- break;
- case 12:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_LL;
- break;
- case 13:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_HL;
- break;
- case 14:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_LH;
- break;
- case 15:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_HH;
- break;
- }
- break;
- case 3:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_LL;
- break;
- case 5:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_HL;
- break;
- case 6:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_LH;
- break;
- case 7:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_HH;
- break;
- case 8:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_LL;
- break;
- case 9:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_HL;
- break;
- case 10:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_LH;
- break;
- case 11:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_HH;
- break;
- case 12:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_LL;
- break;
- case 13:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_HL;
- break;
- case 14:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_LH;
- break;
- case 15:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_HH;
- break;
- }
- break;
- case 4:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL_LDINC;
- break;
- case 9:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL_LDINC;
- break;
- case 10:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH_LDINC;
- break;
- case 11:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH_LDINC;
- break;
- }
- break;
- case 5:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL_LDDEC;
- break;
- case 9:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL_LDDEC;
- break;
- case 10:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH_LDDEC;
- break;
- case 11:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH_LDDEC;
- break;
- }
- break;
- case 6:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_LL;
- break;
- case 5:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_HL;
- break;
- case 6:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_LH;
- break;
- case 7:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_HH;
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL;
- break;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL;
- break;
- case 10:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH;
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH;
- break;
- case 12:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_LL;
- break;
- case 13:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_HL;
- break;
- case 14:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_LH;
- break;
- case 15:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_HH;
- break;
- }
- break;
- case 7:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_LL;
- break;
- case 1:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_HL;
- break;
- case 2:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_LH;
- break;
- case 3:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_HH;
- break;
- case 4:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_LL;
- break;
- case 5:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_HL;
- break;
- case 6:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_LH;
- break;
- case 7:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_HH;
- break;
- case 8:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_LL;
- break;
- case 9:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_HL;
- break;
- case 10:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_LH;
- break;
- case 11:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_HH;
- break;
- case 12:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_LL;
- break;
- case 13:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_HL;
- break;
- case 14:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_LH;
- break;
- case 15:
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_HH;
- break;
- }
- break;
- case 8:
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return OPCODE_LDINC;
- break;
- case 9:
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return OPCODE_LDDEC;
- break;
- }
- break;
- case 5:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_CALL0;
- case 1:
- return OPCODE_CALL4;
- case 2:
- return OPCODE_CALL8;
- case 3:
- return OPCODE_CALL12;
- }
- break;
- case 6:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_J;
- case 1:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_BEQZ;
- case 1:
- return OPCODE_BNEZ;
- case 2:
- return OPCODE_BLTZ;
- case 3:
- return OPCODE_BGEZ;
- }
- break;
- case 2:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_BEQI;
- case 1:
- return OPCODE_BNEI;
- case 2:
- return OPCODE_BLTI;
- case 3:
- return OPCODE_BGEI;
- }
- break;
- case 3:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_ENTRY;
- case 1:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 8:
- return OPCODE_LOOP;
- case 9:
- return OPCODE_LOOPNEZ;
- case 10:
- return OPCODE_LOOPGTZ;
- }
- break;
- case 2:
- return OPCODE_BLTUI;
- case 3:
- return OPCODE_BGEUI;
- }
- break;
- }
- break;
- case 7:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return OPCODE_BNONE;
- case 1:
- return OPCODE_BEQ;
- case 2:
- return OPCODE_BLT;
- case 3:
- return OPCODE_BLTU;
- case 4:
- return OPCODE_BALL;
- case 5:
- return OPCODE_BBC;
- case 6:
- case 7:
- return OPCODE_BBCI;
- case 8:
- return OPCODE_BANY;
- case 9:
- return OPCODE_BNE;
- case 10:
- return OPCODE_BGE;
- case 11:
- return OPCODE_BGEU;
- case 12:
- return OPCODE_BNALL;
- case 13:
- return OPCODE_BBS;
- case 14:
- case 15:
- return OPCODE_BBSI;
- }
- break;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst16b_get (insn))
- {
- case 12:
- switch (Field_i_Slot_inst16b_get (insn))
- {
- case 0:
- return OPCODE_MOVI_N;
- case 1:
- switch (Field_z_Slot_inst16b_get (insn))
- {
- case 0:
- return OPCODE_BEQZ_N;
- case 1:
- return OPCODE_BNEZ_N;
- }
- break;
- }
- break;
- case 13:
- switch (Field_r_Slot_inst16b_get (insn))
- {
- case 0:
- return OPCODE_MOV_N;
- case 15:
- switch (Field_t_Slot_inst16b_get (insn))
- {
- case 0:
- return OPCODE_RET_N;
- case 1:
- return OPCODE_RETW_N;
- case 2:
- return OPCODE_BREAK_N;
- case 3:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_NOP_N;
- break;
- case 6:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_ILL_N;
- break;
- }
- break;
- }
- break;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst16a_get (insn))
- {
- case 8:
- return OPCODE_L32I_N;
- case 9:
- return OPCODE_S32I_N;
- case 10:
- return OPCODE_ADD_N;
- case 11:
- return OPCODE_ADDI_N;
- }
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffffff);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_get,
- Field_rbit2_Slot_inst_get,
- Field_rhi_Slot_inst_get,
- Field_t3_Slot_inst_get,
- Field_tbit2_Slot_inst_get,
- Field_tlo_Slot_inst_get,
- Field_w_Slot_inst_get,
- Field_y_Slot_inst_get,
- Field_x_Slot_inst_get,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- Field_bitindex_Slot_inst_get,
- Field_s3to1_Slot_inst_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_set,
- Field_rbit2_Slot_inst_set,
- Field_rhi_Slot_inst_set,
- Field_t3_Slot_inst_set,
- Field_tbit2_Slot_inst_set,
- Field_tlo_Slot_inst_set,
- Field_w_Slot_inst_set,
- Field_y_Slot_inst_set,
- Field_x_Slot_inst_set,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- Field_bitindex_Slot_inst_set,
- Field_s3to1_Slot_inst_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_get,
- Field_s3to1_Slot_inst16a_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_set,
- Field_s3to1_Slot_inst16a_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_get,
- Field_s3to1_Slot_inst16b_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_set,
- Field_s3to1_Slot_inst16b_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0x8;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xc;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0x8) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc) == 0x8)
- return 1; /* x16a */
- if ((insn[0] & 0xe) == 0xc)
- return 2; /* x16b */
- return -1;
-}
-
-static int length_table[16] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int op0 = insn[0] & 0xf;
- return length_table[op0];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 0 /* little-endian */,
- 3 /* insn_size */, 0,
- 3, formats, format_decoder, length_decoder,
- 3, slots,
- 56 /* num_fields */,
- 93, operands,
- 326, iclasses,
- 452, opcodes, 0,
- 2, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 1, interfaces, 0,
- 0, funcUnits, 0
-};
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_de212
-#include "core-de212/xtensa-modules.inc.c"
+#include "core-de212/xtensa-modules.c.inc"
static XtensaConfig de212 __attribute__((unused)) = {
.name = "de212",
.gdb_regmap = {
.reg = {
-#include "core-de212/gdb-config.inc.c"
+#include "core-de212/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
--- /dev/null
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
+ XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
+ XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
+ XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
+ XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 42,168,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 43,172,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
+ XTREG( 44,176, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
+ XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG( 51,204, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG( 52,208, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG( 53,212,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG( 54,216,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG( 55,220,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG( 56,224,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG( 57,228,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG( 58,232,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG( 59,236,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG( 60,240,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG( 61,244,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG( 63,252,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG( 65,260,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG( 66,264,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG( 67,268,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG( 68,272,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG( 69,276,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG( 70,280,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG( 71,284,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG( 72,288,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG( 73,292,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG( 74,296,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG( 75,300,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG( 76,304,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG( 77,308,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG( 78,312,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG( 79,316,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG( 80,320,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG( 81,324,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG( 82,328,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG( 83,332,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG( 86,344, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG( 87,348,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG( 88,352,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG( 89,356,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG( 90,360,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG( 91,364, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG( 93,372,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG( 94,376,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG( 95,380,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG( 96,384,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG( 98,392,32, 8, 4,0x2015,0x000f,-2, 4,0x0101,pwrctl,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG( 99,400,32, 8, 4,0x2016,0x000f,-2, 4,0x0101,pwrstat,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(100,408, 1, 8, 4,0x2017,0x000f,-2, 4,0x0101,eristat,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(101,416,32, 8, 4,0x2018,0x000f,-2, 4,0x0101,cs_itctrl,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(102,424,16, 8, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimset,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(103,432,16, 8, 4,0x201a,0x000f,-2, 4,0x0101,cs_claimclr,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(104,440,32, 8, 4,0x201b,0x000f,-2, 4,0x0101,cs_lockaccess,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(105,448,32, 8, 4,0x201c,0x000f,-2, 4,0x0101,cs_lockstatus,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(106,456, 1, 8, 4,0x201d,0x000f,-2, 4,0x0101,cs_authstatus,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(107,464,32, 8, 4,0x202c,0x0007,-2, 4,0x0101,trax_id,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(108,472,32, 8, 4,0x202d,0x000f,-2, 4,0x0101,trax_control,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(109,480,32, 8, 4,0x202e,0x000f,-2, 4,0x0101,trax_status,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(110,488,32, 8, 4,0x202f,0x000f,-2, 4,0x0101,trax_data,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(111,496,32, 8, 4,0x2030,0x000f,-2, 4,0x0101,trax_address,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(112,504,32, 8, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(113,512,32, 8, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(114,520,32, 8, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(115,528,32, 8, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(116,536,32, 8, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(117,544,32, 8, 4,0x2043,0x0007,-2, 4,0x0101,ocdid,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(118,552,32, 8, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(119,560,32, 8, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(120,568,32, 8, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(121,576,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG(122,580,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG(123,584,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG(124,588,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG(125,592,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG(126,596,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG(127,600,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG(128,604,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG(129,608,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG(130,612,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG(131,616,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(132,620,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(133,624,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(134,628,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(135,632,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(136,636,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(137,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask0,0,0,0)
+ XTREG(138,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask1,0,0,0)
+ XTREG(139,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask2,0,0,0)
+ XTREG(140,652, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask3,0,0,0)
+ XTREG(141,656, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask4,0,0,0)
+ XTREG(142,660, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask5,0,0,0)
+ XTREG(143,664,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
+ 0,0,&xtensa_mask6,0,0,0)
+ XTREG_END
+++ /dev/null
-/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
-
- Copyright (c) 2003-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
- XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
- XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
- XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
- XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
- XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
- XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
- XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
- XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
- XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
- XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
- XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
- XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
- XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
- XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
- XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
- XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
- XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
- XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
- XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
- XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
- XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
- XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
- XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
- XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
- XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
- XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
- XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
- XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
- XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
- XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
- XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
- XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
- XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
- XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
- XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
- XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
- XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
- XTREG( 42,168,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
- XTREG( 43,172,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
- XTREG( 44,176, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
- XTREG( 45,180,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
- XTREG( 46,184,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
- XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
- XTREG( 48,192,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
- XTREG( 49,196,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
- XTREG( 50,200,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
- XTREG( 51,204, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
- XTREG( 52,208, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
- XTREG( 53,212,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
- XTREG( 54,216,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
- XTREG( 55,220,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
- XTREG( 56,224,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
- XTREG( 57,228,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
- XTREG( 58,232,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
- XTREG( 59,236,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
- XTREG( 60,240,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
- XTREG( 61,244,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
- XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
- XTREG( 63,252,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
- XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
- XTREG( 65,260,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
- XTREG( 66,264,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
- XTREG( 67,268,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
- XTREG( 68,272,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
- XTREG( 69,276,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
- XTREG( 70,280,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
- XTREG( 71,284,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
- XTREG( 72,288,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
- XTREG( 73,292,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
- XTREG( 74,296,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
- XTREG( 75,300,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
- XTREG( 76,304,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
- XTREG( 77,308,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
- XTREG( 78,312,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
- XTREG( 79,316,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
- XTREG( 80,320,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
- XTREG( 81,324,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
- XTREG( 82,328,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
- XTREG( 83,332,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
- XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
- XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
- XTREG( 86,344, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
- XTREG( 87,348,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
- XTREG( 88,352,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
- XTREG( 89,356,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
- XTREG( 90,360,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
- XTREG( 91,364, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
- XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
- XTREG( 93,372,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
- XTREG( 94,376,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
- XTREG( 95,380,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
- XTREG( 96,384,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
- XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
- XTREG( 98,392,32, 8, 4,0x2015,0x000f,-2, 4,0x0101,pwrctl,
- "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG( 99,400,32, 8, 4,0x2016,0x000f,-2, 4,0x0101,pwrstat,
- "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(100,408, 1, 8, 4,0x2017,0x000f,-2, 4,0x0101,eristat,
- "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(101,416,32, 8, 4,0x2018,0x000f,-2, 4,0x0101,cs_itctrl,
- "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(102,424,16, 8, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimset,
- "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(103,432,16, 8, 4,0x201a,0x000f,-2, 4,0x0101,cs_claimclr,
- "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(104,440,32, 8, 4,0x201b,0x000f,-2, 4,0x0101,cs_lockaccess,
- "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(105,448,32, 8, 4,0x201c,0x000f,-2, 4,0x0101,cs_lockstatus,
- "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(106,456, 1, 8, 4,0x201d,0x000f,-2, 4,0x0101,cs_authstatus,
- "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(107,464,32, 8, 4,0x202c,0x0007,-2, 4,0x0101,trax_id,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(108,472,32, 8, 4,0x202d,0x000f,-2, 4,0x0101,trax_control,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(109,480,32, 8, 4,0x202e,0x000f,-2, 4,0x0101,trax_status,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(110,488,32, 8, 4,0x202f,0x000f,-2, 4,0x0101,trax_data,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(111,496,32, 8, 4,0x2030,0x000f,-2, 4,0x0101,trax_address,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(112,504,32, 8, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(113,512,32, 8, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(114,520,32, 8, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(115,528,32, 8, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(116,536,32, 8, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend,
- "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(117,544,32, 8, 4,0x2043,0x0007,-2, 4,0x0101,ocdid,
- "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(118,552,32, 8, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr,
- "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(119,560,32, 8, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset,
- "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(120,568,32, 8, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr,
- "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
- XTREG(121,576,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
- XTREG(122,580,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
- XTREG(123,584,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
- XTREG(124,588,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
- XTREG(125,592,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
- XTREG(126,596,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
- XTREG(127,600,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
- XTREG(128,604,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
- XTREG(129,608,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
- XTREG(130,612,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
- XTREG(131,616,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
- XTREG(132,620,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
- XTREG(133,624,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
- XTREG(134,628,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
- XTREG(135,632,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
- XTREG(136,636,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
- XTREG(137,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
- 0,0,&xtensa_mask0,0,0,0)
- XTREG(138,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
- 0,0,&xtensa_mask1,0,0,0)
- XTREG(139,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
- 0,0,&xtensa_mask2,0,0,0)
- XTREG(140,652, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
- 0,0,&xtensa_mask3,0,0,0)
- XTREG(141,656, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
- 0,0,&xtensa_mask4,0,0,0)
- XTREG(142,660, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
- 0,0,&xtensa_mask5,0,0,0)
- XTREG(143,664,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
- 0,0,&xtensa_mask6,0,0,0)
- XTREG_END
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+
+ Copyright (c) 2003-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "qemu/osdep.h"
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "ACCLO", 16, 0 },
+ { "ACCHI", 17, 0 },
+ { "M0", 32, 0 },
+ { "M1", 33, 0 },
+ { "M2", 34, 0 },
+ { "M3", 35, 0 },
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "CONFIGID0", 176, 0 },
+ { "CONFIGID1", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 64
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 230
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 13, 0 },
+ { "EPS3", 13, 0 },
+ { "EPS4", 13, 0 },
+ { "EPS5", 13, 0 },
+ { "EPS6", 13, 0 },
+ { "EPS7", 13, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "ACC", 40, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "ERI_RAW_INTERLOCK", 1, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 64
+
+enum xtensa_state_id {
+ STATE_LCOUNT,
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EPC3,
+ STATE_EPC4,
+ STATE_EPC5,
+ STATE_EPC6,
+ STATE_EPC7,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EXCSAVE3,
+ STATE_EXCSAVE4,
+ STATE_EXCSAVE5,
+ STATE_EXCSAVE6,
+ STATE_EXCSAVE7,
+ STATE_EPS2,
+ STATE_EPS3,
+ STATE_EPS4,
+ STATE_EPS5,
+ STATE_EPS6,
+ STATE_EPS7,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_LBEG,
+ STATE_LEND,
+ STATE_SAR,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_ACC,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_DBREAKA0,
+ STATE_DBREAKC0,
+ STATE_DBREAKA1,
+ STATE_DBREAKC1,
+ STATE_IBREAKA0,
+ STATE_IBREAKA1,
+ STATE_IBREAKENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_CCOMPARE2,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_ERI_RAW_INTERLOCK,
+ STATE_EXPSTATE
+};
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_r3,
+ FIELD_rbit2,
+ FIELD_rhi,
+ FIELD_t3,
+ FIELD_tbit2,
+ FIELD_tlo,
+ FIELD_w,
+ FIELD_y,
+ FIELD_x,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_bitindex,
+ FIELD_s3to1,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12,
+ FIELD__mr0,
+ FIELD__mr1,
+ FIELD__mr2,
+ FIELD__mr3
+};
+
+\f
+/* Functional units. */
+
+#define funcUnits 0
+
+\f
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR,
+ REGFILE_MR
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 },
+ { "MR", "m", REGFILE_MR, 32, 4 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "ERI_RD_Out", 14, 0, 0, 'o' },
+ { "ERI_RD_In", 32, 0, 1, 'i' },
+ { "ERI_RD_Rdy", 1, 0, 0, 'i' },
+ { "ERI_WR_Out", 46, 0, 2, 'o' },
+ { "ERI_WR_In", 1, 0, 3, 'i' },
+ { "IMPWIRE", 32, 0, 4, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_ERI_RD_Out,
+ INTERFACE_ERI_RD_In,
+ INTERFACE_ERI_RD_Rdy,
+ INTERFACE_ERI_WR_Out,
+ INTERFACE_ERI_WR_In,
+ INTERFACE_IMPWIRE
+};
+
+
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
+{
+ *valp += 2;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
+{
+ int error;
+ error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+ *valp = *valp & 1;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_out_0;
+ unsigned soffsetx4_in_0;
+ soffsetx4_in_0 = *valp & 0x3ffff;
+ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+ unsigned soffsetx4_in_0;
+ unsigned soffsetx4_out_0;
+ soffsetx4_out_0 = *valp;
+ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = soffsetx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_out_0;
+ unsigned uimm12x8_in_0;
+ uimm12x8_in_0 = *valp & 0xfff;
+ uimm12x8_out_0 = uimm12x8_in_0 << 3;
+ *valp = uimm12x8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+ unsigned uimm12x8_in_0;
+ unsigned uimm12x8_out_0;
+ uimm12x8_out_0 = *valp;
+ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+ *valp = uimm12x8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_out_0;
+ unsigned simm4_in_0;
+ simm4_in_0 = *valp & 0xf;
+ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+ *valp = simm4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+ unsigned simm4_in_0;
+ unsigned simm4_out_0;
+ simm4_out_0 = *valp;
+ simm4_in_0 = (simm4_out_0 & 0xf);
+ *valp = simm4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_out_0;
+ unsigned immrx4_in_0;
+ immrx4_in_0 = *valp & 0xf;
+ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+ *valp = immrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+ unsigned immrx4_in_0;
+ unsigned immrx4_out_0;
+ immrx4_out_0 = *valp;
+ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+ *valp = immrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_out_0;
+ unsigned lsi4x4_in_0;
+ lsi4x4_in_0 = *valp & 0xf;
+ lsi4x4_out_0 = lsi4x4_in_0 << 2;
+ *valp = lsi4x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+ unsigned lsi4x4_in_0;
+ unsigned lsi4x4_out_0;
+ lsi4x4_out_0 = *valp;
+ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+ *valp = lsi4x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_out_0;
+ unsigned simm7_in_0;
+ simm7_in_0 = *valp & 0x7f;
+ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+ *valp = simm7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+ unsigned simm7_in_0;
+ unsigned simm7_out_0;
+ simm7_out_0 = *valp;
+ simm7_in_0 = (simm7_out_0 & 0x7f);
+ *valp = simm7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_out_0;
+ unsigned uimm6_in_0;
+ uimm6_in_0 = *valp & 0x3f;
+ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+ *valp = uimm6_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+ unsigned uimm6_in_0;
+ unsigned uimm6_out_0;
+ uimm6_out_0 = *valp;
+ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+ *valp = uimm6_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_out_0;
+ unsigned ai4const_in_0;
+ ai4const_in_0 = *valp & 0xf;
+ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+ *valp = ai4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+ unsigned ai4const_in_0;
+ unsigned ai4const_out_0;
+ ai4const_out_0 = *valp;
+ switch (ai4const_out_0)
+ {
+ case 0xffffffff: ai4const_in_0 = 0; break;
+ case 0x1: ai4const_in_0 = 0x1; break;
+ case 0x2: ai4const_in_0 = 0x2; break;
+ case 0x3: ai4const_in_0 = 0x3; break;
+ case 0x4: ai4const_in_0 = 0x4; break;
+ case 0x5: ai4const_in_0 = 0x5; break;
+ case 0x6: ai4const_in_0 = 0x6; break;
+ case 0x7: ai4const_in_0 = 0x7; break;
+ case 0x8: ai4const_in_0 = 0x8; break;
+ case 0x9: ai4const_in_0 = 0x9; break;
+ case 0xa: ai4const_in_0 = 0xa; break;
+ case 0xb: ai4const_in_0 = 0xb; break;
+ case 0xc: ai4const_in_0 = 0xc; break;
+ case 0xd: ai4const_in_0 = 0xd; break;
+ case 0xe: ai4const_in_0 = 0xe; break;
+ default: ai4const_in_0 = 0xf; break;
+ }
+ *valp = ai4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_out_0;
+ unsigned b4const_in_0;
+ b4const_in_0 = *valp & 0xf;
+ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+ *valp = b4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+ unsigned b4const_in_0;
+ unsigned b4const_out_0;
+ b4const_out_0 = *valp;
+ switch (b4const_out_0)
+ {
+ case 0xffffffff: b4const_in_0 = 0; break;
+ case 0x1: b4const_in_0 = 0x1; break;
+ case 0x2: b4const_in_0 = 0x2; break;
+ case 0x3: b4const_in_0 = 0x3; break;
+ case 0x4: b4const_in_0 = 0x4; break;
+ case 0x5: b4const_in_0 = 0x5; break;
+ case 0x6: b4const_in_0 = 0x6; break;
+ case 0x7: b4const_in_0 = 0x7; break;
+ case 0x8: b4const_in_0 = 0x8; break;
+ case 0xa: b4const_in_0 = 0x9; break;
+ case 0xc: b4const_in_0 = 0xa; break;
+ case 0x10: b4const_in_0 = 0xb; break;
+ case 0x20: b4const_in_0 = 0xc; break;
+ case 0x40: b4const_in_0 = 0xd; break;
+ case 0x80: b4const_in_0 = 0xe; break;
+ default: b4const_in_0 = 0xf; break;
+ }
+ *valp = b4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_out_0;
+ unsigned b4constu_in_0;
+ b4constu_in_0 = *valp & 0xf;
+ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+ *valp = b4constu_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+ unsigned b4constu_in_0;
+ unsigned b4constu_out_0;
+ b4constu_out_0 = *valp;
+ switch (b4constu_out_0)
+ {
+ case 0x8000: b4constu_in_0 = 0; break;
+ case 0x10000: b4constu_in_0 = 0x1; break;
+ case 0x2: b4constu_in_0 = 0x2; break;
+ case 0x3: b4constu_in_0 = 0x3; break;
+ case 0x4: b4constu_in_0 = 0x4; break;
+ case 0x5: b4constu_in_0 = 0x5; break;
+ case 0x6: b4constu_in_0 = 0x6; break;
+ case 0x7: b4constu_in_0 = 0x7; break;
+ case 0x8: b4constu_in_0 = 0x8; break;
+ case 0xa: b4constu_in_0 = 0x9; break;
+ case 0xc: b4constu_in_0 = 0xa; break;
+ case 0x10: b4constu_in_0 = 0xb; break;
+ case 0x20: b4constu_in_0 = 0xc; break;
+ case 0x40: b4constu_in_0 = 0xd; break;
+ case 0x80: b4constu_in_0 = 0xe; break;
+ default: b4constu_in_0 = 0xf; break;
+ }
+ *valp = b4constu_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_out_0;
+ unsigned uimm8_in_0;
+ uimm8_in_0 = *valp & 0xff;
+ uimm8_out_0 = uimm8_in_0;
+ *valp = uimm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+ unsigned uimm8_in_0;
+ unsigned uimm8_out_0;
+ uimm8_out_0 = *valp;
+ uimm8_in_0 = (uimm8_out_0 & 0xff);
+ *valp = uimm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_out_0;
+ unsigned uimm8x2_in_0;
+ uimm8x2_in_0 = *valp & 0xff;
+ uimm8x2_out_0 = uimm8x2_in_0 << 1;
+ *valp = uimm8x2_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+ unsigned uimm8x2_in_0;
+ unsigned uimm8x2_out_0;
+ uimm8x2_out_0 = *valp;
+ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+ *valp = uimm8x2_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_out_0;
+ unsigned uimm8x4_in_0;
+ uimm8x4_in_0 = *valp & 0xff;
+ uimm8x4_out_0 = uimm8x4_in_0 << 2;
+ *valp = uimm8x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+ unsigned uimm8x4_in_0;
+ unsigned uimm8x4_out_0;
+ uimm8x4_out_0 = *valp;
+ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+ *valp = uimm8x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_out_0;
+ unsigned uimm4x16_in_0;
+ uimm4x16_in_0 = *valp & 0xf;
+ uimm4x16_out_0 = uimm4x16_in_0 << 4;
+ *valp = uimm4x16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+ unsigned uimm4x16_in_0;
+ unsigned uimm4x16_out_0;
+ uimm4x16_out_0 = *valp;
+ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+ *valp = uimm4x16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
+{
+ unsigned uimmrx4_out_0;
+ unsigned uimmrx4_in_0;
+ uimmrx4_in_0 = *valp & 0xf;
+ uimmrx4_out_0 = uimmrx4_in_0 << 2;
+ *valp = uimmrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
+{
+ unsigned uimmrx4_in_0;
+ unsigned uimmrx4_out_0;
+ uimmrx4_out_0 = *valp;
+ uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
+ *valp = uimmrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_out_0;
+ unsigned simm8_in_0;
+ simm8_in_0 = *valp & 0xff;
+ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+ *valp = simm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+ unsigned simm8_in_0;
+ unsigned simm8_out_0;
+ simm8_out_0 = *valp;
+ simm8_in_0 = (simm8_out_0 & 0xff);
+ *valp = simm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_out_0;
+ unsigned simm8x256_in_0;
+ simm8x256_in_0 = *valp & 0xff;
+ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+ *valp = simm8x256_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+ unsigned simm8x256_in_0;
+ unsigned simm8x256_out_0;
+ simm8x256_out_0 = *valp;
+ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+ *valp = simm8x256_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_out_0;
+ unsigned simm12b_in_0;
+ simm12b_in_0 = *valp & 0xfff;
+ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+ *valp = simm12b_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+ unsigned simm12b_in_0;
+ unsigned simm12b_out_0;
+ simm12b_out_0 = *valp;
+ simm12b_in_0 = (simm12b_out_0 & 0xfff);
+ *valp = simm12b_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_out_0;
+ unsigned msalp32_in_0;
+ msalp32_in_0 = *valp & 0x1f;
+ msalp32_out_0 = 0x20 - msalp32_in_0;
+ *valp = msalp32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+ unsigned msalp32_in_0;
+ unsigned msalp32_out_0;
+ msalp32_out_0 = *valp;
+ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+ *valp = msalp32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_out_0;
+ unsigned op2p1_in_0;
+ op2p1_in_0 = *valp & 0xf;
+ op2p1_out_0 = op2p1_in_0 + 0x1;
+ *valp = op2p1_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+ unsigned op2p1_in_0;
+ unsigned op2p1_out_0;
+ op2p1_out_0 = *valp;
+ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+ *valp = op2p1_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+ unsigned label8_out_0;
+ unsigned label8_in_0;
+ label8_in_0 = *valp & 0xff;
+ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+ *valp = label8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+ unsigned label8_in_0;
+ unsigned label8_out_0;
+ label8_out_0 = *valp;
+ label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+ *valp = label8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_out_0;
+ unsigned ulabel8_in_0;
+ ulabel8_in_0 = *valp & 0xff;
+ ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+ *valp = ulabel8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+ unsigned ulabel8_in_0;
+ unsigned ulabel8_out_0;
+ ulabel8_out_0 = *valp;
+ ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+ *valp = ulabel8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+ unsigned label12_out_0;
+ unsigned label12_in_0;
+ label12_in_0 = *valp & 0xfff;
+ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+ *valp = label12_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+ unsigned label12_in_0;
+ unsigned label12_out_0;
+ label12_out_0 = *valp;
+ label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+ *valp = label12_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_out_0;
+ unsigned soffset_in_0;
+ soffset_in_0 = *valp & 0x3ffff;
+ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+ *valp = soffset_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+ unsigned soffset_in_0;
+ unsigned soffset_out_0;
+ soffset_out_0 = *valp;
+ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+ *valp = soffset_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_out_0;
+ unsigned uimm16x4_in_0;
+ uimm16x4_in_0 = *valp & 0xffff;
+ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+ *valp = uimm16x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+ unsigned uimm16x4_in_0;
+ unsigned uimm16x4_out_0;
+ uimm16x4_out_0 = *valp;
+ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+ *valp = uimm16x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+ unsigned bbi_out_0;
+ unsigned bbi_in_0;
+ bbi_in_0 = *valp & 0x1f;
+ bbi_out_0 = (0 << 5) | bbi_in_0;
+ *valp = bbi_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+ unsigned bbi_in_0;
+ unsigned bbi_out_0;
+ bbi_out_0 = *valp;
+ bbi_in_0 = (bbi_out_0 & 0x1f);
+ *valp = bbi_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+ unsigned s_out_0;
+ unsigned s_in_0;
+ s_in_0 = *valp & 0xf;
+ s_out_0 = (0 << 4) | s_in_0;
+ *valp = s_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+ unsigned s_in_0;
+ unsigned s_out_0;
+ s_out_0 = *valp;
+ s_in_0 = (s_out_0 & 0xf);
+ *valp = s_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_encode (uint32 *valp)
+{
+ return (*valp >= 4);
+}
+
+static int
+OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
+{
+ return (*valp >= 4);
+}
+
+static int
+OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
+{
+ return (*valp >= 4);
+}
+
+static int
+OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
+{
+ return (*valp >= 4);
+}
+
+static int
+OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
+{
+ return (*valp >= 4);
+}
+
+static int
+OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
+{
+ return (*valp >= 4);
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+ unsigned immt_out_0;
+ unsigned immt_in_0;
+ immt_in_0 = *valp & 0xf;
+ immt_out_0 = immt_in_0;
+ *valp = immt_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+ unsigned immt_in_0;
+ unsigned immt_out_0;
+ immt_out_0 = *valp;
+ immt_in_0 = immt_out_0 & 0xf;
+ *valp = immt_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_out_0;
+ unsigned tp7_in_0;
+ tp7_in_0 = *valp & 0xf;
+ tp7_out_0 = tp7_in_0 + 0x7;
+ *valp = tp7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+ unsigned tp7_in_0;
+ unsigned tp7_out_0;
+ tp7_out_0 = *valp;
+ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+ *valp = tp7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_out_0;
+ unsigned xt_wbr15_label_in_0;
+ xt_wbr15_label_in_0 = *valp & 0x7fff;
+ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+ *valp = xt_wbr15_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_in_0;
+ unsigned xt_wbr15_label_out_0;
+ xt_wbr15_label_out_0 = *valp;
+ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_out_0;
+ unsigned xt_wbr18_label_in_0;
+ xt_wbr18_label_in_0 = *valp & 0x3ffff;
+ xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
+ *valp = xt_wbr18_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_in_0;
+ unsigned xt_wbr18_label_out_0;
+ xt_wbr18_label_out_0 = *valp;
+ xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
+ *valp = xt_wbr18_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
+{
+ unsigned bitindex_out_0;
+ unsigned bitindex_in_0;
+ bitindex_in_0 = *valp & 0x1f;
+ bitindex_out_0 = (0 << 5) | bitindex_in_0;
+ *valp = bitindex_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
+{
+ unsigned bitindex_in_0;
+ unsigned bitindex_out_0;
+ bitindex_out_0 = *valp;
+ bitindex_in_0 = (bitindex_out_0 & 0x1f);
+ *valp = bitindex_in_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+ 0, 0 },
+ { "uimmrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "bbi", FIELD_bbi, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sae", FIELD_sae, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sas", FIELD_sas, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "s", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+ 0, 0 },
+ { "mx", FIELD_x, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
+ 0, 0 },
+ { "my", FIELD_y, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
+ 0, 0 },
+ { "mw", FIELD_w, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
+ 0, 0 },
+ { "mr0", FIELD__mr0, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
+ 0, 0 },
+ { "mr1", FIELD__mr1, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
+ 0, 0 },
+ { "mr2", FIELD__mr2, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
+ 0, 0 },
+ { "mr3", FIELD__mr3, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "bitindex", FIELD_bitindex, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
+ 0, 0 },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
+ { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
+ { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
+ { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
+ { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
+ { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
+ { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_uimmrx4,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_ulabel8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_bbi,
+ OPERAND_sae,
+ OPERAND_sas,
+ OPERAND_sargt,
+ OPERAND_s,
+ OPERAND_mx,
+ OPERAND_my,
+ OPERAND_mw,
+ OPERAND_mr0,
+ OPERAND_mr1,
+ OPERAND_mr2,
+ OPERAND_mr3,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_bitindex,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sal,
+ OPERAND_sas4,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_r3,
+ OPERAND_rbit2,
+ OPERAND_rhi,
+ OPERAND_t3,
+ OPERAND_tbit2,
+ OPERAND_tlo,
+ OPERAND_w,
+ OPERAND_y,
+ OPERAND_x,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_s3to1
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+ { { STATE_ERI_RAW_INTERLOCK }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+ INTERFACE_ERI_RD_In,
+ INTERFACE_ERI_RD_Out
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+ { { STATE_ERI_RAW_INTERLOCK }, 'o' }
+};
+
+static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
+ INTERFACE_ERI_WR_In,
+ INTERFACE_ERI_WR_Out
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32nb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid1_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_aa_args,
+ 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_ad_args,
+ 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_da_args,
+ 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_dd_args,
+ 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_aa_args,
+ 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_ad_args,
+ 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_da_args,
+ 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_dd_args,
+ 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_da_args,
+ 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_dd_args,
+ 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_l_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m3_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acclo_args,
+ 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acclo_args,
+ 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acclo_args,
+ 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acchi_args,
+ 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acchi_args,
+ 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acchi_args,
+ 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_lddr32_p_args,
+ 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sddr32_p_args,
+ 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_lock_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_dcache_dyn_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_lock_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rer_args,
+ 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+ { 2, Iclass_xt_iclass_wer_args,
+ 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
+ { 1, Iclass_rur_expstate_args,
+ 1, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 1, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_loop,
+ ICLASS_xt_iclass_loopz,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s32nb,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_lend,
+ ICLASS_xt_iclass_wsr_lend,
+ ICLASS_xt_iclass_xsr_lend,
+ ICLASS_xt_iclass_rsr_lcount,
+ ICLASS_xt_iclass_wsr_lcount,
+ ICLASS_xt_iclass_xsr_lcount,
+ ICLASS_xt_iclass_rsr_lbeg,
+ ICLASS_xt_iclass_wsr_lbeg,
+ ICLASS_xt_iclass_xsr_lbeg,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_memctl,
+ ICLASS_xt_iclass_wsr_memctl,
+ ICLASS_xt_iclass_xsr_memctl,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_configid0,
+ ICLASS_xt_iclass_wsr_configid0,
+ ICLASS_xt_iclass_rsr_configid1,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_epc3,
+ ICLASS_xt_iclass_wsr_epc3,
+ ICLASS_xt_iclass_xsr_epc3,
+ ICLASS_xt_iclass_rsr_excsave3,
+ ICLASS_xt_iclass_wsr_excsave3,
+ ICLASS_xt_iclass_xsr_excsave3,
+ ICLASS_xt_iclass_rsr_epc4,
+ ICLASS_xt_iclass_wsr_epc4,
+ ICLASS_xt_iclass_xsr_epc4,
+ ICLASS_xt_iclass_rsr_excsave4,
+ ICLASS_xt_iclass_wsr_excsave4,
+ ICLASS_xt_iclass_xsr_excsave4,
+ ICLASS_xt_iclass_rsr_epc5,
+ ICLASS_xt_iclass_wsr_epc5,
+ ICLASS_xt_iclass_xsr_epc5,
+ ICLASS_xt_iclass_rsr_excsave5,
+ ICLASS_xt_iclass_wsr_excsave5,
+ ICLASS_xt_iclass_xsr_excsave5,
+ ICLASS_xt_iclass_rsr_epc6,
+ ICLASS_xt_iclass_wsr_epc6,
+ ICLASS_xt_iclass_xsr_epc6,
+ ICLASS_xt_iclass_rsr_excsave6,
+ ICLASS_xt_iclass_wsr_excsave6,
+ ICLASS_xt_iclass_xsr_excsave6,
+ ICLASS_xt_iclass_rsr_epc7,
+ ICLASS_xt_iclass_wsr_epc7,
+ ICLASS_xt_iclass_xsr_epc7,
+ ICLASS_xt_iclass_rsr_excsave7,
+ ICLASS_xt_iclass_wsr_excsave7,
+ ICLASS_xt_iclass_xsr_excsave7,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_eps3,
+ ICLASS_xt_iclass_wsr_eps3,
+ ICLASS_xt_iclass_xsr_eps3,
+ ICLASS_xt_iclass_rsr_eps4,
+ ICLASS_xt_iclass_wsr_eps4,
+ ICLASS_xt_iclass_xsr_eps4,
+ ICLASS_xt_iclass_rsr_eps5,
+ ICLASS_xt_iclass_wsr_eps5,
+ ICLASS_xt_iclass_xsr_eps5,
+ ICLASS_xt_iclass_rsr_eps6,
+ ICLASS_xt_iclass_wsr_eps6,
+ ICLASS_xt_iclass_xsr_eps6,
+ ICLASS_xt_iclass_rsr_eps7,
+ ICLASS_xt_iclass_wsr_eps7,
+ ICLASS_xt_iclass_xsr_eps7,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_iclass_mac16_aa,
+ ICLASS_xt_iclass_mac16_ad,
+ ICLASS_xt_iclass_mac16_da,
+ ICLASS_xt_iclass_mac16_dd,
+ ICLASS_xt_iclass_mac16a_aa,
+ ICLASS_xt_iclass_mac16a_ad,
+ ICLASS_xt_iclass_mac16a_da,
+ ICLASS_xt_iclass_mac16a_dd,
+ ICLASS_xt_iclass_mac16al_da,
+ ICLASS_xt_iclass_mac16al_dd,
+ ICLASS_xt_iclass_mac16_l,
+ ICLASS_xt_iclass_rsr_m0,
+ ICLASS_xt_iclass_wsr_m0,
+ ICLASS_xt_iclass_xsr_m0,
+ ICLASS_xt_iclass_rsr_m1,
+ ICLASS_xt_iclass_wsr_m1,
+ ICLASS_xt_iclass_xsr_m1,
+ ICLASS_xt_iclass_rsr_m2,
+ ICLASS_xt_iclass_wsr_m2,
+ ICLASS_xt_iclass_xsr_m2,
+ ICLASS_xt_iclass_rsr_m3,
+ ICLASS_xt_iclass_wsr_m3,
+ ICLASS_xt_iclass_xsr_m3,
+ ICLASS_xt_iclass_rsr_acclo,
+ ICLASS_xt_iclass_wsr_acclo,
+ ICLASS_xt_iclass_xsr_acclo,
+ ICLASS_xt_iclass_rsr_acchi,
+ ICLASS_xt_iclass_wsr_acchi,
+ ICLASS_xt_iclass_xsr_acchi,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_dbreaka0,
+ ICLASS_xt_iclass_wsr_dbreaka0,
+ ICLASS_xt_iclass_xsr_dbreaka0,
+ ICLASS_xt_iclass_rsr_dbreakc0,
+ ICLASS_xt_iclass_wsr_dbreakc0,
+ ICLASS_xt_iclass_xsr_dbreakc0,
+ ICLASS_xt_iclass_rsr_dbreaka1,
+ ICLASS_xt_iclass_wsr_dbreaka1,
+ ICLASS_xt_iclass_xsr_dbreaka1,
+ ICLASS_xt_iclass_rsr_dbreakc1,
+ ICLASS_xt_iclass_wsr_dbreakc1,
+ ICLASS_xt_iclass_xsr_dbreakc1,
+ ICLASS_xt_iclass_rsr_ibreaka0,
+ ICLASS_xt_iclass_wsr_ibreaka0,
+ ICLASS_xt_iclass_xsr_ibreaka0,
+ ICLASS_xt_iclass_rsr_ibreaka1,
+ ICLASS_xt_iclass_wsr_ibreaka1,
+ ICLASS_xt_iclass_xsr_ibreaka1,
+ ICLASS_xt_iclass_rsr_ibreakenable,
+ ICLASS_xt_iclass_wsr_ibreakenable,
+ ICLASS_xt_iclass_xsr_ibreakenable,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_lddr32_p,
+ ICLASS_xt_iclass_sddr32_p,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_wsr_mmid,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_rsr_ccompare2,
+ ICLASS_xt_iclass_wsr_ccompare2,
+ ICLASS_xt_iclass_xsr_ccompare2,
+ ICLASS_xt_iclass_icache,
+ ICLASS_xt_iclass_icache_lock,
+ ICLASS_xt_iclass_icache_inv,
+ ICLASS_xt_iclass_licx,
+ ICLASS_xt_iclass_sicx,
+ ICLASS_xt_iclass_dcache,
+ ICLASS_xt_iclass_dcache_dyn,
+ ICLASS_xt_iclass_dcache_ind,
+ ICLASS_xt_iclass_dcache_inv,
+ ICLASS_xt_iclass_dpf,
+ ICLASS_xt_iclass_dcache_lock,
+ ICLASS_xt_iclass_sdct,
+ ICLASS_xt_iclass_ldct,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_clamp,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_div,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_expstate,
+ ICLASS_wur_expstate,
+ ICLASS_iclass_READ_IMPWIRE,
+ ICLASS_iclass_SETB_EXPSTATE,
+ ICLASS_iclass_CLRB_EXPSTATE,
+ ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70c2;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e2;
+}
+
+static void
+Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70d2;
+}
+
+static void
+Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270d2;
+}
+
+static void
+Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370d2;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f2;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf10000;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf12000;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11000;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13000;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7042;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7052;
+}
+
+static void
+Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf7082;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x47082;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x57082;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7062;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7072;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7002;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7012;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7022;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7032;
+}
+
+static void
+Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7082;
+}
+
+static void
+Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x27082;
+}
+
+static void
+Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x37082;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf19000;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf18000;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe2000;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+ Opcode_s32nb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+ Opcode_rsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+ Opcode_wsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+ Opcode_xsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+ Opcode_rsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+ Opcode_wsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+ Opcode_rsr_configid1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+ Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+ Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+ Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+ Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+ Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+ Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+ Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+ Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+ Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+ Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+ Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+ Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+ Opcode_mul_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+ Opcode_mul_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+ Opcode_mul_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+ Opcode_mul_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+ Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+ Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+ Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+ Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+ Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+ Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+ Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+ Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+ Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+ Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+ Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+ Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+ Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+ Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+ Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+ Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+ Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+ Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+ Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+ Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+ Opcode_mula_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+ Opcode_mula_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+ Opcode_mula_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+ Opcode_mula_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+ Opcode_muls_da_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+ Opcode_muls_da_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+ Opcode_muls_da_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+ Opcode_muls_da_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+ Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+ Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+ Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+ Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+ Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+ Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+ Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+ Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+ Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+ Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+ Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+ Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+ Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+ Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+ Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+ Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+ Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+ Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+ Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+ Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+ Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+ Opcode_lddec_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+ Opcode_ldinc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+ Opcode_rsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+ Opcode_wsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+ Opcode_xsr_m0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+ Opcode_rsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+ Opcode_wsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+ Opcode_xsr_m1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+ Opcode_rsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+ Opcode_wsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+ Opcode_xsr_m2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+ Opcode_rsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+ Opcode_wsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+ Opcode_xsr_m3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+ Opcode_rsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+ Opcode_wsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+ Opcode_xsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+ Opcode_rsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+ Opcode_wsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+ Opcode_xsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+ Opcode_lddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+ Opcode_sddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
+ Opcode_ipfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
+ Opcode_ihu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
+ Opcode_iiu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
+ Opcode_diwbui_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
+ Opcode_dpfl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
+ Opcode_dhu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
+ Opcode_diu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+
+
+
+\f
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", ICLASS_xt_iclass_loop,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s32nb", ICLASS_xt_iclass_s32nb,
+ 0,
+ Opcode_s32nb_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+ 0,
+ Opcode_rsr_memctl_encode_fns, 0, 0 },
+ { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+ 0,
+ Opcode_wsr_memctl_encode_fns, 0, 0 },
+ { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+ 0,
+ Opcode_xsr_memctl_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+ 0,
+ Opcode_rsr_configid0_encode_fns, 0, 0 },
+ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+ 0,
+ Opcode_wsr_configid0_encode_fns, 0, 0 },
+ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+ 0,
+ Opcode_rsr_configid1_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_ll_encode_fns, 0, 0 },
+ { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hl_encode_fns, 0, 0 },
+ { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_lh_encode_fns, 0, 0 },
+ { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hh_encode_fns, 0, 0 },
+ { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_ll_encode_fns, 0, 0 },
+ { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hl_encode_fns, 0, 0 },
+ { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_lh_encode_fns, 0, 0 },
+ { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hh_encode_fns, 0, 0 },
+ { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_ll_encode_fns, 0, 0 },
+ { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hl_encode_fns, 0, 0 },
+ { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_lh_encode_fns, 0, 0 },
+ { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hh_encode_fns, 0, 0 },
+ { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_ll_encode_fns, 0, 0 },
+ { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hl_encode_fns, 0, 0 },
+ { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_lh_encode_fns, 0, 0 },
+ { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hh_encode_fns, 0, 0 },
+ { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_ll_encode_fns, 0, 0 },
+ { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hl_encode_fns, 0, 0 },
+ { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_lh_encode_fns, 0, 0 },
+ { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hh_encode_fns, 0, 0 },
+ { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_ll_encode_fns, 0, 0 },
+ { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hl_encode_fns, 0, 0 },
+ { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_lh_encode_fns, 0, 0 },
+ { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hh_encode_fns, 0, 0 },
+ { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_ll_encode_fns, 0, 0 },
+ { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hl_encode_fns, 0, 0 },
+ { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_lh_encode_fns, 0, 0 },
+ { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hh_encode_fns, 0, 0 },
+ { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_ll_encode_fns, 0, 0 },
+ { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hl_encode_fns, 0, 0 },
+ { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_lh_encode_fns, 0, 0 },
+ { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hh_encode_fns, 0, 0 },
+ { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_ll_encode_fns, 0, 0 },
+ { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hl_encode_fns, 0, 0 },
+ { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_lh_encode_fns, 0, 0 },
+ { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hh_encode_fns, 0, 0 },
+ { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_ll_encode_fns, 0, 0 },
+ { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hl_encode_fns, 0, 0 },
+ { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_lh_encode_fns, 0, 0 },
+ { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hh_encode_fns, 0, 0 },
+ { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_ll_encode_fns, 0, 0 },
+ { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hl_encode_fns, 0, 0 },
+ { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_lh_encode_fns, 0, 0 },
+ { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hh_encode_fns, 0, 0 },
+ { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_ll_encode_fns, 0, 0 },
+ { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hl_encode_fns, 0, 0 },
+ { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_lh_encode_fns, 0, 0 },
+ { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hh_encode_fns, 0, 0 },
+ { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_ll_encode_fns, 0, 0 },
+ { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hl_encode_fns, 0, 0 },
+ { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_lh_encode_fns, 0, 0 },
+ { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hh_encode_fns, 0, 0 },
+ { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+ { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+ { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+ { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+ { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+ { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+ { "lddec", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_lddec_encode_fns, 0, 0 },
+ { "ldinc", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_ldinc_encode_fns, 0, 0 },
+ { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
+ 0,
+ Opcode_rsr_m0_encode_fns, 0, 0 },
+ { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
+ 0,
+ Opcode_wsr_m0_encode_fns, 0, 0 },
+ { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
+ 0,
+ Opcode_xsr_m0_encode_fns, 0, 0 },
+ { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
+ 0,
+ Opcode_rsr_m1_encode_fns, 0, 0 },
+ { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
+ 0,
+ Opcode_wsr_m1_encode_fns, 0, 0 },
+ { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
+ 0,
+ Opcode_xsr_m1_encode_fns, 0, 0 },
+ { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
+ 0,
+ Opcode_rsr_m2_encode_fns, 0, 0 },
+ { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
+ 0,
+ Opcode_wsr_m2_encode_fns, 0, 0 },
+ { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
+ 0,
+ Opcode_xsr_m2_encode_fns, 0, 0 },
+ { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
+ 0,
+ Opcode_rsr_m3_encode_fns, 0, 0 },
+ { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
+ 0,
+ Opcode_wsr_m3_encode_fns, 0, 0 },
+ { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
+ 0,
+ Opcode_xsr_m3_encode_fns, 0, 0 },
+ { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
+ 0,
+ Opcode_rsr_acclo_encode_fns, 0, 0 },
+ { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
+ 0,
+ Opcode_wsr_acclo_encode_fns, 0, 0 },
+ { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
+ 0,
+ Opcode_xsr_acclo_encode_fns, 0, 0 },
+ { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
+ 0,
+ Opcode_rsr_acchi_encode_fns, 0, 0 },
+ { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
+ 0,
+ Opcode_wsr_acchi_encode_fns, 0, 0 },
+ { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
+ 0,
+ Opcode_xsr_acchi_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+ 0,
+ Opcode_lddr32_p_encode_fns, 0, 0 },
+ { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+ 0,
+ Opcode_sddr32_p_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "ipf", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "ipfl", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ipfl_encode_fns, 0, 0 },
+ { "ihu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ihu_encode_fns, 0, 0 },
+ { "iiu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_iiu_encode_fns, 0, 0 },
+ { "iii", ICLASS_xt_iclass_icache_inv,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
+ 0,
+ Opcode_diwbui_p_encode_fns, 0, 0 },
+ { "diwb", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "dpfl", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dpfl_encode_fns, 0, 0 },
+ { "dhu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dhu_encode_fns, 0, 0 },
+ { "diu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_diu_encode_fns, 0, 0 },
+ { "sdct", ICLASS_xt_iclass_sdct,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", ICLASS_xt_iclass_ldct,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "clamps", ICLASS_xt_iclass_clamp,
+ 0,
+ Opcode_clamps_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "quou", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.expstate", ICLASS_rur_expstate,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", ICLASS_wur_expstate,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_LOOP,
+ OPCODE_LOOPNEZ,
+ OPCODE_LOOPGTZ,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_SIMCALL,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S32NB,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_LEND,
+ OPCODE_WSR_LEND,
+ OPCODE_XSR_LEND,
+ OPCODE_RSR_LCOUNT,
+ OPCODE_WSR_LCOUNT,
+ OPCODE_XSR_LCOUNT,
+ OPCODE_RSR_LBEG,
+ OPCODE_WSR_LBEG,
+ OPCODE_XSR_LBEG,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_MEMCTL,
+ OPCODE_WSR_MEMCTL,
+ OPCODE_XSR_MEMCTL,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_CONFIGID0,
+ OPCODE_WSR_CONFIGID0,
+ OPCODE_RSR_CONFIGID1,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPC3,
+ OPCODE_WSR_EPC3,
+ OPCODE_XSR_EPC3,
+ OPCODE_RSR_EXCSAVE3,
+ OPCODE_WSR_EXCSAVE3,
+ OPCODE_XSR_EXCSAVE3,
+ OPCODE_RSR_EPC4,
+ OPCODE_WSR_EPC4,
+ OPCODE_XSR_EPC4,
+ OPCODE_RSR_EXCSAVE4,
+ OPCODE_WSR_EXCSAVE4,
+ OPCODE_XSR_EXCSAVE4,
+ OPCODE_RSR_EPC5,
+ OPCODE_WSR_EPC5,
+ OPCODE_XSR_EPC5,
+ OPCODE_RSR_EXCSAVE5,
+ OPCODE_WSR_EXCSAVE5,
+ OPCODE_XSR_EXCSAVE5,
+ OPCODE_RSR_EPC6,
+ OPCODE_WSR_EPC6,
+ OPCODE_XSR_EPC6,
+ OPCODE_RSR_EXCSAVE6,
+ OPCODE_WSR_EXCSAVE6,
+ OPCODE_XSR_EXCSAVE6,
+ OPCODE_RSR_EPC7,
+ OPCODE_WSR_EPC7,
+ OPCODE_XSR_EPC7,
+ OPCODE_RSR_EXCSAVE7,
+ OPCODE_WSR_EXCSAVE7,
+ OPCODE_XSR_EXCSAVE7,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EPS3,
+ OPCODE_WSR_EPS3,
+ OPCODE_XSR_EPS3,
+ OPCODE_RSR_EPS4,
+ OPCODE_WSR_EPS4,
+ OPCODE_XSR_EPS4,
+ OPCODE_RSR_EPS5,
+ OPCODE_WSR_EPS5,
+ OPCODE_XSR_EPS5,
+ OPCODE_RSR_EPS6,
+ OPCODE_WSR_EPS6,
+ OPCODE_XSR_EPS6,
+ OPCODE_RSR_EPS7,
+ OPCODE_WSR_EPS7,
+ OPCODE_XSR_EPS7,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_MUL_AA_LL,
+ OPCODE_MUL_AA_HL,
+ OPCODE_MUL_AA_LH,
+ OPCODE_MUL_AA_HH,
+ OPCODE_UMUL_AA_LL,
+ OPCODE_UMUL_AA_HL,
+ OPCODE_UMUL_AA_LH,
+ OPCODE_UMUL_AA_HH,
+ OPCODE_MUL_AD_LL,
+ OPCODE_MUL_AD_HL,
+ OPCODE_MUL_AD_LH,
+ OPCODE_MUL_AD_HH,
+ OPCODE_MUL_DA_LL,
+ OPCODE_MUL_DA_HL,
+ OPCODE_MUL_DA_LH,
+ OPCODE_MUL_DA_HH,
+ OPCODE_MUL_DD_LL,
+ OPCODE_MUL_DD_HL,
+ OPCODE_MUL_DD_LH,
+ OPCODE_MUL_DD_HH,
+ OPCODE_MULA_AA_LL,
+ OPCODE_MULA_AA_HL,
+ OPCODE_MULA_AA_LH,
+ OPCODE_MULA_AA_HH,
+ OPCODE_MULS_AA_LL,
+ OPCODE_MULS_AA_HL,
+ OPCODE_MULS_AA_LH,
+ OPCODE_MULS_AA_HH,
+ OPCODE_MULA_AD_LL,
+ OPCODE_MULA_AD_HL,
+ OPCODE_MULA_AD_LH,
+ OPCODE_MULA_AD_HH,
+ OPCODE_MULS_AD_LL,
+ OPCODE_MULS_AD_HL,
+ OPCODE_MULS_AD_LH,
+ OPCODE_MULS_AD_HH,
+ OPCODE_MULA_DA_LL,
+ OPCODE_MULA_DA_HL,
+ OPCODE_MULA_DA_LH,
+ OPCODE_MULA_DA_HH,
+ OPCODE_MULS_DA_LL,
+ OPCODE_MULS_DA_HL,
+ OPCODE_MULS_DA_LH,
+ OPCODE_MULS_DA_HH,
+ OPCODE_MULA_DD_LL,
+ OPCODE_MULA_DD_HL,
+ OPCODE_MULA_DD_LH,
+ OPCODE_MULA_DD_HH,
+ OPCODE_MULS_DD_LL,
+ OPCODE_MULS_DD_HL,
+ OPCODE_MULS_DD_LH,
+ OPCODE_MULS_DD_HH,
+ OPCODE_MULA_DA_LL_LDDEC,
+ OPCODE_MULA_DA_LL_LDINC,
+ OPCODE_MULA_DA_HL_LDDEC,
+ OPCODE_MULA_DA_HL_LDINC,
+ OPCODE_MULA_DA_LH_LDDEC,
+ OPCODE_MULA_DA_LH_LDINC,
+ OPCODE_MULA_DA_HH_LDDEC,
+ OPCODE_MULA_DA_HH_LDINC,
+ OPCODE_MULA_DD_LL_LDDEC,
+ OPCODE_MULA_DD_LL_LDINC,
+ OPCODE_MULA_DD_HL_LDDEC,
+ OPCODE_MULA_DD_HL_LDINC,
+ OPCODE_MULA_DD_LH_LDDEC,
+ OPCODE_MULA_DD_LH_LDINC,
+ OPCODE_MULA_DD_HH_LDDEC,
+ OPCODE_MULA_DD_HH_LDINC,
+ OPCODE_LDDEC,
+ OPCODE_LDINC,
+ OPCODE_RSR_M0,
+ OPCODE_WSR_M0,
+ OPCODE_XSR_M0,
+ OPCODE_RSR_M1,
+ OPCODE_WSR_M1,
+ OPCODE_XSR_M1,
+ OPCODE_RSR_M2,
+ OPCODE_WSR_M2,
+ OPCODE_XSR_M2,
+ OPCODE_RSR_M3,
+ OPCODE_WSR_M3,
+ OPCODE_XSR_M3,
+ OPCODE_RSR_ACCLO,
+ OPCODE_WSR_ACCLO,
+ OPCODE_XSR_ACCLO,
+ OPCODE_RSR_ACCHI,
+ OPCODE_WSR_ACCHI,
+ OPCODE_XSR_ACCHI,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DBREAKA0,
+ OPCODE_WSR_DBREAKA0,
+ OPCODE_XSR_DBREAKA0,
+ OPCODE_RSR_DBREAKC0,
+ OPCODE_WSR_DBREAKC0,
+ OPCODE_XSR_DBREAKC0,
+ OPCODE_RSR_DBREAKA1,
+ OPCODE_WSR_DBREAKA1,
+ OPCODE_XSR_DBREAKA1,
+ OPCODE_RSR_DBREAKC1,
+ OPCODE_WSR_DBREAKC1,
+ OPCODE_XSR_DBREAKC1,
+ OPCODE_RSR_IBREAKA0,
+ OPCODE_WSR_IBREAKA0,
+ OPCODE_XSR_IBREAKA0,
+ OPCODE_RSR_IBREAKA1,
+ OPCODE_WSR_IBREAKA1,
+ OPCODE_XSR_IBREAKA1,
+ OPCODE_RSR_IBREAKENABLE,
+ OPCODE_WSR_IBREAKENABLE,
+ OPCODE_XSR_IBREAKENABLE,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_LDDR32_P,
+ OPCODE_SDDR32_P,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_WSR_MMID,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_RSR_CCOMPARE2,
+ OPCODE_WSR_CCOMPARE2,
+ OPCODE_XSR_CCOMPARE2,
+ OPCODE_IPF,
+ OPCODE_IHI,
+ OPCODE_IPFL,
+ OPCODE_IHU,
+ OPCODE_IIU,
+ OPCODE_III,
+ OPCODE_LICT,
+ OPCODE_LICW,
+ OPCODE_SICT,
+ OPCODE_SICW,
+ OPCODE_DHWB,
+ OPCODE_DHWBI,
+ OPCODE_DIWBUI_P,
+ OPCODE_DIWB,
+ OPCODE_DIWBI,
+ OPCODE_DHI,
+ OPCODE_DII,
+ OPCODE_DPFR,
+ OPCODE_DPFW,
+ OPCODE_DPFRO,
+ OPCODE_DPFWO,
+ OPCODE_DPFL,
+ OPCODE_DHU,
+ OPCODE_DIU,
+ OPCODE_SDCT,
+ OPCODE_LDCT,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_CLAMPS,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_QUOU,
+ OPCODE_QUOS,
+ OPCODE_REMU,
+ OPCODE_REMS,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_EXPSTATE,
+ OPCODE_WUR_EXPSTATE,
+ OPCODE_READ_IMPWIRE,
+ OPCODE_SETB_EXPSTATE,
+ OPCODE_CLRB_EXPSTATE,
+ OPCODE_WRMSK_EXPSTATE
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_RET;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_RETW;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_JX;
+ }
+ if (Field_m_Slot_inst_get (insn) == 3)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALLX0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALLX4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALLX8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALLX12;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_MOVSP;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_ISYNC;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RSYNC;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_ESYNC;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DSYNC;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ return OPCODE_EXCW;
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_MEMW;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ return OPCODE_EXTW;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_NOP;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 3)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_RFE;
+ if (Field_s_Slot_inst_get (insn) == 2)
+ return OPCODE_RFDE;
+ if (Field_s_Slot_inst_get (insn) == 4)
+ return OPCODE_RFWO;
+ if (Field_s_Slot_inst_get (insn) == 5)
+ return OPCODE_RFWU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFI;
+ }
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BREAK;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ }
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RSIL;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_LDDR32_P;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_SDDR32_P;
+ }
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_OR;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_XOR;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RER;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_WER;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_NSA;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_NSAU;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_RITLB0;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_PITLB;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_WITLB;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_RITLB1;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_RDTLB0;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_PDTLB;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_WDTLB;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_RDTLB1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_NEG;
+ if (Field_s_Slot_inst_get (insn) == 1)
+ return OPCODE_ABS;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_ADD;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_ADDX2;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_ADDX4;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_ADDX8;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_SUB;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_SUBX2;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_SUBX4;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_SUBX8;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 1)
+ {
+ if ((Field_op2_Slot_inst_get (insn) == 0 ||
+ Field_op2_Slot_inst_get (insn) == 1))
+ return OPCODE_SLLI;
+ if ((Field_op2_Slot_inst_get (insn) == 2 ||
+ Field_op2_Slot_inst_get (insn) == 3))
+ return OPCODE_SRAI;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_SRLI;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_XSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_XSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_XSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_XSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_XSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_XSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_XSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_XSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_XSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_XSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_XSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_XSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_XSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_XSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_XSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_XSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_XSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_XSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_XSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_XSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_XSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_XSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_XSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_XSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_XSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_XSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_XSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_XSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_XSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_XSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_XSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_XSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_XSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_XSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_XSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_XSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_XSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_XSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_XSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_XSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_XSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_XSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_XSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_XSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_XSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_XSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_XSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_XSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_XSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_XSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_XSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_XSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_XSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_XSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_XSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_XSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_XSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_XSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_XSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_SRC;
+ if (Field_op2_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ if (Field_op2_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_op2_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MUL16U;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MUL16S;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_LICT;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_SICT;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_LICW;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_SICW;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LDCT;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_SDCT;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ }
+ }
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MULL;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_QUOU;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_QUOS;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_REMU;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_REMS;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_RSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_RSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_RSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_RSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_RSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_RSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_RSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_RSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_RSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_RSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_RSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_RSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_RSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_RSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_RSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_RSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_RSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_RSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_RSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_RSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_RSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_RSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_RSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_RSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_RSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_RSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_RSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_RSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_RSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_RSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_RSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_RSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_RSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_RSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_RSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_RSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_RSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_RSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_RSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 208)
+ return OPCODE_RSR_CONFIGID1;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_RSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_RSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_RSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_RSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_RSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_RSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_RSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_RSR_INTERRUPT;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_RSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_RSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_RSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_RSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_RSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_RSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 235)
+ return OPCODE_RSR_PRID;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_RSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_RSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_RSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_RSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_RSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_RSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_RSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_RSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_WSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_WSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_WSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_WSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_WSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_WSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_WSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_WSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_WSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_WSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_WSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_WSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_WSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_WSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 89)
+ return OPCODE_WSR_MMID;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_WSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_WSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_WSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_WSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_WSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_WSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_WSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_WSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_WSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_WSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_WSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_WSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_WSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_WSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_WSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_WSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_WSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_WSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_WSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_WSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_WSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_WSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_WSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_WSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_WSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_WSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_WSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_WSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_WSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_WSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_WSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_WSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_WSR_INTSET;
+ if (Field_sr_Slot_inst_get (insn) == 227)
+ return OPCODE_WSR_INTCLEAR;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_WSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_WSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_WSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_WSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_WSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_WSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_WSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_WSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_WSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_SEXT;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_CLAMPS;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_MIN;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_MAX;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_MINU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_MAXU;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MOVEQZ;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_MOVNEZ;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVLTZ;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MOVGEZ;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ {
+ if (Field_st_Slot_inst_get (insn) == 230)
+ return OPCODE_RUR_EXPSTATE;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WUR_EXPSTATE;
+ }
+ }
+ if ((Field_op1_Slot_inst_get (insn) == 4 ||
+ Field_op1_Slot_inst_get (insn) == 5))
+ return OPCODE_EXTUI;
+ if (Field_op1_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_L32E;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_S32E;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_S32NB;
+ }
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_READ_IMPWIRE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_SETB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_CLRB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_WRMSK_EXPSTATE;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 1)
+ return OPCODE_L32R;
+ if (Field_op0_Slot_inst_get (insn) == 2)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_L32I;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_S16I;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_S32I;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFR;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_DPFW;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_DPFRO;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DPFWO;
+ if (Field_t_Slot_inst_get (insn) == 4)
+ return OPCODE_DHWB;
+ if (Field_t_Slot_inst_get (insn) == 5)
+ return OPCODE_DHWBI;
+ if (Field_t_Slot_inst_get (insn) == 6)
+ return OPCODE_DHI;
+ if (Field_t_Slot_inst_get (insn) == 7)
+ return OPCODE_DII;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFL;
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ return OPCODE_DHU;
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ return OPCODE_DIU;
+ if (Field_op1_Slot_inst_get (insn) == 4)
+ return OPCODE_DIWB;
+ if (Field_op1_Slot_inst_get (insn) == 5)
+ return OPCODE_DIWBI;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_DIWBUI_P;
+ }
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_IPF;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ return OPCODE_IPFL;
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ return OPCODE_IHU;
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ return OPCODE_IIU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_IHI;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_III;
+ }
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVI;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_L32AI;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_S32C1I;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_S32RI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 4)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDDEC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDDEC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDDEC;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 5)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALL0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALL4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALL8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALL12;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 6)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_J;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQZ;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTZ;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEZ;
+ }
+ if (Field_n_Slot_inst_get (insn) == 2)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQI;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEI;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEI;
+ }
+ if (Field_n_Slot_inst_get (insn) == 3)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_ENTRY;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ {
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LOOP;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_LOOPNEZ;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_LOOPGTZ;
+ }
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTUI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEUI;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 7)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BALL;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_BBC;
+ if ((Field_r_Slot_inst_get (insn) == 6 ||
+ Field_r_Slot_inst_get (insn) == 7))
+ return OPCODE_BBCI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_BANY;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_BNE;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_BGE;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_BNALL;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_BBS;
+ if ((Field_r_Slot_inst_get (insn) == 14 ||
+ Field_r_Slot_inst_get (insn) == 15))
+ return OPCODE_BBSI;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16b_get (insn) == 12)
+ {
+ if (Field_i_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOVI_N;
+ if (Field_i_Slot_inst16b_get (insn) == 1)
+ {
+ if (Field_z_Slot_inst16b_get (insn) == 0)
+ return OPCODE_BEQZ_N;
+ if (Field_z_Slot_inst16b_get (insn) == 1)
+ return OPCODE_BNEZ_N;
+ }
+ }
+ if (Field_op0_Slot_inst16b_get (insn) == 13)
+ {
+ if (Field_r_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOV_N;
+ if (Field_r_Slot_inst16b_get (insn) == 15)
+ {
+ if (Field_t_Slot_inst16b_get (insn) == 0)
+ return OPCODE_RET_N;
+ if (Field_t_Slot_inst16b_get (insn) == 1)
+ return OPCODE_RETW_N;
+ if (Field_t_Slot_inst16b_get (insn) == 2)
+ return OPCODE_BREAK_N;
+ if (Field_t_Slot_inst16b_get (insn) == 3 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ if (Field_t_Slot_inst16b_get (insn) == 6 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ }
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16a_get (insn) == 8)
+ return OPCODE_L32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 9)
+ return OPCODE_S32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 10)
+ return OPCODE_ADD_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 11)
+ return OPCODE_ADDI_N;
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_get,
+ Field_rbit2_Slot_inst_get,
+ Field_rhi_Slot_inst_get,
+ Field_t3_Slot_inst_get,
+ Field_tbit2_Slot_inst_get,
+ Field_tlo_Slot_inst_get,
+ Field_w_Slot_inst_get,
+ Field_y_Slot_inst_get,
+ Field_x_Slot_inst_get,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_set,
+ Field_rbit2_Slot_inst_set,
+ Field_rhi_Slot_inst_set,
+ Field_t3_Slot_inst_set,
+ Field_tbit2_Slot_inst_set,
+ Field_tlo_Slot_inst_set,
+ Field_w_Slot_inst_set,
+ Field_y_Slot_inst_set,
+ Field_x_Slot_inst_set,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[256] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int l = insn[0];
+ return length_table[l];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 56 /* num_fields */,
+ 94, operands,
+ 313, iclasses,
+ 439, opcodes, 0,
+ 2, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 6, interfaces, 0,
+ 0, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
-
- Copyright (c) 2003-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#include "qemu/osdep.h"
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "ACCLO", 16, 0 },
- { "ACCHI", 17, 0 },
- { "M0", 32, 0 },
- { "M1", 33, 0 },
- { "M2", 34, 0 },
- { "M3", 35, 0 },
- { "MMID", 89, 0 },
- { "DDR", 104, 0 },
- { "CONFIGID0", 176, 0 },
- { "CONFIGID1", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EPC5", 181, 0 },
- { "EPC6", 182, 0 },
- { "EPC7", 183, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EXCSAVE5", 213, 0 },
- { "EXCSAVE6", 214, 0 },
- { "EXCSAVE7", 215, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EPS5", 197, 0 },
- { "EPS6", 198, 0 },
- { "EPS7", 199, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "SCOMPARE1", 12, 0 },
- { "ATOMCTL", 99, 0 },
- { "EXPSTATE", 230, 1 }
-};
-
-#define NUM_SYSREGS 64
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 230
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 22, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EPC5", 32, 0 },
- { "EPC6", 32, 0 },
- { "EPC7", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EXCSAVE5", 32, 0 },
- { "EXCSAVE6", 32, 0 },
- { "EXCSAVE7", 32, 0 },
- { "EPS2", 13, 0 },
- { "EPS3", 13, 0 },
- { "EPS4", 13, 0 },
- { "EPS5", 13, 0 },
- { "EPS6", 13, 0 },
- { "EPS7", 13, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 3, 0 },
- { "WindowStart", 8, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "ACC", 40, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 22, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "SCOMPARE1", 32, 0 },
- { "ATOMCTL", 6, 0 },
- { "ERI_RAW_INTERLOCK", 1, 0 },
- { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
-};
-
-#define NUM_STATES 64
-
-enum xtensa_state_id {
- STATE_LCOUNT,
- STATE_PC,
- STATE_ICOUNT,
- STATE_DDR,
- STATE_INTERRUPT,
- STATE_CCOUNT,
- STATE_XTSYNC,
- STATE_VECBASE,
- STATE_EPC1,
- STATE_EPC2,
- STATE_EPC3,
- STATE_EPC4,
- STATE_EPC5,
- STATE_EPC6,
- STATE_EPC7,
- STATE_EXCSAVE1,
- STATE_EXCSAVE2,
- STATE_EXCSAVE3,
- STATE_EXCSAVE4,
- STATE_EXCSAVE5,
- STATE_EXCSAVE6,
- STATE_EXCSAVE7,
- STATE_EPS2,
- STATE_EPS3,
- STATE_EPS4,
- STATE_EPS5,
- STATE_EPS6,
- STATE_EPS7,
- STATE_EXCCAUSE,
- STATE_PSINTLEVEL,
- STATE_PSUM,
- STATE_PSWOE,
- STATE_PSEXCM,
- STATE_DEPC,
- STATE_EXCVADDR,
- STATE_WindowBase,
- STATE_WindowStart,
- STATE_PSCALLINC,
- STATE_PSOWB,
- STATE_LBEG,
- STATE_LEND,
- STATE_SAR,
- STATE_MISC0,
- STATE_MISC1,
- STATE_ACC,
- STATE_InOCDMode,
- STATE_INTENABLE,
- STATE_DBREAKA0,
- STATE_DBREAKC0,
- STATE_DBREAKA1,
- STATE_DBREAKC1,
- STATE_IBREAKA0,
- STATE_IBREAKA1,
- STATE_IBREAKENABLE,
- STATE_ICOUNTLEVEL,
- STATE_DEBUGCAUSE,
- STATE_DBNUM,
- STATE_CCOMPARE0,
- STATE_CCOMPARE1,
- STATE_CCOMPARE2,
- STATE_SCOMPARE1,
- STATE_ATOMCTL,
- STATE_ERI_RAW_INTERLOCK,
- STATE_EXPSTATE
-};
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_w_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_y_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_x_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
- return tie_t;
-}
-
-static void
-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 17) >> 17;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-static unsigned
-Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 1;
-}
-
-static unsigned
-Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 2;
-}
-
-static unsigned
-Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 3;
-}
-
-enum xtensa_field_id {
- FIELD_t,
- FIELD_bbi4,
- FIELD_bbi,
- FIELD_imm12,
- FIELD_imm8,
- FIELD_s,
- FIELD_imm12b,
- FIELD_imm16,
- FIELD_m,
- FIELD_n,
- FIELD_offset,
- FIELD_op0,
- FIELD_op1,
- FIELD_op2,
- FIELD_r,
- FIELD_sa4,
- FIELD_sae4,
- FIELD_sae,
- FIELD_sal,
- FIELD_sargt,
- FIELD_sas4,
- FIELD_sas,
- FIELD_sr,
- FIELD_st,
- FIELD_thi3,
- FIELD_imm4,
- FIELD_mn,
- FIELD_i,
- FIELD_imm6lo,
- FIELD_imm6hi,
- FIELD_imm7lo,
- FIELD_imm7hi,
- FIELD_z,
- FIELD_imm6,
- FIELD_imm7,
- FIELD_r3,
- FIELD_rbit2,
- FIELD_rhi,
- FIELD_t3,
- FIELD_tbit2,
- FIELD_tlo,
- FIELD_w,
- FIELD_y,
- FIELD_x,
- FIELD_xt_wbr15_imm,
- FIELD_xt_wbr18_imm,
- FIELD_bitindex,
- FIELD_s3to1,
- FIELD__ar0,
- FIELD__ar4,
- FIELD__ar8,
- FIELD__ar12,
- FIELD__mr0,
- FIELD__mr1,
- FIELD__mr2,
- FIELD__mr3
-};
-
-\f
-/* Functional units. */
-
-#define funcUnits 0
-
-\f
-/* Register files. */
-
-enum xtensa_regfile_id {
- REGFILE_AR,
- REGFILE_MR
-};
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", REGFILE_AR, 32, 32 },
- { "MR", "m", REGFILE_MR, 32, 4 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
- { "ERI_RD_Out", 14, 0, 0, 'o' },
- { "ERI_RD_In", 32, 0, 1, 'i' },
- { "ERI_RD_Rdy", 1, 0, 0, 'i' },
- { "ERI_WR_Out", 46, 0, 2, 'o' },
- { "ERI_WR_In", 1, 0, 3, 'i' },
- { "IMPWIRE", 32, 0, 4, 'i' }
-};
-
-enum xtensa_interface_id {
- INTERFACE_ERI_RD_Out,
- INTERFACE_ERI_RD_In,
- INTERFACE_ERI_RD_Rdy,
- INTERFACE_ERI_WR_Out,
- INTERFACE_ERI_WR_In,
- INTERFACE_IMPWIRE
-};
-
-
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
-{
- *valp += 2;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
-{
- int error;
- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
- *valp = *valp & 1;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_out_0;
- unsigned soffsetx4_in_0;
- soffsetx4_in_0 = *valp & 0x3ffff;
- soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
- *valp = soffsetx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
-{
- unsigned soffsetx4_in_0;
- unsigned soffsetx4_out_0;
- soffsetx4_out_0 = *valp;
- soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
- *valp = soffsetx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_out_0;
- unsigned uimm12x8_in_0;
- uimm12x8_in_0 = *valp & 0xfff;
- uimm12x8_out_0 = uimm12x8_in_0 << 3;
- *valp = uimm12x8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
-{
- unsigned uimm12x8_in_0;
- unsigned uimm12x8_out_0;
- uimm12x8_out_0 = *valp;
- uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
- *valp = uimm12x8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_decode (uint32 *valp)
-{
- unsigned simm4_out_0;
- unsigned simm4_in_0;
- simm4_in_0 = *valp & 0xf;
- simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
- *valp = simm4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_encode (uint32 *valp)
-{
- unsigned simm4_in_0;
- unsigned simm4_out_0;
- simm4_out_0 = *valp;
- simm4_in_0 = (simm4_out_0 & 0xf);
- *valp = simm4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_out_0;
- unsigned immrx4_in_0;
- immrx4_in_0 = *valp & 0xf;
- immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
- *valp = immrx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
-{
- unsigned immrx4_in_0;
- unsigned immrx4_out_0;
- immrx4_out_0 = *valp;
- immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
- *valp = immrx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_out_0;
- unsigned lsi4x4_in_0;
- lsi4x4_in_0 = *valp & 0xf;
- lsi4x4_out_0 = lsi4x4_in_0 << 2;
- *valp = lsi4x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
-{
- unsigned lsi4x4_in_0;
- unsigned lsi4x4_out_0;
- lsi4x4_out_0 = *valp;
- lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
- *valp = lsi4x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_decode (uint32 *valp)
-{
- unsigned simm7_out_0;
- unsigned simm7_in_0;
- simm7_in_0 = *valp & 0x7f;
- simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
- *valp = simm7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_encode (uint32 *valp)
-{
- unsigned simm7_in_0;
- unsigned simm7_out_0;
- simm7_out_0 = *valp;
- simm7_in_0 = (simm7_out_0 & 0x7f);
- *valp = simm7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_out_0;
- unsigned uimm6_in_0;
- uimm6_in_0 = *valp & 0x3f;
- uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
- *valp = uimm6_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
-{
- unsigned uimm6_in_0;
- unsigned uimm6_out_0;
- uimm6_out_0 = *valp;
- uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
- *valp = uimm6_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_out_0;
- unsigned ai4const_in_0;
- ai4const_in_0 = *valp & 0xf;
- ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
- *valp = ai4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
-{
- unsigned ai4const_in_0;
- unsigned ai4const_out_0;
- ai4const_out_0 = *valp;
- switch (ai4const_out_0)
- {
- case 0xffffffff: ai4const_in_0 = 0; break;
- case 0x1: ai4const_in_0 = 0x1; break;
- case 0x2: ai4const_in_0 = 0x2; break;
- case 0x3: ai4const_in_0 = 0x3; break;
- case 0x4: ai4const_in_0 = 0x4; break;
- case 0x5: ai4const_in_0 = 0x5; break;
- case 0x6: ai4const_in_0 = 0x6; break;
- case 0x7: ai4const_in_0 = 0x7; break;
- case 0x8: ai4const_in_0 = 0x8; break;
- case 0x9: ai4const_in_0 = 0x9; break;
- case 0xa: ai4const_in_0 = 0xa; break;
- case 0xb: ai4const_in_0 = 0xb; break;
- case 0xc: ai4const_in_0 = 0xc; break;
- case 0xd: ai4const_in_0 = 0xd; break;
- case 0xe: ai4const_in_0 = 0xe; break;
- default: ai4const_in_0 = 0xf; break;
- }
- *valp = ai4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_decode (uint32 *valp)
-{
- unsigned b4const_out_0;
- unsigned b4const_in_0;
- b4const_in_0 = *valp & 0xf;
- b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
- *valp = b4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_encode (uint32 *valp)
-{
- unsigned b4const_in_0;
- unsigned b4const_out_0;
- b4const_out_0 = *valp;
- switch (b4const_out_0)
- {
- case 0xffffffff: b4const_in_0 = 0; break;
- case 0x1: b4const_in_0 = 0x1; break;
- case 0x2: b4const_in_0 = 0x2; break;
- case 0x3: b4const_in_0 = 0x3; break;
- case 0x4: b4const_in_0 = 0x4; break;
- case 0x5: b4const_in_0 = 0x5; break;
- case 0x6: b4const_in_0 = 0x6; break;
- case 0x7: b4const_in_0 = 0x7; break;
- case 0x8: b4const_in_0 = 0x8; break;
- case 0xa: b4const_in_0 = 0x9; break;
- case 0xc: b4const_in_0 = 0xa; break;
- case 0x10: b4const_in_0 = 0xb; break;
- case 0x20: b4const_in_0 = 0xc; break;
- case 0x40: b4const_in_0 = 0xd; break;
- case 0x80: b4const_in_0 = 0xe; break;
- default: b4const_in_0 = 0xf; break;
- }
- *valp = b4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_out_0;
- unsigned b4constu_in_0;
- b4constu_in_0 = *valp & 0xf;
- b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
- *valp = b4constu_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
-{
- unsigned b4constu_in_0;
- unsigned b4constu_out_0;
- b4constu_out_0 = *valp;
- switch (b4constu_out_0)
- {
- case 0x8000: b4constu_in_0 = 0; break;
- case 0x10000: b4constu_in_0 = 0x1; break;
- case 0x2: b4constu_in_0 = 0x2; break;
- case 0x3: b4constu_in_0 = 0x3; break;
- case 0x4: b4constu_in_0 = 0x4; break;
- case 0x5: b4constu_in_0 = 0x5; break;
- case 0x6: b4constu_in_0 = 0x6; break;
- case 0x7: b4constu_in_0 = 0x7; break;
- case 0x8: b4constu_in_0 = 0x8; break;
- case 0xa: b4constu_in_0 = 0x9; break;
- case 0xc: b4constu_in_0 = 0xa; break;
- case 0x10: b4constu_in_0 = 0xb; break;
- case 0x20: b4constu_in_0 = 0xc; break;
- case 0x40: b4constu_in_0 = 0xd; break;
- case 0x80: b4constu_in_0 = 0xe; break;
- default: b4constu_in_0 = 0xf; break;
- }
- *valp = b4constu_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_out_0;
- unsigned uimm8_in_0;
- uimm8_in_0 = *valp & 0xff;
- uimm8_out_0 = uimm8_in_0;
- *valp = uimm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
-{
- unsigned uimm8_in_0;
- unsigned uimm8_out_0;
- uimm8_out_0 = *valp;
- uimm8_in_0 = (uimm8_out_0 & 0xff);
- *valp = uimm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_out_0;
- unsigned uimm8x2_in_0;
- uimm8x2_in_0 = *valp & 0xff;
- uimm8x2_out_0 = uimm8x2_in_0 << 1;
- *valp = uimm8x2_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
-{
- unsigned uimm8x2_in_0;
- unsigned uimm8x2_out_0;
- uimm8x2_out_0 = *valp;
- uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
- *valp = uimm8x2_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_out_0;
- unsigned uimm8x4_in_0;
- uimm8x4_in_0 = *valp & 0xff;
- uimm8x4_out_0 = uimm8x4_in_0 << 2;
- *valp = uimm8x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
-{
- unsigned uimm8x4_in_0;
- unsigned uimm8x4_out_0;
- uimm8x4_out_0 = *valp;
- uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
- *valp = uimm8x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_out_0;
- unsigned uimm4x16_in_0;
- uimm4x16_in_0 = *valp & 0xf;
- uimm4x16_out_0 = uimm4x16_in_0 << 4;
- *valp = uimm4x16_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
-{
- unsigned uimm4x16_in_0;
- unsigned uimm4x16_out_0;
- uimm4x16_out_0 = *valp;
- uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
- *valp = uimm4x16_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
-{
- unsigned uimmrx4_out_0;
- unsigned uimmrx4_in_0;
- uimmrx4_in_0 = *valp & 0xf;
- uimmrx4_out_0 = uimmrx4_in_0 << 2;
- *valp = uimmrx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
-{
- unsigned uimmrx4_in_0;
- unsigned uimmrx4_out_0;
- uimmrx4_out_0 = *valp;
- uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
- *valp = uimmrx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_decode (uint32 *valp)
-{
- unsigned simm8_out_0;
- unsigned simm8_in_0;
- simm8_in_0 = *valp & 0xff;
- simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
- *valp = simm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_encode (uint32 *valp)
-{
- unsigned simm8_in_0;
- unsigned simm8_out_0;
- simm8_out_0 = *valp;
- simm8_in_0 = (simm8_out_0 & 0xff);
- *valp = simm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_out_0;
- unsigned simm8x256_in_0;
- simm8x256_in_0 = *valp & 0xff;
- simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
- *valp = simm8x256_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
-{
- unsigned simm8x256_in_0;
- unsigned simm8x256_out_0;
- simm8x256_out_0 = *valp;
- simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
- *valp = simm8x256_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_out_0;
- unsigned simm12b_in_0;
- simm12b_in_0 = *valp & 0xfff;
- simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
- *valp = simm12b_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
-{
- unsigned simm12b_in_0;
- unsigned simm12b_out_0;
- simm12b_out_0 = *valp;
- simm12b_in_0 = (simm12b_out_0 & 0xfff);
- *valp = simm12b_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_out_0;
- unsigned msalp32_in_0;
- msalp32_in_0 = *valp & 0x1f;
- msalp32_out_0 = 0x20 - msalp32_in_0;
- *valp = msalp32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
-{
- unsigned msalp32_in_0;
- unsigned msalp32_out_0;
- msalp32_out_0 = *valp;
- msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
- *valp = msalp32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_out_0;
- unsigned op2p1_in_0;
- op2p1_in_0 = *valp & 0xf;
- op2p1_out_0 = op2p1_in_0 + 0x1;
- *valp = op2p1_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
-{
- unsigned op2p1_in_0;
- unsigned op2p1_out_0;
- op2p1_out_0 = *valp;
- op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
- *valp = op2p1_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_decode (uint32 *valp)
-{
- unsigned label8_out_0;
- unsigned label8_in_0;
- label8_in_0 = *valp & 0xff;
- label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
- *valp = label8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_encode (uint32 *valp)
-{
- unsigned label8_in_0;
- unsigned label8_out_0;
- label8_out_0 = *valp;
- label8_in_0 = (label8_out_0 - 0x4) & 0xff;
- *valp = label8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
-{
- unsigned ulabel8_out_0;
- unsigned ulabel8_in_0;
- ulabel8_in_0 = *valp & 0xff;
- ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
- *valp = ulabel8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
-{
- unsigned ulabel8_in_0;
- unsigned ulabel8_out_0;
- ulabel8_out_0 = *valp;
- ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
- *valp = ulabel8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_decode (uint32 *valp)
-{
- unsigned label12_out_0;
- unsigned label12_in_0;
- label12_in_0 = *valp & 0xfff;
- label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
- *valp = label12_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_encode (uint32 *valp)
-{
- unsigned label12_in_0;
- unsigned label12_out_0;
- label12_out_0 = *valp;
- label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
- *valp = label12_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_decode (uint32 *valp)
-{
- unsigned soffset_out_0;
- unsigned soffset_in_0;
- soffset_in_0 = *valp & 0x3ffff;
- soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
- *valp = soffset_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_encode (uint32 *valp)
-{
- unsigned soffset_in_0;
- unsigned soffset_out_0;
- soffset_out_0 = *valp;
- soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
- *valp = soffset_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_out_0;
- unsigned uimm16x4_in_0;
- uimm16x4_in_0 = *valp & 0xffff;
- uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
- *valp = uimm16x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
-{
- unsigned uimm16x4_in_0;
- unsigned uimm16x4_out_0;
- uimm16x4_out_0 = *valp;
- uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
- *valp = uimm16x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_decode (uint32 *valp)
-{
- unsigned bbi_out_0;
- unsigned bbi_in_0;
- bbi_in_0 = *valp & 0x1f;
- bbi_out_0 = (0 << 5) | bbi_in_0;
- *valp = bbi_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_encode (uint32 *valp)
-{
- unsigned bbi_in_0;
- unsigned bbi_out_0;
- bbi_out_0 = *valp;
- bbi_in_0 = (bbi_out_0 & 0x1f);
- *valp = bbi_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_decode (uint32 *valp)
-{
- unsigned s_out_0;
- unsigned s_in_0;
- s_in_0 = *valp & 0xf;
- s_out_0 = (0 << 4) | s_in_0;
- *valp = s_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_encode (uint32 *valp)
-{
- unsigned s_in_0;
- unsigned s_out_0;
- s_out_0 = *valp;
- s_in_0 = (s_out_0 & 0xf);
- *valp = s_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_encode (uint32 *valp)
-{
- return (*valp >= 4);
-}
-
-static int
-OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
-{
- return (*valp >= 4);
-}
-
-static int
-OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
-{
- return (*valp >= 4);
-}
-
-static int
-OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
-{
- return (*valp >= 4);
-}
-
-static int
-OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
-{
- return (*valp >= 4);
-}
-
-static int
-OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
-{
- return (*valp >= 4);
-}
-
-static int
-OperandSem_opnd_sem_immt_decode (uint32 *valp)
-{
- unsigned immt_out_0;
- unsigned immt_in_0;
- immt_in_0 = *valp & 0xf;
- immt_out_0 = immt_in_0;
- *valp = immt_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immt_encode (uint32 *valp)
-{
- unsigned immt_in_0;
- unsigned immt_out_0;
- immt_out_0 = *valp;
- immt_in_0 = immt_out_0 & 0xf;
- *valp = immt_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_tp7_decode (uint32 *valp)
-{
- unsigned tp7_out_0;
- unsigned tp7_in_0;
- tp7_in_0 = *valp & 0xf;
- tp7_out_0 = tp7_in_0 + 0x7;
- *valp = tp7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_tp7_encode (uint32 *valp)
-{
- unsigned tp7_in_0;
- unsigned tp7_out_0;
- tp7_out_0 = *valp;
- tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
- *valp = tp7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
-{
- unsigned xt_wbr15_label_out_0;
- unsigned xt_wbr15_label_in_0;
- xt_wbr15_label_in_0 = *valp & 0x7fff;
- xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
- *valp = xt_wbr15_label_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
-{
- unsigned xt_wbr15_label_in_0;
- unsigned xt_wbr15_label_out_0;
- xt_wbr15_label_out_0 = *valp;
- xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_label_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
-{
- unsigned xt_wbr18_label_out_0;
- unsigned xt_wbr18_label_in_0;
- xt_wbr18_label_in_0 = *valp & 0x3ffff;
- xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
- *valp = xt_wbr18_label_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
-{
- unsigned xt_wbr18_label_in_0;
- unsigned xt_wbr18_label_out_0;
- xt_wbr18_label_out_0 = *valp;
- xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
- *valp = xt_wbr18_label_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
-{
- unsigned bitindex_out_0;
- unsigned bitindex_in_0;
- bitindex_in_0 = *valp & 0x1f;
- bitindex_out_0 = (0 << 5) | bitindex_in_0;
- *valp = bitindex_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
-{
- unsigned bitindex_in_0;
- unsigned bitindex_out_0;
- bitindex_out_0 = *valp;
- bitindex_in_0 = (bitindex_out_0 & 0x1f);
- *valp = bitindex_in_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", FIELD_imm12, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
- 0, 0 },
- { "simm4", FIELD_mn, -1, 0,
- 0,
- OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
- 0, 0 },
- { "arr", FIELD_r, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ars", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "art", FIELD_t, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ar0", FIELD__ar0, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
- 0, 0 },
- { "ar4", FIELD__ar4, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
- 0, 0 },
- { "ar8", FIELD__ar8, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
- 0, 0 },
- { "ar12", FIELD__ar12, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
- 0, 0 },
- { "ars_entry", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
- 0, 0 },
- { "immrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
- 0, 0 },
- { "lsi4x4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
- 0, 0 },
- { "simm7", FIELD_imm7, -1, 0,
- 0,
- OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
- 0, 0 },
- { "uimm6", FIELD_imm6, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
- 0, 0 },
- { "b4const", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
- 0, 0 },
- { "b4constu", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
- 0, 0 },
- { "uimm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
- 0, 0 },
- { "uimm8x2", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
- 0, 0 },
- { "uimmrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
- 0, 0 },
- { "simm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
- 0, 0 },
- { "simm8x256", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
- 0, 0 },
- { "simm12b", FIELD_imm12b, -1, 0,
- 0,
- OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
- 0, 0 },
- { "msalp32", FIELD_sal, -1, 0,
- 0,
- OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
- 0, 0 },
- { "op2p1", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
- 0, 0 },
- { "label8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", FIELD_imm12, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", FIELD_imm16, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "bbi", FIELD_bbi, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sae", FIELD_sae, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sas", FIELD_sas, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sargt", FIELD_sargt, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "s", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
- 0, 0 },
- { "mx", FIELD_x, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
- 0, 0 },
- { "my", FIELD_y, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
- 0, 0 },
- { "mw", FIELD_w, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
- 0, 0 },
- { "mr0", FIELD__mr0, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
- 0, 0 },
- { "mr1", FIELD__mr1, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
- 0, 0 },
- { "mr2", FIELD__mr2, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
- 0, 0 },
- { "mr3", FIELD__mr3, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
- 0, 0 },
- { "immt", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "imms", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "tp7", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "bitindex", FIELD_bitindex, -1, 0,
- 0,
- OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
- 0, 0 },
- { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
- { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
- { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
- { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
- { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
- { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
- { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
- { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
- { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
- { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
- { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
- { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
- { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
- { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
- { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
- { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-enum xtensa_operand_id {
- OPERAND_soffsetx4,
- OPERAND_uimm12x8,
- OPERAND_simm4,
- OPERAND_arr,
- OPERAND_ars,
- OPERAND__ars_invisible,
- OPERAND_art,
- OPERAND_ar0,
- OPERAND_ar4,
- OPERAND_ar8,
- OPERAND_ar12,
- OPERAND_ars_entry,
- OPERAND_immrx4,
- OPERAND_lsi4x4,
- OPERAND_simm7,
- OPERAND_uimm6,
- OPERAND_ai4const,
- OPERAND_b4const,
- OPERAND_b4constu,
- OPERAND_uimm8,
- OPERAND_uimm8x2,
- OPERAND_uimm8x4,
- OPERAND_uimm4x16,
- OPERAND_uimmrx4,
- OPERAND_simm8,
- OPERAND_simm8x256,
- OPERAND_simm12b,
- OPERAND_msalp32,
- OPERAND_op2p1,
- OPERAND_label8,
- OPERAND_ulabel8,
- OPERAND_label12,
- OPERAND_soffset,
- OPERAND_uimm16x4,
- OPERAND_bbi,
- OPERAND_sae,
- OPERAND_sas,
- OPERAND_sargt,
- OPERAND_s,
- OPERAND_mx,
- OPERAND_my,
- OPERAND_mw,
- OPERAND_mr0,
- OPERAND_mr1,
- OPERAND_mr2,
- OPERAND_mr3,
- OPERAND_immt,
- OPERAND_imms,
- OPERAND_tp7,
- OPERAND_xt_wbr15_label,
- OPERAND_xt_wbr18_label,
- OPERAND_bitindex,
- OPERAND_t,
- OPERAND_bbi4,
- OPERAND_imm12,
- OPERAND_imm8,
- OPERAND_imm12b,
- OPERAND_imm16,
- OPERAND_m,
- OPERAND_n,
- OPERAND_offset,
- OPERAND_op0,
- OPERAND_op1,
- OPERAND_op2,
- OPERAND_r,
- OPERAND_sa4,
- OPERAND_sae4,
- OPERAND_sal,
- OPERAND_sas4,
- OPERAND_sr,
- OPERAND_st,
- OPERAND_thi3,
- OPERAND_imm4,
- OPERAND_mn,
- OPERAND_i,
- OPERAND_imm6lo,
- OPERAND_imm6hi,
- OPERAND_imm7lo,
- OPERAND_imm7hi,
- OPERAND_z,
- OPERAND_imm6,
- OPERAND_imm7,
- OPERAND_r3,
- OPERAND_rbit2,
- OPERAND_rhi,
- OPERAND_t3,
- OPERAND_tbit2,
- OPERAND_tlo,
- OPERAND_w,
- OPERAND_y,
- OPERAND_x,
- OPERAND_xt_wbr15_imm,
- OPERAND_xt_wbr18_imm,
- OPERAND_s3to1
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSEXCM }, 'o' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { OPERAND_ars_entry }, 's' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm12x8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { OPERAND_simm4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ai4const }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_simm7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8x256 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4const }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bbi }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4constu }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_label12 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sae }, 'i' },
- { { OPERAND_op2p1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { OPERAND_soffset }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_uimm16x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_simm12b }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimmrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { OPERAND_sas }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_msalp32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sargt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_EPC3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_EPC3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_EPC3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_EXCSAVE3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_EXCSAVE3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_EXCSAVE3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_EPC4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_EPC4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_EPC4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_EXCSAVE4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_EXCSAVE4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_EXCSAVE4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
- { { STATE_EPC5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
- { { STATE_EPC5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
- { { STATE_EPC5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
- { { STATE_EXCSAVE5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
- { { STATE_EXCSAVE5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
- { { STATE_EXCSAVE5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
- { { STATE_EPC6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
- { { STATE_EPC6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
- { { STATE_EPC6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
- { { STATE_EXCSAVE6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
- { { STATE_EXCSAVE6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
- { { STATE_EXCSAVE6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
- { { STATE_EPC7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
- { { STATE_EPC7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
- { { STATE_EPC7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
- { { STATE_EXCSAVE7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
- { { STATE_EXCSAVE7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
- { { STATE_EXCSAVE7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_EPS3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_EPS3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_EPS3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_EPS4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_EPS4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
- { { STATE_EPS5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
- { { STATE_EPS5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
- { { STATE_EPS5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
- { { STATE_EPS6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
- { { STATE_EPS6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
- { { STATE_EPS7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
- { { STATE_EPS7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
- { { STATE_EPS7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_VECBASE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_VECBASE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_VECBASE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul16_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPC5 }, 'i' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_EPC7 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_EPS5 }, 'i' },
- { { STATE_EPS6 }, 'i' },
- { { STATE_EPS7 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { OPERAND_imms }, 'i' },
- { { OPERAND_immt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_DBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_DBREAKC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_DBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_DBREAKC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_IBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_IBREAKA0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_IBREAKA0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_IBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_IBREAKA1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_IBREAKA1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_IBREAKENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_IBREAKENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_IBREAKENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_InOCDMode }, 'i' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
- { { STATE_InOCDMode }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_CCOMPARE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_XTSYNC }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
- { { STATE_ATOMCTL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
- { { STATE_ATOMCTL }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
- { { STATE_ATOMCTL }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
- { { STATE_ERI_RAW_INTERLOCK }, 'i' }
-};
-
-static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
- INTERFACE_ERI_RD_In,
- INTERFACE_ERI_RD_Out
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
- { { STATE_ERI_RAW_INTERLOCK }, 'o' }
-};
-
-static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
- INTERFACE_ERI_WR_In,
- INTERFACE_ERI_WR_Out
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
- INTERFACE_IMPWIRE
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32nb_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid0_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_configid0_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid1_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc5_args,
- 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc5_args,
- 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc5_args,
- 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave5_args,
- 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave5_args,
- 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave5_args,
- 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc6_args,
- 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc6_args,
- 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc6_args,
- 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave6_args,
- 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave6_args,
- 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave6_args,
- 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc7_args,
- 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc7_args,
- 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc7_args,
- 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave7_args,
- 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave7_args,
- 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave7_args,
- 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps5_args,
- 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps5_args,
- 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps5_args,
- 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps6_args,
- 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps6_args,
- 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps6_args,
- 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps7_args,
- 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps7_args,
- 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps7_args,
- 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 3, Iclass_xt_mul16_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_aa_args,
- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_ad_args,
- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_da_args,
- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_dd_args,
- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_aa_args,
- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_ad_args,
- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_da_args,
- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_dd_args,
- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_da_args,
- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_dd_args,
- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_l_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m3_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acclo_args,
- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acclo_args,
- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acclo_args,
- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acchi_args,
- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acchi_args,
- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acchi_args,
- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_lddr32_p_args,
- 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sddr32_p_args,
- 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_mmid_args,
- 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_lock_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_dcache_dyn_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_lock_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_clamp_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_atomctl_args,
- 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_atomctl_args,
- 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_atomctl_args,
- 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_div_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rer_args,
- 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
- { 2, Iclass_xt_iclass_wer_args,
- 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
- { 1, Iclass_rur_expstate_args,
- 1, Iclass_rur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_wur_expstate_args,
- 1, Iclass_wur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_iclass_READ_IMPWIRE_args,
- 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
- { 1, Iclass_iclass_SETB_EXPSTATE_args,
- 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
- { 1, Iclass_iclass_CLRB_EXPSTATE_args,
- 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
- { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
- 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
-};
-
-enum xtensa_iclass_id {
- ICLASS_xt_iclass_excw,
- ICLASS_xt_iclass_rfe,
- ICLASS_xt_iclass_rfde,
- ICLASS_xt_iclass_syscall,
- ICLASS_xt_iclass_call12,
- ICLASS_xt_iclass_call8,
- ICLASS_xt_iclass_call4,
- ICLASS_xt_iclass_callx12,
- ICLASS_xt_iclass_callx8,
- ICLASS_xt_iclass_callx4,
- ICLASS_xt_iclass_entry,
- ICLASS_xt_iclass_movsp,
- ICLASS_xt_iclass_rotw,
- ICLASS_xt_iclass_retw,
- ICLASS_xt_iclass_rfwou,
- ICLASS_xt_iclass_l32e,
- ICLASS_xt_iclass_s32e,
- ICLASS_xt_iclass_rsr_windowbase,
- ICLASS_xt_iclass_wsr_windowbase,
- ICLASS_xt_iclass_xsr_windowbase,
- ICLASS_xt_iclass_rsr_windowstart,
- ICLASS_xt_iclass_wsr_windowstart,
- ICLASS_xt_iclass_xsr_windowstart,
- ICLASS_xt_iclass_add_n,
- ICLASS_xt_iclass_addi_n,
- ICLASS_xt_iclass_bz6,
- ICLASS_xt_iclass_ill_n,
- ICLASS_xt_iclass_loadi4,
- ICLASS_xt_iclass_mov_n,
- ICLASS_xt_iclass_movi_n,
- ICLASS_xt_iclass_nopn,
- ICLASS_xt_iclass_retn,
- ICLASS_xt_iclass_storei4,
- ICLASS_xt_iclass_addi,
- ICLASS_xt_iclass_addmi,
- ICLASS_xt_iclass_addsub,
- ICLASS_xt_iclass_bit,
- ICLASS_xt_iclass_bsi8,
- ICLASS_xt_iclass_bsi8b,
- ICLASS_xt_iclass_bsi8u,
- ICLASS_xt_iclass_bst8,
- ICLASS_xt_iclass_bsz12,
- ICLASS_xt_iclass_call0,
- ICLASS_xt_iclass_callx0,
- ICLASS_xt_iclass_exti,
- ICLASS_xt_iclass_ill,
- ICLASS_xt_iclass_jump,
- ICLASS_xt_iclass_jumpx,
- ICLASS_xt_iclass_l16ui,
- ICLASS_xt_iclass_l16si,
- ICLASS_xt_iclass_l32i,
- ICLASS_xt_iclass_l32r,
- ICLASS_xt_iclass_l8i,
- ICLASS_xt_iclass_loop,
- ICLASS_xt_iclass_loopz,
- ICLASS_xt_iclass_movi,
- ICLASS_xt_iclass_movz,
- ICLASS_xt_iclass_neg,
- ICLASS_xt_iclass_nop,
- ICLASS_xt_iclass_return,
- ICLASS_xt_iclass_simcall,
- ICLASS_xt_iclass_s16i,
- ICLASS_xt_iclass_s32i,
- ICLASS_xt_iclass_s32nb,
- ICLASS_xt_iclass_s8i,
- ICLASS_xt_iclass_sar,
- ICLASS_xt_iclass_sari,
- ICLASS_xt_iclass_shifts,
- ICLASS_xt_iclass_shiftst,
- ICLASS_xt_iclass_shiftt,
- ICLASS_xt_iclass_slli,
- ICLASS_xt_iclass_srai,
- ICLASS_xt_iclass_srli,
- ICLASS_xt_iclass_memw,
- ICLASS_xt_iclass_extw,
- ICLASS_xt_iclass_isync,
- ICLASS_xt_iclass_sync,
- ICLASS_xt_iclass_rsil,
- ICLASS_xt_iclass_rsr_lend,
- ICLASS_xt_iclass_wsr_lend,
- ICLASS_xt_iclass_xsr_lend,
- ICLASS_xt_iclass_rsr_lcount,
- ICLASS_xt_iclass_wsr_lcount,
- ICLASS_xt_iclass_xsr_lcount,
- ICLASS_xt_iclass_rsr_lbeg,
- ICLASS_xt_iclass_wsr_lbeg,
- ICLASS_xt_iclass_xsr_lbeg,
- ICLASS_xt_iclass_rsr_sar,
- ICLASS_xt_iclass_wsr_sar,
- ICLASS_xt_iclass_xsr_sar,
- ICLASS_xt_iclass_rsr_memctl,
- ICLASS_xt_iclass_wsr_memctl,
- ICLASS_xt_iclass_xsr_memctl,
- ICLASS_xt_iclass_rsr_litbase,
- ICLASS_xt_iclass_wsr_litbase,
- ICLASS_xt_iclass_xsr_litbase,
- ICLASS_xt_iclass_rsr_configid0,
- ICLASS_xt_iclass_wsr_configid0,
- ICLASS_xt_iclass_rsr_configid1,
- ICLASS_xt_iclass_rsr_ps,
- ICLASS_xt_iclass_wsr_ps,
- ICLASS_xt_iclass_xsr_ps,
- ICLASS_xt_iclass_rsr_epc1,
- ICLASS_xt_iclass_wsr_epc1,
- ICLASS_xt_iclass_xsr_epc1,
- ICLASS_xt_iclass_rsr_excsave1,
- ICLASS_xt_iclass_wsr_excsave1,
- ICLASS_xt_iclass_xsr_excsave1,
- ICLASS_xt_iclass_rsr_epc2,
- ICLASS_xt_iclass_wsr_epc2,
- ICLASS_xt_iclass_xsr_epc2,
- ICLASS_xt_iclass_rsr_excsave2,
- ICLASS_xt_iclass_wsr_excsave2,
- ICLASS_xt_iclass_xsr_excsave2,
- ICLASS_xt_iclass_rsr_epc3,
- ICLASS_xt_iclass_wsr_epc3,
- ICLASS_xt_iclass_xsr_epc3,
- ICLASS_xt_iclass_rsr_excsave3,
- ICLASS_xt_iclass_wsr_excsave3,
- ICLASS_xt_iclass_xsr_excsave3,
- ICLASS_xt_iclass_rsr_epc4,
- ICLASS_xt_iclass_wsr_epc4,
- ICLASS_xt_iclass_xsr_epc4,
- ICLASS_xt_iclass_rsr_excsave4,
- ICLASS_xt_iclass_wsr_excsave4,
- ICLASS_xt_iclass_xsr_excsave4,
- ICLASS_xt_iclass_rsr_epc5,
- ICLASS_xt_iclass_wsr_epc5,
- ICLASS_xt_iclass_xsr_epc5,
- ICLASS_xt_iclass_rsr_excsave5,
- ICLASS_xt_iclass_wsr_excsave5,
- ICLASS_xt_iclass_xsr_excsave5,
- ICLASS_xt_iclass_rsr_epc6,
- ICLASS_xt_iclass_wsr_epc6,
- ICLASS_xt_iclass_xsr_epc6,
- ICLASS_xt_iclass_rsr_excsave6,
- ICLASS_xt_iclass_wsr_excsave6,
- ICLASS_xt_iclass_xsr_excsave6,
- ICLASS_xt_iclass_rsr_epc7,
- ICLASS_xt_iclass_wsr_epc7,
- ICLASS_xt_iclass_xsr_epc7,
- ICLASS_xt_iclass_rsr_excsave7,
- ICLASS_xt_iclass_wsr_excsave7,
- ICLASS_xt_iclass_xsr_excsave7,
- ICLASS_xt_iclass_rsr_eps2,
- ICLASS_xt_iclass_wsr_eps2,
- ICLASS_xt_iclass_xsr_eps2,
- ICLASS_xt_iclass_rsr_eps3,
- ICLASS_xt_iclass_wsr_eps3,
- ICLASS_xt_iclass_xsr_eps3,
- ICLASS_xt_iclass_rsr_eps4,
- ICLASS_xt_iclass_wsr_eps4,
- ICLASS_xt_iclass_xsr_eps4,
- ICLASS_xt_iclass_rsr_eps5,
- ICLASS_xt_iclass_wsr_eps5,
- ICLASS_xt_iclass_xsr_eps5,
- ICLASS_xt_iclass_rsr_eps6,
- ICLASS_xt_iclass_wsr_eps6,
- ICLASS_xt_iclass_xsr_eps6,
- ICLASS_xt_iclass_rsr_eps7,
- ICLASS_xt_iclass_wsr_eps7,
- ICLASS_xt_iclass_xsr_eps7,
- ICLASS_xt_iclass_rsr_excvaddr,
- ICLASS_xt_iclass_wsr_excvaddr,
- ICLASS_xt_iclass_xsr_excvaddr,
- ICLASS_xt_iclass_rsr_depc,
- ICLASS_xt_iclass_wsr_depc,
- ICLASS_xt_iclass_xsr_depc,
- ICLASS_xt_iclass_rsr_exccause,
- ICLASS_xt_iclass_wsr_exccause,
- ICLASS_xt_iclass_xsr_exccause,
- ICLASS_xt_iclass_rsr_misc0,
- ICLASS_xt_iclass_wsr_misc0,
- ICLASS_xt_iclass_xsr_misc0,
- ICLASS_xt_iclass_rsr_misc1,
- ICLASS_xt_iclass_wsr_misc1,
- ICLASS_xt_iclass_xsr_misc1,
- ICLASS_xt_iclass_rsr_prid,
- ICLASS_xt_iclass_rsr_vecbase,
- ICLASS_xt_iclass_wsr_vecbase,
- ICLASS_xt_iclass_xsr_vecbase,
- ICLASS_xt_mul16,
- ICLASS_xt_mul32,
- ICLASS_xt_iclass_mac16_aa,
- ICLASS_xt_iclass_mac16_ad,
- ICLASS_xt_iclass_mac16_da,
- ICLASS_xt_iclass_mac16_dd,
- ICLASS_xt_iclass_mac16a_aa,
- ICLASS_xt_iclass_mac16a_ad,
- ICLASS_xt_iclass_mac16a_da,
- ICLASS_xt_iclass_mac16a_dd,
- ICLASS_xt_iclass_mac16al_da,
- ICLASS_xt_iclass_mac16al_dd,
- ICLASS_xt_iclass_mac16_l,
- ICLASS_xt_iclass_rsr_m0,
- ICLASS_xt_iclass_wsr_m0,
- ICLASS_xt_iclass_xsr_m0,
- ICLASS_xt_iclass_rsr_m1,
- ICLASS_xt_iclass_wsr_m1,
- ICLASS_xt_iclass_xsr_m1,
- ICLASS_xt_iclass_rsr_m2,
- ICLASS_xt_iclass_wsr_m2,
- ICLASS_xt_iclass_xsr_m2,
- ICLASS_xt_iclass_rsr_m3,
- ICLASS_xt_iclass_wsr_m3,
- ICLASS_xt_iclass_xsr_m3,
- ICLASS_xt_iclass_rsr_acclo,
- ICLASS_xt_iclass_wsr_acclo,
- ICLASS_xt_iclass_xsr_acclo,
- ICLASS_xt_iclass_rsr_acchi,
- ICLASS_xt_iclass_wsr_acchi,
- ICLASS_xt_iclass_xsr_acchi,
- ICLASS_xt_iclass_rfi,
- ICLASS_xt_iclass_wait,
- ICLASS_xt_iclass_rsr_interrupt,
- ICLASS_xt_iclass_wsr_intset,
- ICLASS_xt_iclass_wsr_intclear,
- ICLASS_xt_iclass_rsr_intenable,
- ICLASS_xt_iclass_wsr_intenable,
- ICLASS_xt_iclass_xsr_intenable,
- ICLASS_xt_iclass_break,
- ICLASS_xt_iclass_break_n,
- ICLASS_xt_iclass_rsr_dbreaka0,
- ICLASS_xt_iclass_wsr_dbreaka0,
- ICLASS_xt_iclass_xsr_dbreaka0,
- ICLASS_xt_iclass_rsr_dbreakc0,
- ICLASS_xt_iclass_wsr_dbreakc0,
- ICLASS_xt_iclass_xsr_dbreakc0,
- ICLASS_xt_iclass_rsr_dbreaka1,
- ICLASS_xt_iclass_wsr_dbreaka1,
- ICLASS_xt_iclass_xsr_dbreaka1,
- ICLASS_xt_iclass_rsr_dbreakc1,
- ICLASS_xt_iclass_wsr_dbreakc1,
- ICLASS_xt_iclass_xsr_dbreakc1,
- ICLASS_xt_iclass_rsr_ibreaka0,
- ICLASS_xt_iclass_wsr_ibreaka0,
- ICLASS_xt_iclass_xsr_ibreaka0,
- ICLASS_xt_iclass_rsr_ibreaka1,
- ICLASS_xt_iclass_wsr_ibreaka1,
- ICLASS_xt_iclass_xsr_ibreaka1,
- ICLASS_xt_iclass_rsr_ibreakenable,
- ICLASS_xt_iclass_wsr_ibreakenable,
- ICLASS_xt_iclass_xsr_ibreakenable,
- ICLASS_xt_iclass_rsr_debugcause,
- ICLASS_xt_iclass_wsr_debugcause,
- ICLASS_xt_iclass_xsr_debugcause,
- ICLASS_xt_iclass_rsr_icount,
- ICLASS_xt_iclass_wsr_icount,
- ICLASS_xt_iclass_xsr_icount,
- ICLASS_xt_iclass_rsr_icountlevel,
- ICLASS_xt_iclass_wsr_icountlevel,
- ICLASS_xt_iclass_xsr_icountlevel,
- ICLASS_xt_iclass_rsr_ddr,
- ICLASS_xt_iclass_wsr_ddr,
- ICLASS_xt_iclass_xsr_ddr,
- ICLASS_xt_iclass_lddr32_p,
- ICLASS_xt_iclass_sddr32_p,
- ICLASS_xt_iclass_rfdo,
- ICLASS_xt_iclass_rfdd,
- ICLASS_xt_iclass_wsr_mmid,
- ICLASS_xt_iclass_rsr_ccount,
- ICLASS_xt_iclass_wsr_ccount,
- ICLASS_xt_iclass_xsr_ccount,
- ICLASS_xt_iclass_rsr_ccompare0,
- ICLASS_xt_iclass_wsr_ccompare0,
- ICLASS_xt_iclass_xsr_ccompare0,
- ICLASS_xt_iclass_rsr_ccompare1,
- ICLASS_xt_iclass_wsr_ccompare1,
- ICLASS_xt_iclass_xsr_ccompare1,
- ICLASS_xt_iclass_rsr_ccompare2,
- ICLASS_xt_iclass_wsr_ccompare2,
- ICLASS_xt_iclass_xsr_ccompare2,
- ICLASS_xt_iclass_icache,
- ICLASS_xt_iclass_icache_lock,
- ICLASS_xt_iclass_icache_inv,
- ICLASS_xt_iclass_licx,
- ICLASS_xt_iclass_sicx,
- ICLASS_xt_iclass_dcache,
- ICLASS_xt_iclass_dcache_dyn,
- ICLASS_xt_iclass_dcache_ind,
- ICLASS_xt_iclass_dcache_inv,
- ICLASS_xt_iclass_dpf,
- ICLASS_xt_iclass_dcache_lock,
- ICLASS_xt_iclass_sdct,
- ICLASS_xt_iclass_ldct,
- ICLASS_xt_iclass_idtlb,
- ICLASS_xt_iclass_rdtlb,
- ICLASS_xt_iclass_wdtlb,
- ICLASS_xt_iclass_iitlb,
- ICLASS_xt_iclass_ritlb,
- ICLASS_xt_iclass_witlb,
- ICLASS_xt_iclass_clamp,
- ICLASS_xt_iclass_minmax,
- ICLASS_xt_iclass_nsa,
- ICLASS_xt_iclass_sx,
- ICLASS_xt_iclass_l32ai,
- ICLASS_xt_iclass_s32ri,
- ICLASS_xt_iclass_s32c1i,
- ICLASS_xt_iclass_rsr_scompare1,
- ICLASS_xt_iclass_wsr_scompare1,
- ICLASS_xt_iclass_xsr_scompare1,
- ICLASS_xt_iclass_rsr_atomctl,
- ICLASS_xt_iclass_wsr_atomctl,
- ICLASS_xt_iclass_xsr_atomctl,
- ICLASS_xt_iclass_div,
- ICLASS_xt_iclass_rer,
- ICLASS_xt_iclass_wer,
- ICLASS_rur_expstate,
- ICLASS_wur_expstate,
- ICLASS_iclass_READ_IMPWIRE,
- ICLASS_iclass_SETB_EXPSTATE,
- ICLASS_iclass_CLRB_EXPSTATE,
- ICLASS_iclass_WRMSK_EXPSTATE
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2080;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3200;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5000;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x25;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1000;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x408000;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01d;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3400;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3500;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90000;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490000;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34800;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134800;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614800;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34900;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134900;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614900;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf06d;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03d;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00d;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc002;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd002;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800000;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc00000;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900000;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00000;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00000;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00000;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00000;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00000;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300000;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x26;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x66;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe6;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa6;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6007;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe007;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf6;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb6;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1007;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9007;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa007;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2007;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb007;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3007;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8007;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4007;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc007;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5007;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd007;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x56;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd6;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x96;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1002;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9002;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2002;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8076;
-}
-
-static void
-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9076;
-}
-
-static void
-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa076;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa002;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x830000;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x930000;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa30000;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb30000;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600100;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20f0;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5100;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5002;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6002;
-}
-
-static void
-Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x590000;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4002;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400000;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x401000;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x402000;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x403000;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404000;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa10000;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x810000;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x910000;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb10000;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10000;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210000;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410000;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c0;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20d0;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2010;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2020;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2030;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000;
-}
-
-static void
-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30100;
-}
-
-static void
-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130100;
-}
-
-static void
-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610100;
-}
-
-static void
-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30200;
-}
-
-static void
-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130200;
-}
-
-static void
-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610200;
-}
-
-static void
-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130000;
-}
-
-static void
-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610000;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30300;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130300;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610300;
-}
-
-static void
-Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36100;
-}
-
-static void
-Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136100;
-}
-
-static void
-Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616100;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30500;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130500;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610500;
-}
-
-static void
-Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b000;
-}
-
-static void
-Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b000;
-}
-
-static void
-Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d000;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e600;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e600;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e600;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b100;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b100;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b100;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d100;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d100;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d100;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b200;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b200;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b200;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d200;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d200;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d200;
-}
-
-static void
-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b300;
-}
-
-static void
-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b300;
-}
-
-static void
-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b300;
-}
-
-static void
-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d300;
-}
-
-static void
-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d300;
-}
-
-static void
-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d300;
-}
-
-static void
-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b400;
-}
-
-static void
-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b400;
-}
-
-static void
-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b400;
-}
-
-static void
-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d400;
-}
-
-static void
-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d400;
-}
-
-static void
-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d400;
-}
-
-static void
-Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b500;
-}
-
-static void
-Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b500;
-}
-
-static void
-Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b500;
-}
-
-static void
-Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d500;
-}
-
-static void
-Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d500;
-}
-
-static void
-Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d500;
-}
-
-static void
-Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b600;
-}
-
-static void
-Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b600;
-}
-
-static void
-Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b600;
-}
-
-static void
-Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d600;
-}
-
-static void
-Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d600;
-}
-
-static void
-Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d600;
-}
-
-static void
-Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b700;
-}
-
-static void
-Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b700;
-}
-
-static void
-Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b700;
-}
-
-static void
-Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d700;
-}
-
-static void
-Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d700;
-}
-
-static void
-Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d700;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c200;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c200;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c200;
-}
-
-static void
-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c300;
-}
-
-static void
-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c300;
-}
-
-static void
-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c300;
-}
-
-static void
-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c400;
-}
-
-static void
-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c400;
-}
-
-static void
-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c400;
-}
-
-static void
-Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c500;
-}
-
-static void
-Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c500;
-}
-
-static void
-Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c500;
-}
-
-static void
-Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c600;
-}
-
-static void
-Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c600;
-}
-
-static void
-Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c600;
-}
-
-static void
-Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c700;
-}
-
-static void
-Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c700;
-}
-
-static void
-Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c700;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ee00;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ee00;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ee00;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c000;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c000;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c000;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e800;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e800;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e800;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f400;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f400;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f400;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f500;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f500;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f500;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3eb00;
-}
-
-static void
-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e700;
-}
-
-static void
-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e700;
-}
-
-static void
-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e700;
-}
-
-static void
-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc10000;
-}
-
-static void
-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10000;
-}
-
-static void
-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x820000;
-}
-
-static void
-Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x740004;
-}
-
-static void
-Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x750004;
-}
-
-static void
-Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x760004;
-}
-
-static void
-Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x770004;
-}
-
-static void
-Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700004;
-}
-
-static void
-Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x710004;
-}
-
-static void
-Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x720004;
-}
-
-static void
-Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730004;
-}
-
-static void
-Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x340004;
-}
-
-static void
-Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x350004;
-}
-
-static void
-Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x360004;
-}
-
-static void
-Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x370004;
-}
-
-static void
-Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x640004;
-}
-
-static void
-Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x650004;
-}
-
-static void
-Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x660004;
-}
-
-static void
-Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x670004;
-}
-
-static void
-Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x240004;
-}
-
-static void
-Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x250004;
-}
-
-static void
-Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x260004;
-}
-
-static void
-Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270004;
-}
-
-static void
-Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780004;
-}
-
-static void
-Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x790004;
-}
-
-static void
-Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7a0004;
-}
-
-static void
-Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7b0004;
-}
-
-static void
-Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7c0004;
-}
-
-static void
-Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7d0004;
-}
-
-static void
-Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7e0004;
-}
-
-static void
-Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7f0004;
-}
-
-static void
-Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380004;
-}
-
-static void
-Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x390004;
-}
-
-static void
-Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a0004;
-}
-
-static void
-Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b0004;
-}
-
-static void
-Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c0004;
-}
-
-static void
-Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d0004;
-}
-
-static void
-Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e0004;
-}
-
-static void
-Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f0004;
-}
-
-static void
-Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680004;
-}
-
-static void
-Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x690004;
-}
-
-static void
-Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6a0004;
-}
-
-static void
-Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6b0004;
-}
-
-static void
-Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6c0004;
-}
-
-static void
-Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0004;
-}
-
-static void
-Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6e0004;
-}
-
-static void
-Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f0004;
-}
-
-static void
-Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280004;
-}
-
-static void
-Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x290004;
-}
-
-static void
-Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2a0004;
-}
-
-static void
-Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2b0004;
-}
-
-static void
-Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2c0004;
-}
-
-static void
-Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d0004;
-}
-
-static void
-Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e0004;
-}
-
-static void
-Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f0004;
-}
-
-static void
-Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580004;
-}
-
-static void
-Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480004;
-}
-
-static void
-Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x590004;
-}
-
-static void
-Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490004;
-}
-
-static void
-Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a0004;
-}
-
-static void
-Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4a0004;
-}
-
-static void
-Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b0004;
-}
-
-static void
-Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4b0004;
-}
-
-static void
-Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180004;
-}
-
-static void
-Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80004;
-}
-
-static void
-Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x190004;
-}
-
-static void
-Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90004;
-}
-
-static void
-Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1a0004;
-}
-
-static void
-Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0004;
-}
-
-static void
-Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b0004;
-}
-
-static void
-Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb0004;
-}
-
-static void
-Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900004;
-}
-
-static void
-Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800004;
-}
-
-static void
-Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32000;
-}
-
-static void
-Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132000;
-}
-
-static void
-Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612000;
-}
-
-static void
-Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32100;
-}
-
-static void
-Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132100;
-}
-
-static void
-Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612100;
-}
-
-static void
-Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32200;
-}
-
-static void
-Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132200;
-}
-
-static void
-Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612200;
-}
-
-static void
-Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32300;
-}
-
-static void
-Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x132300;
-}
-
-static void
-Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x612300;
-}
-
-static void
-Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31000;
-}
-
-static void
-Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131000;
-}
-
-static void
-Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x611000;
-}
-
-static void
-Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31100;
-}
-
-static void
-Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131100;
-}
-
-static void
-Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x611100;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3010;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7000;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e200;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e200;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e300;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e400;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e400;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e400;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf02d;
-}
-
-static void
-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39000;
-}
-
-static void
-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139000;
-}
-
-static void
-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619000;
-}
-
-static void
-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a000;
-}
-
-static void
-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a000;
-}
-
-static void
-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a000;
-}
-
-static void
-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39100;
-}
-
-static void
-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139100;
-}
-
-static void
-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619100;
-}
-
-static void
-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a100;
-}
-
-static void
-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a100;
-}
-
-static void
-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a100;
-}
-
-static void
-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38000;
-}
-
-static void
-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138000;
-}
-
-static void
-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618000;
-}
-
-static void
-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38100;
-}
-
-static void
-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138100;
-}
-
-static void
-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618100;
-}
-
-static void
-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36000;
-}
-
-static void
-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136000;
-}
-
-static void
-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616000;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e900;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e900;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e900;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ec00;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ec00;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ec00;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ed00;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ed00;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ed00;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36800;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136800;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616800;
-}
-
-static void
-Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70e0;
-}
-
-static void
-Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70f0;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e000;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e010;
-}
-
-static void
-Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135900;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ea00;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ea00;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ea00;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f000;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f000;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f000;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f100;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f100;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f100;
-}
-
-static void
-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f200;
-}
-
-static void
-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f200;
-}
-
-static void
-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f200;
-}
-
-static void
-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70c2;
-}
-
-static void
-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70e2;
-}
-
-static void
-Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70d2;
-}
-
-static void
-Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270d2;
-}
-
-static void
-Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x370d2;
-}
-
-static void
-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70f2;
-}
-
-static void
-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf10000;
-}
-
-static void
-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf12000;
-}
-
-static void
-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf11000;
-}
-
-static void
-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf13000;
-}
-
-static void
-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7042;
-}
-
-static void
-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7052;
-}
-
-static void
-Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf7082;
-}
-
-static void
-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x47082;
-}
-
-static void
-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x57082;
-}
-
-static void
-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7062;
-}
-
-static void
-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7072;
-}
-
-static void
-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7002;
-}
-
-static void
-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7012;
-}
-
-static void
-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7022;
-}
-
-static void
-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7032;
-}
-
-static void
-Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7082;
-}
-
-static void
-Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x27082;
-}
-
-static void
-Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x37082;
-}
-
-static void
-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf19000;
-}
-
-static void
-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf18000;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50c000;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50d000;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50b000;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50f000;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50e000;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x504000;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505000;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x503000;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x507000;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x506000;
-}
-
-static void
-Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x330000;
-}
-
-static void
-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x430000;
-}
-
-static void
-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530000;
-}
-
-static void
-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x630000;
-}
-
-static void
-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730000;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40e000;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40f000;
-}
-
-static void
-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230000;
-}
-
-static void
-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb002;
-}
-
-static void
-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf002;
-}
-
-static void
-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe002;
-}
-
-static void
-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30c00;
-}
-
-static void
-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130c00;
-}
-
-static void
-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610c00;
-}
-
-static void
-Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36300;
-}
-
-static void
-Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136300;
-}
-
-static void
-Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616300;
-}
-
-static void
-Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc20000;
-}
-
-static void
-Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd20000;
-}
-
-static void
-Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe20000;
-}
-
-static void
-Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf20000;
-}
-
-static void
-Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x406000;
-}
-
-static void
-Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x407000;
-}
-
-static void
-Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e60;
-}
-
-static void
-Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e600;
-}
-
-static void
-Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0000;
-}
-
-static void
-Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1000;
-}
-
-static void
-Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1200;
-}
-
-static void
-Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe2000;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
- Opcode_s32nb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
- Opcode_rsr_memctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
- Opcode_wsr_memctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
- Opcode_xsr_memctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
- Opcode_rsr_configid0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
- Opcode_wsr_configid0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
- Opcode_rsr_configid1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
- Opcode_rsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
- Opcode_wsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
- Opcode_xsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
- Opcode_rsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
- Opcode_wsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
- Opcode_xsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
- Opcode_rsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
- Opcode_wsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
- Opcode_xsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
- Opcode_rsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
- Opcode_wsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
- Opcode_xsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
- Opcode_rsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
- Opcode_wsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
- Opcode_xsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
- Opcode_rsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
- Opcode_wsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
- Opcode_xsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
- Opcode_mul_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
- Opcode_mul_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
- Opcode_mul_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
- Opcode_mul_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
- Opcode_mula_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
- Opcode_mula_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
- Opcode_mula_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
- Opcode_mula_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
- Opcode_muls_da_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
- Opcode_muls_da_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
- Opcode_muls_da_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
- Opcode_muls_da_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
- Opcode_lddec_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
- Opcode_ldinc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
- Opcode_rsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
- Opcode_wsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
- Opcode_xsr_m0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
- Opcode_rsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
- Opcode_wsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
- Opcode_xsr_m1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
- Opcode_rsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
- Opcode_wsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
- Opcode_xsr_m2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
- Opcode_rsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
- Opcode_wsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
- Opcode_xsr_m3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
- Opcode_rsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
- Opcode_wsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
- Opcode_xsr_acclo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
- Opcode_rsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
- Opcode_wsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
- Opcode_xsr_acchi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
- Opcode_lddr32_p_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
- Opcode_sddr32_p_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
- Opcode_wsr_mmid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
- Opcode_ipfl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
- Opcode_ihu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
- Opcode_iiu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
- Opcode_diwbui_p_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
- Opcode_dpfl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
- Opcode_dhu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
- Opcode_diu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
- Opcode_clamps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
- Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
- Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
- Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
- Opcode_quou_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
- Opcode_quos_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
- Opcode_remu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
- Opcode_rems_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
- Opcode_rer_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
- Opcode_wer_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
- Opcode_rur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
- Opcode_wur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
- Opcode_read_impwire_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
- Opcode_setb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
- Opcode_clrb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
- Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
-};
-
-
-
-
-\f
-/* Opcode table. */
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", ICLASS_xt_iclass_excw,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", ICLASS_xt_iclass_rfe,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", ICLASS_xt_iclass_rfde,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", ICLASS_xt_iclass_syscall,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "call12", ICLASS_xt_iclass_call12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", ICLASS_xt_iclass_call8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", ICLASS_xt_iclass_call4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", ICLASS_xt_iclass_callx12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", ICLASS_xt_iclass_callx8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", ICLASS_xt_iclass_callx4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", ICLASS_xt_iclass_entry,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", ICLASS_xt_iclass_movsp,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", ICLASS_xt_iclass_rotw,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", ICLASS_xt_iclass_l32e,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", ICLASS_xt_iclass_s32e,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", ICLASS_xt_iclass_add_n,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", ICLASS_xt_iclass_addi_n,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", ICLASS_xt_iclass_ill_n,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", ICLASS_xt_iclass_loadi4,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", ICLASS_xt_iclass_mov_n,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", ICLASS_xt_iclass_movi_n,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", ICLASS_xt_iclass_nopn,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", ICLASS_xt_iclass_retn,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", ICLASS_xt_iclass_storei4,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "addi", ICLASS_xt_iclass_addi,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", ICLASS_xt_iclass_addmi,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", ICLASS_xt_iclass_bit,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", ICLASS_xt_iclass_bit,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", ICLASS_xt_iclass_bit,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", ICLASS_xt_iclass_call0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", ICLASS_xt_iclass_callx0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", ICLASS_xt_iclass_exti,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", ICLASS_xt_iclass_ill,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", ICLASS_xt_iclass_jump,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", ICLASS_xt_iclass_jumpx,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", ICLASS_xt_iclass_l16ui,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", ICLASS_xt_iclass_l16si,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", ICLASS_xt_iclass_l32i,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", ICLASS_xt_iclass_l32r,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", ICLASS_xt_iclass_l8i,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", ICLASS_xt_iclass_loop,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", ICLASS_xt_iclass_movi,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", ICLASS_xt_iclass_neg,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", ICLASS_xt_iclass_neg,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", ICLASS_xt_iclass_nop,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", ICLASS_xt_iclass_return,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "simcall", ICLASS_xt_iclass_simcall,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "s16i", ICLASS_xt_iclass_s16i,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", ICLASS_xt_iclass_s32i,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s32nb", ICLASS_xt_iclass_s32nb,
- 0,
- Opcode_s32nb_encode_fns, 0, 0 },
- { "s8i", ICLASS_xt_iclass_s8i,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", ICLASS_xt_iclass_sari,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", ICLASS_xt_iclass_shifts,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", ICLASS_xt_iclass_shiftst,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", ICLASS_xt_iclass_slli,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", ICLASS_xt_iclass_srai,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", ICLASS_xt_iclass_srli,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", ICLASS_xt_iclass_memw,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", ICLASS_xt_iclass_extw,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", ICLASS_xt_iclass_isync,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", ICLASS_xt_iclass_rsil,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
- 0,
- Opcode_rsr_memctl_encode_fns, 0, 0 },
- { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
- 0,
- Opcode_wsr_memctl_encode_fns, 0, 0 },
- { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
- 0,
- Opcode_xsr_memctl_encode_fns, 0, 0 },
- { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
- 0,
- Opcode_rsr_configid0_encode_fns, 0, 0 },
- { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
- 0,
- Opcode_wsr_configid0_encode_fns, 0, 0 },
- { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
- 0,
- Opcode_rsr_configid1_encode_fns, 0, 0 },
- { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
- 0,
- Opcode_rsr_epc5_encode_fns, 0, 0 },
- { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
- 0,
- Opcode_wsr_epc5_encode_fns, 0, 0 },
- { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
- 0,
- Opcode_xsr_epc5_encode_fns, 0, 0 },
- { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
- 0,
- Opcode_rsr_excsave5_encode_fns, 0, 0 },
- { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
- 0,
- Opcode_wsr_excsave5_encode_fns, 0, 0 },
- { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
- 0,
- Opcode_xsr_excsave5_encode_fns, 0, 0 },
- { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
- 0,
- Opcode_rsr_epc6_encode_fns, 0, 0 },
- { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
- 0,
- Opcode_wsr_epc6_encode_fns, 0, 0 },
- { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
- 0,
- Opcode_xsr_epc6_encode_fns, 0, 0 },
- { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
- 0,
- Opcode_rsr_excsave6_encode_fns, 0, 0 },
- { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
- 0,
- Opcode_wsr_excsave6_encode_fns, 0, 0 },
- { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
- 0,
- Opcode_xsr_excsave6_encode_fns, 0, 0 },
- { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
- 0,
- Opcode_rsr_epc7_encode_fns, 0, 0 },
- { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
- 0,
- Opcode_wsr_epc7_encode_fns, 0, 0 },
- { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
- 0,
- Opcode_xsr_epc7_encode_fns, 0, 0 },
- { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
- 0,
- Opcode_rsr_excsave7_encode_fns, 0, 0 },
- { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
- 0,
- Opcode_wsr_excsave7_encode_fns, 0, 0 },
- { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
- 0,
- Opcode_xsr_excsave7_encode_fns, 0, 0 },
- { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
- 0,
- Opcode_rsr_eps5_encode_fns, 0, 0 },
- { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
- 0,
- Opcode_wsr_eps5_encode_fns, 0, 0 },
- { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
- 0,
- Opcode_xsr_eps5_encode_fns, 0, 0 },
- { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
- 0,
- Opcode_rsr_eps6_encode_fns, 0, 0 },
- { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
- 0,
- Opcode_wsr_eps6_encode_fns, 0, 0 },
- { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
- 0,
- Opcode_xsr_eps6_encode_fns, 0, 0 },
- { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
- 0,
- Opcode_rsr_eps7_encode_fns, 0, 0 },
- { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
- 0,
- Opcode_wsr_eps7_encode_fns, 0, 0 },
- { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
- 0,
- Opcode_xsr_eps7_encode_fns, 0, 0 },
- { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "mul16u", ICLASS_xt_mul16,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", ICLASS_xt_mul16,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "mull", ICLASS_xt_mul32,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_ll_encode_fns, 0, 0 },
- { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_hl_encode_fns, 0, 0 },
- { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_lh_encode_fns, 0, 0 },
- { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_hh_encode_fns, 0, 0 },
- { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_ll_encode_fns, 0, 0 },
- { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_hl_encode_fns, 0, 0 },
- { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_lh_encode_fns, 0, 0 },
- { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_hh_encode_fns, 0, 0 },
- { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_ll_encode_fns, 0, 0 },
- { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_hl_encode_fns, 0, 0 },
- { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_lh_encode_fns, 0, 0 },
- { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_hh_encode_fns, 0, 0 },
- { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_ll_encode_fns, 0, 0 },
- { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_hl_encode_fns, 0, 0 },
- { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_lh_encode_fns, 0, 0 },
- { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_hh_encode_fns, 0, 0 },
- { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_ll_encode_fns, 0, 0 },
- { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_hl_encode_fns, 0, 0 },
- { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_lh_encode_fns, 0, 0 },
- { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_hh_encode_fns, 0, 0 },
- { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_ll_encode_fns, 0, 0 },
- { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_hl_encode_fns, 0, 0 },
- { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_lh_encode_fns, 0, 0 },
- { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_hh_encode_fns, 0, 0 },
- { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_ll_encode_fns, 0, 0 },
- { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_hl_encode_fns, 0, 0 },
- { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_lh_encode_fns, 0, 0 },
- { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_hh_encode_fns, 0, 0 },
- { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_ll_encode_fns, 0, 0 },
- { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_hl_encode_fns, 0, 0 },
- { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_lh_encode_fns, 0, 0 },
- { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_hh_encode_fns, 0, 0 },
- { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_ll_encode_fns, 0, 0 },
- { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_hl_encode_fns, 0, 0 },
- { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_lh_encode_fns, 0, 0 },
- { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_hh_encode_fns, 0, 0 },
- { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_ll_encode_fns, 0, 0 },
- { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_hl_encode_fns, 0, 0 },
- { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_lh_encode_fns, 0, 0 },
- { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_hh_encode_fns, 0, 0 },
- { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_ll_encode_fns, 0, 0 },
- { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_hl_encode_fns, 0, 0 },
- { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_lh_encode_fns, 0, 0 },
- { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_hh_encode_fns, 0, 0 },
- { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_ll_encode_fns, 0, 0 },
- { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_hl_encode_fns, 0, 0 },
- { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_lh_encode_fns, 0, 0 },
- { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_hh_encode_fns, 0, 0 },
- { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_ll_encode_fns, 0, 0 },
- { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_hl_encode_fns, 0, 0 },
- { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_lh_encode_fns, 0, 0 },
- { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_hh_encode_fns, 0, 0 },
- { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
- { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
- { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
- { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
- { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
- { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
- { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
- { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
- { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
- { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
- { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
- { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
- { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
- { "lddec", ICLASS_xt_iclass_mac16_l,
- 0,
- Opcode_lddec_encode_fns, 0, 0 },
- { "ldinc", ICLASS_xt_iclass_mac16_l,
- 0,
- Opcode_ldinc_encode_fns, 0, 0 },
- { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
- 0,
- Opcode_rsr_m0_encode_fns, 0, 0 },
- { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
- 0,
- Opcode_wsr_m0_encode_fns, 0, 0 },
- { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
- 0,
- Opcode_xsr_m0_encode_fns, 0, 0 },
- { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
- 0,
- Opcode_rsr_m1_encode_fns, 0, 0 },
- { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
- 0,
- Opcode_wsr_m1_encode_fns, 0, 0 },
- { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
- 0,
- Opcode_xsr_m1_encode_fns, 0, 0 },
- { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
- 0,
- Opcode_rsr_m2_encode_fns, 0, 0 },
- { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
- 0,
- Opcode_wsr_m2_encode_fns, 0, 0 },
- { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
- 0,
- Opcode_xsr_m2_encode_fns, 0, 0 },
- { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
- 0,
- Opcode_rsr_m3_encode_fns, 0, 0 },
- { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
- 0,
- Opcode_wsr_m3_encode_fns, 0, 0 },
- { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
- 0,
- Opcode_xsr_m3_encode_fns, 0, 0 },
- { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
- 0,
- Opcode_rsr_acclo_encode_fns, 0, 0 },
- { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
- 0,
- Opcode_wsr_acclo_encode_fns, 0, 0 },
- { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
- 0,
- Opcode_xsr_acclo_encode_fns, 0, 0 },
- { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
- 0,
- Opcode_rsr_acchi_encode_fns, 0, 0 },
- { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
- 0,
- Opcode_wsr_acchi_encode_fns, 0, 0 },
- { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
- 0,
- Opcode_xsr_acchi_encode_fns, 0, 0 },
- { "rfi", ICLASS_xt_iclass_rfi,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", ICLASS_xt_iclass_wait,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", ICLASS_xt_iclass_break,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", ICLASS_xt_iclass_break_n,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
- 0,
- Opcode_lddr32_p_encode_fns, 0, 0 },
- { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
- 0,
- Opcode_sddr32_p_encode_fns, 0, 0 },
- { "rfdo", ICLASS_xt_iclass_rfdo,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", ICLASS_xt_iclass_rfdd,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
- 0,
- Opcode_wsr_mmid_encode_fns, 0, 0 },
- { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "ipf", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "ipfl", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_ipfl_encode_fns, 0, 0 },
- { "ihu", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_ihu_encode_fns, 0, 0 },
- { "iiu", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_iiu_encode_fns, 0, 0 },
- { "iii", ICLASS_xt_iclass_icache_inv,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", ICLASS_xt_iclass_licx,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", ICLASS_xt_iclass_licx,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
- 0,
- Opcode_diwbui_p_encode_fns, 0, 0 },
- { "diwb", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "dpfl", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_dpfl_encode_fns, 0, 0 },
- { "dhu", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_dhu_encode_fns, 0, 0 },
- { "diu", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_diu_encode_fns, 0, 0 },
- { "sdct", ICLASS_xt_iclass_sdct,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", ICLASS_xt_iclass_ldct,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "idtlb", ICLASS_xt_iclass_idtlb,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", ICLASS_xt_iclass_wdtlb,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", ICLASS_xt_iclass_iitlb,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", ICLASS_xt_iclass_witlb,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "clamps", ICLASS_xt_iclass_clamp,
- 0,
- Opcode_clamps_encode_fns, 0, 0 },
- { "min", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", ICLASS_xt_iclass_sx,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", ICLASS_xt_iclass_l32ai,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", ICLASS_xt_iclass_s32ri,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", ICLASS_xt_iclass_s32c1i,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
- 0,
- Opcode_rsr_atomctl_encode_fns, 0, 0 },
- { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
- 0,
- Opcode_wsr_atomctl_encode_fns, 0, 0 },
- { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
- 0,
- Opcode_xsr_atomctl_encode_fns, 0, 0 },
- { "quou", ICLASS_xt_iclass_div,
- 0,
- Opcode_quou_encode_fns, 0, 0 },
- { "quos", ICLASS_xt_iclass_div,
- 0,
- Opcode_quos_encode_fns, 0, 0 },
- { "remu", ICLASS_xt_iclass_div,
- 0,
- Opcode_remu_encode_fns, 0, 0 },
- { "rems", ICLASS_xt_iclass_div,
- 0,
- Opcode_rems_encode_fns, 0, 0 },
- { "rer", ICLASS_xt_iclass_rer,
- 0,
- Opcode_rer_encode_fns, 0, 0 },
- { "wer", ICLASS_xt_iclass_wer,
- 0,
- Opcode_wer_encode_fns, 0, 0 },
- { "rur.expstate", ICLASS_rur_expstate,
- 0,
- Opcode_rur_expstate_encode_fns, 0, 0 },
- { "wur.expstate", ICLASS_wur_expstate,
- 0,
- Opcode_wur_expstate_encode_fns, 0, 0 },
- { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
- 0,
- Opcode_read_impwire_encode_fns, 0, 0 },
- { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
- 0,
- Opcode_setb_expstate_encode_fns, 0, 0 },
- { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
- 0,
- Opcode_clrb_expstate_encode_fns, 0, 0 },
- { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
- 0,
- Opcode_wrmsk_expstate_encode_fns, 0, 0 }
-};
-
-enum xtensa_opcode_id {
- OPCODE_EXCW,
- OPCODE_RFE,
- OPCODE_RFDE,
- OPCODE_SYSCALL,
- OPCODE_CALL12,
- OPCODE_CALL8,
- OPCODE_CALL4,
- OPCODE_CALLX12,
- OPCODE_CALLX8,
- OPCODE_CALLX4,
- OPCODE_ENTRY,
- OPCODE_MOVSP,
- OPCODE_ROTW,
- OPCODE_RETW,
- OPCODE_RETW_N,
- OPCODE_RFWO,
- OPCODE_RFWU,
- OPCODE_L32E,
- OPCODE_S32E,
- OPCODE_RSR_WINDOWBASE,
- OPCODE_WSR_WINDOWBASE,
- OPCODE_XSR_WINDOWBASE,
- OPCODE_RSR_WINDOWSTART,
- OPCODE_WSR_WINDOWSTART,
- OPCODE_XSR_WINDOWSTART,
- OPCODE_ADD_N,
- OPCODE_ADDI_N,
- OPCODE_BEQZ_N,
- OPCODE_BNEZ_N,
- OPCODE_ILL_N,
- OPCODE_L32I_N,
- OPCODE_MOV_N,
- OPCODE_MOVI_N,
- OPCODE_NOP_N,
- OPCODE_RET_N,
- OPCODE_S32I_N,
- OPCODE_ADDI,
- OPCODE_ADDMI,
- OPCODE_ADD,
- OPCODE_SUB,
- OPCODE_ADDX2,
- OPCODE_ADDX4,
- OPCODE_ADDX8,
- OPCODE_SUBX2,
- OPCODE_SUBX4,
- OPCODE_SUBX8,
- OPCODE_AND,
- OPCODE_OR,
- OPCODE_XOR,
- OPCODE_BEQI,
- OPCODE_BNEI,
- OPCODE_BGEI,
- OPCODE_BLTI,
- OPCODE_BBCI,
- OPCODE_BBSI,
- OPCODE_BGEUI,
- OPCODE_BLTUI,
- OPCODE_BEQ,
- OPCODE_BNE,
- OPCODE_BGE,
- OPCODE_BLT,
- OPCODE_BGEU,
- OPCODE_BLTU,
- OPCODE_BANY,
- OPCODE_BNONE,
- OPCODE_BALL,
- OPCODE_BNALL,
- OPCODE_BBC,
- OPCODE_BBS,
- OPCODE_BEQZ,
- OPCODE_BNEZ,
- OPCODE_BGEZ,
- OPCODE_BLTZ,
- OPCODE_CALL0,
- OPCODE_CALLX0,
- OPCODE_EXTUI,
- OPCODE_ILL,
- OPCODE_J,
- OPCODE_JX,
- OPCODE_L16UI,
- OPCODE_L16SI,
- OPCODE_L32I,
- OPCODE_L32R,
- OPCODE_L8UI,
- OPCODE_LOOP,
- OPCODE_LOOPNEZ,
- OPCODE_LOOPGTZ,
- OPCODE_MOVI,
- OPCODE_MOVEQZ,
- OPCODE_MOVNEZ,
- OPCODE_MOVLTZ,
- OPCODE_MOVGEZ,
- OPCODE_NEG,
- OPCODE_ABS,
- OPCODE_NOP,
- OPCODE_RET,
- OPCODE_SIMCALL,
- OPCODE_S16I,
- OPCODE_S32I,
- OPCODE_S32NB,
- OPCODE_S8I,
- OPCODE_SSR,
- OPCODE_SSL,
- OPCODE_SSA8L,
- OPCODE_SSA8B,
- OPCODE_SSAI,
- OPCODE_SLL,
- OPCODE_SRC,
- OPCODE_SRL,
- OPCODE_SRA,
- OPCODE_SLLI,
- OPCODE_SRAI,
- OPCODE_SRLI,
- OPCODE_MEMW,
- OPCODE_EXTW,
- OPCODE_ISYNC,
- OPCODE_RSYNC,
- OPCODE_ESYNC,
- OPCODE_DSYNC,
- OPCODE_RSIL,
- OPCODE_RSR_LEND,
- OPCODE_WSR_LEND,
- OPCODE_XSR_LEND,
- OPCODE_RSR_LCOUNT,
- OPCODE_WSR_LCOUNT,
- OPCODE_XSR_LCOUNT,
- OPCODE_RSR_LBEG,
- OPCODE_WSR_LBEG,
- OPCODE_XSR_LBEG,
- OPCODE_RSR_SAR,
- OPCODE_WSR_SAR,
- OPCODE_XSR_SAR,
- OPCODE_RSR_MEMCTL,
- OPCODE_WSR_MEMCTL,
- OPCODE_XSR_MEMCTL,
- OPCODE_RSR_LITBASE,
- OPCODE_WSR_LITBASE,
- OPCODE_XSR_LITBASE,
- OPCODE_RSR_CONFIGID0,
- OPCODE_WSR_CONFIGID0,
- OPCODE_RSR_CONFIGID1,
- OPCODE_RSR_PS,
- OPCODE_WSR_PS,
- OPCODE_XSR_PS,
- OPCODE_RSR_EPC1,
- OPCODE_WSR_EPC1,
- OPCODE_XSR_EPC1,
- OPCODE_RSR_EXCSAVE1,
- OPCODE_WSR_EXCSAVE1,
- OPCODE_XSR_EXCSAVE1,
- OPCODE_RSR_EPC2,
- OPCODE_WSR_EPC2,
- OPCODE_XSR_EPC2,
- OPCODE_RSR_EXCSAVE2,
- OPCODE_WSR_EXCSAVE2,
- OPCODE_XSR_EXCSAVE2,
- OPCODE_RSR_EPC3,
- OPCODE_WSR_EPC3,
- OPCODE_XSR_EPC3,
- OPCODE_RSR_EXCSAVE3,
- OPCODE_WSR_EXCSAVE3,
- OPCODE_XSR_EXCSAVE3,
- OPCODE_RSR_EPC4,
- OPCODE_WSR_EPC4,
- OPCODE_XSR_EPC4,
- OPCODE_RSR_EXCSAVE4,
- OPCODE_WSR_EXCSAVE4,
- OPCODE_XSR_EXCSAVE4,
- OPCODE_RSR_EPC5,
- OPCODE_WSR_EPC5,
- OPCODE_XSR_EPC5,
- OPCODE_RSR_EXCSAVE5,
- OPCODE_WSR_EXCSAVE5,
- OPCODE_XSR_EXCSAVE5,
- OPCODE_RSR_EPC6,
- OPCODE_WSR_EPC6,
- OPCODE_XSR_EPC6,
- OPCODE_RSR_EXCSAVE6,
- OPCODE_WSR_EXCSAVE6,
- OPCODE_XSR_EXCSAVE6,
- OPCODE_RSR_EPC7,
- OPCODE_WSR_EPC7,
- OPCODE_XSR_EPC7,
- OPCODE_RSR_EXCSAVE7,
- OPCODE_WSR_EXCSAVE7,
- OPCODE_XSR_EXCSAVE7,
- OPCODE_RSR_EPS2,
- OPCODE_WSR_EPS2,
- OPCODE_XSR_EPS2,
- OPCODE_RSR_EPS3,
- OPCODE_WSR_EPS3,
- OPCODE_XSR_EPS3,
- OPCODE_RSR_EPS4,
- OPCODE_WSR_EPS4,
- OPCODE_XSR_EPS4,
- OPCODE_RSR_EPS5,
- OPCODE_WSR_EPS5,
- OPCODE_XSR_EPS5,
- OPCODE_RSR_EPS6,
- OPCODE_WSR_EPS6,
- OPCODE_XSR_EPS6,
- OPCODE_RSR_EPS7,
- OPCODE_WSR_EPS7,
- OPCODE_XSR_EPS7,
- OPCODE_RSR_EXCVADDR,
- OPCODE_WSR_EXCVADDR,
- OPCODE_XSR_EXCVADDR,
- OPCODE_RSR_DEPC,
- OPCODE_WSR_DEPC,
- OPCODE_XSR_DEPC,
- OPCODE_RSR_EXCCAUSE,
- OPCODE_WSR_EXCCAUSE,
- OPCODE_XSR_EXCCAUSE,
- OPCODE_RSR_MISC0,
- OPCODE_WSR_MISC0,
- OPCODE_XSR_MISC0,
- OPCODE_RSR_MISC1,
- OPCODE_WSR_MISC1,
- OPCODE_XSR_MISC1,
- OPCODE_RSR_PRID,
- OPCODE_RSR_VECBASE,
- OPCODE_WSR_VECBASE,
- OPCODE_XSR_VECBASE,
- OPCODE_MUL16U,
- OPCODE_MUL16S,
- OPCODE_MULL,
- OPCODE_MUL_AA_LL,
- OPCODE_MUL_AA_HL,
- OPCODE_MUL_AA_LH,
- OPCODE_MUL_AA_HH,
- OPCODE_UMUL_AA_LL,
- OPCODE_UMUL_AA_HL,
- OPCODE_UMUL_AA_LH,
- OPCODE_UMUL_AA_HH,
- OPCODE_MUL_AD_LL,
- OPCODE_MUL_AD_HL,
- OPCODE_MUL_AD_LH,
- OPCODE_MUL_AD_HH,
- OPCODE_MUL_DA_LL,
- OPCODE_MUL_DA_HL,
- OPCODE_MUL_DA_LH,
- OPCODE_MUL_DA_HH,
- OPCODE_MUL_DD_LL,
- OPCODE_MUL_DD_HL,
- OPCODE_MUL_DD_LH,
- OPCODE_MUL_DD_HH,
- OPCODE_MULA_AA_LL,
- OPCODE_MULA_AA_HL,
- OPCODE_MULA_AA_LH,
- OPCODE_MULA_AA_HH,
- OPCODE_MULS_AA_LL,
- OPCODE_MULS_AA_HL,
- OPCODE_MULS_AA_LH,
- OPCODE_MULS_AA_HH,
- OPCODE_MULA_AD_LL,
- OPCODE_MULA_AD_HL,
- OPCODE_MULA_AD_LH,
- OPCODE_MULA_AD_HH,
- OPCODE_MULS_AD_LL,
- OPCODE_MULS_AD_HL,
- OPCODE_MULS_AD_LH,
- OPCODE_MULS_AD_HH,
- OPCODE_MULA_DA_LL,
- OPCODE_MULA_DA_HL,
- OPCODE_MULA_DA_LH,
- OPCODE_MULA_DA_HH,
- OPCODE_MULS_DA_LL,
- OPCODE_MULS_DA_HL,
- OPCODE_MULS_DA_LH,
- OPCODE_MULS_DA_HH,
- OPCODE_MULA_DD_LL,
- OPCODE_MULA_DD_HL,
- OPCODE_MULA_DD_LH,
- OPCODE_MULA_DD_HH,
- OPCODE_MULS_DD_LL,
- OPCODE_MULS_DD_HL,
- OPCODE_MULS_DD_LH,
- OPCODE_MULS_DD_HH,
- OPCODE_MULA_DA_LL_LDDEC,
- OPCODE_MULA_DA_LL_LDINC,
- OPCODE_MULA_DA_HL_LDDEC,
- OPCODE_MULA_DA_HL_LDINC,
- OPCODE_MULA_DA_LH_LDDEC,
- OPCODE_MULA_DA_LH_LDINC,
- OPCODE_MULA_DA_HH_LDDEC,
- OPCODE_MULA_DA_HH_LDINC,
- OPCODE_MULA_DD_LL_LDDEC,
- OPCODE_MULA_DD_LL_LDINC,
- OPCODE_MULA_DD_HL_LDDEC,
- OPCODE_MULA_DD_HL_LDINC,
- OPCODE_MULA_DD_LH_LDDEC,
- OPCODE_MULA_DD_LH_LDINC,
- OPCODE_MULA_DD_HH_LDDEC,
- OPCODE_MULA_DD_HH_LDINC,
- OPCODE_LDDEC,
- OPCODE_LDINC,
- OPCODE_RSR_M0,
- OPCODE_WSR_M0,
- OPCODE_XSR_M0,
- OPCODE_RSR_M1,
- OPCODE_WSR_M1,
- OPCODE_XSR_M1,
- OPCODE_RSR_M2,
- OPCODE_WSR_M2,
- OPCODE_XSR_M2,
- OPCODE_RSR_M3,
- OPCODE_WSR_M3,
- OPCODE_XSR_M3,
- OPCODE_RSR_ACCLO,
- OPCODE_WSR_ACCLO,
- OPCODE_XSR_ACCLO,
- OPCODE_RSR_ACCHI,
- OPCODE_WSR_ACCHI,
- OPCODE_XSR_ACCHI,
- OPCODE_RFI,
- OPCODE_WAITI,
- OPCODE_RSR_INTERRUPT,
- OPCODE_WSR_INTSET,
- OPCODE_WSR_INTCLEAR,
- OPCODE_RSR_INTENABLE,
- OPCODE_WSR_INTENABLE,
- OPCODE_XSR_INTENABLE,
- OPCODE_BREAK,
- OPCODE_BREAK_N,
- OPCODE_RSR_DBREAKA0,
- OPCODE_WSR_DBREAKA0,
- OPCODE_XSR_DBREAKA0,
- OPCODE_RSR_DBREAKC0,
- OPCODE_WSR_DBREAKC0,
- OPCODE_XSR_DBREAKC0,
- OPCODE_RSR_DBREAKA1,
- OPCODE_WSR_DBREAKA1,
- OPCODE_XSR_DBREAKA1,
- OPCODE_RSR_DBREAKC1,
- OPCODE_WSR_DBREAKC1,
- OPCODE_XSR_DBREAKC1,
- OPCODE_RSR_IBREAKA0,
- OPCODE_WSR_IBREAKA0,
- OPCODE_XSR_IBREAKA0,
- OPCODE_RSR_IBREAKA1,
- OPCODE_WSR_IBREAKA1,
- OPCODE_XSR_IBREAKA1,
- OPCODE_RSR_IBREAKENABLE,
- OPCODE_WSR_IBREAKENABLE,
- OPCODE_XSR_IBREAKENABLE,
- OPCODE_RSR_DEBUGCAUSE,
- OPCODE_WSR_DEBUGCAUSE,
- OPCODE_XSR_DEBUGCAUSE,
- OPCODE_RSR_ICOUNT,
- OPCODE_WSR_ICOUNT,
- OPCODE_XSR_ICOUNT,
- OPCODE_RSR_ICOUNTLEVEL,
- OPCODE_WSR_ICOUNTLEVEL,
- OPCODE_XSR_ICOUNTLEVEL,
- OPCODE_RSR_DDR,
- OPCODE_WSR_DDR,
- OPCODE_XSR_DDR,
- OPCODE_LDDR32_P,
- OPCODE_SDDR32_P,
- OPCODE_RFDO,
- OPCODE_RFDD,
- OPCODE_WSR_MMID,
- OPCODE_RSR_CCOUNT,
- OPCODE_WSR_CCOUNT,
- OPCODE_XSR_CCOUNT,
- OPCODE_RSR_CCOMPARE0,
- OPCODE_WSR_CCOMPARE0,
- OPCODE_XSR_CCOMPARE0,
- OPCODE_RSR_CCOMPARE1,
- OPCODE_WSR_CCOMPARE1,
- OPCODE_XSR_CCOMPARE1,
- OPCODE_RSR_CCOMPARE2,
- OPCODE_WSR_CCOMPARE2,
- OPCODE_XSR_CCOMPARE2,
- OPCODE_IPF,
- OPCODE_IHI,
- OPCODE_IPFL,
- OPCODE_IHU,
- OPCODE_IIU,
- OPCODE_III,
- OPCODE_LICT,
- OPCODE_LICW,
- OPCODE_SICT,
- OPCODE_SICW,
- OPCODE_DHWB,
- OPCODE_DHWBI,
- OPCODE_DIWBUI_P,
- OPCODE_DIWB,
- OPCODE_DIWBI,
- OPCODE_DHI,
- OPCODE_DII,
- OPCODE_DPFR,
- OPCODE_DPFW,
- OPCODE_DPFRO,
- OPCODE_DPFWO,
- OPCODE_DPFL,
- OPCODE_DHU,
- OPCODE_DIU,
- OPCODE_SDCT,
- OPCODE_LDCT,
- OPCODE_IDTLB,
- OPCODE_PDTLB,
- OPCODE_RDTLB0,
- OPCODE_RDTLB1,
- OPCODE_WDTLB,
- OPCODE_IITLB,
- OPCODE_PITLB,
- OPCODE_RITLB0,
- OPCODE_RITLB1,
- OPCODE_WITLB,
- OPCODE_CLAMPS,
- OPCODE_MIN,
- OPCODE_MAX,
- OPCODE_MINU,
- OPCODE_MAXU,
- OPCODE_NSA,
- OPCODE_NSAU,
- OPCODE_SEXT,
- OPCODE_L32AI,
- OPCODE_S32RI,
- OPCODE_S32C1I,
- OPCODE_RSR_SCOMPARE1,
- OPCODE_WSR_SCOMPARE1,
- OPCODE_XSR_SCOMPARE1,
- OPCODE_RSR_ATOMCTL,
- OPCODE_WSR_ATOMCTL,
- OPCODE_XSR_ATOMCTL,
- OPCODE_QUOU,
- OPCODE_QUOS,
- OPCODE_REMU,
- OPCODE_REMS,
- OPCODE_RER,
- OPCODE_WER,
- OPCODE_RUR_EXPSTATE,
- OPCODE_WUR_EXPSTATE,
- OPCODE_READ_IMPWIRE,
- OPCODE_SETB_EXPSTATE,
- OPCODE_CLRB_EXPSTATE,
- OPCODE_WRMSK_EXPSTATE
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst_get (insn) == 0)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- {
- if (Field_m_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_ILL;
- if (Field_m_Slot_inst_get (insn) == 2)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_RET;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_RETW;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_JX;
- }
- if (Field_m_Slot_inst_get (insn) == 3)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALLX0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALLX4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALLX8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALLX12;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_MOVSP;
- if (Field_r_Slot_inst_get (insn) == 2)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_ISYNC;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RSYNC;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_ESYNC;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DSYNC;
- if (Field_t_Slot_inst_get (insn) == 8)
- return OPCODE_EXCW;
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_MEMW;
- if (Field_t_Slot_inst_get (insn) == 13)
- return OPCODE_EXTW;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_NOP;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 3)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_RFE;
- if (Field_s_Slot_inst_get (insn) == 2)
- return OPCODE_RFDE;
- if (Field_s_Slot_inst_get (insn) == 4)
- return OPCODE_RFWO;
- if (Field_s_Slot_inst_get (insn) == 5)
- return OPCODE_RFWU;
- }
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFI;
- }
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BREAK;
- if (Field_r_Slot_inst_get (insn) == 5)
- {
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SYSCALL;
- if (Field_s_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SIMCALL;
- }
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RSIL;
- if (Field_r_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_WAITI;
- if (Field_r_Slot_inst_get (insn) == 7)
- {
- if (Field_t_Slot_inst_get (insn) == 14)
- return OPCODE_LDDR32_P;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_SDDR32_P;
- }
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- return OPCODE_AND;
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_OR;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_XOR;
- if (Field_op2_Slot_inst_get (insn) == 4)
- {
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSR;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSL;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8L;
- if (Field_r_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8B;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_thi3_Slot_inst_get (insn) == 0)
- return OPCODE_SSAI;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RER;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_WER;
- if (Field_r_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_ROTW;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_NSA;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_NSAU;
- }
- if (Field_op2_Slot_inst_get (insn) == 5)
- {
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_RITLB0;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IITLB;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_PITLB;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_WITLB;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_RITLB1;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_RDTLB0;
- if (Field_r_Slot_inst_get (insn) == 12 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IDTLB;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_PDTLB;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_WDTLB;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_RDTLB1;
- }
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_NEG;
- if (Field_s_Slot_inst_get (insn) == 1)
- return OPCODE_ABS;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_ADD;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_ADDX2;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_ADDX4;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_ADDX8;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_SUB;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_SUBX2;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_SUBX4;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_SUBX8;
- }
- if (Field_op1_Slot_inst_get (insn) == 1)
- {
- if ((Field_op2_Slot_inst_get (insn) == 0 ||
- Field_op2_Slot_inst_get (insn) == 1))
- return OPCODE_SLLI;
- if ((Field_op2_Slot_inst_get (insn) == 2 ||
- Field_op2_Slot_inst_get (insn) == 3))
- return OPCODE_SRAI;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_SRLI;
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_XSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_XSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_XSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_XSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_XSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_XSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 16)
- return OPCODE_XSR_ACCLO;
- if (Field_sr_Slot_inst_get (insn) == 17)
- return OPCODE_XSR_ACCHI;
- if (Field_sr_Slot_inst_get (insn) == 32)
- return OPCODE_XSR_M0;
- if (Field_sr_Slot_inst_get (insn) == 33)
- return OPCODE_XSR_M1;
- if (Field_sr_Slot_inst_get (insn) == 34)
- return OPCODE_XSR_M2;
- if (Field_sr_Slot_inst_get (insn) == 35)
- return OPCODE_XSR_M3;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_XSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_XSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_XSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_XSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_XSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_XSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_XSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_XSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_XSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_XSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_XSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_XSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_XSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_XSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_XSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_XSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_XSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_XSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_XSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_XSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_XSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_XSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_XSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_XSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_XSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_XSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_XSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_XSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_XSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_XSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_XSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_XSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_XSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_XSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_XSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_XSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_XSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_XSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_XSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_XSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_XSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_XSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_XSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_XSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_XSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_XSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_XSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_SRC;
- if (Field_op2_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRL;
- if (Field_op2_Slot_inst_get (insn) == 10 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SLL;
- if (Field_op2_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRA;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_MUL16U;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_MUL16S;
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_LICT;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_SICT;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_LICW;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_SICW;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_LDCT;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_SDCT;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_RFDO;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFDD;
- }
- }
- if (Field_op1_Slot_inst_get (insn) == 2)
- {
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MULL;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_QUOU;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_QUOS;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_REMU;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_REMS;
- }
- if (Field_op1_Slot_inst_get (insn) == 3)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_RSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_RSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_RSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_RSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_RSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_RSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 16)
- return OPCODE_RSR_ACCLO;
- if (Field_sr_Slot_inst_get (insn) == 17)
- return OPCODE_RSR_ACCHI;
- if (Field_sr_Slot_inst_get (insn) == 32)
- return OPCODE_RSR_M0;
- if (Field_sr_Slot_inst_get (insn) == 33)
- return OPCODE_RSR_M1;
- if (Field_sr_Slot_inst_get (insn) == 34)
- return OPCODE_RSR_M2;
- if (Field_sr_Slot_inst_get (insn) == 35)
- return OPCODE_RSR_M3;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_RSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_RSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_RSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_RSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_RSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_RSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_RSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_RSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_RSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_RSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_RSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_RSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_RSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_RSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_RSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_RSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_RSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_RSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_RSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_RSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_RSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_RSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_RSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_RSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_RSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_RSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_RSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 208)
- return OPCODE_RSR_CONFIGID1;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_RSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_RSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_RSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_RSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_RSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_RSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_RSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_RSR_INTERRUPT;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_RSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_RSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_RSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_RSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_RSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_RSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 235)
- return OPCODE_RSR_PRID;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_RSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_RSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_RSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_RSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_RSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_RSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_RSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_RSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_WSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_WSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_WSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_WSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_WSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_WSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 16)
- return OPCODE_WSR_ACCLO;
- if (Field_sr_Slot_inst_get (insn) == 17)
- return OPCODE_WSR_ACCHI;
- if (Field_sr_Slot_inst_get (insn) == 32)
- return OPCODE_WSR_M0;
- if (Field_sr_Slot_inst_get (insn) == 33)
- return OPCODE_WSR_M1;
- if (Field_sr_Slot_inst_get (insn) == 34)
- return OPCODE_WSR_M2;
- if (Field_sr_Slot_inst_get (insn) == 35)
- return OPCODE_WSR_M3;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_WSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_WSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 89)
- return OPCODE_WSR_MMID;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_WSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_WSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_WSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_WSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_WSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_WSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_WSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_WSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_WSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_WSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_WSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_WSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_WSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_WSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_WSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_WSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_WSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_WSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_WSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_WSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_WSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_WSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_WSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_WSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_WSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_WSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_WSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_WSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_WSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_WSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_WSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_WSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_WSR_INTSET;
- if (Field_sr_Slot_inst_get (insn) == 227)
- return OPCODE_WSR_INTCLEAR;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_WSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_WSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_WSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_WSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_WSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_WSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_WSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_WSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_WSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_WSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_WSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_WSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_WSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_SEXT;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_CLAMPS;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_MIN;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_MAX;
- if (Field_op2_Slot_inst_get (insn) == 6)
- return OPCODE_MINU;
- if (Field_op2_Slot_inst_get (insn) == 7)
- return OPCODE_MAXU;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MOVEQZ;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_MOVNEZ;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_MOVLTZ;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_MOVGEZ;
- if (Field_op2_Slot_inst_get (insn) == 14)
- {
- if (Field_st_Slot_inst_get (insn) == 230)
- return OPCODE_RUR_EXPSTATE;
- }
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WUR_EXPSTATE;
- }
- }
- if ((Field_op1_Slot_inst_get (insn) == 4 ||
- Field_op1_Slot_inst_get (insn) == 5))
- return OPCODE_EXTUI;
- if (Field_op1_Slot_inst_get (insn) == 9)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_L32E;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_S32E;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_S32NB;
- }
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_READ_IMPWIRE;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s3to1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_SETB_EXPSTATE;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s3to1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_CLRB_EXPSTATE;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_WRMSK_EXPSTATE;
- }
- if (Field_op0_Slot_inst_get (insn) == 1)
- return OPCODE_L32R;
- if (Field_op0_Slot_inst_get (insn) == 2)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_L8UI;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_L16UI;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_L32I;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_S8I;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_S16I;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_S32I;
- if (Field_r_Slot_inst_get (insn) == 7)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_DPFR;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_DPFW;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_DPFRO;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DPFWO;
- if (Field_t_Slot_inst_get (insn) == 4)
- return OPCODE_DHWB;
- if (Field_t_Slot_inst_get (insn) == 5)
- return OPCODE_DHWBI;
- if (Field_t_Slot_inst_get (insn) == 6)
- return OPCODE_DHI;
- if (Field_t_Slot_inst_get (insn) == 7)
- return OPCODE_DII;
- if (Field_t_Slot_inst_get (insn) == 8)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- return OPCODE_DPFL;
- if (Field_op1_Slot_inst_get (insn) == 2)
- return OPCODE_DHU;
- if (Field_op1_Slot_inst_get (insn) == 3)
- return OPCODE_DIU;
- if (Field_op1_Slot_inst_get (insn) == 4)
- return OPCODE_DIWB;
- if (Field_op1_Slot_inst_get (insn) == 5)
- return OPCODE_DIWBI;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_DIWBUI_P;
- }
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_IPF;
- if (Field_t_Slot_inst_get (insn) == 13)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- return OPCODE_IPFL;
- if (Field_op1_Slot_inst_get (insn) == 2)
- return OPCODE_IHU;
- if (Field_op1_Slot_inst_get (insn) == 3)
- return OPCODE_IIU;
- }
- if (Field_t_Slot_inst_get (insn) == 14)
- return OPCODE_IHI;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_III;
- }
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_L16SI;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_MOVI;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_L32AI;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_ADDI;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_ADDMI;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_S32C1I;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_S32RI;
- }
- if (Field_op0_Slot_inst_get (insn) == 4)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH_LDINC;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH_LDDEC;
- }
- if (Field_op2_Slot_inst_get (insn) == 2)
- {
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 3)
- {
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 4)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH_LDINC;
- }
- if (Field_op2_Slot_inst_get (insn) == 5)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH_LDDEC;
- }
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 7)
- {
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 1 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 2 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 3 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_HH;
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- {
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return OPCODE_LDINC;
- }
- if (Field_op2_Slot_inst_get (insn) == 9)
- {
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return OPCODE_LDDEC;
- }
- }
- if (Field_op0_Slot_inst_get (insn) == 5)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALL0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALL4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALL8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALL12;
- }
- if (Field_op0_Slot_inst_get (insn) == 6)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_J;
- if (Field_n_Slot_inst_get (insn) == 1)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQZ;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEZ;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTZ;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEZ;
- }
- if (Field_n_Slot_inst_get (insn) == 2)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQI;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEI;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEI;
- }
- if (Field_n_Slot_inst_get (insn) == 3)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_ENTRY;
- if (Field_m_Slot_inst_get (insn) == 1)
- {
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_LOOP;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_LOOPNEZ;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_LOOPGTZ;
- }
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTUI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEUI;
- }
- }
- if (Field_op0_Slot_inst_get (insn) == 7)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_BNONE;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_BEQ;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_BLT;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_BLTU;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BALL;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_BBC;
- if ((Field_r_Slot_inst_get (insn) == 6 ||
- Field_r_Slot_inst_get (insn) == 7))
- return OPCODE_BBCI;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_BANY;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_BNE;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_BGE;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_BGEU;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_BNALL;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_BBS;
- if ((Field_r_Slot_inst_get (insn) == 14 ||
- Field_r_Slot_inst_get (insn) == 15))
- return OPCODE_BBSI;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16b_get (insn) == 12)
- {
- if (Field_i_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOVI_N;
- if (Field_i_Slot_inst16b_get (insn) == 1)
- {
- if (Field_z_Slot_inst16b_get (insn) == 0)
- return OPCODE_BEQZ_N;
- if (Field_z_Slot_inst16b_get (insn) == 1)
- return OPCODE_BNEZ_N;
- }
- }
- if (Field_op0_Slot_inst16b_get (insn) == 13)
- {
- if (Field_r_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOV_N;
- if (Field_r_Slot_inst16b_get (insn) == 15)
- {
- if (Field_t_Slot_inst16b_get (insn) == 0)
- return OPCODE_RET_N;
- if (Field_t_Slot_inst16b_get (insn) == 1)
- return OPCODE_RETW_N;
- if (Field_t_Slot_inst16b_get (insn) == 2)
- return OPCODE_BREAK_N;
- if (Field_t_Slot_inst16b_get (insn) == 3 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_NOP_N;
- if (Field_t_Slot_inst16b_get (insn) == 6 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_ILL_N;
- }
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16a_get (insn) == 8)
- return OPCODE_L32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 9)
- return OPCODE_S32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 10)
- return OPCODE_ADD_N;
- if (Field_op0_Slot_inst16a_get (insn) == 11)
- return OPCODE_ADDI_N;
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffffff);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_get,
- Field_rbit2_Slot_inst_get,
- Field_rhi_Slot_inst_get,
- Field_t3_Slot_inst_get,
- Field_tbit2_Slot_inst_get,
- Field_tlo_Slot_inst_get,
- Field_w_Slot_inst_get,
- Field_y_Slot_inst_get,
- Field_x_Slot_inst_get,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- Field_bitindex_Slot_inst_get,
- Field_s3to1_Slot_inst_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_set,
- Field_rbit2_Slot_inst_set,
- Field_rhi_Slot_inst_set,
- Field_t3_Slot_inst_set,
- Field_tbit2_Slot_inst_set,
- Field_tlo_Slot_inst_set,
- Field_w_Slot_inst_set,
- Field_y_Slot_inst_set,
- Field_x_Slot_inst_set,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- Field_bitindex_Slot_inst_set,
- Field_s3to1_Slot_inst_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_get,
- Field_s3to1_Slot_inst16a_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_set,
- Field_s3to1_Slot_inst16a_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_get,
- Field_s3to1_Slot_inst16b_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_set,
- Field_s3to1_Slot_inst16b_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0x8;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xc;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0x8) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc) == 0x8)
- return 1; /* x16a */
- if ((insn[0] & 0xe) == 0xc)
- return 2; /* x16b */
- return -1;
-}
-
-static int length_table[256] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int l = insn[0];
- return length_table[l];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 0 /* little-endian */,
- 3 /* insn_size */, 0,
- 3, formats, format_decoder, length_decoder,
- 3, slots,
- 56 /* num_fields */,
- 94, operands,
- 313, iclasses,
- 439, opcodes, 0,
- 2, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 6, interfaces, 0,
- 0, funcUnits, 0
-};
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_fsf
-#include "core-fsf/xtensa-modules.inc.c"
+#include "core-fsf/xtensa-modules.c.inc"
static XtensaConfig fsf __attribute__((unused)) = {
.name = "fsf",
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+ Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#include "qemu/osdep.h"
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "PTEVADDR", 83, 0 },
+ { "DDR", 104, 0 },
+ { "176", 176, 0 },
+ { "208", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "LITBASE", 5, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "RASID", 90, 0 },
+ { "ITLBCFG", 91, 0 },
+ { "DTLBCFG", 92, 0 }
+};
+
+#define NUM_SYSREGS 49
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 0
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 17, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EPS2", 15, 0 },
+ { "EPS3", 15, 0 },
+ { "EPS4", 15, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSRING", 2, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 4, 0 },
+ { "WindowStart", 16, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "LITBADDR", 20, 0 },
+ { "LITBEN", 1, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 17, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "ASID3", 8, 0 },
+ { "ASID2", 8, 0 },
+ { "ASID1", 8, 0 },
+ { "INSTPGSZID4", 2, 0 },
+ { "DATAPGSZID4", 2, 0 },
+ { "PTBASE", 10, 0 }
+};
+
+#define NUM_STATES 58
+
+/* Macros for xtensa_state numbers (for use in iclasses because the
+ state numbers are not available when the iclass table is generated). */
+
+#define STATE_LCOUNT 0
+#define STATE_PC 1
+#define STATE_ICOUNT 2
+#define STATE_DDR 3
+#define STATE_INTERRUPT 4
+#define STATE_CCOUNT 5
+#define STATE_XTSYNC 6
+#define STATE_EPC1 7
+#define STATE_EPC2 8
+#define STATE_EPC3 9
+#define STATE_EPC4 10
+#define STATE_EXCSAVE1 11
+#define STATE_EXCSAVE2 12
+#define STATE_EXCSAVE3 13
+#define STATE_EXCSAVE4 14
+#define STATE_EPS2 15
+#define STATE_EPS3 16
+#define STATE_EPS4 17
+#define STATE_EXCCAUSE 18
+#define STATE_PSINTLEVEL 19
+#define STATE_PSUM 20
+#define STATE_PSWOE 21
+#define STATE_PSRING 22
+#define STATE_PSEXCM 23
+#define STATE_DEPC 24
+#define STATE_EXCVADDR 25
+#define STATE_WindowBase 26
+#define STATE_WindowStart 27
+#define STATE_PSCALLINC 28
+#define STATE_PSOWB 29
+#define STATE_LBEG 30
+#define STATE_LEND 31
+#define STATE_SAR 32
+#define STATE_LITBADDR 33
+#define STATE_LITBEN 34
+#define STATE_MISC0 35
+#define STATE_MISC1 36
+#define STATE_InOCDMode 37
+#define STATE_INTENABLE 38
+#define STATE_DBREAKA0 39
+#define STATE_DBREAKC0 40
+#define STATE_DBREAKA1 41
+#define STATE_DBREAKC1 42
+#define STATE_IBREAKA0 43
+#define STATE_IBREAKA1 44
+#define STATE_IBREAKENABLE 45
+#define STATE_ICOUNTLEVEL 46
+#define STATE_DEBUGCAUSE 47
+#define STATE_DBNUM 48
+#define STATE_CCOMPARE0 49
+#define STATE_CCOMPARE1 50
+#define STATE_CCOMPARE2 51
+#define STATE_ASID3 52
+#define STATE_ASID2 53
+#define STATE_ASID1 54
+#define STATE_INSTPGSZID4 55
+#define STATE_DATAPGSZID4 56
+#define STATE_PTBASE 57
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+\f
+/* Functional units. */
+
+static xtensa_funcUnit_internal funcUnits[] = {
+
+};
+
+\f
+/* Register files. */
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", 0, 32, 64 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+
+};
+
+\f
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+Operand_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_0, offset_0;
+ offset_0 = *valp & 0x3ffff;
+ soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_encode (uint32 *valp)
+{
+ unsigned offset_0, soffsetx4_0;
+ soffsetx4_0 = *valp;
+ offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = offset_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_0, imm12_0;
+ imm12_0 = *valp & 0xfff;
+ uimm12x8_0 = imm12_0 << 3;
+ *valp = uimm12x8_0;
+ return 0;
+}
+
+static int
+Operand_uimm12x8_encode (uint32 *valp)
+{
+ unsigned imm12_0, uimm12x8_0;
+ uimm12x8_0 = *valp;
+ imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
+ *valp = imm12_0;
+ return 0;
+}
+
+static int
+Operand_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_0, mn_0;
+ mn_0 = *valp & 0xf;
+ simm4_0 = ((int) mn_0 << 28) >> 28;
+ *valp = simm4_0;
+ return 0;
+}
+
+static int
+Operand_simm4_encode (uint32 *valp)
+{
+ unsigned mn_0, simm4_0;
+ simm4_0 = *valp;
+ mn_0 = (simm4_0 & 0xf);
+ *valp = mn_0;
+ return 0;
+}
+
+static int
+Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_arr_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ars_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_art_encode (uint32 *valp)
+{
+ return (*valp & ~0xf) != 0;
+}
+
+static int
+Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar0_encode (uint32 *valp)
+{
+ return (*valp & ~0x3f) != 0;
+}
+
+static int
+Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar4_encode (uint32 *valp)
+{
+ return (*valp & ~0x3f) != 0;
+}
+
+static int
+Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar8_encode (uint32 *valp)
+{
+ return (*valp & ~0x3f) != 0;
+}
+
+static int
+Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ar12_encode (uint32 *valp)
+{
+ return (*valp & ~0x3f) != 0;
+}
+
+static int
+Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+Operand_ars_entry_encode (uint32 *valp)
+{
+ return (*valp & ~0x3f) != 0;
+}
+
+static int
+Operand_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_0, r_0;
+ r_0 = *valp & 0xf;
+ immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2;
+ *valp = immrx4_0;
+ return 0;
+}
+
+static int
+Operand_immrx4_encode (uint32 *valp)
+{
+ unsigned r_0, immrx4_0;
+ immrx4_0 = *valp;
+ r_0 = ((immrx4_0 >> 2) & 0xf);
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_0, r_0;
+ r_0 = *valp & 0xf;
+ lsi4x4_0 = r_0 << 2;
+ *valp = lsi4x4_0;
+ return 0;
+}
+
+static int
+Operand_lsi4x4_encode (uint32 *valp)
+{
+ unsigned r_0, lsi4x4_0;
+ lsi4x4_0 = *valp;
+ r_0 = ((lsi4x4_0 >> 2) & 0xf);
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_0, imm7_0;
+ imm7_0 = *valp & 0x7f;
+ simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
+ *valp = simm7_0;
+ return 0;
+}
+
+static int
+Operand_simm7_encode (uint32 *valp)
+{
+ unsigned imm7_0, simm7_0;
+ simm7_0 = *valp;
+ imm7_0 = (simm7_0 & 0x7f);
+ *valp = imm7_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_0, imm6_0;
+ imm6_0 = *valp & 0x3f;
+ uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0);
+ *valp = uimm6_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_encode (uint32 *valp)
+{
+ unsigned imm6_0, uimm6_0;
+ uimm6_0 = *valp;
+ imm6_0 = (uimm6_0 - 0x4) & 0x3f;
+ *valp = imm6_0;
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_0, t_0;
+ t_0 = *valp & 0xf;
+ ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
+ *valp = ai4const_0;
+ return 0;
+}
+
+static int
+Operand_ai4const_encode (uint32 *valp)
+{
+ unsigned t_0, ai4const_0;
+ ai4const_0 = *valp;
+ switch (ai4const_0)
+ {
+ case 0xffffffff: t_0 = 0; break;
+ case 0x1: t_0 = 0x1; break;
+ case 0x2: t_0 = 0x2; break;
+ case 0x3: t_0 = 0x3; break;
+ case 0x4: t_0 = 0x4; break;
+ case 0x5: t_0 = 0x5; break;
+ case 0x6: t_0 = 0x6; break;
+ case 0x7: t_0 = 0x7; break;
+ case 0x8: t_0 = 0x8; break;
+ case 0x9: t_0 = 0x9; break;
+ case 0xa: t_0 = 0xa; break;
+ case 0xb: t_0 = 0xb; break;
+ case 0xc: t_0 = 0xc; break;
+ case 0xd: t_0 = 0xd; break;
+ case 0xe: t_0 = 0xe; break;
+ default: t_0 = 0xf; break;
+ }
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_0, r_0;
+ r_0 = *valp & 0xf;
+ b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
+ *valp = b4const_0;
+ return 0;
+}
+
+static int
+Operand_b4const_encode (uint32 *valp)
+{
+ unsigned r_0, b4const_0;
+ b4const_0 = *valp;
+ switch (b4const_0)
+ {
+ case 0xffffffff: r_0 = 0; break;
+ case 0x1: r_0 = 0x1; break;
+ case 0x2: r_0 = 0x2; break;
+ case 0x3: r_0 = 0x3; break;
+ case 0x4: r_0 = 0x4; break;
+ case 0x5: r_0 = 0x5; break;
+ case 0x6: r_0 = 0x6; break;
+ case 0x7: r_0 = 0x7; break;
+ case 0x8: r_0 = 0x8; break;
+ case 0xa: r_0 = 0x9; break;
+ case 0xc: r_0 = 0xa; break;
+ case 0x10: r_0 = 0xb; break;
+ case 0x20: r_0 = 0xc; break;
+ case 0x40: r_0 = 0xd; break;
+ case 0x80: r_0 = 0xe; break;
+ default: r_0 = 0xf; break;
+ }
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_0, r_0;
+ r_0 = *valp & 0xf;
+ b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
+ *valp = b4constu_0;
+ return 0;
+}
+
+static int
+Operand_b4constu_encode (uint32 *valp)
+{
+ unsigned r_0, b4constu_0;
+ b4constu_0 = *valp;
+ switch (b4constu_0)
+ {
+ case 0x8000: r_0 = 0; break;
+ case 0x10000: r_0 = 0x1; break;
+ case 0x2: r_0 = 0x2; break;
+ case 0x3: r_0 = 0x3; break;
+ case 0x4: r_0 = 0x4; break;
+ case 0x5: r_0 = 0x5; break;
+ case 0x6: r_0 = 0x6; break;
+ case 0x7: r_0 = 0x7; break;
+ case 0x8: r_0 = 0x8; break;
+ case 0xa: r_0 = 0x9; break;
+ case 0xc: r_0 = 0xa; break;
+ case 0x10: r_0 = 0xb; break;
+ case 0x20: r_0 = 0xc; break;
+ case 0x40: r_0 = 0xd; break;
+ case 0x80: r_0 = 0xe; break;
+ default: r_0 = 0xf; break;
+ }
+ *valp = r_0;
+ return 0;
+}
+
+static int
+Operand_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8_0 = imm8_0;
+ *valp = uimm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8_0;
+ uimm8_0 = *valp;
+ imm8_0 = (uimm8_0 & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8x2_0 = imm8_0 << 1;
+ *valp = uimm8x2_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x2_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8x2_0;
+ uimm8x2_0 = *valp;
+ imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ uimm8x4_0 = imm8_0 << 2;
+ *valp = uimm8x4_0;
+ return 0;
+}
+
+static int
+Operand_uimm8x4_encode (uint32 *valp)
+{
+ unsigned imm8_0, uimm8x4_0;
+ uimm8x4_0 = *valp;
+ imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_0, op2_0;
+ op2_0 = *valp & 0xf;
+ uimm4x16_0 = op2_0 << 4;
+ *valp = uimm4x16_0;
+ return 0;
+}
+
+static int
+Operand_uimm4x16_encode (uint32 *valp)
+{
+ unsigned op2_0, uimm4x16_0;
+ uimm4x16_0 = *valp;
+ op2_0 = ((uimm4x16_0 >> 4) & 0xf);
+ *valp = op2_0;
+ return 0;
+}
+
+static int
+Operand_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ simm8_0 = ((int) imm8_0 << 24) >> 24;
+ *valp = simm8_0;
+ return 0;
+}
+
+static int
+Operand_simm8_encode (uint32 *valp)
+{
+ unsigned imm8_0, simm8_0;
+ simm8_0 = *valp;
+ imm8_0 = (simm8_0 & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
+ *valp = simm8x256_0;
+ return 0;
+}
+
+static int
+Operand_simm8x256_encode (uint32 *valp)
+{
+ unsigned imm8_0, simm8x256_0;
+ simm8x256_0 = *valp;
+ imm8_0 = ((simm8x256_0 >> 8) & 0xff);
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_0, imm12b_0;
+ imm12b_0 = *valp & 0xfff;
+ simm12b_0 = ((int) imm12b_0 << 20) >> 20;
+ *valp = simm12b_0;
+ return 0;
+}
+
+static int
+Operand_simm12b_encode (uint32 *valp)
+{
+ unsigned imm12b_0, simm12b_0;
+ simm12b_0 = *valp;
+ imm12b_0 = (simm12b_0 & 0xfff);
+ *valp = imm12b_0;
+ return 0;
+}
+
+static int
+Operand_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_0, sal_0;
+ sal_0 = *valp & 0x1f;
+ msalp32_0 = 0x20 - sal_0;
+ *valp = msalp32_0;
+ return 0;
+}
+
+static int
+Operand_msalp32_encode (uint32 *valp)
+{
+ unsigned sal_0, msalp32_0;
+ msalp32_0 = *valp;
+ sal_0 = (0x20 - msalp32_0) & 0x1f;
+ *valp = sal_0;
+ return 0;
+}
+
+static int
+Operand_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_0, op2_0;
+ op2_0 = *valp & 0xf;
+ op2p1_0 = op2_0 + 0x1;
+ *valp = op2p1_0;
+ return 0;
+}
+
+static int
+Operand_op2p1_encode (uint32 *valp)
+{
+ unsigned op2_0, op2p1_0;
+ op2p1_0 = *valp;
+ op2_0 = (op2p1_0 - 0x1) & 0xf;
+ *valp = op2_0;
+ return 0;
+}
+
+static int
+Operand_label8_decode (uint32 *valp)
+{
+ unsigned label8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
+ *valp = label8_0;
+ return 0;
+}
+
+static int
+Operand_label8_encode (uint32 *valp)
+{
+ unsigned imm8_0, label8_0;
+ label8_0 = *valp;
+ imm8_0 = (label8_0 - 0x4) & 0xff;
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_0, imm8_0;
+ imm8_0 = *valp & 0xff;
+ ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0);
+ *valp = ulabel8_0;
+ return 0;
+}
+
+static int
+Operand_ulabel8_encode (uint32 *valp)
+{
+ unsigned imm8_0, ulabel8_0;
+ ulabel8_0 = *valp;
+ imm8_0 = (ulabel8_0 - 0x4) & 0xff;
+ *valp = imm8_0;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_decode (uint32 *valp)
+{
+ unsigned label12_0, imm12_0;
+ imm12_0 = *valp & 0xfff;
+ label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
+ *valp = label12_0;
+ return 0;
+}
+
+static int
+Operand_label12_encode (uint32 *valp)
+{
+ unsigned imm12_0, label12_0;
+ label12_0 = *valp;
+ imm12_0 = (label12_0 - 0x4) & 0xfff;
+ *valp = imm12_0;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_0, offset_0;
+ offset_0 = *valp & 0x3ffff;
+ soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
+ *valp = soffset_0;
+ return 0;
+}
+
+static int
+Operand_soffset_encode (uint32 *valp)
+{
+ unsigned offset_0, soffset_0;
+ soffset_0 = *valp;
+ offset_0 = (soffset_0 - 0x4) & 0x3ffff;
+ *valp = offset_0;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_0, imm16_0;
+ imm16_0 = *valp & 0xffff;
+ uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2;
+ *valp = uimm16x4_0;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_encode (uint32 *valp)
+{
+ unsigned imm16_0, uimm16x4_0;
+ uimm16x4_0 = *valp;
+ imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
+ *valp = imm16_0;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_immt_decode (uint32 *valp)
+{
+ unsigned immt_0, t_0;
+ t_0 = *valp & 0xf;
+ immt_0 = t_0;
+ *valp = immt_0;
+ return 0;
+}
+
+static int
+Operand_immt_encode (uint32 *valp)
+{
+ unsigned t_0, immt_0;
+ immt_0 = *valp;
+ t_0 = immt_0 & 0xf;
+ *valp = t_0;
+ return 0;
+}
+
+static int
+Operand_imms_decode (uint32 *valp)
+{
+ unsigned imms_0, s_0;
+ s_0 = *valp & 0xf;
+ imms_0 = s_0;
+ *valp = imms_0;
+ return 0;
+}
+
+static int
+Operand_imms_encode (uint32 *valp)
+{
+ unsigned s_0, imms_0;
+ imms_0 = *valp;
+ s_0 = imms_0 & 0xf;
+ *valp = s_0;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", 10, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_soffsetx4_encode, Operand_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", 3, -1, 0,
+ 0,
+ Operand_uimm12x8_encode, Operand_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", 26, -1, 0,
+ 0,
+ Operand_simm4_encode, Operand_simm4_decode,
+ 0, 0 },
+ { "arr", 14, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_arr_encode, Operand_arr_decode,
+ 0, 0 },
+ { "ars", 5, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_ars_encode, Operand_ars_decode,
+ 0, 0 },
+ { "*ars_invisible", 5, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ars_encode, Operand_ars_decode,
+ 0, 0 },
+ { "art", 0, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_art_encode, Operand_art_decode,
+ 0, 0 },
+ { "ar0", 35, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar0_encode, Operand_ar0_decode,
+ 0, 0 },
+ { "ar4", 36, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar4_encode, Operand_ar4_decode,
+ 0, 0 },
+ { "ar8", 37, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar8_encode, Operand_ar8_decode,
+ 0, 0 },
+ { "ar12", 38, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ Operand_ar12_encode, Operand_ar12_decode,
+ 0, 0 },
+ { "ars_entry", 5, 0, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ Operand_ars_entry_encode, Operand_ars_entry_decode,
+ 0, 0 },
+ { "immrx4", 14, -1, 0,
+ 0,
+ Operand_immrx4_encode, Operand_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", 14, -1, 0,
+ 0,
+ Operand_lsi4x4_encode, Operand_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", 34, -1, 0,
+ 0,
+ Operand_simm7_encode, Operand_simm7_decode,
+ 0, 0 },
+ { "uimm6", 33, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_uimm6_encode, Operand_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", 0, -1, 0,
+ 0,
+ Operand_ai4const_encode, Operand_ai4const_decode,
+ 0, 0 },
+ { "b4const", 14, -1, 0,
+ 0,
+ Operand_b4const_encode, Operand_b4const_decode,
+ 0, 0 },
+ { "b4constu", 14, -1, 0,
+ 0,
+ Operand_b4constu_encode, Operand_b4constu_decode,
+ 0, 0 },
+ { "uimm8", 4, -1, 0,
+ 0,
+ Operand_uimm8_encode, Operand_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", 4, -1, 0,
+ 0,
+ Operand_uimm8x2_encode, Operand_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", 4, -1, 0,
+ 0,
+ Operand_uimm8x4_encode, Operand_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", 13, -1, 0,
+ 0,
+ Operand_uimm4x16_encode, Operand_uimm4x16_decode,
+ 0, 0 },
+ { "simm8", 4, -1, 0,
+ 0,
+ Operand_simm8_encode, Operand_simm8_decode,
+ 0, 0 },
+ { "simm8x256", 4, -1, 0,
+ 0,
+ Operand_simm8x256_encode, Operand_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", 6, -1, 0,
+ 0,
+ Operand_simm12b_encode, Operand_simm12b_decode,
+ 0, 0 },
+ { "msalp32", 18, -1, 0,
+ 0,
+ Operand_msalp32_encode, Operand_msalp32_decode,
+ 0, 0 },
+ { "op2p1", 13, -1, 0,
+ 0,
+ Operand_op2p1_encode, Operand_op2p1_decode,
+ 0, 0 },
+ { "label8", 4, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_label8_encode, Operand_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", 4, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_ulabel8_encode, Operand_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", 3, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_label12_encode, Operand_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", 10, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_soffset_encode, Operand_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", 7, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ Operand_uimm16x4_encode, Operand_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "immt", 0, -1, 0,
+ 0,
+ Operand_immt_encode, Operand_immt_decode,
+ 0, 0 },
+ { "imms", 5, -1, 0,
+ 0,
+ Operand_imms_encode, Operand_imms_decode,
+ 0, 0 },
+ { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
+ { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
+ { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 10 /* ar12 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 9 /* ar8 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 8 /* ar4 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 10 /* ar12 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 9 /* ar8 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 8 /* ar4 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { 11 /* ars_entry */ }, 's' },
+ { { 4 /* ars */ }, 'i' },
+ { { 1 /* uimm12x8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { 2 /* simm4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { 5 /* *ars_invisible */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 12 /* immrx4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 12 /* immrx4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 16 /* ai4const */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 15 /* uimm6 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 13 /* lsi4x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { 4 /* ars */ }, 'o' },
+ { { 14 /* simm7 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { 5 /* *ars_invisible */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 13 /* lsi4x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 23 /* simm8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 24 /* simm8x256 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 17 /* b4const */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 37 /* bbi */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 18 /* b4constu */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' },
+ { { 28 /* label8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 30 /* label12 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { 0 /* soffsetx4 */ }, 'i' },
+ { { 7 /* ar0 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 7 /* ar0 */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' },
+ { { 52 /* sae */ }, 'i' },
+ { { 27 /* op2p1 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { 31 /* soffset */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 20 /* uimm8x2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 20 /* uimm8x2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 32 /* uimm16x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 19 /* uimm8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 29 /* ulabel8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 29 /* ulabel8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 25 /* simm12b */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { 3 /* arr */ }, 'm' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { 5 /* *ars_invisible */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 20 /* uimm8x2 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 19 /* uimm8 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { 56 /* sas */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 26 /* msalp32 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' },
+ { { 54 /* sargt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 6 /* art */ }, 'i' },
+ { { 40 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 40 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'o' },
+ { { STATE_LITBEN }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'm' },
+ { { STATE_LITBEN }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { 40 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { 40 /* s */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { 34 /* imms */ }, 'i' },
+ { { 33 /* immt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { 34 /* imms */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 22 /* uimm4x16 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'm' },
+ { { STATE_EXCVADDR }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'i' },
+ { { STATE_ASID2 }, 'i' },
+ { { STATE_ASID1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'o' },
+ { { STATE_ASID2 }, 'o' },
+ { { STATE_ASID1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'm' },
+ { { STATE_ASID2 }, 'm' },
+ { { STATE_ASID1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_176_args,
+ 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_208_args,
+ 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdo */,
+ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
+ 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_rasid_args,
+ 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_rasid_args,
+ 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_rasid_args,
+ 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_ldpte */,
+ 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwitlba */,
+ 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwdtlba */,
+ 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 }
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80200;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2300;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1500;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c0000;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580000;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x540000;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0000;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0000;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70000;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0000;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x804;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10f;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4300;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5300;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x94;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4830;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4831;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4816;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4930;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4931;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4916;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc800;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc00;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd60f;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd000;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc000;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd30f;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00f;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200c00;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200d00;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680000;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690000;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0000;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0000;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700600;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700e00;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0000;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0000;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700100;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700900;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700a00;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700200;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700b00;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700300;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700800;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700000;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700400;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700c00;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700500;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700d00;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640000;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650000;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670000;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660000;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500000;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200100;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200900;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200200;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0800;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0900;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0a00;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200a00;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1006;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0200;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200500;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200600;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200400;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x104;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x204;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x304;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x19;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x12;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x14;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0200;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0200;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10200;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20200;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x116;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x231;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x216;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x331;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x316;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x531;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x516;
+}
+
+static void
+Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb030;
+}
+
+static void
+Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd030;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe630;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe631;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe616;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb130;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb131;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb116;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd130;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd131;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd116;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb230;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb231;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb216;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd230;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd231;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd216;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb330;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb331;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb316;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd330;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd331;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd316;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb430;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb431;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb416;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd430;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd431;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd416;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc230;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc231;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc216;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc330;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc331;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc316;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc430;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc431;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc416;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xee30;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xee31;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xee16;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc030;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc031;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc016;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe830;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe831;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe816;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf430;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf431;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf416;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf530;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf531;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf516;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xeb30;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10300;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe230;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe231;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe331;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe430;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe431;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe416;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20f;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9030;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9031;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9016;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa030;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa031;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa016;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9130;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9131;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9116;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa130;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa131;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa116;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8030;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8031;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8016;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8130;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8131;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8116;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6030;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6031;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6016;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe930;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe931;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe916;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xec30;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xec31;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xec16;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed30;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed31;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed16;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6830;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6831;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6816;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1f;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10e1f;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea30;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea31;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea16;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf030;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf031;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf016;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf130;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf131;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf116;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf230;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf231;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf216;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0700;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0700;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0700;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x21f;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x11f;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31f;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240700;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250700;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280740;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280750;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260700;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270700;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200700;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210700;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x220700;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230700;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x91f;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81f;
+}
+
+static void
+Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5331;
+}
+
+static void
+Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5330;
+}
+
+static void
+Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5316;
+}
+
+static void
+Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a30;
+}
+
+static void
+Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a31;
+}
+
+static void
+Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a16;
+}
+
+static void
+Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b30;
+}
+
+static void
+Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b31;
+}
+
+static void
+Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b16;
+}
+
+static void
+Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c30;
+}
+
+static void
+Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c31;
+}
+
+static void
+Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c16;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc05;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd05;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb05;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf05;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe05;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x405;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x305;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x705;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x605;
+}
+
+static void
+Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1f;
+}
+
+static void
+Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x105;
+}
+
+static void
+Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x905;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe04;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf04;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
+ Opcode_rsr_176_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
+ Opcode_rsr_208_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
+ Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
+ Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
+ Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
+ Opcode_rsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
+ Opcode_wsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
+ Opcode_xsr_rasid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
+ Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
+ Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
+ Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
+ Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
+ Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
+ Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
+ Opcode_ldpte_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
+ Opcode_hwwitlba_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
+ Opcode_hwwdtlba_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+\f
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", 0 /* xt_iclass_excw */,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", 1 /* xt_iclass_rfe */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", 2 /* xt_iclass_rfde */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", 3 /* xt_iclass_syscall */,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "simcall", 4 /* xt_iclass_simcall */,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "call12", 5 /* xt_iclass_call12 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", 6 /* xt_iclass_call8 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", 7 /* xt_iclass_call4 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", 8 /* xt_iclass_callx12 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", 9 /* xt_iclass_callx8 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", 10 /* xt_iclass_callx4 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", 11 /* xt_iclass_entry */,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", 12 /* xt_iclass_movsp */,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", 13 /* xt_iclass_rotw */,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", 14 /* xt_iclass_retw */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", 14 /* xt_iclass_retw */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", 15 /* xt_iclass_rfwou */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", 15 /* xt_iclass_rfwou */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", 16 /* xt_iclass_l32e */,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", 17 /* xt_iclass_s32e */,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", 24 /* xt_iclass_add.n */,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", 25 /* xt_iclass_addi.n */,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", 26 /* xt_iclass_bz6 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", 26 /* xt_iclass_bz6 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", 27 /* xt_iclass_ill.n */,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", 28 /* xt_iclass_loadi4 */,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", 29 /* xt_iclass_mov.n */,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", 30 /* xt_iclass_movi.n */,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", 31 /* xt_iclass_nopn */,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", 32 /* xt_iclass_retn */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", 33 /* xt_iclass_storei4 */,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "addi", 34 /* xt_iclass_addi */,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", 35 /* xt_iclass_addmi */,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", 36 /* xt_iclass_addsub */,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", 37 /* xt_iclass_bit */,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", 37 /* xt_iclass_bit */,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", 37 /* xt_iclass_bit */,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", 38 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", 38 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", 38 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", 38 /* xt_iclass_bsi8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", 39 /* xt_iclass_bsi8b */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", 39 /* xt_iclass_bsi8b */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", 40 /* xt_iclass_bsi8u */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", 40 /* xt_iclass_bsi8u */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", 41 /* xt_iclass_bst8 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", 42 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", 42 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", 42 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", 42 /* xt_iclass_bsz12 */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", 43 /* xt_iclass_call0 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", 44 /* xt_iclass_callx0 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", 45 /* xt_iclass_exti */,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", 46 /* xt_iclass_ill */,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", 47 /* xt_iclass_jump */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", 48 /* xt_iclass_jumpx */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", 49 /* xt_iclass_l16ui */,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", 50 /* xt_iclass_l16si */,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", 51 /* xt_iclass_l32i */,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", 52 /* xt_iclass_l32r */,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", 53 /* xt_iclass_l8i */,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", 54 /* xt_iclass_loop */,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", 55 /* xt_iclass_loopz */,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", 55 /* xt_iclass_loopz */,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", 56 /* xt_iclass_movi */,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", 57 /* xt_iclass_movz */,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", 57 /* xt_iclass_movz */,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", 57 /* xt_iclass_movz */,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", 57 /* xt_iclass_movz */,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", 58 /* xt_iclass_neg */,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", 58 /* xt_iclass_neg */,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", 59 /* xt_iclass_nop */,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", 60 /* xt_iclass_return */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "s16i", 61 /* xt_iclass_s16i */,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", 62 /* xt_iclass_s32i */,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s8i", 63 /* xt_iclass_s8i */,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", 64 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", 64 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", 64 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", 64 /* xt_iclass_sar */,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", 65 /* xt_iclass_sari */,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", 66 /* xt_iclass_shifts */,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", 67 /* xt_iclass_shiftst */,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", 68 /* xt_iclass_shiftt */,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", 68 /* xt_iclass_shiftt */,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", 69 /* xt_iclass_slli */,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", 70 /* xt_iclass_srai */,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", 71 /* xt_iclass_srli */,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", 72 /* xt_iclass_memw */,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", 73 /* xt_iclass_extw */,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", 74 /* xt_iclass_isync */,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", 75 /* xt_iclass_sync */,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", 75 /* xt_iclass_sync */,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", 75 /* xt_iclass_sync */,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", 76 /* xt_iclass_rsil */,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", 77 /* xt_iclass_rsr.lend */,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", 78 /* xt_iclass_wsr.lend */,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", 79 /* xt_iclass_xsr.lend */,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", 86 /* xt_iclass_rsr.sar */,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", 87 /* xt_iclass_wsr.sar */,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", 88 /* xt_iclass_xsr.sar */,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.176", 92 /* xt_iclass_rsr.176 */,
+ 0,
+ Opcode_rsr_176_encode_fns, 0, 0 },
+ { "rsr.208", 93 /* xt_iclass_rsr.208 */,
+ 0,
+ Opcode_rsr_208_encode_fns, 0, 0 },
+ { "rsr.ps", 94 /* xt_iclass_rsr.ps */,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", 95 /* xt_iclass_wsr.ps */,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", 96 /* xt_iclass_xsr.ps */,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", 133 /* xt_iclass_rsr.depc */,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", 134 /* xt_iclass_wsr.depc */,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", 135 /* xt_iclass_xsr.depc */,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", 145 /* xt_iclass_rsr.prid */,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rfi", 146 /* xt_iclass_rfi */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", 147 /* xt_iclass_wait */,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", 149 /* xt_iclass_wsr.intset */,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", 154 /* xt_iclass_break */,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", 155 /* xt_iclass_break.n */,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", 180 /* xt_iclass_rsr.icount */,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", 181 /* xt_iclass_wsr.icount */,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", 182 /* xt_iclass_xsr.icount */,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "rfdo", 189 /* xt_iclass_rfdo */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", 190 /* xt_iclass_rfdd */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "ipf", 203 /* xt_iclass_icache */,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", 203 /* xt_iclass_icache */,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "iii", 204 /* xt_iclass_icache_inv */,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", 205 /* xt_iclass_licx */,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", 205 /* xt_iclass_licx */,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", 206 /* xt_iclass_sicx */,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", 206 /* xt_iclass_sicx */,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", 207 /* xt_iclass_dcache */,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", 207 /* xt_iclass_dcache */,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwb", 208 /* xt_iclass_dcache_ind */,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", 208 /* xt_iclass_dcache_ind */,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", 209 /* xt_iclass_dcache_inv */,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", 209 /* xt_iclass_dcache_inv */,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", 210 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", 210 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", 210 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", 210 /* xt_iclass_dpf */,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "sdct", 211 /* xt_iclass_sdct */,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", 212 /* xt_iclass_ldct */,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */,
+ 0,
+ Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */,
+ 0,
+ Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
+ { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */,
+ 0,
+ Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */,
+ 0,
+ Opcode_rsr_rasid_encode_fns, 0, 0 },
+ { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */,
+ 0,
+ Opcode_wsr_rasid_encode_fns, 0, 0 },
+ { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */,
+ 0,
+ Opcode_xsr_rasid_encode_fns, 0, 0 },
+ { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */,
+ 0,
+ Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
+ { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */,
+ 0,
+ Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
+ { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */,
+ 0,
+ Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
+ { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */,
+ 0,
+ Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
+ { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */,
+ 0,
+ Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
+ { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */,
+ 0,
+ Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
+ { "idtlb", 225 /* xt_iclass_idtlb */,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", 226 /* xt_iclass_rdtlb */,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", 226 /* xt_iclass_rdtlb */,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", 226 /* xt_iclass_rdtlb */,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", 227 /* xt_iclass_wdtlb */,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", 228 /* xt_iclass_iitlb */,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", 229 /* xt_iclass_ritlb */,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", 229 /* xt_iclass_ritlb */,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", 229 /* xt_iclass_ritlb */,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", 230 /* xt_iclass_witlb */,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "ldpte", 231 /* xt_iclass_ldpte */,
+ 0,
+ Opcode_ldpte_encode_fns, 0, 0 },
+ { "hwwitlba", 232 /* xt_iclass_hwwitlba */,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_hwwitlba_encode_fns, 0, 0 },
+ { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */,
+ 0,
+ Opcode_hwwdtlba_encode_fns, 0, 0 },
+ { "nsa", 234 /* xt_iclass_nsa */,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", 234 /* xt_iclass_nsa */,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 }
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return 77; /* ill */
+ break;
+ case 2:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 96; /* ret */
+ case 1:
+ return 14; /* retw */
+ case 2:
+ return 79; /* jx */
+ }
+ break;
+ case 3:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 75; /* callx0 */
+ case 1:
+ return 10; /* callx4 */
+ case 2:
+ return 9; /* callx8 */
+ case 3:
+ return 8; /* callx12 */
+ }
+ break;
+ }
+ break;
+ case 1:
+ return 12; /* movsp */
+ case 2:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ return 114; /* isync */
+ case 1:
+ return 115; /* rsync */
+ case 2:
+ return 116; /* esync */
+ case 3:
+ return 117; /* dsync */
+ case 8:
+ return 0; /* excw */
+ case 12:
+ return 112; /* memw */
+ case 13:
+ return 113; /* extw */
+ case 15:
+ return 95; /* nop */
+ }
+ }
+ break;
+ case 3:
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ return 1; /* rfe */
+ case 2:
+ return 2; /* rfde */
+ case 4:
+ return 16; /* rfwo */
+ case 5:
+ return 17; /* rfwu */
+ }
+ break;
+ case 1:
+ return 188; /* rfi */
+ }
+ break;
+ case 4:
+ return 196; /* break */
+ case 5:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 3; /* syscall */
+ break;
+ case 1:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 4; /* simcall */
+ break;
+ }
+ break;
+ case 6:
+ return 118; /* rsil */
+ case 7:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 189; /* waiti */
+ break;
+ }
+ break;
+ case 1:
+ return 47; /* and */
+ case 2:
+ return 48; /* or */
+ case 3:
+ return 49; /* xor */
+ case 4:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 100; /* ssr */
+ break;
+ case 1:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 101; /* ssl */
+ break;
+ case 2:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 102; /* ssa8l */
+ break;
+ case 3:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 103; /* ssa8b */
+ break;
+ case 4:
+ if (Field_thi3_Slot_inst_get (insn) == 0)
+ return 104; /* ssai */
+ break;
+ case 8:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return 13; /* rotw */
+ break;
+ case 14:
+ return 289; /* nsa */
+ case 15:
+ return 290; /* nsau */
+ }
+ break;
+ case 5:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 1:
+ return 287; /* hwwitlba */
+ case 3:
+ return 283; /* ritlb0 */
+ case 4:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 281; /* iitlb */
+ break;
+ case 5:
+ return 282; /* pitlb */
+ case 6:
+ return 285; /* witlb */
+ case 7:
+ return 284; /* ritlb1 */
+ case 9:
+ return 288; /* hwwdtlba */
+ case 11:
+ return 278; /* rdtlb0 */
+ case 12:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 276; /* idtlb */
+ break;
+ case 13:
+ return 277; /* pdtlb */
+ case 14:
+ return 280; /* wdtlb */
+ case 15:
+ return 279; /* rdtlb1 */
+ }
+ break;
+ case 6:
+ switch (Field_s_Slot_inst_get (insn))
+ {
+ case 0:
+ return 93; /* neg */
+ case 1:
+ return 94; /* abs */
+ }
+ break;
+ case 8:
+ return 39; /* add */
+ case 9:
+ return 41; /* addx2 */
+ case 10:
+ return 42; /* addx4 */
+ case 11:
+ return 43; /* addx8 */
+ case 12:
+ return 40; /* sub */
+ case 13:
+ return 44; /* subx2 */
+ case 14:
+ return 45; /* subx4 */
+ case 15:
+ return 46; /* subx8 */
+ }
+ break;
+ case 1:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ case 1:
+ return 109; /* slli */
+ case 2:
+ case 3:
+ return 110; /* srai */
+ case 4:
+ return 111; /* srli */
+ case 6:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return 127; /* xsr.lbeg */
+ case 1:
+ return 121; /* xsr.lend */
+ case 2:
+ return 124; /* xsr.lcount */
+ case 3:
+ return 130; /* xsr.sar */
+ case 5:
+ return 133; /* xsr.litbase */
+ case 72:
+ return 22; /* xsr.windowbase */
+ case 73:
+ return 25; /* xsr.windowstart */
+ case 83:
+ return 266; /* xsr.ptevaddr */
+ case 90:
+ return 269; /* xsr.rasid */
+ case 91:
+ return 272; /* xsr.itlbcfg */
+ case 92:
+ return 275; /* xsr.dtlbcfg */
+ case 96:
+ return 218; /* xsr.ibreakenable */
+ case 104:
+ return 230; /* xsr.ddr */
+ case 128:
+ return 212; /* xsr.ibreaka0 */
+ case 129:
+ return 215; /* xsr.ibreaka1 */
+ case 144:
+ return 200; /* xsr.dbreaka0 */
+ case 145:
+ return 206; /* xsr.dbreaka1 */
+ case 160:
+ return 203; /* xsr.dbreakc0 */
+ case 161:
+ return 209; /* xsr.dbreakc1 */
+ case 177:
+ return 141; /* xsr.epc1 */
+ case 178:
+ return 147; /* xsr.epc2 */
+ case 179:
+ return 153; /* xsr.epc3 */
+ case 180:
+ return 159; /* xsr.epc4 */
+ case 192:
+ return 177; /* xsr.depc */
+ case 194:
+ return 165; /* xsr.eps2 */
+ case 195:
+ return 168; /* xsr.eps3 */
+ case 196:
+ return 171; /* xsr.eps4 */
+ case 209:
+ return 144; /* xsr.excsave1 */
+ case 210:
+ return 150; /* xsr.excsave2 */
+ case 211:
+ return 156; /* xsr.excsave3 */
+ case 212:
+ return 162; /* xsr.excsave4 */
+ case 228:
+ return 195; /* xsr.intenable */
+ case 230:
+ return 138; /* xsr.ps */
+ case 232:
+ return 180; /* xsr.exccause */
+ case 233:
+ return 221; /* xsr.debugcause */
+ case 234:
+ return 235; /* xsr.ccount */
+ case 236:
+ return 224; /* xsr.icount */
+ case 237:
+ return 227; /* xsr.icountlevel */
+ case 238:
+ return 174; /* xsr.excvaddr */
+ case 240:
+ return 238; /* xsr.ccompare0 */
+ case 241:
+ return 241; /* xsr.ccompare1 */
+ case 242:
+ return 244; /* xsr.ccompare2 */
+ case 244:
+ return 183; /* xsr.misc0 */
+ case 245:
+ return 186; /* xsr.misc1 */
+ }
+ break;
+ case 8:
+ return 106; /* src */
+ case 9:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return 107; /* srl */
+ break;
+ case 10:
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return 105; /* sll */
+ break;
+ case 11:
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return 108; /* sra */
+ break;
+ case 15:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return 248; /* lict */
+ case 1:
+ return 250; /* sict */
+ case 2:
+ return 249; /* licw */
+ case 3:
+ return 251; /* sicw */
+ case 8:
+ return 263; /* ldct */
+ case 9:
+ return 262; /* sdct */
+ case 14:
+ if (Field_t_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return 231; /* rfdo */
+ if (Field_t_Slot_inst_get (insn) == 1 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return 232; /* rfdd */
+ break;
+ case 15:
+ return 286; /* ldpte */
+ }
+ break;
+ }
+ break;
+ case 3:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return 125; /* rsr.lbeg */
+ case 1:
+ return 119; /* rsr.lend */
+ case 2:
+ return 122; /* rsr.lcount */
+ case 3:
+ return 128; /* rsr.sar */
+ case 5:
+ return 131; /* rsr.litbase */
+ case 72:
+ return 20; /* rsr.windowbase */
+ case 73:
+ return 23; /* rsr.windowstart */
+ case 83:
+ return 265; /* rsr.ptevaddr */
+ case 90:
+ return 267; /* rsr.rasid */
+ case 91:
+ return 270; /* rsr.itlbcfg */
+ case 92:
+ return 273; /* rsr.dtlbcfg */
+ case 96:
+ return 216; /* rsr.ibreakenable */
+ case 104:
+ return 228; /* rsr.ddr */
+ case 128:
+ return 210; /* rsr.ibreaka0 */
+ case 129:
+ return 213; /* rsr.ibreaka1 */
+ case 144:
+ return 198; /* rsr.dbreaka0 */
+ case 145:
+ return 204; /* rsr.dbreaka1 */
+ case 160:
+ return 201; /* rsr.dbreakc0 */
+ case 161:
+ return 207; /* rsr.dbreakc1 */
+ case 176:
+ return 134; /* rsr.176 */
+ case 177:
+ return 139; /* rsr.epc1 */
+ case 178:
+ return 145; /* rsr.epc2 */
+ case 179:
+ return 151; /* rsr.epc3 */
+ case 180:
+ return 157; /* rsr.epc4 */
+ case 192:
+ return 175; /* rsr.depc */
+ case 194:
+ return 163; /* rsr.eps2 */
+ case 195:
+ return 166; /* rsr.eps3 */
+ case 196:
+ return 169; /* rsr.eps4 */
+ case 208:
+ return 135; /* rsr.208 */
+ case 209:
+ return 142; /* rsr.excsave1 */
+ case 210:
+ return 148; /* rsr.excsave2 */
+ case 211:
+ return 154; /* rsr.excsave3 */
+ case 212:
+ return 160; /* rsr.excsave4 */
+ case 226:
+ return 190; /* rsr.interrupt */
+ case 228:
+ return 193; /* rsr.intenable */
+ case 230:
+ return 136; /* rsr.ps */
+ case 232:
+ return 178; /* rsr.exccause */
+ case 233:
+ return 219; /* rsr.debugcause */
+ case 234:
+ return 233; /* rsr.ccount */
+ case 235:
+ return 187; /* rsr.prid */
+ case 236:
+ return 222; /* rsr.icount */
+ case 237:
+ return 225; /* rsr.icountlevel */
+ case 238:
+ return 172; /* rsr.excvaddr */
+ case 240:
+ return 236; /* rsr.ccompare0 */
+ case 241:
+ return 239; /* rsr.ccompare1 */
+ case 242:
+ return 242; /* rsr.ccompare2 */
+ case 244:
+ return 181; /* rsr.misc0 */
+ case 245:
+ return 184; /* rsr.misc1 */
+ }
+ break;
+ case 1:
+ switch (Field_sr_Slot_inst_get (insn))
+ {
+ case 0:
+ return 126; /* wsr.lbeg */
+ case 1:
+ return 120; /* wsr.lend */
+ case 2:
+ return 123; /* wsr.lcount */
+ case 3:
+ return 129; /* wsr.sar */
+ case 5:
+ return 132; /* wsr.litbase */
+ case 72:
+ return 21; /* wsr.windowbase */
+ case 73:
+ return 24; /* wsr.windowstart */
+ case 83:
+ return 264; /* wsr.ptevaddr */
+ case 90:
+ return 268; /* wsr.rasid */
+ case 91:
+ return 271; /* wsr.itlbcfg */
+ case 92:
+ return 274; /* wsr.dtlbcfg */
+ case 96:
+ return 217; /* wsr.ibreakenable */
+ case 104:
+ return 229; /* wsr.ddr */
+ case 128:
+ return 211; /* wsr.ibreaka0 */
+ case 129:
+ return 214; /* wsr.ibreaka1 */
+ case 144:
+ return 199; /* wsr.dbreaka0 */
+ case 145:
+ return 205; /* wsr.dbreaka1 */
+ case 160:
+ return 202; /* wsr.dbreakc0 */
+ case 161:
+ return 208; /* wsr.dbreakc1 */
+ case 177:
+ return 140; /* wsr.epc1 */
+ case 178:
+ return 146; /* wsr.epc2 */
+ case 179:
+ return 152; /* wsr.epc3 */
+ case 180:
+ return 158; /* wsr.epc4 */
+ case 192:
+ return 176; /* wsr.depc */
+ case 194:
+ return 164; /* wsr.eps2 */
+ case 195:
+ return 167; /* wsr.eps3 */
+ case 196:
+ return 170; /* wsr.eps4 */
+ case 209:
+ return 143; /* wsr.excsave1 */
+ case 210:
+ return 149; /* wsr.excsave2 */
+ case 211:
+ return 155; /* wsr.excsave3 */
+ case 212:
+ return 161; /* wsr.excsave4 */
+ case 226:
+ return 191; /* wsr.intset */
+ case 227:
+ return 192; /* wsr.intclear */
+ case 228:
+ return 194; /* wsr.intenable */
+ case 230:
+ return 137; /* wsr.ps */
+ case 232:
+ return 179; /* wsr.exccause */
+ case 233:
+ return 220; /* wsr.debugcause */
+ case 234:
+ return 234; /* wsr.ccount */
+ case 236:
+ return 223; /* wsr.icount */
+ case 237:
+ return 226; /* wsr.icountlevel */
+ case 238:
+ return 173; /* wsr.excvaddr */
+ case 240:
+ return 237; /* wsr.ccompare0 */
+ case 241:
+ return 240; /* wsr.ccompare1 */
+ case 242:
+ return 243; /* wsr.ccompare2 */
+ case 244:
+ return 182; /* wsr.misc0 */
+ case 245:
+ return 185; /* wsr.misc1 */
+ }
+ break;
+ case 8:
+ return 89; /* moveqz */
+ case 9:
+ return 90; /* movnez */
+ case 10:
+ return 91; /* movltz */
+ case 11:
+ return 92; /* movgez */
+ }
+ break;
+ case 4:
+ case 5:
+ return 76; /* extui */
+ case 9:
+ switch (Field_op2_Slot_inst_get (insn))
+ {
+ case 0:
+ return 18; /* l32e */
+ case 4:
+ return 19; /* s32e */
+ }
+ break;
+ }
+ break;
+ case 1:
+ return 83; /* l32r */
+ case 2:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return 84; /* l8ui */
+ case 1:
+ return 80; /* l16ui */
+ case 2:
+ return 82; /* l32i */
+ case 4:
+ return 99; /* s8i */
+ case 5:
+ return 97; /* s16i */
+ case 6:
+ return 98; /* s32i */
+ case 7:
+ switch (Field_t_Slot_inst_get (insn))
+ {
+ case 0:
+ return 258; /* dpfr */
+ case 1:
+ return 259; /* dpfw */
+ case 2:
+ return 260; /* dpfro */
+ case 3:
+ return 261; /* dpfwo */
+ case 4:
+ return 252; /* dhwb */
+ case 5:
+ return 253; /* dhwbi */
+ case 6:
+ return 256; /* dhi */
+ case 7:
+ return 257; /* dii */
+ case 8:
+ switch (Field_op1_Slot_inst_get (insn))
+ {
+ case 4:
+ return 254; /* diwb */
+ case 5:
+ return 255; /* diwbi */
+ }
+ break;
+ case 12:
+ return 245; /* ipf */
+ case 14:
+ return 246; /* ihi */
+ case 15:
+ return 247; /* iii */
+ }
+ break;
+ case 9:
+ return 81; /* l16si */
+ case 10:
+ return 88; /* movi */
+ case 12:
+ return 37; /* addi */
+ case 13:
+ return 38; /* addmi */
+ }
+ break;
+ case 5:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 74; /* call0 */
+ case 1:
+ return 7; /* call4 */
+ case 2:
+ return 6; /* call8 */
+ case 3:
+ return 5; /* call12 */
+ }
+ break;
+ case 6:
+ switch (Field_n_Slot_inst_get (insn))
+ {
+ case 0:
+ return 78; /* j */
+ case 1:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return 70; /* beqz */
+ case 1:
+ return 71; /* bnez */
+ case 2:
+ return 73; /* bltz */
+ case 3:
+ return 72; /* bgez */
+ }
+ break;
+ case 2:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return 50; /* beqi */
+ case 1:
+ return 51; /* bnei */
+ case 2:
+ return 53; /* blti */
+ case 3:
+ return 52; /* bgei */
+ }
+ break;
+ case 3:
+ switch (Field_m_Slot_inst_get (insn))
+ {
+ case 0:
+ return 11; /* entry */
+ case 1:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 8:
+ return 85; /* loop */
+ case 9:
+ return 86; /* loopnez */
+ case 10:
+ return 87; /* loopgtz */
+ }
+ break;
+ case 2:
+ return 57; /* bltui */
+ case 3:
+ return 56; /* bgeui */
+ }
+ break;
+ }
+ break;
+ case 7:
+ switch (Field_r_Slot_inst_get (insn))
+ {
+ case 0:
+ return 65; /* bnone */
+ case 1:
+ return 58; /* beq */
+ case 2:
+ return 61; /* blt */
+ case 3:
+ return 63; /* bltu */
+ case 4:
+ return 66; /* ball */
+ case 5:
+ return 68; /* bbc */
+ case 6:
+ case 7:
+ return 54; /* bbci */
+ case 8:
+ return 64; /* bany */
+ case 9:
+ return 59; /* bne */
+ case 10:
+ return 60; /* bge */
+ case 11:
+ return 62; /* bgeu */
+ case 12:
+ return 67; /* bnall */
+ case 13:
+ return 69; /* bbs */
+ case 14:
+ case 15:
+ return 55; /* bbsi */
+ }
+ break;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst16b_get (insn))
+ {
+ case 12:
+ switch (Field_i_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 33; /* movi.n */
+ case 1:
+ switch (Field_z_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 28; /* beqz.n */
+ case 1:
+ return 29; /* bnez.n */
+ }
+ break;
+ }
+ break;
+ case 13:
+ switch (Field_r_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 32; /* mov.n */
+ case 15:
+ switch (Field_t_Slot_inst16b_get (insn))
+ {
+ case 0:
+ return 35; /* ret.n */
+ case 1:
+ return 15; /* retw.n */
+ case 2:
+ return 197; /* break.n */
+ case 3:
+ if (Field_s_Slot_inst16b_get (insn) == 0)
+ return 34; /* nop.n */
+ break;
+ case 6:
+ if (Field_s_Slot_inst16b_get (insn) == 0)
+ return 30; /* ill.n */
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ switch (Field_op0_Slot_inst16a_get (insn))
+ {
+ case 8:
+ return 31; /* l32i.n */
+ case 9:
+ return 36; /* s32i.n */
+ case 10:
+ return 26; /* add.n */
+ case 11:
+ return 27; /* addi.n */
+ }
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x800000;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc00000;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x800000) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc00000) == 0x800000)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe00000) == 0xc00000)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[16] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int op0 = (insn[0] >> 4) & 0xf;
+ return length_table[op0];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 1 /* big-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 39 /* num_fields */,
+ 70, operands,
+ 235, iclasses,
+ 291, opcodes, 0,
+ 1, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 0, interfaces, 0,
+ 0, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
- Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#include "qemu/osdep.h"
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "PTEVADDR", 83, 0 },
- { "DDR", 104, 0 },
- { "176", 176, 0 },
- { "208", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "LITBASE", 5, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "RASID", 90, 0 },
- { "ITLBCFG", 91, 0 },
- { "DTLBCFG", 92, 0 }
-};
-
-#define NUM_SYSREGS 49
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 0
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 17, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EPS2", 15, 0 },
- { "EPS3", 15, 0 },
- { "EPS4", 15, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSRING", 2, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 4, 0 },
- { "WindowStart", 16, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "LITBADDR", 20, 0 },
- { "LITBEN", 1, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 17, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "ASID3", 8, 0 },
- { "ASID2", 8, 0 },
- { "ASID1", 8, 0 },
- { "INSTPGSZID4", 2, 0 },
- { "DATAPGSZID4", 2, 0 },
- { "PTBASE", 10, 0 }
-};
-
-#define NUM_STATES 58
-
-/* Macros for xtensa_state numbers (for use in iclasses because the
- state numbers are not available when the iclass table is generated). */
-
-#define STATE_LCOUNT 0
-#define STATE_PC 1
-#define STATE_ICOUNT 2
-#define STATE_DDR 3
-#define STATE_INTERRUPT 4
-#define STATE_CCOUNT 5
-#define STATE_XTSYNC 6
-#define STATE_EPC1 7
-#define STATE_EPC2 8
-#define STATE_EPC3 9
-#define STATE_EPC4 10
-#define STATE_EXCSAVE1 11
-#define STATE_EXCSAVE2 12
-#define STATE_EXCSAVE3 13
-#define STATE_EXCSAVE4 14
-#define STATE_EPS2 15
-#define STATE_EPS3 16
-#define STATE_EPS4 17
-#define STATE_EXCCAUSE 18
-#define STATE_PSINTLEVEL 19
-#define STATE_PSUM 20
-#define STATE_PSWOE 21
-#define STATE_PSRING 22
-#define STATE_PSEXCM 23
-#define STATE_DEPC 24
-#define STATE_EXCVADDR 25
-#define STATE_WindowBase 26
-#define STATE_WindowStart 27
-#define STATE_PSCALLINC 28
-#define STATE_PSOWB 29
-#define STATE_LBEG 30
-#define STATE_LEND 31
-#define STATE_SAR 32
-#define STATE_LITBADDR 33
-#define STATE_LITBEN 34
-#define STATE_MISC0 35
-#define STATE_MISC1 36
-#define STATE_InOCDMode 37
-#define STATE_INTENABLE 38
-#define STATE_DBREAKA0 39
-#define STATE_DBREAKC0 40
-#define STATE_DBREAKA1 41
-#define STATE_DBREAKC1 42
-#define STATE_IBREAKA0 43
-#define STATE_IBREAKA1 44
-#define STATE_IBREAKENABLE 45
-#define STATE_ICOUNTLEVEL 46
-#define STATE_DEBUGCAUSE 47
-#define STATE_DBNUM 48
-#define STATE_CCOMPARE0 49
-#define STATE_CCOMPARE1 50
-#define STATE_CCOMPARE2 51
-#define STATE_ASID3 52
-#define STATE_ASID2 53
-#define STATE_ASID1 54
-#define STATE_INSTPGSZID4 55
-#define STATE_DATAPGSZID4 56
-#define STATE_PTBASE 57
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-\f
-/* Functional units. */
-
-static xtensa_funcUnit_internal funcUnits[] = {
-
-};
-
-\f
-/* Register files. */
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", 0, 32, 64 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
-
-};
-
-\f
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-Operand_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
- *valp = soffsetx4_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_encode (uint32 *valp)
-{
- unsigned offset_0, soffsetx4_0;
- soffsetx4_0 = *valp;
- offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
- *valp = offset_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- uimm12x8_0 = imm12_0 << 3;
- *valp = uimm12x8_0;
- return 0;
-}
-
-static int
-Operand_uimm12x8_encode (uint32 *valp)
-{
- unsigned imm12_0, uimm12x8_0;
- uimm12x8_0 = *valp;
- imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
- *valp = imm12_0;
- return 0;
-}
-
-static int
-Operand_simm4_decode (uint32 *valp)
-{
- unsigned simm4_0, mn_0;
- mn_0 = *valp & 0xf;
- simm4_0 = ((int) mn_0 << 28) >> 28;
- *valp = simm4_0;
- return 0;
-}
-
-static int
-Operand_simm4_encode (uint32 *valp)
-{
- unsigned mn_0, simm4_0;
- simm4_0 = *valp;
- mn_0 = (simm4_0 & 0xf);
- *valp = mn_0;
- return 0;
-}
-
-static int
-Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_arr_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ars_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_art_encode (uint32 *valp)
-{
- return (*valp & ~0xf) != 0;
-}
-
-static int
-Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar0_encode (uint32 *valp)
-{
- return (*valp & ~0x3f) != 0;
-}
-
-static int
-Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar4_encode (uint32 *valp)
-{
- return (*valp & ~0x3f) != 0;
-}
-
-static int
-Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar8_encode (uint32 *valp)
-{
- return (*valp & ~0x3f) != 0;
-}
-
-static int
-Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ar12_encode (uint32 *valp)
-{
- return (*valp & ~0x3f) != 0;
-}
-
-static int
-Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-Operand_ars_entry_encode (uint32 *valp)
-{
- return (*valp & ~0x3f) != 0;
-}
-
-static int
-Operand_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_0, r_0;
- r_0 = *valp & 0xf;
- immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2;
- *valp = immrx4_0;
- return 0;
-}
-
-static int
-Operand_immrx4_encode (uint32 *valp)
-{
- unsigned r_0, immrx4_0;
- immrx4_0 = *valp;
- r_0 = ((immrx4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_0, r_0;
- r_0 = *valp & 0xf;
- lsi4x4_0 = r_0 << 2;
- *valp = lsi4x4_0;
- return 0;
-}
-
-static int
-Operand_lsi4x4_encode (uint32 *valp)
-{
- unsigned r_0, lsi4x4_0;
- lsi4x4_0 = *valp;
- r_0 = ((lsi4x4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_simm7_decode (uint32 *valp)
-{
- unsigned simm7_0, imm7_0;
- imm7_0 = *valp & 0x7f;
- simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
- *valp = simm7_0;
- return 0;
-}
-
-static int
-Operand_simm7_encode (uint32 *valp)
-{
- unsigned imm7_0, simm7_0;
- simm7_0 = *valp;
- imm7_0 = (simm7_0 & 0x7f);
- *valp = imm7_0;
- return 0;
-}
-
-static int
-Operand_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_0, imm6_0;
- imm6_0 = *valp & 0x3f;
- uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0);
- *valp = uimm6_0;
- return 0;
-}
-
-static int
-Operand_uimm6_encode (uint32 *valp)
-{
- unsigned imm6_0, uimm6_0;
- uimm6_0 = *valp;
- imm6_0 = (uimm6_0 - 0x4) & 0x3f;
- *valp = imm6_0;
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_0, t_0;
- t_0 = *valp & 0xf;
- ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
- *valp = ai4const_0;
- return 0;
-}
-
-static int
-Operand_ai4const_encode (uint32 *valp)
-{
- unsigned t_0, ai4const_0;
- ai4const_0 = *valp;
- switch (ai4const_0)
- {
- case 0xffffffff: t_0 = 0; break;
- case 0x1: t_0 = 0x1; break;
- case 0x2: t_0 = 0x2; break;
- case 0x3: t_0 = 0x3; break;
- case 0x4: t_0 = 0x4; break;
- case 0x5: t_0 = 0x5; break;
- case 0x6: t_0 = 0x6; break;
- case 0x7: t_0 = 0x7; break;
- case 0x8: t_0 = 0x8; break;
- case 0x9: t_0 = 0x9; break;
- case 0xa: t_0 = 0xa; break;
- case 0xb: t_0 = 0xb; break;
- case 0xc: t_0 = 0xc; break;
- case 0xd: t_0 = 0xd; break;
- case 0xe: t_0 = 0xe; break;
- default: t_0 = 0xf; break;
- }
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_b4const_decode (uint32 *valp)
-{
- unsigned b4const_0, r_0;
- r_0 = *valp & 0xf;
- b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
- *valp = b4const_0;
- return 0;
-}
-
-static int
-Operand_b4const_encode (uint32 *valp)
-{
- unsigned r_0, b4const_0;
- b4const_0 = *valp;
- switch (b4const_0)
- {
- case 0xffffffff: r_0 = 0; break;
- case 0x1: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_0, r_0;
- r_0 = *valp & 0xf;
- b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
- *valp = b4constu_0;
- return 0;
-}
-
-static int
-Operand_b4constu_encode (uint32 *valp)
-{
- unsigned r_0, b4constu_0;
- b4constu_0 = *valp;
- switch (b4constu_0)
- {
- case 0x8000: r_0 = 0; break;
- case 0x10000: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
-}
-
-static int
-Operand_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8_0 = imm8_0;
- *valp = uimm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8_0;
- uimm8_0 = *valp;
- imm8_0 = (uimm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x2_0 = imm8_0 << 1;
- *valp = uimm8x2_0;
- return 0;
-}
-
-static int
-Operand_uimm8x2_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8x2_0;
- uimm8x2_0 = *valp;
- imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x4_0 = imm8_0 << 2;
- *valp = uimm8x4_0;
- return 0;
-}
-
-static int
-Operand_uimm8x4_encode (uint32 *valp)
-{
- unsigned imm8_0, uimm8x4_0;
- uimm8x4_0 = *valp;
- imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_0, op2_0;
- op2_0 = *valp & 0xf;
- uimm4x16_0 = op2_0 << 4;
- *valp = uimm4x16_0;
- return 0;
-}
-
-static int
-Operand_uimm4x16_encode (uint32 *valp)
-{
- unsigned op2_0, uimm4x16_0;
- uimm4x16_0 = *valp;
- op2_0 = ((uimm4x16_0 >> 4) & 0xf);
- *valp = op2_0;
- return 0;
-}
-
-static int
-Operand_simm8_decode (uint32 *valp)
-{
- unsigned simm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8_0 = ((int) imm8_0 << 24) >> 24;
- *valp = simm8_0;
- return 0;
-}
-
-static int
-Operand_simm8_encode (uint32 *valp)
-{
- unsigned imm8_0, simm8_0;
- simm8_0 = *valp;
- imm8_0 = (simm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
- *valp = simm8x256_0;
- return 0;
-}
-
-static int
-Operand_simm8x256_encode (uint32 *valp)
-{
- unsigned imm8_0, simm8x256_0;
- simm8x256_0 = *valp;
- imm8_0 = ((simm8x256_0 >> 8) & 0xff);
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_0, imm12b_0;
- imm12b_0 = *valp & 0xfff;
- simm12b_0 = ((int) imm12b_0 << 20) >> 20;
- *valp = simm12b_0;
- return 0;
-}
-
-static int
-Operand_simm12b_encode (uint32 *valp)
-{
- unsigned imm12b_0, simm12b_0;
- simm12b_0 = *valp;
- imm12b_0 = (simm12b_0 & 0xfff);
- *valp = imm12b_0;
- return 0;
-}
-
-static int
-Operand_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_0, sal_0;
- sal_0 = *valp & 0x1f;
- msalp32_0 = 0x20 - sal_0;
- *valp = msalp32_0;
- return 0;
-}
-
-static int
-Operand_msalp32_encode (uint32 *valp)
-{
- unsigned sal_0, msalp32_0;
- msalp32_0 = *valp;
- sal_0 = (0x20 - msalp32_0) & 0x1f;
- *valp = sal_0;
- return 0;
-}
-
-static int
-Operand_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_0, op2_0;
- op2_0 = *valp & 0xf;
- op2p1_0 = op2_0 + 0x1;
- *valp = op2p1_0;
- return 0;
-}
-
-static int
-Operand_op2p1_encode (uint32 *valp)
-{
- unsigned op2_0, op2p1_0;
- op2p1_0 = *valp;
- op2_0 = (op2p1_0 - 0x1) & 0xf;
- *valp = op2_0;
- return 0;
-}
-
-static int
-Operand_label8_decode (uint32 *valp)
-{
- unsigned label8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
- *valp = label8_0;
- return 0;
-}
-
-static int
-Operand_label8_encode (uint32 *valp)
-{
- unsigned imm8_0, label8_0;
- label8_0 = *valp;
- imm8_0 = (label8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_decode (uint32 *valp)
-{
- unsigned ulabel8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0);
- *valp = ulabel8_0;
- return 0;
-}
-
-static int
-Operand_ulabel8_encode (uint32 *valp)
-{
- unsigned imm8_0, ulabel8_0;
- ulabel8_0 = *valp;
- imm8_0 = (ulabel8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
-}
-
-static int
-Operand_ulabel8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_decode (uint32 *valp)
-{
- unsigned label12_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
- *valp = label12_0;
- return 0;
-}
-
-static int
-Operand_label12_encode (uint32 *valp)
-{
- unsigned imm12_0, label12_0;
- label12_0 = *valp;
- imm12_0 = (label12_0 - 0x4) & 0xfff;
- *valp = imm12_0;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_decode (uint32 *valp)
-{
- unsigned soffset_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
- *valp = soffset_0;
- return 0;
-}
-
-static int
-Operand_soffset_encode (uint32 *valp)
-{
- unsigned offset_0, soffset_0;
- soffset_0 = *valp;
- offset_0 = (soffset_0 - 0x4) & 0x3ffff;
- *valp = offset_0;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_0, imm16_0;
- imm16_0 = *valp & 0xffff;
- uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2;
- *valp = uimm16x4_0;
- return 0;
-}
-
-static int
-Operand_uimm16x4_encode (uint32 *valp)
-{
- unsigned imm16_0, uimm16x4_0;
- uimm16x4_0 = *valp;
- imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
- *valp = imm16_0;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_immt_decode (uint32 *valp)
-{
- unsigned immt_0, t_0;
- t_0 = *valp & 0xf;
- immt_0 = t_0;
- *valp = immt_0;
- return 0;
-}
-
-static int
-Operand_immt_encode (uint32 *valp)
-{
- unsigned t_0, immt_0;
- immt_0 = *valp;
- t_0 = immt_0 & 0xf;
- *valp = t_0;
- return 0;
-}
-
-static int
-Operand_imms_decode (uint32 *valp)
-{
- unsigned imms_0, s_0;
- s_0 = *valp & 0xf;
- imms_0 = s_0;
- *valp = imms_0;
- return 0;
-}
-
-static int
-Operand_imms_encode (uint32 *valp)
-{
- unsigned s_0, imms_0;
- imms_0 = *valp;
- s_0 = imms_0 & 0xf;
- *valp = s_0;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", 10, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffsetx4_encode, Operand_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", 3, -1, 0,
- 0,
- Operand_uimm12x8_encode, Operand_uimm12x8_decode,
- 0, 0 },
- { "simm4", 26, -1, 0,
- 0,
- Operand_simm4_encode, Operand_simm4_decode,
- 0, 0 },
- { "arr", 14, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_arr_encode, Operand_arr_decode,
- 0, 0 },
- { "ars", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "*ars_invisible", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "art", 0, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_art_encode, Operand_art_decode,
- 0, 0 },
- { "ar0", 35, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar0_encode, Operand_ar0_decode,
- 0, 0 },
- { "ar4", 36, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar4_encode, Operand_ar4_decode,
- 0, 0 },
- { "ar8", 37, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar8_encode, Operand_ar8_decode,
- 0, 0 },
- { "ar12", 38, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar12_encode, Operand_ar12_decode,
- 0, 0 },
- { "ars_entry", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_entry_encode, Operand_ars_entry_decode,
- 0, 0 },
- { "immrx4", 14, -1, 0,
- 0,
- Operand_immrx4_encode, Operand_immrx4_decode,
- 0, 0 },
- { "lsi4x4", 14, -1, 0,
- 0,
- Operand_lsi4x4_encode, Operand_lsi4x4_decode,
- 0, 0 },
- { "simm7", 34, -1, 0,
- 0,
- Operand_simm7_encode, Operand_simm7_decode,
- 0, 0 },
- { "uimm6", 33, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm6_encode, Operand_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", 0, -1, 0,
- 0,
- Operand_ai4const_encode, Operand_ai4const_decode,
- 0, 0 },
- { "b4const", 14, -1, 0,
- 0,
- Operand_b4const_encode, Operand_b4const_decode,
- 0, 0 },
- { "b4constu", 14, -1, 0,
- 0,
- Operand_b4constu_encode, Operand_b4constu_decode,
- 0, 0 },
- { "uimm8", 4, -1, 0,
- 0,
- Operand_uimm8_encode, Operand_uimm8_decode,
- 0, 0 },
- { "uimm8x2", 4, -1, 0,
- 0,
- Operand_uimm8x2_encode, Operand_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", 4, -1, 0,
- 0,
- Operand_uimm8x4_encode, Operand_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", 13, -1, 0,
- 0,
- Operand_uimm4x16_encode, Operand_uimm4x16_decode,
- 0, 0 },
- { "simm8", 4, -1, 0,
- 0,
- Operand_simm8_encode, Operand_simm8_decode,
- 0, 0 },
- { "simm8x256", 4, -1, 0,
- 0,
- Operand_simm8x256_encode, Operand_simm8x256_decode,
- 0, 0 },
- { "simm12b", 6, -1, 0,
- 0,
- Operand_simm12b_encode, Operand_simm12b_decode,
- 0, 0 },
- { "msalp32", 18, -1, 0,
- 0,
- Operand_msalp32_encode, Operand_msalp32_decode,
- 0, 0 },
- { "op2p1", 13, -1, 0,
- 0,
- Operand_op2p1_encode, Operand_op2p1_decode,
- 0, 0 },
- { "label8", 4, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label8_encode, Operand_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", 4, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_ulabel8_encode, Operand_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", 3, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label12_encode, Operand_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", 10, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffset_encode, Operand_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", 7, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm16x4_encode, Operand_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "immt", 0, -1, 0,
- 0,
- Operand_immt_encode, Operand_immt_decode,
- 0, 0 },
- { "imms", 5, -1, 0,
- 0,
- Operand_imms_encode, Operand_imms_decode,
- 0, 0 },
- { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
- { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
- { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
- { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
- { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
- { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
- { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
- { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
- { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
- { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
- { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSRING }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 10 /* ar12 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 9 /* ar8 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 8 /* ar4 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 10 /* ar12 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 9 /* ar8 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 8 /* ar4 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { 11 /* ars_entry */ }, 's' },
- { { 4 /* ars */ }, 'i' },
- { { 1 /* uimm12x8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { 2 /* simm4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 12 /* immrx4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 12 /* immrx4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 16 /* ai4const */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 15 /* uimm6 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 13 /* lsi4x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { 4 /* ars */ }, 'o' },
- { { 14 /* simm7 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 13 /* lsi4x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 23 /* simm8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 24 /* simm8x256 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 17 /* b4const */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 37 /* bbi */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 18 /* b4constu */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 30 /* label12 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 7 /* ar0 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 7 /* ar0 */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 52 /* sae */ }, 'i' },
- { { 27 /* op2p1 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { 31 /* soffset */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 32 /* uimm16x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 19 /* uimm8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 29 /* ulabel8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 29 /* ulabel8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 25 /* simm12b */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { 3 /* arr */ }, 'm' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 19 /* uimm8 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { 56 /* sas */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 26 /* msalp32 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 54 /* sargt */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 40 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 40 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'o' },
- { { STATE_LITBEN }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'm' },
- { { STATE_LITBEN }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { 40 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { 40 /* s */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { 34 /* imms */ }, 'i' },
- { { 33 /* immt */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { 34 /* imms */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'm' },
- { { STATE_EXCVADDR }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'i' },
- { { STATE_ASID2 }, 'i' },
- { { STATE_ASID1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'o' },
- { { STATE_ASID2 }, 'o' },
- { { STATE_ASID1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'm' },
- { { STATE_ASID2 }, 'm' },
- { { STATE_ASID1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_176_args,
- 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_208_args,
- 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdo */,
- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_rasid_args,
- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_rasid_args,
- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_rasid_args,
- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
- 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
- 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
- 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
- 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_ldpte */,
- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwitlba */,
- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwdtlba */,
- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 }
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80200;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2300;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1500;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c0000;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580000;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x540000;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0000;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb0000;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70000;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6c0000;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x804;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60000;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10f;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4300;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5300;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x94;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4830;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4831;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4816;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4930;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4931;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4916;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa000;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb000;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc800;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc00;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd60f;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8000;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd000;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc000;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd30f;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00f;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9000;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200c00;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200d00;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680000;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x690000;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6b0000;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6a0000;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700600;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700e00;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f0000;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6e0000;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700100;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700900;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700a00;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700200;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700b00;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700300;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700800;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700000;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700400;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700c00;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700500;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700d00;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x640000;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x650000;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x670000;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x660000;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500000;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0000;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200100;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200900;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200200;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0800;
-}
-
-static void
-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0900;
-}
-
-static void
-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0a00;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200a00;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1006;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0200;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20000;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200500;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200600;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200400;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x104;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x204;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x304;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1a;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x19;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x12;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x14;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0200;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0200;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10200;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20200;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30200;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600;
-}
-
-static void
-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130;
-}
-
-static void
-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131;
-}
-
-static void
-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x116;
-}
-
-static void
-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230;
-}
-
-static void
-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x231;
-}
-
-static void
-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x216;
-}
-
-static void
-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30;
-}
-
-static void
-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31;
-}
-
-static void
-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x330;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x331;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x316;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x531;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x516;
-}
-
-static void
-Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb030;
-}
-
-static void
-Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd030;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe630;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe631;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe616;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb130;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb131;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb116;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd130;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd131;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd116;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb230;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb231;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb216;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd230;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd231;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd216;
-}
-
-static void
-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb330;
-}
-
-static void
-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb331;
-}
-
-static void
-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb316;
-}
-
-static void
-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd330;
-}
-
-static void
-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd331;
-}
-
-static void
-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd316;
-}
-
-static void
-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb430;
-}
-
-static void
-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb431;
-}
-
-static void
-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb416;
-}
-
-static void
-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd430;
-}
-
-static void
-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd431;
-}
-
-static void
-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd416;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc230;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc231;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc216;
-}
-
-static void
-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc330;
-}
-
-static void
-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc331;
-}
-
-static void
-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc316;
-}
-
-static void
-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc430;
-}
-
-static void
-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc431;
-}
-
-static void
-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc416;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xee30;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xee31;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xee16;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc030;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc031;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc016;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe830;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe831;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe816;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf430;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf431;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf416;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf530;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf531;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf516;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xeb30;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10300;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe230;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe231;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe331;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe430;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe431;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe416;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd20f;
-}
-
-static void
-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9030;
-}
-
-static void
-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9031;
-}
-
-static void
-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9016;
-}
-
-static void
-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa030;
-}
-
-static void
-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa031;
-}
-
-static void
-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa016;
-}
-
-static void
-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9130;
-}
-
-static void
-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9131;
-}
-
-static void
-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9116;
-}
-
-static void
-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa130;
-}
-
-static void
-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa131;
-}
-
-static void
-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa116;
-}
-
-static void
-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8030;
-}
-
-static void
-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8031;
-}
-
-static void
-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8016;
-}
-
-static void
-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8130;
-}
-
-static void
-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8131;
-}
-
-static void
-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8116;
-}
-
-static void
-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6030;
-}
-
-static void
-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6031;
-}
-
-static void
-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6016;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe930;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe931;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe916;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xec30;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xec31;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xec16;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed30;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed31;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed16;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6830;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6831;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6816;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1f;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10e1f;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xea30;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xea31;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xea16;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf030;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf031;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf016;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf130;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf131;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf116;
-}
-
-static void
-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf230;
-}
-
-static void
-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf231;
-}
-
-static void
-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf216;
-}
-
-static void
-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2c0700;
-}
-
-static void
-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e0700;
-}
-
-static void
-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f0700;
-}
-
-static void
-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f;
-}
-
-static void
-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x21f;
-}
-
-static void
-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x11f;
-}
-
-static void
-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31f;
-}
-
-static void
-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x240700;
-}
-
-static void
-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x250700;
-}
-
-static void
-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280740;
-}
-
-static void
-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280750;
-}
-
-static void
-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x260700;
-}
-
-static void
-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270700;
-}
-
-static void
-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200700;
-}
-
-static void
-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210700;
-}
-
-static void
-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x220700;
-}
-
-static void
-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230700;
-}
-
-static void
-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x91f;
-}
-
-static void
-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81f;
-}
-
-static void
-Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5331;
-}
-
-static void
-Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5330;
-}
-
-static void
-Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5316;
-}
-
-static void
-Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a30;
-}
-
-static void
-Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a31;
-}
-
-static void
-Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a16;
-}
-
-static void
-Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b30;
-}
-
-static void
-Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b31;
-}
-
-static void
-Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b16;
-}
-
-static void
-Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c30;
-}
-
-static void
-Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c31;
-}
-
-static void
-Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c16;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc05;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd05;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb05;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf05;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe05;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x405;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x305;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x705;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x605;
-}
-
-static void
-Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1f;
-}
-
-static void
-Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x105;
-}
-
-static void
-Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x905;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe04;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf04;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
- Opcode_rsr_176_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
- Opcode_rsr_208_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
- Opcode_rsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
- Opcode_wsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
- Opcode_xsr_rasid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
- Opcode_ldpte_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
- Opcode_hwwitlba_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
- Opcode_hwwdtlba_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0
-};
-
-\f
-/* Opcode table. */
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", 0 /* xt_iclass_excw */,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", 1 /* xt_iclass_rfe */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", 2 /* xt_iclass_rfde */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", 3 /* xt_iclass_syscall */,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "simcall", 4 /* xt_iclass_simcall */,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "call12", 5 /* xt_iclass_call12 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", 6 /* xt_iclass_call8 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", 7 /* xt_iclass_call4 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", 8 /* xt_iclass_callx12 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", 9 /* xt_iclass_callx8 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", 10 /* xt_iclass_callx4 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", 11 /* xt_iclass_entry */,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", 12 /* xt_iclass_movsp */,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", 13 /* xt_iclass_rotw */,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", 14 /* xt_iclass_retw */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", 14 /* xt_iclass_retw */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", 15 /* xt_iclass_rfwou */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", 15 /* xt_iclass_rfwou */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", 16 /* xt_iclass_l32e */,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", 17 /* xt_iclass_s32e */,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", 24 /* xt_iclass_add.n */,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", 25 /* xt_iclass_addi.n */,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", 26 /* xt_iclass_bz6 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", 26 /* xt_iclass_bz6 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", 27 /* xt_iclass_ill.n */,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", 28 /* xt_iclass_loadi4 */,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", 29 /* xt_iclass_mov.n */,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", 30 /* xt_iclass_movi.n */,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", 31 /* xt_iclass_nopn */,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", 32 /* xt_iclass_retn */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", 33 /* xt_iclass_storei4 */,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "addi", 34 /* xt_iclass_addi */,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", 35 /* xt_iclass_addmi */,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", 36 /* xt_iclass_addsub */,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", 37 /* xt_iclass_bit */,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", 37 /* xt_iclass_bit */,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", 37 /* xt_iclass_bit */,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", 38 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", 38 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", 38 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", 38 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", 39 /* xt_iclass_bsi8b */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", 39 /* xt_iclass_bsi8b */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", 40 /* xt_iclass_bsi8u */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", 40 /* xt_iclass_bsi8u */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", 41 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", 42 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", 42 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", 42 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", 42 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", 43 /* xt_iclass_call0 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", 44 /* xt_iclass_callx0 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", 45 /* xt_iclass_exti */,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", 46 /* xt_iclass_ill */,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", 47 /* xt_iclass_jump */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", 48 /* xt_iclass_jumpx */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", 49 /* xt_iclass_l16ui */,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", 50 /* xt_iclass_l16si */,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", 51 /* xt_iclass_l32i */,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", 52 /* xt_iclass_l32r */,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", 53 /* xt_iclass_l8i */,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", 54 /* xt_iclass_loop */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", 55 /* xt_iclass_loopz */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", 55 /* xt_iclass_loopz */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", 56 /* xt_iclass_movi */,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", 57 /* xt_iclass_movz */,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", 57 /* xt_iclass_movz */,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", 57 /* xt_iclass_movz */,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", 57 /* xt_iclass_movz */,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", 58 /* xt_iclass_neg */,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", 58 /* xt_iclass_neg */,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", 59 /* xt_iclass_nop */,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", 60 /* xt_iclass_return */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "s16i", 61 /* xt_iclass_s16i */,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", 62 /* xt_iclass_s32i */,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s8i", 63 /* xt_iclass_s8i */,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", 64 /* xt_iclass_sar */,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", 64 /* xt_iclass_sar */,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", 64 /* xt_iclass_sar */,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", 64 /* xt_iclass_sar */,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", 65 /* xt_iclass_sari */,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", 66 /* xt_iclass_shifts */,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", 67 /* xt_iclass_shiftst */,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", 68 /* xt_iclass_shiftt */,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", 68 /* xt_iclass_shiftt */,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", 69 /* xt_iclass_slli */,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", 70 /* xt_iclass_srai */,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", 71 /* xt_iclass_srli */,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", 72 /* xt_iclass_memw */,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", 73 /* xt_iclass_extw */,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", 74 /* xt_iclass_isync */,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", 75 /* xt_iclass_sync */,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", 75 /* xt_iclass_sync */,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", 75 /* xt_iclass_sync */,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", 76 /* xt_iclass_rsil */,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", 77 /* xt_iclass_rsr.lend */,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", 78 /* xt_iclass_wsr.lend */,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", 79 /* xt_iclass_xsr.lend */,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", 86 /* xt_iclass_rsr.sar */,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", 87 /* xt_iclass_wsr.sar */,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", 88 /* xt_iclass_xsr.sar */,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.176", 92 /* xt_iclass_rsr.176 */,
- 0,
- Opcode_rsr_176_encode_fns, 0, 0 },
- { "rsr.208", 93 /* xt_iclass_rsr.208 */,
- 0,
- Opcode_rsr_208_encode_fns, 0, 0 },
- { "rsr.ps", 94 /* xt_iclass_rsr.ps */,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", 95 /* xt_iclass_wsr.ps */,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", 96 /* xt_iclass_xsr.ps */,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", 133 /* xt_iclass_rsr.depc */,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", 134 /* xt_iclass_wsr.depc */,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", 135 /* xt_iclass_xsr.depc */,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", 145 /* xt_iclass_rsr.prid */,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rfi", 146 /* xt_iclass_rfi */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", 147 /* xt_iclass_wait */,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", 149 /* xt_iclass_wsr.intset */,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", 154 /* xt_iclass_break */,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", 155 /* xt_iclass_break.n */,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", 180 /* xt_iclass_rsr.icount */,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", 181 /* xt_iclass_wsr.icount */,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", 182 /* xt_iclass_xsr.icount */,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "rfdo", 189 /* xt_iclass_rfdo */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", 190 /* xt_iclass_rfdd */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "ipf", 203 /* xt_iclass_icache */,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", 203 /* xt_iclass_icache */,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "iii", 204 /* xt_iclass_icache_inv */,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", 205 /* xt_iclass_licx */,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", 205 /* xt_iclass_licx */,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", 206 /* xt_iclass_sicx */,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", 206 /* xt_iclass_sicx */,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", 207 /* xt_iclass_dcache */,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", 207 /* xt_iclass_dcache */,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwb", 208 /* xt_iclass_dcache_ind */,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", 208 /* xt_iclass_dcache_ind */,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", 209 /* xt_iclass_dcache_inv */,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", 209 /* xt_iclass_dcache_inv */,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", 210 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", 210 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", 210 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", 210 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "sdct", 211 /* xt_iclass_sdct */,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", 212 /* xt_iclass_ldct */,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */,
- 0,
- Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */,
- 0,
- Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
- { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */,
- 0,
- Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */,
- 0,
- Opcode_rsr_rasid_encode_fns, 0, 0 },
- { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */,
- 0,
- Opcode_wsr_rasid_encode_fns, 0, 0 },
- { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */,
- 0,
- Opcode_xsr_rasid_encode_fns, 0, 0 },
- { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */,
- 0,
- Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
- { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */,
- 0,
- Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
- { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */,
- 0,
- Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
- { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */,
- 0,
- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
- { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */,
- 0,
- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
- { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */,
- 0,
- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
- { "idtlb", 225 /* xt_iclass_idtlb */,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", 226 /* xt_iclass_rdtlb */,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", 226 /* xt_iclass_rdtlb */,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", 226 /* xt_iclass_rdtlb */,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", 227 /* xt_iclass_wdtlb */,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", 228 /* xt_iclass_iitlb */,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", 229 /* xt_iclass_ritlb */,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", 229 /* xt_iclass_ritlb */,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", 229 /* xt_iclass_ritlb */,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", 230 /* xt_iclass_witlb */,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "ldpte", 231 /* xt_iclass_ldpte */,
- 0,
- Opcode_ldpte_encode_fns, 0, 0 },
- { "hwwitlba", 232 /* xt_iclass_hwwitlba */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_hwwitlba_encode_fns, 0, 0 },
- { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */,
- 0,
- Opcode_hwwdtlba_encode_fns, 0, 0 },
- { "nsa", 234 /* xt_iclass_nsa */,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", 234 /* xt_iclass_nsa */,
- 0,
- Opcode_nsau_encode_fns, 0, 0 }
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return 77; /* ill */
- break;
- case 2:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 96; /* ret */
- case 1:
- return 14; /* retw */
- case 2:
- return 79; /* jx */
- }
- break;
- case 3:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 75; /* callx0 */
- case 1:
- return 10; /* callx4 */
- case 2:
- return 9; /* callx8 */
- case 3:
- return 8; /* callx12 */
- }
- break;
- }
- break;
- case 1:
- return 12; /* movsp */
- case 2:
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 114; /* isync */
- case 1:
- return 115; /* rsync */
- case 2:
- return 116; /* esync */
- case 3:
- return 117; /* dsync */
- case 8:
- return 0; /* excw */
- case 12:
- return 112; /* memw */
- case 13:
- return 113; /* extw */
- case 15:
- return 95; /* nop */
- }
- }
- break;
- case 3:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return 1; /* rfe */
- case 2:
- return 2; /* rfde */
- case 4:
- return 16; /* rfwo */
- case 5:
- return 17; /* rfwu */
- }
- break;
- case 1:
- return 188; /* rfi */
- }
- break;
- case 4:
- return 196; /* break */
- case 5:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 3; /* syscall */
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 4; /* simcall */
- break;
- }
- break;
- case 6:
- return 118; /* rsil */
- case 7:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 189; /* waiti */
- break;
- }
- break;
- case 1:
- return 47; /* and */
- case 2:
- return 48; /* or */
- case 3:
- return 49; /* xor */
- case 4:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 100; /* ssr */
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 101; /* ssl */
- break;
- case 2:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 102; /* ssa8l */
- break;
- case 3:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 103; /* ssa8b */
- break;
- case 4:
- if (Field_thi3_Slot_inst_get (insn) == 0)
- return 104; /* ssai */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 13; /* rotw */
- break;
- case 14:
- return 289; /* nsa */
- case 15:
- return 290; /* nsau */
- }
- break;
- case 5:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 1:
- return 287; /* hwwitlba */
- case 3:
- return 283; /* ritlb0 */
- case 4:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 281; /* iitlb */
- break;
- case 5:
- return 282; /* pitlb */
- case 6:
- return 285; /* witlb */
- case 7:
- return 284; /* ritlb1 */
- case 9:
- return 288; /* hwwdtlba */
- case 11:
- return 278; /* rdtlb0 */
- case 12:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 276; /* idtlb */
- break;
- case 13:
- return 277; /* pdtlb */
- case 14:
- return 280; /* wdtlb */
- case 15:
- return 279; /* rdtlb1 */
- }
- break;
- case 6:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return 93; /* neg */
- case 1:
- return 94; /* abs */
- }
- break;
- case 8:
- return 39; /* add */
- case 9:
- return 41; /* addx2 */
- case 10:
- return 42; /* addx4 */
- case 11:
- return 43; /* addx8 */
- case 12:
- return 40; /* sub */
- case 13:
- return 44; /* subx2 */
- case 14:
- return 45; /* subx4 */
- case 15:
- return 46; /* subx8 */
- }
- break;
- case 1:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- case 1:
- return 109; /* slli */
- case 2:
- case 3:
- return 110; /* srai */
- case 4:
- return 111; /* srli */
- case 6:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 127; /* xsr.lbeg */
- case 1:
- return 121; /* xsr.lend */
- case 2:
- return 124; /* xsr.lcount */
- case 3:
- return 130; /* xsr.sar */
- case 5:
- return 133; /* xsr.litbase */
- case 72:
- return 22; /* xsr.windowbase */
- case 73:
- return 25; /* xsr.windowstart */
- case 83:
- return 266; /* xsr.ptevaddr */
- case 90:
- return 269; /* xsr.rasid */
- case 91:
- return 272; /* xsr.itlbcfg */
- case 92:
- return 275; /* xsr.dtlbcfg */
- case 96:
- return 218; /* xsr.ibreakenable */
- case 104:
- return 230; /* xsr.ddr */
- case 128:
- return 212; /* xsr.ibreaka0 */
- case 129:
- return 215; /* xsr.ibreaka1 */
- case 144:
- return 200; /* xsr.dbreaka0 */
- case 145:
- return 206; /* xsr.dbreaka1 */
- case 160:
- return 203; /* xsr.dbreakc0 */
- case 161:
- return 209; /* xsr.dbreakc1 */
- case 177:
- return 141; /* xsr.epc1 */
- case 178:
- return 147; /* xsr.epc2 */
- case 179:
- return 153; /* xsr.epc3 */
- case 180:
- return 159; /* xsr.epc4 */
- case 192:
- return 177; /* xsr.depc */
- case 194:
- return 165; /* xsr.eps2 */
- case 195:
- return 168; /* xsr.eps3 */
- case 196:
- return 171; /* xsr.eps4 */
- case 209:
- return 144; /* xsr.excsave1 */
- case 210:
- return 150; /* xsr.excsave2 */
- case 211:
- return 156; /* xsr.excsave3 */
- case 212:
- return 162; /* xsr.excsave4 */
- case 228:
- return 195; /* xsr.intenable */
- case 230:
- return 138; /* xsr.ps */
- case 232:
- return 180; /* xsr.exccause */
- case 233:
- return 221; /* xsr.debugcause */
- case 234:
- return 235; /* xsr.ccount */
- case 236:
- return 224; /* xsr.icount */
- case 237:
- return 227; /* xsr.icountlevel */
- case 238:
- return 174; /* xsr.excvaddr */
- case 240:
- return 238; /* xsr.ccompare0 */
- case 241:
- return 241; /* xsr.ccompare1 */
- case 242:
- return 244; /* xsr.ccompare2 */
- case 244:
- return 183; /* xsr.misc0 */
- case 245:
- return 186; /* xsr.misc1 */
- }
- break;
- case 8:
- return 106; /* src */
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 107; /* srl */
- break;
- case 10:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 105; /* sll */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 108; /* sra */
- break;
- case 15:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 248; /* lict */
- case 1:
- return 250; /* sict */
- case 2:
- return 249; /* licw */
- case 3:
- return 251; /* sicw */
- case 8:
- return 263; /* ldct */
- case 9:
- return 262; /* sdct */
- case 14:
- if (Field_t_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0)
- return 231; /* rfdo */
- if (Field_t_Slot_inst_get (insn) == 1 &&
- Field_s_Slot_inst_get (insn) == 0)
- return 232; /* rfdd */
- break;
- case 15:
- return 286; /* ldpte */
- }
- break;
- }
- break;
- case 3:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 125; /* rsr.lbeg */
- case 1:
- return 119; /* rsr.lend */
- case 2:
- return 122; /* rsr.lcount */
- case 3:
- return 128; /* rsr.sar */
- case 5:
- return 131; /* rsr.litbase */
- case 72:
- return 20; /* rsr.windowbase */
- case 73:
- return 23; /* rsr.windowstart */
- case 83:
- return 265; /* rsr.ptevaddr */
- case 90:
- return 267; /* rsr.rasid */
- case 91:
- return 270; /* rsr.itlbcfg */
- case 92:
- return 273; /* rsr.dtlbcfg */
- case 96:
- return 216; /* rsr.ibreakenable */
- case 104:
- return 228; /* rsr.ddr */
- case 128:
- return 210; /* rsr.ibreaka0 */
- case 129:
- return 213; /* rsr.ibreaka1 */
- case 144:
- return 198; /* rsr.dbreaka0 */
- case 145:
- return 204; /* rsr.dbreaka1 */
- case 160:
- return 201; /* rsr.dbreakc0 */
- case 161:
- return 207; /* rsr.dbreakc1 */
- case 176:
- return 134; /* rsr.176 */
- case 177:
- return 139; /* rsr.epc1 */
- case 178:
- return 145; /* rsr.epc2 */
- case 179:
- return 151; /* rsr.epc3 */
- case 180:
- return 157; /* rsr.epc4 */
- case 192:
- return 175; /* rsr.depc */
- case 194:
- return 163; /* rsr.eps2 */
- case 195:
- return 166; /* rsr.eps3 */
- case 196:
- return 169; /* rsr.eps4 */
- case 208:
- return 135; /* rsr.208 */
- case 209:
- return 142; /* rsr.excsave1 */
- case 210:
- return 148; /* rsr.excsave2 */
- case 211:
- return 154; /* rsr.excsave3 */
- case 212:
- return 160; /* rsr.excsave4 */
- case 226:
- return 190; /* rsr.interrupt */
- case 228:
- return 193; /* rsr.intenable */
- case 230:
- return 136; /* rsr.ps */
- case 232:
- return 178; /* rsr.exccause */
- case 233:
- return 219; /* rsr.debugcause */
- case 234:
- return 233; /* rsr.ccount */
- case 235:
- return 187; /* rsr.prid */
- case 236:
- return 222; /* rsr.icount */
- case 237:
- return 225; /* rsr.icountlevel */
- case 238:
- return 172; /* rsr.excvaddr */
- case 240:
- return 236; /* rsr.ccompare0 */
- case 241:
- return 239; /* rsr.ccompare1 */
- case 242:
- return 242; /* rsr.ccompare2 */
- case 244:
- return 181; /* rsr.misc0 */
- case 245:
- return 184; /* rsr.misc1 */
- }
- break;
- case 1:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 126; /* wsr.lbeg */
- case 1:
- return 120; /* wsr.lend */
- case 2:
- return 123; /* wsr.lcount */
- case 3:
- return 129; /* wsr.sar */
- case 5:
- return 132; /* wsr.litbase */
- case 72:
- return 21; /* wsr.windowbase */
- case 73:
- return 24; /* wsr.windowstart */
- case 83:
- return 264; /* wsr.ptevaddr */
- case 90:
- return 268; /* wsr.rasid */
- case 91:
- return 271; /* wsr.itlbcfg */
- case 92:
- return 274; /* wsr.dtlbcfg */
- case 96:
- return 217; /* wsr.ibreakenable */
- case 104:
- return 229; /* wsr.ddr */
- case 128:
- return 211; /* wsr.ibreaka0 */
- case 129:
- return 214; /* wsr.ibreaka1 */
- case 144:
- return 199; /* wsr.dbreaka0 */
- case 145:
- return 205; /* wsr.dbreaka1 */
- case 160:
- return 202; /* wsr.dbreakc0 */
- case 161:
- return 208; /* wsr.dbreakc1 */
- case 177:
- return 140; /* wsr.epc1 */
- case 178:
- return 146; /* wsr.epc2 */
- case 179:
- return 152; /* wsr.epc3 */
- case 180:
- return 158; /* wsr.epc4 */
- case 192:
- return 176; /* wsr.depc */
- case 194:
- return 164; /* wsr.eps2 */
- case 195:
- return 167; /* wsr.eps3 */
- case 196:
- return 170; /* wsr.eps4 */
- case 209:
- return 143; /* wsr.excsave1 */
- case 210:
- return 149; /* wsr.excsave2 */
- case 211:
- return 155; /* wsr.excsave3 */
- case 212:
- return 161; /* wsr.excsave4 */
- case 226:
- return 191; /* wsr.intset */
- case 227:
- return 192; /* wsr.intclear */
- case 228:
- return 194; /* wsr.intenable */
- case 230:
- return 137; /* wsr.ps */
- case 232:
- return 179; /* wsr.exccause */
- case 233:
- return 220; /* wsr.debugcause */
- case 234:
- return 234; /* wsr.ccount */
- case 236:
- return 223; /* wsr.icount */
- case 237:
- return 226; /* wsr.icountlevel */
- case 238:
- return 173; /* wsr.excvaddr */
- case 240:
- return 237; /* wsr.ccompare0 */
- case 241:
- return 240; /* wsr.ccompare1 */
- case 242:
- return 243; /* wsr.ccompare2 */
- case 244:
- return 182; /* wsr.misc0 */
- case 245:
- return 185; /* wsr.misc1 */
- }
- break;
- case 8:
- return 89; /* moveqz */
- case 9:
- return 90; /* movnez */
- case 10:
- return 91; /* movltz */
- case 11:
- return 92; /* movgez */
- }
- break;
- case 4:
- case 5:
- return 76; /* extui */
- case 9:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return 18; /* l32e */
- case 4:
- return 19; /* s32e */
- }
- break;
- }
- break;
- case 1:
- return 83; /* l32r */
- case 2:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 84; /* l8ui */
- case 1:
- return 80; /* l16ui */
- case 2:
- return 82; /* l32i */
- case 4:
- return 99; /* s8i */
- case 5:
- return 97; /* s16i */
- case 6:
- return 98; /* s32i */
- case 7:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 258; /* dpfr */
- case 1:
- return 259; /* dpfw */
- case 2:
- return 260; /* dpfro */
- case 3:
- return 261; /* dpfwo */
- case 4:
- return 252; /* dhwb */
- case 5:
- return 253; /* dhwbi */
- case 6:
- return 256; /* dhi */
- case 7:
- return 257; /* dii */
- case 8:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- return 254; /* diwb */
- case 5:
- return 255; /* diwbi */
- }
- break;
- case 12:
- return 245; /* ipf */
- case 14:
- return 246; /* ihi */
- case 15:
- return 247; /* iii */
- }
- break;
- case 9:
- return 81; /* l16si */
- case 10:
- return 88; /* movi */
- case 12:
- return 37; /* addi */
- case 13:
- return 38; /* addmi */
- }
- break;
- case 5:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 74; /* call0 */
- case 1:
- return 7; /* call4 */
- case 2:
- return 6; /* call8 */
- case 3:
- return 5; /* call12 */
- }
- break;
- case 6:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 78; /* j */
- case 1:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 70; /* beqz */
- case 1:
- return 71; /* bnez */
- case 2:
- return 73; /* bltz */
- case 3:
- return 72; /* bgez */
- }
- break;
- case 2:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 50; /* beqi */
- case 1:
- return 51; /* bnei */
- case 2:
- return 53; /* blti */
- case 3:
- return 52; /* bgei */
- }
- break;
- case 3:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 11; /* entry */
- case 1:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 8:
- return 85; /* loop */
- case 9:
- return 86; /* loopnez */
- case 10:
- return 87; /* loopgtz */
- }
- break;
- case 2:
- return 57; /* bltui */
- case 3:
- return 56; /* bgeui */
- }
- break;
- }
- break;
- case 7:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 65; /* bnone */
- case 1:
- return 58; /* beq */
- case 2:
- return 61; /* blt */
- case 3:
- return 63; /* bltu */
- case 4:
- return 66; /* ball */
- case 5:
- return 68; /* bbc */
- case 6:
- case 7:
- return 54; /* bbci */
- case 8:
- return 64; /* bany */
- case 9:
- return 59; /* bne */
- case 10:
- return 60; /* bge */
- case 11:
- return 62; /* bgeu */
- case 12:
- return 67; /* bnall */
- case 13:
- return 69; /* bbs */
- case 14:
- case 15:
- return 55; /* bbsi */
- }
- break;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst16b_get (insn))
- {
- case 12:
- switch (Field_i_Slot_inst16b_get (insn))
- {
- case 0:
- return 33; /* movi.n */
- case 1:
- switch (Field_z_Slot_inst16b_get (insn))
- {
- case 0:
- return 28; /* beqz.n */
- case 1:
- return 29; /* bnez.n */
- }
- break;
- }
- break;
- case 13:
- switch (Field_r_Slot_inst16b_get (insn))
- {
- case 0:
- return 32; /* mov.n */
- case 15:
- switch (Field_t_Slot_inst16b_get (insn))
- {
- case 0:
- return 35; /* ret.n */
- case 1:
- return 15; /* retw.n */
- case 2:
- return 197; /* break.n */
- case 3:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return 34; /* nop.n */
- break;
- case 6:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return 30; /* ill.n */
- break;
- }
- break;
- }
- break;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- switch (Field_op0_Slot_inst16a_get (insn))
- {
- case 8:
- return 31; /* l32i.n */
- case 9:
- return 36; /* s32i.n */
- case 10:
- return 26; /* add.n */
- case 11:
- return 27; /* addi.n */
- }
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffffff);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0x800000;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xc00000;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0x800000) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc00000) == 0x800000)
- return 1; /* x16a */
- if ((insn[0] & 0xe00000) == 0xc00000)
- return 2; /* x16b */
- return -1;
-}
-
-static int length_table[16] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int op0 = (insn[0] >> 4) & 0xf;
- return length_table[op0];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 1 /* big-endian */,
- 3 /* insn_size */, 0,
- 3, formats, format_decoder, length_decoder,
- 3, slots,
- 39 /* num_fields */,
- 70, operands,
- 235, iclasses,
- 291, opcodes, 0,
- 1, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 0, interfaces, 0,
- 0, funcUnits, 0
-};
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_sample_controller
-#include "core-sample_controller/xtensa-modules.inc.c"
+#include "core-sample_controller/xtensa-modules.c.inc"
static XtensaConfig sample_controller __attribute__((unused)) = {
.name = "sample_controller",
.gdb_regmap = {
.reg = {
-#include "core-sample_controller/gdb-config.inc.c"
+#include "core-sample_controller/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
--- /dev/null
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2016 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
+ XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 39,156,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
+ XTREG( 41,164,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG( 42,168, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG( 43,172, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG( 44,176,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG( 47,188,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG( 51,204,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG( 52,208,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG( 53,212,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG( 54,216,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG( 56,224,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG( 57,228,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG( 58,232,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG( 59,236,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG( 60,240,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG( 61,244,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG( 62,248,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG( 63,252,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG( 64,256,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG( 65,260,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG( 66,264,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG( 67,268,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG( 68,272,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG( 69,276,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG( 70,280,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG( 71,284,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG( 72,288,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG( 73,292,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG( 74,296,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG( 77,308, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG( 78,312,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG( 79,316,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG( 80,320,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG( 81,324,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG( 82,328, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG( 84,336,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG( 85,340,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG( 86,344,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG( 87,348,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG( 89,356,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG( 90,360,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG( 91,364,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG( 92,368,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG( 93,372,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG( 94,376,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG( 95,380,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG( 96,384,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG( 97,388,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG( 98,392,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG( 99,396,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(100,400,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(101,404,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(102,408,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(103,412,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(104,416,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(105,420, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask0,0,0,0)
+ XTREG(106,424, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask1,0,0,0)
+ XTREG(107,428, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask2,0,0,0)
+ XTREG(108,432, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask3,0,0,0)
+ XTREG(109,436, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask4,0,0,0)
+ XTREG(110,440, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask5,0,0,0)
+ XTREG_END
+++ /dev/null
-/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
-
- Copyright (c) 2003-2016 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
- XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
- XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
- XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
- XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
- XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
- XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
- XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
- XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
- XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
- XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
- XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
- XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
- XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
- XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
- XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
- XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
- XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
- XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
- XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
- XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
- XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
- XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
- XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
- XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
- XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
- XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
- XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
- XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
- XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
- XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
- XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
- XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
- XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
- XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
- XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
- XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
- XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
- XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
- XTREG( 39,156,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
- XTREG( 40,160,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
- XTREG( 41,164,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
- XTREG( 42,168, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
- XTREG( 43,172, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
- XTREG( 44,176,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
- XTREG( 45,180,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
- XTREG( 46,184,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
- XTREG( 47,188,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
- XTREG( 48,192,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
- XTREG( 49,196,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
- XTREG( 50,200,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
- XTREG( 51,204,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
- XTREG( 52,208,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
- XTREG( 53,212,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
- XTREG( 54,216,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
- XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
- XTREG( 56,224,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
- XTREG( 57,228,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
- XTREG( 58,232,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
- XTREG( 59,236,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
- XTREG( 60,240,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
- XTREG( 61,244,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
- XTREG( 62,248,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
- XTREG( 63,252,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
- XTREG( 64,256,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
- XTREG( 65,260,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
- XTREG( 66,264,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
- XTREG( 67,268,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
- XTREG( 68,272,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
- XTREG( 69,276,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
- XTREG( 70,280,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
- XTREG( 71,284,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
- XTREG( 72,288,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
- XTREG( 73,292,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
- XTREG( 74,296,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
- XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
- XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
- XTREG( 77,308, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
- XTREG( 78,312,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
- XTREG( 79,316,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
- XTREG( 80,320,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
- XTREG( 81,324,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
- XTREG( 82,328, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
- XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
- XTREG( 84,336,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
- XTREG( 85,340,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
- XTREG( 86,344,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
- XTREG( 87,348,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
- XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
- XTREG( 89,356,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
- XTREG( 90,360,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
- XTREG( 91,364,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
- XTREG( 92,368,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
- XTREG( 93,372,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
- XTREG( 94,376,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
- XTREG( 95,380,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
- XTREG( 96,384,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
- XTREG( 97,388,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
- XTREG( 98,392,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
- XTREG( 99,396,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
- XTREG(100,400,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
- XTREG(101,404,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
- XTREG(102,408,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
- XTREG(103,412,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
- XTREG(104,416,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
- XTREG(105,420, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
- 0,0,&xtensa_mask0,0,0,0)
- XTREG(106,424, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
- 0,0,&xtensa_mask1,0,0,0)
- XTREG(107,428, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
- 0,0,&xtensa_mask2,0,0,0)
- XTREG(108,432, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
- 0,0,&xtensa_mask3,0,0,0)
- XTREG(109,436, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
- 0,0,&xtensa_mask4,0,0,0)
- XTREG(110,440, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
- 0,0,&xtensa_mask5,0,0,0)
- XTREG_END
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+
+ Copyright (c) 2003-2016 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "qemu/osdep.h"
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "CONFIGID0", 176, 0 },
+ { "CONFIGID1", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 55
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 230
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 13, 0 },
+ { "EPS3", 13, 0 },
+ { "EPS4", 13, 0 },
+ { "EPS5", 13, 0 },
+ { "EPS6", 13, 0 },
+ { "EPS7", 13, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "SAR", 6, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 59
+
+enum xtensa_state_id {
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EPC3,
+ STATE_EPC4,
+ STATE_EPC5,
+ STATE_EPC6,
+ STATE_EPC7,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EXCSAVE3,
+ STATE_EXCSAVE4,
+ STATE_EXCSAVE5,
+ STATE_EXCSAVE6,
+ STATE_EXCSAVE7,
+ STATE_EPS2,
+ STATE_EPS3,
+ STATE_EPS4,
+ STATE_EPS5,
+ STATE_EPS6,
+ STATE_EPS7,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_SAR,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_DBREAKA0,
+ STATE_DBREAKC0,
+ STATE_DBREAKA1,
+ STATE_DBREAKC1,
+ STATE_IBREAKA0,
+ STATE_IBREAKA1,
+ STATE_IBREAKENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_CCOMPARE2,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_EXPSTATE
+};
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_bitindex,
+ FIELD_s3to1,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12
+};
+
+\f
+/* Functional units. */
+
+#define funcUnits 0
+
+\f
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "IMPWIRE", 32, 0, 0, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_IMPWIRE
+};
+
+
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_out_0;
+ unsigned soffsetx4_in_0;
+ soffsetx4_in_0 = *valp & 0x3ffff;
+ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+ unsigned soffsetx4_in_0;
+ unsigned soffsetx4_out_0;
+ soffsetx4_out_0 = *valp;
+ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = soffsetx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_out_0;
+ unsigned uimm12x8_in_0;
+ uimm12x8_in_0 = *valp & 0xfff;
+ uimm12x8_out_0 = uimm12x8_in_0 << 3;
+ *valp = uimm12x8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+ unsigned uimm12x8_in_0;
+ unsigned uimm12x8_out_0;
+ uimm12x8_out_0 = *valp;
+ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+ *valp = uimm12x8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_out_0;
+ unsigned simm4_in_0;
+ simm4_in_0 = *valp & 0xf;
+ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+ *valp = simm4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+ unsigned simm4_in_0;
+ unsigned simm4_out_0;
+ simm4_out_0 = *valp;
+ simm4_in_0 = (simm4_out_0 & 0xf);
+ *valp = simm4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+ return (*valp >= 32);
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_out_0;
+ unsigned immrx4_in_0;
+ immrx4_in_0 = *valp & 0xf;
+ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+ *valp = immrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+ unsigned immrx4_in_0;
+ unsigned immrx4_out_0;
+ immrx4_out_0 = *valp;
+ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+ *valp = immrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_out_0;
+ unsigned lsi4x4_in_0;
+ lsi4x4_in_0 = *valp & 0xf;
+ lsi4x4_out_0 = lsi4x4_in_0 << 2;
+ *valp = lsi4x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+ unsigned lsi4x4_in_0;
+ unsigned lsi4x4_out_0;
+ lsi4x4_out_0 = *valp;
+ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+ *valp = lsi4x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_out_0;
+ unsigned simm7_in_0;
+ simm7_in_0 = *valp & 0x7f;
+ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+ *valp = simm7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+ unsigned simm7_in_0;
+ unsigned simm7_out_0;
+ simm7_out_0 = *valp;
+ simm7_in_0 = (simm7_out_0 & 0x7f);
+ *valp = simm7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_out_0;
+ unsigned uimm6_in_0;
+ uimm6_in_0 = *valp & 0x3f;
+ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+ *valp = uimm6_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+ unsigned uimm6_in_0;
+ unsigned uimm6_out_0;
+ uimm6_out_0 = *valp;
+ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+ *valp = uimm6_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_out_0;
+ unsigned ai4const_in_0;
+ ai4const_in_0 = *valp & 0xf;
+ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+ *valp = ai4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+ unsigned ai4const_in_0;
+ unsigned ai4const_out_0;
+ ai4const_out_0 = *valp;
+ switch (ai4const_out_0)
+ {
+ case 0xffffffff: ai4const_in_0 = 0; break;
+ case 0x1: ai4const_in_0 = 0x1; break;
+ case 0x2: ai4const_in_0 = 0x2; break;
+ case 0x3: ai4const_in_0 = 0x3; break;
+ case 0x4: ai4const_in_0 = 0x4; break;
+ case 0x5: ai4const_in_0 = 0x5; break;
+ case 0x6: ai4const_in_0 = 0x6; break;
+ case 0x7: ai4const_in_0 = 0x7; break;
+ case 0x8: ai4const_in_0 = 0x8; break;
+ case 0x9: ai4const_in_0 = 0x9; break;
+ case 0xa: ai4const_in_0 = 0xa; break;
+ case 0xb: ai4const_in_0 = 0xb; break;
+ case 0xc: ai4const_in_0 = 0xc; break;
+ case 0xd: ai4const_in_0 = 0xd; break;
+ case 0xe: ai4const_in_0 = 0xe; break;
+ default: ai4const_in_0 = 0xf; break;
+ }
+ *valp = ai4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_out_0;
+ unsigned b4const_in_0;
+ b4const_in_0 = *valp & 0xf;
+ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+ *valp = b4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+ unsigned b4const_in_0;
+ unsigned b4const_out_0;
+ b4const_out_0 = *valp;
+ switch (b4const_out_0)
+ {
+ case 0xffffffff: b4const_in_0 = 0; break;
+ case 0x1: b4const_in_0 = 0x1; break;
+ case 0x2: b4const_in_0 = 0x2; break;
+ case 0x3: b4const_in_0 = 0x3; break;
+ case 0x4: b4const_in_0 = 0x4; break;
+ case 0x5: b4const_in_0 = 0x5; break;
+ case 0x6: b4const_in_0 = 0x6; break;
+ case 0x7: b4const_in_0 = 0x7; break;
+ case 0x8: b4const_in_0 = 0x8; break;
+ case 0xa: b4const_in_0 = 0x9; break;
+ case 0xc: b4const_in_0 = 0xa; break;
+ case 0x10: b4const_in_0 = 0xb; break;
+ case 0x20: b4const_in_0 = 0xc; break;
+ case 0x40: b4const_in_0 = 0xd; break;
+ case 0x80: b4const_in_0 = 0xe; break;
+ default: b4const_in_0 = 0xf; break;
+ }
+ *valp = b4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_out_0;
+ unsigned b4constu_in_0;
+ b4constu_in_0 = *valp & 0xf;
+ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+ *valp = b4constu_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+ unsigned b4constu_in_0;
+ unsigned b4constu_out_0;
+ b4constu_out_0 = *valp;
+ switch (b4constu_out_0)
+ {
+ case 0x8000: b4constu_in_0 = 0; break;
+ case 0x10000: b4constu_in_0 = 0x1; break;
+ case 0x2: b4constu_in_0 = 0x2; break;
+ case 0x3: b4constu_in_0 = 0x3; break;
+ case 0x4: b4constu_in_0 = 0x4; break;
+ case 0x5: b4constu_in_0 = 0x5; break;
+ case 0x6: b4constu_in_0 = 0x6; break;
+ case 0x7: b4constu_in_0 = 0x7; break;
+ case 0x8: b4constu_in_0 = 0x8; break;
+ case 0xa: b4constu_in_0 = 0x9; break;
+ case 0xc: b4constu_in_0 = 0xa; break;
+ case 0x10: b4constu_in_0 = 0xb; break;
+ case 0x20: b4constu_in_0 = 0xc; break;
+ case 0x40: b4constu_in_0 = 0xd; break;
+ case 0x80: b4constu_in_0 = 0xe; break;
+ default: b4constu_in_0 = 0xf; break;
+ }
+ *valp = b4constu_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_out_0;
+ unsigned uimm8_in_0;
+ uimm8_in_0 = *valp & 0xff;
+ uimm8_out_0 = uimm8_in_0;
+ *valp = uimm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+ unsigned uimm8_in_0;
+ unsigned uimm8_out_0;
+ uimm8_out_0 = *valp;
+ uimm8_in_0 = (uimm8_out_0 & 0xff);
+ *valp = uimm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_out_0;
+ unsigned uimm8x2_in_0;
+ uimm8x2_in_0 = *valp & 0xff;
+ uimm8x2_out_0 = uimm8x2_in_0 << 1;
+ *valp = uimm8x2_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+ unsigned uimm8x2_in_0;
+ unsigned uimm8x2_out_0;
+ uimm8x2_out_0 = *valp;
+ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+ *valp = uimm8x2_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_out_0;
+ unsigned uimm8x4_in_0;
+ uimm8x4_in_0 = *valp & 0xff;
+ uimm8x4_out_0 = uimm8x4_in_0 << 2;
+ *valp = uimm8x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+ unsigned uimm8x4_in_0;
+ unsigned uimm8x4_out_0;
+ uimm8x4_out_0 = *valp;
+ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+ *valp = uimm8x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_out_0;
+ unsigned uimm4x16_in_0;
+ uimm4x16_in_0 = *valp & 0xf;
+ uimm4x16_out_0 = uimm4x16_in_0 << 4;
+ *valp = uimm4x16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+ unsigned uimm4x16_in_0;
+ unsigned uimm4x16_out_0;
+ uimm4x16_out_0 = *valp;
+ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+ *valp = uimm4x16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
+{
+ unsigned uimmrx4_out_0;
+ unsigned uimmrx4_in_0;
+ uimmrx4_in_0 = *valp & 0xf;
+ uimmrx4_out_0 = uimmrx4_in_0 << 2;
+ *valp = uimmrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
+{
+ unsigned uimmrx4_in_0;
+ unsigned uimmrx4_out_0;
+ uimmrx4_out_0 = *valp;
+ uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
+ *valp = uimmrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_out_0;
+ unsigned simm8_in_0;
+ simm8_in_0 = *valp & 0xff;
+ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+ *valp = simm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+ unsigned simm8_in_0;
+ unsigned simm8_out_0;
+ simm8_out_0 = *valp;
+ simm8_in_0 = (simm8_out_0 & 0xff);
+ *valp = simm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_out_0;
+ unsigned simm8x256_in_0;
+ simm8x256_in_0 = *valp & 0xff;
+ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+ *valp = simm8x256_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+ unsigned simm8x256_in_0;
+ unsigned simm8x256_out_0;
+ simm8x256_out_0 = *valp;
+ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+ *valp = simm8x256_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_out_0;
+ unsigned simm12b_in_0;
+ simm12b_in_0 = *valp & 0xfff;
+ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+ *valp = simm12b_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+ unsigned simm12b_in_0;
+ unsigned simm12b_out_0;
+ simm12b_out_0 = *valp;
+ simm12b_in_0 = (simm12b_out_0 & 0xfff);
+ *valp = simm12b_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_out_0;
+ unsigned msalp32_in_0;
+ msalp32_in_0 = *valp & 0x1f;
+ msalp32_out_0 = 0x20 - msalp32_in_0;
+ *valp = msalp32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+ unsigned msalp32_in_0;
+ unsigned msalp32_out_0;
+ msalp32_out_0 = *valp;
+ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+ *valp = msalp32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_out_0;
+ unsigned op2p1_in_0;
+ op2p1_in_0 = *valp & 0xf;
+ op2p1_out_0 = op2p1_in_0 + 0x1;
+ *valp = op2p1_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+ unsigned op2p1_in_0;
+ unsigned op2p1_out_0;
+ op2p1_out_0 = *valp;
+ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+ *valp = op2p1_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+ unsigned label8_out_0;
+ unsigned label8_in_0;
+ label8_in_0 = *valp & 0xff;
+ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+ *valp = label8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+ unsigned label8_in_0;
+ unsigned label8_out_0;
+ label8_out_0 = *valp;
+ label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+ *valp = label8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+ unsigned label12_out_0;
+ unsigned label12_in_0;
+ label12_in_0 = *valp & 0xfff;
+ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+ *valp = label12_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+ unsigned label12_in_0;
+ unsigned label12_out_0;
+ label12_out_0 = *valp;
+ label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+ *valp = label12_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_out_0;
+ unsigned soffset_in_0;
+ soffset_in_0 = *valp & 0x3ffff;
+ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+ *valp = soffset_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+ unsigned soffset_in_0;
+ unsigned soffset_out_0;
+ soffset_out_0 = *valp;
+ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+ *valp = soffset_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_out_0;
+ unsigned uimm16x4_in_0;
+ uimm16x4_in_0 = *valp & 0xffff;
+ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+ *valp = uimm16x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+ unsigned uimm16x4_in_0;
+ unsigned uimm16x4_out_0;
+ uimm16x4_out_0 = *valp;
+ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+ *valp = uimm16x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+ unsigned bbi_out_0;
+ unsigned bbi_in_0;
+ bbi_in_0 = *valp & 0x1f;
+ bbi_out_0 = (0 << 5) | bbi_in_0;
+ *valp = bbi_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+ unsigned bbi_in_0;
+ unsigned bbi_out_0;
+ bbi_out_0 = *valp;
+ bbi_in_0 = (bbi_out_0 & 0x1f);
+ *valp = bbi_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+ unsigned s_out_0;
+ unsigned s_in_0;
+ s_in_0 = *valp & 0xf;
+ s_out_0 = (0 << 4) | s_in_0;
+ *valp = s_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+ unsigned s_in_0;
+ unsigned s_out_0;
+ s_out_0 = *valp;
+ s_in_0 = (s_out_0 & 0xf);
+ *valp = s_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+ unsigned immt_out_0;
+ unsigned immt_in_0;
+ immt_in_0 = *valp & 0xf;
+ immt_out_0 = immt_in_0;
+ *valp = immt_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+ unsigned immt_in_0;
+ unsigned immt_out_0;
+ immt_out_0 = *valp;
+ immt_in_0 = immt_out_0 & 0xf;
+ *valp = immt_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_out_0;
+ unsigned tp7_in_0;
+ tp7_in_0 = *valp & 0xf;
+ tp7_out_0 = tp7_in_0 + 0x7;
+ *valp = tp7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+ unsigned tp7_in_0;
+ unsigned tp7_out_0;
+ tp7_out_0 = *valp;
+ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+ *valp = tp7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_out_0;
+ unsigned xt_wbr15_label_in_0;
+ xt_wbr15_label_in_0 = *valp & 0x7fff;
+ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+ *valp = xt_wbr15_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_in_0;
+ unsigned xt_wbr15_label_out_0;
+ xt_wbr15_label_out_0 = *valp;
+ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_out_0;
+ unsigned xt_wbr18_label_in_0;
+ xt_wbr18_label_in_0 = *valp & 0x3ffff;
+ xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
+ *valp = xt_wbr18_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr18_label_in_0;
+ unsigned xt_wbr18_label_out_0;
+ xt_wbr18_label_out_0 = *valp;
+ xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
+ *valp = xt_wbr18_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
+{
+ unsigned bitindex_out_0;
+ unsigned bitindex_in_0;
+ bitindex_in_0 = *valp & 0x1f;
+ bitindex_out_0 = (0 << 5) | bitindex_in_0;
+ *valp = bitindex_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
+{
+ unsigned bitindex_in_0;
+ unsigned bitindex_out_0;
+ bitindex_out_0 = *valp;
+ bitindex_in_0 = (bitindex_out_0 & 0x1f);
+ *valp = bitindex_in_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+ 0, 0 },
+ { "uimmrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "bbi", FIELD_bbi, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sae", FIELD_sae, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sas", FIELD_sas, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "s", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "bitindex", FIELD_bitindex, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
+ 0, 0 },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_uimmrx4,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_bbi,
+ OPERAND_sae,
+ OPERAND_sas,
+ OPERAND_sargt,
+ OPERAND_s,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_bitindex,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sal,
+ OPERAND_sas4,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_s3to1
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32nb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_configid0_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid1_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_salt_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_lddr32_p_args,
+ 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sddr32_p_args,
+ 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eraccess_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eraccess_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eraccess_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rer_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wer_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_expstate_args,
+ 1, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 1, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s32nb,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_memctl,
+ ICLASS_xt_iclass_wsr_memctl,
+ ICLASS_xt_iclass_xsr_memctl,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_configid0,
+ ICLASS_xt_iclass_wsr_configid0,
+ ICLASS_xt_iclass_rsr_configid1,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_epc3,
+ ICLASS_xt_iclass_wsr_epc3,
+ ICLASS_xt_iclass_xsr_epc3,
+ ICLASS_xt_iclass_rsr_excsave3,
+ ICLASS_xt_iclass_wsr_excsave3,
+ ICLASS_xt_iclass_xsr_excsave3,
+ ICLASS_xt_iclass_rsr_epc4,
+ ICLASS_xt_iclass_wsr_epc4,
+ ICLASS_xt_iclass_xsr_epc4,
+ ICLASS_xt_iclass_rsr_excsave4,
+ ICLASS_xt_iclass_wsr_excsave4,
+ ICLASS_xt_iclass_xsr_excsave4,
+ ICLASS_xt_iclass_rsr_epc5,
+ ICLASS_xt_iclass_wsr_epc5,
+ ICLASS_xt_iclass_xsr_epc5,
+ ICLASS_xt_iclass_rsr_excsave5,
+ ICLASS_xt_iclass_wsr_excsave5,
+ ICLASS_xt_iclass_xsr_excsave5,
+ ICLASS_xt_iclass_rsr_epc6,
+ ICLASS_xt_iclass_wsr_epc6,
+ ICLASS_xt_iclass_xsr_epc6,
+ ICLASS_xt_iclass_rsr_excsave6,
+ ICLASS_xt_iclass_wsr_excsave6,
+ ICLASS_xt_iclass_xsr_excsave6,
+ ICLASS_xt_iclass_rsr_epc7,
+ ICLASS_xt_iclass_wsr_epc7,
+ ICLASS_xt_iclass_xsr_epc7,
+ ICLASS_xt_iclass_rsr_excsave7,
+ ICLASS_xt_iclass_wsr_excsave7,
+ ICLASS_xt_iclass_xsr_excsave7,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_eps3,
+ ICLASS_xt_iclass_wsr_eps3,
+ ICLASS_xt_iclass_xsr_eps3,
+ ICLASS_xt_iclass_rsr_eps4,
+ ICLASS_xt_iclass_wsr_eps4,
+ ICLASS_xt_iclass_xsr_eps4,
+ ICLASS_xt_iclass_rsr_eps5,
+ ICLASS_xt_iclass_wsr_eps5,
+ ICLASS_xt_iclass_xsr_eps5,
+ ICLASS_xt_iclass_rsr_eps6,
+ ICLASS_xt_iclass_wsr_eps6,
+ ICLASS_xt_iclass_xsr_eps6,
+ ICLASS_xt_iclass_rsr_eps7,
+ ICLASS_xt_iclass_wsr_eps7,
+ ICLASS_xt_iclass_xsr_eps7,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_iclass_salt,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_dbreaka0,
+ ICLASS_xt_iclass_wsr_dbreaka0,
+ ICLASS_xt_iclass_xsr_dbreaka0,
+ ICLASS_xt_iclass_rsr_dbreakc0,
+ ICLASS_xt_iclass_wsr_dbreakc0,
+ ICLASS_xt_iclass_xsr_dbreakc0,
+ ICLASS_xt_iclass_rsr_dbreaka1,
+ ICLASS_xt_iclass_wsr_dbreaka1,
+ ICLASS_xt_iclass_xsr_dbreaka1,
+ ICLASS_xt_iclass_rsr_dbreakc1,
+ ICLASS_xt_iclass_wsr_dbreakc1,
+ ICLASS_xt_iclass_xsr_dbreakc1,
+ ICLASS_xt_iclass_rsr_ibreaka0,
+ ICLASS_xt_iclass_wsr_ibreaka0,
+ ICLASS_xt_iclass_xsr_ibreaka0,
+ ICLASS_xt_iclass_rsr_ibreaka1,
+ ICLASS_xt_iclass_wsr_ibreaka1,
+ ICLASS_xt_iclass_xsr_ibreaka1,
+ ICLASS_xt_iclass_rsr_ibreakenable,
+ ICLASS_xt_iclass_wsr_ibreakenable,
+ ICLASS_xt_iclass_xsr_ibreakenable,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_lddr32_p,
+ ICLASS_xt_iclass_sddr32_p,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_wsr_mmid,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_rsr_ccompare2,
+ ICLASS_xt_iclass_wsr_ccompare2,
+ ICLASS_xt_iclass_xsr_ccompare2,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_div,
+ ICLASS_xt_iclass_rsr_eraccess,
+ ICLASS_xt_iclass_wsr_eraccess,
+ ICLASS_xt_iclass_xsr_eraccess,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_expstate,
+ ICLASS_wur_expstate,
+ ICLASS_iclass_READ_IMPWIRE,
+ ICLASS_iclass_SETB_EXPSTATE,
+ ICLASS_iclass_CLRB_EXPSTATE,
+ ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720000;
+}
+
+static void
+Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x620000;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35f00;
+}
+
+static void
+Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135f00;
+}
+
+static void
+Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615f00;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe2000;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+ Opcode_s32nb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+ Opcode_rsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+ Opcode_wsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+ Opcode_xsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+ Opcode_rsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+ Opcode_wsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+ Opcode_rsr_configid1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
+ Opcode_salt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
+ Opcode_saltu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+ Opcode_lddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+ Opcode_sddr32_p_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
+ Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
+ Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
+ Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+
+
+
+\f
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s32nb", ICLASS_xt_iclass_s32nb,
+ 0,
+ Opcode_s32nb_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+ 0,
+ Opcode_rsr_memctl_encode_fns, 0, 0 },
+ { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+ 0,
+ Opcode_wsr_memctl_encode_fns, 0, 0 },
+ { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+ 0,
+ Opcode_xsr_memctl_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+ 0,
+ Opcode_rsr_configid0_encode_fns, 0, 0 },
+ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+ 0,
+ Opcode_wsr_configid0_encode_fns, 0, 0 },
+ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+ 0,
+ Opcode_rsr_configid1_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "salt", ICLASS_xt_iclass_salt,
+ 0,
+ Opcode_salt_encode_fns, 0, 0 },
+ { "saltu", ICLASS_xt_iclass_salt,
+ 0,
+ Opcode_saltu_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+ 0,
+ Opcode_lddr32_p_encode_fns, 0, 0 },
+ { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+ 0,
+ Opcode_sddr32_p_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "quou", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
+ 0,
+ Opcode_rsr_eraccess_encode_fns, 0, 0 },
+ { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
+ 0,
+ Opcode_wsr_eraccess_encode_fns, 0, 0 },
+ { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
+ 0,
+ Opcode_xsr_eraccess_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.expstate", ICLASS_rur_expstate,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", ICLASS_wur_expstate,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_SIMCALL,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S32NB,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_MEMCTL,
+ OPCODE_WSR_MEMCTL,
+ OPCODE_XSR_MEMCTL,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_CONFIGID0,
+ OPCODE_WSR_CONFIGID0,
+ OPCODE_RSR_CONFIGID1,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPC3,
+ OPCODE_WSR_EPC3,
+ OPCODE_XSR_EPC3,
+ OPCODE_RSR_EXCSAVE3,
+ OPCODE_WSR_EXCSAVE3,
+ OPCODE_XSR_EXCSAVE3,
+ OPCODE_RSR_EPC4,
+ OPCODE_WSR_EPC4,
+ OPCODE_XSR_EPC4,
+ OPCODE_RSR_EXCSAVE4,
+ OPCODE_WSR_EXCSAVE4,
+ OPCODE_XSR_EXCSAVE4,
+ OPCODE_RSR_EPC5,
+ OPCODE_WSR_EPC5,
+ OPCODE_XSR_EPC5,
+ OPCODE_RSR_EXCSAVE5,
+ OPCODE_WSR_EXCSAVE5,
+ OPCODE_XSR_EXCSAVE5,
+ OPCODE_RSR_EPC6,
+ OPCODE_WSR_EPC6,
+ OPCODE_XSR_EPC6,
+ OPCODE_RSR_EXCSAVE6,
+ OPCODE_WSR_EXCSAVE6,
+ OPCODE_XSR_EXCSAVE6,
+ OPCODE_RSR_EPC7,
+ OPCODE_WSR_EPC7,
+ OPCODE_XSR_EPC7,
+ OPCODE_RSR_EXCSAVE7,
+ OPCODE_WSR_EXCSAVE7,
+ OPCODE_XSR_EXCSAVE7,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EPS3,
+ OPCODE_WSR_EPS3,
+ OPCODE_XSR_EPS3,
+ OPCODE_RSR_EPS4,
+ OPCODE_WSR_EPS4,
+ OPCODE_XSR_EPS4,
+ OPCODE_RSR_EPS5,
+ OPCODE_WSR_EPS5,
+ OPCODE_XSR_EPS5,
+ OPCODE_RSR_EPS6,
+ OPCODE_WSR_EPS6,
+ OPCODE_XSR_EPS6,
+ OPCODE_RSR_EPS7,
+ OPCODE_WSR_EPS7,
+ OPCODE_XSR_EPS7,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_SALT,
+ OPCODE_SALTU,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DBREAKA0,
+ OPCODE_WSR_DBREAKA0,
+ OPCODE_XSR_DBREAKA0,
+ OPCODE_RSR_DBREAKC0,
+ OPCODE_WSR_DBREAKC0,
+ OPCODE_XSR_DBREAKC0,
+ OPCODE_RSR_DBREAKA1,
+ OPCODE_WSR_DBREAKA1,
+ OPCODE_XSR_DBREAKA1,
+ OPCODE_RSR_DBREAKC1,
+ OPCODE_WSR_DBREAKC1,
+ OPCODE_XSR_DBREAKC1,
+ OPCODE_RSR_IBREAKA0,
+ OPCODE_WSR_IBREAKA0,
+ OPCODE_XSR_IBREAKA0,
+ OPCODE_RSR_IBREAKA1,
+ OPCODE_WSR_IBREAKA1,
+ OPCODE_XSR_IBREAKA1,
+ OPCODE_RSR_IBREAKENABLE,
+ OPCODE_WSR_IBREAKENABLE,
+ OPCODE_XSR_IBREAKENABLE,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_LDDR32_P,
+ OPCODE_SDDR32_P,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_WSR_MMID,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_RSR_CCOMPARE2,
+ OPCODE_WSR_CCOMPARE2,
+ OPCODE_XSR_CCOMPARE2,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_QUOU,
+ OPCODE_QUOS,
+ OPCODE_REMU,
+ OPCODE_REMS,
+ OPCODE_RSR_ERACCESS,
+ OPCODE_WSR_ERACCESS,
+ OPCODE_XSR_ERACCESS,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_EXPSTATE,
+ OPCODE_WUR_EXPSTATE,
+ OPCODE_READ_IMPWIRE,
+ OPCODE_SETB_EXPSTATE,
+ OPCODE_CLRB_EXPSTATE,
+ OPCODE_WRMSK_EXPSTATE
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_RET;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_RETW;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_JX;
+ }
+ if (Field_m_Slot_inst_get (insn) == 3)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALLX0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALLX4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALLX8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALLX12;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_MOVSP;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_ISYNC;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RSYNC;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_ESYNC;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DSYNC;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ return OPCODE_EXCW;
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_MEMW;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ return OPCODE_EXTW;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_NOP;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 3)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_RFE;
+ if (Field_s_Slot_inst_get (insn) == 2)
+ return OPCODE_RFDE;
+ if (Field_s_Slot_inst_get (insn) == 4)
+ return OPCODE_RFWO;
+ if (Field_s_Slot_inst_get (insn) == 5)
+ return OPCODE_RFWU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFI;
+ }
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BREAK;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ }
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RSIL;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_LDDR32_P;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_SDDR32_P;
+ }
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_OR;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_XOR;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RER;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_WER;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_NSA;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_NSAU;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_RITLB0;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_PITLB;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_WITLB;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_RITLB1;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_RDTLB0;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_PDTLB;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_WDTLB;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_RDTLB1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_NEG;
+ if (Field_s_Slot_inst_get (insn) == 1)
+ return OPCODE_ABS;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_ADD;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_ADDX2;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_ADDX4;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_ADDX8;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_SUB;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_SUBX2;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_SUBX4;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_SUBX8;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 1)
+ {
+ if ((Field_op2_Slot_inst_get (insn) == 0 ||
+ Field_op2_Slot_inst_get (insn) == 1))
+ return OPCODE_SLLI;
+ if ((Field_op2_Slot_inst_get (insn) == 2 ||
+ Field_op2_Slot_inst_get (insn) == 3))
+ return OPCODE_SRAI;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_SRLI;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_XSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_XSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_XSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_XSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_XSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 95)
+ return OPCODE_XSR_ERACCESS;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_XSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_XSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_XSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_XSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_XSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_XSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_XSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_XSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_XSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_XSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_XSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_XSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_XSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_XSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_XSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_XSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_XSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_XSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_XSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_XSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_XSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_XSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_XSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_XSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_XSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_XSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_XSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_XSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_XSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_XSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_XSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_XSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_XSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_XSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_XSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_XSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_XSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_XSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_XSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_XSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_XSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_XSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_XSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_XSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_XSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_SRC;
+ if (Field_op2_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ if (Field_op2_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_op2_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MUL16U;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MUL16S;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ }
+ }
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_SALTU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_SALT;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MULL;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_QUOU;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_QUOS;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_REMU;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_REMS;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_RSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_RSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_RSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_RSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_RSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 95)
+ return OPCODE_RSR_ERACCESS;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_RSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_RSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_RSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_RSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_RSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_RSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_RSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_RSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_RSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_RSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_RSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_RSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_RSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_RSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_RSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_RSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_RSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_RSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_RSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_RSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_RSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_RSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_RSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_RSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_RSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 208)
+ return OPCODE_RSR_CONFIGID1;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_RSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_RSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_RSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_RSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_RSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_RSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_RSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_RSR_INTERRUPT;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_RSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_RSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_RSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_RSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_RSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_RSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 235)
+ return OPCODE_RSR_PRID;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_RSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_RSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_RSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_RSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_RSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_RSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_RSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_RSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_WSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_WSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_WSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_WSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_WSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 89)
+ return OPCODE_WSR_MMID;
+ if (Field_sr_Slot_inst_get (insn) == 95)
+ return OPCODE_WSR_ERACCESS;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_WSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_WSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_WSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_WSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_WSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_WSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_WSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_WSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_WSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_WSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_WSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_WSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_WSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_WSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_WSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_WSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_WSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_WSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_WSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_WSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_WSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_WSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_WSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_WSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_WSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_WSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_WSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_WSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_WSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_WSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_WSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_WSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_WSR_INTSET;
+ if (Field_sr_Slot_inst_get (insn) == 227)
+ return OPCODE_WSR_INTCLEAR;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_WSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_WSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_WSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_WSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_WSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_WSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_WSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_WSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_WSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_SEXT;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_MIN;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_MAX;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_MINU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_MAXU;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MOVEQZ;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_MOVNEZ;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVLTZ;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MOVGEZ;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ {
+ if (Field_st_Slot_inst_get (insn) == 230)
+ return OPCODE_RUR_EXPSTATE;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WUR_EXPSTATE;
+ }
+ }
+ if ((Field_op1_Slot_inst_get (insn) == 4 ||
+ Field_op1_Slot_inst_get (insn) == 5))
+ return OPCODE_EXTUI;
+ if (Field_op1_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_L32E;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_S32E;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_S32NB;
+ }
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_READ_IMPWIRE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_SETB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_CLRB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_WRMSK_EXPSTATE;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 1)
+ return OPCODE_L32R;
+ if (Field_op0_Slot_inst_get (insn) == 2)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_L32I;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_S16I;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_S32I;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVI;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_L32AI;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_S32C1I;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_S32RI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 5)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALL0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALL4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALL8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALL12;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 6)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_J;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQZ;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTZ;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEZ;
+ }
+ if (Field_n_Slot_inst_get (insn) == 2)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQI;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEI;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEI;
+ }
+ if (Field_n_Slot_inst_get (insn) == 3)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_ENTRY;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTUI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEUI;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 7)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BALL;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_BBC;
+ if ((Field_r_Slot_inst_get (insn) == 6 ||
+ Field_r_Slot_inst_get (insn) == 7))
+ return OPCODE_BBCI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_BANY;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_BNE;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_BGE;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_BNALL;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_BBS;
+ if ((Field_r_Slot_inst_get (insn) == 14 ||
+ Field_r_Slot_inst_get (insn) == 15))
+ return OPCODE_BBSI;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16b_get (insn) == 12)
+ {
+ if (Field_i_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOVI_N;
+ if (Field_i_Slot_inst16b_get (insn) == 1)
+ {
+ if (Field_z_Slot_inst16b_get (insn) == 0)
+ return OPCODE_BEQZ_N;
+ if (Field_z_Slot_inst16b_get (insn) == 1)
+ return OPCODE_BNEZ_N;
+ }
+ }
+ if (Field_op0_Slot_inst16b_get (insn) == 13)
+ {
+ if (Field_r_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOV_N;
+ if (Field_r_Slot_inst16b_get (insn) == 15)
+ {
+ if (Field_t_Slot_inst16b_get (insn) == 0)
+ return OPCODE_RET_N;
+ if (Field_t_Slot_inst16b_get (insn) == 1)
+ return OPCODE_RETW_N;
+ if (Field_t_Slot_inst16b_get (insn) == 2)
+ return OPCODE_BREAK_N;
+ if (Field_t_Slot_inst16b_get (insn) == 3 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ if (Field_t_Slot_inst16b_get (insn) == 6 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ }
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16a_get (insn) == 8)
+ return OPCODE_L32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 9)
+ return OPCODE_S32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 10)
+ return OPCODE_ADD_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 11)
+ return OPCODE_ADDI_N;
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc)
+ return 2; /* x16b */
+ return -1;
+}
+
+static int length_table[256] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int l = insn[0];
+ return length_table[l];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 3 /* insn_size */, 0,
+ 3, formats, format_decoder, length_decoder,
+ 3, slots,
+ 43 /* num_fields */,
+ 77, operands,
+ 263, iclasses,
+ 317, opcodes, 0,
+ 1, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 1, interfaces, 0,
+ 0, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
-
- Copyright (c) 2003-2016 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#include "qemu/osdep.h"
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "MMID", 89, 0 },
- { "DDR", 104, 0 },
- { "CONFIGID0", 176, 0 },
- { "CONFIGID1", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EPC5", 181, 0 },
- { "EPC6", 182, 0 },
- { "EPC7", 183, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EXCSAVE5", 213, 0 },
- { "EXCSAVE6", 214, 0 },
- { "EXCSAVE7", 215, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EPS5", 197, 0 },
- { "EPS6", 198, 0 },
- { "EPS7", 199, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "SCOMPARE1", 12, 0 },
- { "ATOMCTL", 99, 0 },
- { "EXPSTATE", 230, 1 }
-};
-
-#define NUM_SYSREGS 55
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 230
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 22, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EPC5", 32, 0 },
- { "EPC6", 32, 0 },
- { "EPC7", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EXCSAVE5", 32, 0 },
- { "EXCSAVE6", 32, 0 },
- { "EXCSAVE7", 32, 0 },
- { "EPS2", 13, 0 },
- { "EPS3", 13, 0 },
- { "EPS4", 13, 0 },
- { "EPS5", 13, 0 },
- { "EPS6", 13, 0 },
- { "EPS7", 13, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 3, 0 },
- { "WindowStart", 8, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "SAR", 6, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 22, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "SCOMPARE1", 32, 0 },
- { "ATOMCTL", 6, 0 },
- { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
-};
-
-#define NUM_STATES 59
-
-enum xtensa_state_id {
- STATE_PC,
- STATE_ICOUNT,
- STATE_DDR,
- STATE_INTERRUPT,
- STATE_CCOUNT,
- STATE_XTSYNC,
- STATE_VECBASE,
- STATE_EPC1,
- STATE_EPC2,
- STATE_EPC3,
- STATE_EPC4,
- STATE_EPC5,
- STATE_EPC6,
- STATE_EPC7,
- STATE_EXCSAVE1,
- STATE_EXCSAVE2,
- STATE_EXCSAVE3,
- STATE_EXCSAVE4,
- STATE_EXCSAVE5,
- STATE_EXCSAVE6,
- STATE_EXCSAVE7,
- STATE_EPS2,
- STATE_EPS3,
- STATE_EPS4,
- STATE_EPS5,
- STATE_EPS6,
- STATE_EPS7,
- STATE_EXCCAUSE,
- STATE_PSINTLEVEL,
- STATE_PSUM,
- STATE_PSWOE,
- STATE_PSEXCM,
- STATE_DEPC,
- STATE_EXCVADDR,
- STATE_WindowBase,
- STATE_WindowStart,
- STATE_PSCALLINC,
- STATE_PSOWB,
- STATE_SAR,
- STATE_MISC0,
- STATE_MISC1,
- STATE_InOCDMode,
- STATE_INTENABLE,
- STATE_DBREAKA0,
- STATE_DBREAKC0,
- STATE_DBREAKA1,
- STATE_DBREAKC1,
- STATE_IBREAKA0,
- STATE_IBREAKA1,
- STATE_IBREAKENABLE,
- STATE_ICOUNTLEVEL,
- STATE_DEBUGCAUSE,
- STATE_DBNUM,
- STATE_CCOMPARE0,
- STATE_CCOMPARE1,
- STATE_CCOMPARE2,
- STATE_SCOMPARE1,
- STATE_ATOMCTL,
- STATE_EXPSTATE
-};
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
- return tie_t;
-}
-
-static void
-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 17) >> 17;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-enum xtensa_field_id {
- FIELD_t,
- FIELD_bbi4,
- FIELD_bbi,
- FIELD_imm12,
- FIELD_imm8,
- FIELD_s,
- FIELD_imm12b,
- FIELD_imm16,
- FIELD_m,
- FIELD_n,
- FIELD_offset,
- FIELD_op0,
- FIELD_op1,
- FIELD_op2,
- FIELD_r,
- FIELD_sa4,
- FIELD_sae4,
- FIELD_sae,
- FIELD_sal,
- FIELD_sargt,
- FIELD_sas4,
- FIELD_sas,
- FIELD_sr,
- FIELD_st,
- FIELD_thi3,
- FIELD_imm4,
- FIELD_mn,
- FIELD_i,
- FIELD_imm6lo,
- FIELD_imm6hi,
- FIELD_imm7lo,
- FIELD_imm7hi,
- FIELD_z,
- FIELD_imm6,
- FIELD_imm7,
- FIELD_xt_wbr15_imm,
- FIELD_xt_wbr18_imm,
- FIELD_bitindex,
- FIELD_s3to1,
- FIELD__ar0,
- FIELD__ar4,
- FIELD__ar8,
- FIELD__ar12
-};
-
-\f
-/* Functional units. */
-
-#define funcUnits 0
-
-\f
-/* Register files. */
-
-enum xtensa_regfile_id {
- REGFILE_AR
-};
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", REGFILE_AR, 32, 32 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
- { "IMPWIRE", 32, 0, 0, 'i' }
-};
-
-enum xtensa_interface_id {
- INTERFACE_IMPWIRE
-};
-
-
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_out_0;
- unsigned soffsetx4_in_0;
- soffsetx4_in_0 = *valp & 0x3ffff;
- soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
- *valp = soffsetx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
-{
- unsigned soffsetx4_in_0;
- unsigned soffsetx4_out_0;
- soffsetx4_out_0 = *valp;
- soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
- *valp = soffsetx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_out_0;
- unsigned uimm12x8_in_0;
- uimm12x8_in_0 = *valp & 0xfff;
- uimm12x8_out_0 = uimm12x8_in_0 << 3;
- *valp = uimm12x8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
-{
- unsigned uimm12x8_in_0;
- unsigned uimm12x8_out_0;
- uimm12x8_out_0 = *valp;
- uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
- *valp = uimm12x8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_decode (uint32 *valp)
-{
- unsigned simm4_out_0;
- unsigned simm4_in_0;
- simm4_in_0 = *valp & 0xf;
- simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
- *valp = simm4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_encode (uint32 *valp)
-{
- unsigned simm4_in_0;
- unsigned simm4_out_0;
- simm4_out_0 = *valp;
- simm4_in_0 = (simm4_out_0 & 0xf);
- *valp = simm4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
-{
- return (*valp >= 32);
-}
-
-static int
-OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_out_0;
- unsigned immrx4_in_0;
- immrx4_in_0 = *valp & 0xf;
- immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
- *valp = immrx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
-{
- unsigned immrx4_in_0;
- unsigned immrx4_out_0;
- immrx4_out_0 = *valp;
- immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
- *valp = immrx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_out_0;
- unsigned lsi4x4_in_0;
- lsi4x4_in_0 = *valp & 0xf;
- lsi4x4_out_0 = lsi4x4_in_0 << 2;
- *valp = lsi4x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
-{
- unsigned lsi4x4_in_0;
- unsigned lsi4x4_out_0;
- lsi4x4_out_0 = *valp;
- lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
- *valp = lsi4x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_decode (uint32 *valp)
-{
- unsigned simm7_out_0;
- unsigned simm7_in_0;
- simm7_in_0 = *valp & 0x7f;
- simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
- *valp = simm7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_encode (uint32 *valp)
-{
- unsigned simm7_in_0;
- unsigned simm7_out_0;
- simm7_out_0 = *valp;
- simm7_in_0 = (simm7_out_0 & 0x7f);
- *valp = simm7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_out_0;
- unsigned uimm6_in_0;
- uimm6_in_0 = *valp & 0x3f;
- uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
- *valp = uimm6_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
-{
- unsigned uimm6_in_0;
- unsigned uimm6_out_0;
- uimm6_out_0 = *valp;
- uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
- *valp = uimm6_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_out_0;
- unsigned ai4const_in_0;
- ai4const_in_0 = *valp & 0xf;
- ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
- *valp = ai4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
-{
- unsigned ai4const_in_0;
- unsigned ai4const_out_0;
- ai4const_out_0 = *valp;
- switch (ai4const_out_0)
- {
- case 0xffffffff: ai4const_in_0 = 0; break;
- case 0x1: ai4const_in_0 = 0x1; break;
- case 0x2: ai4const_in_0 = 0x2; break;
- case 0x3: ai4const_in_0 = 0x3; break;
- case 0x4: ai4const_in_0 = 0x4; break;
- case 0x5: ai4const_in_0 = 0x5; break;
- case 0x6: ai4const_in_0 = 0x6; break;
- case 0x7: ai4const_in_0 = 0x7; break;
- case 0x8: ai4const_in_0 = 0x8; break;
- case 0x9: ai4const_in_0 = 0x9; break;
- case 0xa: ai4const_in_0 = 0xa; break;
- case 0xb: ai4const_in_0 = 0xb; break;
- case 0xc: ai4const_in_0 = 0xc; break;
- case 0xd: ai4const_in_0 = 0xd; break;
- case 0xe: ai4const_in_0 = 0xe; break;
- default: ai4const_in_0 = 0xf; break;
- }
- *valp = ai4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_decode (uint32 *valp)
-{
- unsigned b4const_out_0;
- unsigned b4const_in_0;
- b4const_in_0 = *valp & 0xf;
- b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
- *valp = b4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_encode (uint32 *valp)
-{
- unsigned b4const_in_0;
- unsigned b4const_out_0;
- b4const_out_0 = *valp;
- switch (b4const_out_0)
- {
- case 0xffffffff: b4const_in_0 = 0; break;
- case 0x1: b4const_in_0 = 0x1; break;
- case 0x2: b4const_in_0 = 0x2; break;
- case 0x3: b4const_in_0 = 0x3; break;
- case 0x4: b4const_in_0 = 0x4; break;
- case 0x5: b4const_in_0 = 0x5; break;
- case 0x6: b4const_in_0 = 0x6; break;
- case 0x7: b4const_in_0 = 0x7; break;
- case 0x8: b4const_in_0 = 0x8; break;
- case 0xa: b4const_in_0 = 0x9; break;
- case 0xc: b4const_in_0 = 0xa; break;
- case 0x10: b4const_in_0 = 0xb; break;
- case 0x20: b4const_in_0 = 0xc; break;
- case 0x40: b4const_in_0 = 0xd; break;
- case 0x80: b4const_in_0 = 0xe; break;
- default: b4const_in_0 = 0xf; break;
- }
- *valp = b4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_out_0;
- unsigned b4constu_in_0;
- b4constu_in_0 = *valp & 0xf;
- b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
- *valp = b4constu_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
-{
- unsigned b4constu_in_0;
- unsigned b4constu_out_0;
- b4constu_out_0 = *valp;
- switch (b4constu_out_0)
- {
- case 0x8000: b4constu_in_0 = 0; break;
- case 0x10000: b4constu_in_0 = 0x1; break;
- case 0x2: b4constu_in_0 = 0x2; break;
- case 0x3: b4constu_in_0 = 0x3; break;
- case 0x4: b4constu_in_0 = 0x4; break;
- case 0x5: b4constu_in_0 = 0x5; break;
- case 0x6: b4constu_in_0 = 0x6; break;
- case 0x7: b4constu_in_0 = 0x7; break;
- case 0x8: b4constu_in_0 = 0x8; break;
- case 0xa: b4constu_in_0 = 0x9; break;
- case 0xc: b4constu_in_0 = 0xa; break;
- case 0x10: b4constu_in_0 = 0xb; break;
- case 0x20: b4constu_in_0 = 0xc; break;
- case 0x40: b4constu_in_0 = 0xd; break;
- case 0x80: b4constu_in_0 = 0xe; break;
- default: b4constu_in_0 = 0xf; break;
- }
- *valp = b4constu_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_out_0;
- unsigned uimm8_in_0;
- uimm8_in_0 = *valp & 0xff;
- uimm8_out_0 = uimm8_in_0;
- *valp = uimm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
-{
- unsigned uimm8_in_0;
- unsigned uimm8_out_0;
- uimm8_out_0 = *valp;
- uimm8_in_0 = (uimm8_out_0 & 0xff);
- *valp = uimm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_out_0;
- unsigned uimm8x2_in_0;
- uimm8x2_in_0 = *valp & 0xff;
- uimm8x2_out_0 = uimm8x2_in_0 << 1;
- *valp = uimm8x2_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
-{
- unsigned uimm8x2_in_0;
- unsigned uimm8x2_out_0;
- uimm8x2_out_0 = *valp;
- uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
- *valp = uimm8x2_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_out_0;
- unsigned uimm8x4_in_0;
- uimm8x4_in_0 = *valp & 0xff;
- uimm8x4_out_0 = uimm8x4_in_0 << 2;
- *valp = uimm8x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
-{
- unsigned uimm8x4_in_0;
- unsigned uimm8x4_out_0;
- uimm8x4_out_0 = *valp;
- uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
- *valp = uimm8x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_out_0;
- unsigned uimm4x16_in_0;
- uimm4x16_in_0 = *valp & 0xf;
- uimm4x16_out_0 = uimm4x16_in_0 << 4;
- *valp = uimm4x16_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
-{
- unsigned uimm4x16_in_0;
- unsigned uimm4x16_out_0;
- uimm4x16_out_0 = *valp;
- uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
- *valp = uimm4x16_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
-{
- unsigned uimmrx4_out_0;
- unsigned uimmrx4_in_0;
- uimmrx4_in_0 = *valp & 0xf;
- uimmrx4_out_0 = uimmrx4_in_0 << 2;
- *valp = uimmrx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
-{
- unsigned uimmrx4_in_0;
- unsigned uimmrx4_out_0;
- uimmrx4_out_0 = *valp;
- uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
- *valp = uimmrx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_decode (uint32 *valp)
-{
- unsigned simm8_out_0;
- unsigned simm8_in_0;
- simm8_in_0 = *valp & 0xff;
- simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
- *valp = simm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_encode (uint32 *valp)
-{
- unsigned simm8_in_0;
- unsigned simm8_out_0;
- simm8_out_0 = *valp;
- simm8_in_0 = (simm8_out_0 & 0xff);
- *valp = simm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_out_0;
- unsigned simm8x256_in_0;
- simm8x256_in_0 = *valp & 0xff;
- simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
- *valp = simm8x256_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
-{
- unsigned simm8x256_in_0;
- unsigned simm8x256_out_0;
- simm8x256_out_0 = *valp;
- simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
- *valp = simm8x256_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_out_0;
- unsigned simm12b_in_0;
- simm12b_in_0 = *valp & 0xfff;
- simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
- *valp = simm12b_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
-{
- unsigned simm12b_in_0;
- unsigned simm12b_out_0;
- simm12b_out_0 = *valp;
- simm12b_in_0 = (simm12b_out_0 & 0xfff);
- *valp = simm12b_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_out_0;
- unsigned msalp32_in_0;
- msalp32_in_0 = *valp & 0x1f;
- msalp32_out_0 = 0x20 - msalp32_in_0;
- *valp = msalp32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
-{
- unsigned msalp32_in_0;
- unsigned msalp32_out_0;
- msalp32_out_0 = *valp;
- msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
- *valp = msalp32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_out_0;
- unsigned op2p1_in_0;
- op2p1_in_0 = *valp & 0xf;
- op2p1_out_0 = op2p1_in_0 + 0x1;
- *valp = op2p1_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
-{
- unsigned op2p1_in_0;
- unsigned op2p1_out_0;
- op2p1_out_0 = *valp;
- op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
- *valp = op2p1_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_decode (uint32 *valp)
-{
- unsigned label8_out_0;
- unsigned label8_in_0;
- label8_in_0 = *valp & 0xff;
- label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
- *valp = label8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_encode (uint32 *valp)
-{
- unsigned label8_in_0;
- unsigned label8_out_0;
- label8_out_0 = *valp;
- label8_in_0 = (label8_out_0 - 0x4) & 0xff;
- *valp = label8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_decode (uint32 *valp)
-{
- unsigned label12_out_0;
- unsigned label12_in_0;
- label12_in_0 = *valp & 0xfff;
- label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
- *valp = label12_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_encode (uint32 *valp)
-{
- unsigned label12_in_0;
- unsigned label12_out_0;
- label12_out_0 = *valp;
- label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
- *valp = label12_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_decode (uint32 *valp)
-{
- unsigned soffset_out_0;
- unsigned soffset_in_0;
- soffset_in_0 = *valp & 0x3ffff;
- soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
- *valp = soffset_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_encode (uint32 *valp)
-{
- unsigned soffset_in_0;
- unsigned soffset_out_0;
- soffset_out_0 = *valp;
- soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
- *valp = soffset_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_out_0;
- unsigned uimm16x4_in_0;
- uimm16x4_in_0 = *valp & 0xffff;
- uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
- *valp = uimm16x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
-{
- unsigned uimm16x4_in_0;
- unsigned uimm16x4_out_0;
- uimm16x4_out_0 = *valp;
- uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
- *valp = uimm16x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_decode (uint32 *valp)
-{
- unsigned bbi_out_0;
- unsigned bbi_in_0;
- bbi_in_0 = *valp & 0x1f;
- bbi_out_0 = (0 << 5) | bbi_in_0;
- *valp = bbi_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_encode (uint32 *valp)
-{
- unsigned bbi_in_0;
- unsigned bbi_out_0;
- bbi_out_0 = *valp;
- bbi_in_0 = (bbi_out_0 & 0x1f);
- *valp = bbi_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_decode (uint32 *valp)
-{
- unsigned s_out_0;
- unsigned s_in_0;
- s_in_0 = *valp & 0xf;
- s_out_0 = (0 << 4) | s_in_0;
- *valp = s_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_encode (uint32 *valp)
-{
- unsigned s_in_0;
- unsigned s_out_0;
- s_out_0 = *valp;
- s_in_0 = (s_out_0 & 0xf);
- *valp = s_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immt_decode (uint32 *valp)
-{
- unsigned immt_out_0;
- unsigned immt_in_0;
- immt_in_0 = *valp & 0xf;
- immt_out_0 = immt_in_0;
- *valp = immt_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immt_encode (uint32 *valp)
-{
- unsigned immt_in_0;
- unsigned immt_out_0;
- immt_out_0 = *valp;
- immt_in_0 = immt_out_0 & 0xf;
- *valp = immt_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_tp7_decode (uint32 *valp)
-{
- unsigned tp7_out_0;
- unsigned tp7_in_0;
- tp7_in_0 = *valp & 0xf;
- tp7_out_0 = tp7_in_0 + 0x7;
- *valp = tp7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_tp7_encode (uint32 *valp)
-{
- unsigned tp7_in_0;
- unsigned tp7_out_0;
- tp7_out_0 = *valp;
- tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
- *valp = tp7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
-{
- unsigned xt_wbr15_label_out_0;
- unsigned xt_wbr15_label_in_0;
- xt_wbr15_label_in_0 = *valp & 0x7fff;
- xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
- *valp = xt_wbr15_label_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
-{
- unsigned xt_wbr15_label_in_0;
- unsigned xt_wbr15_label_out_0;
- xt_wbr15_label_out_0 = *valp;
- xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_label_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
-{
- unsigned xt_wbr18_label_out_0;
- unsigned xt_wbr18_label_in_0;
- xt_wbr18_label_in_0 = *valp & 0x3ffff;
- xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
- *valp = xt_wbr18_label_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
-{
- unsigned xt_wbr18_label_in_0;
- unsigned xt_wbr18_label_out_0;
- xt_wbr18_label_out_0 = *valp;
- xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
- *valp = xt_wbr18_label_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
-{
- unsigned bitindex_out_0;
- unsigned bitindex_in_0;
- bitindex_in_0 = *valp & 0x1f;
- bitindex_out_0 = (0 << 5) | bitindex_in_0;
- *valp = bitindex_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
-{
- unsigned bitindex_in_0;
- unsigned bitindex_out_0;
- bitindex_out_0 = *valp;
- bitindex_in_0 = (bitindex_out_0 & 0x1f);
- *valp = bitindex_in_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", FIELD_imm12, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
- 0, 0 },
- { "simm4", FIELD_mn, -1, 0,
- 0,
- OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
- 0, 0 },
- { "arr", FIELD_r, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ars", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "art", FIELD_t, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ar0", FIELD__ar0, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
- 0, 0 },
- { "ar4", FIELD__ar4, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
- 0, 0 },
- { "ar8", FIELD__ar8, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
- 0, 0 },
- { "ar12", FIELD__ar12, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
- 0, 0 },
- { "ars_entry", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
- 0, 0 },
- { "immrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
- 0, 0 },
- { "lsi4x4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
- 0, 0 },
- { "simm7", FIELD_imm7, -1, 0,
- 0,
- OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
- 0, 0 },
- { "uimm6", FIELD_imm6, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
- 0, 0 },
- { "b4const", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
- 0, 0 },
- { "b4constu", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
- 0, 0 },
- { "uimm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
- 0, 0 },
- { "uimm8x2", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
- 0, 0 },
- { "uimmrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
- 0, 0 },
- { "simm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
- 0, 0 },
- { "simm8x256", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
- 0, 0 },
- { "simm12b", FIELD_imm12b, -1, 0,
- 0,
- OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
- 0, 0 },
- { "msalp32", FIELD_sal, -1, 0,
- 0,
- OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
- 0, 0 },
- { "op2p1", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
- 0, 0 },
- { "label8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "label12", FIELD_imm12, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", FIELD_imm16, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "bbi", FIELD_bbi, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sae", FIELD_sae, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sas", FIELD_sas, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sargt", FIELD_sargt, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "s", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
- 0, 0 },
- { "immt", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "imms", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "tp7", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "bitindex", FIELD_bitindex, -1, 0,
- 0,
- OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
- 0, 0 },
- { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
- { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
- { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
- { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
- { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
- { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
- { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-enum xtensa_operand_id {
- OPERAND_soffsetx4,
- OPERAND_uimm12x8,
- OPERAND_simm4,
- OPERAND_arr,
- OPERAND_ars,
- OPERAND__ars_invisible,
- OPERAND_art,
- OPERAND_ar0,
- OPERAND_ar4,
- OPERAND_ar8,
- OPERAND_ar12,
- OPERAND_ars_entry,
- OPERAND_immrx4,
- OPERAND_lsi4x4,
- OPERAND_simm7,
- OPERAND_uimm6,
- OPERAND_ai4const,
- OPERAND_b4const,
- OPERAND_b4constu,
- OPERAND_uimm8,
- OPERAND_uimm8x2,
- OPERAND_uimm8x4,
- OPERAND_uimm4x16,
- OPERAND_uimmrx4,
- OPERAND_simm8,
- OPERAND_simm8x256,
- OPERAND_simm12b,
- OPERAND_msalp32,
- OPERAND_op2p1,
- OPERAND_label8,
- OPERAND_label12,
- OPERAND_soffset,
- OPERAND_uimm16x4,
- OPERAND_bbi,
- OPERAND_sae,
- OPERAND_sas,
- OPERAND_sargt,
- OPERAND_s,
- OPERAND_immt,
- OPERAND_imms,
- OPERAND_tp7,
- OPERAND_xt_wbr15_label,
- OPERAND_xt_wbr18_label,
- OPERAND_bitindex,
- OPERAND_t,
- OPERAND_bbi4,
- OPERAND_imm12,
- OPERAND_imm8,
- OPERAND_imm12b,
- OPERAND_imm16,
- OPERAND_m,
- OPERAND_n,
- OPERAND_offset,
- OPERAND_op0,
- OPERAND_op1,
- OPERAND_op2,
- OPERAND_r,
- OPERAND_sa4,
- OPERAND_sae4,
- OPERAND_sal,
- OPERAND_sas4,
- OPERAND_sr,
- OPERAND_st,
- OPERAND_thi3,
- OPERAND_imm4,
- OPERAND_mn,
- OPERAND_i,
- OPERAND_imm6lo,
- OPERAND_imm6hi,
- OPERAND_imm7lo,
- OPERAND_imm7hi,
- OPERAND_z,
- OPERAND_imm6,
- OPERAND_imm7,
- OPERAND_xt_wbr15_imm,
- OPERAND_xt_wbr18_imm,
- OPERAND_s3to1
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSEXCM }, 'o' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { OPERAND_ars_entry }, 's' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm12x8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { OPERAND_simm4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ai4const }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_simm7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8x256 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4const }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bbi }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4constu }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_label12 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sae }, 'i' },
- { { OPERAND_op2p1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { OPERAND_soffset }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_uimm16x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_simm12b }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimmrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { OPERAND_sas }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_msalp32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sargt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_EPC3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_EPC3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_EPC3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_EXCSAVE3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_EXCSAVE3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_EXCSAVE3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_EPC4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_EPC4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_EPC4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_EXCSAVE4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_EXCSAVE4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_EXCSAVE4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
- { { STATE_EPC5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
- { { STATE_EPC5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
- { { STATE_EPC5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
- { { STATE_EXCSAVE5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
- { { STATE_EXCSAVE5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
- { { STATE_EXCSAVE5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
- { { STATE_EPC6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
- { { STATE_EPC6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
- { { STATE_EPC6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
- { { STATE_EXCSAVE6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
- { { STATE_EXCSAVE6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
- { { STATE_EXCSAVE6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
- { { STATE_EPC7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
- { { STATE_EPC7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
- { { STATE_EPC7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
- { { STATE_EXCSAVE7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
- { { STATE_EXCSAVE7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
- { { STATE_EXCSAVE7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_EPS3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_EPS3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_EPS3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_EPS4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_EPS4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
- { { STATE_EPS5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
- { { STATE_EPS5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
- { { STATE_EPS5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
- { { STATE_EPS6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
- { { STATE_EPS6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
- { { STATE_EPS7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
- { { STATE_EPS7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
- { { STATE_EPS7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_VECBASE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_VECBASE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_VECBASE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul16_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPC5 }, 'i' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_EPC7 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_EPS5 }, 'i' },
- { { STATE_EPS6 }, 'i' },
- { { STATE_EPS7 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { OPERAND_imms }, 'i' },
- { { OPERAND_immt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_DBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_DBREAKC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_DBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_DBREAKC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_IBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_IBREAKA0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_IBREAKA0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_IBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_IBREAKA1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_IBREAKA1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_IBREAKENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_IBREAKENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_IBREAKENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_InOCDMode }, 'i' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
- { { STATE_InOCDMode }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_CCOMPARE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_XTSYNC }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
- { { STATE_ATOMCTL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
- { { STATE_ATOMCTL }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
- { { STATE_ATOMCTL }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
- INTERFACE_IMPWIRE
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32nb_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid0_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_configid0_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid1_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc5_args,
- 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc5_args,
- 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc5_args,
- 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave5_args,
- 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave5_args,
- 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave5_args,
- 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc6_args,
- 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc6_args,
- 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc6_args,
- 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave6_args,
- 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave6_args,
- 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave6_args,
- 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc7_args,
- 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc7_args,
- 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc7_args,
- 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave7_args,
- 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave7_args,
- 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave7_args,
- 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps5_args,
- 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps5_args,
- 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps5_args,
- 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps6_args,
- 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps6_args,
- 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps6_args,
- 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps7_args,
- 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps7_args,
- 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps7_args,
- 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_salt_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul16_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_lddr32_p_args,
- 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sddr32_p_args,
- 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_mmid_args,
- 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_atomctl_args,
- 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_atomctl_args,
- 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_atomctl_args,
- 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_div_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eraccess_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eraccess_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eraccess_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rer_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wer_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_expstate_args,
- 1, Iclass_rur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_wur_expstate_args,
- 1, Iclass_wur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_iclass_READ_IMPWIRE_args,
- 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
- { 1, Iclass_iclass_SETB_EXPSTATE_args,
- 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
- { 1, Iclass_iclass_CLRB_EXPSTATE_args,
- 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
- { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
- 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
-};
-
-enum xtensa_iclass_id {
- ICLASS_xt_iclass_excw,
- ICLASS_xt_iclass_rfe,
- ICLASS_xt_iclass_rfde,
- ICLASS_xt_iclass_syscall,
- ICLASS_xt_iclass_call12,
- ICLASS_xt_iclass_call8,
- ICLASS_xt_iclass_call4,
- ICLASS_xt_iclass_callx12,
- ICLASS_xt_iclass_callx8,
- ICLASS_xt_iclass_callx4,
- ICLASS_xt_iclass_entry,
- ICLASS_xt_iclass_movsp,
- ICLASS_xt_iclass_rotw,
- ICLASS_xt_iclass_retw,
- ICLASS_xt_iclass_rfwou,
- ICLASS_xt_iclass_l32e,
- ICLASS_xt_iclass_s32e,
- ICLASS_xt_iclass_rsr_windowbase,
- ICLASS_xt_iclass_wsr_windowbase,
- ICLASS_xt_iclass_xsr_windowbase,
- ICLASS_xt_iclass_rsr_windowstart,
- ICLASS_xt_iclass_wsr_windowstart,
- ICLASS_xt_iclass_xsr_windowstart,
- ICLASS_xt_iclass_add_n,
- ICLASS_xt_iclass_addi_n,
- ICLASS_xt_iclass_bz6,
- ICLASS_xt_iclass_ill_n,
- ICLASS_xt_iclass_loadi4,
- ICLASS_xt_iclass_mov_n,
- ICLASS_xt_iclass_movi_n,
- ICLASS_xt_iclass_nopn,
- ICLASS_xt_iclass_retn,
- ICLASS_xt_iclass_storei4,
- ICLASS_xt_iclass_addi,
- ICLASS_xt_iclass_addmi,
- ICLASS_xt_iclass_addsub,
- ICLASS_xt_iclass_bit,
- ICLASS_xt_iclass_bsi8,
- ICLASS_xt_iclass_bsi8b,
- ICLASS_xt_iclass_bsi8u,
- ICLASS_xt_iclass_bst8,
- ICLASS_xt_iclass_bsz12,
- ICLASS_xt_iclass_call0,
- ICLASS_xt_iclass_callx0,
- ICLASS_xt_iclass_exti,
- ICLASS_xt_iclass_ill,
- ICLASS_xt_iclass_jump,
- ICLASS_xt_iclass_jumpx,
- ICLASS_xt_iclass_l16ui,
- ICLASS_xt_iclass_l16si,
- ICLASS_xt_iclass_l32i,
- ICLASS_xt_iclass_l32r,
- ICLASS_xt_iclass_l8i,
- ICLASS_xt_iclass_movi,
- ICLASS_xt_iclass_movz,
- ICLASS_xt_iclass_neg,
- ICLASS_xt_iclass_nop,
- ICLASS_xt_iclass_return,
- ICLASS_xt_iclass_simcall,
- ICLASS_xt_iclass_s16i,
- ICLASS_xt_iclass_s32i,
- ICLASS_xt_iclass_s32nb,
- ICLASS_xt_iclass_s8i,
- ICLASS_xt_iclass_sar,
- ICLASS_xt_iclass_sari,
- ICLASS_xt_iclass_shifts,
- ICLASS_xt_iclass_shiftst,
- ICLASS_xt_iclass_shiftt,
- ICLASS_xt_iclass_slli,
- ICLASS_xt_iclass_srai,
- ICLASS_xt_iclass_srli,
- ICLASS_xt_iclass_memw,
- ICLASS_xt_iclass_extw,
- ICLASS_xt_iclass_isync,
- ICLASS_xt_iclass_sync,
- ICLASS_xt_iclass_rsil,
- ICLASS_xt_iclass_rsr_sar,
- ICLASS_xt_iclass_wsr_sar,
- ICLASS_xt_iclass_xsr_sar,
- ICLASS_xt_iclass_rsr_memctl,
- ICLASS_xt_iclass_wsr_memctl,
- ICLASS_xt_iclass_xsr_memctl,
- ICLASS_xt_iclass_rsr_litbase,
- ICLASS_xt_iclass_wsr_litbase,
- ICLASS_xt_iclass_xsr_litbase,
- ICLASS_xt_iclass_rsr_configid0,
- ICLASS_xt_iclass_wsr_configid0,
- ICLASS_xt_iclass_rsr_configid1,
- ICLASS_xt_iclass_rsr_ps,
- ICLASS_xt_iclass_wsr_ps,
- ICLASS_xt_iclass_xsr_ps,
- ICLASS_xt_iclass_rsr_epc1,
- ICLASS_xt_iclass_wsr_epc1,
- ICLASS_xt_iclass_xsr_epc1,
- ICLASS_xt_iclass_rsr_excsave1,
- ICLASS_xt_iclass_wsr_excsave1,
- ICLASS_xt_iclass_xsr_excsave1,
- ICLASS_xt_iclass_rsr_epc2,
- ICLASS_xt_iclass_wsr_epc2,
- ICLASS_xt_iclass_xsr_epc2,
- ICLASS_xt_iclass_rsr_excsave2,
- ICLASS_xt_iclass_wsr_excsave2,
- ICLASS_xt_iclass_xsr_excsave2,
- ICLASS_xt_iclass_rsr_epc3,
- ICLASS_xt_iclass_wsr_epc3,
- ICLASS_xt_iclass_xsr_epc3,
- ICLASS_xt_iclass_rsr_excsave3,
- ICLASS_xt_iclass_wsr_excsave3,
- ICLASS_xt_iclass_xsr_excsave3,
- ICLASS_xt_iclass_rsr_epc4,
- ICLASS_xt_iclass_wsr_epc4,
- ICLASS_xt_iclass_xsr_epc4,
- ICLASS_xt_iclass_rsr_excsave4,
- ICLASS_xt_iclass_wsr_excsave4,
- ICLASS_xt_iclass_xsr_excsave4,
- ICLASS_xt_iclass_rsr_epc5,
- ICLASS_xt_iclass_wsr_epc5,
- ICLASS_xt_iclass_xsr_epc5,
- ICLASS_xt_iclass_rsr_excsave5,
- ICLASS_xt_iclass_wsr_excsave5,
- ICLASS_xt_iclass_xsr_excsave5,
- ICLASS_xt_iclass_rsr_epc6,
- ICLASS_xt_iclass_wsr_epc6,
- ICLASS_xt_iclass_xsr_epc6,
- ICLASS_xt_iclass_rsr_excsave6,
- ICLASS_xt_iclass_wsr_excsave6,
- ICLASS_xt_iclass_xsr_excsave6,
- ICLASS_xt_iclass_rsr_epc7,
- ICLASS_xt_iclass_wsr_epc7,
- ICLASS_xt_iclass_xsr_epc7,
- ICLASS_xt_iclass_rsr_excsave7,
- ICLASS_xt_iclass_wsr_excsave7,
- ICLASS_xt_iclass_xsr_excsave7,
- ICLASS_xt_iclass_rsr_eps2,
- ICLASS_xt_iclass_wsr_eps2,
- ICLASS_xt_iclass_xsr_eps2,
- ICLASS_xt_iclass_rsr_eps3,
- ICLASS_xt_iclass_wsr_eps3,
- ICLASS_xt_iclass_xsr_eps3,
- ICLASS_xt_iclass_rsr_eps4,
- ICLASS_xt_iclass_wsr_eps4,
- ICLASS_xt_iclass_xsr_eps4,
- ICLASS_xt_iclass_rsr_eps5,
- ICLASS_xt_iclass_wsr_eps5,
- ICLASS_xt_iclass_xsr_eps5,
- ICLASS_xt_iclass_rsr_eps6,
- ICLASS_xt_iclass_wsr_eps6,
- ICLASS_xt_iclass_xsr_eps6,
- ICLASS_xt_iclass_rsr_eps7,
- ICLASS_xt_iclass_wsr_eps7,
- ICLASS_xt_iclass_xsr_eps7,
- ICLASS_xt_iclass_rsr_excvaddr,
- ICLASS_xt_iclass_wsr_excvaddr,
- ICLASS_xt_iclass_xsr_excvaddr,
- ICLASS_xt_iclass_rsr_depc,
- ICLASS_xt_iclass_wsr_depc,
- ICLASS_xt_iclass_xsr_depc,
- ICLASS_xt_iclass_rsr_exccause,
- ICLASS_xt_iclass_wsr_exccause,
- ICLASS_xt_iclass_xsr_exccause,
- ICLASS_xt_iclass_rsr_misc0,
- ICLASS_xt_iclass_wsr_misc0,
- ICLASS_xt_iclass_xsr_misc0,
- ICLASS_xt_iclass_rsr_misc1,
- ICLASS_xt_iclass_wsr_misc1,
- ICLASS_xt_iclass_xsr_misc1,
- ICLASS_xt_iclass_rsr_prid,
- ICLASS_xt_iclass_rsr_vecbase,
- ICLASS_xt_iclass_wsr_vecbase,
- ICLASS_xt_iclass_xsr_vecbase,
- ICLASS_xt_iclass_salt,
- ICLASS_xt_mul16,
- ICLASS_xt_mul32,
- ICLASS_xt_iclass_rfi,
- ICLASS_xt_iclass_wait,
- ICLASS_xt_iclass_rsr_interrupt,
- ICLASS_xt_iclass_wsr_intset,
- ICLASS_xt_iclass_wsr_intclear,
- ICLASS_xt_iclass_rsr_intenable,
- ICLASS_xt_iclass_wsr_intenable,
- ICLASS_xt_iclass_xsr_intenable,
- ICLASS_xt_iclass_break,
- ICLASS_xt_iclass_break_n,
- ICLASS_xt_iclass_rsr_dbreaka0,
- ICLASS_xt_iclass_wsr_dbreaka0,
- ICLASS_xt_iclass_xsr_dbreaka0,
- ICLASS_xt_iclass_rsr_dbreakc0,
- ICLASS_xt_iclass_wsr_dbreakc0,
- ICLASS_xt_iclass_xsr_dbreakc0,
- ICLASS_xt_iclass_rsr_dbreaka1,
- ICLASS_xt_iclass_wsr_dbreaka1,
- ICLASS_xt_iclass_xsr_dbreaka1,
- ICLASS_xt_iclass_rsr_dbreakc1,
- ICLASS_xt_iclass_wsr_dbreakc1,
- ICLASS_xt_iclass_xsr_dbreakc1,
- ICLASS_xt_iclass_rsr_ibreaka0,
- ICLASS_xt_iclass_wsr_ibreaka0,
- ICLASS_xt_iclass_xsr_ibreaka0,
- ICLASS_xt_iclass_rsr_ibreaka1,
- ICLASS_xt_iclass_wsr_ibreaka1,
- ICLASS_xt_iclass_xsr_ibreaka1,
- ICLASS_xt_iclass_rsr_ibreakenable,
- ICLASS_xt_iclass_wsr_ibreakenable,
- ICLASS_xt_iclass_xsr_ibreakenable,
- ICLASS_xt_iclass_rsr_debugcause,
- ICLASS_xt_iclass_wsr_debugcause,
- ICLASS_xt_iclass_xsr_debugcause,
- ICLASS_xt_iclass_rsr_icount,
- ICLASS_xt_iclass_wsr_icount,
- ICLASS_xt_iclass_xsr_icount,
- ICLASS_xt_iclass_rsr_icountlevel,
- ICLASS_xt_iclass_wsr_icountlevel,
- ICLASS_xt_iclass_xsr_icountlevel,
- ICLASS_xt_iclass_rsr_ddr,
- ICLASS_xt_iclass_wsr_ddr,
- ICLASS_xt_iclass_xsr_ddr,
- ICLASS_xt_iclass_lddr32_p,
- ICLASS_xt_iclass_sddr32_p,
- ICLASS_xt_iclass_rfdo,
- ICLASS_xt_iclass_rfdd,
- ICLASS_xt_iclass_wsr_mmid,
- ICLASS_xt_iclass_rsr_ccount,
- ICLASS_xt_iclass_wsr_ccount,
- ICLASS_xt_iclass_xsr_ccount,
- ICLASS_xt_iclass_rsr_ccompare0,
- ICLASS_xt_iclass_wsr_ccompare0,
- ICLASS_xt_iclass_xsr_ccompare0,
- ICLASS_xt_iclass_rsr_ccompare1,
- ICLASS_xt_iclass_wsr_ccompare1,
- ICLASS_xt_iclass_xsr_ccompare1,
- ICLASS_xt_iclass_rsr_ccompare2,
- ICLASS_xt_iclass_wsr_ccompare2,
- ICLASS_xt_iclass_xsr_ccompare2,
- ICLASS_xt_iclass_idtlb,
- ICLASS_xt_iclass_rdtlb,
- ICLASS_xt_iclass_wdtlb,
- ICLASS_xt_iclass_iitlb,
- ICLASS_xt_iclass_ritlb,
- ICLASS_xt_iclass_witlb,
- ICLASS_xt_iclass_minmax,
- ICLASS_xt_iclass_nsa,
- ICLASS_xt_iclass_sx,
- ICLASS_xt_iclass_l32ai,
- ICLASS_xt_iclass_s32ri,
- ICLASS_xt_iclass_s32c1i,
- ICLASS_xt_iclass_rsr_scompare1,
- ICLASS_xt_iclass_wsr_scompare1,
- ICLASS_xt_iclass_xsr_scompare1,
- ICLASS_xt_iclass_rsr_atomctl,
- ICLASS_xt_iclass_wsr_atomctl,
- ICLASS_xt_iclass_xsr_atomctl,
- ICLASS_xt_iclass_div,
- ICLASS_xt_iclass_rsr_eraccess,
- ICLASS_xt_iclass_wsr_eraccess,
- ICLASS_xt_iclass_xsr_eraccess,
- ICLASS_xt_iclass_rer,
- ICLASS_xt_iclass_wer,
- ICLASS_rur_expstate,
- ICLASS_wur_expstate,
- ICLASS_iclass_READ_IMPWIRE,
- ICLASS_iclass_SETB_EXPSTATE,
- ICLASS_iclass_CLRB_EXPSTATE,
- ICLASS_iclass_WRMSK_EXPSTATE
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2080;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3200;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5000;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x25;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1000;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x408000;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01d;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3400;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3500;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90000;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490000;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34800;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134800;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614800;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34900;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134900;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614900;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf06d;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03d;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00d;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc002;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd002;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800000;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc00000;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900000;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00000;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00000;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00000;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00000;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00000;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300000;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x26;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x66;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe6;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa6;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6007;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe007;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf6;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb6;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1007;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9007;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa007;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2007;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb007;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3007;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8007;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4007;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc007;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5007;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd007;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x56;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd6;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x96;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1002;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9002;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2002;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa002;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x830000;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x930000;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa30000;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb30000;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600100;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20f0;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5100;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5002;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6002;
-}
-
-static void
-Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x590000;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4002;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400000;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x401000;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x402000;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x403000;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404000;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa10000;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x810000;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x910000;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb10000;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10000;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210000;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410000;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c0;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20d0;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2010;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2020;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2030;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30300;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130300;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610300;
-}
-
-static void
-Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36100;
-}
-
-static void
-Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136100;
-}
-
-static void
-Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616100;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30500;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130500;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610500;
-}
-
-static void
-Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b000;
-}
-
-static void
-Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b000;
-}
-
-static void
-Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d000;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e600;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e600;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e600;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b100;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b100;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b100;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d100;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d100;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d100;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b200;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b200;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b200;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d200;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d200;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d200;
-}
-
-static void
-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b300;
-}
-
-static void
-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b300;
-}
-
-static void
-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b300;
-}
-
-static void
-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d300;
-}
-
-static void
-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d300;
-}
-
-static void
-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d300;
-}
-
-static void
-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b400;
-}
-
-static void
-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b400;
-}
-
-static void
-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b400;
-}
-
-static void
-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d400;
-}
-
-static void
-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d400;
-}
-
-static void
-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d400;
-}
-
-static void
-Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b500;
-}
-
-static void
-Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b500;
-}
-
-static void
-Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b500;
-}
-
-static void
-Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d500;
-}
-
-static void
-Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d500;
-}
-
-static void
-Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d500;
-}
-
-static void
-Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b600;
-}
-
-static void
-Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b600;
-}
-
-static void
-Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b600;
-}
-
-static void
-Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d600;
-}
-
-static void
-Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d600;
-}
-
-static void
-Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d600;
-}
-
-static void
-Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b700;
-}
-
-static void
-Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b700;
-}
-
-static void
-Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b700;
-}
-
-static void
-Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d700;
-}
-
-static void
-Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d700;
-}
-
-static void
-Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d700;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c200;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c200;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c200;
-}
-
-static void
-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c300;
-}
-
-static void
-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c300;
-}
-
-static void
-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c300;
-}
-
-static void
-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c400;
-}
-
-static void
-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c400;
-}
-
-static void
-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c400;
-}
-
-static void
-Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c500;
-}
-
-static void
-Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c500;
-}
-
-static void
-Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c500;
-}
-
-static void
-Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c600;
-}
-
-static void
-Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c600;
-}
-
-static void
-Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c600;
-}
-
-static void
-Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c700;
-}
-
-static void
-Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c700;
-}
-
-static void
-Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c700;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ee00;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ee00;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ee00;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c000;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c000;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c000;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e800;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e800;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e800;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f400;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f400;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f400;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f500;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f500;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f500;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3eb00;
-}
-
-static void
-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e700;
-}
-
-static void
-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e700;
-}
-
-static void
-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e700;
-}
-
-static void
-Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x720000;
-}
-
-static void
-Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x620000;
-}
-
-static void
-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc10000;
-}
-
-static void
-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10000;
-}
-
-static void
-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x820000;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3010;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7000;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e200;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e200;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e300;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e400;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e400;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e400;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf02d;
-}
-
-static void
-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39000;
-}
-
-static void
-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139000;
-}
-
-static void
-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619000;
-}
-
-static void
-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a000;
-}
-
-static void
-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a000;
-}
-
-static void
-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a000;
-}
-
-static void
-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39100;
-}
-
-static void
-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x139100;
-}
-
-static void
-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x619100;
-}
-
-static void
-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a100;
-}
-
-static void
-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13a100;
-}
-
-static void
-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61a100;
-}
-
-static void
-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38000;
-}
-
-static void
-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138000;
-}
-
-static void
-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618000;
-}
-
-static void
-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38100;
-}
-
-static void
-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x138100;
-}
-
-static void
-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x618100;
-}
-
-static void
-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36000;
-}
-
-static void
-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136000;
-}
-
-static void
-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616000;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e900;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e900;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e900;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ec00;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ec00;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ec00;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ed00;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ed00;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ed00;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36800;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136800;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616800;
-}
-
-static void
-Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70e0;
-}
-
-static void
-Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70f0;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e000;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e010;
-}
-
-static void
-Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135900;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ea00;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ea00;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ea00;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f000;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f000;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f000;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f100;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f100;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f100;
-}
-
-static void
-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f200;
-}
-
-static void
-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f200;
-}
-
-static void
-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f200;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50c000;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50d000;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50b000;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50f000;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50e000;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x504000;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505000;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x503000;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x507000;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x506000;
-}
-
-static void
-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x430000;
-}
-
-static void
-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530000;
-}
-
-static void
-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x630000;
-}
-
-static void
-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730000;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40e000;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40f000;
-}
-
-static void
-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230000;
-}
-
-static void
-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb002;
-}
-
-static void
-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf002;
-}
-
-static void
-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe002;
-}
-
-static void
-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30c00;
-}
-
-static void
-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130c00;
-}
-
-static void
-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610c00;
-}
-
-static void
-Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36300;
-}
-
-static void
-Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136300;
-}
-
-static void
-Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616300;
-}
-
-static void
-Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc20000;
-}
-
-static void
-Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd20000;
-}
-
-static void
-Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe20000;
-}
-
-static void
-Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf20000;
-}
-
-static void
-Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35f00;
-}
-
-static void
-Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135f00;
-}
-
-static void
-Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615f00;
-}
-
-static void
-Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x406000;
-}
-
-static void
-Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x407000;
-}
-
-static void
-Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e60;
-}
-
-static void
-Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e600;
-}
-
-static void
-Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0000;
-}
-
-static void
-Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1000;
-}
-
-static void
-Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1200;
-}
-
-static void
-Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe2000;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
- Opcode_s32nb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
- Opcode_rsr_memctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
- Opcode_wsr_memctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
- Opcode_xsr_memctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
- Opcode_rsr_configid0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
- Opcode_wsr_configid0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
- Opcode_rsr_configid1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
- Opcode_rsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
- Opcode_wsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
- Opcode_xsr_epc5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
- Opcode_rsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
- Opcode_wsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
- Opcode_xsr_epc6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
- Opcode_rsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
- Opcode_wsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
- Opcode_xsr_epc7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
- Opcode_rsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
- Opcode_wsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
- Opcode_xsr_eps5_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
- Opcode_rsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
- Opcode_wsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
- Opcode_xsr_eps6_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
- Opcode_rsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
- Opcode_wsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
- Opcode_xsr_eps7_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
- Opcode_salt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
- Opcode_saltu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
- Opcode_lddr32_p_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
- Opcode_sddr32_p_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
- Opcode_wsr_mmid_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
- Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
- Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
- Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
- Opcode_quou_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
- Opcode_quos_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
- Opcode_remu_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
- Opcode_rems_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
- Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
- Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
- Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
- Opcode_rer_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
- Opcode_wer_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
- Opcode_rur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
- Opcode_wur_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
- Opcode_read_impwire_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
- Opcode_setb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
- Opcode_clrb_expstate_Slot_inst_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
- Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
-};
-
-
-
-
-\f
-/* Opcode table. */
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", ICLASS_xt_iclass_excw,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", ICLASS_xt_iclass_rfe,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", ICLASS_xt_iclass_rfde,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", ICLASS_xt_iclass_syscall,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "call12", ICLASS_xt_iclass_call12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", ICLASS_xt_iclass_call8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", ICLASS_xt_iclass_call4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", ICLASS_xt_iclass_callx12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", ICLASS_xt_iclass_callx8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", ICLASS_xt_iclass_callx4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", ICLASS_xt_iclass_entry,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", ICLASS_xt_iclass_movsp,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", ICLASS_xt_iclass_rotw,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", ICLASS_xt_iclass_l32e,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", ICLASS_xt_iclass_s32e,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", ICLASS_xt_iclass_add_n,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", ICLASS_xt_iclass_addi_n,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", ICLASS_xt_iclass_ill_n,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", ICLASS_xt_iclass_loadi4,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", ICLASS_xt_iclass_mov_n,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", ICLASS_xt_iclass_movi_n,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", ICLASS_xt_iclass_nopn,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", ICLASS_xt_iclass_retn,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", ICLASS_xt_iclass_storei4,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "addi", ICLASS_xt_iclass_addi,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", ICLASS_xt_iclass_addmi,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", ICLASS_xt_iclass_bit,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", ICLASS_xt_iclass_bit,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", ICLASS_xt_iclass_bit,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", ICLASS_xt_iclass_call0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", ICLASS_xt_iclass_callx0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", ICLASS_xt_iclass_exti,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", ICLASS_xt_iclass_ill,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", ICLASS_xt_iclass_jump,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", ICLASS_xt_iclass_jumpx,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", ICLASS_xt_iclass_l16ui,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", ICLASS_xt_iclass_l16si,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", ICLASS_xt_iclass_l32i,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", ICLASS_xt_iclass_l32r,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", ICLASS_xt_iclass_l8i,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "movi", ICLASS_xt_iclass_movi,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", ICLASS_xt_iclass_neg,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", ICLASS_xt_iclass_neg,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", ICLASS_xt_iclass_nop,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", ICLASS_xt_iclass_return,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "simcall", ICLASS_xt_iclass_simcall,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "s16i", ICLASS_xt_iclass_s16i,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", ICLASS_xt_iclass_s32i,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s32nb", ICLASS_xt_iclass_s32nb,
- 0,
- Opcode_s32nb_encode_fns, 0, 0 },
- { "s8i", ICLASS_xt_iclass_s8i,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", ICLASS_xt_iclass_sari,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", ICLASS_xt_iclass_shifts,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", ICLASS_xt_iclass_shiftst,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", ICLASS_xt_iclass_slli,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", ICLASS_xt_iclass_srai,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", ICLASS_xt_iclass_srli,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", ICLASS_xt_iclass_memw,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", ICLASS_xt_iclass_extw,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", ICLASS_xt_iclass_isync,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", ICLASS_xt_iclass_rsil,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
- 0,
- Opcode_rsr_memctl_encode_fns, 0, 0 },
- { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
- 0,
- Opcode_wsr_memctl_encode_fns, 0, 0 },
- { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
- 0,
- Opcode_xsr_memctl_encode_fns, 0, 0 },
- { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
- 0,
- Opcode_rsr_configid0_encode_fns, 0, 0 },
- { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
- 0,
- Opcode_wsr_configid0_encode_fns, 0, 0 },
- { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
- 0,
- Opcode_rsr_configid1_encode_fns, 0, 0 },
- { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
- 0,
- Opcode_rsr_epc5_encode_fns, 0, 0 },
- { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
- 0,
- Opcode_wsr_epc5_encode_fns, 0, 0 },
- { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
- 0,
- Opcode_xsr_epc5_encode_fns, 0, 0 },
- { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
- 0,
- Opcode_rsr_excsave5_encode_fns, 0, 0 },
- { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
- 0,
- Opcode_wsr_excsave5_encode_fns, 0, 0 },
- { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
- 0,
- Opcode_xsr_excsave5_encode_fns, 0, 0 },
- { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
- 0,
- Opcode_rsr_epc6_encode_fns, 0, 0 },
- { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
- 0,
- Opcode_wsr_epc6_encode_fns, 0, 0 },
- { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
- 0,
- Opcode_xsr_epc6_encode_fns, 0, 0 },
- { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
- 0,
- Opcode_rsr_excsave6_encode_fns, 0, 0 },
- { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
- 0,
- Opcode_wsr_excsave6_encode_fns, 0, 0 },
- { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
- 0,
- Opcode_xsr_excsave6_encode_fns, 0, 0 },
- { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
- 0,
- Opcode_rsr_epc7_encode_fns, 0, 0 },
- { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
- 0,
- Opcode_wsr_epc7_encode_fns, 0, 0 },
- { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
- 0,
- Opcode_xsr_epc7_encode_fns, 0, 0 },
- { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
- 0,
- Opcode_rsr_excsave7_encode_fns, 0, 0 },
- { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
- 0,
- Opcode_wsr_excsave7_encode_fns, 0, 0 },
- { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
- 0,
- Opcode_xsr_excsave7_encode_fns, 0, 0 },
- { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
- 0,
- Opcode_rsr_eps5_encode_fns, 0, 0 },
- { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
- 0,
- Opcode_wsr_eps5_encode_fns, 0, 0 },
- { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
- 0,
- Opcode_xsr_eps5_encode_fns, 0, 0 },
- { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
- 0,
- Opcode_rsr_eps6_encode_fns, 0, 0 },
- { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
- 0,
- Opcode_wsr_eps6_encode_fns, 0, 0 },
- { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
- 0,
- Opcode_xsr_eps6_encode_fns, 0, 0 },
- { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
- 0,
- Opcode_rsr_eps7_encode_fns, 0, 0 },
- { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
- 0,
- Opcode_wsr_eps7_encode_fns, 0, 0 },
- { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
- 0,
- Opcode_xsr_eps7_encode_fns, 0, 0 },
- { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "salt", ICLASS_xt_iclass_salt,
- 0,
- Opcode_salt_encode_fns, 0, 0 },
- { "saltu", ICLASS_xt_iclass_salt,
- 0,
- Opcode_saltu_encode_fns, 0, 0 },
- { "mul16u", ICLASS_xt_mul16,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", ICLASS_xt_mul16,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "mull", ICLASS_xt_mul32,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "rfi", ICLASS_xt_iclass_rfi,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", ICLASS_xt_iclass_wait,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", ICLASS_xt_iclass_break,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", ICLASS_xt_iclass_break_n,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
- 0,
- Opcode_lddr32_p_encode_fns, 0, 0 },
- { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
- 0,
- Opcode_sddr32_p_encode_fns, 0, 0 },
- { "rfdo", ICLASS_xt_iclass_rfdo,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", ICLASS_xt_iclass_rfdd,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
- 0,
- Opcode_wsr_mmid_encode_fns, 0, 0 },
- { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "idtlb", ICLASS_xt_iclass_idtlb,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", ICLASS_xt_iclass_wdtlb,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", ICLASS_xt_iclass_iitlb,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", ICLASS_xt_iclass_witlb,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "min", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", ICLASS_xt_iclass_sx,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", ICLASS_xt_iclass_l32ai,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", ICLASS_xt_iclass_s32ri,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", ICLASS_xt_iclass_s32c1i,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
- 0,
- Opcode_rsr_atomctl_encode_fns, 0, 0 },
- { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
- 0,
- Opcode_wsr_atomctl_encode_fns, 0, 0 },
- { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
- 0,
- Opcode_xsr_atomctl_encode_fns, 0, 0 },
- { "quou", ICLASS_xt_iclass_div,
- 0,
- Opcode_quou_encode_fns, 0, 0 },
- { "quos", ICLASS_xt_iclass_div,
- 0,
- Opcode_quos_encode_fns, 0, 0 },
- { "remu", ICLASS_xt_iclass_div,
- 0,
- Opcode_remu_encode_fns, 0, 0 },
- { "rems", ICLASS_xt_iclass_div,
- 0,
- Opcode_rems_encode_fns, 0, 0 },
- { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
- 0,
- Opcode_rsr_eraccess_encode_fns, 0, 0 },
- { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
- 0,
- Opcode_wsr_eraccess_encode_fns, 0, 0 },
- { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
- 0,
- Opcode_xsr_eraccess_encode_fns, 0, 0 },
- { "rer", ICLASS_xt_iclass_rer,
- 0,
- Opcode_rer_encode_fns, 0, 0 },
- { "wer", ICLASS_xt_iclass_wer,
- 0,
- Opcode_wer_encode_fns, 0, 0 },
- { "rur.expstate", ICLASS_rur_expstate,
- 0,
- Opcode_rur_expstate_encode_fns, 0, 0 },
- { "wur.expstate", ICLASS_wur_expstate,
- 0,
- Opcode_wur_expstate_encode_fns, 0, 0 },
- { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
- 0,
- Opcode_read_impwire_encode_fns, 0, 0 },
- { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
- 0,
- Opcode_setb_expstate_encode_fns, 0, 0 },
- { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
- 0,
- Opcode_clrb_expstate_encode_fns, 0, 0 },
- { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
- 0,
- Opcode_wrmsk_expstate_encode_fns, 0, 0 }
-};
-
-enum xtensa_opcode_id {
- OPCODE_EXCW,
- OPCODE_RFE,
- OPCODE_RFDE,
- OPCODE_SYSCALL,
- OPCODE_CALL12,
- OPCODE_CALL8,
- OPCODE_CALL4,
- OPCODE_CALLX12,
- OPCODE_CALLX8,
- OPCODE_CALLX4,
- OPCODE_ENTRY,
- OPCODE_MOVSP,
- OPCODE_ROTW,
- OPCODE_RETW,
- OPCODE_RETW_N,
- OPCODE_RFWO,
- OPCODE_RFWU,
- OPCODE_L32E,
- OPCODE_S32E,
- OPCODE_RSR_WINDOWBASE,
- OPCODE_WSR_WINDOWBASE,
- OPCODE_XSR_WINDOWBASE,
- OPCODE_RSR_WINDOWSTART,
- OPCODE_WSR_WINDOWSTART,
- OPCODE_XSR_WINDOWSTART,
- OPCODE_ADD_N,
- OPCODE_ADDI_N,
- OPCODE_BEQZ_N,
- OPCODE_BNEZ_N,
- OPCODE_ILL_N,
- OPCODE_L32I_N,
- OPCODE_MOV_N,
- OPCODE_MOVI_N,
- OPCODE_NOP_N,
- OPCODE_RET_N,
- OPCODE_S32I_N,
- OPCODE_ADDI,
- OPCODE_ADDMI,
- OPCODE_ADD,
- OPCODE_SUB,
- OPCODE_ADDX2,
- OPCODE_ADDX4,
- OPCODE_ADDX8,
- OPCODE_SUBX2,
- OPCODE_SUBX4,
- OPCODE_SUBX8,
- OPCODE_AND,
- OPCODE_OR,
- OPCODE_XOR,
- OPCODE_BEQI,
- OPCODE_BNEI,
- OPCODE_BGEI,
- OPCODE_BLTI,
- OPCODE_BBCI,
- OPCODE_BBSI,
- OPCODE_BGEUI,
- OPCODE_BLTUI,
- OPCODE_BEQ,
- OPCODE_BNE,
- OPCODE_BGE,
- OPCODE_BLT,
- OPCODE_BGEU,
- OPCODE_BLTU,
- OPCODE_BANY,
- OPCODE_BNONE,
- OPCODE_BALL,
- OPCODE_BNALL,
- OPCODE_BBC,
- OPCODE_BBS,
- OPCODE_BEQZ,
- OPCODE_BNEZ,
- OPCODE_BGEZ,
- OPCODE_BLTZ,
- OPCODE_CALL0,
- OPCODE_CALLX0,
- OPCODE_EXTUI,
- OPCODE_ILL,
- OPCODE_J,
- OPCODE_JX,
- OPCODE_L16UI,
- OPCODE_L16SI,
- OPCODE_L32I,
- OPCODE_L32R,
- OPCODE_L8UI,
- OPCODE_MOVI,
- OPCODE_MOVEQZ,
- OPCODE_MOVNEZ,
- OPCODE_MOVLTZ,
- OPCODE_MOVGEZ,
- OPCODE_NEG,
- OPCODE_ABS,
- OPCODE_NOP,
- OPCODE_RET,
- OPCODE_SIMCALL,
- OPCODE_S16I,
- OPCODE_S32I,
- OPCODE_S32NB,
- OPCODE_S8I,
- OPCODE_SSR,
- OPCODE_SSL,
- OPCODE_SSA8L,
- OPCODE_SSA8B,
- OPCODE_SSAI,
- OPCODE_SLL,
- OPCODE_SRC,
- OPCODE_SRL,
- OPCODE_SRA,
- OPCODE_SLLI,
- OPCODE_SRAI,
- OPCODE_SRLI,
- OPCODE_MEMW,
- OPCODE_EXTW,
- OPCODE_ISYNC,
- OPCODE_RSYNC,
- OPCODE_ESYNC,
- OPCODE_DSYNC,
- OPCODE_RSIL,
- OPCODE_RSR_SAR,
- OPCODE_WSR_SAR,
- OPCODE_XSR_SAR,
- OPCODE_RSR_MEMCTL,
- OPCODE_WSR_MEMCTL,
- OPCODE_XSR_MEMCTL,
- OPCODE_RSR_LITBASE,
- OPCODE_WSR_LITBASE,
- OPCODE_XSR_LITBASE,
- OPCODE_RSR_CONFIGID0,
- OPCODE_WSR_CONFIGID0,
- OPCODE_RSR_CONFIGID1,
- OPCODE_RSR_PS,
- OPCODE_WSR_PS,
- OPCODE_XSR_PS,
- OPCODE_RSR_EPC1,
- OPCODE_WSR_EPC1,
- OPCODE_XSR_EPC1,
- OPCODE_RSR_EXCSAVE1,
- OPCODE_WSR_EXCSAVE1,
- OPCODE_XSR_EXCSAVE1,
- OPCODE_RSR_EPC2,
- OPCODE_WSR_EPC2,
- OPCODE_XSR_EPC2,
- OPCODE_RSR_EXCSAVE2,
- OPCODE_WSR_EXCSAVE2,
- OPCODE_XSR_EXCSAVE2,
- OPCODE_RSR_EPC3,
- OPCODE_WSR_EPC3,
- OPCODE_XSR_EPC3,
- OPCODE_RSR_EXCSAVE3,
- OPCODE_WSR_EXCSAVE3,
- OPCODE_XSR_EXCSAVE3,
- OPCODE_RSR_EPC4,
- OPCODE_WSR_EPC4,
- OPCODE_XSR_EPC4,
- OPCODE_RSR_EXCSAVE4,
- OPCODE_WSR_EXCSAVE4,
- OPCODE_XSR_EXCSAVE4,
- OPCODE_RSR_EPC5,
- OPCODE_WSR_EPC5,
- OPCODE_XSR_EPC5,
- OPCODE_RSR_EXCSAVE5,
- OPCODE_WSR_EXCSAVE5,
- OPCODE_XSR_EXCSAVE5,
- OPCODE_RSR_EPC6,
- OPCODE_WSR_EPC6,
- OPCODE_XSR_EPC6,
- OPCODE_RSR_EXCSAVE6,
- OPCODE_WSR_EXCSAVE6,
- OPCODE_XSR_EXCSAVE6,
- OPCODE_RSR_EPC7,
- OPCODE_WSR_EPC7,
- OPCODE_XSR_EPC7,
- OPCODE_RSR_EXCSAVE7,
- OPCODE_WSR_EXCSAVE7,
- OPCODE_XSR_EXCSAVE7,
- OPCODE_RSR_EPS2,
- OPCODE_WSR_EPS2,
- OPCODE_XSR_EPS2,
- OPCODE_RSR_EPS3,
- OPCODE_WSR_EPS3,
- OPCODE_XSR_EPS3,
- OPCODE_RSR_EPS4,
- OPCODE_WSR_EPS4,
- OPCODE_XSR_EPS4,
- OPCODE_RSR_EPS5,
- OPCODE_WSR_EPS5,
- OPCODE_XSR_EPS5,
- OPCODE_RSR_EPS6,
- OPCODE_WSR_EPS6,
- OPCODE_XSR_EPS6,
- OPCODE_RSR_EPS7,
- OPCODE_WSR_EPS7,
- OPCODE_XSR_EPS7,
- OPCODE_RSR_EXCVADDR,
- OPCODE_WSR_EXCVADDR,
- OPCODE_XSR_EXCVADDR,
- OPCODE_RSR_DEPC,
- OPCODE_WSR_DEPC,
- OPCODE_XSR_DEPC,
- OPCODE_RSR_EXCCAUSE,
- OPCODE_WSR_EXCCAUSE,
- OPCODE_XSR_EXCCAUSE,
- OPCODE_RSR_MISC0,
- OPCODE_WSR_MISC0,
- OPCODE_XSR_MISC0,
- OPCODE_RSR_MISC1,
- OPCODE_WSR_MISC1,
- OPCODE_XSR_MISC1,
- OPCODE_RSR_PRID,
- OPCODE_RSR_VECBASE,
- OPCODE_WSR_VECBASE,
- OPCODE_XSR_VECBASE,
- OPCODE_SALT,
- OPCODE_SALTU,
- OPCODE_MUL16U,
- OPCODE_MUL16S,
- OPCODE_MULL,
- OPCODE_RFI,
- OPCODE_WAITI,
- OPCODE_RSR_INTERRUPT,
- OPCODE_WSR_INTSET,
- OPCODE_WSR_INTCLEAR,
- OPCODE_RSR_INTENABLE,
- OPCODE_WSR_INTENABLE,
- OPCODE_XSR_INTENABLE,
- OPCODE_BREAK,
- OPCODE_BREAK_N,
- OPCODE_RSR_DBREAKA0,
- OPCODE_WSR_DBREAKA0,
- OPCODE_XSR_DBREAKA0,
- OPCODE_RSR_DBREAKC0,
- OPCODE_WSR_DBREAKC0,
- OPCODE_XSR_DBREAKC0,
- OPCODE_RSR_DBREAKA1,
- OPCODE_WSR_DBREAKA1,
- OPCODE_XSR_DBREAKA1,
- OPCODE_RSR_DBREAKC1,
- OPCODE_WSR_DBREAKC1,
- OPCODE_XSR_DBREAKC1,
- OPCODE_RSR_IBREAKA0,
- OPCODE_WSR_IBREAKA0,
- OPCODE_XSR_IBREAKA0,
- OPCODE_RSR_IBREAKA1,
- OPCODE_WSR_IBREAKA1,
- OPCODE_XSR_IBREAKA1,
- OPCODE_RSR_IBREAKENABLE,
- OPCODE_WSR_IBREAKENABLE,
- OPCODE_XSR_IBREAKENABLE,
- OPCODE_RSR_DEBUGCAUSE,
- OPCODE_WSR_DEBUGCAUSE,
- OPCODE_XSR_DEBUGCAUSE,
- OPCODE_RSR_ICOUNT,
- OPCODE_WSR_ICOUNT,
- OPCODE_XSR_ICOUNT,
- OPCODE_RSR_ICOUNTLEVEL,
- OPCODE_WSR_ICOUNTLEVEL,
- OPCODE_XSR_ICOUNTLEVEL,
- OPCODE_RSR_DDR,
- OPCODE_WSR_DDR,
- OPCODE_XSR_DDR,
- OPCODE_LDDR32_P,
- OPCODE_SDDR32_P,
- OPCODE_RFDO,
- OPCODE_RFDD,
- OPCODE_WSR_MMID,
- OPCODE_RSR_CCOUNT,
- OPCODE_WSR_CCOUNT,
- OPCODE_XSR_CCOUNT,
- OPCODE_RSR_CCOMPARE0,
- OPCODE_WSR_CCOMPARE0,
- OPCODE_XSR_CCOMPARE0,
- OPCODE_RSR_CCOMPARE1,
- OPCODE_WSR_CCOMPARE1,
- OPCODE_XSR_CCOMPARE1,
- OPCODE_RSR_CCOMPARE2,
- OPCODE_WSR_CCOMPARE2,
- OPCODE_XSR_CCOMPARE2,
- OPCODE_IDTLB,
- OPCODE_PDTLB,
- OPCODE_RDTLB0,
- OPCODE_RDTLB1,
- OPCODE_WDTLB,
- OPCODE_IITLB,
- OPCODE_PITLB,
- OPCODE_RITLB0,
- OPCODE_RITLB1,
- OPCODE_WITLB,
- OPCODE_MIN,
- OPCODE_MAX,
- OPCODE_MINU,
- OPCODE_MAXU,
- OPCODE_NSA,
- OPCODE_NSAU,
- OPCODE_SEXT,
- OPCODE_L32AI,
- OPCODE_S32RI,
- OPCODE_S32C1I,
- OPCODE_RSR_SCOMPARE1,
- OPCODE_WSR_SCOMPARE1,
- OPCODE_XSR_SCOMPARE1,
- OPCODE_RSR_ATOMCTL,
- OPCODE_WSR_ATOMCTL,
- OPCODE_XSR_ATOMCTL,
- OPCODE_QUOU,
- OPCODE_QUOS,
- OPCODE_REMU,
- OPCODE_REMS,
- OPCODE_RSR_ERACCESS,
- OPCODE_WSR_ERACCESS,
- OPCODE_XSR_ERACCESS,
- OPCODE_RER,
- OPCODE_WER,
- OPCODE_RUR_EXPSTATE,
- OPCODE_WUR_EXPSTATE,
- OPCODE_READ_IMPWIRE,
- OPCODE_SETB_EXPSTATE,
- OPCODE_CLRB_EXPSTATE,
- OPCODE_WRMSK_EXPSTATE
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst_get (insn) == 0)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- {
- if (Field_m_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_ILL;
- if (Field_m_Slot_inst_get (insn) == 2)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_RET;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_RETW;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_JX;
- }
- if (Field_m_Slot_inst_get (insn) == 3)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALLX0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALLX4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALLX8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALLX12;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_MOVSP;
- if (Field_r_Slot_inst_get (insn) == 2)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_ISYNC;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RSYNC;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_ESYNC;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DSYNC;
- if (Field_t_Slot_inst_get (insn) == 8)
- return OPCODE_EXCW;
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_MEMW;
- if (Field_t_Slot_inst_get (insn) == 13)
- return OPCODE_EXTW;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_NOP;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 3)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_RFE;
- if (Field_s_Slot_inst_get (insn) == 2)
- return OPCODE_RFDE;
- if (Field_s_Slot_inst_get (insn) == 4)
- return OPCODE_RFWO;
- if (Field_s_Slot_inst_get (insn) == 5)
- return OPCODE_RFWU;
- }
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFI;
- }
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BREAK;
- if (Field_r_Slot_inst_get (insn) == 5)
- {
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SYSCALL;
- if (Field_s_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SIMCALL;
- }
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RSIL;
- if (Field_r_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_WAITI;
- if (Field_r_Slot_inst_get (insn) == 7)
- {
- if (Field_t_Slot_inst_get (insn) == 14)
- return OPCODE_LDDR32_P;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_SDDR32_P;
- }
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- return OPCODE_AND;
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_OR;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_XOR;
- if (Field_op2_Slot_inst_get (insn) == 4)
- {
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSR;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSL;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8L;
- if (Field_r_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8B;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_thi3_Slot_inst_get (insn) == 0)
- return OPCODE_SSAI;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RER;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_WER;
- if (Field_r_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_ROTW;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_NSA;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_NSAU;
- }
- if (Field_op2_Slot_inst_get (insn) == 5)
- {
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_RITLB0;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IITLB;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_PITLB;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_WITLB;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_RITLB1;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_RDTLB0;
- if (Field_r_Slot_inst_get (insn) == 12 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IDTLB;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_PDTLB;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_WDTLB;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_RDTLB1;
- }
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_NEG;
- if (Field_s_Slot_inst_get (insn) == 1)
- return OPCODE_ABS;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_ADD;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_ADDX2;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_ADDX4;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_ADDX8;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_SUB;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_SUBX2;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_SUBX4;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_SUBX8;
- }
- if (Field_op1_Slot_inst_get (insn) == 1)
- {
- if ((Field_op2_Slot_inst_get (insn) == 0 ||
- Field_op2_Slot_inst_get (insn) == 1))
- return OPCODE_SLLI;
- if ((Field_op2_Slot_inst_get (insn) == 2 ||
- Field_op2_Slot_inst_get (insn) == 3))
- return OPCODE_SRAI;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_SRLI;
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_XSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_XSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_XSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_XSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_XSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 95)
- return OPCODE_XSR_ERACCESS;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_XSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_XSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_XSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_XSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_XSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_XSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_XSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_XSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_XSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_XSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_XSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_XSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_XSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_XSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_XSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_XSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_XSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_XSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_XSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_XSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_XSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_XSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_XSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_XSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_XSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_XSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_XSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_XSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_XSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_XSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_XSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_XSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_XSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_XSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_XSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_XSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_XSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_XSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_XSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_XSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_XSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_XSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_XSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_XSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_XSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_SRC;
- if (Field_op2_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRL;
- if (Field_op2_Slot_inst_get (insn) == 10 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SLL;
- if (Field_op2_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRA;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_MUL16U;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_MUL16S;
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_RFDO;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFDD;
- }
- }
- if (Field_op1_Slot_inst_get (insn) == 2)
- {
- if (Field_op2_Slot_inst_get (insn) == 6)
- return OPCODE_SALTU;
- if (Field_op2_Slot_inst_get (insn) == 7)
- return OPCODE_SALT;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MULL;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_QUOU;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_QUOS;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_REMU;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_REMS;
- }
- if (Field_op1_Slot_inst_get (insn) == 3)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_RSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_RSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_RSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_RSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_RSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 95)
- return OPCODE_RSR_ERACCESS;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_RSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_RSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_RSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_RSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_RSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_RSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_RSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_RSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_RSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_RSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_RSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_RSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_RSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_RSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_RSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_RSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_RSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_RSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_RSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_RSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_RSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_RSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_RSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_RSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_RSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 208)
- return OPCODE_RSR_CONFIGID1;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_RSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_RSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_RSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_RSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_RSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_RSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_RSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_RSR_INTERRUPT;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_RSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_RSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_RSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_RSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_RSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_RSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 235)
- return OPCODE_RSR_PRID;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_RSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_RSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_RSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_RSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_RSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_RSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_RSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_RSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- {
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_WSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_WSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_WSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_WSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_WSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 89)
- return OPCODE_WSR_MMID;
- if (Field_sr_Slot_inst_get (insn) == 95)
- return OPCODE_WSR_ERACCESS;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_WSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_WSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_WSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_WSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_WSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_WSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_WSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_WSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_WSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_WSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_WSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_WSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_WSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_WSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_WSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_WSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_WSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_WSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_WSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_WSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_WSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_WSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_WSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_WSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_WSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_WSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_WSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_WSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_WSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_WSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_WSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_WSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_WSR_INTSET;
- if (Field_sr_Slot_inst_get (insn) == 227)
- return OPCODE_WSR_INTCLEAR;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_WSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_WSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_WSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_WSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_WSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_WSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_WSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_WSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_WSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_WSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_WSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_WSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_WSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_SEXT;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_MIN;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_MAX;
- if (Field_op2_Slot_inst_get (insn) == 6)
- return OPCODE_MINU;
- if (Field_op2_Slot_inst_get (insn) == 7)
- return OPCODE_MAXU;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MOVEQZ;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_MOVNEZ;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_MOVLTZ;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_MOVGEZ;
- if (Field_op2_Slot_inst_get (insn) == 14)
- {
- if (Field_st_Slot_inst_get (insn) == 230)
- return OPCODE_RUR_EXPSTATE;
- }
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WUR_EXPSTATE;
- }
- }
- if ((Field_op1_Slot_inst_get (insn) == 4 ||
- Field_op1_Slot_inst_get (insn) == 5))
- return OPCODE_EXTUI;
- if (Field_op1_Slot_inst_get (insn) == 9)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_L32E;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_S32E;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_S32NB;
- }
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_READ_IMPWIRE;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s3to1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_SETB_EXPSTATE;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s3to1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_CLRB_EXPSTATE;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_WRMSK_EXPSTATE;
- }
- if (Field_op0_Slot_inst_get (insn) == 1)
- return OPCODE_L32R;
- if (Field_op0_Slot_inst_get (insn) == 2)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_L8UI;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_L16UI;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_L32I;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_S8I;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_S16I;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_S32I;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_L16SI;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_MOVI;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_L32AI;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_ADDI;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_ADDMI;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_S32C1I;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_S32RI;
- }
- if (Field_op0_Slot_inst_get (insn) == 5)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALL0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALL4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALL8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALL12;
- }
- if (Field_op0_Slot_inst_get (insn) == 6)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_J;
- if (Field_n_Slot_inst_get (insn) == 1)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQZ;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEZ;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTZ;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEZ;
- }
- if (Field_n_Slot_inst_get (insn) == 2)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQI;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEI;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEI;
- }
- if (Field_n_Slot_inst_get (insn) == 3)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_ENTRY;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTUI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEUI;
- }
- }
- if (Field_op0_Slot_inst_get (insn) == 7)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_BNONE;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_BEQ;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_BLT;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_BLTU;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BALL;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_BBC;
- if ((Field_r_Slot_inst_get (insn) == 6 ||
- Field_r_Slot_inst_get (insn) == 7))
- return OPCODE_BBCI;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_BANY;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_BNE;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_BGE;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_BGEU;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_BNALL;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_BBS;
- if ((Field_r_Slot_inst_get (insn) == 14 ||
- Field_r_Slot_inst_get (insn) == 15))
- return OPCODE_BBSI;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16b_get (insn) == 12)
- {
- if (Field_i_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOVI_N;
- if (Field_i_Slot_inst16b_get (insn) == 1)
- {
- if (Field_z_Slot_inst16b_get (insn) == 0)
- return OPCODE_BEQZ_N;
- if (Field_z_Slot_inst16b_get (insn) == 1)
- return OPCODE_BNEZ_N;
- }
- }
- if (Field_op0_Slot_inst16b_get (insn) == 13)
- {
- if (Field_r_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOV_N;
- if (Field_r_Slot_inst16b_get (insn) == 15)
- {
- if (Field_t_Slot_inst16b_get (insn) == 0)
- return OPCODE_RET_N;
- if (Field_t_Slot_inst16b_get (insn) == 1)
- return OPCODE_RETW_N;
- if (Field_t_Slot_inst16b_get (insn) == 2)
- return OPCODE_BREAK_N;
- if (Field_t_Slot_inst16b_get (insn) == 3 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_NOP_N;
- if (Field_t_Slot_inst16b_get (insn) == 6 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_ILL_N;
- }
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16a_get (insn) == 8)
- return OPCODE_L32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 9)
- return OPCODE_S32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 10)
- return OPCODE_ADD_N;
- if (Field_op0_Slot_inst16a_get (insn) == 11)
- return OPCODE_ADDI_N;
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffffff);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- Field_bitindex_Slot_inst_get,
- Field_s3to1_Slot_inst_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- Field_bitindex_Slot_inst_set,
- Field_s3to1_Slot_inst_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_get,
- Field_s3to1_Slot_inst16a_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_set,
- Field_s3to1_Slot_inst16a_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_get,
- Field_s3to1_Slot_inst16b_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_set,
- Field_s3to1_Slot_inst16b_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0x8;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xc;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0x8) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc) == 0x8)
- return 1; /* x16a */
- if ((insn[0] & 0xe) == 0xc)
- return 2; /* x16b */
- return -1;
-}
-
-static int length_table[256] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int l = insn[0];
- return length_table[l];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 0 /* little-endian */,
- 3 /* insn_size */, 0,
- 3, formats, format_decoder, length_decoder,
- 3, slots,
- 43 /* num_fields */,
- 77, operands,
- 263, iclasses,
- 317, opcodes, 0,
- 1, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 1, interfaces, 0,
- 0, funcUnits, 0
-};
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_test_kc705_be
-#include "core-test_kc705_be/xtensa-modules.inc.c"
+#include "core-test_kc705_be/xtensa-modules.c.inc"
static XtensaConfig test_kc705_be __attribute__((unused)) = {
.name = "test_kc705_be",
.gdb_regmap = {
.reg = {
-#include "core-test_kc705_be/gdb-config.inc.c"
+#include "core-test_kc705_be/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
--- /dev/null
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
+ XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
+ XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
+ XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
+ XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
+ XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
+ XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
+ XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
+ XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
+ XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
+ XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
+ "03:40:48:2b","03:40:48:7a",0,0,0,0)
+ XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
+ "03:40:49:2b","03:40:49:7a",0,0,0,0)
+ XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
+ "03:40:4a:2b","03:40:4a:7a",0,0,0,0)
+ XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
+ "03:40:4b:2b","03:40:4b:7a",0,0,0,0)
+ XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
+ "03:40:4c:2b","03:40:4c:7a",0,0,0,0)
+ XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
+ "03:40:4d:2b","03:40:4d:7a",0,0,0,0)
+ XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
+ "03:40:4e:2b","03:40:4e:7a",0,0,0,0)
+ XTREG( 60,268,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
+ "03:40:4f:2b","03:40:4f:7a",0,0,0,0)
+ XTREG( 61,276,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
+ "03:40:40:3c","03:40:40:1c",0,0,0,0)
+ XTREG( 62,284,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
+ "03:40:41:3c","03:40:44:1c",0,0,0,0)
+ XTREG( 63,292,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
+ "03:40:42:3c","03:40:48:1c",0,0,0,0)
+ XTREG( 64,300,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
+ "03:40:43:3c","03:40:4c:1c",0,0,0,0)
+ XTREG( 65,308, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
+ XTREG( 66,312,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
+ XTREG( 67,316,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
+ XTREG( 68,320,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
+ XTREG( 69,324,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
+ XTREG( 70,328,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
+ XTREG( 71,332,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
+ XTREG( 72,336,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG( 73,340,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
+ XTREG( 74,344,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
+ XTREG( 75,348,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
+ XTREG( 76,352, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG( 77,356, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG( 78,360,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG( 79,364,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG( 80,368,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG( 81,372,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG( 82,376,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG( 83,380,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG( 84,384,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG( 85,388,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG( 86,392,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG( 87,396,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG( 88,400,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG( 90,408,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG( 91,412,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG( 92,416,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG( 93,420,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG( 94,424,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG( 95,428,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG( 96,432,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG( 97,436,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG( 98,440,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG( 99,444,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG(100,448,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG(101,452,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG(102,456,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG(103,460,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG(104,464,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG(105,468,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG(106,472, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
+ XTREG(107,476,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG(108,480,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG(109,484,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG(112,496, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG(113,500,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG(114,504,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG(115,508,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG(116,512,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG(117,516, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG(119,524,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG(120,528,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG(121,532,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG(122,536,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG(124,544,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG(125,548,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG(126,552,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG(127,556,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG(128,560,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG(129,564,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG(130,568,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG(131,572,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG(132,576,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG(133,580,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG(134,584,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(135,588,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(136,592,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(137,596,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(138,600,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(139,604,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(140,608, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
+ 0,0,&xtensa_mask0,0,0,0)
+ XTREG(141,609, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
+ 0,0,&xtensa_mask1,0,0,0)
+ XTREG(142,610, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
+ 0,0,&xtensa_mask2,0,0,0)
+ XTREG(143,611, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
+ 0,0,&xtensa_mask3,0,0,0)
+ XTREG(144,612, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
+ 0,0,&xtensa_mask4,0,0,0)
+ XTREG(145,613, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
+ 0,0,&xtensa_mask5,0,0,0)
+ XTREG(146,614, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
+ 0,0,&xtensa_mask6,0,0,0)
+ XTREG(147,615, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
+ 0,0,&xtensa_mask7,0,0,0)
+ XTREG(148,616, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
+ 0,0,&xtensa_mask8,0,0,0)
+ XTREG(149,617, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
+ 0,0,&xtensa_mask9,0,0,0)
+ XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
+ 0,0,&xtensa_mask10,0,0,0)
+ XTREG(151,619, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
+ 0,0,&xtensa_mask11,0,0,0)
+ XTREG(152,620, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
+ 0,0,&xtensa_mask12,0,0,0)
+ XTREG(153,621, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
+ 0,0,&xtensa_mask13,0,0,0)
+ XTREG(154,622, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
+ 0,0,&xtensa_mask14,0,0,0)
+ XTREG(155,623, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
+ 0,0,&xtensa_mask15,0,0,0)
+ XTREG(156,624, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask16,0,0,0)
+ XTREG(157,628, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask17,0,0,0)
+ XTREG(158,632, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask18,0,0,0)
+ XTREG(159,636, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
+ 0,0,&xtensa_mask19,0,0,0)
+ XTREG(160,640, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask20,0,0,0)
+ XTREG(161,644, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask21,0,0,0)
+ XTREG(162,648, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask22,0,0,0)
+ XTREG(163,652,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc,
+ 0,0,&xtensa_mask23,0,0,0)
+ XTREG(164,660, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum,
+ 0,0,&xtensa_mask24,0,0,0)
+ XTREG(165,664, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
+ 0,0,&xtensa_mask25,0,0,0)
+ XTREG(166,668, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
+ 0,0,&xtensa_mask26,0,0,0)
+ XTREG(167,672, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
+ 0,0,&xtensa_mask27,0,0,0)
+ XTREG(168,676, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid6,
+ 0,0,&xtensa_mask28,0,0,0)
+ XTREG(169,680, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid5,
+ 0,0,&xtensa_mask29,0,0,0)
+ XTREG(170,684, 2, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid4,
+ 0,0,&xtensa_mask30,0,0,0)
+ XTREG(171,688, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid6,
+ 0,0,&xtensa_mask31,0,0,0)
+ XTREG(172,692, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid5,
+ 0,0,&xtensa_mask32,0,0,0)
+ XTREG(173,696, 2, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid4,
+ 0,0,&xtensa_mask33,0,0,0)
+ XTREG(174,700,10, 4, 4,0x201f,0x0006,-2, 6,0x1010,ptbase,
+ 0,0,&xtensa_mask34,0,0,0)
+ XTREG(175,704, 1, 4, 4,0x2021,0x0006, 1, 5,0x1010,ae_overflow,
+ 0,0,&xtensa_mask35,0,0,0)
+ XTREG(176,708, 6, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_sar,
+ 0,0,&xtensa_mask36,0,0,0)
+ XTREG(177,712, 4, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_bitptr,
+ 0,0,&xtensa_mask37,0,0,0)
+ XTREG(178,716, 4, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_bitsused,
+ 0,0,&xtensa_mask38,0,0,0)
+ XTREG(179,720, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_tablesize,
+ 0,0,&xtensa_mask39,0,0,0)
+ XTREG(180,724, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_first_ts,
+ 0,0,&xtensa_mask40,0,0,0)
+ XTREG(181,728,27, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_nextoffset,
+ 0,0,&xtensa_mask41,0,0,0)
+ XTREG_END
+++ /dev/null
-/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
-
- Copyright (c) 2003-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
- XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
- XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
- XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
- XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
- XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
- XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
- XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
- XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
- XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
- XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
- XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
- XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
- XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
- XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
- XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
- XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
- XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
- XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
- XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
- XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
- XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
- XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
- XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
- XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
- XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
- XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
- XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
- XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
- XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
- XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
- XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
- XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
- XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
- XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
- XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
- XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
- XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
- XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
- XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
- XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
- XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
- XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
- XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
- XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
- XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
- XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
- XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
- XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
- XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
- "03:40:48:2b","03:40:48:7a",0,0,0,0)
- XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
- "03:40:49:2b","03:40:49:7a",0,0,0,0)
- XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
- "03:40:4a:2b","03:40:4a:7a",0,0,0,0)
- XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
- "03:40:4b:2b","03:40:4b:7a",0,0,0,0)
- XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
- "03:40:4c:2b","03:40:4c:7a",0,0,0,0)
- XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
- "03:40:4d:2b","03:40:4d:7a",0,0,0,0)
- XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
- "03:40:4e:2b","03:40:4e:7a",0,0,0,0)
- XTREG( 60,268,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
- "03:40:4f:2b","03:40:4f:7a",0,0,0,0)
- XTREG( 61,276,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
- "03:40:40:3c","03:40:40:1c",0,0,0,0)
- XTREG( 62,284,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
- "03:40:41:3c","03:40:44:1c",0,0,0,0)
- XTREG( 63,292,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
- "03:40:42:3c","03:40:48:1c",0,0,0,0)
- XTREG( 64,300,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
- "03:40:43:3c","03:40:4c:1c",0,0,0,0)
- XTREG( 65,308, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
- XTREG( 66,312,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
- XTREG( 67,316,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
- XTREG( 68,320,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
- XTREG( 69,324,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
- XTREG( 70,328,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
- XTREG( 71,332,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
- XTREG( 72,336,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
- XTREG( 73,340,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
- XTREG( 74,344,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
- XTREG( 75,348,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
- XTREG( 76,352, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
- XTREG( 77,356, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
- XTREG( 78,360,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
- XTREG( 79,364,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
- XTREG( 80,368,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
- XTREG( 81,372,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
- XTREG( 82,376,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
- XTREG( 83,380,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
- XTREG( 84,384,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
- XTREG( 85,388,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
- XTREG( 86,392,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
- XTREG( 87,396,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
- XTREG( 88,400,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
- XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
- XTREG( 90,408,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
- XTREG( 91,412,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
- XTREG( 92,416,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
- XTREG( 93,420,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
- XTREG( 94,424,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
- XTREG( 95,428,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
- XTREG( 96,432,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
- XTREG( 97,436,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
- XTREG( 98,440,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
- XTREG( 99,444,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
- XTREG(100,448,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
- XTREG(101,452,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
- XTREG(102,456,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
- XTREG(103,460,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
- XTREG(104,464,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
- XTREG(105,468,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
- XTREG(106,472, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
- XTREG(107,476,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
- XTREG(108,480,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
- XTREG(109,484,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
- XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
- XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
- XTREG(112,496, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
- XTREG(113,500,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
- XTREG(114,504,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
- XTREG(115,508,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
- XTREG(116,512,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
- XTREG(117,516, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
- XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
- XTREG(119,524,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
- XTREG(120,528,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
- XTREG(121,532,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
- XTREG(122,536,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
- XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
- XTREG(124,544,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
- XTREG(125,548,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
- XTREG(126,552,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
- XTREG(127,556,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
- XTREG(128,560,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
- XTREG(129,564,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
- XTREG(130,568,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
- XTREG(131,572,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
- XTREG(132,576,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
- XTREG(133,580,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
- XTREG(134,584,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
- XTREG(135,588,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
- XTREG(136,592,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
- XTREG(137,596,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
- XTREG(138,600,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
- XTREG(139,604,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
- XTREG(140,608, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
- 0,0,&xtensa_mask0,0,0,0)
- XTREG(141,609, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
- 0,0,&xtensa_mask1,0,0,0)
- XTREG(142,610, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
- 0,0,&xtensa_mask2,0,0,0)
- XTREG(143,611, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
- 0,0,&xtensa_mask3,0,0,0)
- XTREG(144,612, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
- 0,0,&xtensa_mask4,0,0,0)
- XTREG(145,613, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
- 0,0,&xtensa_mask5,0,0,0)
- XTREG(146,614, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
- 0,0,&xtensa_mask6,0,0,0)
- XTREG(147,615, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
- 0,0,&xtensa_mask7,0,0,0)
- XTREG(148,616, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
- 0,0,&xtensa_mask8,0,0,0)
- XTREG(149,617, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
- 0,0,&xtensa_mask9,0,0,0)
- XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
- 0,0,&xtensa_mask10,0,0,0)
- XTREG(151,619, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
- 0,0,&xtensa_mask11,0,0,0)
- XTREG(152,620, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
- 0,0,&xtensa_mask12,0,0,0)
- XTREG(153,621, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
- 0,0,&xtensa_mask13,0,0,0)
- XTREG(154,622, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
- 0,0,&xtensa_mask14,0,0,0)
- XTREG(155,623, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
- 0,0,&xtensa_mask15,0,0,0)
- XTREG(156,624, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
- 0,0,&xtensa_mask16,0,0,0)
- XTREG(157,628, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
- 0,0,&xtensa_mask17,0,0,0)
- XTREG(158,632, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
- 0,0,&xtensa_mask18,0,0,0)
- XTREG(159,636, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
- 0,0,&xtensa_mask19,0,0,0)
- XTREG(160,640, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
- 0,0,&xtensa_mask20,0,0,0)
- XTREG(161,644, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
- 0,0,&xtensa_mask21,0,0,0)
- XTREG(162,648, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
- 0,0,&xtensa_mask22,0,0,0)
- XTREG(163,652,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc,
- 0,0,&xtensa_mask23,0,0,0)
- XTREG(164,660, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum,
- 0,0,&xtensa_mask24,0,0,0)
- XTREG(165,664, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
- 0,0,&xtensa_mask25,0,0,0)
- XTREG(166,668, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
- 0,0,&xtensa_mask26,0,0,0)
- XTREG(167,672, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
- 0,0,&xtensa_mask27,0,0,0)
- XTREG(168,676, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid6,
- 0,0,&xtensa_mask28,0,0,0)
- XTREG(169,680, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid5,
- 0,0,&xtensa_mask29,0,0,0)
- XTREG(170,684, 2, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid4,
- 0,0,&xtensa_mask30,0,0,0)
- XTREG(171,688, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid6,
- 0,0,&xtensa_mask31,0,0,0)
- XTREG(172,692, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid5,
- 0,0,&xtensa_mask32,0,0,0)
- XTREG(173,696, 2, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid4,
- 0,0,&xtensa_mask33,0,0,0)
- XTREG(174,700,10, 4, 4,0x201f,0x0006,-2, 6,0x1010,ptbase,
- 0,0,&xtensa_mask34,0,0,0)
- XTREG(175,704, 1, 4, 4,0x2021,0x0006, 1, 5,0x1010,ae_overflow,
- 0,0,&xtensa_mask35,0,0,0)
- XTREG(176,708, 6, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_sar,
- 0,0,&xtensa_mask36,0,0,0)
- XTREG(177,712, 4, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_bitptr,
- 0,0,&xtensa_mask37,0,0,0)
- XTREG(178,716, 4, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_bitsused,
- 0,0,&xtensa_mask38,0,0,0)
- XTREG(179,720, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_tablesize,
- 0,0,&xtensa_mask39,0,0,0)
- XTREG(180,724, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_first_ts,
- 0,0,&xtensa_mask40,0,0,0)
- XTREG(181,728,27, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_nextoffset,
- 0,0,&xtensa_mask41,0,0,0)
- XTREG_END
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+
+ Copyright (c) 2003-2015 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "BR", 4, 0 },
+ { "ACCLO", 16, 0 },
+ { "ACCHI", 17, 0 },
+ { "M0", 32, 0 },
+ { "M1", 33, 0 },
+ { "M2", 34, 0 },
+ { "M3", 35, 0 },
+ { "PTEVADDR", 83, 0 },
+ { "MMID", 89, 0 },
+ { "DDR", 104, 0 },
+ { "CONFIGID0", 176, 0 },
+ { "CONFIGID1", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "CCOMPARE2", 242, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EPC3", 179, 0 },
+ { "EPC4", 180, 0 },
+ { "EPC5", 181, 0 },
+ { "EPC6", 182, 0 },
+ { "EPC7", 183, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EXCSAVE3", 211, 0 },
+ { "EXCSAVE4", 212, 0 },
+ { "EXCSAVE5", 213, 0 },
+ { "EXCSAVE6", 214, 0 },
+ { "EXCSAVE7", 215, 0 },
+ { "EPS2", 194, 0 },
+ { "EPS3", 195, 0 },
+ { "EPS4", 196, 0 },
+ { "EPS5", 197, 0 },
+ { "EPS6", 198, 0 },
+ { "EPS7", 199, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "DBREAKA0", 144, 0 },
+ { "DBREAKC0", 160, 0 },
+ { "DBREAKA1", 145, 0 },
+ { "DBREAKC1", 161, 0 },
+ { "IBREAKA0", 128, 0 },
+ { "IBREAKA1", 129, 0 },
+ { "IBREAKENABLE", 96, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "PREFCTL", 40, 0 },
+ { "RASID", 90, 0 },
+ { "ITLBCFG", 91, 0 },
+ { "DTLBCFG", 92, 0 },
+ { "CPENABLE", 224, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "THREADPTR", 231, 1 },
+ { "AE_OVF_SAR", 240, 1 },
+ { "AE_BITHEAD", 241, 1 },
+ { "AE_TS_FTS_BU_BP", 242, 1 },
+ { "AE_SD_NO", 243, 1 },
+ { "AE_CBEGIN0", 246, 1 },
+ { "AE_CEND0", 247, 1 },
+ { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 78
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 247
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 22, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EPC3", 32, 0 },
+ { "EPC4", 32, 0 },
+ { "EPC5", 32, 0 },
+ { "EPC6", 32, 0 },
+ { "EPC7", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EXCSAVE3", 32, 0 },
+ { "EXCSAVE4", 32, 0 },
+ { "EXCSAVE5", 32, 0 },
+ { "EXCSAVE6", 32, 0 },
+ { "EXCSAVE7", 32, 0 },
+ { "EPS2", 15, 0 },
+ { "EPS3", 15, 0 },
+ { "EPS4", 15, 0 },
+ { "EPS5", 15, 0 },
+ { "EPS6", 15, 0 },
+ { "EPS7", 15, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSRING", 2, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "THREADPTR", 32, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "ACC", 40, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 22, 0 },
+ { "DBREAKA0", 32, 0 },
+ { "DBREAKC0", 8, 0 },
+ { "DBREAKA1", 32, 0 },
+ { "DBREAKC1", 8, 0 },
+ { "IBREAKA0", 32, 0 },
+ { "IBREAKA1", 32, 0 },
+ { "IBREAKENABLE", 2, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "CCOMPARE2", 32, 0 },
+ { "PREFCTL", 9, 0 },
+ { "ASID3", 8, 0 },
+ { "ASID2", 8, 0 },
+ { "ASID1", 8, 0 },
+ { "INSTPGSZID6", 1, 0 },
+ { "INSTPGSZID5", 1, 0 },
+ { "INSTPGSZID4", 2, 0 },
+ { "DATAPGSZID6", 1, 0 },
+ { "DATAPGSZID5", 1, 0 },
+ { "DATAPGSZID4", 2, 0 },
+ { "PTBASE", 10, 0 },
+ { "CPENABLE", 8, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "ERI_RAW_INTERLOCK", 1, 0 },
+ { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR },
+ { "AE_SAR", 6, 0 },
+ { "AE_BITHEAD", 32, 0 },
+ { "AE_BITPTR", 4, 0 },
+ { "AE_BITSUSED", 4, 0 },
+ { "AE_TABLESIZE", 4, 0 },
+ { "AE_FIRST_TS", 4, 0 },
+ { "AE_NEXTOFFSET", 27, 0 },
+ { "AE_SEARCHDONE", 1, 0 },
+ { "AE_CBEGIN0", 32, 0 },
+ { "AE_CEND0", 32, 0 },
+ { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 89
+
+enum xtensa_state_id {
+ STATE_LCOUNT,
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EPC3,
+ STATE_EPC4,
+ STATE_EPC5,
+ STATE_EPC6,
+ STATE_EPC7,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EXCSAVE3,
+ STATE_EXCSAVE4,
+ STATE_EXCSAVE5,
+ STATE_EXCSAVE6,
+ STATE_EXCSAVE7,
+ STATE_EPS2,
+ STATE_EPS3,
+ STATE_EPS4,
+ STATE_EPS5,
+ STATE_EPS6,
+ STATE_EPS7,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSRING,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_LBEG,
+ STATE_LEND,
+ STATE_SAR,
+ STATE_THREADPTR,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_ACC,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_DBREAKA0,
+ STATE_DBREAKC0,
+ STATE_DBREAKA1,
+ STATE_DBREAKC1,
+ STATE_IBREAKA0,
+ STATE_IBREAKA1,
+ STATE_IBREAKENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_CCOMPARE2,
+ STATE_PREFCTL,
+ STATE_ASID3,
+ STATE_ASID2,
+ STATE_ASID1,
+ STATE_INSTPGSZID6,
+ STATE_INSTPGSZID5,
+ STATE_INSTPGSZID4,
+ STATE_DATAPGSZID6,
+ STATE_DATAPGSZID5,
+ STATE_DATAPGSZID4,
+ STATE_PTBASE,
+ STATE_CPENABLE,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_ERI_RAW_INTERLOCK,
+ STATE_AE_OVERFLOW,
+ STATE_AE_SAR,
+ STATE_AE_BITHEAD,
+ STATE_AE_BITPTR,
+ STATE_AE_BITSUSED,
+ STATE_AE_TABLESIZE,
+ STATE_AE_FIRST_TS,
+ STATE_AE_NEXTOFFSET,
+ STATE_AE_SEARCHDONE,
+ STATE_AE_CBEGIN0,
+ STATE_AE_CEND0,
+ STATE_EXPSTATE
+};
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf333ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf333ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_ftsf359ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf359ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_ftsf355ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf355ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf354ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf354ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
+}
+
+static unsigned
+Field_ftsf357ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf357ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9);
+ tie_t = (val << 26) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 27) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf347ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf347ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10);
+}
+
+static unsigned
+Field_ftsf345ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf345ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 26) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+ tie_t = (val << 22) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf358ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf358ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 20) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf93ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf93ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 26) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+ tie_t = (val << 22) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf55_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf55_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf121ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf121ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 21) >> 24;
+ insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf91_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 22) >> 27;
+ insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_ftsf351_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf351_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 21) >> 26;
+ insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 20) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf20ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf20ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf356ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf356ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf62ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf62ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
+}
+
+static unsigned
+Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf352ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf352ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 20) >> 23;
+ insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 20) >> 23;
+ insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf123ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf123ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+ tie_t = (val << 23) >> 29;
+ insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 29) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf117ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf117ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf68ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf68ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+ tie_t = (val << 28) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf61_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf61_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf83ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf83ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 25) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf70ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf70ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf74ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf74ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf85ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf85ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf102ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf102ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 23) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+ tie_t = (val << 26) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_ftsf335_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf335_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
+}
+
+static unsigned
+Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf208ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf208ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf340ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf340ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld69_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld68_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld19_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld74_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld66_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld90_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld88_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld65_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld79_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
+}
+
+static unsigned
+Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf280_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf280_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf288_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf288_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
+}
+
+static unsigned
+Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x380) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf211ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf211ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 21) >> 29;
+ insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
+ tie_t = (val << 17) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20);
+ return tie_t;
+}
+
+static void
+Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
+ tie_t = (val << 18) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
+ tie_t = (val << 26) >> 31;
+ insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 21) >> 29;
+ insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
+ tie_t = (val << 17) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf287ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf287ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 23) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+ tie_t = (val << 22) >> 31;
+ insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
+}
+
+static unsigned
+Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 26) >> 27;
+ insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf285ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf285ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 23) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+ tie_t = (val << 21) >> 30;
+ insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
+}
+
+static unsigned
+Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 23) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+ tie_t = (val << 20) >> 29;
+ insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 28) >> 29;
+ insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 14) | ((insn[0] << 11) >> 18);
+ return tie_t;
+}
+
+static void
+Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 18) >> 18;
+ insn[0] = (insn[0] & ~0x1fff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf309_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf309_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf327ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf327ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+ tie_t = (val << 21) >> 30;
+ insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
+}
+
+static unsigned
+Field_ftsf363ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf363ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf373ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf373ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_ftsf376ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf376ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 21) >> 29;
+ insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_ftsf370ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf370ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x18000) | (tie_t << 15);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_ftsf378ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf378ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf217ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf217ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf305ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf305ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf307ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf307ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+ tie_t = (val << 27) >> 29;
+ insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf379ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf379ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
+ tie_t = (val << 29) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
+ return tie_t;
+}
+
+static void
+Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 19) >> 19;
+ insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf315_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf315_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld52_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
+}
+
+static unsigned
+Field_combined1e9fefee_fld96_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined1e9fefee_fld96_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_combined1e9fefee_fld98_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_combined1e9fefee_fld98_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld49_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld50_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld40_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf362_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf362_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_op0_s4_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s4_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+}
+
+static unsigned
+Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30);
+ return tie_t;
+}
+
+static void
+Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x18000) | (tie_t << 15);
+}
+
+static unsigned
+Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld47_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
+ return tie_t;
+}
+
+static void
+Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
+}
+
+static unsigned
+Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
+ return tie_t;
+}
+
+static void
+Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+ tie_t = (val << 19) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf289ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf289ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+ tie_t = (val << 19) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20);
+ return tie_t;
+}
+
+static void
+Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7);
+ tie_t = (val << 19) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 24) >> 31;
+ insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
+}
+
+static unsigned
+Field_ftsf386ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf386ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 26) >> 27;
+ insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+ tie_t = (val << 18) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 24) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+ tie_t = (val << 21) >> 29;
+ insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_ftsf382ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf382ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf291ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf291ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 24) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 24) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
+}
+
+static unsigned
+Field_ftsf383ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf383ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 28) >> 29;
+ insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf293ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf293ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+ tie_t = (val << 24) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
+}
+
+static unsigned
+Field_ftsf384ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf384ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22);
+ return tie_t;
+}
+
+static void
+Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 22) >> 22;
+ insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf387ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf387ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
+ tie_t = (val << 25) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf319ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22);
+ return tie_t;
+}
+
+static void
+Field_ftsf319ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 22) >> 22;
+ insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7);
+ tie_t = (val << 21) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf388ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf388ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
+ tie_t = (val << 27) >> 29;
+ insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
+ tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22);
+ return tie_t;
+}
+
+static void
+Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 22) >> 22;
+ insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7);
+ tie_t = (val << 21) >> 31;
+ insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
+ tie_t = (val << 20) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf389ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf389ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
+ tie_t = (val << 28) >> 29;
+ insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
+}
+
+static unsigned
+Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20);
+ return tie_t;
+}
+
+static void
+Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7);
+ tie_t = (val << 19) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 23) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+ tie_t = (val << 21) >> 30;
+ insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
+}
+
+static unsigned
+Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+ tie_t = (val << 22) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+ tie_t = (val << 18) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld123_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld121_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld28_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld127_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld46_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 5) >> 24);
+ tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x7800) | (tie_t << 11);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0x7f80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 9) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0x7ff800) | (tie_t << 11);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
+}
+
+static unsigned
+Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
+ return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
+ return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+ return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+ tie_t = (val << 29) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
+ return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
+}
+
+static unsigned
+Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
+ return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
+}
+
+static unsigned
+Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
+}
+
+static unsigned
+Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
+ return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
+}
+
+static unsigned
+Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
+ return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
+}
+
+static unsigned
+Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+}
+
+static unsigned
+Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
+}
+
+static unsigned
+Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26);
+ return tie_t;
+}
+
+static void
+Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 26) >> 26;
+ insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
+ tie_t = (val << 26) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf11_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf11_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_ftsf11_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf11_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf11_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+ tie_t = (val << 29) >> 31;
+ insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld37_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld37_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 11) | ((insn[0] << 14) >> 21);
+ return tie_t;
+}
+
+static void
+Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 21) >> 21;
+ insn[0] = (insn[0] & ~0x3ff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
+
+static unsigned
+Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_r3,
+ FIELD_rbit2,
+ FIELD_rhi,
+ FIELD_t3,
+ FIELD_tbit2,
+ FIELD_tlo,
+ FIELD_w,
+ FIELD_y,
+ FIELD_x,
+ FIELD_t2,
+ FIELD_s2,
+ FIELD_r2,
+ FIELD_t4,
+ FIELD_s4,
+ FIELD_r4,
+ FIELD_t8,
+ FIELD_s8,
+ FIELD_r8,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_ae_r3,
+ FIELD_ae_s_non_samt,
+ FIELD_ae_s3,
+ FIELD_ae_r32,
+ FIELD_ae_samt_s_t,
+ FIELD_ae_r20,
+ FIELD_ae_r10,
+ FIELD_ae_s20,
+ FIELD_ae_fld_ohba,
+ FIELD_ae_fld_ohba2,
+ FIELD_op0_s3,
+ FIELD_ftsf11,
+ FIELD_ftsf12,
+ FIELD_ftsf13,
+ FIELD_ftsf20ae_slot1,
+ FIELD_ftsf21ae_slot1,
+ FIELD_ftsf22ae_slot1,
+ FIELD_ftsf23ae_slot1,
+ FIELD_ftsf24ae_slot1,
+ FIELD_ftsf25ae_slot1,
+ FIELD_ftsf26ae_slot1,
+ FIELD_ftsf27ae_slot1,
+ FIELD_ftsf28ae_slot1,
+ FIELD_ftsf29ae_slot1,
+ FIELD_ftsf30ae_slot1,
+ FIELD_ftsf31ae_slot1,
+ FIELD_ftsf32ae_slot1,
+ FIELD_ftsf33ae_slot1,
+ FIELD_ftsf34ae_slot1,
+ FIELD_ftsf35ae_slot1,
+ FIELD_ftsf36ae_slot1,
+ FIELD_ftsf37ae_slot1,
+ FIELD_ftsf38ae_slot1,
+ FIELD_ftsf40ae_slot1,
+ FIELD_ftsf41ae_slot1,
+ FIELD_ftsf42ae_slot1,
+ FIELD_ftsf43ae_slot1,
+ FIELD_ftsf45ae_slot1,
+ FIELD_ftsf47ae_slot1,
+ FIELD_ftsf48ae_slot1,
+ FIELD_ftsf49ae_slot1,
+ FIELD_ftsf50ae_slot1,
+ FIELD_ftsf51ae_slot1,
+ FIELD_ftsf52ae_slot1,
+ FIELD_ftsf53ae_slot1,
+ FIELD_ftsf54ae_slot1,
+ FIELD_ftsf55,
+ FIELD_ftsf56ae_slot1,
+ FIELD_ftsf57ae_slot1,
+ FIELD_ftsf58ae_slot1,
+ FIELD_ftsf60ae_slot1,
+ FIELD_ftsf61,
+ FIELD_ftsf62ae_slot1,
+ FIELD_ftsf63ae_slot1,
+ FIELD_ftsf64ae_slot1,
+ FIELD_ftsf66ae_slot1,
+ FIELD_ftsf68ae_slot1,
+ FIELD_ftsf69ae_slot1,
+ FIELD_ftsf70ae_slot1,
+ FIELD_ftsf71ae_slot1,
+ FIELD_ftsf72ae_slot1,
+ FIELD_ftsf73ae_slot1,
+ FIELD_ftsf74ae_slot1,
+ FIELD_ftsf75ae_slot1,
+ FIELD_ftsf76ae_slot1,
+ FIELD_ftsf77ae_slot1,
+ FIELD_ftsf78ae_slot1,
+ FIELD_ftsf79ae_slot1,
+ FIELD_ftsf80ae_slot1,
+ FIELD_ftsf81ae_slot1,
+ FIELD_ftsf82ae_slot1,
+ FIELD_ftsf83ae_slot1,
+ FIELD_ftsf84ae_slot1,
+ FIELD_ftsf85ae_slot1,
+ FIELD_ftsf86ae_slot1,
+ FIELD_ftsf87ae_slot1,
+ FIELD_ftsf88ae_slot1,
+ FIELD_ftsf89ae_slot1,
+ FIELD_ftsf90ae_slot1,
+ FIELD_ftsf91,
+ FIELD_ftsf92ae_slot1,
+ FIELD_ftsf93ae_slot1,
+ FIELD_ftsf94ae_slot1,
+ FIELD_ftsf96ae_slot1,
+ FIELD_ftsf97ae_slot1,
+ FIELD_ftsf99ae_slot1,
+ FIELD_ftsf101ae_slot1,
+ FIELD_ftsf102ae_slot1,
+ FIELD_ftsf103ae_slot1,
+ FIELD_ftsf106ae_slot1,
+ FIELD_ftsf107ae_slot1,
+ FIELD_ftsf108ae_slot1,
+ FIELD_ftsf109ae_slot1,
+ FIELD_ftsf110ae_slot1,
+ FIELD_ftsf111ae_slot1,
+ FIELD_ftsf112ae_slot1,
+ FIELD_ftsf113ae_slot1,
+ FIELD_ftsf114ae_slot1,
+ FIELD_ftsf115ae_slot1,
+ FIELD_ftsf116ae_slot1,
+ FIELD_ftsf117ae_slot1,
+ FIELD_ftsf118ae_slot1,
+ FIELD_ftsf120ae_slot1,
+ FIELD_ftsf121ae_slot1,
+ FIELD_ftsf123ae_slot1,
+ FIELD_ftsf124ae_slot1,
+ FIELD_ftsf125ae_slot1,
+ FIELD_ftsf126ae_slot1,
+ FIELD_ftsf127ae_slot1,
+ FIELD_ftsf128ae_slot1,
+ FIELD_ftsf129ae_slot1,
+ FIELD_ftsf130ae_slot1,
+ FIELD_ftsf131ae_slot1,
+ FIELD_ftsf132ae_slot1,
+ FIELD_ftsf133ae_slot1,
+ FIELD_ftsf134ae_slot1,
+ FIELD_ftsf135ae_slot1,
+ FIELD_ftsf136ae_slot1,
+ FIELD_ftsf137ae_slot1,
+ FIELD_ftsf138ae_slot1,
+ FIELD_ftsf139ae_slot1,
+ FIELD_ftsf140ae_slot1,
+ FIELD_ftsf141ae_slot1,
+ FIELD_ftsf142ae_slot1,
+ FIELD_ftsf143ae_slot1,
+ FIELD_ftsf144ae_slot1,
+ FIELD_ftsf145ae_slot1,
+ FIELD_ftsf146ae_slot1,
+ FIELD_ftsf147ae_slot1,
+ FIELD_ftsf148ae_slot1,
+ FIELD_ftsf149ae_slot1,
+ FIELD_ftsf150ae_slot1,
+ FIELD_ftsf151ae_slot1,
+ FIELD_ftsf152ae_slot1,
+ FIELD_ftsf153ae_slot1,
+ FIELD_ftsf154ae_slot1,
+ FIELD_ftsf155ae_slot1,
+ FIELD_ftsf156ae_slot1,
+ FIELD_ftsf157ae_slot1,
+ FIELD_ftsf158ae_slot1,
+ FIELD_ftsf159ae_slot1,
+ FIELD_ftsf160ae_slot1,
+ FIELD_ftsf161ae_slot1,
+ FIELD_ftsf162ae_slot1,
+ FIELD_ftsf163ae_slot1,
+ FIELD_ftsf164ae_slot1,
+ FIELD_ftsf165ae_slot1,
+ FIELD_ftsf166ae_slot1,
+ FIELD_ftsf167ae_slot1,
+ FIELD_ftsf168ae_slot1,
+ FIELD_ftsf169ae_slot1,
+ FIELD_ftsf170ae_slot1,
+ FIELD_ftsf171ae_slot1,
+ FIELD_ftsf172ae_slot1,
+ FIELD_ftsf173ae_slot1,
+ FIELD_ftsf174ae_slot1,
+ FIELD_ftsf175ae_slot1,
+ FIELD_ftsf176ae_slot1,
+ FIELD_ftsf177ae_slot1,
+ FIELD_ftsf178ae_slot1,
+ FIELD_ftsf179ae_slot1,
+ FIELD_ftsf180ae_slot1,
+ FIELD_ftsf181ae_slot1,
+ FIELD_ftsf182ae_slot1,
+ FIELD_ftsf183ae_slot1,
+ FIELD_ftsf184ae_slot1,
+ FIELD_ftsf185ae_slot1,
+ FIELD_ftsf186ae_slot1,
+ FIELD_ftsf187ae_slot1,
+ FIELD_ftsf188ae_slot1,
+ FIELD_ftsf189ae_slot1,
+ FIELD_ftsf190ae_slot1,
+ FIELD_ftsf191ae_slot1,
+ FIELD_ftsf192ae_slot1,
+ FIELD_ftsf193ae_slot1,
+ FIELD_ftsf194ae_slot1,
+ FIELD_ftsf195ae_slot1,
+ FIELD_ftsf196ae_slot1,
+ FIELD_ftsf197ae_slot1,
+ FIELD_ftsf198ae_slot1,
+ FIELD_ftsf199ae_slot1,
+ FIELD_ftsf200ae_slot1,
+ FIELD_ftsf201ae_slot1,
+ FIELD_ftsf202ae_slot1,
+ FIELD_ftsf203ae_slot1,
+ FIELD_ftsf204ae_slot1,
+ FIELD_ftsf205ae_slot1,
+ FIELD_ftsf206ae_slot1,
+ FIELD_ftsf207ae_slot1,
+ FIELD_ftsf208ae_slot1,
+ FIELD_ftsf210ae_slot1,
+ FIELD_ftsf333ae_slot1,
+ FIELD_ftsf334ae_slot1,
+ FIELD_ftsf335,
+ FIELD_ftsf336ae_slot1,
+ FIELD_ftsf337ae_slot1,
+ FIELD_ftsf339ae_slot1,
+ FIELD_ftsf340ae_slot1,
+ FIELD_ftsf341ae_slot1,
+ FIELD_ftsf342ae_slot1,
+ FIELD_ftsf343ae_slot1,
+ FIELD_ftsf344ae_slot1,
+ FIELD_ftsf345ae_slot1,
+ FIELD_ftsf347ae_slot1,
+ FIELD_ftsf348ae_slot1,
+ FIELD_ftsf349ae_slot1,
+ FIELD_ftsf350ae_slot1,
+ FIELD_ftsf351,
+ FIELD_ftsf352ae_slot1,
+ FIELD_ftsf354ae_slot1,
+ FIELD_ftsf355ae_slot1,
+ FIELD_ftsf356ae_slot1,
+ FIELD_ftsf357ae_slot1,
+ FIELD_ftsf358ae_slot1,
+ FIELD_ftsf359ae_slot1,
+ FIELD_op0_s4,
+ FIELD_ftsf211ae_slot0,
+ FIELD_ftsf212ae_slot0,
+ FIELD_ftsf213ae_slot0,
+ FIELD_ftsf214ae_slot0,
+ FIELD_ftsf215ae_slot0,
+ FIELD_ftsf217ae_slot0,
+ FIELD_ftsf218ae_slot0,
+ FIELD_ftsf219ae_slot0,
+ FIELD_ftsf220ae_slot0,
+ FIELD_ftsf221ae_slot0,
+ FIELD_ftsf222ae_slot0,
+ FIELD_ftsf223ae_slot0,
+ FIELD_ftsf224ae_slot0,
+ FIELD_ftsf225ae_slot0,
+ FIELD_ftsf226ae_slot0,
+ FIELD_ftsf227ae_slot0,
+ FIELD_ftsf228ae_slot0,
+ FIELD_ftsf229ae_slot0,
+ FIELD_ftsf230ae_slot0,
+ FIELD_ftsf231ae_slot0,
+ FIELD_ftsf232ae_slot0,
+ FIELD_ftsf233ae_slot0,
+ FIELD_ftsf234ae_slot0,
+ FIELD_ftsf235ae_slot0,
+ FIELD_ftsf236ae_slot0,
+ FIELD_ftsf237ae_slot0,
+ FIELD_ftsf238ae_slot0,
+ FIELD_ftsf239ae_slot0,
+ FIELD_ftsf240ae_slot0,
+ FIELD_ftsf241ae_slot0,
+ FIELD_ftsf242ae_slot0,
+ FIELD_ftsf243ae_slot0,
+ FIELD_ftsf244ae_slot0,
+ FIELD_ftsf245ae_slot0,
+ FIELD_ftsf246ae_slot0,
+ FIELD_ftsf247ae_slot0,
+ FIELD_ftsf248ae_slot0,
+ FIELD_ftsf249ae_slot0,
+ FIELD_ftsf250ae_slot0,
+ FIELD_ftsf251ae_slot0,
+ FIELD_ftsf252ae_slot0,
+ FIELD_ftsf253ae_slot0,
+ FIELD_ftsf254ae_slot0,
+ FIELD_ftsf255ae_slot0,
+ FIELD_ftsf256ae_slot0,
+ FIELD_ftsf257ae_slot0,
+ FIELD_ftsf258ae_slot0,
+ FIELD_ftsf259ae_slot0,
+ FIELD_ftsf260ae_slot0,
+ FIELD_ftsf261ae_slot0,
+ FIELD_ftsf262ae_slot0,
+ FIELD_ftsf263ae_slot0,
+ FIELD_ftsf264ae_slot0,
+ FIELD_ftsf265ae_slot0,
+ FIELD_ftsf266ae_slot0,
+ FIELD_ftsf267ae_slot0,
+ FIELD_ftsf268ae_slot0,
+ FIELD_ftsf269ae_slot0,
+ FIELD_ftsf270ae_slot0,
+ FIELD_ftsf271ae_slot0,
+ FIELD_ftsf272ae_slot0,
+ FIELD_ftsf273ae_slot0,
+ FIELD_ftsf274ae_slot0,
+ FIELD_ftsf275ae_slot0,
+ FIELD_ftsf276ae_slot0,
+ FIELD_ftsf277ae_slot0,
+ FIELD_ftsf278ae_slot0,
+ FIELD_ftsf279ae_slot0,
+ FIELD_ftsf280,
+ FIELD_ftsf281ae_slot0,
+ FIELD_ftsf282ae_slot0,
+ FIELD_ftsf284ae_slot0,
+ FIELD_ftsf285ae_slot0,
+ FIELD_ftsf287ae_slot0,
+ FIELD_ftsf288,
+ FIELD_ftsf289ae_slot0,
+ FIELD_ftsf290ae_slot0,
+ FIELD_ftsf291ae_slot0,
+ FIELD_ftsf292ae_slot0,
+ FIELD_ftsf293ae_slot0,
+ FIELD_ftsf294ae_slot0,
+ FIELD_ftsf295ae_slot0,
+ FIELD_ftsf296ae_slot0,
+ FIELD_ftsf297ae_slot0,
+ FIELD_ftsf298ae_slot0,
+ FIELD_ftsf300ae_slot0,
+ FIELD_ftsf302ae_slot0,
+ FIELD_ftsf304ae_slot0,
+ FIELD_ftsf305ae_slot0,
+ FIELD_ftsf306ae_slot0,
+ FIELD_ftsf307ae_slot0,
+ FIELD_ftsf308ae_slot0,
+ FIELD_ftsf309,
+ FIELD_ftsf310ae_slot0,
+ FIELD_ftsf311ae_slot0,
+ FIELD_ftsf312ae_slot0,
+ FIELD_ftsf313ae_slot0,
+ FIELD_ftsf314ae_slot0,
+ FIELD_ftsf315,
+ FIELD_ftsf316ae_slot0,
+ FIELD_ftsf317ae_slot0,
+ FIELD_ftsf319ae_slot0,
+ FIELD_ftsf320ae_slot0,
+ FIELD_ftsf322ae_slot0,
+ FIELD_ftsf323ae_slot0,
+ FIELD_ftsf324ae_slot0,
+ FIELD_ftsf325ae_slot0,
+ FIELD_ftsf326ae_slot0,
+ FIELD_ftsf327ae_slot0,
+ FIELD_ftsf328ae_slot0,
+ FIELD_ftsf329ae_slot0,
+ FIELD_ftsf360ae_slot0,
+ FIELD_ftsf361ae_slot0,
+ FIELD_ftsf362,
+ FIELD_ftsf363ae_slot0,
+ FIELD_ftsf364ae_slot0,
+ FIELD_ftsf366ae_slot0,
+ FIELD_ftsf368ae_slot0,
+ FIELD_ftsf370ae_slot0,
+ FIELD_ftsf373ae_slot0,
+ FIELD_ftsf376ae_slot0,
+ FIELD_ftsf378ae_slot0,
+ FIELD_ftsf379ae_slot0,
+ FIELD_ftsf382ae_slot0,
+ FIELD_ftsf383ae_slot0,
+ FIELD_ftsf384ae_slot0,
+ FIELD_ftsf386ae_slot0,
+ FIELD_ftsf387ae_slot0,
+ FIELD_ftsf388ae_slot0,
+ FIELD_ftsf389ae_slot0,
+ FIELD_ae_mul32x24fld,
+ FIELD_op0_s4_s4,
+ FIELD_combined2c0b5f72_fld28,
+ FIELD_combined2c0b5f72_fld37,
+ FIELD_combined2c0b5f72_fld39,
+ FIELD_combined2c0b5f72_fld40,
+ FIELD_combined2c0b5f72_fld46,
+ FIELD_combined2c0b5f72_fld47,
+ FIELD_combined2c0b5f72_fld49,
+ FIELD_combined2c0b5f72_fld50,
+ FIELD_combined2c0b5f72_fld52,
+ FIELD_combined2c0b5f72_fld121,
+ FIELD_combined2c0b5f72_fld123,
+ FIELD_combined2c0b5f72_fld127,
+ FIELD_combined2c0b5f72_fld133ae_slot0,
+ FIELD_combined2c0b5f72_fld134ae_slot0,
+ FIELD_combined2c0b5f72_fld135ae_slot0,
+ FIELD_combined2c0b5f72_fld136ae_slot0,
+ FIELD_combined2c0b5f72_fld137ae_slot0,
+ FIELD_combined2c0b5f72_fld138ae_slot0,
+ FIELD_combined2c0b5f72_fld139ae_slot0,
+ FIELD_combined2c0b5f72_fld140ae_slot0,
+ FIELD_combined2c0b5f72_fld141ae_slot0,
+ FIELD_combined2c0b5f72_fld142ae_slot0,
+ FIELD_combined2c0b5f72_fld143ae_slot0,
+ FIELD_combined2c0b5f72_fld144ae_slot0,
+ FIELD_combined2c0b5f72_fld145ae_slot0,
+ FIELD_combined2c0b5f72_fld146ae_slot0,
+ FIELD_combined2c0b5f72_fld148ae_slot0,
+ FIELD_combined2c0b5f72_fld149ae_slot0,
+ FIELD_op0_s4_s4_s4,
+ FIELD_combined1e9fefee_fld96,
+ FIELD_combined1e9fefee_fld98,
+ FIELD_combined1e9fefee_fld106ae_slot0,
+ FIELD_combined1e9fefee_fld107ae_slot0,
+ FIELD_combined1e9fefee_fld108ae_slot0,
+ FIELD_combined1e9fefee_fld109ae_slot0,
+ FIELD_op0_s3_s3,
+ FIELD_combined2c0b5f72_fld19,
+ FIELD_combined2c0b5f72_fld22,
+ FIELD_combined2c0b5f72_fld24,
+ FIELD_combined2c0b5f72_fld65,
+ FIELD_combined2c0b5f72_fld66,
+ FIELD_combined2c0b5f72_fld68,
+ FIELD_combined2c0b5f72_fld69,
+ FIELD_combined2c0b5f72_fld74,
+ FIELD_combined2c0b5f72_fld79,
+ FIELD_combined2c0b5f72_fld88,
+ FIELD_combined2c0b5f72_fld90,
+ FIELD_combined2c0b5f72_fld91,
+ FIELD_combined2c0b5f72_fld131ae_slot1,
+ FIELD_combined2c0b5f72_fld132ae_slot1,
+ FIELD_combined2c0b5f72_fld147ae_slot1,
+ FIELD_bitindex,
+ FIELD_s3to1,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12,
+ FIELD__mr0,
+ FIELD__mr1,
+ FIELD__mr2,
+ FIELD__mr3,
+ FIELD__bt16,
+ FIELD__bs16,
+ FIELD__br16,
+ FIELD__brall
+};
+
+\f
+/* Functional units. */
+
+static xtensa_funcUnit_internal funcUnits[] = {
+ { "ae_add32", 1 },
+ { "ae_shift32x4", 1 },
+ { "ae_shift32x5", 1 },
+ { "ae_subshift", 1 }
+};
+
+enum xtensa_funcUnit_id {
+ FUNCUNIT_ae_add32,
+ FUNCUNIT_ae_shift32x4,
+ FUNCUNIT_ae_shift32x5,
+ FUNCUNIT_ae_subshift
+};
+
+\f
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR,
+ REGFILE_MR,
+ REGFILE_BR,
+ REGFILE_AE_PR,
+ REGFILE_AE_QR,
+ REGFILE_BR2,
+ REGFILE_BR4,
+ REGFILE_BR8,
+ REGFILE_BR16
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 },
+ { "MR", "m", REGFILE_MR, 32, 4 },
+ { "BR", "b", REGFILE_BR, 1, 16 },
+ { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
+ { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
+ { "BR2", "b", REGFILE_BR, 2, 8 },
+ { "BR4", "b", REGFILE_BR, 4, 4 },
+ { "BR8", "b", REGFILE_BR, 8, 2 },
+ { "BR16", "b", REGFILE_BR, 16, 1 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "ERI_RD_Out", 14, 0, 0, 'o' },
+ { "ERI_RD_In", 32, 0, 1, 'i' },
+ { "ERI_RD_Rdy", 1, 0, 0, 'i' },
+ { "ERI_WR_Out", 46, 0, 2, 'o' },
+ { "ERI_WR_In", 1, 0, 3, 'i' },
+ { "IMPWIRE", 32, 0, 4, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_ERI_RD_Out,
+ INTERFACE_ERI_RD_In,
+ INTERFACE_ERI_RD_Rdy,
+ INTERFACE_ERI_WR_Out,
+ INTERFACE_ERI_WR_In,
+ INTERFACE_IMPWIRE
+};
+
+
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
+{
+ *valp += 2;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
+{
+ int error;
+ error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+ *valp = *valp & 1;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_out_0;
+ unsigned soffsetx4_in_0;
+ soffsetx4_in_0 = *valp & 0x3ffff;
+ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+ unsigned soffsetx4_in_0;
+ unsigned soffsetx4_out_0;
+ soffsetx4_out_0 = *valp;
+ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = soffsetx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_out_0;
+ unsigned uimm12x8_in_0;
+ uimm12x8_in_0 = *valp & 0xfff;
+ uimm12x8_out_0 = uimm12x8_in_0 << 3;
+ *valp = uimm12x8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+ unsigned uimm12x8_in_0;
+ unsigned uimm12x8_out_0;
+ uimm12x8_out_0 = *valp;
+ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+ *valp = uimm12x8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_out_0;
+ unsigned simm4_in_0;
+ simm4_in_0 = *valp & 0xf;
+ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+ *valp = simm4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+ unsigned simm4_in_0;
+ unsigned simm4_out_0;
+ simm4_out_0 = *valp;
+ simm4_in_0 = (simm4_out_0 & 0xf);
+ *valp = simm4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_out_0;
+ unsigned immrx4_in_0;
+ immrx4_in_0 = *valp & 0xf;
+ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+ *valp = immrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+ unsigned immrx4_in_0;
+ unsigned immrx4_out_0;
+ immrx4_out_0 = *valp;
+ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+ *valp = immrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_out_0;
+ unsigned lsi4x4_in_0;
+ lsi4x4_in_0 = *valp & 0xf;
+ lsi4x4_out_0 = lsi4x4_in_0 << 2;
+ *valp = lsi4x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+ unsigned lsi4x4_in_0;
+ unsigned lsi4x4_out_0;
+ lsi4x4_out_0 = *valp;
+ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+ *valp = lsi4x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_out_0;
+ unsigned simm7_in_0;
+ simm7_in_0 = *valp & 0x7f;
+ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+ *valp = simm7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+ unsigned simm7_in_0;
+ unsigned simm7_out_0;
+ simm7_out_0 = *valp;
+ simm7_in_0 = (simm7_out_0 & 0x7f);
+ *valp = simm7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_out_0;
+ unsigned uimm6_in_0;
+ uimm6_in_0 = *valp & 0x3f;
+ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+ *valp = uimm6_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+ unsigned uimm6_in_0;
+ unsigned uimm6_out_0;
+ uimm6_out_0 = *valp;
+ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+ *valp = uimm6_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_out_0;
+ unsigned ai4const_in_0;
+ ai4const_in_0 = *valp & 0xf;
+ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+ *valp = ai4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+ unsigned ai4const_in_0;
+ unsigned ai4const_out_0;
+ ai4const_out_0 = *valp;
+ switch (ai4const_out_0)
+ {
+ case 0xffffffff: ai4const_in_0 = 0; break;
+ case 0x1: ai4const_in_0 = 0x1; break;
+ case 0x2: ai4const_in_0 = 0x2; break;
+ case 0x3: ai4const_in_0 = 0x3; break;
+ case 0x4: ai4const_in_0 = 0x4; break;
+ case 0x5: ai4const_in_0 = 0x5; break;
+ case 0x6: ai4const_in_0 = 0x6; break;
+ case 0x7: ai4const_in_0 = 0x7; break;
+ case 0x8: ai4const_in_0 = 0x8; break;
+ case 0x9: ai4const_in_0 = 0x9; break;
+ case 0xa: ai4const_in_0 = 0xa; break;
+ case 0xb: ai4const_in_0 = 0xb; break;
+ case 0xc: ai4const_in_0 = 0xc; break;
+ case 0xd: ai4const_in_0 = 0xd; break;
+ case 0xe: ai4const_in_0 = 0xe; break;
+ default: ai4const_in_0 = 0xf; break;
+ }
+ *valp = ai4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_out_0;
+ unsigned b4const_in_0;
+ b4const_in_0 = *valp & 0xf;
+ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+ *valp = b4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+ unsigned b4const_in_0;
+ unsigned b4const_out_0;
+ b4const_out_0 = *valp;
+ switch (b4const_out_0)
+ {
+ case 0xffffffff: b4const_in_0 = 0; break;
+ case 0x1: b4const_in_0 = 0x1; break;
+ case 0x2: b4const_in_0 = 0x2; break;
+ case 0x3: b4const_in_0 = 0x3; break;
+ case 0x4: b4const_in_0 = 0x4; break;
+ case 0x5: b4const_in_0 = 0x5; break;
+ case 0x6: b4const_in_0 = 0x6; break;
+ case 0x7: b4const_in_0 = 0x7; break;
+ case 0x8: b4const_in_0 = 0x8; break;
+ case 0xa: b4const_in_0 = 0x9; break;
+ case 0xc: b4const_in_0 = 0xa; break;
+ case 0x10: b4const_in_0 = 0xb; break;
+ case 0x20: b4const_in_0 = 0xc; break;
+ case 0x40: b4const_in_0 = 0xd; break;
+ case 0x80: b4const_in_0 = 0xe; break;
+ default: b4const_in_0 = 0xf; break;
+ }
+ *valp = b4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_out_0;
+ unsigned b4constu_in_0;
+ b4constu_in_0 = *valp & 0xf;
+ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+ *valp = b4constu_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+ unsigned b4constu_in_0;
+ unsigned b4constu_out_0;
+ b4constu_out_0 = *valp;
+ switch (b4constu_out_0)
+ {
+ case 0x8000: b4constu_in_0 = 0; break;
+ case 0x10000: b4constu_in_0 = 0x1; break;
+ case 0x2: b4constu_in_0 = 0x2; break;
+ case 0x3: b4constu_in_0 = 0x3; break;
+ case 0x4: b4constu_in_0 = 0x4; break;
+ case 0x5: b4constu_in_0 = 0x5; break;
+ case 0x6: b4constu_in_0 = 0x6; break;
+ case 0x7: b4constu_in_0 = 0x7; break;
+ case 0x8: b4constu_in_0 = 0x8; break;
+ case 0xa: b4constu_in_0 = 0x9; break;
+ case 0xc: b4constu_in_0 = 0xa; break;
+ case 0x10: b4constu_in_0 = 0xb; break;
+ case 0x20: b4constu_in_0 = 0xc; break;
+ case 0x40: b4constu_in_0 = 0xd; break;
+ case 0x80: b4constu_in_0 = 0xe; break;
+ default: b4constu_in_0 = 0xf; break;
+ }
+ *valp = b4constu_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_out_0;
+ unsigned uimm8_in_0;
+ uimm8_in_0 = *valp & 0xff;
+ uimm8_out_0 = uimm8_in_0;
+ *valp = uimm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+ unsigned uimm8_in_0;
+ unsigned uimm8_out_0;
+ uimm8_out_0 = *valp;
+ uimm8_in_0 = (uimm8_out_0 & 0xff);
+ *valp = uimm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_out_0;
+ unsigned uimm8x2_in_0;
+ uimm8x2_in_0 = *valp & 0xff;
+ uimm8x2_out_0 = uimm8x2_in_0 << 1;
+ *valp = uimm8x2_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+ unsigned uimm8x2_in_0;
+ unsigned uimm8x2_out_0;
+ uimm8x2_out_0 = *valp;
+ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+ *valp = uimm8x2_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_out_0;
+ unsigned uimm8x4_in_0;
+ uimm8x4_in_0 = *valp & 0xff;
+ uimm8x4_out_0 = uimm8x4_in_0 << 2;
+ *valp = uimm8x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+ unsigned uimm8x4_in_0;
+ unsigned uimm8x4_out_0;
+ uimm8x4_out_0 = *valp;
+ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+ *valp = uimm8x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_out_0;
+ unsigned uimm4x16_in_0;
+ uimm4x16_in_0 = *valp & 0xf;
+ uimm4x16_out_0 = uimm4x16_in_0 << 4;
+ *valp = uimm4x16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+ unsigned uimm4x16_in_0;
+ unsigned uimm4x16_out_0;
+ uimm4x16_out_0 = *valp;
+ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+ *valp = uimm4x16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_out_0;
+ unsigned simm8_in_0;
+ simm8_in_0 = *valp & 0xff;
+ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+ *valp = simm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+ unsigned simm8_in_0;
+ unsigned simm8_out_0;
+ simm8_out_0 = *valp;
+ simm8_in_0 = (simm8_out_0 & 0xff);
+ *valp = simm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_out_0;
+ unsigned simm8x256_in_0;
+ simm8x256_in_0 = *valp & 0xff;
+ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+ *valp = simm8x256_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+ unsigned simm8x256_in_0;
+ unsigned simm8x256_out_0;
+ simm8x256_out_0 = *valp;
+ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+ *valp = simm8x256_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_out_0;
+ unsigned simm12b_in_0;
+ simm12b_in_0 = *valp & 0xfff;
+ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+ *valp = simm12b_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+ unsigned simm12b_in_0;
+ unsigned simm12b_out_0;
+ simm12b_out_0 = *valp;
+ simm12b_in_0 = (simm12b_out_0 & 0xfff);
+ *valp = simm12b_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_out_0;
+ unsigned msalp32_in_0;
+ msalp32_in_0 = *valp & 0x1f;
+ msalp32_out_0 = 0x20 - msalp32_in_0;
+ *valp = msalp32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+ unsigned msalp32_in_0;
+ unsigned msalp32_out_0;
+ msalp32_out_0 = *valp;
+ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+ *valp = msalp32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_out_0;
+ unsigned op2p1_in_0;
+ op2p1_in_0 = *valp & 0xf;
+ op2p1_out_0 = op2p1_in_0 + 0x1;
+ *valp = op2p1_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+ unsigned op2p1_in_0;
+ unsigned op2p1_out_0;
+ op2p1_out_0 = *valp;
+ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+ *valp = op2p1_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+ unsigned label8_out_0;
+ unsigned label8_in_0;
+ label8_in_0 = *valp & 0xff;
+ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+ *valp = label8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+ unsigned label8_in_0;
+ unsigned label8_out_0;
+ label8_out_0 = *valp;
+ label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+ *valp = label8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_out_0;
+ unsigned ulabel8_in_0;
+ ulabel8_in_0 = *valp & 0xff;
+ ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+ *valp = ulabel8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+ unsigned ulabel8_in_0;
+ unsigned ulabel8_out_0;
+ ulabel8_out_0 = *valp;
+ ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+ *valp = ulabel8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+ unsigned label12_out_0;
+ unsigned label12_in_0;
+ label12_in_0 = *valp & 0xfff;
+ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+ *valp = label12_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+ unsigned label12_in_0;
+ unsigned label12_out_0;
+ label12_out_0 = *valp;
+ label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+ *valp = label12_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_out_0;
+ unsigned soffset_in_0;
+ soffset_in_0 = *valp & 0x3ffff;
+ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+ *valp = soffset_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+ unsigned soffset_in_0;
+ unsigned soffset_out_0;
+ soffset_out_0 = *valp;
+ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+ *valp = soffset_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_out_0;
+ unsigned uimm16x4_in_0;
+ uimm16x4_in_0 = *valp & 0xffff;
+ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+ *valp = uimm16x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+ unsigned uimm16x4_in_0;
+ unsigned uimm16x4_out_0;
+ uimm16x4_out_0 = *valp;
+ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+ *valp = uimm16x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+ unsigned bbi_out_0;
+ unsigned bbi_in_0;
+ bbi_in_0 = *valp & 0x1f;
+ bbi_out_0 = (0 << 5) | bbi_in_0;
+ *valp = bbi_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+ unsigned bbi_in_0;
+ unsigned bbi_out_0;
+ bbi_out_0 = *valp;
+ bbi_in_0 = (bbi_out_0 & 0x1f);
+ *valp = bbi_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+ unsigned s_out_0;
+ unsigned s_in_0;
+ s_in_0 = *valp & 0xf;
+ s_out_0 = (0 << 4) | s_in_0;
+ *valp = s_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+ unsigned s_in_0;
+ unsigned s_out_0;
+ s_out_0 = *valp;
+ s_in_0 = (s_out_0 & 0xf);
+ *valp = s_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+ unsigned immt_out_0;
+ unsigned immt_in_0;
+ immt_in_0 = *valp & 0xf;
+ immt_out_0 = immt_in_0;
+ *valp = immt_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+ unsigned immt_in_0;
+ unsigned immt_out_0;
+ immt_out_0 = *valp;
+ immt_in_0 = immt_out_0 & 0xf;
+ *valp = immt_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR2_decode (uint32 *valp)
+{
+ *valp = *valp << 1;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 1) != 0);
+ *valp = *valp >> 1;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR4_decode (uint32 *valp)
+{
+ *valp = *valp << 2;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 3) != 0);
+ *valp = *valp >> 2;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR8_decode (uint32 *valp)
+{
+ *valp = *valp << 3;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR8_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 7) != 0);
+ *valp = *valp >> 3;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR16_decode (uint32 *valp)
+{
+ *valp = *valp << 4;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR16_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 15) != 0);
+ *valp = *valp >> 4;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_out_0;
+ unsigned tp7_in_0;
+ tp7_in_0 = *valp & 0xf;
+ tp7_out_0 = tp7_in_0 + 0x7;
+ *valp = tp7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+ unsigned tp7_in_0;
+ unsigned tp7_out_0;
+ tp7_out_0 = *valp;
+ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+ *valp = tp7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_out_0;
+ unsigned xt_wbr15_label_in_0;
+ xt_wbr15_label_in_0 = *valp & 0x7fff;
+ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+ *valp = xt_wbr15_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_in_0;
+ unsigned xt_wbr15_label_out_0;
+ xt_wbr15_label_out_0 = *valp;
+ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
+{
+ unsigned ae_samt32_out_0;
+ unsigned ae_samt32_in_0;
+ ae_samt32_in_0 = *valp & 0x1f;
+ ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
+ *valp = ae_samt32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
+{
+ unsigned ae_samt32_in_0;
+ unsigned ae_samt32_out_0;
+ ae_samt32_out_0 = *valp;
+ ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
+ *valp = ae_samt32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 8);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
+{
+ unsigned ae_lsimm16_out_0;
+ unsigned ae_lsimm16_in_0;
+ ae_lsimm16_in_0 = *valp & 0xf;
+ ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
+ *valp = ae_lsimm16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
+{
+ unsigned ae_lsimm16_in_0;
+ unsigned ae_lsimm16_out_0;
+ ae_lsimm16_out_0 = *valp;
+ ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
+ *valp = ae_lsimm16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
+{
+ unsigned ae_lsimm32_out_0;
+ unsigned ae_lsimm32_in_0;
+ ae_lsimm32_in_0 = *valp & 0xf;
+ ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
+ *valp = ae_lsimm32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
+{
+ unsigned ae_lsimm32_in_0;
+ unsigned ae_lsimm32_out_0;
+ ae_lsimm32_out_0 = *valp;
+ ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
+ *valp = ae_lsimm32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
+{
+ unsigned ae_lsimm64_out_0;
+ unsigned ae_lsimm64_in_0;
+ ae_lsimm64_in_0 = *valp & 0xf;
+ ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
+ *valp = ae_lsimm64_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
+{
+ unsigned ae_lsimm64_in_0;
+ unsigned ae_lsimm64_out_0;
+ ae_lsimm64_out_0 = *valp;
+ ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
+ *valp = ae_lsimm64_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
+{
+ unsigned ae_samt64_out_0;
+ unsigned ae_samt64_in_0;
+ ae_samt64_in_0 = *valp & 0x3f;
+ ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
+ *valp = ae_samt64_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
+{
+ unsigned ae_samt64_in_0;
+ unsigned ae_samt64_out_0;
+ ae_samt64_out_0 = *valp;
+ ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
+ *valp = ae_samt64_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
+{
+ unsigned ae_ohba_out_0;
+ unsigned ae_ohba_in_0;
+ ae_ohba_in_0 = *valp & 0xf;
+ ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
+ *valp = ae_ohba_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
+{
+ unsigned ae_ohba_in_0;
+ unsigned ae_ohba_out_0;
+ ae_ohba_out_0 = *valp;
+ ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
+ *valp = ae_ohba_in_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+ 0, 0 },
+ { "uimmrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "bbi", FIELD_bbi, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sae", FIELD_sae, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sas", FIELD_sas, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "s", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+ 0, 0 },
+ { "mx", FIELD_x, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
+ 0, 0 },
+ { "my", FIELD_y, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+ OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
+ 0, 0 },
+ { "mw", FIELD_w, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
+ 0, 0 },
+ { "mr0", FIELD__mr0, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
+ 0, 0 },
+ { "mr1", FIELD__mr1, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
+ 0, 0 },
+ { "mr2", FIELD__mr2, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
+ 0, 0 },
+ { "mr3", FIELD__mr3, REGFILE_MR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "bt", FIELD_t, REGFILE_BR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+ 0, 0 },
+ { "bs", FIELD_s, REGFILE_BR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+ 0, 0 },
+ { "br", FIELD_r, REGFILE_BR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+ 0, 0 },
+ { "bt2", FIELD_t2, REGFILE_BR, 2,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+ 0, 0 },
+ { "bs2", FIELD_s2, REGFILE_BR, 2,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+ 0, 0 },
+ { "br2", FIELD_r2, REGFILE_BR, 2,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+ 0, 0 },
+ { "bt4", FIELD_t4, REGFILE_BR, 4,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+ 0, 0 },
+ { "bs4", FIELD_s4, REGFILE_BR, 4,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+ 0, 0 },
+ { "br4", FIELD_r4, REGFILE_BR, 4,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+ 0, 0 },
+ { "bt8", FIELD_t8, REGFILE_BR, 8,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+ 0, 0 },
+ { "bs8", FIELD_s8, REGFILE_BR, 8,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+ 0, 0 },
+ { "br8", FIELD_r8, REGFILE_BR, 8,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+ 0, 0 },
+ { "bt16", FIELD__bt16, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "bs16", FIELD__bs16, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "br16", FIELD__br16, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "brall", FIELD__brall, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "ae_samt32", FIELD_ftsf13, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
+ 0, 0 },
+ { "pr0", FIELD_ftsf11, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "qr0", FIELD_ftsf12, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "mac_qr0", FIELD_ftsf12, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "ae_lsimm16", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
+ 0, 0 },
+ { "ae_lsimm32", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
+ 0, 0 },
+ { "ae_lsimm64", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
+ 0, 0 },
+ { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
+ 0, 0 },
+ { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
+ 0, 0 },
+ { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
+ 0, 0 },
+ { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "bitindex", FIELD_bitindex, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
+ { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
+ { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
+ { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
+ { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
+ { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
+ { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
+ { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
+ { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
+ { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
+ { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
+ { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
+ { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
+ { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
+ { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
+ { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf11", FIELD_ftsf11, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf20ae_slot1", FIELD_ftsf20ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
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+ { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf280", FIELD_ftsf280, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf285ae_slot0", FIELD_ftsf285ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf287ae_slot0", FIELD_ftsf287ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf288", FIELD_ftsf288, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf289ae_slot0", FIELD_ftsf289ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf291ae_slot0", FIELD_ftsf291ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf293ae_slot0", FIELD_ftsf293ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf305ae_slot0", FIELD_ftsf305ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf307ae_slot0", FIELD_ftsf307ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf309", FIELD_ftsf309, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf315", FIELD_ftsf315, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf319ae_slot0", FIELD_ftsf319ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf327ae_slot0", FIELD_ftsf327ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf362", FIELD_ftsf362, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf363ae_slot0", FIELD_ftsf363ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf370ae_slot0", FIELD_ftsf370ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf373ae_slot0", FIELD_ftsf373ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf376ae_slot0", FIELD_ftsf376ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf378ae_slot0", FIELD_ftsf378ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf379ae_slot0", FIELD_ftsf379ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf382ae_slot0", FIELD_ftsf382ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf383ae_slot0", FIELD_ftsf383ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf384ae_slot0", FIELD_ftsf384ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf386ae_slot0", FIELD_ftsf386ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf387ae_slot0", FIELD_ftsf387ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf388ae_slot0", FIELD_ftsf388ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf389ae_slot0", FIELD_ftsf389ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld28", FIELD_combined2c0b5f72_fld28, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld37", FIELD_combined2c0b5f72_fld37, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld39", FIELD_combined2c0b5f72_fld39, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld40", FIELD_combined2c0b5f72_fld40, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld46", FIELD_combined2c0b5f72_fld46, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld47", FIELD_combined2c0b5f72_fld47, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld49", FIELD_combined2c0b5f72_fld49, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld50", FIELD_combined2c0b5f72_fld50, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld52", FIELD_combined2c0b5f72_fld52, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld121", FIELD_combined2c0b5f72_fld121, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld123", FIELD_combined2c0b5f72_fld123, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld127", FIELD_combined2c0b5f72_fld127, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld133ae_slot0", FIELD_combined2c0b5f72_fld133ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld134ae_slot0", FIELD_combined2c0b5f72_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld135ae_slot0", FIELD_combined2c0b5f72_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld136ae_slot0", FIELD_combined2c0b5f72_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld137ae_slot0", FIELD_combined2c0b5f72_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld138ae_slot0", FIELD_combined2c0b5f72_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld139ae_slot0", FIELD_combined2c0b5f72_fld139ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld140ae_slot0", FIELD_combined2c0b5f72_fld140ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld141ae_slot0", FIELD_combined2c0b5f72_fld141ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld142ae_slot0", FIELD_combined2c0b5f72_fld142ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld143ae_slot0", FIELD_combined2c0b5f72_fld143ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld144ae_slot0", FIELD_combined2c0b5f72_fld144ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld145ae_slot0", FIELD_combined2c0b5f72_fld145ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld146ae_slot0", FIELD_combined2c0b5f72_fld146ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld148ae_slot0", FIELD_combined2c0b5f72_fld148ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld149ae_slot0", FIELD_combined2c0b5f72_fld149ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0_s4_s4_s4", FIELD_op0_s4_s4_s4, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined1e9fefee_fld96", FIELD_combined1e9fefee_fld96, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined1e9fefee_fld98", FIELD_combined1e9fefee_fld98, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined1e9fefee_fld106ae_slot0", FIELD_combined1e9fefee_fld106ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined1e9fefee_fld107ae_slot0", FIELD_combined1e9fefee_fld107ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined1e9fefee_fld108ae_slot0", FIELD_combined1e9fefee_fld108ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined1e9fefee_fld109ae_slot0", FIELD_combined1e9fefee_fld109ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld19", FIELD_combined2c0b5f72_fld19, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld22", FIELD_combined2c0b5f72_fld22, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld24", FIELD_combined2c0b5f72_fld24, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld65", FIELD_combined2c0b5f72_fld65, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld66", FIELD_combined2c0b5f72_fld66, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld68", FIELD_combined2c0b5f72_fld68, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld69", FIELD_combined2c0b5f72_fld69, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld74", FIELD_combined2c0b5f72_fld74, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld79", FIELD_combined2c0b5f72_fld79, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld88", FIELD_combined2c0b5f72_fld88, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld90", FIELD_combined2c0b5f72_fld90, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld91", FIELD_combined2c0b5f72_fld91, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld131ae_slot1", FIELD_combined2c0b5f72_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld132ae_slot1", FIELD_combined2c0b5f72_fld132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "combined2c0b5f72_fld147ae_slot1", FIELD_combined2c0b5f72_fld147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_uimmrx4,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_ulabel8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_bbi,
+ OPERAND_sae,
+ OPERAND_sas,
+ OPERAND_sargt,
+ OPERAND_s,
+ OPERAND_mx,
+ OPERAND_my,
+ OPERAND_mw,
+ OPERAND_mr0,
+ OPERAND_mr1,
+ OPERAND_mr2,
+ OPERAND_mr3,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_bt,
+ OPERAND_bs,
+ OPERAND_br,
+ OPERAND_bt2,
+ OPERAND_bs2,
+ OPERAND_br2,
+ OPERAND_bt4,
+ OPERAND_bs4,
+ OPERAND_br4,
+ OPERAND_bt8,
+ OPERAND_bs8,
+ OPERAND_br8,
+ OPERAND_bt16,
+ OPERAND_bs16,
+ OPERAND_br16,
+ OPERAND_brall,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_ae_samt32,
+ OPERAND_pr0,
+ OPERAND_qr0,
+ OPERAND_mac_qr0,
+ OPERAND_ae_lsimm16,
+ OPERAND_ae_lsimm32,
+ OPERAND_ae_lsimm64,
+ OPERAND_ae_samt64,
+ OPERAND_ae_ohba,
+ OPERAND_ae_ohba2,
+ OPERAND_pr,
+ OPERAND_cvt_pr,
+ OPERAND_qr0_rw,
+ OPERAND_mac_qr0_rw,
+ OPERAND_qr1_w,
+ OPERAND_mac_qr1_w,
+ OPERAND_ps,
+ OPERAND_alupppb_ps,
+ OPERAND_bitindex,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sal,
+ OPERAND_sas4,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_r3,
+ OPERAND_rbit2,
+ OPERAND_rhi,
+ OPERAND_t3,
+ OPERAND_tbit2,
+ OPERAND_tlo,
+ OPERAND_w,
+ OPERAND_y,
+ OPERAND_x,
+ OPERAND_t2,
+ OPERAND_s2,
+ OPERAND_r2,
+ OPERAND_t4,
+ OPERAND_s4,
+ OPERAND_r4,
+ OPERAND_t8,
+ OPERAND_s8,
+ OPERAND_r8,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_ae_r3,
+ OPERAND_ae_s_non_samt,
+ OPERAND_ae_s3,
+ OPERAND_ae_r32,
+ OPERAND_ae_samt_s_t,
+ OPERAND_ae_r20,
+ OPERAND_ae_r10,
+ OPERAND_ae_s20,
+ OPERAND_ae_fld_ohba,
+ OPERAND_ae_fld_ohba2,
+ OPERAND_op0_s3,
+ OPERAND_ftsf11,
+ OPERAND_ftsf12,
+ OPERAND_ftsf13,
+ OPERAND_ftsf20ae_slot1,
+ OPERAND_ftsf21ae_slot1,
+ OPERAND_ftsf22ae_slot1,
+ OPERAND_ftsf23ae_slot1,
+ OPERAND_ftsf24ae_slot1,
+ OPERAND_ftsf25ae_slot1,
+ OPERAND_ftsf26ae_slot1,
+ OPERAND_ftsf27ae_slot1,
+ OPERAND_ftsf28ae_slot1,
+ OPERAND_ftsf29ae_slot1,
+ OPERAND_ftsf30ae_slot1,
+ OPERAND_ftsf31ae_slot1,
+ OPERAND_ftsf32ae_slot1,
+ OPERAND_ftsf33ae_slot1,
+ OPERAND_ftsf34ae_slot1,
+ OPERAND_ftsf35ae_slot1,
+ OPERAND_ftsf36ae_slot1,
+ OPERAND_ftsf37ae_slot1,
+ OPERAND_ftsf38ae_slot1,
+ OPERAND_ftsf40ae_slot1,
+ OPERAND_ftsf41ae_slot1,
+ OPERAND_ftsf42ae_slot1,
+ OPERAND_ftsf43ae_slot1,
+ OPERAND_ftsf45ae_slot1,
+ OPERAND_ftsf47ae_slot1,
+ OPERAND_ftsf48ae_slot1,
+ OPERAND_ftsf49ae_slot1,
+ OPERAND_ftsf50ae_slot1,
+ OPERAND_ftsf51ae_slot1,
+ OPERAND_ftsf52ae_slot1,
+ OPERAND_ftsf53ae_slot1,
+ OPERAND_ftsf54ae_slot1,
+ OPERAND_ftsf55,
+ OPERAND_ftsf56ae_slot1,
+ OPERAND_ftsf57ae_slot1,
+ OPERAND_ftsf58ae_slot1,
+ OPERAND_ftsf60ae_slot1,
+ OPERAND_ftsf61,
+ OPERAND_ftsf62ae_slot1,
+ OPERAND_ftsf63ae_slot1,
+ OPERAND_ftsf64ae_slot1,
+ OPERAND_ftsf66ae_slot1,
+ OPERAND_ftsf68ae_slot1,
+ OPERAND_ftsf69ae_slot1,
+ OPERAND_ftsf70ae_slot1,
+ OPERAND_ftsf71ae_slot1,
+ OPERAND_ftsf72ae_slot1,
+ OPERAND_ftsf73ae_slot1,
+ OPERAND_ftsf74ae_slot1,
+ OPERAND_ftsf75ae_slot1,
+ OPERAND_ftsf76ae_slot1,
+ OPERAND_ftsf77ae_slot1,
+ OPERAND_ftsf78ae_slot1,
+ OPERAND_ftsf79ae_slot1,
+ OPERAND_ftsf80ae_slot1,
+ OPERAND_ftsf81ae_slot1,
+ OPERAND_ftsf82ae_slot1,
+ OPERAND_ftsf83ae_slot1,
+ OPERAND_ftsf84ae_slot1,
+ OPERAND_ftsf85ae_slot1,
+ OPERAND_ftsf86ae_slot1,
+ OPERAND_ftsf87ae_slot1,
+ OPERAND_ftsf88ae_slot1,
+ OPERAND_ftsf89ae_slot1,
+ OPERAND_ftsf90ae_slot1,
+ OPERAND_ftsf91,
+ OPERAND_ftsf92ae_slot1,
+ OPERAND_ftsf93ae_slot1,
+ OPERAND_ftsf94ae_slot1,
+ OPERAND_ftsf96ae_slot1,
+ OPERAND_ftsf97ae_slot1,
+ OPERAND_ftsf99ae_slot1,
+ OPERAND_ftsf101ae_slot1,
+ OPERAND_ftsf102ae_slot1,
+ OPERAND_ftsf103ae_slot1,
+ OPERAND_ftsf106ae_slot1,
+ OPERAND_ftsf107ae_slot1,
+ OPERAND_ftsf108ae_slot1,
+ OPERAND_ftsf109ae_slot1,
+ OPERAND_ftsf110ae_slot1,
+ OPERAND_ftsf111ae_slot1,
+ OPERAND_ftsf112ae_slot1,
+ OPERAND_ftsf113ae_slot1,
+ OPERAND_ftsf114ae_slot1,
+ OPERAND_ftsf115ae_slot1,
+ OPERAND_ftsf116ae_slot1,
+ OPERAND_ftsf117ae_slot1,
+ OPERAND_ftsf118ae_slot1,
+ OPERAND_ftsf120ae_slot1,
+ OPERAND_ftsf121ae_slot1,
+ OPERAND_ftsf123ae_slot1,
+ OPERAND_ftsf124ae_slot1,
+ OPERAND_ftsf125ae_slot1,
+ OPERAND_ftsf126ae_slot1,
+ OPERAND_ftsf127ae_slot1,
+ OPERAND_ftsf128ae_slot1,
+ OPERAND_ftsf129ae_slot1,
+ OPERAND_ftsf130ae_slot1,
+ OPERAND_ftsf131ae_slot1,
+ OPERAND_ftsf132ae_slot1,
+ OPERAND_ftsf133ae_slot1,
+ OPERAND_ftsf134ae_slot1,
+ OPERAND_ftsf135ae_slot1,
+ OPERAND_ftsf136ae_slot1,
+ OPERAND_ftsf137ae_slot1,
+ OPERAND_ftsf138ae_slot1,
+ OPERAND_ftsf139ae_slot1,
+ OPERAND_ftsf140ae_slot1,
+ OPERAND_ftsf141ae_slot1,
+ OPERAND_ftsf142ae_slot1,
+ OPERAND_ftsf143ae_slot1,
+ OPERAND_ftsf144ae_slot1,
+ OPERAND_ftsf145ae_slot1,
+ OPERAND_ftsf146ae_slot1,
+ OPERAND_ftsf147ae_slot1,
+ OPERAND_ftsf148ae_slot1,
+ OPERAND_ftsf149ae_slot1,
+ OPERAND_ftsf150ae_slot1,
+ OPERAND_ftsf151ae_slot1,
+ OPERAND_ftsf152ae_slot1,
+ OPERAND_ftsf153ae_slot1,
+ OPERAND_ftsf154ae_slot1,
+ OPERAND_ftsf155ae_slot1,
+ OPERAND_ftsf156ae_slot1,
+ OPERAND_ftsf157ae_slot1,
+ OPERAND_ftsf158ae_slot1,
+ OPERAND_ftsf159ae_slot1,
+ OPERAND_ftsf160ae_slot1,
+ OPERAND_ftsf161ae_slot1,
+ OPERAND_ftsf162ae_slot1,
+ OPERAND_ftsf163ae_slot1,
+ OPERAND_ftsf164ae_slot1,
+ OPERAND_ftsf165ae_slot1,
+ OPERAND_ftsf166ae_slot1,
+ OPERAND_ftsf167ae_slot1,
+ OPERAND_ftsf168ae_slot1,
+ OPERAND_ftsf169ae_slot1,
+ OPERAND_ftsf170ae_slot1,
+ OPERAND_ftsf171ae_slot1,
+ OPERAND_ftsf172ae_slot1,
+ OPERAND_ftsf173ae_slot1,
+ OPERAND_ftsf174ae_slot1,
+ OPERAND_ftsf175ae_slot1,
+ OPERAND_ftsf176ae_slot1,
+ OPERAND_ftsf177ae_slot1,
+ OPERAND_ftsf178ae_slot1,
+ OPERAND_ftsf179ae_slot1,
+ OPERAND_ftsf180ae_slot1,
+ OPERAND_ftsf181ae_slot1,
+ OPERAND_ftsf182ae_slot1,
+ OPERAND_ftsf183ae_slot1,
+ OPERAND_ftsf184ae_slot1,
+ OPERAND_ftsf185ae_slot1,
+ OPERAND_ftsf186ae_slot1,
+ OPERAND_ftsf187ae_slot1,
+ OPERAND_ftsf188ae_slot1,
+ OPERAND_ftsf189ae_slot1,
+ OPERAND_ftsf190ae_slot1,
+ OPERAND_ftsf191ae_slot1,
+ OPERAND_ftsf192ae_slot1,
+ OPERAND_ftsf193ae_slot1,
+ OPERAND_ftsf194ae_slot1,
+ OPERAND_ftsf195ae_slot1,
+ OPERAND_ftsf196ae_slot1,
+ OPERAND_ftsf197ae_slot1,
+ OPERAND_ftsf198ae_slot1,
+ OPERAND_ftsf199ae_slot1,
+ OPERAND_ftsf200ae_slot1,
+ OPERAND_ftsf201ae_slot1,
+ OPERAND_ftsf202ae_slot1,
+ OPERAND_ftsf203ae_slot1,
+ OPERAND_ftsf204ae_slot1,
+ OPERAND_ftsf205ae_slot1,
+ OPERAND_ftsf206ae_slot1,
+ OPERAND_ftsf207ae_slot1,
+ OPERAND_ftsf208ae_slot1,
+ OPERAND_ftsf210ae_slot1,
+ OPERAND_ftsf333ae_slot1,
+ OPERAND_ftsf334ae_slot1,
+ OPERAND_ftsf335,
+ OPERAND_ftsf336ae_slot1,
+ OPERAND_ftsf337ae_slot1,
+ OPERAND_ftsf339ae_slot1,
+ OPERAND_ftsf340ae_slot1,
+ OPERAND_ftsf341ae_slot1,
+ OPERAND_ftsf342ae_slot1,
+ OPERAND_ftsf343ae_slot1,
+ OPERAND_ftsf344ae_slot1,
+ OPERAND_ftsf345ae_slot1,
+ OPERAND_ftsf347ae_slot1,
+ OPERAND_ftsf348ae_slot1,
+ OPERAND_ftsf349ae_slot1,
+ OPERAND_ftsf350ae_slot1,
+ OPERAND_ftsf351,
+ OPERAND_ftsf352ae_slot1,
+ OPERAND_ftsf354ae_slot1,
+ OPERAND_ftsf355ae_slot1,
+ OPERAND_ftsf356ae_slot1,
+ OPERAND_ftsf357ae_slot1,
+ OPERAND_ftsf358ae_slot1,
+ OPERAND_ftsf359ae_slot1,
+ OPERAND_op0_s4,
+ OPERAND_ftsf211ae_slot0,
+ OPERAND_ftsf212ae_slot0,
+ OPERAND_ftsf213ae_slot0,
+ OPERAND_ftsf214ae_slot0,
+ OPERAND_ftsf215ae_slot0,
+ OPERAND_ftsf217ae_slot0,
+ OPERAND_ftsf218ae_slot0,
+ OPERAND_ftsf219ae_slot0,
+ OPERAND_ftsf220ae_slot0,
+ OPERAND_ftsf221ae_slot0,
+ OPERAND_ftsf222ae_slot0,
+ OPERAND_ftsf223ae_slot0,
+ OPERAND_ftsf224ae_slot0,
+ OPERAND_ftsf225ae_slot0,
+ OPERAND_ftsf226ae_slot0,
+ OPERAND_ftsf227ae_slot0,
+ OPERAND_ftsf228ae_slot0,
+ OPERAND_ftsf229ae_slot0,
+ OPERAND_ftsf230ae_slot0,
+ OPERAND_ftsf231ae_slot0,
+ OPERAND_ftsf232ae_slot0,
+ OPERAND_ftsf233ae_slot0,
+ OPERAND_ftsf234ae_slot0,
+ OPERAND_ftsf235ae_slot0,
+ OPERAND_ftsf236ae_slot0,
+ OPERAND_ftsf237ae_slot0,
+ OPERAND_ftsf238ae_slot0,
+ OPERAND_ftsf239ae_slot0,
+ OPERAND_ftsf240ae_slot0,
+ OPERAND_ftsf241ae_slot0,
+ OPERAND_ftsf242ae_slot0,
+ OPERAND_ftsf243ae_slot0,
+ OPERAND_ftsf244ae_slot0,
+ OPERAND_ftsf245ae_slot0,
+ OPERAND_ftsf246ae_slot0,
+ OPERAND_ftsf247ae_slot0,
+ OPERAND_ftsf248ae_slot0,
+ OPERAND_ftsf249ae_slot0,
+ OPERAND_ftsf250ae_slot0,
+ OPERAND_ftsf251ae_slot0,
+ OPERAND_ftsf252ae_slot0,
+ OPERAND_ftsf253ae_slot0,
+ OPERAND_ftsf254ae_slot0,
+ OPERAND_ftsf255ae_slot0,
+ OPERAND_ftsf256ae_slot0,
+ OPERAND_ftsf257ae_slot0,
+ OPERAND_ftsf258ae_slot0,
+ OPERAND_ftsf259ae_slot0,
+ OPERAND_ftsf260ae_slot0,
+ OPERAND_ftsf261ae_slot0,
+ OPERAND_ftsf262ae_slot0,
+ OPERAND_ftsf263ae_slot0,
+ OPERAND_ftsf264ae_slot0,
+ OPERAND_ftsf265ae_slot0,
+ OPERAND_ftsf266ae_slot0,
+ OPERAND_ftsf267ae_slot0,
+ OPERAND_ftsf268ae_slot0,
+ OPERAND_ftsf269ae_slot0,
+ OPERAND_ftsf270ae_slot0,
+ OPERAND_ftsf271ae_slot0,
+ OPERAND_ftsf272ae_slot0,
+ OPERAND_ftsf273ae_slot0,
+ OPERAND_ftsf274ae_slot0,
+ OPERAND_ftsf275ae_slot0,
+ OPERAND_ftsf276ae_slot0,
+ OPERAND_ftsf277ae_slot0,
+ OPERAND_ftsf278ae_slot0,
+ OPERAND_ftsf279ae_slot0,
+ OPERAND_ftsf280,
+ OPERAND_ftsf281ae_slot0,
+ OPERAND_ftsf282ae_slot0,
+ OPERAND_ftsf284ae_slot0,
+ OPERAND_ftsf285ae_slot0,
+ OPERAND_ftsf287ae_slot0,
+ OPERAND_ftsf288,
+ OPERAND_ftsf289ae_slot0,
+ OPERAND_ftsf290ae_slot0,
+ OPERAND_ftsf291ae_slot0,
+ OPERAND_ftsf292ae_slot0,
+ OPERAND_ftsf293ae_slot0,
+ OPERAND_ftsf294ae_slot0,
+ OPERAND_ftsf295ae_slot0,
+ OPERAND_ftsf296ae_slot0,
+ OPERAND_ftsf297ae_slot0,
+ OPERAND_ftsf298ae_slot0,
+ OPERAND_ftsf300ae_slot0,
+ OPERAND_ftsf302ae_slot0,
+ OPERAND_ftsf304ae_slot0,
+ OPERAND_ftsf305ae_slot0,
+ OPERAND_ftsf306ae_slot0,
+ OPERAND_ftsf307ae_slot0,
+ OPERAND_ftsf308ae_slot0,
+ OPERAND_ftsf309,
+ OPERAND_ftsf310ae_slot0,
+ OPERAND_ftsf311ae_slot0,
+ OPERAND_ftsf312ae_slot0,
+ OPERAND_ftsf313ae_slot0,
+ OPERAND_ftsf314ae_slot0,
+ OPERAND_ftsf315,
+ OPERAND_ftsf316ae_slot0,
+ OPERAND_ftsf317ae_slot0,
+ OPERAND_ftsf319ae_slot0,
+ OPERAND_ftsf320ae_slot0,
+ OPERAND_ftsf322ae_slot0,
+ OPERAND_ftsf323ae_slot0,
+ OPERAND_ftsf324ae_slot0,
+ OPERAND_ftsf325ae_slot0,
+ OPERAND_ftsf326ae_slot0,
+ OPERAND_ftsf327ae_slot0,
+ OPERAND_ftsf328ae_slot0,
+ OPERAND_ftsf329ae_slot0,
+ OPERAND_ftsf360ae_slot0,
+ OPERAND_ftsf361ae_slot0,
+ OPERAND_ftsf362,
+ OPERAND_ftsf363ae_slot0,
+ OPERAND_ftsf364ae_slot0,
+ OPERAND_ftsf366ae_slot0,
+ OPERAND_ftsf368ae_slot0,
+ OPERAND_ftsf370ae_slot0,
+ OPERAND_ftsf373ae_slot0,
+ OPERAND_ftsf376ae_slot0,
+ OPERAND_ftsf378ae_slot0,
+ OPERAND_ftsf379ae_slot0,
+ OPERAND_ftsf382ae_slot0,
+ OPERAND_ftsf383ae_slot0,
+ OPERAND_ftsf384ae_slot0,
+ OPERAND_ftsf386ae_slot0,
+ OPERAND_ftsf387ae_slot0,
+ OPERAND_ftsf388ae_slot0,
+ OPERAND_ftsf389ae_slot0,
+ OPERAND_ae_mul32x24fld,
+ OPERAND_op0_s4_s4,
+ OPERAND_combined2c0b5f72_fld28,
+ OPERAND_combined2c0b5f72_fld37,
+ OPERAND_combined2c0b5f72_fld39,
+ OPERAND_combined2c0b5f72_fld40,
+ OPERAND_combined2c0b5f72_fld46,
+ OPERAND_combined2c0b5f72_fld47,
+ OPERAND_combined2c0b5f72_fld49,
+ OPERAND_combined2c0b5f72_fld50,
+ OPERAND_combined2c0b5f72_fld52,
+ OPERAND_combined2c0b5f72_fld121,
+ OPERAND_combined2c0b5f72_fld123,
+ OPERAND_combined2c0b5f72_fld127,
+ OPERAND_combined2c0b5f72_fld133ae_slot0,
+ OPERAND_combined2c0b5f72_fld134ae_slot0,
+ OPERAND_combined2c0b5f72_fld135ae_slot0,
+ OPERAND_combined2c0b5f72_fld136ae_slot0,
+ OPERAND_combined2c0b5f72_fld137ae_slot0,
+ OPERAND_combined2c0b5f72_fld138ae_slot0,
+ OPERAND_combined2c0b5f72_fld139ae_slot0,
+ OPERAND_combined2c0b5f72_fld140ae_slot0,
+ OPERAND_combined2c0b5f72_fld141ae_slot0,
+ OPERAND_combined2c0b5f72_fld142ae_slot0,
+ OPERAND_combined2c0b5f72_fld143ae_slot0,
+ OPERAND_combined2c0b5f72_fld144ae_slot0,
+ OPERAND_combined2c0b5f72_fld145ae_slot0,
+ OPERAND_combined2c0b5f72_fld146ae_slot0,
+ OPERAND_combined2c0b5f72_fld148ae_slot0,
+ OPERAND_combined2c0b5f72_fld149ae_slot0,
+ OPERAND_op0_s4_s4_s4,
+ OPERAND_combined1e9fefee_fld96,
+ OPERAND_combined1e9fefee_fld98,
+ OPERAND_combined1e9fefee_fld106ae_slot0,
+ OPERAND_combined1e9fefee_fld107ae_slot0,
+ OPERAND_combined1e9fefee_fld108ae_slot0,
+ OPERAND_combined1e9fefee_fld109ae_slot0,
+ OPERAND_op0_s3_s3,
+ OPERAND_combined2c0b5f72_fld19,
+ OPERAND_combined2c0b5f72_fld22,
+ OPERAND_combined2c0b5f72_fld24,
+ OPERAND_combined2c0b5f72_fld65,
+ OPERAND_combined2c0b5f72_fld66,
+ OPERAND_combined2c0b5f72_fld68,
+ OPERAND_combined2c0b5f72_fld69,
+ OPERAND_combined2c0b5f72_fld74,
+ OPERAND_combined2c0b5f72_fld79,
+ OPERAND_combined2c0b5f72_fld88,
+ OPERAND_combined2c0b5f72_fld90,
+ OPERAND_combined2c0b5f72_fld91,
+ OPERAND_combined2c0b5f72_fld131ae_slot1,
+ OPERAND_combined2c0b5f72_fld132ae_slot1,
+ OPERAND_combined2c0b5f72_fld147ae_slot1,
+ OPERAND_s3to1
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_243_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32h_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+ { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_mx }, 'i' },
+ { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+ { { OPERAND_mw }, 'o' },
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_mr3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_mr3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_mr3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+ { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPC3 }, 'i' },
+ { { STATE_EPC4 }, 'i' },
+ { { STATE_EPC5 }, 'i' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_EPC7 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_EPS3 }, 'i' },
+ { { STATE_EPS4 }, 'i' },
+ { { STATE_EPS5 }, 'i' },
+ { { STATE_EPS6 }, 'i' },
+ { { STATE_EPS7 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC0 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKA1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DBREAKC1 }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_InOCDMode }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC6 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_bs }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_bs4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_bs8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
+ { { OPERAND_bs }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_brall }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_brall }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_brall }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE2 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = {
+ { { STATE_PREFCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = {
+ { { STATE_PREFCTL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = {
+ { { STATE_PREFCTL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'm' },
+ { { STATE_EXCVADDR }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'i' },
+ { { STATE_ASID2 }, 'i' },
+ { { STATE_ASID1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'o' },
+ { { STATE_ASID2 }, 'o' },
+ { { STATE_ASID1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'm' },
+ { { STATE_ASID2 }, 'm' },
+ { { STATE_ASID1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID6 }, 'i' },
+ { { STATE_INSTPGSZID5 }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID6 }, 'o' },
+ { { STATE_INSTPGSZID5 }, 'o' },
+ { { STATE_INSTPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID6 }, 'm' },
+ { { STATE_INSTPGSZID5 }, 'm' },
+ { { STATE_INSTPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID6 }, 'i' },
+ { { STATE_DATAPGSZID5 }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID6 }, 'o' },
+ { { STATE_DATAPGSZID5 }, 'o' },
+ { { STATE_DATAPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID6 }, 'm' },
+ { { STATE_DATAPGSZID5 }, 'm' },
+ { { STATE_DATAPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_ERI_RAW_INTERLOCK }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+ INTERFACE_ERI_RD_In,
+ INTERFACE_ERI_RD_Out
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_ERI_RAW_INTERLOCK }, 'o' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
+ INTERFACE_ERI_WR_In,
+ INTERFACE_ERI_WR_Out
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'i' },
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'o' },
+ { { STATE_AE_SAR }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
+ { { STATE_AE_BITHEAD }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_TABLESIZE }, 'i' },
+ { { STATE_AE_FIRST_TS }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'o' },
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_TABLESIZE }, 'o' },
+ { { STATE_AE_FIRST_TS }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'i' },
+ { { STATE_AE_SEARCHDONE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
+ { { STATE_AE_SAR }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
+ { { STATE_AE_FIRST_TS }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
+ { { STATE_AE_FIRST_TS }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
+ { { STATE_AE_SEARCHDONE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
+ { { OPERAND_ps }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
+ { { OPERAND_qr1_w }, 'm' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
+ { { OPERAND_qr1_w }, 'm' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_cvt_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_cvt_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
+ { { OPERAND_alupppb_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
+ { { OPERAND_alupppb_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
+ { { OPERAND_bt2 }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
+ { { OPERAND_bt2 }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
+ { { OPERAND_bt2 }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bt }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bt }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'm' },
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'm' },
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'm' },
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'm' },
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'm' },
+ { { STATE_AE_TABLESIZE }, 'm' },
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_AE_FIRST_TS }, 'i' },
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_SEARCHDONE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_AE_FIRST_TS }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_AE_TABLESIZE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ae_ohba2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_ohba2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_ohba }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ae_ohba }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_NEXTOFFSET }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = {
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = {
+ { { STATE_AE_CEND0 }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = {
+ { { STATE_AE_CBEGIN0 }, 'i' },
+ { { STATE_AE_CEND0 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+ INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+ { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+ { { STATE_EXPSTATE }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_threadptr_args,
+ 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_threadptr_args,
+ 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32nb_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_memctl_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid0_args,
+ 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_configid0_args,
+ 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid1_args,
+ 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_243_args,
+ 2, Iclass_xt_iclass_rsr_243_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32h_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_aa_args,
+ 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_ad_args,
+ 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_da_args,
+ 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_dd_args,
+ 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_aa_args,
+ 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_ad_args,
+ 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_da_args,
+ 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_dd_args,
+ 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_da_args,
+ 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_dd_args,
+ 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_l_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m3_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acclo_args,
+ 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acclo_args,
+ 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acclo_args,
+ 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acchi_args,
+ 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acchi_args,
+ 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acchi_args,
+ 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_lddr32_p_args,
+ 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sddr32_p_args,
+ 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_bbool1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbool4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbool8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbranch_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bmove_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_RSR_BR_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_WSR_BR_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_XSR_BR_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_lock_args,
+ 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_dcache_dyn_args,
+ 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_lock_args,
+ 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prefctl_args,
+ 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_prefctl_args,
+ 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_prefctl_args,
+ 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
+ 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_rasid_args,
+ 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_rasid_args,
+ 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_rasid_args,
+ 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
+ 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
+ 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
+ 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
+ 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
+ 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
+ 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_ldpte */,
+ 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwitlba */,
+ 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwdtlba */,
+ 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_cpenable_args,
+ 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_cpenable_args,
+ 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_cpenable_args,
+ 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rer_args,
+ 3, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+ { 2, Iclass_xt_iclass_wer_args,
+ 3, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
+ { 1, Iclass_rur_ae_ovf_sar_args,
+ 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_ovf_sar_args,
+ 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_bithead_args,
+ 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_bithead_args,
+ 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_ts_fts_bu_bp_args,
+ 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_ts_fts_bu_bp_args,
+ 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_sd_no_args,
+ 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_sd_no_args,
+ 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_overflow_args,
+ 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_overflow_args,
+ 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_sar_args,
+ 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_sar_args,
+ 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_bitptr_args,
+ 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_bitptr_args,
+ 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_bitsused_args,
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+ { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_sha32_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_ae_iclass_vldl32t_args,
+ 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_vldl16t_args,
+ 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_vldl16c_args,
+ 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_vldsht_args,
+ 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_lb_args,
+ 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_lbi_args,
+ 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lbk_args,
+ 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lbki_args,
+ 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_db_args,
+ 3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_dbi_args,
+ 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_vlel32t_args,
+ 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_vlel16t_args,
+ 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_sb_args,
+ 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sbi_args,
+ 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_vles16c_args,
+ 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_sbf_args,
+ 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SLAASQ56S_args,
+ 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_ADDBRBA32_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_icls_AE_MINABSSP24S_args,
+ 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_MAXABSSP24S_args,
+ 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_MINABSSQ56S_args,
+ 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_MAXABSSQ56S_args,
+ 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_cbegin0_args,
+ 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_cbegin0_args,
+ 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_cend0_args,
+ 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_cend0_args,
+ 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LP24X2_C_args,
+ 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SP24X2S_C_args,
+ 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LP24X2F_C_args,
+ 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SP24X2F_C_args,
+ 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LP16X2F_C_args,
+ 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SP16X2F_C_args,
+ 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LP24_C_args,
+ 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SP24S_L_C_args,
+ 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LP24F_C_args,
+ 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SP24F_L_C_args,
+ 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LP16F_C_args,
+ 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SP16F_L_C_args,
+ 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LQ56_C_args,
+ 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SQ56S_C_args,
+ 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_LQ32F_C_args,
+ 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 },
+ { 3, Iclass_icls_AE_SQ32F_C_args,
+ 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 },
+ { 1, Iclass_rur_expstate_args,
+ 2, Iclass_rur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_wur_expstate_args,
+ 2, Iclass_wur_expstate_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_READ_IMPWIRE_args,
+ 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+ { 1, Iclass_iclass_SETB_EXPSTATE_args,
+ 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+ { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+ 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+ { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+ 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_rur_threadptr,
+ ICLASS_wur_threadptr,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_loop,
+ ICLASS_xt_iclass_loopz,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s32nb,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_lend,
+ ICLASS_xt_iclass_wsr_lend,
+ ICLASS_xt_iclass_xsr_lend,
+ ICLASS_xt_iclass_rsr_lcount,
+ ICLASS_xt_iclass_wsr_lcount,
+ ICLASS_xt_iclass_xsr_lcount,
+ ICLASS_xt_iclass_rsr_lbeg,
+ ICLASS_xt_iclass_wsr_lbeg,
+ ICLASS_xt_iclass_xsr_lbeg,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_memctl,
+ ICLASS_xt_iclass_wsr_memctl,
+ ICLASS_xt_iclass_xsr_memctl,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_configid0,
+ ICLASS_xt_iclass_wsr_configid0,
+ ICLASS_xt_iclass_rsr_configid1,
+ ICLASS_xt_iclass_rsr_243,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_epc3,
+ ICLASS_xt_iclass_wsr_epc3,
+ ICLASS_xt_iclass_xsr_epc3,
+ ICLASS_xt_iclass_rsr_excsave3,
+ ICLASS_xt_iclass_wsr_excsave3,
+ ICLASS_xt_iclass_xsr_excsave3,
+ ICLASS_xt_iclass_rsr_epc4,
+ ICLASS_xt_iclass_wsr_epc4,
+ ICLASS_xt_iclass_xsr_epc4,
+ ICLASS_xt_iclass_rsr_excsave4,
+ ICLASS_xt_iclass_wsr_excsave4,
+ ICLASS_xt_iclass_xsr_excsave4,
+ ICLASS_xt_iclass_rsr_epc5,
+ ICLASS_xt_iclass_wsr_epc5,
+ ICLASS_xt_iclass_xsr_epc5,
+ ICLASS_xt_iclass_rsr_excsave5,
+ ICLASS_xt_iclass_wsr_excsave5,
+ ICLASS_xt_iclass_xsr_excsave5,
+ ICLASS_xt_iclass_rsr_epc6,
+ ICLASS_xt_iclass_wsr_epc6,
+ ICLASS_xt_iclass_xsr_epc6,
+ ICLASS_xt_iclass_rsr_excsave6,
+ ICLASS_xt_iclass_wsr_excsave6,
+ ICLASS_xt_iclass_xsr_excsave6,
+ ICLASS_xt_iclass_rsr_epc7,
+ ICLASS_xt_iclass_wsr_epc7,
+ ICLASS_xt_iclass_xsr_epc7,
+ ICLASS_xt_iclass_rsr_excsave7,
+ ICLASS_xt_iclass_wsr_excsave7,
+ ICLASS_xt_iclass_xsr_excsave7,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_eps3,
+ ICLASS_xt_iclass_wsr_eps3,
+ ICLASS_xt_iclass_xsr_eps3,
+ ICLASS_xt_iclass_rsr_eps4,
+ ICLASS_xt_iclass_wsr_eps4,
+ ICLASS_xt_iclass_xsr_eps4,
+ ICLASS_xt_iclass_rsr_eps5,
+ ICLASS_xt_iclass_wsr_eps5,
+ ICLASS_xt_iclass_xsr_eps5,
+ ICLASS_xt_iclass_rsr_eps6,
+ ICLASS_xt_iclass_wsr_eps6,
+ ICLASS_xt_iclass_xsr_eps6,
+ ICLASS_xt_iclass_rsr_eps7,
+ ICLASS_xt_iclass_wsr_eps7,
+ ICLASS_xt_iclass_xsr_eps7,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_mul32h,
+ ICLASS_xt_iclass_mac16_aa,
+ ICLASS_xt_iclass_mac16_ad,
+ ICLASS_xt_iclass_mac16_da,
+ ICLASS_xt_iclass_mac16_dd,
+ ICLASS_xt_iclass_mac16a_aa,
+ ICLASS_xt_iclass_mac16a_ad,
+ ICLASS_xt_iclass_mac16a_da,
+ ICLASS_xt_iclass_mac16a_dd,
+ ICLASS_xt_iclass_mac16al_da,
+ ICLASS_xt_iclass_mac16al_dd,
+ ICLASS_xt_iclass_mac16_l,
+ ICLASS_xt_iclass_rsr_m0,
+ ICLASS_xt_iclass_wsr_m0,
+ ICLASS_xt_iclass_xsr_m0,
+ ICLASS_xt_iclass_rsr_m1,
+ ICLASS_xt_iclass_wsr_m1,
+ ICLASS_xt_iclass_xsr_m1,
+ ICLASS_xt_iclass_rsr_m2,
+ ICLASS_xt_iclass_wsr_m2,
+ ICLASS_xt_iclass_xsr_m2,
+ ICLASS_xt_iclass_rsr_m3,
+ ICLASS_xt_iclass_wsr_m3,
+ ICLASS_xt_iclass_xsr_m3,
+ ICLASS_xt_iclass_rsr_acclo,
+ ICLASS_xt_iclass_wsr_acclo,
+ ICLASS_xt_iclass_xsr_acclo,
+ ICLASS_xt_iclass_rsr_acchi,
+ ICLASS_xt_iclass_wsr_acchi,
+ ICLASS_xt_iclass_xsr_acchi,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_dbreaka0,
+ ICLASS_xt_iclass_wsr_dbreaka0,
+ ICLASS_xt_iclass_xsr_dbreaka0,
+ ICLASS_xt_iclass_rsr_dbreakc0,
+ ICLASS_xt_iclass_wsr_dbreakc0,
+ ICLASS_xt_iclass_xsr_dbreakc0,
+ ICLASS_xt_iclass_rsr_dbreaka1,
+ ICLASS_xt_iclass_wsr_dbreaka1,
+ ICLASS_xt_iclass_xsr_dbreaka1,
+ ICLASS_xt_iclass_rsr_dbreakc1,
+ ICLASS_xt_iclass_wsr_dbreakc1,
+ ICLASS_xt_iclass_xsr_dbreakc1,
+ ICLASS_xt_iclass_rsr_ibreaka0,
+ ICLASS_xt_iclass_wsr_ibreaka0,
+ ICLASS_xt_iclass_xsr_ibreaka0,
+ ICLASS_xt_iclass_rsr_ibreaka1,
+ ICLASS_xt_iclass_wsr_ibreaka1,
+ ICLASS_xt_iclass_xsr_ibreaka1,
+ ICLASS_xt_iclass_rsr_ibreakenable,
+ ICLASS_xt_iclass_wsr_ibreakenable,
+ ICLASS_xt_iclass_xsr_ibreakenable,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_lddr32_p,
+ ICLASS_xt_iclass_sddr32_p,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_wsr_mmid,
+ ICLASS_xt_iclass_bbool1,
+ ICLASS_xt_iclass_bbool4,
+ ICLASS_xt_iclass_bbool8,
+ ICLASS_xt_iclass_bbranch,
+ ICLASS_xt_iclass_bmove,
+ ICLASS_xt_iclass_RSR_BR,
+ ICLASS_xt_iclass_WSR_BR,
+ ICLASS_xt_iclass_XSR_BR,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_rsr_ccompare2,
+ ICLASS_xt_iclass_wsr_ccompare2,
+ ICLASS_xt_iclass_xsr_ccompare2,
+ ICLASS_xt_iclass_icache,
+ ICLASS_xt_iclass_icache_lock,
+ ICLASS_xt_iclass_icache_inv,
+ ICLASS_xt_iclass_licx,
+ ICLASS_xt_iclass_sicx,
+ ICLASS_xt_iclass_dcache,
+ ICLASS_xt_iclass_dcache_dyn,
+ ICLASS_xt_iclass_dcache_ind,
+ ICLASS_xt_iclass_dcache_inv,
+ ICLASS_xt_iclass_dpf,
+ ICLASS_xt_iclass_dcache_lock,
+ ICLASS_xt_iclass_sdct,
+ ICLASS_xt_iclass_ldct,
+ ICLASS_xt_iclass_rsr_prefctl,
+ ICLASS_xt_iclass_wsr_prefctl,
+ ICLASS_xt_iclass_xsr_prefctl,
+ ICLASS_xt_iclass_wsr_ptevaddr,
+ ICLASS_xt_iclass_rsr_ptevaddr,
+ ICLASS_xt_iclass_xsr_ptevaddr,
+ ICLASS_xt_iclass_rsr_rasid,
+ ICLASS_xt_iclass_wsr_rasid,
+ ICLASS_xt_iclass_xsr_rasid,
+ ICLASS_xt_iclass_rsr_itlbcfg,
+ ICLASS_xt_iclass_wsr_itlbcfg,
+ ICLASS_xt_iclass_xsr_itlbcfg,
+ ICLASS_xt_iclass_rsr_dtlbcfg,
+ ICLASS_xt_iclass_wsr_dtlbcfg,
+ ICLASS_xt_iclass_xsr_dtlbcfg,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_ldpte,
+ ICLASS_xt_iclass_hwwitlba,
+ ICLASS_xt_iclass_hwwdtlba,
+ ICLASS_xt_iclass_rsr_cpenable,
+ ICLASS_xt_iclass_wsr_cpenable,
+ ICLASS_xt_iclass_xsr_cpenable,
+ ICLASS_xt_iclass_clamp,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_div,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_ae_ovf_sar,
+ ICLASS_wur_ae_ovf_sar,
+ ICLASS_rur_ae_bithead,
+ ICLASS_wur_ae_bithead,
+ ICLASS_rur_ae_ts_fts_bu_bp,
+ ICLASS_wur_ae_ts_fts_bu_bp,
+ ICLASS_rur_ae_sd_no,
+ ICLASS_wur_ae_sd_no,
+ ICLASS_ae_iclass_rur_ae_overflow,
+ ICLASS_ae_iclass_wur_ae_overflow,
+ ICLASS_ae_iclass_rur_ae_sar,
+ ICLASS_ae_iclass_wur_ae_sar,
+ ICLASS_ae_iclass_rur_ae_bitptr,
+ ICLASS_ae_iclass_wur_ae_bitptr,
+ ICLASS_ae_iclass_rur_ae_bitsused,
+ ICLASS_ae_iclass_wur_ae_bitsused,
+ ICLASS_ae_iclass_rur_ae_tablesize,
+ ICLASS_ae_iclass_wur_ae_tablesize,
+ ICLASS_ae_iclass_rur_ae_first_ts,
+ ICLASS_ae_iclass_wur_ae_first_ts,
+ ICLASS_ae_iclass_rur_ae_nextoffset,
+ ICLASS_ae_iclass_wur_ae_nextoffset,
+ ICLASS_ae_iclass_rur_ae_searchdone,
+ ICLASS_ae_iclass_wur_ae_searchdone,
+ ICLASS_ae_iclass_lp16f_i,
+ ICLASS_ae_iclass_lp16f_iu,
+ ICLASS_ae_iclass_lp16f_x,
+ ICLASS_ae_iclass_lp16f_xu,
+ ICLASS_ae_iclass_lp24_i,
+ ICLASS_ae_iclass_lp24_iu,
+ ICLASS_ae_iclass_lp24_x,
+ ICLASS_ae_iclass_lp24_xu,
+ ICLASS_ae_iclass_lp24f_i,
+ ICLASS_ae_iclass_lp24f_iu,
+ ICLASS_ae_iclass_lp24f_x,
+ ICLASS_ae_iclass_lp24f_xu,
+ ICLASS_ae_iclass_lp16x2f_i,
+ ICLASS_ae_iclass_lp16x2f_iu,
+ ICLASS_ae_iclass_lp16x2f_x,
+ ICLASS_ae_iclass_lp16x2f_xu,
+ ICLASS_ae_iclass_lp24x2f_i,
+ ICLASS_ae_iclass_lp24x2f_iu,
+ ICLASS_ae_iclass_lp24x2f_x,
+ ICLASS_ae_iclass_lp24x2f_xu,
+ ICLASS_ae_iclass_lp24x2_i,
+ ICLASS_ae_iclass_lp24x2_iu,
+ ICLASS_ae_iclass_lp24x2_x,
+ ICLASS_ae_iclass_lp24x2_xu,
+ ICLASS_ae_iclass_sp16x2f_i,
+ ICLASS_ae_iclass_sp16x2f_iu,
+ ICLASS_ae_iclass_sp16x2f_x,
+ ICLASS_ae_iclass_sp16x2f_xu,
+ ICLASS_ae_iclass_sp24x2s_i,
+ ICLASS_ae_iclass_sp24x2s_iu,
+ ICLASS_ae_iclass_sp24x2s_x,
+ ICLASS_ae_iclass_sp24x2s_xu,
+ ICLASS_ae_iclass_sp24x2f_i,
+ ICLASS_ae_iclass_sp24x2f_iu,
+ ICLASS_ae_iclass_sp24x2f_x,
+ ICLASS_ae_iclass_sp24x2f_xu,
+ ICLASS_ae_iclass_sp16f_l_i,
+ ICLASS_ae_iclass_sp16f_l_iu,
+ ICLASS_ae_iclass_sp16f_l_x,
+ ICLASS_ae_iclass_sp16f_l_xu,
+ ICLASS_ae_iclass_sp24s_l_i,
+ ICLASS_ae_iclass_sp24s_l_iu,
+ ICLASS_ae_iclass_sp24s_l_x,
+ ICLASS_ae_iclass_sp24s_l_xu,
+ ICLASS_ae_iclass_sp24f_l_i,
+ ICLASS_ae_iclass_sp24f_l_iu,
+ ICLASS_ae_iclass_sp24f_l_x,
+ ICLASS_ae_iclass_sp24f_l_xu,
+ ICLASS_ae_iclass_lq56_i,
+ ICLASS_ae_iclass_lq56_iu,
+ ICLASS_ae_iclass_lq56_x,
+ ICLASS_ae_iclass_lq56_xu,
+ ICLASS_ae_iclass_lq32f_i,
+ ICLASS_ae_iclass_lq32f_iu,
+ ICLASS_ae_iclass_lq32f_x,
+ ICLASS_ae_iclass_lq32f_xu,
+ ICLASS_ae_iclass_sq56s_i,
+ ICLASS_ae_iclass_sq56s_iu,
+ ICLASS_ae_iclass_sq56s_x,
+ ICLASS_ae_iclass_sq56s_xu,
+ ICLASS_ae_iclass_sq32f_i,
+ ICLASS_ae_iclass_sq32f_iu,
+ ICLASS_ae_iclass_sq32f_x,
+ ICLASS_ae_iclass_sq32f_xu,
+ ICLASS_ae_iclass_zerop48,
+ ICLASS_ae_iclass_movp48,
+ ICLASS_ae_iclass_selp24_ll,
+ ICLASS_ae_iclass_selp24_lh,
+ ICLASS_ae_iclass_selp24_hl,
+ ICLASS_ae_iclass_selp24_hh,
+ ICLASS_ae_iclass_movtp24x2,
+ ICLASS_ae_iclass_movfp24x2,
+ ICLASS_ae_iclass_movtp48,
+ ICLASS_ae_iclass_movfp48,
+ ICLASS_ae_iclass_movpa24x2,
+ ICLASS_ae_iclass_truncp24a32x2,
+ ICLASS_ae_iclass_cvta32p24_l,
+ ICLASS_ae_iclass_cvta32p24_h,
+ ICLASS_ae_iclass_cvtp24a16x2_ll,
+ ICLASS_ae_iclass_cvtp24a16x2_lh,
+ ICLASS_ae_iclass_cvtp24a16x2_hl,
+ ICLASS_ae_iclass_cvtp24a16x2_hh,
+ ICLASS_ae_iclass_truncp24q48x2,
+ ICLASS_ae_iclass_truncp16,
+ ICLASS_ae_iclass_roundsp24q48sym,
+ ICLASS_ae_iclass_roundsp24q48asym,
+ ICLASS_ae_iclass_roundsp16q48sym,
+ ICLASS_ae_iclass_roundsp16q48asym,
+ ICLASS_ae_iclass_roundsp16sym,
+ ICLASS_ae_iclass_roundsp16asym,
+ ICLASS_ae_iclass_zeroq56,
+ ICLASS_ae_iclass_movq56,
+ ICLASS_ae_iclass_movtq56,
+ ICLASS_ae_iclass_movfq56,
+ ICLASS_ae_iclass_cvtq48a32s,
+ ICLASS_ae_iclass_cvtq48p24s_l,
+ ICLASS_ae_iclass_cvtq48p24s_h,
+ ICLASS_ae_iclass_satq48s,
+ ICLASS_ae_iclass_truncq32,
+ ICLASS_ae_iclass_roundsq32sym,
+ ICLASS_ae_iclass_roundsq32asym,
+ ICLASS_ae_iclass_trunca32q48,
+ ICLASS_ae_iclass_movap24s_l,
+ ICLASS_ae_iclass_movap24s_h,
+ ICLASS_ae_iclass_trunca16p24s_l,
+ ICLASS_ae_iclass_trunca16p24s_h,
+ ICLASS_ae_iclass_addp24,
+ ICLASS_ae_iclass_subp24,
+ ICLASS_ae_iclass_negp24,
+ ICLASS_ae_iclass_absp24,
+ ICLASS_ae_iclass_maxp24s,
+ ICLASS_ae_iclass_minp24s,
+ ICLASS_ae_iclass_maxbp24s,
+ ICLASS_ae_iclass_minbp24s,
+ ICLASS_ae_iclass_addsp24s,
+ ICLASS_ae_iclass_subsp24s,
+ ICLASS_ae_iclass_negsp24s,
+ ICLASS_ae_iclass_abssp24s,
+ ICLASS_ae_iclass_andp48,
+ ICLASS_ae_iclass_nandp48,
+ ICLASS_ae_iclass_orp48,
+ ICLASS_ae_iclass_xorp48,
+ ICLASS_ae_iclass_ltp24s,
+ ICLASS_ae_iclass_lep24s,
+ ICLASS_ae_iclass_eqp24,
+ ICLASS_ae_iclass_addq56,
+ ICLASS_ae_iclass_subq56,
+ ICLASS_ae_iclass_negq56,
+ ICLASS_ae_iclass_absq56,
+ ICLASS_ae_iclass_maxq56s,
+ ICLASS_ae_iclass_minq56s,
+ ICLASS_ae_iclass_maxbq56s,
+ ICLASS_ae_iclass_minbq56s,
+ ICLASS_ae_iclass_addsq56s,
+ ICLASS_ae_iclass_subsq56s,
+ ICLASS_ae_iclass_negsq56s,
+ ICLASS_ae_iclass_abssq56s,
+ ICLASS_ae_iclass_andq56,
+ ICLASS_ae_iclass_nandq56,
+ ICLASS_ae_iclass_orq56,
+ ICLASS_ae_iclass_xorq56,
+ ICLASS_ae_iclass_sllip24,
+ ICLASS_ae_iclass_srlip24,
+ ICLASS_ae_iclass_sraip24,
+ ICLASS_ae_iclass_sllsp24,
+ ICLASS_ae_iclass_srlsp24,
+ ICLASS_ae_iclass_srasp24,
+ ICLASS_ae_iclass_sllisp24s,
+ ICLASS_ae_iclass_sllssp24s,
+ ICLASS_ae_iclass_slliq56,
+ ICLASS_ae_iclass_srliq56,
+ ICLASS_ae_iclass_sraiq56,
+ ICLASS_ae_iclass_sllsq56,
+ ICLASS_ae_iclass_srlsq56,
+ ICLASS_ae_iclass_srasq56,
+ ICLASS_ae_iclass_sllaq56,
+ ICLASS_ae_iclass_srlaq56,
+ ICLASS_ae_iclass_sraaq56,
+ ICLASS_ae_iclass_sllisq56s,
+ ICLASS_ae_iclass_sllssq56s,
+ ICLASS_ae_iclass_sllasq56s,
+ ICLASS_ae_iclass_ltq56s,
+ ICLASS_ae_iclass_leq56s,
+ ICLASS_ae_iclass_eqq56,
+ ICLASS_ae_iclass_nsaq56s,
+ ICLASS_ae_iclass_mulsrfq32sp24s_h,
+ ICLASS_ae_iclass_mulsrfq32sp24s_l,
+ ICLASS_ae_iclass_mularfq32sp24s_h,
+ ICLASS_ae_iclass_mularfq32sp24s_l,
+ ICLASS_ae_iclass_mulrfq32sp24s_h,
+ ICLASS_ae_iclass_mulrfq32sp24s_l,
+ ICLASS_ae_iclass_mulsfq32sp24s_h,
+ ICLASS_ae_iclass_mulsfq32sp24s_l,
+ ICLASS_ae_iclass_mulafq32sp24s_h,
+ ICLASS_ae_iclass_mulafq32sp24s_l,
+ ICLASS_ae_iclass_mulfq32sp24s_h,
+ ICLASS_ae_iclass_mulfq32sp24s_l,
+ ICLASS_ae_iclass_mulfs32p16s_ll,
+ ICLASS_ae_iclass_mulfp24s_ll,
+ ICLASS_ae_iclass_mulp24s_ll,
+ ICLASS_ae_iclass_mulfs32p16s_lh,
+ ICLASS_ae_iclass_mulfp24s_lh,
+ ICLASS_ae_iclass_mulp24s_lh,
+ ICLASS_ae_iclass_mulfs32p16s_hl,
+ ICLASS_ae_iclass_mulfp24s_hl,
+ ICLASS_ae_iclass_mulp24s_hl,
+ ICLASS_ae_iclass_mulfs32p16s_hh,
+ ICLASS_ae_iclass_mulfp24s_hh,
+ ICLASS_ae_iclass_mulp24s_hh,
+ ICLASS_ae_iclass_mulafs32p16s_ll,
+ ICLASS_ae_iclass_mulafp24s_ll,
+ ICLASS_ae_iclass_mulap24s_ll,
+ ICLASS_ae_iclass_mulafs32p16s_lh,
+ ICLASS_ae_iclass_mulafp24s_lh,
+ ICLASS_ae_iclass_mulap24s_lh,
+ ICLASS_ae_iclass_mulafs32p16s_hl,
+ ICLASS_ae_iclass_mulafp24s_hl,
+ ICLASS_ae_iclass_mulap24s_hl,
+ ICLASS_ae_iclass_mulafs32p16s_hh,
+ ICLASS_ae_iclass_mulafp24s_hh,
+ ICLASS_ae_iclass_mulap24s_hh,
+ ICLASS_ae_iclass_mulsfs32p16s_ll,
+ ICLASS_ae_iclass_mulsfp24s_ll,
+ ICLASS_ae_iclass_mulsp24s_ll,
+ ICLASS_ae_iclass_mulsfs32p16s_lh,
+ ICLASS_ae_iclass_mulsfp24s_lh,
+ ICLASS_ae_iclass_mulsp24s_lh,
+ ICLASS_ae_iclass_mulsfs32p16s_hl,
+ ICLASS_ae_iclass_mulsfp24s_hl,
+ ICLASS_ae_iclass_mulsp24s_hl,
+ ICLASS_ae_iclass_mulsfs32p16s_hh,
+ ICLASS_ae_iclass_mulsfp24s_hh,
+ ICLASS_ae_iclass_mulsp24s_hh,
+ ICLASS_ae_iclass_mulafs56p24s_ll,
+ ICLASS_ae_iclass_mulas56p24s_ll,
+ ICLASS_ae_iclass_mulafs56p24s_lh,
+ ICLASS_ae_iclass_mulas56p24s_lh,
+ ICLASS_ae_iclass_mulafs56p24s_hl,
+ ICLASS_ae_iclass_mulas56p24s_hl,
+ ICLASS_ae_iclass_mulafs56p24s_hh,
+ ICLASS_ae_iclass_mulas56p24s_hh,
+ ICLASS_ae_iclass_mulsfs56p24s_ll,
+ ICLASS_ae_iclass_mulss56p24s_ll,
+ ICLASS_ae_iclass_mulsfs56p24s_lh,
+ ICLASS_ae_iclass_mulss56p24s_lh,
+ ICLASS_ae_iclass_mulsfs56p24s_hl,
+ ICLASS_ae_iclass_mulss56p24s_hl,
+ ICLASS_ae_iclass_mulsfs56p24s_hh,
+ ICLASS_ae_iclass_mulss56p24s_hh,
+ ICLASS_ae_iclass_mulfq32sp16s_l,
+ ICLASS_ae_iclass_mulfq32sp16s_h,
+ ICLASS_ae_iclass_mulfq32sp16u_l,
+ ICLASS_ae_iclass_mulfq32sp16u_h,
+ ICLASS_ae_iclass_mulq32sp16s_l,
+ ICLASS_ae_iclass_mulq32sp16s_h,
+ ICLASS_ae_iclass_mulq32sp16u_l,
+ ICLASS_ae_iclass_mulq32sp16u_h,
+ ICLASS_ae_iclass_mulafq32sp16s_l,
+ ICLASS_ae_iclass_mulafq32sp16s_h,
+ ICLASS_ae_iclass_mulafq32sp16u_l,
+ ICLASS_ae_iclass_mulafq32sp16u_h,
+ ICLASS_ae_iclass_mulaq32sp16s_l,
+ ICLASS_ae_iclass_mulaq32sp16s_h,
+ ICLASS_ae_iclass_mulaq32sp16u_l,
+ ICLASS_ae_iclass_mulaq32sp16u_h,
+ ICLASS_ae_iclass_mulsfq32sp16s_l,
+ ICLASS_ae_iclass_mulsfq32sp16s_h,
+ ICLASS_ae_iclass_mulsfq32sp16u_l,
+ ICLASS_ae_iclass_mulsfq32sp16u_h,
+ ICLASS_ae_iclass_mulsq32sp16s_l,
+ ICLASS_ae_iclass_mulsq32sp16s_h,
+ ICLASS_ae_iclass_mulsq32sp16u_l,
+ ICLASS_ae_iclass_mulsq32sp16u_h,
+ ICLASS_ae_iclass_mulzaaq32sp16s_ll,
+ ICLASS_ae_iclass_mulzaafq32sp16s_ll,
+ ICLASS_ae_iclass_mulzaaq32sp16u_ll,
+ ICLASS_ae_iclass_mulzaafq32sp16u_ll,
+ ICLASS_ae_iclass_mulzaaq32sp16s_hh,
+ ICLASS_ae_iclass_mulzaafq32sp16s_hh,
+ ICLASS_ae_iclass_mulzaaq32sp16u_hh,
+ ICLASS_ae_iclass_mulzaafq32sp16u_hh,
+ ICLASS_ae_iclass_mulzaaq32sp16s_lh,
+ ICLASS_ae_iclass_mulzaafq32sp16s_lh,
+ ICLASS_ae_iclass_mulzaaq32sp16u_lh,
+ ICLASS_ae_iclass_mulzaafq32sp16u_lh,
+ ICLASS_ae_iclass_mulzasq32sp16s_ll,
+ ICLASS_ae_iclass_mulzasfq32sp16s_ll,
+ ICLASS_ae_iclass_mulzasq32sp16u_ll,
+ ICLASS_ae_iclass_mulzasfq32sp16u_ll,
+ ICLASS_ae_iclass_mulzasq32sp16s_hh,
+ ICLASS_ae_iclass_mulzasfq32sp16s_hh,
+ ICLASS_ae_iclass_mulzasq32sp16u_hh,
+ ICLASS_ae_iclass_mulzasfq32sp16u_hh,
+ ICLASS_ae_iclass_mulzasq32sp16s_lh,
+ ICLASS_ae_iclass_mulzasfq32sp16s_lh,
+ ICLASS_ae_iclass_mulzasq32sp16u_lh,
+ ICLASS_ae_iclass_mulzasfq32sp16u_lh,
+ ICLASS_ae_iclass_mulzsaq32sp16s_ll,
+ ICLASS_ae_iclass_mulzsafq32sp16s_ll,
+ ICLASS_ae_iclass_mulzsaq32sp16u_ll,
+ ICLASS_ae_iclass_mulzsafq32sp16u_ll,
+ ICLASS_ae_iclass_mulzsaq32sp16s_hh,
+ ICLASS_ae_iclass_mulzsafq32sp16s_hh,
+ ICLASS_ae_iclass_mulzsaq32sp16u_hh,
+ ICLASS_ae_iclass_mulzsafq32sp16u_hh,
+ ICLASS_ae_iclass_mulzsaq32sp16s_lh,
+ ICLASS_ae_iclass_mulzsafq32sp16s_lh,
+ ICLASS_ae_iclass_mulzsaq32sp16u_lh,
+ ICLASS_ae_iclass_mulzsafq32sp16u_lh,
+ ICLASS_ae_iclass_mulzssq32sp16s_ll,
+ ICLASS_ae_iclass_mulzssfq32sp16s_ll,
+ ICLASS_ae_iclass_mulzssq32sp16u_ll,
+ ICLASS_ae_iclass_mulzssfq32sp16u_ll,
+ ICLASS_ae_iclass_mulzssq32sp16s_hh,
+ ICLASS_ae_iclass_mulzssfq32sp16s_hh,
+ ICLASS_ae_iclass_mulzssq32sp16u_hh,
+ ICLASS_ae_iclass_mulzssfq32sp16u_hh,
+ ICLASS_ae_iclass_mulzssq32sp16s_lh,
+ ICLASS_ae_iclass_mulzssfq32sp16s_lh,
+ ICLASS_ae_iclass_mulzssq32sp16u_lh,
+ ICLASS_ae_iclass_mulzssfq32sp16u_lh,
+ ICLASS_ae_iclass_mulzaafp24s_hh_ll,
+ ICLASS_ae_iclass_mulzaap24s_hh_ll,
+ ICLASS_ae_iclass_mulzaafp24s_hl_lh,
+ ICLASS_ae_iclass_mulzaap24s_hl_lh,
+ ICLASS_ae_iclass_mulzasfp24s_hh_ll,
+ ICLASS_ae_iclass_mulzasp24s_hh_ll,
+ ICLASS_ae_iclass_mulzasfp24s_hl_lh,
+ ICLASS_ae_iclass_mulzasp24s_hl_lh,
+ ICLASS_ae_iclass_mulzsafp24s_hh_ll,
+ ICLASS_ae_iclass_mulzsap24s_hh_ll,
+ ICLASS_ae_iclass_mulzsafp24s_hl_lh,
+ ICLASS_ae_iclass_mulzsap24s_hl_lh,
+ ICLASS_ae_iclass_mulzssfp24s_hh_ll,
+ ICLASS_ae_iclass_mulzssp24s_hh_ll,
+ ICLASS_ae_iclass_mulzssfp24s_hl_lh,
+ ICLASS_ae_iclass_mulzssp24s_hl_lh,
+ ICLASS_ae_iclass_mulaafp24s_hh_ll,
+ ICLASS_ae_iclass_mulaap24s_hh_ll,
+ ICLASS_ae_iclass_mulaafp24s_hl_lh,
+ ICLASS_ae_iclass_mulaap24s_hl_lh,
+ ICLASS_ae_iclass_mulasfp24s_hh_ll,
+ ICLASS_ae_iclass_mulasp24s_hh_ll,
+ ICLASS_ae_iclass_mulasfp24s_hl_lh,
+ ICLASS_ae_iclass_mulasp24s_hl_lh,
+ ICLASS_ae_iclass_mulsafp24s_hh_ll,
+ ICLASS_ae_iclass_mulsap24s_hh_ll,
+ ICLASS_ae_iclass_mulsafp24s_hl_lh,
+ ICLASS_ae_iclass_mulsap24s_hl_lh,
+ ICLASS_ae_iclass_mulssfp24s_hh_ll,
+ ICLASS_ae_iclass_mulssp24s_hh_ll,
+ ICLASS_ae_iclass_mulssfp24s_hl_lh,
+ ICLASS_ae_iclass_mulssp24s_hl_lh,
+ ICLASS_ae_iclass_sha32,
+ ICLASS_ae_iclass_vldl32t,
+ ICLASS_ae_iclass_vldl16t,
+ ICLASS_ae_iclass_vldl16c,
+ ICLASS_ae_iclass_vldsht,
+ ICLASS_ae_iclass_lb,
+ ICLASS_ae_iclass_lbi,
+ ICLASS_ae_iclass_lbk,
+ ICLASS_ae_iclass_lbki,
+ ICLASS_ae_iclass_db,
+ ICLASS_ae_iclass_dbi,
+ ICLASS_ae_iclass_vlel32t,
+ ICLASS_ae_iclass_vlel16t,
+ ICLASS_ae_iclass_sb,
+ ICLASS_ae_iclass_sbi,
+ ICLASS_ae_iclass_vles16c,
+ ICLASS_ae_iclass_sbf,
+ ICLASS_icls_AE_SLAASQ56S,
+ ICLASS_icls_AE_ADDBRBA32,
+ ICLASS_icls_AE_MINABSSP24S,
+ ICLASS_icls_AE_MAXABSSP24S,
+ ICLASS_icls_AE_MINABSSQ56S,
+ ICLASS_icls_AE_MAXABSSQ56S,
+ ICLASS_rur_ae_cbegin0,
+ ICLASS_wur_ae_cbegin0,
+ ICLASS_rur_ae_cend0,
+ ICLASS_wur_ae_cend0,
+ ICLASS_icls_AE_LP24X2_C,
+ ICLASS_icls_AE_SP24X2S_C,
+ ICLASS_icls_AE_LP24X2F_C,
+ ICLASS_icls_AE_SP24X2F_C,
+ ICLASS_icls_AE_LP16X2F_C,
+ ICLASS_icls_AE_SP16X2F_C,
+ ICLASS_icls_AE_LP24_C,
+ ICLASS_icls_AE_SP24S_L_C,
+ ICLASS_icls_AE_LP24F_C,
+ ICLASS_icls_AE_SP24F_L_C,
+ ICLASS_icls_AE_LP16F_C,
+ ICLASS_icls_AE_SP16F_L_C,
+ ICLASS_icls_AE_LQ56_C,
+ ICLASS_icls_AE_SQ56S_C,
+ ICLASS_icls_AE_LQ32F_C,
+ ICLASS_icls_AE_SQ32F_C,
+ ICLASS_rur_expstate,
+ ICLASS_wur_expstate,
+ ICLASS_iclass_READ_IMPWIRE,
+ ICLASS_iclass_SETB_EXPSTATE,
+ ICLASS_iclass_CLRB_EXPSTATE,
+ ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80200;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2300;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c0000;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580000;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x540000;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0000;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0000;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70000;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0000;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x804;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10f;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4300;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5300;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x94;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4830;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4831;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4816;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4930;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4931;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4916;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc800;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc00;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd60f;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd000;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc000;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd30f;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00f;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7e03e;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe73f;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200c00;
+}
+
+static void
+Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200d00;
+}
+
+static void
+Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb81;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1381;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2381;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b81;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4d01;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe;
+}
+
+static void
+Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf81;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf;
+}
+
+static void
+Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4d81;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b81;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2501;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4f01;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680000;
+}
+
+static void
+Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690000;
+}
+
+static void
+Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1800003;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0000;
+}
+
+static void
+Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800003;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0000;
+}
+
+static void
+Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000003;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700600;
+}
+
+static void
+Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700e00;
+}
+
+static void
+Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80002;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0000;
+}
+
+static void
+Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000003;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0000;
+}
+
+static void
+Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000003;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700100;
+}
+
+static void
+Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300002;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700900;
+}
+
+static void
+Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700a00;
+}
+
+static void
+Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600002;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700200;
+}
+
+static void
+Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680002;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700b00;
+}
+
+static void
+Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380002;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700300;
+}
+
+static void
+Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700002;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700800;
+}
+
+static void
+Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500002;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700000;
+}
+
+static void
+Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700400;
+}
+
+static void
+Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180002;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700c00;
+}
+
+static void
+Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780002;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700500;
+}
+
+static void
+Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580002;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700d00;
+}
+
+static void
+Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280002;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640000;
+}
+
+static void
+Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x101;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650000;
+}
+
+static void
+Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x181;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670000;
+}
+
+static void
+Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x281;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660000;
+}
+
+static void
+Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x681;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500000;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40;
+}
+
+static void
+Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x983d01;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200100;
+}
+
+static void
+Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200004;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200900;
+}
+
+static void
+Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100004;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200200;
+}
+
+static void
+Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400004;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0800;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0900;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0a00;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200a00;
+}
+
+static void
+Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x301;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38;
+}
+
+static void
+Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7381;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39;
+}
+
+static void
+Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd01;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a;
+}
+
+static void
+Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x701;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b;
+}
+
+static void
+Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x581;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed81;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1006;
+}
+
+static void
+Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ed81;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0200;
+}
+
+static void
+Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36001;
+}
+
+static void
+Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb83d01;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1500;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200500;
+}
+
+static void
+Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200600;
+}
+
+static void
+Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300004;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x95;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200400;
+}
+
+static void
+Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4;
+}
+
+static void
+Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x983d81;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x104;
+}
+
+static void
+Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4183d01;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x204;
+}
+
+static void
+Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2183d01;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x304;
+}
+
+static void
+Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1183d01;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404;
+}
+
+static void
+Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18e501;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a;
+}
+
+static void
+Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2806f81;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18;
+}
+
+static void
+Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4781;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x19;
+}
+
+static void
+Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7ed81;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b;
+}
+
+static void
+Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5ed81;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10;
+}
+
+static void
+Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x501;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x12;
+}
+
+static void
+Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x381;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x14;
+}
+
+static void
+Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd81;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0200;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0200;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10200;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20200;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x116;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x231;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x216;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x331;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x316;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6130;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6131;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6116;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x531;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x516;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb030;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb031;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd030;
+}
+
+static void
+Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf330;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe630;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe631;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe616;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb130;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb131;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb116;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd130;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd131;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd116;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb230;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb231;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb216;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd230;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd231;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd216;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb330;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb331;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb316;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd330;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd331;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd316;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb430;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb431;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb416;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd430;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd431;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd416;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb530;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb531;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb516;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd530;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd531;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd516;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb630;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb631;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb616;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd630;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd631;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd616;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb730;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb731;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb716;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd730;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd731;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd716;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc230;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc231;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc216;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc330;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc331;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc316;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc430;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc431;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc416;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc530;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc531;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc516;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc630;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc631;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc616;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc730;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc731;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc716;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xee30;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xee31;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xee16;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc030;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc031;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc016;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe830;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe831;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe816;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf430;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf431;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf416;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf530;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf531;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf516;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xeb30;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe730;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe731;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe716;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x28;
+}
+
+static void
+Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a;
+}
+
+static void
+Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400047;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400057;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400067;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400077;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400007;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400017;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400027;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400037;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400043;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400053;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400063;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400073;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400046;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400056;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400066;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400076;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400042;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400052;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400062;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400072;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400087;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400097;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a7;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b7;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000c7;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000d7;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000e7;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000f7;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400083;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400093;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a3;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b3;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000c3;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000d3;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000e3;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000f3;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400086;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400096;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a6;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b6;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000c6;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000d6;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000e6;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000f6;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400082;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400092;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a2;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b2;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000c2;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000d2;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000e2;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000f2;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400085;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400084;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400095;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400094;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a5;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a4;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b5;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b4;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400081;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400080;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400091;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400090;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a1;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a0;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b1;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b0;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400009;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400008;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2031;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2016;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2130;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2131;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2116;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2230;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2231;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2216;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2330;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2331;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2316;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1030;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1031;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1016;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1130;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1131;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1116;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10300;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe230;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe231;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe331;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe430;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe431;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe416;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20f;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9030;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9031;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9016;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa030;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa031;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa016;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9130;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9131;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9116;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa130;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa131;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa116;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8030;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8031;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8016;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8130;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8131;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8116;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6030;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6031;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6016;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe930;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe931;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe916;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xec30;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xec31;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xec16;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed30;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed31;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed16;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6830;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6831;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6816;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0700;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0700;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe1f;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10e1f;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5931;
+}
+
+static void
+Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20;
+}
+
+static void
+Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5381;
+}
+
+static void
+Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x21;
+}
+
+static void
+Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b81;
+}
+
+static void
+Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x22;
+}
+
+static void
+Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4581;
+}
+
+static void
+Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x23;
+}
+
+static void
+Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x781;
+}
+
+static void
+Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x24;
+}
+
+static void
+Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4f81;
+}
+
+static void
+Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800;
+}
+
+static void
+Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96501;
+}
+
+static void
+Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900;
+}
+
+static void
+Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8e501;
+}
+
+static void
+Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00;
+}
+
+static void
+Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc6501;
+}
+
+static void
+Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00;
+}
+
+static void
+Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6501;
+}
+
+static void
+Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0000;
+}
+
+static void
+Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2800003;
+}
+
+static void
+Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0100;
+}
+
+static void
+Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000003;
+}
+
+static void
+Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c;
+}
+
+static void
+Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b81;
+}
+
+static void
+Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d;
+}
+
+static void
+Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1501;
+}
+
+static void
+Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430;
+}
+
+static void
+Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x431;
+}
+
+static void
+Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x416;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea30;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea31;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea16;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf030;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf031;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf016;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf130;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf131;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf116;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf230;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf231;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf216;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0700;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0700;
+}
+
+static void
+Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0700;
+}
+
+static void
+Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0720;
+}
+
+static void
+Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0730;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0700;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x21f;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x11f;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31f;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240700;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250700;
+}
+
+static void
+Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2807f0;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280740;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280750;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260700;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270700;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200700;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210700;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x220700;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230700;
+}
+
+static void
+Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280700;
+}
+
+static void
+Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280720;
+}
+
+static void
+Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280730;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x91f;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81f;
+}
+
+static void
+Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2830;
+}
+
+static void
+Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2831;
+}
+
+static void
+Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2816;
+}
+
+static void
+Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5331;
+}
+
+static void
+Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5330;
+}
+
+static void
+Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5316;
+}
+
+static void
+Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a30;
+}
+
+static void
+Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a31;
+}
+
+static void
+Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a16;
+}
+
+static void
+Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b30;
+}
+
+static void
+Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b31;
+}
+
+static void
+Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b16;
+}
+
+static void
+Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c30;
+}
+
+static void
+Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c31;
+}
+
+static void
+Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5c16;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc05;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd05;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb05;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf05;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe05;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x405;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x305;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x705;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x605;
+}
+
+static void
+Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1f;
+}
+
+static void
+Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x105;
+}
+
+static void
+Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x905;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe030;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe031;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe016;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x33;
+}
+
+static void
+Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b81;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34;
+}
+
+static void
+Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b81;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3381;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b81;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x37;
+}
+
+static void
+Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6381;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe04;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf04;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32;
+}
+
+static void
+Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4701;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200b00;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200f00;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200e00;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc30;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc31;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc16;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6330;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6331;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6316;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x604;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x704;
+}
+
+static void
+Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03e;
+}
+
+static void
+Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03f;
+}
+
+static void
+Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f03e;
+}
+
+static void
+Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13f;
+}
+
+static void
+Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f03e;
+}
+
+static void
+Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf23f;
+}
+
+static void
+Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f03e;
+}
+
+static void
+Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf33f;
+}
+
+static void
+Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40809c;
+}
+
+static void
+Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000ac;
+}
+
+static void
+Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40909c;
+}
+
+static void
+Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4001ac;
+}
+
+static void
+Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40a09c;
+}
+
+static void
+Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002ac;
+}
+
+static void
+Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40b09c;
+}
+
+static void
+Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4003ac;
+}
+
+static void
+Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40c09c;
+}
+
+static void
+Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4004ac;
+}
+
+static void
+Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40d09c;
+}
+
+static void
+Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4005ac;
+}
+
+static void
+Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e09c;
+}
+
+static void
+Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4006ac;
+}
+
+static void
+Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f09c;
+}
+
+static void
+Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007ac;
+}
+
+static void
+Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81581;
+}
+
+static void
+Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40005a;
+}
+
+static void
+Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1781;
+}
+
+static void
+Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40009a;
+}
+
+static void
+Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81701;
+}
+
+static void
+Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000ca;
+}
+
+static void
+Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81781;
+}
+
+static void
+Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000fa;
+}
+
+static void
+Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81d81;
+}
+
+static void
+Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40085a;
+}
+
+static void
+Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81f01;
+}
+
+static void
+Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40089a;
+}
+
+static void
+Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81f81;
+}
+
+static void
+Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008ca;
+}
+
+static void
+Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5581;
+}
+
+static void
+Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008fa;
+}
+
+static void
+Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5701;
+}
+
+static void
+Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40006a;
+}
+
+static void
+Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5d01;
+}
+
+static void
+Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000aa;
+}
+
+static void
+Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85501;
+}
+
+static void
+Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000da;
+}
+
+static void
+Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5781;
+}
+
+static void
+Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000b;
+}
+
+static void
+Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d81;
+}
+
+static void
+Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40086a;
+}
+
+static void
+Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f01;
+}
+
+static void
+Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008aa;
+}
+
+static void
+Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81d01;
+}
+
+static void
+Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008da;
+}
+
+static void
+Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f81;
+}
+
+static void
+Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40080b;
+}
+
+static void
+Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85701;
+}
+
+static void
+Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40007a;
+}
+
+static void
+Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85d01;
+}
+
+static void
+Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000ba;
+}
+
+static void
+Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85781;
+}
+
+static void
+Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000ea;
+}
+
+static void
+Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85d81;
+}
+
+static void
+Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40001b;
+}
+
+static void
+Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5d81;
+}
+
+static void
+Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40087a;
+}
+
+static void
+Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5f01;
+}
+
+static void
+Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008ba;
+}
+
+static void
+Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5f81;
+}
+
+static void
+Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008ea;
+}
+
+static void
+Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85581;
+}
+
+static void
+Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40081b;
+}
+
+static void
+Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3501;
+}
+
+static void
+Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40002b;
+}
+
+static void
+Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6501;
+}
+
+static void
+Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40005b;
+}
+
+static void
+Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82581;
+}
+
+static void
+Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40008b;
+}
+
+static void
+Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2781;
+}
+
+static void
+Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000bb;
+}
+
+static void
+Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83501;
+}
+
+static void
+Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40082b;
+}
+
+static void
+Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3781;
+}
+
+static void
+Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40085b;
+}
+
+static void
+Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d81;
+}
+
+static void
+Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40088b;
+}
+
+static void
+Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f01;
+}
+
+static void
+Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008bb;
+}
+
+static void
+Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82f81;
+}
+
+static void
+Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40003b;
+}
+
+static void
+Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3581;
+}
+
+static void
+Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40006b;
+}
+
+static void
+Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3701;
+}
+
+static void
+Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40009b;
+}
+
+static void
+Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d01;
+}
+
+static void
+Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000cb;
+}
+
+static void
+Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85f81;
+}
+
+static void
+Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40083b;
+}
+
+static void
+Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2581;
+}
+
+static void
+Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40086b;
+}
+
+static void
+Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2701;
+}
+
+static void
+Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40089b;
+}
+
+static void
+Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d01;
+}
+
+static void
+Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008cb;
+}
+
+static void
+Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82d01;
+}
+
+static void
+Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40004b;
+}
+
+static void
+Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f81;
+}
+
+static void
+Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40007b;
+}
+
+static void
+Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82d81;
+}
+
+static void
+Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000ab;
+}
+
+static void
+Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82f01;
+}
+
+static void
+Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000db;
+}
+
+static void
+Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82701;
+}
+
+static void
+Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40084b;
+}
+
+static void
+Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82781;
+}
+
+static void
+Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40087b;
+}
+
+static void
+Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d81;
+}
+
+static void
+Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008ab;
+}
+
+static void
+Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f01;
+}
+
+static void
+Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008db;
+}
+
+static void
+Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x206581;
+}
+
+static void
+Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40001c;
+}
+
+static void
+Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406581;
+}
+
+static void
+Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40021c;
+}
+
+static void
+Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x606581;
+}
+
+static void
+Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40002c;
+}
+
+static void
+Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6781;
+}
+
+static void
+Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40022c;
+}
+
+static void
+Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6581;
+}
+
+static void
+Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40011c;
+}
+
+static void
+Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6701;
+}
+
+static void
+Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40031c;
+}
+
+static void
+Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d01;
+}
+
+static void
+Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40012c;
+}
+
+static void
+Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7501;
+}
+
+static void
+Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40032c;
+}
+
+static void
+Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83781;
+}
+
+static void
+Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40003c;
+}
+
+static void
+Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x183701;
+}
+
+static void
+Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40083c;
+}
+
+static void
+Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x183781;
+}
+
+static void
+Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40004c;
+}
+
+static void
+Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83d81;
+}
+
+static void
+Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40084c;
+}
+
+static void
+Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83581;
+}
+
+static void
+Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40043c;
+}
+
+static void
+Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83701;
+}
+
+static void
+Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400c3c;
+}
+
+static void
+Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83d01;
+}
+
+static void
+Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40044c;
+}
+
+static void
+Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x183581;
+}
+
+static void
+Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400c4c;
+}
+
+static void
+Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x46001;
+}
+
+static void
+Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86001;
+}
+
+static void
+Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86501;
+}
+
+static void
+Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40009c;
+}
+
+static void
+Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd081;
+}
+
+static void
+Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x24000;
+}
+
+static void
+Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x89001;
+}
+
+static void
+Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x14000;
+}
+
+static void
+Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd001;
+}
+
+static void
+Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc000;
+}
+
+static void
+Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9081;
+}
+
+static void
+Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402081;
+}
+
+static void
+Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x202081;
+}
+
+static void
+Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2001;
+}
+
+static void
+Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1001;
+}
+
+static void
+Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85f01;
+}
+
+static void
+Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000c;
+}
+
+static void
+Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f81;
+}
+
+static void
+Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40080c;
+}
+
+static void
+Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83f81;
+}
+
+static void
+Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000bc;
+}
+
+static void
+Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83f01;
+}
+
+static void
+Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008bc;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5501;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000eb;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d01;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008eb;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1701;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000fb;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1581;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008fb;
+}
+
+static void
+Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20005;
+}
+
+static void
+Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86e01;
+}
+
+static void
+Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3881;
+}
+
+static void
+Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3481;
+}
+
+static void
+Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3281;
+}
+
+static void
+Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3081;
+}
+
+static void
+Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86401;
+}
+
+static void
+Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86201;
+}
+
+static void
+Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x284581;
+}
+
+static void
+Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380581;
+}
+
+static void
+Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xef01;
+}
+
+static void
+Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41409c;
+}
+
+static void
+Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x806f81;
+}
+
+static void
+Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41005e;
+}
+
+static void
+Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f81;
+}
+
+static void
+Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41006e;
+}
+
+static void
+Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x206701;
+}
+
+static void
+Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x43027e;
+}
+
+static void
+Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300581;
+}
+
+static void
+Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280581;
+}
+
+static void
+Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x488605;
+}
+
+static void
+Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c0581;
+}
+
+static void
+Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a0581;
+}
+
+static void
+Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x390581;
+}
+
+static void
+Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x183d81;
+}
+
+static void
+Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41007e;
+}
+
+static void
+Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1083f01;
+}
+
+static void
+Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40007c;
+}
+
+static void
+Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x883f01;
+}
+
+static void
+Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40087c;
+}
+
+static void
+Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4083f01;
+}
+
+static void
+Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40008c;
+}
+
+static void
+Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2083f01;
+}
+
+static void
+Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40088c;
+}
+
+static void
+Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1081;
+}
+
+static void
+Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x89081;
+}
+
+static void
+Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16001;
+}
+
+static void
+Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6001;
+}
+
+static void
+Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81081;
+}
+
+static void
+Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5081;
+}
+
+static void
+Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81;
+}
+
+static void
+Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5001;
+}
+
+static void
+Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8d001;
+}
+
+static void
+Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26001;
+}
+
+static void
+Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa001;
+}
+
+static void
+Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9001;
+}
+
+static void
+Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85001;
+}
+
+static void
+Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x85081;
+}
+
+static void
+Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8d081;
+}
+
+static void
+Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x102081;
+}
+
+static void
+Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3001;
+}
+
+static void
+Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2081;
+}
+
+static void
+Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40005;
+}
+
+static void
+Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280605;
+}
+
+static void
+Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600605;
+}
+
+static void
+Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480605;
+}
+
+static void
+Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100605;
+}
+
+static void
+Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200605;
+}
+
+static void
+Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x205;
+}
+
+static void
+Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x605;
+}
+
+static void
+Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300605;
+}
+
+static void
+Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x484605;
+}
+
+static void
+Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500605;
+}
+
+static void
+Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80605;
+}
+
+static void
+Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400605;
+}
+
+static void
+Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180605;
+}
+
+static void
+Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380605;
+}
+
+static void
+Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x101;
+}
+
+static void
+Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x501;
+}
+
+static void
+Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x301;
+}
+
+static void
+Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86801;
+}
+
+static void
+Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86c01;
+}
+
+static void
+Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86a01;
+}
+
+static void
+Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x181;
+}
+
+static void
+Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86601;
+}
+
+static void
+Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d81;
+}
+
+static void
+Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40005c;
+}
+
+static void
+Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16d81;
+}
+
+static void
+Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40105c;
+}
+
+static void
+Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xed81;
+}
+
+static void
+Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40205c;
+}
+
+static void
+Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16f01;
+}
+
+static void
+Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41009c;
+}
+
+static void
+Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80ef01;
+}
+
+static void
+Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41109c;
+}
+
+static void
+Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4ef01;
+}
+
+static void
+Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41209c;
+}
+
+static void
+Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1006f81;
+}
+
+static void
+Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41001e;
+}
+
+static void
+Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1806f81;
+}
+
+static void
+Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41002e;
+}
+
+static void
+Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4006f81;
+}
+
+static void
+Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41003e;
+}
+
+static void
+Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f01;
+}
+
+static void
+Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40305c;
+}
+
+static void
+Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2ef01;
+}
+
+static void
+Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41309c;
+}
+
+static void
+Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2006f81;
+}
+
+static void
+Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41004e;
+}
+
+static void
+Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10005;
+}
+
+static void
+Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x805;
+}
+
+static void
+Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x405;
+}
+
+static void
+Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x183d01;
+}
+
+static void
+Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41047e;
+}
+
+static void
+Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500901;
+}
+
+static void
+Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300901;
+}
+
+static void
+Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600901;
+}
+
+static void
+Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100901;
+}
+
+static void
+Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400901;
+}
+
+static void
+Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200901;
+}
+
+static void
+Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680901;
+}
+
+static void
+Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180901;
+}
+
+static void
+Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480901;
+}
+
+static void
+Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280901;
+}
+
+static void
+Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700901;
+}
+
+static void
+Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80901;
+}
+
+static void
+Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100086;
+}
+
+static void
+Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x88186;
+}
+
+static void
+Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180006;
+}
+
+static void
+Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c186;
+}
+
+static void
+Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c006;
+}
+
+static void
+Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x108006;
+}
+
+static void
+Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c106;
+}
+
+static void
+Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x88106;
+}
+
+static void
+Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x104006;
+}
+
+static void
+Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c086;
+}
+
+static void
+Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x88086;
+}
+
+static void
+Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100106;
+}
+
+static void
+Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4106;
+}
+
+static void
+Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200006;
+}
+
+static void
+Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc186;
+}
+
+static void
+Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4086;
+}
+
+static void
+Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100006;
+}
+
+static void
+Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc106;
+}
+
+static void
+Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x186;
+}
+
+static void
+Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80006;
+}
+
+static void
+Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc086;
+}
+
+static void
+Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400006;
+}
+
+static void
+Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8006;
+}
+
+static void
+Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8186;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180086;
+}
+
+static void
+Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x108186;
+}
+
+static void
+Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x188086;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10c186;
+}
+
+static void
+Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10c006;
+}
+
+static void
+Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x184186;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10c106;
+}
+
+static void
+Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x108106;
+}
+
+static void
+Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x184106;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10c086;
+}
+
+static void
+Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x108086;
+}
+
+static void
+Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x184086;
+}
+
+static void
+Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc006;
+}
+
+static void
+Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x88006;
+}
+
+static void
+Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8106;
+}
+
+static void
+Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x84006;
+}
+
+static void
+Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8086;
+}
+
+static void
+Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80106;
+}
+
+static void
+Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4186;
+}
+
+static void
+Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80086;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180186;
+}
+
+static void
+Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18c086;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x188006;
+}
+
+static void
+Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x188186;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x184006;
+}
+
+static void
+Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18c006;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180106;
+}
+
+static void
+Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x188106;
+}
+
+static void
+Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380381;
+}
+
+static void
+Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300381;
+}
+
+static void
+Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500381;
+}
+
+static void
+Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480381;
+}
+
+static void
+Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580381;
+}
+
+static void
+Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600381;
+}
+
+static void
+Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700381;
+}
+
+static void
+Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680381;
+}
+
+static void
+Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x381;
+}
+
+static void
+Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x901;
+}
+
+static void
+Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100381;
+}
+
+static void
+Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80381;
+}
+
+static void
+Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400381;
+}
+
+static void
+Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200381;
+}
+
+static void
+Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280381;
+}
+
+static void
+Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180381;
+}
+
+static void
+Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x581;
+}
+
+static void
+Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780381;
+}
+
+static void
+Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80581;
+}
+
+static void
+Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x701;
+}
+
+static void
+Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200581;
+}
+
+static void
+Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100581;
+}
+
+static void
+Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180581;
+}
+
+static void
+Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400581;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380002;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100002;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600002;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180002;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280002;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480002;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200002;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300002;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80002;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500002;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400002;
+}
+
+static void
+Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700002;
+}
+
+static void
+Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80003;
+}
+
+static void
+Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580002;
+}
+
+static void
+Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780002;
+}
+
+static void
+Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680002;
+}
+
+static void
+Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500003;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200004;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680003;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700003;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380003;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600003;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780003;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480003;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100004;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580003;
+}
+
+static void
+Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500004;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400004;
+}
+
+static void
+Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300004;
+}
+
+static void
+Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600004;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x204006;
+}
+
+static void
+Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280006;
+}
+
+static void
+Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x208006;
+}
+
+static void
+Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300006;
+}
+
+static void
+Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200186;
+}
+
+static void
+Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x204106;
+}
+
+static void
+Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x204086;
+}
+
+static void
+Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x204186;
+}
+
+static void
+Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x208086;
+}
+
+static void
+Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c006;
+}
+
+static void
+Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x208106;
+}
+
+static void
+Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x208186;
+}
+
+static void
+Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c086;
+}
+
+static void
+Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c186;
+}
+
+static void
+Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c106;
+}
+
+static void
+Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280086;
+}
+
+static void
+Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x106;
+}
+
+static void
+Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x86;
+}
+
+static void
+Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4006;
+}
+
+static void
+Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80186;
+}
+
+static void
+Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x84106;
+}
+
+static void
+Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x84086;
+}
+
+static void
+Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x84186;
+}
+
+static void
+Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100186;
+}
+
+static void
+Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x104106;
+}
+
+static void
+Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x104086;
+}
+
+static void
+Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x104186;
+}
+
+static void
+Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18c106;
+}
+
+static void
+Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200086;
+}
+
+static void
+Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18c186;
+}
+
+static void
+Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200106;
+}
+
+static void
+Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41000e;
+}
+
+static void
+Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000a;
+}
+
+static void
+Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40001a;
+}
+
+static void
+Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410e7e;
+}
+
+static void
+Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4008ac;
+}
+
+static void
+Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40006c;
+}
+
+static void
+Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x42000e;
+}
+
+static void
+Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40002a;
+}
+
+static void
+Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000e;
+}
+
+static void
+Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40010f;
+}
+
+static void
+Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40020f;
+}
+
+static void
+Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40003a;
+}
+
+static void
+Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40004a;
+}
+
+static void
+Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40011f;
+}
+
+static void
+Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000f;
+}
+
+static void
+Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410c7e;
+}
+
+static void
+Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410d7e;
+}
+
+static void
+Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6006f81;
+}
+
+static void
+Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8e001;
+}
+
+static void
+Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe001;
+}
+
+static void
+Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240005;
+}
+
+static void
+Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x440005;
+}
+
+static void
+Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f03e;
+}
+
+static void
+Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf63f;
+}
+
+static void
+Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f03e;
+}
+
+static void
+Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf73f;
+}
+
+static void
+Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f01;
+}
+
+static void
+Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87781;
+}
+
+static void
+Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87f01;
+}
+
+static void
+Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7781;
+}
+
+static void
+Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87d01;
+}
+
+static void
+Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87581;
+}
+
+static void
+Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7701;
+}
+
+static void
+Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87d81;
+}
+
+static void
+Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87701;
+}
+
+static void
+Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d81;
+}
+
+static void
+Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d01;
+}
+
+static void
+Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7581;
+}
+
+static void
+Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x207501;
+}
+
+static void
+Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x87f81;
+}
+
+static void
+Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407501;
+}
+
+static void
+Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f81;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e03e;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe63f;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e0;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x21e0;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+ Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+ Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+ Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+ Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+ Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+ Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+ Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+ Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+ Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = {
+ Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
+ Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
+ Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+ Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+ Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+ Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+ Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+ Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+ Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+ Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+ Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+ Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+ Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+ Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+ Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+ Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+ Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+ Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+ Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+ Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+ Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+ Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+ Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+ Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+ Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+ Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+ Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+ Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+ Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+ Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+ Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+ Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+ Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+ Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+ Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+ Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+ Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+ Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+ Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+ Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+ Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+ Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+ Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+ Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+ Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+ Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+ Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+ Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+ Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+ Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+ Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+ Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+ Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+ Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+ Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+ Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+ Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+ Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+ Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+ Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+ Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+ Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+ Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+ Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+ Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+ Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+ Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+ Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+ Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+ Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+ Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+ Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+ Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+ Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+ Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+ Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+ Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+ Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+ Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+ Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+ Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+ Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+ Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+ Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+ Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+ Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+ Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+ Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+ Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+ Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
+ Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
+ Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
+ Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
+ Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
+ Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
+ Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
+ Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
+ Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
+ Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
+ Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
+ Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
+ Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
+ Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
+ Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
+ Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
+ Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
+ Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
+ Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
+ Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
+ Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
+ Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
+ Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
+ Opcode_diu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = {
+ Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = {
+ Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = {
+ Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
+ Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
+ Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
+ Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
+ Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
+ Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
+ Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
+ Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
+ Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
+ Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
+ Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
+ Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
+ Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
+ Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
+ Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
+ Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+ Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+ Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+ Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
+ Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
+ Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
+ Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
+ Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
+ Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
+ Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
+ Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
+ Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
+ Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
+ Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
+ Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
+ Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
+ Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
+ Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
+ Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
+ Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
+ Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
+ Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
+ Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
+ Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
+ Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
+ Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
+ Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
+ Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
+ Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
+ Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
+ Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
+ Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
+ Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
+ Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
+ Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
+ Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
+ Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
+ Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
+ Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
+ Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
+ Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
+ Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
+ Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
+ Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
+ Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
+ Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
+ Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
+ Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
+ Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
+ Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
+ Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
+ Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
+ Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
+ Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
+ Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
+ Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
+ Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
+ Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
+ Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
+ Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
+ Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
+ Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
+ Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
+ Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
+ Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
+ Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
+ Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
+ Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
+ Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
+ Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
+ Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
+ Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
+ Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
+ Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
+ Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
+ Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
+ Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
+ Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
+ Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
+ Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
+ Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
+ Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
+ Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
+ Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
+ Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
+ Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
+ Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
+ Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
+ Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
+ Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
+ Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
+ Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
+ Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
+ Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
+ Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
+ Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
+ Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
+ Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
+ Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
+ Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
+ Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
+ Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
+ Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
+ Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
+ Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
+ Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
+ Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
+ Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
+ Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
+ Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
+ Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
+ Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
+ Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
+ Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
+ Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
+ Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
+ Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
+ Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
+ Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
+ Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
+ Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
+ Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
+ Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
+ Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
+ Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
+ Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
+ Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
+ Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
+ Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
+ Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
+ Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
+ Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
+ Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
+ Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
+ Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
+ Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = {
+ Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = {
+ Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = {
+ Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = {
+ Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = {
+ 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+ Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+ Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+ Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+ Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+ Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+ Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0
+};
+
+
+
+
+\f
+/* Opcode table. */
+
+static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_shift32x5, 3 },
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_shift32x5, 3 },
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "rur.threadptr", ICLASS_rur_threadptr,
+ 0,
+ Opcode_rur_threadptr_encode_fns, 0, 0 },
+ { "wur.threadptr", ICLASS_wur_threadptr,
+ 0,
+ Opcode_wur_threadptr_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", ICLASS_xt_iclass_loop,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s32nb", ICLASS_xt_iclass_s32nb,
+ 0,
+ Opcode_s32nb_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+ 0,
+ Opcode_rsr_memctl_encode_fns, 0, 0 },
+ { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+ 0,
+ Opcode_wsr_memctl_encode_fns, 0, 0 },
+ { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+ 0,
+ Opcode_xsr_memctl_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+ 0,
+ Opcode_rsr_configid0_encode_fns, 0, 0 },
+ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+ 0,
+ Opcode_wsr_configid0_encode_fns, 0, 0 },
+ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+ 0,
+ Opcode_rsr_configid1_encode_fns, 0, 0 },
+ { "rsr.243", ICLASS_xt_iclass_rsr_243,
+ 0,
+ Opcode_rsr_243_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+ 0,
+ Opcode_rsr_epc3_encode_fns, 0, 0 },
+ { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+ 0,
+ Opcode_wsr_epc3_encode_fns, 0, 0 },
+ { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+ 0,
+ Opcode_xsr_epc3_encode_fns, 0, 0 },
+ { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+ 0,
+ Opcode_rsr_excsave3_encode_fns, 0, 0 },
+ { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+ 0,
+ Opcode_wsr_excsave3_encode_fns, 0, 0 },
+ { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+ 0,
+ Opcode_xsr_excsave3_encode_fns, 0, 0 },
+ { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+ 0,
+ Opcode_rsr_epc4_encode_fns, 0, 0 },
+ { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+ 0,
+ Opcode_wsr_epc4_encode_fns, 0, 0 },
+ { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+ 0,
+ Opcode_xsr_epc4_encode_fns, 0, 0 },
+ { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+ 0,
+ Opcode_rsr_excsave4_encode_fns, 0, 0 },
+ { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+ 0,
+ Opcode_wsr_excsave4_encode_fns, 0, 0 },
+ { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+ 0,
+ Opcode_xsr_excsave4_encode_fns, 0, 0 },
+ { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+ 0,
+ Opcode_rsr_epc5_encode_fns, 0, 0 },
+ { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+ 0,
+ Opcode_wsr_epc5_encode_fns, 0, 0 },
+ { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+ 0,
+ Opcode_xsr_epc5_encode_fns, 0, 0 },
+ { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+ 0,
+ Opcode_rsr_excsave5_encode_fns, 0, 0 },
+ { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+ 0,
+ Opcode_wsr_excsave5_encode_fns, 0, 0 },
+ { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+ 0,
+ Opcode_xsr_excsave5_encode_fns, 0, 0 },
+ { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+ 0,
+ Opcode_rsr_epc6_encode_fns, 0, 0 },
+ { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+ 0,
+ Opcode_wsr_epc6_encode_fns, 0, 0 },
+ { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+ 0,
+ Opcode_xsr_epc6_encode_fns, 0, 0 },
+ { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+ 0,
+ Opcode_rsr_excsave6_encode_fns, 0, 0 },
+ { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+ 0,
+ Opcode_wsr_excsave6_encode_fns, 0, 0 },
+ { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+ 0,
+ Opcode_xsr_excsave6_encode_fns, 0, 0 },
+ { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+ 0,
+ Opcode_rsr_epc7_encode_fns, 0, 0 },
+ { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+ 0,
+ Opcode_wsr_epc7_encode_fns, 0, 0 },
+ { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+ 0,
+ Opcode_xsr_epc7_encode_fns, 0, 0 },
+ { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+ 0,
+ Opcode_rsr_excsave7_encode_fns, 0, 0 },
+ { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+ 0,
+ Opcode_wsr_excsave7_encode_fns, 0, 0 },
+ { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+ 0,
+ Opcode_xsr_excsave7_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+ 0,
+ Opcode_rsr_eps3_encode_fns, 0, 0 },
+ { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+ 0,
+ Opcode_wsr_eps3_encode_fns, 0, 0 },
+ { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+ 0,
+ Opcode_xsr_eps3_encode_fns, 0, 0 },
+ { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+ 0,
+ Opcode_rsr_eps4_encode_fns, 0, 0 },
+ { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+ 0,
+ Opcode_wsr_eps4_encode_fns, 0, 0 },
+ { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+ 0,
+ Opcode_xsr_eps4_encode_fns, 0, 0 },
+ { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+ 0,
+ Opcode_rsr_eps5_encode_fns, 0, 0 },
+ { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+ 0,
+ Opcode_wsr_eps5_encode_fns, 0, 0 },
+ { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+ 0,
+ Opcode_xsr_eps5_encode_fns, 0, 0 },
+ { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+ 0,
+ Opcode_rsr_eps6_encode_fns, 0, 0 },
+ { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+ 0,
+ Opcode_wsr_eps6_encode_fns, 0, 0 },
+ { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+ 0,
+ Opcode_xsr_eps6_encode_fns, 0, 0 },
+ { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+ 0,
+ Opcode_rsr_eps7_encode_fns, 0, 0 },
+ { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+ 0,
+ Opcode_wsr_eps7_encode_fns, 0, 0 },
+ { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+ 0,
+ Opcode_xsr_eps7_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "muluh", ICLASS_xt_mul32h,
+ 0,
+ Opcode_muluh_encode_fns, 0, 0 },
+ { "mulsh", ICLASS_xt_mul32h,
+ 0,
+ Opcode_mulsh_encode_fns, 0, 0 },
+ { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_ll_encode_fns, 0, 0 },
+ { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hl_encode_fns, 0, 0 },
+ { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_lh_encode_fns, 0, 0 },
+ { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_mul_aa_hh_encode_fns, 0, 0 },
+ { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_ll_encode_fns, 0, 0 },
+ { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hl_encode_fns, 0, 0 },
+ { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_lh_encode_fns, 0, 0 },
+ { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+ 0,
+ Opcode_umul_aa_hh_encode_fns, 0, 0 },
+ { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_ll_encode_fns, 0, 0 },
+ { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hl_encode_fns, 0, 0 },
+ { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_lh_encode_fns, 0, 0 },
+ { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
+ 0,
+ Opcode_mul_ad_hh_encode_fns, 0, 0 },
+ { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_ll_encode_fns, 0, 0 },
+ { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hl_encode_fns, 0, 0 },
+ { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_lh_encode_fns, 0, 0 },
+ { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
+ 0,
+ Opcode_mul_da_hh_encode_fns, 0, 0 },
+ { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_ll_encode_fns, 0, 0 },
+ { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hl_encode_fns, 0, 0 },
+ { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_lh_encode_fns, 0, 0 },
+ { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
+ 0,
+ Opcode_mul_dd_hh_encode_fns, 0, 0 },
+ { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_ll_encode_fns, 0, 0 },
+ { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hl_encode_fns, 0, 0 },
+ { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_lh_encode_fns, 0, 0 },
+ { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_mula_aa_hh_encode_fns, 0, 0 },
+ { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_ll_encode_fns, 0, 0 },
+ { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hl_encode_fns, 0, 0 },
+ { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_lh_encode_fns, 0, 0 },
+ { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+ 0,
+ Opcode_muls_aa_hh_encode_fns, 0, 0 },
+ { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_ll_encode_fns, 0, 0 },
+ { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hl_encode_fns, 0, 0 },
+ { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_lh_encode_fns, 0, 0 },
+ { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_mula_ad_hh_encode_fns, 0, 0 },
+ { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_ll_encode_fns, 0, 0 },
+ { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hl_encode_fns, 0, 0 },
+ { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_lh_encode_fns, 0, 0 },
+ { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+ 0,
+ Opcode_muls_ad_hh_encode_fns, 0, 0 },
+ { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_ll_encode_fns, 0, 0 },
+ { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hl_encode_fns, 0, 0 },
+ { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_lh_encode_fns, 0, 0 },
+ { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_mula_da_hh_encode_fns, 0, 0 },
+ { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_ll_encode_fns, 0, 0 },
+ { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hl_encode_fns, 0, 0 },
+ { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_lh_encode_fns, 0, 0 },
+ { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
+ 0,
+ Opcode_muls_da_hh_encode_fns, 0, 0 },
+ { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_ll_encode_fns, 0, 0 },
+ { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hl_encode_fns, 0, 0 },
+ { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_lh_encode_fns, 0, 0 },
+ { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_mula_dd_hh_encode_fns, 0, 0 },
+ { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_ll_encode_fns, 0, 0 },
+ { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hl_encode_fns, 0, 0 },
+ { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_lh_encode_fns, 0, 0 },
+ { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+ 0,
+ Opcode_muls_dd_hh_encode_fns, 0, 0 },
+ { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+ { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+ { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+ { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+ { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
+ 0,
+ Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+ { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+ { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+ { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+ 0,
+ Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+ { "lddec", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_lddec_encode_fns, 0, 0 },
+ { "ldinc", ICLASS_xt_iclass_mac16_l,
+ 0,
+ Opcode_ldinc_encode_fns, 0, 0 },
+ { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
+ 0,
+ Opcode_rsr_m0_encode_fns, 0, 0 },
+ { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
+ 0,
+ Opcode_wsr_m0_encode_fns, 0, 0 },
+ { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
+ 0,
+ Opcode_xsr_m0_encode_fns, 0, 0 },
+ { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
+ 0,
+ Opcode_rsr_m1_encode_fns, 0, 0 },
+ { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
+ 0,
+ Opcode_wsr_m1_encode_fns, 0, 0 },
+ { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
+ 0,
+ Opcode_xsr_m1_encode_fns, 0, 0 },
+ { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
+ 0,
+ Opcode_rsr_m2_encode_fns, 0, 0 },
+ { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
+ 0,
+ Opcode_wsr_m2_encode_fns, 0, 0 },
+ { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
+ 0,
+ Opcode_xsr_m2_encode_fns, 0, 0 },
+ { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
+ 0,
+ Opcode_rsr_m3_encode_fns, 0, 0 },
+ { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
+ 0,
+ Opcode_wsr_m3_encode_fns, 0, 0 },
+ { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
+ 0,
+ Opcode_xsr_m3_encode_fns, 0, 0 },
+ { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
+ 0,
+ Opcode_rsr_acclo_encode_fns, 0, 0 },
+ { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
+ 0,
+ Opcode_wsr_acclo_encode_fns, 0, 0 },
+ { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
+ 0,
+ Opcode_xsr_acclo_encode_fns, 0, 0 },
+ { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
+ 0,
+ Opcode_rsr_acchi_encode_fns, 0, 0 },
+ { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
+ 0,
+ Opcode_wsr_acchi_encode_fns, 0, 0 },
+ { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
+ 0,
+ Opcode_xsr_acchi_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+ 0,
+ Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+ { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+ 0,
+ Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+ { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+ 0,
+ Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+ { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+ 0,
+ Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+ { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+ 0,
+ Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+ { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+ 0,
+ Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+ { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+ 0,
+ Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+ { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+ 0,
+ Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+ { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+ 0,
+ Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+ { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+ 0,
+ Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+ { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+ 0,
+ Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+ { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+ 0,
+ Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+ { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+ 0,
+ Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+ { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+ 0,
+ Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+ { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+ 0,
+ Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+ { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+ 0,
+ Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+ { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+ 0,
+ Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+ { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+ 0,
+ Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+ { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+ 0,
+ Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+ { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+ 0,
+ Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+ { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+ 0,
+ Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+ 0,
+ Opcode_lddr32_p_encode_fns, 0, 0 },
+ { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+ 0,
+ Opcode_sddr32_p_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+ 0,
+ Opcode_wsr_mmid_encode_fns, 0, 0 },
+ { "andb", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_andb_encode_fns, 0, 0 },
+ { "andbc", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_andbc_encode_fns, 0, 0 },
+ { "orb", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_orb_encode_fns, 0, 0 },
+ { "orbc", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_orbc_encode_fns, 0, 0 },
+ { "xorb", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_xorb_encode_fns, 0, 0 },
+ { "any4", ICLASS_xt_iclass_bbool4,
+ 0,
+ Opcode_any4_encode_fns, 0, 0 },
+ { "all4", ICLASS_xt_iclass_bbool4,
+ 0,
+ Opcode_all4_encode_fns, 0, 0 },
+ { "any8", ICLASS_xt_iclass_bbool8,
+ 0,
+ Opcode_any8_encode_fns, 0, 0 },
+ { "all8", ICLASS_xt_iclass_bbool8,
+ 0,
+ Opcode_all8_encode_fns, 0, 0 },
+ { "bf", ICLASS_xt_iclass_bbranch,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bf_encode_fns, 0, 0 },
+ { "bt", ICLASS_xt_iclass_bbranch,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bt_encode_fns, 0, 0 },
+ { "movf", ICLASS_xt_iclass_bmove,
+ 0,
+ Opcode_movf_encode_fns, 0, 0 },
+ { "movt", ICLASS_xt_iclass_bmove,
+ 0,
+ Opcode_movt_encode_fns, 0, 0 },
+ { "rsr.br", ICLASS_xt_iclass_RSR_BR,
+ 0,
+ Opcode_rsr_br_encode_fns, 0, 0 },
+ { "wsr.br", ICLASS_xt_iclass_WSR_BR,
+ 0,
+ Opcode_wsr_br_encode_fns, 0, 0 },
+ { "xsr.br", ICLASS_xt_iclass_XSR_BR,
+ 0,
+ Opcode_xsr_br_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+ 0,
+ Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+ { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+ 0,
+ Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+ { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+ 0,
+ Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+ { "ipf", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "ipfl", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ipfl_encode_fns, 0, 0 },
+ { "ihu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_ihu_encode_fns, 0, 0 },
+ { "iiu", ICLASS_xt_iclass_icache_lock,
+ 0,
+ Opcode_iiu_encode_fns, 0, 0 },
+ { "iii", ICLASS_xt_iclass_icache_inv,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
+ 0,
+ Opcode_diwbui_p_encode_fns, 0, 0 },
+ { "diwb", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "dpfl", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dpfl_encode_fns, 0, 0 },
+ { "dhu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_dhu_encode_fns, 0, 0 },
+ { "diu", ICLASS_xt_iclass_dcache_lock,
+ 0,
+ Opcode_diu_encode_fns, 0, 0 },
+ { "sdct", ICLASS_xt_iclass_sdct,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", ICLASS_xt_iclass_ldct,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl,
+ 0,
+ Opcode_rsr_prefctl_encode_fns, 0, 0 },
+ { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl,
+ 0,
+ Opcode_wsr_prefctl_encode_fns, 0, 0 },
+ { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl,
+ 0,
+ Opcode_xsr_prefctl_encode_fns, 0, 0 },
+ { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
+ 0,
+ Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
+ 0,
+ Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
+ { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
+ 0,
+ Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
+ 0,
+ Opcode_rsr_rasid_encode_fns, 0, 0 },
+ { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
+ 0,
+ Opcode_wsr_rasid_encode_fns, 0, 0 },
+ { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
+ 0,
+ Opcode_xsr_rasid_encode_fns, 0, 0 },
+ { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
+ 0,
+ Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
+ { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
+ 0,
+ Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
+ { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
+ 0,
+ Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
+ { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
+ 0,
+ Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
+ { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
+ 0,
+ Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
+ { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
+ 0,
+ Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "ldpte", ICLASS_xt_iclass_ldpte,
+ 0,
+ Opcode_ldpte_encode_fns, 0, 0 },
+ { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_hwwitlba_encode_fns, 0, 0 },
+ { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
+ 0,
+ Opcode_hwwdtlba_encode_fns, 0, 0 },
+ { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
+ 0,
+ Opcode_rsr_cpenable_encode_fns, 0, 0 },
+ { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
+ 0,
+ Opcode_wsr_cpenable_encode_fns, 0, 0 },
+ { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
+ 0,
+ Opcode_xsr_cpenable_encode_fns, 0, 0 },
+ { "clamps", ICLASS_xt_iclass_clamp,
+ 0,
+ Opcode_clamps_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "quou", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quou_encode_fns, 0, 0 },
+ { "quos", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_quos_encode_fns, 0, 0 },
+ { "remu", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_remu_encode_fns, 0, 0 },
+ { "rems", ICLASS_xt_iclass_div,
+ 0,
+ Opcode_rems_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
+ 0,
+ Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
+ { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
+ 0,
+ Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
+ { "rur.ae_bithead", ICLASS_rur_ae_bithead,
+ 0,
+ Opcode_rur_ae_bithead_encode_fns, 0, 0 },
+ { "wur.ae_bithead", ICLASS_wur_ae_bithead,
+ 0,
+ Opcode_wur_ae_bithead_encode_fns, 0, 0 },
+ { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
+ 0,
+ Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
+ { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
+ 0,
+ Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
+ { "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
+ 0,
+ Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
+ { "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
+ 0,
+ Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
+ { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
+ 0,
+ Opcode_rur_ae_overflow_encode_fns, 0, 0 },
+ { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
+ 0,
+ Opcode_wur_ae_overflow_encode_fns, 0, 0 },
+ { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
+ 0,
+ Opcode_rur_ae_sar_encode_fns, 0, 0 },
+ { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
+ 0,
+ Opcode_wur_ae_sar_encode_fns, 0, 0 },
+ { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
+ 0,
+ Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
+ { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
+ 0,
+ Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
+ { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
+ 0,
+ Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
+ { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
+ 0,
+ Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
+ { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
+ 0,
+ Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
+ { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
+ 0,
+ Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
+ { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
+ 0,
+ Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
+ { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
+ 0,
+ Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
+ { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
+ 0,
+ Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
+ { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
+ 0,
+ Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
+ { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
+ 0,
+ Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
+ { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
+ 0,
+ Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
+ { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
+ 0,
+ Opcode_ae_lp16f_i_encode_fns, 0, 0 },
+ { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
+ 0,
+ Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
+ { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
+ 0,
+ Opcode_ae_lp16f_x_encode_fns, 0, 0 },
+ { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
+ 0,
+ Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
+ { "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
+ 0,
+ Opcode_ae_lp24_i_encode_fns, 0, 0 },
+ { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
+ 0,
+ Opcode_ae_lp24_iu_encode_fns, 0, 0 },
+ { "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
+ 0,
+ Opcode_ae_lp24_x_encode_fns, 0, 0 },
+ { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
+ 0,
+ Opcode_ae_lp24_xu_encode_fns, 0, 0 },
+ { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
+ 0,
+ Opcode_ae_lp24f_i_encode_fns, 0, 0 },
+ { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
+ 0,
+ Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
+ { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
+ 0,
+ Opcode_ae_lp24f_x_encode_fns, 0, 0 },
+ { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
+ 0,
+ Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
+ { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
+ 0,
+ Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
+ { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
+ 0,
+ Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
+ { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
+ 0,
+ Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
+ { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
+ 0,
+ Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
+ { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
+ 0,
+ Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
+ { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
+ 0,
+ Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
+ { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
+ 0,
+ Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
+ { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
+ 0,
+ Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
+ { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
+ 0,
+ Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
+ { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
+ 0,
+ Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
+ { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
+ 0,
+ Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
+ { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
+ 0,
+ Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
+ { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
+ 0,
+ Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
+ { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
+ 0,
+ Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
+ { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
+ 0,
+ Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
+ { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
+ 0,
+ Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
+ { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
+ 0,
+ Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
+ { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
+ 0,
+ Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
+ { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
+ 0,
+ Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
+ { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
+ 0,
+ Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
+ { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
+ 0,
+ Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
+ { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
+ 0,
+ Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
+ { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
+ 0,
+ Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
+ { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
+ 0,
+ Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
+ { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
+ 0,
+ Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
+ { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
+ 0,
+ Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
+ { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
+ 0,
+ Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
+ { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
+ 0,
+ Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
+ { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
+ 0,
+ Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
+ { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
+ 0,
+ Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
+ { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
+ 0,
+ Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
+ { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
+ 0,
+ Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
+ { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
+ 0,
+ Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
+ { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
+ 0,
+ Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
+ { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
+ 0,
+ Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
+ { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
+ 0,
+ Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
+ { "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
+ 0,
+ Opcode_ae_lq56_i_encode_fns, 0, 0 },
+ { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
+ 0,
+ Opcode_ae_lq56_iu_encode_fns, 0, 0 },
+ { "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
+ 0,
+ Opcode_ae_lq56_x_encode_fns, 0, 0 },
+ { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
+ 0,
+ Opcode_ae_lq56_xu_encode_fns, 0, 0 },
+ { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
+ 0,
+ Opcode_ae_lq32f_i_encode_fns, 0, 0 },
+ { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
+ 0,
+ Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
+ { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
+ 0,
+ Opcode_ae_lq32f_x_encode_fns, 0, 0 },
+ { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
+ 0,
+ Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
+ { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
+ 0,
+ Opcode_ae_sq56s_i_encode_fns, 0, 0 },
+ { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
+ 0,
+ Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
+ { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
+ 0,
+ Opcode_ae_sq56s_x_encode_fns, 0, 0 },
+ { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
+ 0,
+ Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
+ { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
+ 0,
+ Opcode_ae_sq32f_i_encode_fns, 0, 0 },
+ { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
+ 0,
+ Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
+ { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
+ 0,
+ Opcode_ae_sq32f_x_encode_fns, 0, 0 },
+ { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
+ 0,
+ Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
+ { "ae_zerop48", ICLASS_ae_iclass_zerop48,
+ 0,
+ Opcode_ae_zerop48_encode_fns, 0, 0 },
+ { "ae_movp48", ICLASS_ae_iclass_movp48,
+ 0,
+ Opcode_ae_movp48_encode_fns, 0, 0 },
+ { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
+ 0,
+ Opcode_ae_selp24_ll_encode_fns, 0, 0 },
+ { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
+ 0,
+ Opcode_ae_selp24_lh_encode_fns, 0, 0 },
+ { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
+ 0,
+ Opcode_ae_selp24_hl_encode_fns, 0, 0 },
+ { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
+ 0,
+ Opcode_ae_selp24_hh_encode_fns, 0, 0 },
+ { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
+ 0,
+ Opcode_ae_movtp24x2_encode_fns, 0, 0 },
+ { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
+ 0,
+ Opcode_ae_movfp24x2_encode_fns, 0, 0 },
+ { "ae_movtp48", ICLASS_ae_iclass_movtp48,
+ 0,
+ Opcode_ae_movtp48_encode_fns, 0, 0 },
+ { "ae_movfp48", ICLASS_ae_iclass_movfp48,
+ 0,
+ Opcode_ae_movfp48_encode_fns, 0, 0 },
+ { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
+ 0,
+ Opcode_ae_movpa24x2_encode_fns, 0, 0 },
+ { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
+ 0,
+ Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
+ { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
+ 0,
+ Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
+ { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
+ 0,
+ Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
+ 0,
+ Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
+ 0,
+ Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
+ 0,
+ Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
+ 0,
+ Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
+ { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
+ 0,
+ Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
+ { "ae_truncp16", ICLASS_ae_iclass_truncp16,
+ 0,
+ Opcode_ae_truncp16_encode_fns, 0, 0 },
+ { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
+ 0,
+ Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
+ { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
+ 0,
+ Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
+ { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
+ 0,
+ Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
+ { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
+ 0,
+ Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
+ { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
+ 0,
+ Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
+ { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
+ 0,
+ Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
+ { "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
+ 0,
+ Opcode_ae_zeroq56_encode_fns, 0, 0 },
+ { "ae_movq56", ICLASS_ae_iclass_movq56,
+ 0,
+ Opcode_ae_movq56_encode_fns, 0, 0 },
+ { "ae_movtq56", ICLASS_ae_iclass_movtq56,
+ 0,
+ Opcode_ae_movtq56_encode_fns, 0, 0 },
+ { "ae_movfq56", ICLASS_ae_iclass_movfq56,
+ 0,
+ Opcode_ae_movfq56_encode_fns, 0, 0 },
+ { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
+ 0,
+ Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
+ { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
+ 0,
+ Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
+ { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
+ 0,
+ Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
+ { "ae_satq48s", ICLASS_ae_iclass_satq48s,
+ 0,
+ Opcode_ae_satq48s_encode_fns, 0, 0 },
+ { "ae_truncq32", ICLASS_ae_iclass_truncq32,
+ 0,
+ Opcode_ae_truncq32_encode_fns, 0, 0 },
+ { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
+ 0,
+ Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
+ { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
+ 0,
+ Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
+ { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
+ 0,
+ Opcode_ae_trunca32q48_encode_fns, 0, 0 },
+ { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
+ 0,
+ Opcode_ae_movap24s_l_encode_fns, 0, 0 },
+ { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
+ 0,
+ Opcode_ae_movap24s_h_encode_fns, 0, 0 },
+ { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
+ 0,
+ Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
+ { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
+ 0,
+ Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
+ { "ae_addp24", ICLASS_ae_iclass_addp24,
+ 0,
+ Opcode_ae_addp24_encode_fns, 0, 0 },
+ { "ae_subp24", ICLASS_ae_iclass_subp24,
+ 0,
+ Opcode_ae_subp24_encode_fns, 0, 0 },
+ { "ae_negp24", ICLASS_ae_iclass_negp24,
+ 0,
+ Opcode_ae_negp24_encode_fns, 0, 0 },
+ { "ae_absp24", ICLASS_ae_iclass_absp24,
+ 0,
+ Opcode_ae_absp24_encode_fns, 0, 0 },
+ { "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
+ 0,
+ Opcode_ae_maxp24s_encode_fns, 0, 0 },
+ { "ae_minp24s", ICLASS_ae_iclass_minp24s,
+ 0,
+ Opcode_ae_minp24s_encode_fns, 0, 0 },
+ { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
+ 0,
+ Opcode_ae_maxbp24s_encode_fns, 0, 0 },
+ { "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
+ 0,
+ Opcode_ae_minbp24s_encode_fns, 0, 0 },
+ { "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
+ 0,
+ Opcode_ae_addsp24s_encode_fns, 0, 0 },
+ { "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
+ 0,
+ Opcode_ae_subsp24s_encode_fns, 0, 0 },
+ { "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
+ 0,
+ Opcode_ae_negsp24s_encode_fns, 0, 0 },
+ { "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
+ 0,
+ Opcode_ae_abssp24s_encode_fns, 0, 0 },
+ { "ae_andp48", ICLASS_ae_iclass_andp48,
+ 0,
+ Opcode_ae_andp48_encode_fns, 0, 0 },
+ { "ae_nandp48", ICLASS_ae_iclass_nandp48,
+ 0,
+ Opcode_ae_nandp48_encode_fns, 0, 0 },
+ { "ae_orp48", ICLASS_ae_iclass_orp48,
+ 0,
+ Opcode_ae_orp48_encode_fns, 0, 0 },
+ { "ae_xorp48", ICLASS_ae_iclass_xorp48,
+ 0,
+ Opcode_ae_xorp48_encode_fns, 0, 0 },
+ { "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
+ 0,
+ Opcode_ae_ltp24s_encode_fns, 0, 0 },
+ { "ae_lep24s", ICLASS_ae_iclass_lep24s,
+ 0,
+ Opcode_ae_lep24s_encode_fns, 0, 0 },
+ { "ae_eqp24", ICLASS_ae_iclass_eqp24,
+ 0,
+ Opcode_ae_eqp24_encode_fns, 0, 0 },
+ { "ae_addq56", ICLASS_ae_iclass_addq56,
+ 0,
+ Opcode_ae_addq56_encode_fns, 0, 0 },
+ { "ae_subq56", ICLASS_ae_iclass_subq56,
+ 0,
+ Opcode_ae_subq56_encode_fns, 0, 0 },
+ { "ae_negq56", ICLASS_ae_iclass_negq56,
+ 0,
+ Opcode_ae_negq56_encode_fns, 0, 0 },
+ { "ae_absq56", ICLASS_ae_iclass_absq56,
+ 0,
+ Opcode_ae_absq56_encode_fns, 0, 0 },
+ { "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
+ 0,
+ Opcode_ae_maxq56s_encode_fns, 0, 0 },
+ { "ae_minq56s", ICLASS_ae_iclass_minq56s,
+ 0,
+ Opcode_ae_minq56s_encode_fns, 0, 0 },
+ { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
+ 0,
+ Opcode_ae_maxbq56s_encode_fns, 0, 0 },
+ { "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
+ 0,
+ Opcode_ae_minbq56s_encode_fns, 0, 0 },
+ { "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
+ 0,
+ Opcode_ae_addsq56s_encode_fns, 0, 0 },
+ { "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
+ 0,
+ Opcode_ae_subsq56s_encode_fns, 0, 0 },
+ { "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
+ 0,
+ Opcode_ae_negsq56s_encode_fns, 0, 0 },
+ { "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
+ 0,
+ Opcode_ae_abssq56s_encode_fns, 0, 0 },
+ { "ae_andq56", ICLASS_ae_iclass_andq56,
+ 0,
+ Opcode_ae_andq56_encode_fns, 0, 0 },
+ { "ae_nandq56", ICLASS_ae_iclass_nandq56,
+ 0,
+ Opcode_ae_nandq56_encode_fns, 0, 0 },
+ { "ae_orq56", ICLASS_ae_iclass_orq56,
+ 0,
+ Opcode_ae_orq56_encode_fns, 0, 0 },
+ { "ae_xorq56", ICLASS_ae_iclass_xorq56,
+ 0,
+ Opcode_ae_xorq56_encode_fns, 0, 0 },
+ { "ae_sllip24", ICLASS_ae_iclass_sllip24,
+ 0,
+ Opcode_ae_sllip24_encode_fns, 0, 0 },
+ { "ae_srlip24", ICLASS_ae_iclass_srlip24,
+ 0,
+ Opcode_ae_srlip24_encode_fns, 0, 0 },
+ { "ae_sraip24", ICLASS_ae_iclass_sraip24,
+ 0,
+ Opcode_ae_sraip24_encode_fns, 0, 0 },
+ { "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
+ 0,
+ Opcode_ae_sllsp24_encode_fns, 0, 0 },
+ { "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
+ 0,
+ Opcode_ae_srlsp24_encode_fns, 0, 0 },
+ { "ae_srasp24", ICLASS_ae_iclass_srasp24,
+ 0,
+ Opcode_ae_srasp24_encode_fns, 0, 0 },
+ { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
+ 0,
+ Opcode_ae_sllisp24s_encode_fns, 0, 0 },
+ { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
+ 0,
+ Opcode_ae_sllssp24s_encode_fns, 0, 0 },
+ { "ae_slliq56", ICLASS_ae_iclass_slliq56,
+ 0,
+ Opcode_ae_slliq56_encode_fns, 0, 0 },
+ { "ae_srliq56", ICLASS_ae_iclass_srliq56,
+ 0,
+ Opcode_ae_srliq56_encode_fns, 0, 0 },
+ { "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
+ 0,
+ Opcode_ae_sraiq56_encode_fns, 0, 0 },
+ { "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
+ 0,
+ Opcode_ae_sllsq56_encode_fns, 0, 0 },
+ { "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
+ 0,
+ Opcode_ae_srlsq56_encode_fns, 0, 0 },
+ { "ae_srasq56", ICLASS_ae_iclass_srasq56,
+ 0,
+ Opcode_ae_srasq56_encode_fns, 0, 0 },
+ { "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
+ 0,
+ Opcode_ae_sllaq56_encode_fns, 0, 0 },
+ { "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
+ 0,
+ Opcode_ae_srlaq56_encode_fns, 0, 0 },
+ { "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
+ 0,
+ Opcode_ae_sraaq56_encode_fns, 0, 0 },
+ { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
+ 0,
+ Opcode_ae_sllisq56s_encode_fns, 0, 0 },
+ { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
+ 0,
+ Opcode_ae_sllssq56s_encode_fns, 0, 0 },
+ { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
+ 0,
+ Opcode_ae_sllasq56s_encode_fns, 0, 0 },
+ { "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
+ 0,
+ Opcode_ae_ltq56s_encode_fns, 0, 0 },
+ { "ae_leq56s", ICLASS_ae_iclass_leq56s,
+ 0,
+ Opcode_ae_leq56s_encode_fns, 0, 0 },
+ { "ae_eqq56", ICLASS_ae_iclass_eqq56,
+ 0,
+ Opcode_ae_eqq56_encode_fns, 0, 0 },
+ { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
+ 0,
+ Opcode_ae_nsaq56s_encode_fns, 0, 0 },
+ { "ae_mulsrfq32sp24s.h", ICLASS_ae_iclass_mulsrfq32sp24s_h,
+ 0,
+ Opcode_ae_mulsrfq32sp24s_h_encode_fns, 0, 0 },
+ { "ae_mulsrfq32sp24s.l", ICLASS_ae_iclass_mulsrfq32sp24s_l,
+ 0,
+ Opcode_ae_mulsrfq32sp24s_l_encode_fns, 0, 0 },
+ { "ae_mularfq32sp24s.h", ICLASS_ae_iclass_mularfq32sp24s_h,
+ 0,
+ Opcode_ae_mularfq32sp24s_h_encode_fns, 0, 0 },
+ { "ae_mularfq32sp24s.l", ICLASS_ae_iclass_mularfq32sp24s_l,
+ 0,
+ Opcode_ae_mularfq32sp24s_l_encode_fns, 0, 0 },
+ { "ae_mulrfq32sp24s.h", ICLASS_ae_iclass_mulrfq32sp24s_h,
+ 0,
+ Opcode_ae_mulrfq32sp24s_h_encode_fns, 0, 0 },
+ { "ae_mulrfq32sp24s.l", ICLASS_ae_iclass_mulrfq32sp24s_l,
+ 0,
+ Opcode_ae_mulrfq32sp24s_l_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp24s.h", ICLASS_ae_iclass_mulsfq32sp24s_h,
+ 0,
+ Opcode_ae_mulsfq32sp24s_h_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp24s.l", ICLASS_ae_iclass_mulsfq32sp24s_l,
+ 0,
+ Opcode_ae_mulsfq32sp24s_l_encode_fns, 0, 0 },
+ { "ae_mulafq32sp24s.h", ICLASS_ae_iclass_mulafq32sp24s_h,
+ 0,
+ Opcode_ae_mulafq32sp24s_h_encode_fns, 0, 0 },
+ { "ae_mulafq32sp24s.l", ICLASS_ae_iclass_mulafq32sp24s_l,
+ 0,
+ Opcode_ae_mulafq32sp24s_l_encode_fns, 0, 0 },
+ { "ae_mulfq32sp24s.h", ICLASS_ae_iclass_mulfq32sp24s_h,
+ 0,
+ Opcode_ae_mulfq32sp24s_h_encode_fns, 0, 0 },
+ { "ae_mulfq32sp24s.l", ICLASS_ae_iclass_mulfq32sp24s_l,
+ 0,
+ Opcode_ae_mulfq32sp24s_l_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
+ 0,
+ Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
+ { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
+ 0,
+ Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
+ 0,
+ Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
+ 0,
+ Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
+ { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
+ 0,
+ Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
+ 0,
+ Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
+ 0,
+ Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
+ { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
+ 0,
+ Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
+ 0,
+ Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
+ 0,
+ Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
+ { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
+ 0,
+ Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
+ 0,
+ Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
+ 0,
+ Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
+ { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
+ 0,
+ Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
+ 0,
+ Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
+ 0,
+ Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
+ { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
+ 0,
+ Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
+ 0,
+ Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
+ 0,
+ Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
+ { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
+ 0,
+ Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
+ 0,
+ Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
+ 0,
+ Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
+ { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
+ 0,
+ Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
+ 0,
+ Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
+ 0,
+ Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
+ 0,
+ Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
+ 0,
+ Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
+ 0,
+ Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
+ 0,
+ Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
+ 0,
+ Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
+ 0,
+ Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
+ 0,
+ Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
+ 0,
+ Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
+ 0,
+ Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
+ 0,
+ Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
+ 0,
+ Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
+ 0,
+ Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
+ 0,
+ Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
+ 0,
+ Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
+ 0,
+ Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
+ 0,
+ Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
+ 0,
+ Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
+ 0,
+ Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
+ 0,
+ Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
+ 0,
+ Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
+ 0,
+ Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
+ 0,
+ Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
+ 0,
+ Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
+ 0,
+ Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
+ 0,
+ Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
+ 0,
+ Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
+ 0,
+ Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
+ 0,
+ Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
+ 0,
+ Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
+ 0,
+ Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
+ 0,
+ Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
+ 0,
+ Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
+ 0,
+ Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
+ 0,
+ Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
+ 0,
+ Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
+ 0,
+ Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
+ 0,
+ Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
+ 0,
+ Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
+ 0,
+ Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
+ 0,
+ Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
+ 0,
+ Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
+ 0,
+ Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
+ 0,
+ Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
+ 0,
+ Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
+ 0,
+ Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
+ 0,
+ Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
+ 0,
+ Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
+ 0,
+ Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
+ 0,
+ Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
+ 0,
+ Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
+ 0,
+ Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
+ 0,
+ Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
+ 0,
+ Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
+ 0,
+ Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
+ 0,
+ Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
+ 0,
+ Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
+ 0,
+ Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
+ 0,
+ Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
+ 0,
+ Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
+ 0,
+ Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
+ 0,
+ Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
+ 0,
+ Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
+ 0,
+ Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_sha32", ICLASS_ae_iclass_sha32,
+ 0,
+ Opcode_ae_sha32_encode_fns, 0, 0 },
+ { "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
+ 0,
+ Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
+ { "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
+ 0,
+ Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
+ { "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
+ 0,
+ Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
+ { "ae_vldsht", ICLASS_ae_iclass_vldsht,
+ 0,
+ Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
+ { "ae_lb", ICLASS_ae_iclass_lb,
+ 0,
+ Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
+ { "ae_lbi", ICLASS_ae_iclass_lbi,
+ 0,
+ Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
+ { "ae_lbk", ICLASS_ae_iclass_lbk,
+ 0,
+ Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
+ { "ae_lbki", ICLASS_ae_iclass_lbki,
+ 0,
+ Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
+ { "ae_db", ICLASS_ae_iclass_db,
+ 0,
+ Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
+ { "ae_dbi", ICLASS_ae_iclass_dbi,
+ 0,
+ Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
+ { "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
+ 0,
+ Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
+ { "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
+ 0,
+ Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
+ { "ae_sb", ICLASS_ae_iclass_sb,
+ 0,
+ Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
+ { "ae_sbi", ICLASS_ae_iclass_sbi,
+ 0,
+ Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
+ { "ae_vles16c", ICLASS_ae_iclass_vles16c,
+ 0,
+ Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
+ { "ae_sbf", ICLASS_ae_iclass_sbf,
+ 0,
+ Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses },
+ { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S,
+ 0,
+ Opcode_ae_slaasq56s_encode_fns, 0, 0 },
+ { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32,
+ 0,
+ Opcode_ae_addbrba32_encode_fns, 0, 0 },
+ { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S,
+ 0,
+ Opcode_ae_minabssp24s_encode_fns, 0, 0 },
+ { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S,
+ 0,
+ Opcode_ae_maxabssp24s_encode_fns, 0, 0 },
+ { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S,
+ 0,
+ Opcode_ae_minabssq56s_encode_fns, 0, 0 },
+ { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S,
+ 0,
+ Opcode_ae_maxabssq56s_encode_fns, 0, 0 },
+ { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0,
+ 0,
+ Opcode_rur_ae_cbegin0_encode_fns, 0, 0 },
+ { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0,
+ 0,
+ Opcode_wur_ae_cbegin0_encode_fns, 0, 0 },
+ { "rur.ae_cend0", ICLASS_rur_ae_cend0,
+ 0,
+ Opcode_rur_ae_cend0_encode_fns, 0, 0 },
+ { "wur.ae_cend0", ICLASS_wur_ae_cend0,
+ 0,
+ Opcode_wur_ae_cend0_encode_fns, 0, 0 },
+ { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C,
+ 0,
+ Opcode_ae_lp24x2_c_encode_fns, 0, 0 },
+ { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C,
+ 0,
+ Opcode_ae_sp24x2s_c_encode_fns, 0, 0 },
+ { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C,
+ 0,
+ Opcode_ae_lp24x2f_c_encode_fns, 0, 0 },
+ { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C,
+ 0,
+ Opcode_ae_sp24x2f_c_encode_fns, 0, 0 },
+ { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C,
+ 0,
+ Opcode_ae_lp16x2f_c_encode_fns, 0, 0 },
+ { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C,
+ 0,
+ Opcode_ae_sp16x2f_c_encode_fns, 0, 0 },
+ { "ae_lp24.c", ICLASS_icls_AE_LP24_C,
+ 0,
+ Opcode_ae_lp24_c_encode_fns, 0, 0 },
+ { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C,
+ 0,
+ Opcode_ae_sp24s_l_c_encode_fns, 0, 0 },
+ { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C,
+ 0,
+ Opcode_ae_lp24f_c_encode_fns, 0, 0 },
+ { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C,
+ 0,
+ Opcode_ae_sp24f_l_c_encode_fns, 0, 0 },
+ { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C,
+ 0,
+ Opcode_ae_lp16f_c_encode_fns, 0, 0 },
+ { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C,
+ 0,
+ Opcode_ae_sp16f_l_c_encode_fns, 0, 0 },
+ { "ae_lq56.c", ICLASS_icls_AE_LQ56_C,
+ 0,
+ Opcode_ae_lq56_c_encode_fns, 0, 0 },
+ { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C,
+ 0,
+ Opcode_ae_sq56s_c_encode_fns, 0, 0 },
+ { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C,
+ 0,
+ Opcode_ae_lq32f_c_encode_fns, 0, 0 },
+ { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C,
+ 0,
+ Opcode_ae_sq32f_c_encode_fns, 0, 0 },
+ { "rur.expstate", ICLASS_rur_expstate,
+ 0,
+ Opcode_rur_expstate_encode_fns, 0, 0 },
+ { "wur.expstate", ICLASS_wur_expstate,
+ 0,
+ Opcode_wur_expstate_encode_fns, 0, 0 },
+ { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+ 0,
+ Opcode_read_impwire_encode_fns, 0, 0 },
+ { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+ 0,
+ Opcode_setb_expstate_encode_fns, 0, 0 },
+ { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+ 0,
+ Opcode_clrb_expstate_encode_fns, 0, 0 },
+ { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+ 0,
+ Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_RUR_THREADPTR,
+ OPCODE_WUR_THREADPTR,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_LOOP,
+ OPCODE_LOOPNEZ,
+ OPCODE_LOOPGTZ,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_SIMCALL,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S32NB,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_LEND,
+ OPCODE_WSR_LEND,
+ OPCODE_XSR_LEND,
+ OPCODE_RSR_LCOUNT,
+ OPCODE_WSR_LCOUNT,
+ OPCODE_XSR_LCOUNT,
+ OPCODE_RSR_LBEG,
+ OPCODE_WSR_LBEG,
+ OPCODE_XSR_LBEG,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_MEMCTL,
+ OPCODE_WSR_MEMCTL,
+ OPCODE_XSR_MEMCTL,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_CONFIGID0,
+ OPCODE_WSR_CONFIGID0,
+ OPCODE_RSR_CONFIGID1,
+ OPCODE_RSR_243,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPC3,
+ OPCODE_WSR_EPC3,
+ OPCODE_XSR_EPC3,
+ OPCODE_RSR_EXCSAVE3,
+ OPCODE_WSR_EXCSAVE3,
+ OPCODE_XSR_EXCSAVE3,
+ OPCODE_RSR_EPC4,
+ OPCODE_WSR_EPC4,
+ OPCODE_XSR_EPC4,
+ OPCODE_RSR_EXCSAVE4,
+ OPCODE_WSR_EXCSAVE4,
+ OPCODE_XSR_EXCSAVE4,
+ OPCODE_RSR_EPC5,
+ OPCODE_WSR_EPC5,
+ OPCODE_XSR_EPC5,
+ OPCODE_RSR_EXCSAVE5,
+ OPCODE_WSR_EXCSAVE5,
+ OPCODE_XSR_EXCSAVE5,
+ OPCODE_RSR_EPC6,
+ OPCODE_WSR_EPC6,
+ OPCODE_XSR_EPC6,
+ OPCODE_RSR_EXCSAVE6,
+ OPCODE_WSR_EXCSAVE6,
+ OPCODE_XSR_EXCSAVE6,
+ OPCODE_RSR_EPC7,
+ OPCODE_WSR_EPC7,
+ OPCODE_XSR_EPC7,
+ OPCODE_RSR_EXCSAVE7,
+ OPCODE_WSR_EXCSAVE7,
+ OPCODE_XSR_EXCSAVE7,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EPS3,
+ OPCODE_WSR_EPS3,
+ OPCODE_XSR_EPS3,
+ OPCODE_RSR_EPS4,
+ OPCODE_WSR_EPS4,
+ OPCODE_XSR_EPS4,
+ OPCODE_RSR_EPS5,
+ OPCODE_WSR_EPS5,
+ OPCODE_XSR_EPS5,
+ OPCODE_RSR_EPS6,
+ OPCODE_WSR_EPS6,
+ OPCODE_XSR_EPS6,
+ OPCODE_RSR_EPS7,
+ OPCODE_WSR_EPS7,
+ OPCODE_XSR_EPS7,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_MULUH,
+ OPCODE_MULSH,
+ OPCODE_MUL_AA_LL,
+ OPCODE_MUL_AA_HL,
+ OPCODE_MUL_AA_LH,
+ OPCODE_MUL_AA_HH,
+ OPCODE_UMUL_AA_LL,
+ OPCODE_UMUL_AA_HL,
+ OPCODE_UMUL_AA_LH,
+ OPCODE_UMUL_AA_HH,
+ OPCODE_MUL_AD_LL,
+ OPCODE_MUL_AD_HL,
+ OPCODE_MUL_AD_LH,
+ OPCODE_MUL_AD_HH,
+ OPCODE_MUL_DA_LL,
+ OPCODE_MUL_DA_HL,
+ OPCODE_MUL_DA_LH,
+ OPCODE_MUL_DA_HH,
+ OPCODE_MUL_DD_LL,
+ OPCODE_MUL_DD_HL,
+ OPCODE_MUL_DD_LH,
+ OPCODE_MUL_DD_HH,
+ OPCODE_MULA_AA_LL,
+ OPCODE_MULA_AA_HL,
+ OPCODE_MULA_AA_LH,
+ OPCODE_MULA_AA_HH,
+ OPCODE_MULS_AA_LL,
+ OPCODE_MULS_AA_HL,
+ OPCODE_MULS_AA_LH,
+ OPCODE_MULS_AA_HH,
+ OPCODE_MULA_AD_LL,
+ OPCODE_MULA_AD_HL,
+ OPCODE_MULA_AD_LH,
+ OPCODE_MULA_AD_HH,
+ OPCODE_MULS_AD_LL,
+ OPCODE_MULS_AD_HL,
+ OPCODE_MULS_AD_LH,
+ OPCODE_MULS_AD_HH,
+ OPCODE_MULA_DA_LL,
+ OPCODE_MULA_DA_HL,
+ OPCODE_MULA_DA_LH,
+ OPCODE_MULA_DA_HH,
+ OPCODE_MULS_DA_LL,
+ OPCODE_MULS_DA_HL,
+ OPCODE_MULS_DA_LH,
+ OPCODE_MULS_DA_HH,
+ OPCODE_MULA_DD_LL,
+ OPCODE_MULA_DD_HL,
+ OPCODE_MULA_DD_LH,
+ OPCODE_MULA_DD_HH,
+ OPCODE_MULS_DD_LL,
+ OPCODE_MULS_DD_HL,
+ OPCODE_MULS_DD_LH,
+ OPCODE_MULS_DD_HH,
+ OPCODE_MULA_DA_LL_LDDEC,
+ OPCODE_MULA_DA_LL_LDINC,
+ OPCODE_MULA_DA_HL_LDDEC,
+ OPCODE_MULA_DA_HL_LDINC,
+ OPCODE_MULA_DA_LH_LDDEC,
+ OPCODE_MULA_DA_LH_LDINC,
+ OPCODE_MULA_DA_HH_LDDEC,
+ OPCODE_MULA_DA_HH_LDINC,
+ OPCODE_MULA_DD_LL_LDDEC,
+ OPCODE_MULA_DD_LL_LDINC,
+ OPCODE_MULA_DD_HL_LDDEC,
+ OPCODE_MULA_DD_HL_LDINC,
+ OPCODE_MULA_DD_LH_LDDEC,
+ OPCODE_MULA_DD_LH_LDINC,
+ OPCODE_MULA_DD_HH_LDDEC,
+ OPCODE_MULA_DD_HH_LDINC,
+ OPCODE_LDDEC,
+ OPCODE_LDINC,
+ OPCODE_RSR_M0,
+ OPCODE_WSR_M0,
+ OPCODE_XSR_M0,
+ OPCODE_RSR_M1,
+ OPCODE_WSR_M1,
+ OPCODE_XSR_M1,
+ OPCODE_RSR_M2,
+ OPCODE_WSR_M2,
+ OPCODE_XSR_M2,
+ OPCODE_RSR_M3,
+ OPCODE_WSR_M3,
+ OPCODE_XSR_M3,
+ OPCODE_RSR_ACCLO,
+ OPCODE_WSR_ACCLO,
+ OPCODE_XSR_ACCLO,
+ OPCODE_RSR_ACCHI,
+ OPCODE_WSR_ACCHI,
+ OPCODE_XSR_ACCHI,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DBREAKA0,
+ OPCODE_WSR_DBREAKA0,
+ OPCODE_XSR_DBREAKA0,
+ OPCODE_RSR_DBREAKC0,
+ OPCODE_WSR_DBREAKC0,
+ OPCODE_XSR_DBREAKC0,
+ OPCODE_RSR_DBREAKA1,
+ OPCODE_WSR_DBREAKA1,
+ OPCODE_XSR_DBREAKA1,
+ OPCODE_RSR_DBREAKC1,
+ OPCODE_WSR_DBREAKC1,
+ OPCODE_XSR_DBREAKC1,
+ OPCODE_RSR_IBREAKA0,
+ OPCODE_WSR_IBREAKA0,
+ OPCODE_XSR_IBREAKA0,
+ OPCODE_RSR_IBREAKA1,
+ OPCODE_WSR_IBREAKA1,
+ OPCODE_XSR_IBREAKA1,
+ OPCODE_RSR_IBREAKENABLE,
+ OPCODE_WSR_IBREAKENABLE,
+ OPCODE_XSR_IBREAKENABLE,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_LDDR32_P,
+ OPCODE_SDDR32_P,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_WSR_MMID,
+ OPCODE_ANDB,
+ OPCODE_ANDBC,
+ OPCODE_ORB,
+ OPCODE_ORBC,
+ OPCODE_XORB,
+ OPCODE_ANY4,
+ OPCODE_ALL4,
+ OPCODE_ANY8,
+ OPCODE_ALL8,
+ OPCODE_BF,
+ OPCODE_BT,
+ OPCODE_MOVF,
+ OPCODE_MOVT,
+ OPCODE_RSR_BR,
+ OPCODE_WSR_BR,
+ OPCODE_XSR_BR,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_RSR_CCOMPARE2,
+ OPCODE_WSR_CCOMPARE2,
+ OPCODE_XSR_CCOMPARE2,
+ OPCODE_IPF,
+ OPCODE_IHI,
+ OPCODE_IPFL,
+ OPCODE_IHU,
+ OPCODE_IIU,
+ OPCODE_III,
+ OPCODE_LICT,
+ OPCODE_LICW,
+ OPCODE_SICT,
+ OPCODE_SICW,
+ OPCODE_DHWB,
+ OPCODE_DHWBI,
+ OPCODE_DIWBUI_P,
+ OPCODE_DIWB,
+ OPCODE_DIWBI,
+ OPCODE_DHI,
+ OPCODE_DII,
+ OPCODE_DPFR,
+ OPCODE_DPFW,
+ OPCODE_DPFRO,
+ OPCODE_DPFWO,
+ OPCODE_DPFL,
+ OPCODE_DHU,
+ OPCODE_DIU,
+ OPCODE_SDCT,
+ OPCODE_LDCT,
+ OPCODE_RSR_PREFCTL,
+ OPCODE_WSR_PREFCTL,
+ OPCODE_XSR_PREFCTL,
+ OPCODE_WSR_PTEVADDR,
+ OPCODE_RSR_PTEVADDR,
+ OPCODE_XSR_PTEVADDR,
+ OPCODE_RSR_RASID,
+ OPCODE_WSR_RASID,
+ OPCODE_XSR_RASID,
+ OPCODE_RSR_ITLBCFG,
+ OPCODE_WSR_ITLBCFG,
+ OPCODE_XSR_ITLBCFG,
+ OPCODE_RSR_DTLBCFG,
+ OPCODE_WSR_DTLBCFG,
+ OPCODE_XSR_DTLBCFG,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_LDPTE,
+ OPCODE_HWWITLBA,
+ OPCODE_HWWDTLBA,
+ OPCODE_RSR_CPENABLE,
+ OPCODE_WSR_CPENABLE,
+ OPCODE_XSR_CPENABLE,
+ OPCODE_CLAMPS,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_QUOU,
+ OPCODE_QUOS,
+ OPCODE_REMU,
+ OPCODE_REMS,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_AE_OVF_SAR,
+ OPCODE_WUR_AE_OVF_SAR,
+ OPCODE_RUR_AE_BITHEAD,
+ OPCODE_WUR_AE_BITHEAD,
+ OPCODE_RUR_AE_TS_FTS_BU_BP,
+ OPCODE_WUR_AE_TS_FTS_BU_BP,
+ OPCODE_RUR_AE_SD_NO,
+ OPCODE_WUR_AE_SD_NO,
+ OPCODE_RUR_AE_OVERFLOW,
+ OPCODE_WUR_AE_OVERFLOW,
+ OPCODE_RUR_AE_SAR,
+ OPCODE_WUR_AE_SAR,
+ OPCODE_RUR_AE_BITPTR,
+ OPCODE_WUR_AE_BITPTR,
+ OPCODE_RUR_AE_BITSUSED,
+ OPCODE_WUR_AE_BITSUSED,
+ OPCODE_RUR_AE_TABLESIZE,
+ OPCODE_WUR_AE_TABLESIZE,
+ OPCODE_RUR_AE_FIRST_TS,
+ OPCODE_WUR_AE_FIRST_TS,
+ OPCODE_RUR_AE_NEXTOFFSET,
+ OPCODE_WUR_AE_NEXTOFFSET,
+ OPCODE_RUR_AE_SEARCHDONE,
+ OPCODE_WUR_AE_SEARCHDONE,
+ OPCODE_AE_LP16F_I,
+ OPCODE_AE_LP16F_IU,
+ OPCODE_AE_LP16F_X,
+ OPCODE_AE_LP16F_XU,
+ OPCODE_AE_LP24_I,
+ OPCODE_AE_LP24_IU,
+ OPCODE_AE_LP24_X,
+ OPCODE_AE_LP24_XU,
+ OPCODE_AE_LP24F_I,
+ OPCODE_AE_LP24F_IU,
+ OPCODE_AE_LP24F_X,
+ OPCODE_AE_LP24F_XU,
+ OPCODE_AE_LP16X2F_I,
+ OPCODE_AE_LP16X2F_IU,
+ OPCODE_AE_LP16X2F_X,
+ OPCODE_AE_LP16X2F_XU,
+ OPCODE_AE_LP24X2F_I,
+ OPCODE_AE_LP24X2F_IU,
+ OPCODE_AE_LP24X2F_X,
+ OPCODE_AE_LP24X2F_XU,
+ OPCODE_AE_LP24X2_I,
+ OPCODE_AE_LP24X2_IU,
+ OPCODE_AE_LP24X2_X,
+ OPCODE_AE_LP24X2_XU,
+ OPCODE_AE_SP16X2F_I,
+ OPCODE_AE_SP16X2F_IU,
+ OPCODE_AE_SP16X2F_X,
+ OPCODE_AE_SP16X2F_XU,
+ OPCODE_AE_SP24X2S_I,
+ OPCODE_AE_SP24X2S_IU,
+ OPCODE_AE_SP24X2S_X,
+ OPCODE_AE_SP24X2S_XU,
+ OPCODE_AE_SP24X2F_I,
+ OPCODE_AE_SP24X2F_IU,
+ OPCODE_AE_SP24X2F_X,
+ OPCODE_AE_SP24X2F_XU,
+ OPCODE_AE_SP16F_L_I,
+ OPCODE_AE_SP16F_L_IU,
+ OPCODE_AE_SP16F_L_X,
+ OPCODE_AE_SP16F_L_XU,
+ OPCODE_AE_SP24S_L_I,
+ OPCODE_AE_SP24S_L_IU,
+ OPCODE_AE_SP24S_L_X,
+ OPCODE_AE_SP24S_L_XU,
+ OPCODE_AE_SP24F_L_I,
+ OPCODE_AE_SP24F_L_IU,
+ OPCODE_AE_SP24F_L_X,
+ OPCODE_AE_SP24F_L_XU,
+ OPCODE_AE_LQ56_I,
+ OPCODE_AE_LQ56_IU,
+ OPCODE_AE_LQ56_X,
+ OPCODE_AE_LQ56_XU,
+ OPCODE_AE_LQ32F_I,
+ OPCODE_AE_LQ32F_IU,
+ OPCODE_AE_LQ32F_X,
+ OPCODE_AE_LQ32F_XU,
+ OPCODE_AE_SQ56S_I,
+ OPCODE_AE_SQ56S_IU,
+ OPCODE_AE_SQ56S_X,
+ OPCODE_AE_SQ56S_XU,
+ OPCODE_AE_SQ32F_I,
+ OPCODE_AE_SQ32F_IU,
+ OPCODE_AE_SQ32F_X,
+ OPCODE_AE_SQ32F_XU,
+ OPCODE_AE_ZEROP48,
+ OPCODE_AE_MOVP48,
+ OPCODE_AE_SELP24_LL,
+ OPCODE_AE_SELP24_LH,
+ OPCODE_AE_SELP24_HL,
+ OPCODE_AE_SELP24_HH,
+ OPCODE_AE_MOVTP24X2,
+ OPCODE_AE_MOVFP24X2,
+ OPCODE_AE_MOVTP48,
+ OPCODE_AE_MOVFP48,
+ OPCODE_AE_MOVPA24X2,
+ OPCODE_AE_TRUNCP24A32X2,
+ OPCODE_AE_CVTA32P24_L,
+ OPCODE_AE_CVTA32P24_H,
+ OPCODE_AE_CVTP24A16X2_LL,
+ OPCODE_AE_CVTP24A16X2_LH,
+ OPCODE_AE_CVTP24A16X2_HL,
+ OPCODE_AE_CVTP24A16X2_HH,
+ OPCODE_AE_TRUNCP24Q48X2,
+ OPCODE_AE_TRUNCP16,
+ OPCODE_AE_ROUNDSP24Q48SYM,
+ OPCODE_AE_ROUNDSP24Q48ASYM,
+ OPCODE_AE_ROUNDSP16Q48SYM,
+ OPCODE_AE_ROUNDSP16Q48ASYM,
+ OPCODE_AE_ROUNDSP16SYM,
+ OPCODE_AE_ROUNDSP16ASYM,
+ OPCODE_AE_ZEROQ56,
+ OPCODE_AE_MOVQ56,
+ OPCODE_AE_MOVTQ56,
+ OPCODE_AE_MOVFQ56,
+ OPCODE_AE_CVTQ48A32S,
+ OPCODE_AE_CVTQ48P24S_L,
+ OPCODE_AE_CVTQ48P24S_H,
+ OPCODE_AE_SATQ48S,
+ OPCODE_AE_TRUNCQ32,
+ OPCODE_AE_ROUNDSQ32SYM,
+ OPCODE_AE_ROUNDSQ32ASYM,
+ OPCODE_AE_TRUNCA32Q48,
+ OPCODE_AE_MOVAP24S_L,
+ OPCODE_AE_MOVAP24S_H,
+ OPCODE_AE_TRUNCA16P24S_L,
+ OPCODE_AE_TRUNCA16P24S_H,
+ OPCODE_AE_ADDP24,
+ OPCODE_AE_SUBP24,
+ OPCODE_AE_NEGP24,
+ OPCODE_AE_ABSP24,
+ OPCODE_AE_MAXP24S,
+ OPCODE_AE_MINP24S,
+ OPCODE_AE_MAXBP24S,
+ OPCODE_AE_MINBP24S,
+ OPCODE_AE_ADDSP24S,
+ OPCODE_AE_SUBSP24S,
+ OPCODE_AE_NEGSP24S,
+ OPCODE_AE_ABSSP24S,
+ OPCODE_AE_ANDP48,
+ OPCODE_AE_NANDP48,
+ OPCODE_AE_ORP48,
+ OPCODE_AE_XORP48,
+ OPCODE_AE_LTP24S,
+ OPCODE_AE_LEP24S,
+ OPCODE_AE_EQP24,
+ OPCODE_AE_ADDQ56,
+ OPCODE_AE_SUBQ56,
+ OPCODE_AE_NEGQ56,
+ OPCODE_AE_ABSQ56,
+ OPCODE_AE_MAXQ56S,
+ OPCODE_AE_MINQ56S,
+ OPCODE_AE_MAXBQ56S,
+ OPCODE_AE_MINBQ56S,
+ OPCODE_AE_ADDSQ56S,
+ OPCODE_AE_SUBSQ56S,
+ OPCODE_AE_NEGSQ56S,
+ OPCODE_AE_ABSSQ56S,
+ OPCODE_AE_ANDQ56,
+ OPCODE_AE_NANDQ56,
+ OPCODE_AE_ORQ56,
+ OPCODE_AE_XORQ56,
+ OPCODE_AE_SLLIP24,
+ OPCODE_AE_SRLIP24,
+ OPCODE_AE_SRAIP24,
+ OPCODE_AE_SLLSP24,
+ OPCODE_AE_SRLSP24,
+ OPCODE_AE_SRASP24,
+ OPCODE_AE_SLLISP24S,
+ OPCODE_AE_SLLSSP24S,
+ OPCODE_AE_SLLIQ56,
+ OPCODE_AE_SRLIQ56,
+ OPCODE_AE_SRAIQ56,
+ OPCODE_AE_SLLSQ56,
+ OPCODE_AE_SRLSQ56,
+ OPCODE_AE_SRASQ56,
+ OPCODE_AE_SLLAQ56,
+ OPCODE_AE_SRLAQ56,
+ OPCODE_AE_SRAAQ56,
+ OPCODE_AE_SLLISQ56S,
+ OPCODE_AE_SLLSSQ56S,
+ OPCODE_AE_SLLASQ56S,
+ OPCODE_AE_LTQ56S,
+ OPCODE_AE_LEQ56S,
+ OPCODE_AE_EQQ56,
+ OPCODE_AE_NSAQ56S,
+ OPCODE_AE_MULSRFQ32SP24S_H,
+ OPCODE_AE_MULSRFQ32SP24S_L,
+ OPCODE_AE_MULARFQ32SP24S_H,
+ OPCODE_AE_MULARFQ32SP24S_L,
+ OPCODE_AE_MULRFQ32SP24S_H,
+ OPCODE_AE_MULRFQ32SP24S_L,
+ OPCODE_AE_MULSFQ32SP24S_H,
+ OPCODE_AE_MULSFQ32SP24S_L,
+ OPCODE_AE_MULAFQ32SP24S_H,
+ OPCODE_AE_MULAFQ32SP24S_L,
+ OPCODE_AE_MULFQ32SP24S_H,
+ OPCODE_AE_MULFQ32SP24S_L,
+ OPCODE_AE_MULFS32P16S_LL,
+ OPCODE_AE_MULFP24S_LL,
+ OPCODE_AE_MULP24S_LL,
+ OPCODE_AE_MULFS32P16S_LH,
+ OPCODE_AE_MULFP24S_LH,
+ OPCODE_AE_MULP24S_LH,
+ OPCODE_AE_MULFS32P16S_HL,
+ OPCODE_AE_MULFP24S_HL,
+ OPCODE_AE_MULP24S_HL,
+ OPCODE_AE_MULFS32P16S_HH,
+ OPCODE_AE_MULFP24S_HH,
+ OPCODE_AE_MULP24S_HH,
+ OPCODE_AE_MULAFS32P16S_LL,
+ OPCODE_AE_MULAFP24S_LL,
+ OPCODE_AE_MULAP24S_LL,
+ OPCODE_AE_MULAFS32P16S_LH,
+ OPCODE_AE_MULAFP24S_LH,
+ OPCODE_AE_MULAP24S_LH,
+ OPCODE_AE_MULAFS32P16S_HL,
+ OPCODE_AE_MULAFP24S_HL,
+ OPCODE_AE_MULAP24S_HL,
+ OPCODE_AE_MULAFS32P16S_HH,
+ OPCODE_AE_MULAFP24S_HH,
+ OPCODE_AE_MULAP24S_HH,
+ OPCODE_AE_MULSFS32P16S_LL,
+ OPCODE_AE_MULSFP24S_LL,
+ OPCODE_AE_MULSP24S_LL,
+ OPCODE_AE_MULSFS32P16S_LH,
+ OPCODE_AE_MULSFP24S_LH,
+ OPCODE_AE_MULSP24S_LH,
+ OPCODE_AE_MULSFS32P16S_HL,
+ OPCODE_AE_MULSFP24S_HL,
+ OPCODE_AE_MULSP24S_HL,
+ OPCODE_AE_MULSFS32P16S_HH,
+ OPCODE_AE_MULSFP24S_HH,
+ OPCODE_AE_MULSP24S_HH,
+ OPCODE_AE_MULAFS56P24S_LL,
+ OPCODE_AE_MULAS56P24S_LL,
+ OPCODE_AE_MULAFS56P24S_LH,
+ OPCODE_AE_MULAS56P24S_LH,
+ OPCODE_AE_MULAFS56P24S_HL,
+ OPCODE_AE_MULAS56P24S_HL,
+ OPCODE_AE_MULAFS56P24S_HH,
+ OPCODE_AE_MULAS56P24S_HH,
+ OPCODE_AE_MULSFS56P24S_LL,
+ OPCODE_AE_MULSS56P24S_LL,
+ OPCODE_AE_MULSFS56P24S_LH,
+ OPCODE_AE_MULSS56P24S_LH,
+ OPCODE_AE_MULSFS56P24S_HL,
+ OPCODE_AE_MULSS56P24S_HL,
+ OPCODE_AE_MULSFS56P24S_HH,
+ OPCODE_AE_MULSS56P24S_HH,
+ OPCODE_AE_MULFQ32SP16S_L,
+ OPCODE_AE_MULFQ32SP16S_H,
+ OPCODE_AE_MULFQ32SP16U_L,
+ OPCODE_AE_MULFQ32SP16U_H,
+ OPCODE_AE_MULQ32SP16S_L,
+ OPCODE_AE_MULQ32SP16S_H,
+ OPCODE_AE_MULQ32SP16U_L,
+ OPCODE_AE_MULQ32SP16U_H,
+ OPCODE_AE_MULAFQ32SP16S_L,
+ OPCODE_AE_MULAFQ32SP16S_H,
+ OPCODE_AE_MULAFQ32SP16U_L,
+ OPCODE_AE_MULAFQ32SP16U_H,
+ OPCODE_AE_MULAQ32SP16S_L,
+ OPCODE_AE_MULAQ32SP16S_H,
+ OPCODE_AE_MULAQ32SP16U_L,
+ OPCODE_AE_MULAQ32SP16U_H,
+ OPCODE_AE_MULSFQ32SP16S_L,
+ OPCODE_AE_MULSFQ32SP16S_H,
+ OPCODE_AE_MULSFQ32SP16U_L,
+ OPCODE_AE_MULSFQ32SP16U_H,
+ OPCODE_AE_MULSQ32SP16S_L,
+ OPCODE_AE_MULSQ32SP16S_H,
+ OPCODE_AE_MULSQ32SP16U_L,
+ OPCODE_AE_MULSQ32SP16U_H,
+ OPCODE_AE_MULZAAQ32SP16S_LL,
+ OPCODE_AE_MULZAAFQ32SP16S_LL,
+ OPCODE_AE_MULZAAQ32SP16U_LL,
+ OPCODE_AE_MULZAAFQ32SP16U_LL,
+ OPCODE_AE_MULZAAQ32SP16S_HH,
+ OPCODE_AE_MULZAAFQ32SP16S_HH,
+ OPCODE_AE_MULZAAQ32SP16U_HH,
+ OPCODE_AE_MULZAAFQ32SP16U_HH,
+ OPCODE_AE_MULZAAQ32SP16S_LH,
+ OPCODE_AE_MULZAAFQ32SP16S_LH,
+ OPCODE_AE_MULZAAQ32SP16U_LH,
+ OPCODE_AE_MULZAAFQ32SP16U_LH,
+ OPCODE_AE_MULZASQ32SP16S_LL,
+ OPCODE_AE_MULZASFQ32SP16S_LL,
+ OPCODE_AE_MULZASQ32SP16U_LL,
+ OPCODE_AE_MULZASFQ32SP16U_LL,
+ OPCODE_AE_MULZASQ32SP16S_HH,
+ OPCODE_AE_MULZASFQ32SP16S_HH,
+ OPCODE_AE_MULZASQ32SP16U_HH,
+ OPCODE_AE_MULZASFQ32SP16U_HH,
+ OPCODE_AE_MULZASQ32SP16S_LH,
+ OPCODE_AE_MULZASFQ32SP16S_LH,
+ OPCODE_AE_MULZASQ32SP16U_LH,
+ OPCODE_AE_MULZASFQ32SP16U_LH,
+ OPCODE_AE_MULZSAQ32SP16S_LL,
+ OPCODE_AE_MULZSAFQ32SP16S_LL,
+ OPCODE_AE_MULZSAQ32SP16U_LL,
+ OPCODE_AE_MULZSAFQ32SP16U_LL,
+ OPCODE_AE_MULZSAQ32SP16S_HH,
+ OPCODE_AE_MULZSAFQ32SP16S_HH,
+ OPCODE_AE_MULZSAQ32SP16U_HH,
+ OPCODE_AE_MULZSAFQ32SP16U_HH,
+ OPCODE_AE_MULZSAQ32SP16S_LH,
+ OPCODE_AE_MULZSAFQ32SP16S_LH,
+ OPCODE_AE_MULZSAQ32SP16U_LH,
+ OPCODE_AE_MULZSAFQ32SP16U_LH,
+ OPCODE_AE_MULZSSQ32SP16S_LL,
+ OPCODE_AE_MULZSSFQ32SP16S_LL,
+ OPCODE_AE_MULZSSQ32SP16U_LL,
+ OPCODE_AE_MULZSSFQ32SP16U_LL,
+ OPCODE_AE_MULZSSQ32SP16S_HH,
+ OPCODE_AE_MULZSSFQ32SP16S_HH,
+ OPCODE_AE_MULZSSQ32SP16U_HH,
+ OPCODE_AE_MULZSSFQ32SP16U_HH,
+ OPCODE_AE_MULZSSQ32SP16S_LH,
+ OPCODE_AE_MULZSSFQ32SP16S_LH,
+ OPCODE_AE_MULZSSQ32SP16U_LH,
+ OPCODE_AE_MULZSSFQ32SP16U_LH,
+ OPCODE_AE_MULZAAFP24S_HH_LL,
+ OPCODE_AE_MULZAAP24S_HH_LL,
+ OPCODE_AE_MULZAAFP24S_HL_LH,
+ OPCODE_AE_MULZAAP24S_HL_LH,
+ OPCODE_AE_MULZASFP24S_HH_LL,
+ OPCODE_AE_MULZASP24S_HH_LL,
+ OPCODE_AE_MULZASFP24S_HL_LH,
+ OPCODE_AE_MULZASP24S_HL_LH,
+ OPCODE_AE_MULZSAFP24S_HH_LL,
+ OPCODE_AE_MULZSAP24S_HH_LL,
+ OPCODE_AE_MULZSAFP24S_HL_LH,
+ OPCODE_AE_MULZSAP24S_HL_LH,
+ OPCODE_AE_MULZSSFP24S_HH_LL,
+ OPCODE_AE_MULZSSP24S_HH_LL,
+ OPCODE_AE_MULZSSFP24S_HL_LH,
+ OPCODE_AE_MULZSSP24S_HL_LH,
+ OPCODE_AE_MULAAFP24S_HH_LL,
+ OPCODE_AE_MULAAP24S_HH_LL,
+ OPCODE_AE_MULAAFP24S_HL_LH,
+ OPCODE_AE_MULAAP24S_HL_LH,
+ OPCODE_AE_MULASFP24S_HH_LL,
+ OPCODE_AE_MULASP24S_HH_LL,
+ OPCODE_AE_MULASFP24S_HL_LH,
+ OPCODE_AE_MULASP24S_HL_LH,
+ OPCODE_AE_MULSAFP24S_HH_LL,
+ OPCODE_AE_MULSAP24S_HH_LL,
+ OPCODE_AE_MULSAFP24S_HL_LH,
+ OPCODE_AE_MULSAP24S_HL_LH,
+ OPCODE_AE_MULSSFP24S_HH_LL,
+ OPCODE_AE_MULSSP24S_HH_LL,
+ OPCODE_AE_MULSSFP24S_HL_LH,
+ OPCODE_AE_MULSSP24S_HL_LH,
+ OPCODE_AE_SHA32,
+ OPCODE_AE_VLDL32T,
+ OPCODE_AE_VLDL16T,
+ OPCODE_AE_VLDL16C,
+ OPCODE_AE_VLDSHT,
+ OPCODE_AE_LB,
+ OPCODE_AE_LBI,
+ OPCODE_AE_LBK,
+ OPCODE_AE_LBKI,
+ OPCODE_AE_DB,
+ OPCODE_AE_DBI,
+ OPCODE_AE_VLEL32T,
+ OPCODE_AE_VLEL16T,
+ OPCODE_AE_SB,
+ OPCODE_AE_SBI,
+ OPCODE_AE_VLES16C,
+ OPCODE_AE_SBF,
+ OPCODE_AE_SLAASQ56S,
+ OPCODE_AE_ADDBRBA32,
+ OPCODE_AE_MINABSSP24S,
+ OPCODE_AE_MAXABSSP24S,
+ OPCODE_AE_MINABSSQ56S,
+ OPCODE_AE_MAXABSSQ56S,
+ OPCODE_RUR_AE_CBEGIN0,
+ OPCODE_WUR_AE_CBEGIN0,
+ OPCODE_RUR_AE_CEND0,
+ OPCODE_WUR_AE_CEND0,
+ OPCODE_AE_LP24X2_C,
+ OPCODE_AE_SP24X2S_C,
+ OPCODE_AE_LP24X2F_C,
+ OPCODE_AE_SP24X2F_C,
+ OPCODE_AE_LP16X2F_C,
+ OPCODE_AE_SP16X2F_C,
+ OPCODE_AE_LP24_C,
+ OPCODE_AE_SP24S_L_C,
+ OPCODE_AE_LP24F_C,
+ OPCODE_AE_SP24F_L_C,
+ OPCODE_AE_LP16F_C,
+ OPCODE_AE_SP16F_L_C,
+ OPCODE_AE_LQ56_C,
+ OPCODE_AE_SQ56S_C,
+ OPCODE_AE_LQ32F_C,
+ OPCODE_AE_SQ32F_C,
+ OPCODE_RUR_EXPSTATE,
+ OPCODE_WUR_EXPSTATE,
+ OPCODE_READ_IMPWIRE,
+ OPCODE_SETB_EXPSTATE,
+ OPCODE_CLRB_EXPSTATE,
+ OPCODE_WRMSK_EXPSTATE
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_RET;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_RETW;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_JX;
+ }
+ if (Field_m_Slot_inst_get (insn) == 3)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALLX0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALLX4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALLX8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALLX12;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_MOVSP;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_ISYNC;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RSYNC;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_ESYNC;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DSYNC;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ return OPCODE_EXCW;
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_MEMW;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ return OPCODE_EXTW;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_NOP;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 3)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_RFE;
+ if (Field_s_Slot_inst_get (insn) == 2)
+ return OPCODE_RFDE;
+ if (Field_s_Slot_inst_get (insn) == 4)
+ return OPCODE_RFWO;
+ if (Field_s_Slot_inst_get (insn) == 5)
+ return OPCODE_RFWU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFI;
+ }
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BREAK;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ }
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RSIL;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_LDDR32_P;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_SDDR32_P;
+ }
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_ANY4;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_ALL4;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_ANY8;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_ALL8;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_OR;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_XOR;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RER;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_WER;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_NSA;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_NSAU;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_HWWITLBA;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_RITLB0;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_PITLB;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_WITLB;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_RITLB1;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_HWWDTLBA;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_RDTLB0;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_PDTLB;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_WDTLB;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_RDTLB1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_NEG;
+ if (Field_s_Slot_inst_get (insn) == 1)
+ return OPCODE_ABS;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_ADD;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_ADDX2;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_ADDX4;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_ADDX8;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_SUB;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_SUBX2;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_SUBX4;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_SUBX8;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 1)
+ {
+ if ((Field_op2_Slot_inst_get (insn) == 0 ||
+ Field_op2_Slot_inst_get (insn) == 1))
+ return OPCODE_SLLI;
+ if ((Field_op2_Slot_inst_get (insn) == 2 ||
+ Field_op2_Slot_inst_get (insn) == 3))
+ return OPCODE_SRAI;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_SRLI;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_XSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_XSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_XSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_XSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 4)
+ return OPCODE_XSR_BR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_XSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_XSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_XSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_XSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_XSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_XSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_XSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_XSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 40)
+ return OPCODE_XSR_PREFCTL;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_XSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_XSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 83)
+ return OPCODE_XSR_PTEVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 90)
+ return OPCODE_XSR_RASID;
+ if (Field_sr_Slot_inst_get (insn) == 91)
+ return OPCODE_XSR_ITLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 92)
+ return OPCODE_XSR_DTLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_XSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_XSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_XSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_XSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_XSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_XSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_XSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_XSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_XSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_XSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_XSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_XSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_XSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_XSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_XSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_XSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_XSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_XSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_XSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_XSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_XSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_XSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_XSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_XSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_XSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_XSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_XSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_XSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_XSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_XSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_XSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 224)
+ return OPCODE_XSR_CPENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_XSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_XSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_XSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_XSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_XSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_XSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_XSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_XSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_XSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_XSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_XSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_XSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_XSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_XSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_SRC;
+ if (Field_op2_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ if (Field_op2_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_op2_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MUL16U;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MUL16S;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_LICT;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_SICT;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_LICW;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_SICW;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LDCT;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_SDCT;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_LDPTE;
+ }
+ }
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_ANDB;
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_ANDBC;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_ORB;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_ORBC;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_XORB;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MULL;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MULUH;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MULSH;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_QUOU;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_QUOS;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_REMU;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_REMS;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_RSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_RSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_RSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_RSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 4)
+ return OPCODE_RSR_BR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_RSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_RSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_RSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_RSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_RSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_RSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_RSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_RSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 40)
+ return OPCODE_RSR_PREFCTL;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_RSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_RSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 83)
+ return OPCODE_RSR_PTEVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 90)
+ return OPCODE_RSR_RASID;
+ if (Field_sr_Slot_inst_get (insn) == 91)
+ return OPCODE_RSR_ITLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 92)
+ return OPCODE_RSR_DTLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_RSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_RSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_RSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_RSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_RSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_RSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_RSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_RSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_RSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_RSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_RSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_RSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_RSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_RSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_RSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_RSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_RSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_RSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_RSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_RSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_RSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_RSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_RSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_RSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_RSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 208)
+ return OPCODE_RSR_CONFIGID1;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_RSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_RSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_RSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_RSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_RSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_RSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_RSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 224)
+ return OPCODE_RSR_CPENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_RSR_INTERRUPT;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_RSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_RSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_RSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_RSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_RSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_RSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 235)
+ return OPCODE_RSR_PRID;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_RSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_RSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_RSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_RSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_RSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_RSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 243)
+ return OPCODE_RSR_243;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_RSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_RSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_WSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_WSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_WSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_WSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 4)
+ return OPCODE_WSR_BR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_WSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_WSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 16)
+ return OPCODE_WSR_ACCLO;
+ if (Field_sr_Slot_inst_get (insn) == 17)
+ return OPCODE_WSR_ACCHI;
+ if (Field_sr_Slot_inst_get (insn) == 32)
+ return OPCODE_WSR_M0;
+ if (Field_sr_Slot_inst_get (insn) == 33)
+ return OPCODE_WSR_M1;
+ if (Field_sr_Slot_inst_get (insn) == 34)
+ return OPCODE_WSR_M2;
+ if (Field_sr_Slot_inst_get (insn) == 35)
+ return OPCODE_WSR_M3;
+ if (Field_sr_Slot_inst_get (insn) == 40)
+ return OPCODE_WSR_PREFCTL;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_WSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_WSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 83)
+ return OPCODE_WSR_PTEVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 89)
+ return OPCODE_WSR_MMID;
+ if (Field_sr_Slot_inst_get (insn) == 90)
+ return OPCODE_WSR_RASID;
+ if (Field_sr_Slot_inst_get (insn) == 91)
+ return OPCODE_WSR_ITLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 92)
+ return OPCODE_WSR_DTLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 96)
+ return OPCODE_WSR_IBREAKENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 97)
+ return OPCODE_WSR_MEMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_WSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_WSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 128)
+ return OPCODE_WSR_IBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 129)
+ return OPCODE_WSR_IBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 144)
+ return OPCODE_WSR_DBREAKA0;
+ if (Field_sr_Slot_inst_get (insn) == 145)
+ return OPCODE_WSR_DBREAKA1;
+ if (Field_sr_Slot_inst_get (insn) == 160)
+ return OPCODE_WSR_DBREAKC0;
+ if (Field_sr_Slot_inst_get (insn) == 161)
+ return OPCODE_WSR_DBREAKC1;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_WSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_WSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_WSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 179)
+ return OPCODE_WSR_EPC3;
+ if (Field_sr_Slot_inst_get (insn) == 180)
+ return OPCODE_WSR_EPC4;
+ if (Field_sr_Slot_inst_get (insn) == 181)
+ return OPCODE_WSR_EPC5;
+ if (Field_sr_Slot_inst_get (insn) == 182)
+ return OPCODE_WSR_EPC6;
+ if (Field_sr_Slot_inst_get (insn) == 183)
+ return OPCODE_WSR_EPC7;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_WSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_WSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 195)
+ return OPCODE_WSR_EPS3;
+ if (Field_sr_Slot_inst_get (insn) == 196)
+ return OPCODE_WSR_EPS4;
+ if (Field_sr_Slot_inst_get (insn) == 197)
+ return OPCODE_WSR_EPS5;
+ if (Field_sr_Slot_inst_get (insn) == 198)
+ return OPCODE_WSR_EPS6;
+ if (Field_sr_Slot_inst_get (insn) == 199)
+ return OPCODE_WSR_EPS7;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_WSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_WSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 211)
+ return OPCODE_WSR_EXCSAVE3;
+ if (Field_sr_Slot_inst_get (insn) == 212)
+ return OPCODE_WSR_EXCSAVE4;
+ if (Field_sr_Slot_inst_get (insn) == 213)
+ return OPCODE_WSR_EXCSAVE5;
+ if (Field_sr_Slot_inst_get (insn) == 214)
+ return OPCODE_WSR_EXCSAVE6;
+ if (Field_sr_Slot_inst_get (insn) == 215)
+ return OPCODE_WSR_EXCSAVE7;
+ if (Field_sr_Slot_inst_get (insn) == 224)
+ return OPCODE_WSR_CPENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_WSR_INTSET;
+ if (Field_sr_Slot_inst_get (insn) == 227)
+ return OPCODE_WSR_INTCLEAR;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_WSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_WSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_WSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_WSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_WSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_WSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_WSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WSR_CCOMPARE2;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_WSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_WSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_SEXT;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_CLAMPS;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_MIN;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_MAX;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_MINU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_MAXU;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MOVEQZ;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_MOVNEZ;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVLTZ;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MOVGEZ;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MOVF;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MOVT;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ {
+ if (Field_st_Slot_inst_get (insn) == 230)
+ return OPCODE_RUR_EXPSTATE;
+ if (Field_st_Slot_inst_get (insn) == 231)
+ return OPCODE_RUR_THREADPTR;
+ if (Field_st_Slot_inst_get (insn) == 240)
+ return OPCODE_RUR_AE_OVF_SAR;
+ if (Field_st_Slot_inst_get (insn) == 241)
+ return OPCODE_RUR_AE_BITHEAD;
+ if (Field_st_Slot_inst_get (insn) == 242)
+ return OPCODE_RUR_AE_TS_FTS_BU_BP;
+ if (Field_st_Slot_inst_get (insn) == 243)
+ return OPCODE_RUR_AE_SD_NO;
+ if (Field_st_Slot_inst_get (insn) == 246)
+ return OPCODE_RUR_AE_CBEGIN0;
+ if (Field_st_Slot_inst_get (insn) == 247)
+ return OPCODE_RUR_AE_CEND0;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WUR_EXPSTATE;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WUR_THREADPTR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WUR_AE_OVF_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WUR_AE_BITHEAD;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WUR_AE_TS_FTS_BU_BP;
+ if (Field_sr_Slot_inst_get (insn) == 243)
+ return OPCODE_WUR_AE_SD_NO;
+ if (Field_sr_Slot_inst_get (insn) == 246)
+ return OPCODE_WUR_AE_CBEGIN0;
+ if (Field_sr_Slot_inst_get (insn) == 247)
+ return OPCODE_WUR_AE_CEND0;
+ }
+ }
+ if ((Field_op1_Slot_inst_get (insn) == 4 ||
+ Field_op1_Slot_inst_get (insn) == 5))
+ return OPCODE_EXTUI;
+ if (Field_op1_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_L32E;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_S32E;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_S32NB;
+ }
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_READ_IMPWIRE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_SETB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s3to1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_CLRB_EXPSTATE;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14)
+ return OPCODE_WRMSK_EXPSTATE;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 1)
+ return OPCODE_L32R;
+ if (Field_op0_Slot_inst_get (insn) == 2)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_L32I;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_S16I;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_S32I;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFR;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_DPFW;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_DPFRO;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DPFWO;
+ if (Field_t_Slot_inst_get (insn) == 4)
+ return OPCODE_DHWB;
+ if (Field_t_Slot_inst_get (insn) == 5)
+ return OPCODE_DHWBI;
+ if (Field_t_Slot_inst_get (insn) == 6)
+ return OPCODE_DHI;
+ if (Field_t_Slot_inst_get (insn) == 7)
+ return OPCODE_DII;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFL;
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ return OPCODE_DHU;
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ return OPCODE_DIU;
+ if (Field_op1_Slot_inst_get (insn) == 4)
+ return OPCODE_DIWB;
+ if (Field_op1_Slot_inst_get (insn) == 5)
+ return OPCODE_DIWBI;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_DIWBUI_P;
+ }
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_IPF;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ return OPCODE_IPFL;
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ return OPCODE_IHU;
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ return OPCODE_IIU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_IHI;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_III;
+ }
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVI;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_L32AI;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_S32C1I;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_S32RI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 4)
+ {
+ if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_I;
+ if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_X;
+ if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_I;
+ if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_X;
+ if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_IU;
+ if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_XU;
+ if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_CVTQ48A32S;
+ if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_IU;
+ if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP24F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP24X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_ae_s3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVP48;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVPA24X2;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_CVTA32P24_L;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_LL;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_HL;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVAP24S_L;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_TRUNCA16P24S_L;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP16X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP24X2_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_TRUNCP24A32X2;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_CVTA32P24_H;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_LH;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_HH;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVAP24S_H;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_TRUNCA16P24S_H;
+ if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_I;
+ if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_X;
+ if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_TRUNCA32Q48;
+ if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_I;
+ if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_X;
+ if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_NSAQ56S;
+ if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_IU;
+ if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_XU;
+ if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_IU;
+ if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_XU;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLIQ56;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRLIQ56;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRAIQ56;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLISQ56S;
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SHA32;
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLDL32T;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SLLAQ56;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLDL16T;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SRLAQ56;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LBK;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SRAAQ56;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLEL32T;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SLLASQ56S;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLEL16T;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_MOVTQ56;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_MOVFQ56;
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH_LDDEC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DD_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AD_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t3_Slot_inst_get (insn) == 0 &&
+ Field_tlo_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AD_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDINC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH_LDDEC;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH_LDDEC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_DA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_DA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_w_Slot_inst_get (insn) == 0 &&
+ Field_r3_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_DA_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_UMUL_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MUL_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULA_AA_HH;
+ if (Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LL;
+ if (Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HL;
+ if (Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_LH;
+ if (Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_MULS_AA_HH;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDINC;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_rhi_Slot_inst_get (insn) == 0)
+ return OPCODE_LDDEC;
+ }
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_OVERFLOW;
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_SBI;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_SAR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_DB;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_SB;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_BITPTR;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_BITSUSED;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_TABLESIZE;
+ if (Field_r_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_FIRST_TS;
+ if (Field_r_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_NEXTOFFSET;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_SEARCHDONE;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_VLDSHT;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_VLES16C;
+ if (Field_r_Slot_inst_get (insn) == 13 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SBF;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_VLDL16C;
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLSQ56;
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LB;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRLSQ56;
+ if (Field_s_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRASQ56;
+ if (Field_s_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLSSQ56S;
+ if (Field_s_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVQ56;
+ if (Field_s_Slot_inst_get (insn) == 8 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_OVERFLOW;
+ if (Field_s_Slot_inst_get (insn) == 9 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_SAR;
+ if (Field_s_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_BITPTR;
+ if (Field_s_Slot_inst_get (insn) == 11 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_BITSUSED;
+ if (Field_s_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_TABLESIZE;
+ if (Field_s_Slot_inst_get (insn) == 13 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_FIRST_TS;
+ if (Field_s_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_NEXTOFFSET;
+ if (Field_s_Slot_inst_get (insn) == 15 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_SEARCHDONE;
+ if (Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_LBKI;
+ if (Field_t_Slot_inst_get (insn) == 0 &&
+ Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_DBI;
+ if (Field_t_Slot_inst_get (insn) == 2 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_LBI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 5)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALL0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALL4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALL8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALL12;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 6)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_J;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQZ;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTZ;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEZ;
+ }
+ if (Field_n_Slot_inst_get (insn) == 2)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQI;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEI;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEI;
+ }
+ if (Field_n_Slot_inst_get (insn) == 3)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_ENTRY;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BF;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BT;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LOOP;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_LOOPNEZ;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_LOOPGTZ;
+ }
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTUI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEUI;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 7)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BALL;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_BBC;
+ if ((Field_r_Slot_inst_get (insn) == 6 ||
+ Field_r_Slot_inst_get (insn) == 7))
+ return OPCODE_BBCI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_BANY;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_BNE;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_BGE;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_BNALL;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_BBS;
+ if ((Field_r_Slot_inst_get (insn) == 14 ||
+ Field_r_Slot_inst_get (insn) == 15))
+ return OPCODE_BBSI;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16b_get (insn) == 12)
+ {
+ if (Field_i_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOVI_N;
+ if (Field_i_Slot_inst16b_get (insn) == 1)
+ {
+ if (Field_z_Slot_inst16b_get (insn) == 0)
+ return OPCODE_BEQZ_N;
+ if (Field_z_Slot_inst16b_get (insn) == 1)
+ return OPCODE_BNEZ_N;
+ }
+ }
+ if (Field_op0_Slot_inst16b_get (insn) == 13)
+ {
+ if (Field_r_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOV_N;
+ if (Field_r_Slot_inst16b_get (insn) == 15)
+ {
+ if (Field_t_Slot_inst16b_get (insn) == 0)
+ return OPCODE_RET_N;
+ if (Field_t_Slot_inst16b_get (insn) == 1)
+ return OPCODE_RETW_N;
+ if (Field_t_Slot_inst16b_get (insn) == 2)
+ return OPCODE_BREAK_N;
+ if (Field_t_Slot_inst16b_get (insn) == 3 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ if (Field_t_Slot_inst16b_get (insn) == 6 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ }
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16a_get (insn) == 8)
+ return OPCODE_L32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 9)
+ return OPCODE_S32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 10)
+ return OPCODE_ADD_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 11)
+ return OPCODE_ADDI_N;
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_ae_slot0_decode (const xtensa_insnbuf insn)
+{
+ if (Field_ae_s20_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+ Field_ftsf378ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_BT;
+ if (Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SELP24_HH;
+ if (Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SELP24_HL;
+ if (Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SELP24_LH;
+ if (Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_ftsf315_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 2 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLAASQ56S;
+ if (Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_C;
+ if (Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_C;
+ if (Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_C;
+ if (Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_C;
+ if (Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_C;
+ if (Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_C;
+ if (Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_C;
+ if (Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_C;
+ if (Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_C;
+ if (Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_C;
+ if (Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_C;
+ if (Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_C;
+ if (Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SQ32F_C;
+ if (Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SQ56S_C;
+ if (Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SELP24_LL;
+ if (Field_ftsf211ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_J;
+ if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_EXTUI;
+ if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BEQZ;
+ if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BGEZ;
+ if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVI;
+ if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 13 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BLTZ;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRAI;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SLLI;
+ if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 43 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_HH;
+ if (Field_ftsf217ae_slot0_Slot_ae_slot0_get (insn) == 299 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_I;
+ if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 46 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_HL;
+ if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 47 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_IU;
+ if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 302 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_X;
+ if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 303 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_XU;
+ if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 58 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_LH;
+ if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 59 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_I;
+ if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 62 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_IU;
+ if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 63 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_XU;
+ if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 314 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_X;
+ if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 315 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_I;
+ if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 318 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_IU;
+ if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 319 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_X;
+ if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 170 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_LL;
+ if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 171 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_XU;
+ if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 174 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_I;
+ if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 175 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_XU;
+ if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 186 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_IU;
+ if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 187 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_I;
+ if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 190 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_IU;
+ if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 191 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_X;
+ if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_X;
+ if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_XU;
+ if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_I;
+ if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_X;
+ if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_IU;
+ if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_XU;
+ if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVPA24X2;
+ if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_I;
+ if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 75 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_IU;
+ if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 331 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_X;
+ if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 78 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_X;
+ if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 79 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_XU;
+ if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 334 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_I;
+ if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 335 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_IU;
+ if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 90 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_XU;
+ if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 91 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_X;
+ if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 94 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_XU;
+ if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 95 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_IU;
+ if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 346 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_I;
+ if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 347 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_X;
+ if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 350 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_XU;
+ if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 351 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_I;
+ if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 106 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_I;
+ if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 107 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_IU;
+ if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 110 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_X;
+ if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 111 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_IU;
+ if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 122 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_XU;
+ if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_X;
+ if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 126 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_XU;
+ if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 127 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_TRUNCP24A32X2;
+ if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 362 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_I;
+ if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 363 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ32F_I;
+ if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 875 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ32F_XU;
+ if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 366 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ32F_IU;
+ if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 367 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_I;
+ if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 878 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_IU;
+ if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 879 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_X;
+ if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 378 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ32F_X;
+ if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 379 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_XU;
+ if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 890 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_NSAQ56S;
+ if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 891 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_TRUNCA32Q48;
+ if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 2938 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s8_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_JX;
+ if (Field_ftsf280_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBCI;
+ if (Field_ftsf280_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBSI;
+ if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 2939 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s8_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 1981 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_NOP;
+ if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 957 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_ftsf285ae_slot0_Slot_ae_slot0_get (insn) == 957 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_ftsf287ae_slot0_Slot_ae_slot0_get (insn) == 957 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_ftsf288_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+ Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_BLTUI;
+ if (Field_ftsf289ae_slot0_Slot_ae_slot0_get (insn) == 382 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTA32P24_H;
+ if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 383 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTA32P24_L;
+ if (Field_ftsf291ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVAP24S_H;
+ if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf382ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVAP24S_L;
+ if (Field_ftsf293ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf384ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_TRUNCA16P24S_H;
+ if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf383ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_TRUNCA16P24S_L;
+ if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 202 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_IU;
+ if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 4298 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf315_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVP48;
+ if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 4554 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ALL4;
+ if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 12746 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf309_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 2506 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf373ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ANY4;
+ if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 1482 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf370ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ALL8;
+ if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 970 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf376ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ANY8;
+ if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 203 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ32F_I;
+ if (Field_ftsf305ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ56_I;
+ if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 715 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ56_IU;
+ if (Field_ftsf307ae_slot0_Slot_ae_slot0_get (insn) == 971 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ56_X;
+ if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 206 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s8_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_LQ32F_IU;
+ if (Field_ftsf309_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s8_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_LQ56_C;
+ if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 207 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s8_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_LQ56_XU;
+ if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 231 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf386ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_CVTQ48A32S;
+ if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 219 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLIQ56;
+ if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 222 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLISQ56S;
+ if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 475 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SRAIQ56;
+ if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 731 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SRLIQ56;
+ if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 987 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ABS;
+ if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 2011 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_NEG;
+ if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 3035 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRA;
+ if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 4059 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRL;
+ if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVQ56;
+ if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 1502 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SLLSSQ56S;
+ if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 1502 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf389ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRASQ56;
+ if (Field_ftsf319ae_slot0_Slot_ae_slot0_get (insn) == 1502 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf388ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRLSQ56;
+ if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf387ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SLLSQ56;
+ if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 223 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVFQ56;
+ if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 479 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVTQ56;
+ if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 735 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLAQ56;
+ if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 991 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SRLAQ56;
+ if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 735 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SLLASQ56S;
+ if (Field_ftsf327ae_slot0_Slot_ae_slot0_get (insn) == 991 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 479 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRAAQ56;
+ if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf379ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_LQ32F_XU;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 11 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVGEZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 14 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVLTZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 15 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ORBC;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 23 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADD;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 26 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVNEZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 27 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRLI;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 30 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 31 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUBX4;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 39 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADDX2;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 42 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVT;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 55 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 71 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADDX4;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 74 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_OR;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 87 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_CLAMPS;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 103 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MAX;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 119 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MIN;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 139 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ORB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 142 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SEXT;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 143 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRC;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 151 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADDX8;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 154 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUBX2;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 155 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUBX8;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 158 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_XOR;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 159 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_XORB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 167 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ANDB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ANDBC;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MAXU;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 215 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MINU;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 218 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ae_r10_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_LQ32F_X;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 231 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVEQZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 247 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVF;
+ if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
+ return OPCODE_L32R;
+ if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_ADDBRBA32;
+ if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_BNE;
+ if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BALL;
+ if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBS;
+ if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_S16I;
+ if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_S32I;
+ if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BANY;
+ if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBC;
+ if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BGE;
+ if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BNALL;
+ if (Field_s8_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
+ Field_ftsf280_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_L32I;
+ if (Field_s8_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf309_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ32F_C;
+ if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BEQI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BGEI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BGEUI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BNEI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BLTI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+ Field_r_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_BF;
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_ae_slot1_decode (const xtensa_insnbuf insn)
+{
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 50 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP24S_L;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 82 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULARFQ32SP24S_L;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 114 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP24S_L;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 146 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULRFQ32SP24S_L;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 178 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP24S_L;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 210 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSRFQ32SP24S_L;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 274 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULRFQ32SP24S_H;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 306 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP24S_H;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 338 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSRFQ32SP24S_H;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 402 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULARFQ32SP24S_H;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 434 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP24S_H;
+ if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 466 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP24S_H;
+ if (Field_ae_r20_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_LTQ56S;
+ if (Field_ae_s20_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf340ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULZAAP24S_HL_LH;
+ if (Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf91_Slot_ae_slot1_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 &&
+ Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MAXABSSP24S;
+ if (Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf91_Slot_ae_slot1_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 &&
+ Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MINABSSP24S;
+ if (Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 &&
+ Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MINABSSQ56S;
+ if (Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 0 &&
+ Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 &&
+ Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 &&
+ Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MAXABSSQ56S;
+ if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf335_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULSQ32SP16U_H;
+ if (Field_ftsf102ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULSFQ32SP16U_H;
+ if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULAFQ32SP16S_H;
+ if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MAXBQ56S;
+ if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MINBQ56S;
+ if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_EQQ56;
+ if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ADDSQ56S;
+ if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ANDQ56;
+ if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 131 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MAXQ56S;
+ if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ORQ56;
+ if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 259 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MINQ56S;
+ if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 323 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_SUBQ56;
+ if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 387 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_SUBSQ56S;
+ if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 451 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_XORQ56;
+ if (Field_ftsf117ae_slot1_Slot_ae_slot1_get (insn) == 515 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_NANDQ56;
+ if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 2307 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ABSQ56;
+ if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 2315 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_NEGSQ56S;
+ if (Field_ftsf121ae_slot1_Slot_ae_slot1_get (insn) == 1163 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf91_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_SATQ48S;
+ if (Field_ftsf123ae_slot1_Slot_ae_slot1_get (insn) == 323 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ABSSQ56S;
+ if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf352ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_NEGQ56;
+ if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_LEQ56S;
+ if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf357ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_TRUNCP24Q48X2;
+ if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ADDQ56;
+ if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAFP24S_HH_LL;
+ if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAFP24S_HL_LH;
+ if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAP24S_HH_LL;
+ if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS32P16S_HL;
+ if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAP24S_HL_LH;
+ if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS32P16S_LH;
+ if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS32P16S_LL;
+ if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_HH;
+ if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_HH;
+ if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_HL;
+ if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_LH;
+ if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_HH;
+ if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_LL;
+ if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_HL;
+ if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_LH;
+ if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_LL;
+ if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_HL;
+ if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_HH;
+ if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_HL;
+ if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASFP24S_HH_LL;
+ if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_LH;
+ if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASFP24S_HL_LH;
+ if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASP24S_HH_LL;
+ if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASP24S_HL_LH;
+ if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_LL;
+ if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_HH;
+ if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_HL;
+ if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_LL;
+ if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_LH;
+ if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_HH;
+ if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_HL;
+ if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_LH;
+ if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_LH;
+ if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_LL;
+ if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_HH;
+ if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAFP24S_HH_LL;
+ if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_HL;
+ if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAFP24S_HL_LH;
+ if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAP24S_HH_LL;
+ if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAP24S_HL_LH;
+ if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_LH;
+ if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_HH;
+ if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_HL;
+ if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_LL;
+ if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_LH;
+ if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_HH;
+ if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_HL;
+ if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_LH;
+ if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_LL;
+ if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_LL;
+ if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_HH;
+ if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_LL;
+ if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_HL;
+ if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_HH;
+ if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_HL;
+ if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_LH;
+ if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_LH;
+ if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_LL;
+ if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_HH;
+ if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_LH;
+ if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_HL;
+ if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_LL;
+ if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSFP24S_HH_LL;
+ if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSFP24S_HL_LH;
+ if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_LL;
+ if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSP24S_HH_LL;
+ if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSP24S_HL_LH;
+ if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASFP24S_HH_LL;
+ if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZAAFP24S_HH_LL;
+ if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASFP24S_HL_LH;
+ if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASP24S_HH_LL;
+ if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASP24S_HL_LH;
+ if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZAAFP24S_HL_LH;
+ if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAFP24S_HH_LL;
+ if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAFP24S_HL_LH;
+ if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAP24S_HL_LH;
+ if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAP24S_HH_LL;
+ if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSSFP24S_HH_LL;
+ if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSSFP24S_HL_LH;
+ if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSSP24S_HH_LL;
+ if (Field_ftsf208ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULZAAP24S_HH_LL;
+ if (Field_ftsf20ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MAXBP24S;
+ if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULZSSP24S_HL_LH;
+ if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MINBP24S;
+ if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVFP48;
+ if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ADDP24;
+ if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MAXP24S;
+ if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ADDSP24S;
+ if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MINP24S;
+ if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 84 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_NANDP48;
+ if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 85 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ORP48;
+ if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ANDP48;
+ if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_HH;
+ if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_HL;
+ if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_LL;
+ if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 100 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_LH;
+ if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 101 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SUBP24;
+ if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 116 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SUBSP24S;
+ if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 117 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_XORP48;
+ if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVTP48;
+ if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ABSP24;
+ if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 88 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_NEGP24;
+ if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 152 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_NEGSP24S;
+ if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 216 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf333ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_NOP;
+ if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 88 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf359ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ZEROP48;
+ if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 704 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVP48;
+ if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 708 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSP16ASYM;
+ if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 712 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSP16SYM;
+ if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 716 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SLLSSP24S;
+ if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 720 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SLLSP24;
+ if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 724 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRASP24;
+ if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 728 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRLSP24;
+ if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 732 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_TRUNCP16;
+ if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf356ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ABSSP24S;
+ if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_EQP24;
+ if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_LTP24S;
+ if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MOVFP24X2;
+ if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf355ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MOVTP24X2;
+ if (Field_ftsf61_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULAFS32P16S_HH;
+ if (Field_ftsf62ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_LEP24S;
+ if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSP16Q48ASYM;
+ if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 101 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSP16Q48SYM;
+ if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf345ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSP24Q48ASYM;
+ if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf347ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSP24Q48SYM;
+ if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SLLIP24;
+ if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SLLISP24S;
+ if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRAIP24;
+ if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRLIP24;
+ if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16S_L;
+ if (Field_ftsf70ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16U_H;
+ if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16U_L;
+ if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 103 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16U_H;
+ if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 135 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16S_H;
+ if (Field_ftsf74ae_slot1_Slot_ae_slot1_get (insn) == 167 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16U_L;
+ if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 199 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16S_H;
+ if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 231 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16S_L;
+ if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 263 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16S_L;
+ if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 295 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16U_H;
+ if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 327 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16U_L;
+ if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 359 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16S_L;
+ if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 391 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16S_H;
+ if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16U_H;
+ if (Field_ftsf83ae_slot1_Slot_ae_slot1_get (insn) == 455 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16U_L;
+ if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 487 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16S_H;
+ if (Field_ftsf85ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16S_L;
+ if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16U_L;
+ if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSQ32SP16S_H;
+ if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 107 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSQ32SP16U_L;
+ if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 139 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSQ32SP16S_L;
+ if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 331 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf55_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_CVTQ48P24S_H;
+ if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 363 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf358ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ZEROQ56;
+ if (Field_ftsf93ae_slot1_Slot_ae_slot1_get (insn) == 203 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_CVTQ48P24S_L;
+ if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 1803 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVQ56;
+ if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 1835 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSQ32ASYM;
+ if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 939 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSQ32SYM;
+ if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 491 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf351_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_TRUNCQ32;
+ if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16U_LL;
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[1] & 0xffffff00) >> 8);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[1] = (insn[1] & ~0xffffff00) | ((slotbuf[0] & 0xffffff) << 8);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
+}
+
+static void
+Slot_ae_format_Format_ae_slot1_10_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[0] & 0xfffffc00) >> 10);
+ slotbuf[0] = (slotbuf[0] & ~0x400000) | ((insn[1] & 0x1) << 22);
+}
+
+static void
+Slot_ae_format_Format_ae_slot1_10_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xfffffc00) | ((slotbuf[0] & 0x3fffff) << 10);
+ insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x400000) >> 22);
+}
+
+static void
+Slot_ae_format_Format_ae_slot0_33_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[1] & 0xffffffe) >> 1);
+}
+
+static void
+Slot_ae_format_Format_ae_slot0_33_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[1] = (insn[1] & ~0xffffffe) | ((slotbuf[0] & 0x7ffffff) << 1);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_get,
+ Field_rbit2_Slot_inst_get,
+ Field_rhi_Slot_inst_get,
+ Field_t3_Slot_inst_get,
+ Field_tbit2_Slot_inst_get,
+ Field_tlo_Slot_inst_get,
+ Field_w_Slot_inst_get,
+ Field_y_Slot_inst_get,
+ Field_x_Slot_inst_get,
+ Field_t2_Slot_inst_get,
+ Field_s2_Slot_inst_get,
+ Field_r2_Slot_inst_get,
+ Field_t4_Slot_inst_get,
+ Field_s4_Slot_inst_get,
+ Field_r4_Slot_inst_get,
+ Field_t8_Slot_inst_get,
+ Field_s8_Slot_inst_get,
+ Field_r8_Slot_inst_get,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_ae_r3_Slot_inst_get,
+ Field_ae_s_non_samt_Slot_inst_get,
+ Field_ae_s3_Slot_inst_get,
+ Field_ae_r32_Slot_inst_get,
+ Field_ae_samt_s_t_Slot_inst_get,
+ Field_ae_r20_Slot_inst_get,
+ Field_ae_r10_Slot_inst_get,
+ Field_ae_s20_Slot_inst_get,
+ Field_ae_fld_ohba_Slot_inst_get,
+ Field_ae_fld_ohba2_Slot_inst_get,
+ 0,
+ Field_ftsf11_Slot_inst_get,
+ Field_ftsf12_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst_get,
+ Field_s3to1_Slot_inst_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_r3_Slot_inst_set,
+ Field_rbit2_Slot_inst_set,
+ Field_rhi_Slot_inst_set,
+ Field_t3_Slot_inst_set,
+ Field_tbit2_Slot_inst_set,
+ Field_tlo_Slot_inst_set,
+ Field_w_Slot_inst_set,
+ Field_y_Slot_inst_set,
+ Field_x_Slot_inst_set,
+ Field_t2_Slot_inst_set,
+ Field_s2_Slot_inst_set,
+ Field_r2_Slot_inst_set,
+ Field_t4_Slot_inst_set,
+ Field_s4_Slot_inst_set,
+ Field_r4_Slot_inst_set,
+ Field_t8_Slot_inst_set,
+ Field_s8_Slot_inst_set,
+ Field_r8_Slot_inst_set,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_ae_r3_Slot_inst_set,
+ Field_ae_s_non_samt_Slot_inst_set,
+ Field_ae_s3_Slot_inst_set,
+ Field_ae_r32_Slot_inst_set,
+ Field_ae_samt_s_t_Slot_inst_set,
+ Field_ae_r20_Slot_inst_set,
+ Field_ae_r10_Slot_inst_set,
+ Field_ae_s20_Slot_inst_set,
+ Field_ae_fld_ohba_Slot_inst_set,
+ Field_ae_fld_ohba2_Slot_inst_set,
+ 0,
+ Field_ftsf11_Slot_inst_set,
+ Field_ftsf12_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst_set,
+ Field_s3to1_Slot_inst_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_inst16a_get,
+ Field_s2_Slot_inst16a_get,
+ Field_r2_Slot_inst16a_get,
+ Field_t4_Slot_inst16a_get,
+ Field_s4_Slot_inst16a_get,
+ Field_r4_Slot_inst16a_get,
+ Field_t8_Slot_inst16a_get,
+ Field_s8_Slot_inst16a_get,
+ Field_r8_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_get,
+ Field_s3to1_Slot_inst16a_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_inst16a_set,
+ Field_s2_Slot_inst16a_set,
+ Field_r2_Slot_inst16a_set,
+ Field_t4_Slot_inst16a_set,
+ Field_s4_Slot_inst16a_set,
+ Field_r4_Slot_inst16a_set,
+ Field_t8_Slot_inst16a_set,
+ Field_s8_Slot_inst16a_set,
+ Field_r8_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16a_set,
+ Field_s3to1_Slot_inst16a_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_inst16b_get,
+ Field_s2_Slot_inst16b_get,
+ Field_r2_Slot_inst16b_get,
+ Field_t4_Slot_inst16b_get,
+ Field_s4_Slot_inst16b_get,
+ Field_r4_Slot_inst16b_get,
+ Field_t8_Slot_inst16b_get,
+ Field_s8_Slot_inst16b_get,
+ Field_r8_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_get,
+ Field_s3to1_Slot_inst16b_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_inst16b_set,
+ Field_s2_Slot_inst16b_set,
+ Field_r2_Slot_inst16b_set,
+ Field_t4_Slot_inst16b_set,
+ Field_s4_Slot_inst16b_set,
+ Field_r4_Slot_inst16b_set,
+ Field_t8_Slot_inst16b_set,
+ Field_s8_Slot_inst16b_set,
+ Field_r8_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_inst16b_set,
+ Field_s3to1_Slot_inst16b_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_ae_slot1_get_field_fns[] = {
+ Field_t_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot1_get,
+ 0,
+ Field_ae_r20_Slot_ae_slot1_get,
+ Field_ae_r10_Slot_ae_slot1_get,
+ Field_ae_s20_Slot_ae_slot1_get,
+ 0,
+ 0,
+ Field_op0_s3_Slot_ae_slot1_get,
+ Field_ftsf11_Slot_ae_slot1_get,
+ Field_ftsf12_Slot_ae_slot1_get,
+ Field_ftsf13_Slot_ae_slot1_get,
+ Field_ftsf20ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf21ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf22ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf23ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf24ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf25ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf26ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf27ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf28ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf29ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf30ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf31ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf32ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf33ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf34ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf35ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf36ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf37ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf38ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf40ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf41ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf42ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf43ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf45ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf47ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf48ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf49ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf50ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf51ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf52ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf53ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf54ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf55_Slot_ae_slot1_get,
+ Field_ftsf56ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf57ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf58ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf60ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf61_Slot_ae_slot1_get,
+ Field_ftsf62ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf63ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf64ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf66ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf68ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf69ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf70ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf71ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf72ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf73ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf74ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf75ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf76ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf77ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf78ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf79ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf80ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf81ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf82ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf83ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf84ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf85ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf86ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf87ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf88ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf89ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf90ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf91_Slot_ae_slot1_get,
+ Field_ftsf92ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf93ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf94ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf96ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf97ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf99ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf101ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf102ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf103ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf106ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf107ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf108ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf109ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf110ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf111ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf112ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf113ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf114ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf115ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf116ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf117ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf118ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf120ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf121ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf123ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf124ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf125ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf126ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf127ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf128ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf129ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf130ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf131ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf132ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf133ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf134ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf135ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf136ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf137ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf138ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf139ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf140ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf141ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf142ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf143ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf144ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf145ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf146ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf147ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf148ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf149ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf150ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf151ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf152ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf153ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf154ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf155ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf156ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf157ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf158ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf159ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf160ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf161ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf162ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf163ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf164ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf165ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf166ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf167ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf168ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf169ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf170ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf171ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf172ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf173ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf174ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf175ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf176ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf177ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf178ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf179ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf180ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf181ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf182ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf183ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf184ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf185ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf186ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf187ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf188ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf189ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf190ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf191ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf192ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf193ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf194ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf195ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf196ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf197ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf198ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf199ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf200ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf201ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf202ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf203ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf204ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf205ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf206ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf207ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf208ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf210ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf333ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf334ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf335_Slot_ae_slot1_get,
+ Field_ftsf336ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf337ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf339ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf340ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf341ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf342ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf343ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf344ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf345ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf347ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf348ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf349ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf350ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf351_Slot_ae_slot1_get,
+ Field_ftsf352ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf354ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf355ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf356ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf357ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf358ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf359ae_slot1_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_mul32x24fld_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_s3_s3_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld19_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld22_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld24_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld65_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld66_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld68_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld69_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld74_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld79_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld88_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld90_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld91_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get,
+ Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get,
+ 0,
+ 0,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_ae_slot1_set_field_fns[] = {
+ Field_t_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot1_set,
+ 0,
+ Field_ae_r20_Slot_ae_slot1_set,
+ Field_ae_r10_Slot_ae_slot1_set,
+ Field_ae_s20_Slot_ae_slot1_set,
+ 0,
+ 0,
+ Field_op0_s3_Slot_ae_slot1_set,
+ Field_ftsf11_Slot_ae_slot1_set,
+ Field_ftsf12_Slot_ae_slot1_set,
+ Field_ftsf13_Slot_ae_slot1_set,
+ Field_ftsf20ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf21ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf22ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf23ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf24ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf25ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf26ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf27ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf28ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf29ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf30ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf31ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf32ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf33ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf34ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf35ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf36ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf37ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf38ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf40ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf41ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf42ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf43ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf45ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf47ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf48ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf49ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf50ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf51ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf52ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf53ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf54ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf55_Slot_ae_slot1_set,
+ Field_ftsf56ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf57ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf58ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf60ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf61_Slot_ae_slot1_set,
+ Field_ftsf62ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf63ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf64ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf66ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf68ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf69ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf70ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf71ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf72ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf73ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf74ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf75ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf76ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf77ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf78ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf79ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf80ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf81ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf82ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf83ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf84ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf85ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf86ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf87ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf88ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf89ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf90ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf91_Slot_ae_slot1_set,
+ Field_ftsf92ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf93ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf94ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf96ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf97ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf99ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf101ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf102ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf103ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf106ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf107ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf108ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf109ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf110ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf111ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf112ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf113ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf114ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf115ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf116ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf117ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf118ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf120ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf121ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf123ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf124ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf125ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf126ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf127ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf128ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf129ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf130ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf131ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf132ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf133ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf134ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf135ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf136ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf137ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf138ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf139ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf140ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf141ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf142ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf143ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf144ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf145ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf146ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf147ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf148ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf149ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf150ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf151ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf152ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf153ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf154ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf155ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf156ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf157ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf158ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf159ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf160ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf161ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf162ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf163ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf164ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf165ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf166ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf167ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf168ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf169ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf170ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf171ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf172ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf173ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf174ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf175ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf176ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf177ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf178ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf179ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf180ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf181ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf182ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf183ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf184ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf185ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf186ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf187ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf188ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf189ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf190ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf191ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf192ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf193ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf194ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf195ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf196ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf197ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf198ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf199ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf200ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf201ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf202ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf203ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf204ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf205ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf206ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf207ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf208ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf210ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf333ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf334ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf335_Slot_ae_slot1_set,
+ Field_ftsf336ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf337ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf339ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf340ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf341ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf342ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf343ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf344ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf345ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf347ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf348ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf349ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf350ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf351_Slot_ae_slot1_set,
+ Field_ftsf352ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf354ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf355ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf356ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf357ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf358ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf359ae_slot1_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_mul32x24fld_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_s3_s3_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld19_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld22_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld24_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld65_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld66_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld68_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld69_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld74_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld79_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld88_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld90_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld91_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set,
+ Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set,
+ 0,
+ 0,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_ae_slot0_get_field_fns[] = {
+ Field_t_Slot_ae_slot0_get,
+ 0,
+ Field_bbi_Slot_ae_slot0_get,
+ Field_imm12_Slot_ae_slot0_get,
+ Field_imm8_Slot_ae_slot0_get,
+ Field_s_Slot_ae_slot0_get,
+ Field_imm12b_Slot_ae_slot0_get,
+ Field_imm16_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_offset_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_op2_Slot_ae_slot0_get,
+ Field_r_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_sae_Slot_ae_slot0_get,
+ Field_sal_Slot_ae_slot0_get,
+ Field_sargt_Slot_ae_slot0_get,
+ 0,
+ Field_sas_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s4_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_s8_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot0_get,
+ Field_ae_samt_s_t_Slot_ae_slot0_get,
+ Field_ae_r20_Slot_ae_slot0_get,
+ Field_ae_r10_Slot_ae_slot0_get,
+ Field_ae_s20_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ Field_ftsf11_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_s4_Slot_ae_slot0_get,
+ Field_ftsf211ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf212ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf213ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf214ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf215ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf217ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf218ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf219ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf220ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf221ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf222ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf223ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf224ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf225ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf226ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf227ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf228ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf229ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf230ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf231ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf232ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf233ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf234ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf235ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf236ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf237ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf238ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf239ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf240ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf241ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf242ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf243ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf244ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf245ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf246ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf247ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf248ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf249ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf250ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf251ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf252ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf253ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf254ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf255ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf256ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf257ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf258ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf259ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf260ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf261ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf262ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf263ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf264ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf265ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf266ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf267ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf268ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf269ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf270ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf271ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf272ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf273ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf274ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf275ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf276ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf277ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf278ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf279ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf280_Slot_ae_slot0_get,
+ Field_ftsf281ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf282ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf284ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf285ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf287ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf288_Slot_ae_slot0_get,
+ Field_ftsf289ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf290ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf291ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf292ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf293ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf294ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf295ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf296ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf297ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf298ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf300ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf302ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf304ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf305ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf306ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf307ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf308ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf309_Slot_ae_slot0_get,
+ Field_ftsf310ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf311ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf312ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf313ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf314ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf315_Slot_ae_slot0_get,
+ Field_ftsf316ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf317ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf319ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf320ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf322ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf323ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf324ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf325ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf326ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf327ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf328ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf329ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf360ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf361ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf362_Slot_ae_slot0_get,
+ Field_ftsf363ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf364ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf366ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf368ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf370ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf373ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf376ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf378ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf379ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf382ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf383ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf384ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf386ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf387ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf388ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf389ae_slot0_Slot_ae_slot0_get,
+ 0,
+ Field_op0_s4_s4_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld37_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld46_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld47_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld52_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld121_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld123_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get,
+ Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get,
+ Field_op0_s4_s4_s4_Slot_ae_slot0_get,
+ Field_combined1e9fefee_fld96_Slot_ae_slot0_get,
+ Field_combined1e9fefee_fld98_Slot_ae_slot0_get,
+ Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get,
+ Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get,
+ Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get,
+ Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_ae_slot0_get,
+ Field_s3to1_Slot_ae_slot0_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_mr0_get,
+ Implicit_Field_mr1_get,
+ Implicit_Field_mr2_get,
+ Implicit_Field_mr3_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_ae_slot0_set_field_fns[] = {
+ Field_t_Slot_ae_slot0_set,
+ 0,
+ Field_bbi_Slot_ae_slot0_set,
+ Field_imm12_Slot_ae_slot0_set,
+ Field_imm8_Slot_ae_slot0_set,
+ Field_s_Slot_ae_slot0_set,
+ Field_imm12b_Slot_ae_slot0_set,
+ Field_imm16_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_offset_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_op2_Slot_ae_slot0_set,
+ Field_r_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_sae_Slot_ae_slot0_set,
+ Field_sal_Slot_ae_slot0_set,
+ Field_sargt_Slot_ae_slot0_set,
+ 0,
+ Field_sas_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s4_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_s8_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot0_set,
+ Field_ae_samt_s_t_Slot_ae_slot0_set,
+ Field_ae_r20_Slot_ae_slot0_set,
+ Field_ae_r10_Slot_ae_slot0_set,
+ Field_ae_s20_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ Field_ftsf11_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_s4_Slot_ae_slot0_set,
+ Field_ftsf211ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf212ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf213ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf214ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf215ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf217ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf218ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf219ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf220ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf221ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf222ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf223ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf224ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf225ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf226ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf227ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf228ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf229ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf230ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf231ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf232ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf233ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf234ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf235ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf236ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf237ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf238ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf239ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf240ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf241ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf242ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf243ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf244ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf245ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf246ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf247ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf248ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf249ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf250ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf251ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf252ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf253ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf254ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf255ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf256ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf257ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf258ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf259ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf260ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf261ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf262ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf263ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf264ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf265ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf266ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf267ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf268ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf269ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf270ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf271ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf272ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf273ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf274ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf275ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf276ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf277ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf278ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf279ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf280_Slot_ae_slot0_set,
+ Field_ftsf281ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf282ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf284ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf285ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf287ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf288_Slot_ae_slot0_set,
+ Field_ftsf289ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf290ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf291ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf292ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf293ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf294ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf295ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf296ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf297ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf298ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf300ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf302ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf304ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf305ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf306ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf307ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf308ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf309_Slot_ae_slot0_set,
+ Field_ftsf310ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf311ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf312ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf313ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf314ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf315_Slot_ae_slot0_set,
+ Field_ftsf316ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf317ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf319ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf320ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf322ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf323ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf324ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf325ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf326ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf327ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf328ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf329ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf360ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf361ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf362_Slot_ae_slot0_set,
+ Field_ftsf363ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf364ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf366ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf368ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf370ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf373ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf376ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf378ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf379ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf382ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf383ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf384ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf386ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf387ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf388ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf389ae_slot0_Slot_ae_slot0_set,
+ 0,
+ Field_op0_s4_s4_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld28_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld37_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld39_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld40_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld46_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld47_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld49_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld50_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld52_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld121_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld123_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld127_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set,
+ Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set,
+ Field_op0_s4_s4_s4_Slot_ae_slot0_set,
+ Field_combined1e9fefee_fld96_Slot_ae_slot0_set,
+ Field_combined1e9fefee_fld98_Slot_ae_slot0_set,
+ Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set,
+ Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set,
+ Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set,
+ Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_bitindex_Slot_ae_slot0_set,
+ Field_s3to1_Slot_ae_slot0_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" },
+ { "ae_slot1", "ae_format", 1,
+ Slot_ae_format_Format_ae_slot1_10_get, Slot_ae_format_Format_ae_slot1_10_set,
+ Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
+ Slot_ae_slot1_decode, "nop" },
+ { "ae_slot0", "ae_format", 0,
+ Slot_ae_format_Format_ae_slot0_33_get, Slot_ae_format_Format_ae_slot0_33_set,
+ Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
+ Slot_ae_slot0_decode, "nop" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+ insn[1] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+ insn[1] = 0x80000000;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+ insn[1] = 0xc0000000;
+}
+
+static void
+Format_ae_format_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+ insn[1] = 0xf0000000;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static int Format_ae_format_slots[] = { 3, 4 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
+ { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0) == 0 && (insn[1] & 0x80000000) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0) == 0 && (insn[1] & 0xc0000000) == 0x80000000)
+ return 1; /* x16a */
+ if ((insn[0] & 0) == 0 && (insn[1] & 0xe0000000) == 0xc0000000)
+ return 2; /* x16b */
+ if ((insn[0] & 0x3ff) == 0 && (insn[1] & 0xf0000000) == 0xf0000000)
+ return 3; /* ae_format */
+ return -1;
+}
+
+static int length_table[256] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ -1,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int l = insn[0];
+ return length_table[l];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 1 /* big-endian */,
+ 8 /* insn_size */, 0,
+ 4, formats, format_decoder, length_decoder,
+ 5, slots,
+ 468 /* num_fields */,
+ 536, operands,
+ 746, iclasses,
+ 881, opcodes, 0,
+ 9, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 6, interfaces, 0,
+ 4, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
-
- Copyright (c) 2003-2015 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "BR", 4, 0 },
- { "ACCLO", 16, 0 },
- { "ACCHI", 17, 0 },
- { "M0", 32, 0 },
- { "M1", 33, 0 },
- { "M2", 34, 0 },
- { "M3", 35, 0 },
- { "PTEVADDR", 83, 0 },
- { "MMID", 89, 0 },
- { "DDR", 104, 0 },
- { "CONFIGID0", 176, 0 },
- { "CONFIGID1", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EPC5", 181, 0 },
- { "EPC6", 182, 0 },
- { "EPC7", 183, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EXCSAVE5", 213, 0 },
- { "EXCSAVE6", 214, 0 },
- { "EXCSAVE7", 215, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EPS5", 197, 0 },
- { "EPS6", 198, 0 },
- { "EPS7", 199, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "PREFCTL", 40, 0 },
- { "RASID", 90, 0 },
- { "ITLBCFG", 91, 0 },
- { "DTLBCFG", 92, 0 },
- { "CPENABLE", 224, 0 },
- { "SCOMPARE1", 12, 0 },
- { "ATOMCTL", 99, 0 },
- { "THREADPTR", 231, 1 },
- { "AE_OVF_SAR", 240, 1 },
- { "AE_BITHEAD", 241, 1 },
- { "AE_TS_FTS_BU_BP", 242, 1 },
- { "AE_SD_NO", 243, 1 },
- { "AE_CBEGIN0", 246, 1 },
- { "AE_CEND0", 247, 1 },
- { "EXPSTATE", 230, 1 }
-};
-
-#define NUM_SYSREGS 78
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 247
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 22, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EPC5", 32, 0 },
- { "EPC6", 32, 0 },
- { "EPC7", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EXCSAVE5", 32, 0 },
- { "EXCSAVE6", 32, 0 },
- { "EXCSAVE7", 32, 0 },
- { "EPS2", 15, 0 },
- { "EPS3", 15, 0 },
- { "EPS4", 15, 0 },
- { "EPS5", 15, 0 },
- { "EPS6", 15, 0 },
- { "EPS7", 15, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSRING", 2, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 3, 0 },
- { "WindowStart", 8, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "THREADPTR", 32, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "ACC", 40, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 22, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "PREFCTL", 9, 0 },
- { "ASID3", 8, 0 },
- { "ASID2", 8, 0 },
- { "ASID1", 8, 0 },
- { "INSTPGSZID6", 1, 0 },
- { "INSTPGSZID5", 1, 0 },
- { "INSTPGSZID4", 2, 0 },
- { "DATAPGSZID6", 1, 0 },
- { "DATAPGSZID5", 1, 0 },
- { "DATAPGSZID4", 2, 0 },
- { "PTBASE", 10, 0 },
- { "CPENABLE", 8, 0 },
- { "SCOMPARE1", 32, 0 },
- { "ATOMCTL", 6, 0 },
- { "ERI_RAW_INTERLOCK", 1, 0 },
- { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR },
- { "AE_SAR", 6, 0 },
- { "AE_BITHEAD", 32, 0 },
- { "AE_BITPTR", 4, 0 },
- { "AE_BITSUSED", 4, 0 },
- { "AE_TABLESIZE", 4, 0 },
- { "AE_FIRST_TS", 4, 0 },
- { "AE_NEXTOFFSET", 27, 0 },
- { "AE_SEARCHDONE", 1, 0 },
- { "AE_CBEGIN0", 32, 0 },
- { "AE_CEND0", 32, 0 },
- { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
-};
-
-#define NUM_STATES 89
-
-enum xtensa_state_id {
- STATE_LCOUNT,
- STATE_PC,
- STATE_ICOUNT,
- STATE_DDR,
- STATE_INTERRUPT,
- STATE_CCOUNT,
- STATE_XTSYNC,
- STATE_VECBASE,
- STATE_EPC1,
- STATE_EPC2,
- STATE_EPC3,
- STATE_EPC4,
- STATE_EPC5,
- STATE_EPC6,
- STATE_EPC7,
- STATE_EXCSAVE1,
- STATE_EXCSAVE2,
- STATE_EXCSAVE3,
- STATE_EXCSAVE4,
- STATE_EXCSAVE5,
- STATE_EXCSAVE6,
- STATE_EXCSAVE7,
- STATE_EPS2,
- STATE_EPS3,
- STATE_EPS4,
- STATE_EPS5,
- STATE_EPS6,
- STATE_EPS7,
- STATE_EXCCAUSE,
- STATE_PSINTLEVEL,
- STATE_PSUM,
- STATE_PSWOE,
- STATE_PSRING,
- STATE_PSEXCM,
- STATE_DEPC,
- STATE_EXCVADDR,
- STATE_WindowBase,
- STATE_WindowStart,
- STATE_PSCALLINC,
- STATE_PSOWB,
- STATE_LBEG,
- STATE_LEND,
- STATE_SAR,
- STATE_THREADPTR,
- STATE_MISC0,
- STATE_MISC1,
- STATE_ACC,
- STATE_InOCDMode,
- STATE_INTENABLE,
- STATE_DBREAKA0,
- STATE_DBREAKC0,
- STATE_DBREAKA1,
- STATE_DBREAKC1,
- STATE_IBREAKA0,
- STATE_IBREAKA1,
- STATE_IBREAKENABLE,
- STATE_ICOUNTLEVEL,
- STATE_DEBUGCAUSE,
- STATE_DBNUM,
- STATE_CCOMPARE0,
- STATE_CCOMPARE1,
- STATE_CCOMPARE2,
- STATE_PREFCTL,
- STATE_ASID3,
- STATE_ASID2,
- STATE_ASID1,
- STATE_INSTPGSZID6,
- STATE_INSTPGSZID5,
- STATE_INSTPGSZID4,
- STATE_DATAPGSZID6,
- STATE_DATAPGSZID5,
- STATE_DATAPGSZID4,
- STATE_PTBASE,
- STATE_CPENABLE,
- STATE_SCOMPARE1,
- STATE_ATOMCTL,
- STATE_ERI_RAW_INTERLOCK,
- STATE_AE_OVERFLOW,
- STATE_AE_SAR,
- STATE_AE_BITHEAD,
- STATE_AE_BITPTR,
- STATE_AE_BITSUSED,
- STATE_AE_TABLESIZE,
- STATE_AE_FIRST_TS,
- STATE_AE_NEXTOFFSET,
- STATE_AE_SEARCHDONE,
- STATE_AE_CBEGIN0,
- STATE_AE_CEND0,
- STATE_EXPSTATE
-};
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
-}
-
-static unsigned
-Field_w_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- return tie_t;
-}
-
-static void
-Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf333ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf333ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_ftsf359ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf359ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_ftsf355ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf355ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf354ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf354ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
-}
-
-static unsigned
-Field_ftsf357ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf357ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9);
- tie_t = (val << 26) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 27) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf347ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf347ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10);
-}
-
-static unsigned
-Field_ftsf345ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf345ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 26) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
- tie_t = (val << 22) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf358ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf358ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 20) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf93ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf93ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 26) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
- tie_t = (val << 22) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf55_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf55_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf121ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf121ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 21) >> 24;
- insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf91_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 22) >> 27;
- insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_ftsf351_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf351_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 21) >> 26;
- insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 20) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf20ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf20ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf356ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf356ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf62ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf62ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
-}
-
-static unsigned
-Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf352ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf352ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 20) >> 23;
- insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 20) >> 23;
- insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf123ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf123ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
- tie_t = (val << 23) >> 29;
- insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 29) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf117ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf117ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf68ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf68ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- tie_t = (val << 28) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf61_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf61_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf83ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf83ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 25) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf70ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf70ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf74ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf74ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf85ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf85ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf102ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf102ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 23) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- tie_t = (val << 26) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_ftsf335_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf335_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
-}
-
-static unsigned
-Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf208ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf208ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf340ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf340ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld69_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld68_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld19_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld74_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld66_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld90_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld88_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld65_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld79_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x780000) | (tie_t << 19);
-}
-
-static unsigned
-Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
-}
-
-static unsigned
-Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf280_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf280_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf288_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf288_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
-}
-
-static unsigned
-Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x380) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf211ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf211ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 21) >> 29;
- insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
- tie_t = (val << 17) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20);
- return tie_t;
-}
-
-static void
-Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
- tie_t = (val << 18) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
- tie_t = (val << 26) >> 31;
- insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
-}
-
-static unsigned
-Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 21) >> 29;
- insn[0] = (insn[0] & ~0x380000) | (tie_t << 19);
- tie_t = (val << 17) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf287ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf287ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 23) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
- tie_t = (val << 22) >> 31;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
-}
-
-static unsigned
-Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 26) >> 27;
- insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf285ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf285ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 23) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
- tie_t = (val << 21) >> 30;
- insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
-}
-
-static unsigned
-Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 23) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
- tie_t = (val << 20) >> 29;
- insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
-}
-
-static unsigned
-Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 28) >> 29;
- insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 14) | ((insn[0] << 11) >> 18);
- return tie_t;
-}
-
-static void
-Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 18) >> 18;
- insn[0] = (insn[0] & ~0x1fff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf309_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf309_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf327ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf327ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
- tie_t = (val << 21) >> 30;
- insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
-}
-
-static unsigned
-Field_ftsf363ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf363ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24);
-}
-
-static unsigned
-Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf373ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf373ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_ftsf376ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf376ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 21) >> 29;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_ftsf370ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf370ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x18000) | (tie_t << 15);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
-}
-
-static unsigned
-Field_ftsf378ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf378ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf217ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf217ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf305ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf305ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf307ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf307ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
- tie_t = (val << 27) >> 29;
- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf379ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf379ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
- tie_t = (val << 29) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
- return tie_t;
-}
-
-static void
-Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 19) >> 19;
- insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf315_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf315_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld52_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
-}
-
-static unsigned
-Field_combined1e9fefee_fld96_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined1e9fefee_fld96_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_combined1e9fefee_fld98_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_combined1e9fefee_fld98_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld49_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld50_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld40_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf362_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf362_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_op0_s4_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s4_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
-}
-
-static unsigned
-Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30);
- return tie_t;
-}
-
-static void
-Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x18000) | (tie_t << 15);
-}
-
-static unsigned
-Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld47_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
- return tie_t;
-}
-
-static void
-Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
-}
-
-static unsigned
-Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
- return tie_t;
-}
-
-static void
-Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
- tie_t = (val << 19) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf289ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf289ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
- tie_t = (val << 19) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20);
- return tie_t;
-}
-
-static void
-Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7);
- tie_t = (val << 19) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 24) >> 31;
- insn[0] = (insn[0] & ~0x200000) | (tie_t << 21);
-}
-
-static unsigned
-Field_ftsf386ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf386ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 26) >> 27;
- insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22);
-}
-
-static unsigned
-Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
- tie_t = (val << 18) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 24) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
- tie_t = (val << 21) >> 29;
- insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
-}
-
-static unsigned
-Field_ftsf382ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf382ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf291ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf291ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 24) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 24) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
-}
-
-static unsigned
-Field_ftsf383ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf383ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 28) >> 29;
- insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf293ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf293ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
- tie_t = (val << 24) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
-}
-
-static unsigned
-Field_ftsf384ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf384ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22);
- return tie_t;
-}
-
-static void
-Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 22) >> 22;
- insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf387ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf387ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
- tie_t = (val << 25) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf319ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22);
- return tie_t;
-}
-
-static void
-Field_ftsf319ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 22) >> 22;
- insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7);
- tie_t = (val << 21) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf388ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf388ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
- tie_t = (val << 27) >> 29;
- insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
-}
-
-static unsigned
-Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
- tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22);
- return tie_t;
-}
-
-static void
-Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 22) >> 22;
- insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7);
- tie_t = (val << 21) >> 31;
- insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
- tie_t = (val << 20) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf389ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf389ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
- tie_t = (val << 28) >> 29;
- insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24);
-}
-
-static unsigned
-Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
-}
-
-static unsigned
-Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20);
- return tie_t;
-}
-
-static void
-Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7);
- tie_t = (val << 19) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 23) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
- tie_t = (val << 21) >> 30;
- insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25);
-}
-
-static unsigned
-Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
- tie_t = (val << 22) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
- tie_t = (val << 18) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld123_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld121_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld28_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld127_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld46_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 5) >> 24);
- tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x7800) | (tie_t << 11);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0x7f80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 9) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0x7ff800) | (tie_t << 11);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
-}
-
-static unsigned
-Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x78000) | (tie_t << 15);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
- return tie_t;
-}
-
-static void
-Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
-}
-
-static unsigned
-Field_y_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31);
- return tie_t;
-}
-
-static void
-Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40000) | (tie_t << 18);
-}
-
-static unsigned
-Field_x_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
- return tie_t;
-}
-
-static void
-Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
-}
-
-static unsigned
-Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- tie_t = (val << 29) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
- return tie_t;
-}
-
-static void
-Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
-}
-
-static unsigned
-Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
- return tie_t;
-}
-
-static void
-Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
-}
-
-static unsigned
-Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
- return tie_t;
-}
-
-static void
-Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
-}
-
-static unsigned
-Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- return tie_t;
-}
-
-static void
-Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600000) | (tie_t << 21);
-}
-
-static unsigned
-Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
- return tie_t;
-}
-
-static void
-Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
-}
-
-static unsigned
-Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
- return tie_t;
-}
-
-static void
-Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
-}
-
-static unsigned
-Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- return tie_t;
-}
-
-static void
-Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
-}
-
-static unsigned
-Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
-}
-
-static unsigned
-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
- return tie_t;
-}
-
-static void
-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 17) >> 17;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180000) | (tie_t << 19);
-}
-
-static unsigned
-Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26);
- return tie_t;
-}
-
-static void
-Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 26) >> 26;
- insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x60000) | (tie_t << 17);
- tie_t = (val << 26) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
-}
-
-static unsigned
-Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf11_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf11_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_ftsf11_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf11_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf11_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
- tie_t = (val << 29) >> 31;
- insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
-}
-
-static unsigned
-Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80000) | (tie_t << 19);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld37_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld37_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 11) | ((insn[0] << 14) >> 21);
- return tie_t;
-}
-
-static void
-Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 21) >> 21;
- insn[0] = (insn[0] & ~0x3ff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28);
- return tie_t;
-}
-
-static void
-Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29);
- return tie_t;
-}
-
-static void
-Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70000) | (tie_t << 16);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-static unsigned
-Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 1;
-}
-
-static unsigned
-Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 2;
-}
-
-static unsigned
-Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 3;
-}
-
-static unsigned
-Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-enum xtensa_field_id {
- FIELD_t,
- FIELD_bbi4,
- FIELD_bbi,
- FIELD_imm12,
- FIELD_imm8,
- FIELD_s,
- FIELD_imm12b,
- FIELD_imm16,
- FIELD_m,
- FIELD_n,
- FIELD_offset,
- FIELD_op0,
- FIELD_op1,
- FIELD_op2,
- FIELD_r,
- FIELD_sa4,
- FIELD_sae4,
- FIELD_sae,
- FIELD_sal,
- FIELD_sargt,
- FIELD_sas4,
- FIELD_sas,
- FIELD_sr,
- FIELD_st,
- FIELD_thi3,
- FIELD_imm4,
- FIELD_mn,
- FIELD_i,
- FIELD_imm6lo,
- FIELD_imm6hi,
- FIELD_imm7lo,
- FIELD_imm7hi,
- FIELD_z,
- FIELD_imm6,
- FIELD_imm7,
- FIELD_r3,
- FIELD_rbit2,
- FIELD_rhi,
- FIELD_t3,
- FIELD_tbit2,
- FIELD_tlo,
- FIELD_w,
- FIELD_y,
- FIELD_x,
- FIELD_t2,
- FIELD_s2,
- FIELD_r2,
- FIELD_t4,
- FIELD_s4,
- FIELD_r4,
- FIELD_t8,
- FIELD_s8,
- FIELD_r8,
- FIELD_xt_wbr15_imm,
- FIELD_xt_wbr18_imm,
- FIELD_ae_r3,
- FIELD_ae_s_non_samt,
- FIELD_ae_s3,
- FIELD_ae_r32,
- FIELD_ae_samt_s_t,
- FIELD_ae_r20,
- FIELD_ae_r10,
- FIELD_ae_s20,
- FIELD_ae_fld_ohba,
- FIELD_ae_fld_ohba2,
- FIELD_op0_s3,
- FIELD_ftsf11,
- FIELD_ftsf12,
- FIELD_ftsf13,
- FIELD_ftsf20ae_slot1,
- FIELD_ftsf21ae_slot1,
- FIELD_ftsf22ae_slot1,
- FIELD_ftsf23ae_slot1,
- FIELD_ftsf24ae_slot1,
- FIELD_ftsf25ae_slot1,
- FIELD_ftsf26ae_slot1,
- FIELD_ftsf27ae_slot1,
- FIELD_ftsf28ae_slot1,
- FIELD_ftsf29ae_slot1,
- FIELD_ftsf30ae_slot1,
- FIELD_ftsf31ae_slot1,
- FIELD_ftsf32ae_slot1,
- FIELD_ftsf33ae_slot1,
- FIELD_ftsf34ae_slot1,
- FIELD_ftsf35ae_slot1,
- FIELD_ftsf36ae_slot1,
- FIELD_ftsf37ae_slot1,
- FIELD_ftsf38ae_slot1,
- FIELD_ftsf40ae_slot1,
- FIELD_ftsf41ae_slot1,
- FIELD_ftsf42ae_slot1,
- FIELD_ftsf43ae_slot1,
- FIELD_ftsf45ae_slot1,
- FIELD_ftsf47ae_slot1,
- FIELD_ftsf48ae_slot1,
- FIELD_ftsf49ae_slot1,
- FIELD_ftsf50ae_slot1,
- FIELD_ftsf51ae_slot1,
- FIELD_ftsf52ae_slot1,
- FIELD_ftsf53ae_slot1,
- FIELD_ftsf54ae_slot1,
- FIELD_ftsf55,
- FIELD_ftsf56ae_slot1,
- FIELD_ftsf57ae_slot1,
- FIELD_ftsf58ae_slot1,
- FIELD_ftsf60ae_slot1,
- FIELD_ftsf61,
- FIELD_ftsf62ae_slot1,
- FIELD_ftsf63ae_slot1,
- FIELD_ftsf64ae_slot1,
- FIELD_ftsf66ae_slot1,
- FIELD_ftsf68ae_slot1,
- FIELD_ftsf69ae_slot1,
- FIELD_ftsf70ae_slot1,
- FIELD_ftsf71ae_slot1,
- FIELD_ftsf72ae_slot1,
- FIELD_ftsf73ae_slot1,
- FIELD_ftsf74ae_slot1,
- FIELD_ftsf75ae_slot1,
- FIELD_ftsf76ae_slot1,
- FIELD_ftsf77ae_slot1,
- FIELD_ftsf78ae_slot1,
- FIELD_ftsf79ae_slot1,
- FIELD_ftsf80ae_slot1,
- FIELD_ftsf81ae_slot1,
- FIELD_ftsf82ae_slot1,
- FIELD_ftsf83ae_slot1,
- FIELD_ftsf84ae_slot1,
- FIELD_ftsf85ae_slot1,
- FIELD_ftsf86ae_slot1,
- FIELD_ftsf87ae_slot1,
- FIELD_ftsf88ae_slot1,
- FIELD_ftsf89ae_slot1,
- FIELD_ftsf90ae_slot1,
- FIELD_ftsf91,
- FIELD_ftsf92ae_slot1,
- FIELD_ftsf93ae_slot1,
- FIELD_ftsf94ae_slot1,
- FIELD_ftsf96ae_slot1,
- FIELD_ftsf97ae_slot1,
- FIELD_ftsf99ae_slot1,
- FIELD_ftsf101ae_slot1,
- FIELD_ftsf102ae_slot1,
- FIELD_ftsf103ae_slot1,
- FIELD_ftsf106ae_slot1,
- FIELD_ftsf107ae_slot1,
- FIELD_ftsf108ae_slot1,
- FIELD_ftsf109ae_slot1,
- FIELD_ftsf110ae_slot1,
- FIELD_ftsf111ae_slot1,
- FIELD_ftsf112ae_slot1,
- FIELD_ftsf113ae_slot1,
- FIELD_ftsf114ae_slot1,
- FIELD_ftsf115ae_slot1,
- FIELD_ftsf116ae_slot1,
- FIELD_ftsf117ae_slot1,
- FIELD_ftsf118ae_slot1,
- FIELD_ftsf120ae_slot1,
- FIELD_ftsf121ae_slot1,
- FIELD_ftsf123ae_slot1,
- FIELD_ftsf124ae_slot1,
- FIELD_ftsf125ae_slot1,
- FIELD_ftsf126ae_slot1,
- FIELD_ftsf127ae_slot1,
- FIELD_ftsf128ae_slot1,
- FIELD_ftsf129ae_slot1,
- FIELD_ftsf130ae_slot1,
- FIELD_ftsf131ae_slot1,
- FIELD_ftsf132ae_slot1,
- FIELD_ftsf133ae_slot1,
- FIELD_ftsf134ae_slot1,
- FIELD_ftsf135ae_slot1,
- FIELD_ftsf136ae_slot1,
- FIELD_ftsf137ae_slot1,
- FIELD_ftsf138ae_slot1,
- FIELD_ftsf139ae_slot1,
- FIELD_ftsf140ae_slot1,
- FIELD_ftsf141ae_slot1,
- FIELD_ftsf142ae_slot1,
- FIELD_ftsf143ae_slot1,
- FIELD_ftsf144ae_slot1,
- FIELD_ftsf145ae_slot1,
- FIELD_ftsf146ae_slot1,
- FIELD_ftsf147ae_slot1,
- FIELD_ftsf148ae_slot1,
- FIELD_ftsf149ae_slot1,
- FIELD_ftsf150ae_slot1,
- FIELD_ftsf151ae_slot1,
- FIELD_ftsf152ae_slot1,
- FIELD_ftsf153ae_slot1,
- FIELD_ftsf154ae_slot1,
- FIELD_ftsf155ae_slot1,
- FIELD_ftsf156ae_slot1,
- FIELD_ftsf157ae_slot1,
- FIELD_ftsf158ae_slot1,
- FIELD_ftsf159ae_slot1,
- FIELD_ftsf160ae_slot1,
- FIELD_ftsf161ae_slot1,
- FIELD_ftsf162ae_slot1,
- FIELD_ftsf163ae_slot1,
- FIELD_ftsf164ae_slot1,
- FIELD_ftsf165ae_slot1,
- FIELD_ftsf166ae_slot1,
- FIELD_ftsf167ae_slot1,
- FIELD_ftsf168ae_slot1,
- FIELD_ftsf169ae_slot1,
- FIELD_ftsf170ae_slot1,
- FIELD_ftsf171ae_slot1,
- FIELD_ftsf172ae_slot1,
- FIELD_ftsf173ae_slot1,
- FIELD_ftsf174ae_slot1,
- FIELD_ftsf175ae_slot1,
- FIELD_ftsf176ae_slot1,
- FIELD_ftsf177ae_slot1,
- FIELD_ftsf178ae_slot1,
- FIELD_ftsf179ae_slot1,
- FIELD_ftsf180ae_slot1,
- FIELD_ftsf181ae_slot1,
- FIELD_ftsf182ae_slot1,
- FIELD_ftsf183ae_slot1,
- FIELD_ftsf184ae_slot1,
- FIELD_ftsf185ae_slot1,
- FIELD_ftsf186ae_slot1,
- FIELD_ftsf187ae_slot1,
- FIELD_ftsf188ae_slot1,
- FIELD_ftsf189ae_slot1,
- FIELD_ftsf190ae_slot1,
- FIELD_ftsf191ae_slot1,
- FIELD_ftsf192ae_slot1,
- FIELD_ftsf193ae_slot1,
- FIELD_ftsf194ae_slot1,
- FIELD_ftsf195ae_slot1,
- FIELD_ftsf196ae_slot1,
- FIELD_ftsf197ae_slot1,
- FIELD_ftsf198ae_slot1,
- FIELD_ftsf199ae_slot1,
- FIELD_ftsf200ae_slot1,
- FIELD_ftsf201ae_slot1,
- FIELD_ftsf202ae_slot1,
- FIELD_ftsf203ae_slot1,
- FIELD_ftsf204ae_slot1,
- FIELD_ftsf205ae_slot1,
- FIELD_ftsf206ae_slot1,
- FIELD_ftsf207ae_slot1,
- FIELD_ftsf208ae_slot1,
- FIELD_ftsf210ae_slot1,
- FIELD_ftsf333ae_slot1,
- FIELD_ftsf334ae_slot1,
- FIELD_ftsf335,
- FIELD_ftsf336ae_slot1,
- FIELD_ftsf337ae_slot1,
- FIELD_ftsf339ae_slot1,
- FIELD_ftsf340ae_slot1,
- FIELD_ftsf341ae_slot1,
- FIELD_ftsf342ae_slot1,
- FIELD_ftsf343ae_slot1,
- FIELD_ftsf344ae_slot1,
- FIELD_ftsf345ae_slot1,
- FIELD_ftsf347ae_slot1,
- FIELD_ftsf348ae_slot1,
- FIELD_ftsf349ae_slot1,
- FIELD_ftsf350ae_slot1,
- FIELD_ftsf351,
- FIELD_ftsf352ae_slot1,
- FIELD_ftsf354ae_slot1,
- FIELD_ftsf355ae_slot1,
- FIELD_ftsf356ae_slot1,
- FIELD_ftsf357ae_slot1,
- FIELD_ftsf358ae_slot1,
- FIELD_ftsf359ae_slot1,
- FIELD_op0_s4,
- FIELD_ftsf211ae_slot0,
- FIELD_ftsf212ae_slot0,
- FIELD_ftsf213ae_slot0,
- FIELD_ftsf214ae_slot0,
- FIELD_ftsf215ae_slot0,
- FIELD_ftsf217ae_slot0,
- FIELD_ftsf218ae_slot0,
- FIELD_ftsf219ae_slot0,
- FIELD_ftsf220ae_slot0,
- FIELD_ftsf221ae_slot0,
- FIELD_ftsf222ae_slot0,
- FIELD_ftsf223ae_slot0,
- FIELD_ftsf224ae_slot0,
- FIELD_ftsf225ae_slot0,
- FIELD_ftsf226ae_slot0,
- FIELD_ftsf227ae_slot0,
- FIELD_ftsf228ae_slot0,
- FIELD_ftsf229ae_slot0,
- FIELD_ftsf230ae_slot0,
- FIELD_ftsf231ae_slot0,
- FIELD_ftsf232ae_slot0,
- FIELD_ftsf233ae_slot0,
- FIELD_ftsf234ae_slot0,
- FIELD_ftsf235ae_slot0,
- FIELD_ftsf236ae_slot0,
- FIELD_ftsf237ae_slot0,
- FIELD_ftsf238ae_slot0,
- FIELD_ftsf239ae_slot0,
- FIELD_ftsf240ae_slot0,
- FIELD_ftsf241ae_slot0,
- FIELD_ftsf242ae_slot0,
- FIELD_ftsf243ae_slot0,
- FIELD_ftsf244ae_slot0,
- FIELD_ftsf245ae_slot0,
- FIELD_ftsf246ae_slot0,
- FIELD_ftsf247ae_slot0,
- FIELD_ftsf248ae_slot0,
- FIELD_ftsf249ae_slot0,
- FIELD_ftsf250ae_slot0,
- FIELD_ftsf251ae_slot0,
- FIELD_ftsf252ae_slot0,
- FIELD_ftsf253ae_slot0,
- FIELD_ftsf254ae_slot0,
- FIELD_ftsf255ae_slot0,
- FIELD_ftsf256ae_slot0,
- FIELD_ftsf257ae_slot0,
- FIELD_ftsf258ae_slot0,
- FIELD_ftsf259ae_slot0,
- FIELD_ftsf260ae_slot0,
- FIELD_ftsf261ae_slot0,
- FIELD_ftsf262ae_slot0,
- FIELD_ftsf263ae_slot0,
- FIELD_ftsf264ae_slot0,
- FIELD_ftsf265ae_slot0,
- FIELD_ftsf266ae_slot0,
- FIELD_ftsf267ae_slot0,
- FIELD_ftsf268ae_slot0,
- FIELD_ftsf269ae_slot0,
- FIELD_ftsf270ae_slot0,
- FIELD_ftsf271ae_slot0,
- FIELD_ftsf272ae_slot0,
- FIELD_ftsf273ae_slot0,
- FIELD_ftsf274ae_slot0,
- FIELD_ftsf275ae_slot0,
- FIELD_ftsf276ae_slot0,
- FIELD_ftsf277ae_slot0,
- FIELD_ftsf278ae_slot0,
- FIELD_ftsf279ae_slot0,
- FIELD_ftsf280,
- FIELD_ftsf281ae_slot0,
- FIELD_ftsf282ae_slot0,
- FIELD_ftsf284ae_slot0,
- FIELD_ftsf285ae_slot0,
- FIELD_ftsf287ae_slot0,
- FIELD_ftsf288,
- FIELD_ftsf289ae_slot0,
- FIELD_ftsf290ae_slot0,
- FIELD_ftsf291ae_slot0,
- FIELD_ftsf292ae_slot0,
- FIELD_ftsf293ae_slot0,
- FIELD_ftsf294ae_slot0,
- FIELD_ftsf295ae_slot0,
- FIELD_ftsf296ae_slot0,
- FIELD_ftsf297ae_slot0,
- FIELD_ftsf298ae_slot0,
- FIELD_ftsf300ae_slot0,
- FIELD_ftsf302ae_slot0,
- FIELD_ftsf304ae_slot0,
- FIELD_ftsf305ae_slot0,
- FIELD_ftsf306ae_slot0,
- FIELD_ftsf307ae_slot0,
- FIELD_ftsf308ae_slot0,
- FIELD_ftsf309,
- FIELD_ftsf310ae_slot0,
- FIELD_ftsf311ae_slot0,
- FIELD_ftsf312ae_slot0,
- FIELD_ftsf313ae_slot0,
- FIELD_ftsf314ae_slot0,
- FIELD_ftsf315,
- FIELD_ftsf316ae_slot0,
- FIELD_ftsf317ae_slot0,
- FIELD_ftsf319ae_slot0,
- FIELD_ftsf320ae_slot0,
- FIELD_ftsf322ae_slot0,
- FIELD_ftsf323ae_slot0,
- FIELD_ftsf324ae_slot0,
- FIELD_ftsf325ae_slot0,
- FIELD_ftsf326ae_slot0,
- FIELD_ftsf327ae_slot0,
- FIELD_ftsf328ae_slot0,
- FIELD_ftsf329ae_slot0,
- FIELD_ftsf360ae_slot0,
- FIELD_ftsf361ae_slot0,
- FIELD_ftsf362,
- FIELD_ftsf363ae_slot0,
- FIELD_ftsf364ae_slot0,
- FIELD_ftsf366ae_slot0,
- FIELD_ftsf368ae_slot0,
- FIELD_ftsf370ae_slot0,
- FIELD_ftsf373ae_slot0,
- FIELD_ftsf376ae_slot0,
- FIELD_ftsf378ae_slot0,
- FIELD_ftsf379ae_slot0,
- FIELD_ftsf382ae_slot0,
- FIELD_ftsf383ae_slot0,
- FIELD_ftsf384ae_slot0,
- FIELD_ftsf386ae_slot0,
- FIELD_ftsf387ae_slot0,
- FIELD_ftsf388ae_slot0,
- FIELD_ftsf389ae_slot0,
- FIELD_ae_mul32x24fld,
- FIELD_op0_s4_s4,
- FIELD_combined2c0b5f72_fld28,
- FIELD_combined2c0b5f72_fld37,
- FIELD_combined2c0b5f72_fld39,
- FIELD_combined2c0b5f72_fld40,
- FIELD_combined2c0b5f72_fld46,
- FIELD_combined2c0b5f72_fld47,
- FIELD_combined2c0b5f72_fld49,
- FIELD_combined2c0b5f72_fld50,
- FIELD_combined2c0b5f72_fld52,
- FIELD_combined2c0b5f72_fld121,
- FIELD_combined2c0b5f72_fld123,
- FIELD_combined2c0b5f72_fld127,
- FIELD_combined2c0b5f72_fld133ae_slot0,
- FIELD_combined2c0b5f72_fld134ae_slot0,
- FIELD_combined2c0b5f72_fld135ae_slot0,
- FIELD_combined2c0b5f72_fld136ae_slot0,
- FIELD_combined2c0b5f72_fld137ae_slot0,
- FIELD_combined2c0b5f72_fld138ae_slot0,
- FIELD_combined2c0b5f72_fld139ae_slot0,
- FIELD_combined2c0b5f72_fld140ae_slot0,
- FIELD_combined2c0b5f72_fld141ae_slot0,
- FIELD_combined2c0b5f72_fld142ae_slot0,
- FIELD_combined2c0b5f72_fld143ae_slot0,
- FIELD_combined2c0b5f72_fld144ae_slot0,
- FIELD_combined2c0b5f72_fld145ae_slot0,
- FIELD_combined2c0b5f72_fld146ae_slot0,
- FIELD_combined2c0b5f72_fld148ae_slot0,
- FIELD_combined2c0b5f72_fld149ae_slot0,
- FIELD_op0_s4_s4_s4,
- FIELD_combined1e9fefee_fld96,
- FIELD_combined1e9fefee_fld98,
- FIELD_combined1e9fefee_fld106ae_slot0,
- FIELD_combined1e9fefee_fld107ae_slot0,
- FIELD_combined1e9fefee_fld108ae_slot0,
- FIELD_combined1e9fefee_fld109ae_slot0,
- FIELD_op0_s3_s3,
- FIELD_combined2c0b5f72_fld19,
- FIELD_combined2c0b5f72_fld22,
- FIELD_combined2c0b5f72_fld24,
- FIELD_combined2c0b5f72_fld65,
- FIELD_combined2c0b5f72_fld66,
- FIELD_combined2c0b5f72_fld68,
- FIELD_combined2c0b5f72_fld69,
- FIELD_combined2c0b5f72_fld74,
- FIELD_combined2c0b5f72_fld79,
- FIELD_combined2c0b5f72_fld88,
- FIELD_combined2c0b5f72_fld90,
- FIELD_combined2c0b5f72_fld91,
- FIELD_combined2c0b5f72_fld131ae_slot1,
- FIELD_combined2c0b5f72_fld132ae_slot1,
- FIELD_combined2c0b5f72_fld147ae_slot1,
- FIELD_bitindex,
- FIELD_s3to1,
- FIELD__ar0,
- FIELD__ar4,
- FIELD__ar8,
- FIELD__ar12,
- FIELD__mr0,
- FIELD__mr1,
- FIELD__mr2,
- FIELD__mr3,
- FIELD__bt16,
- FIELD__bs16,
- FIELD__br16,
- FIELD__brall
-};
-
-\f
-/* Functional units. */
-
-static xtensa_funcUnit_internal funcUnits[] = {
- { "ae_add32", 1 },
- { "ae_shift32x4", 1 },
- { "ae_shift32x5", 1 },
- { "ae_subshift", 1 }
-};
-
-enum xtensa_funcUnit_id {
- FUNCUNIT_ae_add32,
- FUNCUNIT_ae_shift32x4,
- FUNCUNIT_ae_shift32x5,
- FUNCUNIT_ae_subshift
-};
-
-\f
-/* Register files. */
-
-enum xtensa_regfile_id {
- REGFILE_AR,
- REGFILE_MR,
- REGFILE_BR,
- REGFILE_AE_PR,
- REGFILE_AE_QR,
- REGFILE_BR2,
- REGFILE_BR4,
- REGFILE_BR8,
- REGFILE_BR16
-};
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", REGFILE_AR, 32, 32 },
- { "MR", "m", REGFILE_MR, 32, 4 },
- { "BR", "b", REGFILE_BR, 1, 16 },
- { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
- { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
- { "BR2", "b", REGFILE_BR, 2, 8 },
- { "BR4", "b", REGFILE_BR, 4, 4 },
- { "BR8", "b", REGFILE_BR, 8, 2 },
- { "BR16", "b", REGFILE_BR, 16, 1 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
- { "ERI_RD_Out", 14, 0, 0, 'o' },
- { "ERI_RD_In", 32, 0, 1, 'i' },
- { "ERI_RD_Rdy", 1, 0, 0, 'i' },
- { "ERI_WR_Out", 46, 0, 2, 'o' },
- { "ERI_WR_In", 1, 0, 3, 'i' },
- { "IMPWIRE", 32, 0, 4, 'i' }
-};
-
-enum xtensa_interface_id {
- INTERFACE_ERI_RD_Out,
- INTERFACE_ERI_RD_In,
- INTERFACE_ERI_RD_Rdy,
- INTERFACE_ERI_WR_Out,
- INTERFACE_ERI_WR_In,
- INTERFACE_IMPWIRE
-};
-
-
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
-{
- *valp += 2;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
-{
- int error;
- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
- *valp = *valp & 1;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_out_0;
- unsigned soffsetx4_in_0;
- soffsetx4_in_0 = *valp & 0x3ffff;
- soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
- *valp = soffsetx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
-{
- unsigned soffsetx4_in_0;
- unsigned soffsetx4_out_0;
- soffsetx4_out_0 = *valp;
- soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
- *valp = soffsetx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_out_0;
- unsigned uimm12x8_in_0;
- uimm12x8_in_0 = *valp & 0xfff;
- uimm12x8_out_0 = uimm12x8_in_0 << 3;
- *valp = uimm12x8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
-{
- unsigned uimm12x8_in_0;
- unsigned uimm12x8_out_0;
- uimm12x8_out_0 = *valp;
- uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
- *valp = uimm12x8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_decode (uint32 *valp)
-{
- unsigned simm4_out_0;
- unsigned simm4_in_0;
- simm4_in_0 = *valp & 0xf;
- simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
- *valp = simm4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_encode (uint32 *valp)
-{
- unsigned simm4_in_0;
- unsigned simm4_out_0;
- simm4_out_0 = *valp;
- simm4_in_0 = (simm4_out_0 & 0xf);
- *valp = simm4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_out_0;
- unsigned immrx4_in_0;
- immrx4_in_0 = *valp & 0xf;
- immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
- *valp = immrx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
-{
- unsigned immrx4_in_0;
- unsigned immrx4_out_0;
- immrx4_out_0 = *valp;
- immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
- *valp = immrx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_out_0;
- unsigned lsi4x4_in_0;
- lsi4x4_in_0 = *valp & 0xf;
- lsi4x4_out_0 = lsi4x4_in_0 << 2;
- *valp = lsi4x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
-{
- unsigned lsi4x4_in_0;
- unsigned lsi4x4_out_0;
- lsi4x4_out_0 = *valp;
- lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
- *valp = lsi4x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_decode (uint32 *valp)
-{
- unsigned simm7_out_0;
- unsigned simm7_in_0;
- simm7_in_0 = *valp & 0x7f;
- simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
- *valp = simm7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_encode (uint32 *valp)
-{
- unsigned simm7_in_0;
- unsigned simm7_out_0;
- simm7_out_0 = *valp;
- simm7_in_0 = (simm7_out_0 & 0x7f);
- *valp = simm7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_out_0;
- unsigned uimm6_in_0;
- uimm6_in_0 = *valp & 0x3f;
- uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
- *valp = uimm6_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
-{
- unsigned uimm6_in_0;
- unsigned uimm6_out_0;
- uimm6_out_0 = *valp;
- uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
- *valp = uimm6_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_out_0;
- unsigned ai4const_in_0;
- ai4const_in_0 = *valp & 0xf;
- ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
- *valp = ai4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
-{
- unsigned ai4const_in_0;
- unsigned ai4const_out_0;
- ai4const_out_0 = *valp;
- switch (ai4const_out_0)
- {
- case 0xffffffff: ai4const_in_0 = 0; break;
- case 0x1: ai4const_in_0 = 0x1; break;
- case 0x2: ai4const_in_0 = 0x2; break;
- case 0x3: ai4const_in_0 = 0x3; break;
- case 0x4: ai4const_in_0 = 0x4; break;
- case 0x5: ai4const_in_0 = 0x5; break;
- case 0x6: ai4const_in_0 = 0x6; break;
- case 0x7: ai4const_in_0 = 0x7; break;
- case 0x8: ai4const_in_0 = 0x8; break;
- case 0x9: ai4const_in_0 = 0x9; break;
- case 0xa: ai4const_in_0 = 0xa; break;
- case 0xb: ai4const_in_0 = 0xb; break;
- case 0xc: ai4const_in_0 = 0xc; break;
- case 0xd: ai4const_in_0 = 0xd; break;
- case 0xe: ai4const_in_0 = 0xe; break;
- default: ai4const_in_0 = 0xf; break;
- }
- *valp = ai4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_decode (uint32 *valp)
-{
- unsigned b4const_out_0;
- unsigned b4const_in_0;
- b4const_in_0 = *valp & 0xf;
- b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
- *valp = b4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_encode (uint32 *valp)
-{
- unsigned b4const_in_0;
- unsigned b4const_out_0;
- b4const_out_0 = *valp;
- switch (b4const_out_0)
- {
- case 0xffffffff: b4const_in_0 = 0; break;
- case 0x1: b4const_in_0 = 0x1; break;
- case 0x2: b4const_in_0 = 0x2; break;
- case 0x3: b4const_in_0 = 0x3; break;
- case 0x4: b4const_in_0 = 0x4; break;
- case 0x5: b4const_in_0 = 0x5; break;
- case 0x6: b4const_in_0 = 0x6; break;
- case 0x7: b4const_in_0 = 0x7; break;
- case 0x8: b4const_in_0 = 0x8; break;
- case 0xa: b4const_in_0 = 0x9; break;
- case 0xc: b4const_in_0 = 0xa; break;
- case 0x10: b4const_in_0 = 0xb; break;
- case 0x20: b4const_in_0 = 0xc; break;
- case 0x40: b4const_in_0 = 0xd; break;
- case 0x80: b4const_in_0 = 0xe; break;
- default: b4const_in_0 = 0xf; break;
- }
- *valp = b4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_out_0;
- unsigned b4constu_in_0;
- b4constu_in_0 = *valp & 0xf;
- b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
- *valp = b4constu_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
-{
- unsigned b4constu_in_0;
- unsigned b4constu_out_0;
- b4constu_out_0 = *valp;
- switch (b4constu_out_0)
- {
- case 0x8000: b4constu_in_0 = 0; break;
- case 0x10000: b4constu_in_0 = 0x1; break;
- case 0x2: b4constu_in_0 = 0x2; break;
- case 0x3: b4constu_in_0 = 0x3; break;
- case 0x4: b4constu_in_0 = 0x4; break;
- case 0x5: b4constu_in_0 = 0x5; break;
- case 0x6: b4constu_in_0 = 0x6; break;
- case 0x7: b4constu_in_0 = 0x7; break;
- case 0x8: b4constu_in_0 = 0x8; break;
- case 0xa: b4constu_in_0 = 0x9; break;
- case 0xc: b4constu_in_0 = 0xa; break;
- case 0x10: b4constu_in_0 = 0xb; break;
- case 0x20: b4constu_in_0 = 0xc; break;
- case 0x40: b4constu_in_0 = 0xd; break;
- case 0x80: b4constu_in_0 = 0xe; break;
- default: b4constu_in_0 = 0xf; break;
- }
- *valp = b4constu_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_out_0;
- unsigned uimm8_in_0;
- uimm8_in_0 = *valp & 0xff;
- uimm8_out_0 = uimm8_in_0;
- *valp = uimm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
-{
- unsigned uimm8_in_0;
- unsigned uimm8_out_0;
- uimm8_out_0 = *valp;
- uimm8_in_0 = (uimm8_out_0 & 0xff);
- *valp = uimm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_out_0;
- unsigned uimm8x2_in_0;
- uimm8x2_in_0 = *valp & 0xff;
- uimm8x2_out_0 = uimm8x2_in_0 << 1;
- *valp = uimm8x2_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
-{
- unsigned uimm8x2_in_0;
- unsigned uimm8x2_out_0;
- uimm8x2_out_0 = *valp;
- uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
- *valp = uimm8x2_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_out_0;
- unsigned uimm8x4_in_0;
- uimm8x4_in_0 = *valp & 0xff;
- uimm8x4_out_0 = uimm8x4_in_0 << 2;
- *valp = uimm8x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
-{
- unsigned uimm8x4_in_0;
- unsigned uimm8x4_out_0;
- uimm8x4_out_0 = *valp;
- uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
- *valp = uimm8x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_out_0;
- unsigned uimm4x16_in_0;
- uimm4x16_in_0 = *valp & 0xf;
- uimm4x16_out_0 = uimm4x16_in_0 << 4;
- *valp = uimm4x16_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
-{
- unsigned uimm4x16_in_0;
- unsigned uimm4x16_out_0;
- uimm4x16_out_0 = *valp;
- uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
- *valp = uimm4x16_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_decode (uint32 *valp)
-{
- unsigned simm8_out_0;
- unsigned simm8_in_0;
- simm8_in_0 = *valp & 0xff;
- simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
- *valp = simm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_encode (uint32 *valp)
-{
- unsigned simm8_in_0;
- unsigned simm8_out_0;
- simm8_out_0 = *valp;
- simm8_in_0 = (simm8_out_0 & 0xff);
- *valp = simm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_out_0;
- unsigned simm8x256_in_0;
- simm8x256_in_0 = *valp & 0xff;
- simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
- *valp = simm8x256_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
-{
- unsigned simm8x256_in_0;
- unsigned simm8x256_out_0;
- simm8x256_out_0 = *valp;
- simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
- *valp = simm8x256_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_out_0;
- unsigned simm12b_in_0;
- simm12b_in_0 = *valp & 0xfff;
- simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
- *valp = simm12b_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
-{
- unsigned simm12b_in_0;
- unsigned simm12b_out_0;
- simm12b_out_0 = *valp;
- simm12b_in_0 = (simm12b_out_0 & 0xfff);
- *valp = simm12b_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_out_0;
- unsigned msalp32_in_0;
- msalp32_in_0 = *valp & 0x1f;
- msalp32_out_0 = 0x20 - msalp32_in_0;
- *valp = msalp32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
-{
- unsigned msalp32_in_0;
- unsigned msalp32_out_0;
- msalp32_out_0 = *valp;
- msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
- *valp = msalp32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_out_0;
- unsigned op2p1_in_0;
- op2p1_in_0 = *valp & 0xf;
- op2p1_out_0 = op2p1_in_0 + 0x1;
- *valp = op2p1_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
-{
- unsigned op2p1_in_0;
- unsigned op2p1_out_0;
- op2p1_out_0 = *valp;
- op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
- *valp = op2p1_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_decode (uint32 *valp)
-{
- unsigned label8_out_0;
- unsigned label8_in_0;
- label8_in_0 = *valp & 0xff;
- label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
- *valp = label8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_encode (uint32 *valp)
-{
- unsigned label8_in_0;
- unsigned label8_out_0;
- label8_out_0 = *valp;
- label8_in_0 = (label8_out_0 - 0x4) & 0xff;
- *valp = label8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
-{
- unsigned ulabel8_out_0;
- unsigned ulabel8_in_0;
- ulabel8_in_0 = *valp & 0xff;
- ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
- *valp = ulabel8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
-{
- unsigned ulabel8_in_0;
- unsigned ulabel8_out_0;
- ulabel8_out_0 = *valp;
- ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
- *valp = ulabel8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_decode (uint32 *valp)
-{
- unsigned label12_out_0;
- unsigned label12_in_0;
- label12_in_0 = *valp & 0xfff;
- label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
- *valp = label12_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_encode (uint32 *valp)
-{
- unsigned label12_in_0;
- unsigned label12_out_0;
- label12_out_0 = *valp;
- label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
- *valp = label12_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_decode (uint32 *valp)
-{
- unsigned soffset_out_0;
- unsigned soffset_in_0;
- soffset_in_0 = *valp & 0x3ffff;
- soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
- *valp = soffset_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_encode (uint32 *valp)
-{
- unsigned soffset_in_0;
- unsigned soffset_out_0;
- soffset_out_0 = *valp;
- soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
- *valp = soffset_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_out_0;
- unsigned uimm16x4_in_0;
- uimm16x4_in_0 = *valp & 0xffff;
- uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
- *valp = uimm16x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
-{
- unsigned uimm16x4_in_0;
- unsigned uimm16x4_out_0;
- uimm16x4_out_0 = *valp;
- uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
- *valp = uimm16x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_decode (uint32 *valp)
-{
- unsigned bbi_out_0;
- unsigned bbi_in_0;
- bbi_in_0 = *valp & 0x1f;
- bbi_out_0 = (0 << 5) | bbi_in_0;
- *valp = bbi_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_encode (uint32 *valp)
-{
- unsigned bbi_in_0;
- unsigned bbi_out_0;
- bbi_out_0 = *valp;
- bbi_in_0 = (bbi_out_0 & 0x1f);
- *valp = bbi_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_decode (uint32 *valp)
-{
- unsigned s_out_0;
- unsigned s_in_0;
- s_in_0 = *valp & 0xf;
- s_out_0 = (0 << 4) | s_in_0;
- *valp = s_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_encode (uint32 *valp)
-{
- unsigned s_in_0;
- unsigned s_out_0;
- s_out_0 = *valp;
- s_in_0 = (s_out_0 & 0xf);
- *valp = s_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_immt_decode (uint32 *valp)
-{
- unsigned immt_out_0;
- unsigned immt_in_0;
- immt_in_0 = *valp & 0xf;
- immt_out_0 = immt_in_0;
- *valp = immt_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immt_encode (uint32 *valp)
-{
- unsigned immt_in_0;
- unsigned immt_out_0;
- immt_out_0 = *valp;
- immt_in_0 = immt_out_0 & 0xf;
- *valp = immt_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR2_decode (uint32 *valp)
-{
- *valp = *valp << 1;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR2_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 1) != 0);
- *valp = *valp >> 1;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR4_decode (uint32 *valp)
-{
- *valp = *valp << 2;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR4_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 3) != 0);
- *valp = *valp >> 2;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR8_decode (uint32 *valp)
-{
- *valp = *valp << 3;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR8_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 7) != 0);
- *valp = *valp >> 3;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR16_decode (uint32 *valp)
-{
- *valp = *valp << 4;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR16_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 15) != 0);
- *valp = *valp >> 4;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_tp7_decode (uint32 *valp)
-{
- unsigned tp7_out_0;
- unsigned tp7_in_0;
- tp7_in_0 = *valp & 0xf;
- tp7_out_0 = tp7_in_0 + 0x7;
- *valp = tp7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_tp7_encode (uint32 *valp)
-{
- unsigned tp7_in_0;
- unsigned tp7_out_0;
- tp7_out_0 = *valp;
- tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
- *valp = tp7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
-{
- unsigned xt_wbr15_label_out_0;
- unsigned xt_wbr15_label_in_0;
- xt_wbr15_label_in_0 = *valp & 0x7fff;
- xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
- *valp = xt_wbr15_label_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
-{
- unsigned xt_wbr15_label_in_0;
- unsigned xt_wbr15_label_out_0;
- xt_wbr15_label_out_0 = *valp;
- xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_label_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
-{
- unsigned ae_samt32_out_0;
- unsigned ae_samt32_in_0;
- ae_samt32_in_0 = *valp & 0x1f;
- ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
- *valp = ae_samt32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
-{
- unsigned ae_samt32_in_0;
- unsigned ae_samt32_out_0;
- ae_samt32_out_0 = *valp;
- ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
- *valp = ae_samt32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 8);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
-{
- unsigned ae_lsimm16_out_0;
- unsigned ae_lsimm16_in_0;
- ae_lsimm16_in_0 = *valp & 0xf;
- ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
- *valp = ae_lsimm16_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
-{
- unsigned ae_lsimm16_in_0;
- unsigned ae_lsimm16_out_0;
- ae_lsimm16_out_0 = *valp;
- ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
- *valp = ae_lsimm16_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
-{
- unsigned ae_lsimm32_out_0;
- unsigned ae_lsimm32_in_0;
- ae_lsimm32_in_0 = *valp & 0xf;
- ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
- *valp = ae_lsimm32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
-{
- unsigned ae_lsimm32_in_0;
- unsigned ae_lsimm32_out_0;
- ae_lsimm32_out_0 = *valp;
- ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
- *valp = ae_lsimm32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
-{
- unsigned ae_lsimm64_out_0;
- unsigned ae_lsimm64_in_0;
- ae_lsimm64_in_0 = *valp & 0xf;
- ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
- *valp = ae_lsimm64_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
-{
- unsigned ae_lsimm64_in_0;
- unsigned ae_lsimm64_out_0;
- ae_lsimm64_out_0 = *valp;
- ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
- *valp = ae_lsimm64_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
-{
- unsigned ae_samt64_out_0;
- unsigned ae_samt64_in_0;
- ae_samt64_in_0 = *valp & 0x3f;
- ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
- *valp = ae_samt64_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
-{
- unsigned ae_samt64_in_0;
- unsigned ae_samt64_out_0;
- ae_samt64_out_0 = *valp;
- ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
- *valp = ae_samt64_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
-{
- unsigned ae_ohba_out_0;
- unsigned ae_ohba_in_0;
- ae_ohba_in_0 = *valp & 0xf;
- ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
- *valp = ae_ohba_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
-{
- unsigned ae_ohba_in_0;
- unsigned ae_ohba_out_0;
- ae_ohba_out_0 = *valp;
- ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
- *valp = ae_ohba_in_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", FIELD_imm12, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
- 0, 0 },
- { "simm4", FIELD_mn, -1, 0,
- 0,
- OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
- 0, 0 },
- { "arr", FIELD_r, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ars", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "art", FIELD_t, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ar0", FIELD__ar0, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
- 0, 0 },
- { "ar4", FIELD__ar4, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
- 0, 0 },
- { "ar8", FIELD__ar8, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
- 0, 0 },
- { "ar12", FIELD__ar12, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
- 0, 0 },
- { "ars_entry", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
- 0, 0 },
- { "immrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
- 0, 0 },
- { "lsi4x4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
- 0, 0 },
- { "simm7", FIELD_imm7, -1, 0,
- 0,
- OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
- 0, 0 },
- { "uimm6", FIELD_imm6, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
- 0, 0 },
- { "b4const", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
- 0, 0 },
- { "b4constu", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
- 0, 0 },
- { "uimm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
- 0, 0 },
- { "uimm8x2", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
- 0, 0 },
- { "uimmrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
- 0, 0 },
- { "simm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
- 0, 0 },
- { "simm8x256", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
- 0, 0 },
- { "simm12b", FIELD_imm12b, -1, 0,
- 0,
- OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
- 0, 0 },
- { "msalp32", FIELD_sal, -1, 0,
- 0,
- OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
- 0, 0 },
- { "op2p1", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
- 0, 0 },
- { "label8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", FIELD_imm12, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", FIELD_imm16, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "bbi", FIELD_bbi, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sae", FIELD_sae, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sas", FIELD_sas, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sargt", FIELD_sargt, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "s", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
- 0, 0 },
- { "mx", FIELD_x, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
- 0, 0 },
- { "my", FIELD_y, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
- 0, 0 },
- { "mw", FIELD_w, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
- 0, 0 },
- { "mr0", FIELD__mr0, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
- 0, 0 },
- { "mr1", FIELD__mr1, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
- 0, 0 },
- { "mr2", FIELD__mr2, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
- 0, 0 },
- { "mr3", FIELD__mr3, REGFILE_MR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
- 0, 0 },
- { "immt", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "imms", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "bt", FIELD_t, REGFILE_BR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
- 0, 0 },
- { "bs", FIELD_s, REGFILE_BR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
- 0, 0 },
- { "br", FIELD_r, REGFILE_BR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
- 0, 0 },
- { "bt2", FIELD_t2, REGFILE_BR, 2,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
- 0, 0 },
- { "bs2", FIELD_s2, REGFILE_BR, 2,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
- 0, 0 },
- { "br2", FIELD_r2, REGFILE_BR, 2,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
- 0, 0 },
- { "bt4", FIELD_t4, REGFILE_BR, 4,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
- 0, 0 },
- { "bs4", FIELD_s4, REGFILE_BR, 4,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
- 0, 0 },
- { "br4", FIELD_r4, REGFILE_BR, 4,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
- 0, 0 },
- { "bt8", FIELD_t8, REGFILE_BR, 8,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
- 0, 0 },
- { "bs8", FIELD_s8, REGFILE_BR, 8,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
- 0, 0 },
- { "br8", FIELD_r8, REGFILE_BR, 8,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
- 0, 0 },
- { "bt16", FIELD__bt16, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "bs16", FIELD__bs16, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "br16", FIELD__br16, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "brall", FIELD__brall, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "tp7", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "ae_samt32", FIELD_ftsf13, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
- 0, 0 },
- { "pr0", FIELD_ftsf11, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "qr0", FIELD_ftsf12, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "mac_qr0", FIELD_ftsf12, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "ae_lsimm16", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
- 0, 0 },
- { "ae_lsimm32", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
- 0, 0 },
- { "ae_lsimm64", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
- 0, 0 },
- { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
- 0, 0 },
- { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
- 0, 0 },
- { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
- 0, 0 },
- { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "bitindex", FIELD_bitindex, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
- { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
- { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
- { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
- { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
- { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
- { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
- { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
- { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
- { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
- { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
- { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
- { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
- { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
- { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
- { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
- { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
- { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
- { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
- { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
- { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
- { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
- { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
- { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
- { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf11", FIELD_ftsf11, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf20ae_slot1", FIELD_ftsf20ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf280", FIELD_ftsf280, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf285ae_slot0", FIELD_ftsf285ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf287ae_slot0", FIELD_ftsf287ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf288", FIELD_ftsf288, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf289ae_slot0", FIELD_ftsf289ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf291ae_slot0", FIELD_ftsf291ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf293ae_slot0", FIELD_ftsf293ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf305ae_slot0", FIELD_ftsf305ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf307ae_slot0", FIELD_ftsf307ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf309", FIELD_ftsf309, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf315", FIELD_ftsf315, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf319ae_slot0", FIELD_ftsf319ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf327ae_slot0", FIELD_ftsf327ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf362", FIELD_ftsf362, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf363ae_slot0", FIELD_ftsf363ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf370ae_slot0", FIELD_ftsf370ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf373ae_slot0", FIELD_ftsf373ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf376ae_slot0", FIELD_ftsf376ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf378ae_slot0", FIELD_ftsf378ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf379ae_slot0", FIELD_ftsf379ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf382ae_slot0", FIELD_ftsf382ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf383ae_slot0", FIELD_ftsf383ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf384ae_slot0", FIELD_ftsf384ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf386ae_slot0", FIELD_ftsf386ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf387ae_slot0", FIELD_ftsf387ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf388ae_slot0", FIELD_ftsf388ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf389ae_slot0", FIELD_ftsf389ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld28", FIELD_combined2c0b5f72_fld28, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld37", FIELD_combined2c0b5f72_fld37, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld39", FIELD_combined2c0b5f72_fld39, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld40", FIELD_combined2c0b5f72_fld40, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld46", FIELD_combined2c0b5f72_fld46, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld47", FIELD_combined2c0b5f72_fld47, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld49", FIELD_combined2c0b5f72_fld49, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld50", FIELD_combined2c0b5f72_fld50, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld52", FIELD_combined2c0b5f72_fld52, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld121", FIELD_combined2c0b5f72_fld121, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld123", FIELD_combined2c0b5f72_fld123, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld127", FIELD_combined2c0b5f72_fld127, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld133ae_slot0", FIELD_combined2c0b5f72_fld133ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld134ae_slot0", FIELD_combined2c0b5f72_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld135ae_slot0", FIELD_combined2c0b5f72_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld136ae_slot0", FIELD_combined2c0b5f72_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld137ae_slot0", FIELD_combined2c0b5f72_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld138ae_slot0", FIELD_combined2c0b5f72_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld139ae_slot0", FIELD_combined2c0b5f72_fld139ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld140ae_slot0", FIELD_combined2c0b5f72_fld140ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld141ae_slot0", FIELD_combined2c0b5f72_fld141ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld142ae_slot0", FIELD_combined2c0b5f72_fld142ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld143ae_slot0", FIELD_combined2c0b5f72_fld143ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld144ae_slot0", FIELD_combined2c0b5f72_fld144ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld145ae_slot0", FIELD_combined2c0b5f72_fld145ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld146ae_slot0", FIELD_combined2c0b5f72_fld146ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld148ae_slot0", FIELD_combined2c0b5f72_fld148ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld149ae_slot0", FIELD_combined2c0b5f72_fld149ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s4_s4_s4", FIELD_op0_s4_s4_s4, -1, 0, 0, 0, 0, 0, 0 },
- { "combined1e9fefee_fld96", FIELD_combined1e9fefee_fld96, -1, 0, 0, 0, 0, 0, 0 },
- { "combined1e9fefee_fld98", FIELD_combined1e9fefee_fld98, -1, 0, 0, 0, 0, 0, 0 },
- { "combined1e9fefee_fld106ae_slot0", FIELD_combined1e9fefee_fld106ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined1e9fefee_fld107ae_slot0", FIELD_combined1e9fefee_fld107ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined1e9fefee_fld108ae_slot0", FIELD_combined1e9fefee_fld108ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "combined1e9fefee_fld109ae_slot0", FIELD_combined1e9fefee_fld109ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld19", FIELD_combined2c0b5f72_fld19, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld22", FIELD_combined2c0b5f72_fld22, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld24", FIELD_combined2c0b5f72_fld24, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld65", FIELD_combined2c0b5f72_fld65, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld66", FIELD_combined2c0b5f72_fld66, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld68", FIELD_combined2c0b5f72_fld68, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld69", FIELD_combined2c0b5f72_fld69, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld74", FIELD_combined2c0b5f72_fld74, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld79", FIELD_combined2c0b5f72_fld79, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld88", FIELD_combined2c0b5f72_fld88, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld90", FIELD_combined2c0b5f72_fld90, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld91", FIELD_combined2c0b5f72_fld91, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld131ae_slot1", FIELD_combined2c0b5f72_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld132ae_slot1", FIELD_combined2c0b5f72_fld132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "combined2c0b5f72_fld147ae_slot1", FIELD_combined2c0b5f72_fld147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-enum xtensa_operand_id {
- OPERAND_soffsetx4,
- OPERAND_uimm12x8,
- OPERAND_simm4,
- OPERAND_arr,
- OPERAND_ars,
- OPERAND__ars_invisible,
- OPERAND_art,
- OPERAND_ar0,
- OPERAND_ar4,
- OPERAND_ar8,
- OPERAND_ar12,
- OPERAND_ars_entry,
- OPERAND_immrx4,
- OPERAND_lsi4x4,
- OPERAND_simm7,
- OPERAND_uimm6,
- OPERAND_ai4const,
- OPERAND_b4const,
- OPERAND_b4constu,
- OPERAND_uimm8,
- OPERAND_uimm8x2,
- OPERAND_uimm8x4,
- OPERAND_uimm4x16,
- OPERAND_uimmrx4,
- OPERAND_simm8,
- OPERAND_simm8x256,
- OPERAND_simm12b,
- OPERAND_msalp32,
- OPERAND_op2p1,
- OPERAND_label8,
- OPERAND_ulabel8,
- OPERAND_label12,
- OPERAND_soffset,
- OPERAND_uimm16x4,
- OPERAND_bbi,
- OPERAND_sae,
- OPERAND_sas,
- OPERAND_sargt,
- OPERAND_s,
- OPERAND_mx,
- OPERAND_my,
- OPERAND_mw,
- OPERAND_mr0,
- OPERAND_mr1,
- OPERAND_mr2,
- OPERAND_mr3,
- OPERAND_immt,
- OPERAND_imms,
- OPERAND_bt,
- OPERAND_bs,
- OPERAND_br,
- OPERAND_bt2,
- OPERAND_bs2,
- OPERAND_br2,
- OPERAND_bt4,
- OPERAND_bs4,
- OPERAND_br4,
- OPERAND_bt8,
- OPERAND_bs8,
- OPERAND_br8,
- OPERAND_bt16,
- OPERAND_bs16,
- OPERAND_br16,
- OPERAND_brall,
- OPERAND_tp7,
- OPERAND_xt_wbr15_label,
- OPERAND_xt_wbr18_label,
- OPERAND_ae_samt32,
- OPERAND_pr0,
- OPERAND_qr0,
- OPERAND_mac_qr0,
- OPERAND_ae_lsimm16,
- OPERAND_ae_lsimm32,
- OPERAND_ae_lsimm64,
- OPERAND_ae_samt64,
- OPERAND_ae_ohba,
- OPERAND_ae_ohba2,
- OPERAND_pr,
- OPERAND_cvt_pr,
- OPERAND_qr0_rw,
- OPERAND_mac_qr0_rw,
- OPERAND_qr1_w,
- OPERAND_mac_qr1_w,
- OPERAND_ps,
- OPERAND_alupppb_ps,
- OPERAND_bitindex,
- OPERAND_t,
- OPERAND_bbi4,
- OPERAND_imm12,
- OPERAND_imm8,
- OPERAND_imm12b,
- OPERAND_imm16,
- OPERAND_m,
- OPERAND_n,
- OPERAND_offset,
- OPERAND_op0,
- OPERAND_op1,
- OPERAND_op2,
- OPERAND_r,
- OPERAND_sa4,
- OPERAND_sae4,
- OPERAND_sal,
- OPERAND_sas4,
- OPERAND_sr,
- OPERAND_st,
- OPERAND_thi3,
- OPERAND_imm4,
- OPERAND_mn,
- OPERAND_i,
- OPERAND_imm6lo,
- OPERAND_imm6hi,
- OPERAND_imm7lo,
- OPERAND_imm7hi,
- OPERAND_z,
- OPERAND_imm6,
- OPERAND_imm7,
- OPERAND_r3,
- OPERAND_rbit2,
- OPERAND_rhi,
- OPERAND_t3,
- OPERAND_tbit2,
- OPERAND_tlo,
- OPERAND_w,
- OPERAND_y,
- OPERAND_x,
- OPERAND_t2,
- OPERAND_s2,
- OPERAND_r2,
- OPERAND_t4,
- OPERAND_s4,
- OPERAND_r4,
- OPERAND_t8,
- OPERAND_s8,
- OPERAND_r8,
- OPERAND_xt_wbr15_imm,
- OPERAND_xt_wbr18_imm,
- OPERAND_ae_r3,
- OPERAND_ae_s_non_samt,
- OPERAND_ae_s3,
- OPERAND_ae_r32,
- OPERAND_ae_samt_s_t,
- OPERAND_ae_r20,
- OPERAND_ae_r10,
- OPERAND_ae_s20,
- OPERAND_ae_fld_ohba,
- OPERAND_ae_fld_ohba2,
- OPERAND_op0_s3,
- OPERAND_ftsf11,
- OPERAND_ftsf12,
- OPERAND_ftsf13,
- OPERAND_ftsf20ae_slot1,
- OPERAND_ftsf21ae_slot1,
- OPERAND_ftsf22ae_slot1,
- OPERAND_ftsf23ae_slot1,
- OPERAND_ftsf24ae_slot1,
- OPERAND_ftsf25ae_slot1,
- OPERAND_ftsf26ae_slot1,
- OPERAND_ftsf27ae_slot1,
- OPERAND_ftsf28ae_slot1,
- OPERAND_ftsf29ae_slot1,
- OPERAND_ftsf30ae_slot1,
- OPERAND_ftsf31ae_slot1,
- OPERAND_ftsf32ae_slot1,
- OPERAND_ftsf33ae_slot1,
- OPERAND_ftsf34ae_slot1,
- OPERAND_ftsf35ae_slot1,
- OPERAND_ftsf36ae_slot1,
- OPERAND_ftsf37ae_slot1,
- OPERAND_ftsf38ae_slot1,
- OPERAND_ftsf40ae_slot1,
- OPERAND_ftsf41ae_slot1,
- OPERAND_ftsf42ae_slot1,
- OPERAND_ftsf43ae_slot1,
- OPERAND_ftsf45ae_slot1,
- OPERAND_ftsf47ae_slot1,
- OPERAND_ftsf48ae_slot1,
- OPERAND_ftsf49ae_slot1,
- OPERAND_ftsf50ae_slot1,
- OPERAND_ftsf51ae_slot1,
- OPERAND_ftsf52ae_slot1,
- OPERAND_ftsf53ae_slot1,
- OPERAND_ftsf54ae_slot1,
- OPERAND_ftsf55,
- OPERAND_ftsf56ae_slot1,
- OPERAND_ftsf57ae_slot1,
- OPERAND_ftsf58ae_slot1,
- OPERAND_ftsf60ae_slot1,
- OPERAND_ftsf61,
- OPERAND_ftsf62ae_slot1,
- OPERAND_ftsf63ae_slot1,
- OPERAND_ftsf64ae_slot1,
- OPERAND_ftsf66ae_slot1,
- OPERAND_ftsf68ae_slot1,
- OPERAND_ftsf69ae_slot1,
- OPERAND_ftsf70ae_slot1,
- OPERAND_ftsf71ae_slot1,
- OPERAND_ftsf72ae_slot1,
- OPERAND_ftsf73ae_slot1,
- OPERAND_ftsf74ae_slot1,
- OPERAND_ftsf75ae_slot1,
- OPERAND_ftsf76ae_slot1,
- OPERAND_ftsf77ae_slot1,
- OPERAND_ftsf78ae_slot1,
- OPERAND_ftsf79ae_slot1,
- OPERAND_ftsf80ae_slot1,
- OPERAND_ftsf81ae_slot1,
- OPERAND_ftsf82ae_slot1,
- OPERAND_ftsf83ae_slot1,
- OPERAND_ftsf84ae_slot1,
- OPERAND_ftsf85ae_slot1,
- OPERAND_ftsf86ae_slot1,
- OPERAND_ftsf87ae_slot1,
- OPERAND_ftsf88ae_slot1,
- OPERAND_ftsf89ae_slot1,
- OPERAND_ftsf90ae_slot1,
- OPERAND_ftsf91,
- OPERAND_ftsf92ae_slot1,
- OPERAND_ftsf93ae_slot1,
- OPERAND_ftsf94ae_slot1,
- OPERAND_ftsf96ae_slot1,
- OPERAND_ftsf97ae_slot1,
- OPERAND_ftsf99ae_slot1,
- OPERAND_ftsf101ae_slot1,
- OPERAND_ftsf102ae_slot1,
- OPERAND_ftsf103ae_slot1,
- OPERAND_ftsf106ae_slot1,
- OPERAND_ftsf107ae_slot1,
- OPERAND_ftsf108ae_slot1,
- OPERAND_ftsf109ae_slot1,
- OPERAND_ftsf110ae_slot1,
- OPERAND_ftsf111ae_slot1,
- OPERAND_ftsf112ae_slot1,
- OPERAND_ftsf113ae_slot1,
- OPERAND_ftsf114ae_slot1,
- OPERAND_ftsf115ae_slot1,
- OPERAND_ftsf116ae_slot1,
- OPERAND_ftsf117ae_slot1,
- OPERAND_ftsf118ae_slot1,
- OPERAND_ftsf120ae_slot1,
- OPERAND_ftsf121ae_slot1,
- OPERAND_ftsf123ae_slot1,
- OPERAND_ftsf124ae_slot1,
- OPERAND_ftsf125ae_slot1,
- OPERAND_ftsf126ae_slot1,
- OPERAND_ftsf127ae_slot1,
- OPERAND_ftsf128ae_slot1,
- OPERAND_ftsf129ae_slot1,
- OPERAND_ftsf130ae_slot1,
- OPERAND_ftsf131ae_slot1,
- OPERAND_ftsf132ae_slot1,
- OPERAND_ftsf133ae_slot1,
- OPERAND_ftsf134ae_slot1,
- OPERAND_ftsf135ae_slot1,
- OPERAND_ftsf136ae_slot1,
- OPERAND_ftsf137ae_slot1,
- OPERAND_ftsf138ae_slot1,
- OPERAND_ftsf139ae_slot1,
- OPERAND_ftsf140ae_slot1,
- OPERAND_ftsf141ae_slot1,
- OPERAND_ftsf142ae_slot1,
- OPERAND_ftsf143ae_slot1,
- OPERAND_ftsf144ae_slot1,
- OPERAND_ftsf145ae_slot1,
- OPERAND_ftsf146ae_slot1,
- OPERAND_ftsf147ae_slot1,
- OPERAND_ftsf148ae_slot1,
- OPERAND_ftsf149ae_slot1,
- OPERAND_ftsf150ae_slot1,
- OPERAND_ftsf151ae_slot1,
- OPERAND_ftsf152ae_slot1,
- OPERAND_ftsf153ae_slot1,
- OPERAND_ftsf154ae_slot1,
- OPERAND_ftsf155ae_slot1,
- OPERAND_ftsf156ae_slot1,
- OPERAND_ftsf157ae_slot1,
- OPERAND_ftsf158ae_slot1,
- OPERAND_ftsf159ae_slot1,
- OPERAND_ftsf160ae_slot1,
- OPERAND_ftsf161ae_slot1,
- OPERAND_ftsf162ae_slot1,
- OPERAND_ftsf163ae_slot1,
- OPERAND_ftsf164ae_slot1,
- OPERAND_ftsf165ae_slot1,
- OPERAND_ftsf166ae_slot1,
- OPERAND_ftsf167ae_slot1,
- OPERAND_ftsf168ae_slot1,
- OPERAND_ftsf169ae_slot1,
- OPERAND_ftsf170ae_slot1,
- OPERAND_ftsf171ae_slot1,
- OPERAND_ftsf172ae_slot1,
- OPERAND_ftsf173ae_slot1,
- OPERAND_ftsf174ae_slot1,
- OPERAND_ftsf175ae_slot1,
- OPERAND_ftsf176ae_slot1,
- OPERAND_ftsf177ae_slot1,
- OPERAND_ftsf178ae_slot1,
- OPERAND_ftsf179ae_slot1,
- OPERAND_ftsf180ae_slot1,
- OPERAND_ftsf181ae_slot1,
- OPERAND_ftsf182ae_slot1,
- OPERAND_ftsf183ae_slot1,
- OPERAND_ftsf184ae_slot1,
- OPERAND_ftsf185ae_slot1,
- OPERAND_ftsf186ae_slot1,
- OPERAND_ftsf187ae_slot1,
- OPERAND_ftsf188ae_slot1,
- OPERAND_ftsf189ae_slot1,
- OPERAND_ftsf190ae_slot1,
- OPERAND_ftsf191ae_slot1,
- OPERAND_ftsf192ae_slot1,
- OPERAND_ftsf193ae_slot1,
- OPERAND_ftsf194ae_slot1,
- OPERAND_ftsf195ae_slot1,
- OPERAND_ftsf196ae_slot1,
- OPERAND_ftsf197ae_slot1,
- OPERAND_ftsf198ae_slot1,
- OPERAND_ftsf199ae_slot1,
- OPERAND_ftsf200ae_slot1,
- OPERAND_ftsf201ae_slot1,
- OPERAND_ftsf202ae_slot1,
- OPERAND_ftsf203ae_slot1,
- OPERAND_ftsf204ae_slot1,
- OPERAND_ftsf205ae_slot1,
- OPERAND_ftsf206ae_slot1,
- OPERAND_ftsf207ae_slot1,
- OPERAND_ftsf208ae_slot1,
- OPERAND_ftsf210ae_slot1,
- OPERAND_ftsf333ae_slot1,
- OPERAND_ftsf334ae_slot1,
- OPERAND_ftsf335,
- OPERAND_ftsf336ae_slot1,
- OPERAND_ftsf337ae_slot1,
- OPERAND_ftsf339ae_slot1,
- OPERAND_ftsf340ae_slot1,
- OPERAND_ftsf341ae_slot1,
- OPERAND_ftsf342ae_slot1,
- OPERAND_ftsf343ae_slot1,
- OPERAND_ftsf344ae_slot1,
- OPERAND_ftsf345ae_slot1,
- OPERAND_ftsf347ae_slot1,
- OPERAND_ftsf348ae_slot1,
- OPERAND_ftsf349ae_slot1,
- OPERAND_ftsf350ae_slot1,
- OPERAND_ftsf351,
- OPERAND_ftsf352ae_slot1,
- OPERAND_ftsf354ae_slot1,
- OPERAND_ftsf355ae_slot1,
- OPERAND_ftsf356ae_slot1,
- OPERAND_ftsf357ae_slot1,
- OPERAND_ftsf358ae_slot1,
- OPERAND_ftsf359ae_slot1,
- OPERAND_op0_s4,
- OPERAND_ftsf211ae_slot0,
- OPERAND_ftsf212ae_slot0,
- OPERAND_ftsf213ae_slot0,
- OPERAND_ftsf214ae_slot0,
- OPERAND_ftsf215ae_slot0,
- OPERAND_ftsf217ae_slot0,
- OPERAND_ftsf218ae_slot0,
- OPERAND_ftsf219ae_slot0,
- OPERAND_ftsf220ae_slot0,
- OPERAND_ftsf221ae_slot0,
- OPERAND_ftsf222ae_slot0,
- OPERAND_ftsf223ae_slot0,
- OPERAND_ftsf224ae_slot0,
- OPERAND_ftsf225ae_slot0,
- OPERAND_ftsf226ae_slot0,
- OPERAND_ftsf227ae_slot0,
- OPERAND_ftsf228ae_slot0,
- OPERAND_ftsf229ae_slot0,
- OPERAND_ftsf230ae_slot0,
- OPERAND_ftsf231ae_slot0,
- OPERAND_ftsf232ae_slot0,
- OPERAND_ftsf233ae_slot0,
- OPERAND_ftsf234ae_slot0,
- OPERAND_ftsf235ae_slot0,
- OPERAND_ftsf236ae_slot0,
- OPERAND_ftsf237ae_slot0,
- OPERAND_ftsf238ae_slot0,
- OPERAND_ftsf239ae_slot0,
- OPERAND_ftsf240ae_slot0,
- OPERAND_ftsf241ae_slot0,
- OPERAND_ftsf242ae_slot0,
- OPERAND_ftsf243ae_slot0,
- OPERAND_ftsf244ae_slot0,
- OPERAND_ftsf245ae_slot0,
- OPERAND_ftsf246ae_slot0,
- OPERAND_ftsf247ae_slot0,
- OPERAND_ftsf248ae_slot0,
- OPERAND_ftsf249ae_slot0,
- OPERAND_ftsf250ae_slot0,
- OPERAND_ftsf251ae_slot0,
- OPERAND_ftsf252ae_slot0,
- OPERAND_ftsf253ae_slot0,
- OPERAND_ftsf254ae_slot0,
- OPERAND_ftsf255ae_slot0,
- OPERAND_ftsf256ae_slot0,
- OPERAND_ftsf257ae_slot0,
- OPERAND_ftsf258ae_slot0,
- OPERAND_ftsf259ae_slot0,
- OPERAND_ftsf260ae_slot0,
- OPERAND_ftsf261ae_slot0,
- OPERAND_ftsf262ae_slot0,
- OPERAND_ftsf263ae_slot0,
- OPERAND_ftsf264ae_slot0,
- OPERAND_ftsf265ae_slot0,
- OPERAND_ftsf266ae_slot0,
- OPERAND_ftsf267ae_slot0,
- OPERAND_ftsf268ae_slot0,
- OPERAND_ftsf269ae_slot0,
- OPERAND_ftsf270ae_slot0,
- OPERAND_ftsf271ae_slot0,
- OPERAND_ftsf272ae_slot0,
- OPERAND_ftsf273ae_slot0,
- OPERAND_ftsf274ae_slot0,
- OPERAND_ftsf275ae_slot0,
- OPERAND_ftsf276ae_slot0,
- OPERAND_ftsf277ae_slot0,
- OPERAND_ftsf278ae_slot0,
- OPERAND_ftsf279ae_slot0,
- OPERAND_ftsf280,
- OPERAND_ftsf281ae_slot0,
- OPERAND_ftsf282ae_slot0,
- OPERAND_ftsf284ae_slot0,
- OPERAND_ftsf285ae_slot0,
- OPERAND_ftsf287ae_slot0,
- OPERAND_ftsf288,
- OPERAND_ftsf289ae_slot0,
- OPERAND_ftsf290ae_slot0,
- OPERAND_ftsf291ae_slot0,
- OPERAND_ftsf292ae_slot0,
- OPERAND_ftsf293ae_slot0,
- OPERAND_ftsf294ae_slot0,
- OPERAND_ftsf295ae_slot0,
- OPERAND_ftsf296ae_slot0,
- OPERAND_ftsf297ae_slot0,
- OPERAND_ftsf298ae_slot0,
- OPERAND_ftsf300ae_slot0,
- OPERAND_ftsf302ae_slot0,
- OPERAND_ftsf304ae_slot0,
- OPERAND_ftsf305ae_slot0,
- OPERAND_ftsf306ae_slot0,
- OPERAND_ftsf307ae_slot0,
- OPERAND_ftsf308ae_slot0,
- OPERAND_ftsf309,
- OPERAND_ftsf310ae_slot0,
- OPERAND_ftsf311ae_slot0,
- OPERAND_ftsf312ae_slot0,
- OPERAND_ftsf313ae_slot0,
- OPERAND_ftsf314ae_slot0,
- OPERAND_ftsf315,
- OPERAND_ftsf316ae_slot0,
- OPERAND_ftsf317ae_slot0,
- OPERAND_ftsf319ae_slot0,
- OPERAND_ftsf320ae_slot0,
- OPERAND_ftsf322ae_slot0,
- OPERAND_ftsf323ae_slot0,
- OPERAND_ftsf324ae_slot0,
- OPERAND_ftsf325ae_slot0,
- OPERAND_ftsf326ae_slot0,
- OPERAND_ftsf327ae_slot0,
- OPERAND_ftsf328ae_slot0,
- OPERAND_ftsf329ae_slot0,
- OPERAND_ftsf360ae_slot0,
- OPERAND_ftsf361ae_slot0,
- OPERAND_ftsf362,
- OPERAND_ftsf363ae_slot0,
- OPERAND_ftsf364ae_slot0,
- OPERAND_ftsf366ae_slot0,
- OPERAND_ftsf368ae_slot0,
- OPERAND_ftsf370ae_slot0,
- OPERAND_ftsf373ae_slot0,
- OPERAND_ftsf376ae_slot0,
- OPERAND_ftsf378ae_slot0,
- OPERAND_ftsf379ae_slot0,
- OPERAND_ftsf382ae_slot0,
- OPERAND_ftsf383ae_slot0,
- OPERAND_ftsf384ae_slot0,
- OPERAND_ftsf386ae_slot0,
- OPERAND_ftsf387ae_slot0,
- OPERAND_ftsf388ae_slot0,
- OPERAND_ftsf389ae_slot0,
- OPERAND_ae_mul32x24fld,
- OPERAND_op0_s4_s4,
- OPERAND_combined2c0b5f72_fld28,
- OPERAND_combined2c0b5f72_fld37,
- OPERAND_combined2c0b5f72_fld39,
- OPERAND_combined2c0b5f72_fld40,
- OPERAND_combined2c0b5f72_fld46,
- OPERAND_combined2c0b5f72_fld47,
- OPERAND_combined2c0b5f72_fld49,
- OPERAND_combined2c0b5f72_fld50,
- OPERAND_combined2c0b5f72_fld52,
- OPERAND_combined2c0b5f72_fld121,
- OPERAND_combined2c0b5f72_fld123,
- OPERAND_combined2c0b5f72_fld127,
- OPERAND_combined2c0b5f72_fld133ae_slot0,
- OPERAND_combined2c0b5f72_fld134ae_slot0,
- OPERAND_combined2c0b5f72_fld135ae_slot0,
- OPERAND_combined2c0b5f72_fld136ae_slot0,
- OPERAND_combined2c0b5f72_fld137ae_slot0,
- OPERAND_combined2c0b5f72_fld138ae_slot0,
- OPERAND_combined2c0b5f72_fld139ae_slot0,
- OPERAND_combined2c0b5f72_fld140ae_slot0,
- OPERAND_combined2c0b5f72_fld141ae_slot0,
- OPERAND_combined2c0b5f72_fld142ae_slot0,
- OPERAND_combined2c0b5f72_fld143ae_slot0,
- OPERAND_combined2c0b5f72_fld144ae_slot0,
- OPERAND_combined2c0b5f72_fld145ae_slot0,
- OPERAND_combined2c0b5f72_fld146ae_slot0,
- OPERAND_combined2c0b5f72_fld148ae_slot0,
- OPERAND_combined2c0b5f72_fld149ae_slot0,
- OPERAND_op0_s4_s4_s4,
- OPERAND_combined1e9fefee_fld96,
- OPERAND_combined1e9fefee_fld98,
- OPERAND_combined1e9fefee_fld106ae_slot0,
- OPERAND_combined1e9fefee_fld107ae_slot0,
- OPERAND_combined1e9fefee_fld108ae_slot0,
- OPERAND_combined1e9fefee_fld109ae_slot0,
- OPERAND_op0_s3_s3,
- OPERAND_combined2c0b5f72_fld19,
- OPERAND_combined2c0b5f72_fld22,
- OPERAND_combined2c0b5f72_fld24,
- OPERAND_combined2c0b5f72_fld65,
- OPERAND_combined2c0b5f72_fld66,
- OPERAND_combined2c0b5f72_fld68,
- OPERAND_combined2c0b5f72_fld69,
- OPERAND_combined2c0b5f72_fld74,
- OPERAND_combined2c0b5f72_fld79,
- OPERAND_combined2c0b5f72_fld88,
- OPERAND_combined2c0b5f72_fld90,
- OPERAND_combined2c0b5f72_fld91,
- OPERAND_combined2c0b5f72_fld131ae_slot1,
- OPERAND_combined2c0b5f72_fld132ae_slot1,
- OPERAND_combined2c0b5f72_fld147ae_slot1,
- OPERAND_s3to1
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSRING }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { OPERAND_ars_entry }, 's' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm12x8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { OPERAND_simm4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ai4const }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_simm7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8x256 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4const }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bbi }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4constu }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_label12 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sae }, 'i' },
- { { OPERAND_op2p1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { OPERAND_soffset }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_uimm16x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_simm12b }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimmrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { OPERAND_sas }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_msalp32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sargt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_243_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul16_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32h_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
- { { STATE_ACC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_mx }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_mx }, 'i' },
- { { OPERAND_my }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
- { { OPERAND_mw }, 'o' },
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_mr3 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_mr3 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_mr3 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPC5 }, 'i' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_EPC7 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_EPS5 }, 'i' },
- { { STATE_EPS6 }, 'i' },
- { { STATE_EPS7 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { OPERAND_imms }, 'i' },
- { { OPERAND_immt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_InOCDMode }, 'i' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_InOCDMode }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_bs }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_bs4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_bs8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
- { { OPERAND_bs }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_brall }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_brall }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_brall }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = {
- { { STATE_PREFCTL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = {
- { { STATE_PREFCTL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = {
- { { STATE_PREFCTL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'm' },
- { { STATE_EXCVADDR }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'i' },
- { { STATE_ASID2 }, 'i' },
- { { STATE_ASID1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'o' },
- { { STATE_ASID2 }, 'o' },
- { { STATE_ASID1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'm' },
- { { STATE_ASID2 }, 'm' },
- { { STATE_ASID1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID6 }, 'i' },
- { { STATE_INSTPGSZID5 }, 'i' },
- { { STATE_INSTPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID6 }, 'o' },
- { { STATE_INSTPGSZID5 }, 'o' },
- { { STATE_INSTPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID6 }, 'm' },
- { { STATE_INSTPGSZID5 }, 'm' },
- { { STATE_INSTPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID6 }, 'i' },
- { { STATE_DATAPGSZID5 }, 'i' },
- { { STATE_DATAPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID6 }, 'o' },
- { { STATE_DATAPGSZID5 }, 'o' },
- { { STATE_DATAPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID6 }, 'm' },
- { { STATE_DATAPGSZID5 }, 'm' },
- { { STATE_DATAPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_XTSYNC }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_ERI_RAW_INTERLOCK }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
- INTERFACE_ERI_RD_In,
- INTERFACE_ERI_RD_Out
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_ERI_RAW_INTERLOCK }, 'o' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
- INTERFACE_ERI_WR_In,
- INTERFACE_ERI_WR_Out
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'i' },
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'o' },
- { { STATE_AE_SAR }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
- { { STATE_AE_BITHEAD }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_TABLESIZE }, 'i' },
- { { STATE_AE_FIRST_TS }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'o' },
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_TABLESIZE }, 'o' },
- { { STATE_AE_FIRST_TS }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'i' },
- { { STATE_AE_SEARCHDONE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
- { { STATE_AE_SAR }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
- { { STATE_AE_FIRST_TS }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
- { { STATE_AE_FIRST_TS }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
- { { STATE_AE_SEARCHDONE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
- { { OPERAND_ps }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
- { { OPERAND_qr1_w }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
- { { OPERAND_qr1_w }, 'm' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bs }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
- { { OPERAND_qr1_w }, 'm' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bs }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_cvt_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_cvt_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
- { { OPERAND_alupppb_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
- { { OPERAND_alupppb_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
- { { OPERAND_bt2 }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
- { { OPERAND_bt2 }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
- { { OPERAND_bt2 }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bt }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bt }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'm' },
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'm' },
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'm' },
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'm' },
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'm' },
- { { STATE_AE_TABLESIZE }, 'm' },
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_AE_FIRST_TS }, 'i' },
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_SEARCHDONE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_AE_FIRST_TS }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_AE_TABLESIZE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ae_ohba2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_ohba2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_ohba }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_ae_ohba }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_NEXTOFFSET }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = {
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = {
- { { STATE_AE_CEND0 }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = {
- { { STATE_AE_CBEGIN0 }, 'i' },
- { { STATE_AE_CEND0 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
- { { STATE_EXPSTATE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
- INTERFACE_IMPWIRE
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
- { { OPERAND_bitindex }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
- { { STATE_EXPSTATE }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_threadptr_args,
- 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
- { 1, Iclass_wur_threadptr_args,
- 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32nb_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_memctl_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid0_args,
- 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_configid0_args,
- 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid1_args,
- 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_243_args,
- 2, Iclass_xt_iclass_rsr_243_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc5_args,
- 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc5_args,
- 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc5_args,
- 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave5_args,
- 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave5_args,
- 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave5_args,
- 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc6_args,
- 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc6_args,
- 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc6_args,
- 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave6_args,
- 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave6_args,
- 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave6_args,
- 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc7_args,
- 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc7_args,
- 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc7_args,
- 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave7_args,
- 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave7_args,
- 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave7_args,
- 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps5_args,
- 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps5_args,
- 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps5_args,
- 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps6_args,
- 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps6_args,
- 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps6_args,
- 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps7_args,
- 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps7_args,
- 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps7_args,
- 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 3, Iclass_xt_mul16_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32h_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_aa_args,
- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_ad_args,
- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_da_args,
- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_dd_args,
- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_aa_args,
- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_ad_args,
- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_da_args,
- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_dd_args,
- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_da_args,
- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_dd_args,
- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_l_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m3_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acclo_args,
- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acclo_args,
- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acclo_args,
- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acchi_args,
- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acchi_args,
- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acchi_args,
- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_lddr32_p_args,
- 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sddr32_p_args,
- 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_mmid_args,
- 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_bbool1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbool4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbool8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbranch_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bmove_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_RSR_BR_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_WSR_BR_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_XSR_BR_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_lock_args,
- 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_dcache_dyn_args,
- 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_lock_args,
- 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prefctl_args,
- 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_prefctl_args,
- 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_prefctl_args,
- 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_rasid_args,
- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_rasid_args,
- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_rasid_args,
- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
- 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
- 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
- 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
- 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
- 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
- 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_ldpte */,
- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwitlba */,
- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwdtlba */,
- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_cpenable_args,
- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_cpenable_args,
- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_cpenable_args,
- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_clamp_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_atomctl_args,
- 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_atomctl_args,
- 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_atomctl_args,
- 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_div_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rer_args,
- 3, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
- { 2, Iclass_xt_iclass_wer_args,
- 3, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
- { 1, Iclass_rur_ae_ovf_sar_args,
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- 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_sha32_args,
- 0, 0, 0, 0 },
- { 3, Iclass_ae_iclass_vldl32t_args,
- 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_vldl16t_args,
- 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_vldl16c_args,
- 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_vldsht_args,
- 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_lb_args,
- 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_lbi_args,
- 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lbk_args,
- 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lbki_args,
- 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_db_args,
- 3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_dbi_args,
- 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_vlel32t_args,
- 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_vlel16t_args,
- 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_sb_args,
- 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sbi_args,
- 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_vles16c_args,
- 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_sbf_args,
- 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SLAASQ56S_args,
- 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_ADDBRBA32_args,
- 0, 0, 0, 0 },
- { 3, Iclass_icls_AE_MINABSSP24S_args,
- 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_MAXABSSP24S_args,
- 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_MINABSSQ56S_args,
- 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_MAXABSSQ56S_args,
- 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 },
- { 1, Iclass_rur_ae_cbegin0_args,
- 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 },
- { 1, Iclass_wur_ae_cbegin0_args,
- 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 },
- { 1, Iclass_rur_ae_cend0_args,
- 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 },
- { 1, Iclass_wur_ae_cend0_args,
- 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LP24X2_C_args,
- 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SP24X2S_C_args,
- 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LP24X2F_C_args,
- 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SP24X2F_C_args,
- 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LP16X2F_C_args,
- 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SP16X2F_C_args,
- 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LP24_C_args,
- 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SP24S_L_C_args,
- 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LP24F_C_args,
- 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SP24F_L_C_args,
- 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LP16F_C_args,
- 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SP16F_L_C_args,
- 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LQ56_C_args,
- 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SQ56S_C_args,
- 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_LQ32F_C_args,
- 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 },
- { 3, Iclass_icls_AE_SQ32F_C_args,
- 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 },
- { 1, Iclass_rur_expstate_args,
- 2, Iclass_rur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_wur_expstate_args,
- 2, Iclass_wur_expstate_stateArgs, 0, 0 },
- { 1, Iclass_iclass_READ_IMPWIRE_args,
- 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
- { 1, Iclass_iclass_SETB_EXPSTATE_args,
- 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
- { 1, Iclass_iclass_CLRB_EXPSTATE_args,
- 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
- { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
- 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
-};
-
-enum xtensa_iclass_id {
- ICLASS_xt_iclass_excw,
- ICLASS_xt_iclass_rfe,
- ICLASS_xt_iclass_rfde,
- ICLASS_xt_iclass_syscall,
- ICLASS_xt_iclass_call12,
- ICLASS_xt_iclass_call8,
- ICLASS_xt_iclass_call4,
- ICLASS_xt_iclass_callx12,
- ICLASS_xt_iclass_callx8,
- ICLASS_xt_iclass_callx4,
- ICLASS_xt_iclass_entry,
- ICLASS_xt_iclass_movsp,
- ICLASS_xt_iclass_rotw,
- ICLASS_xt_iclass_retw,
- ICLASS_xt_iclass_rfwou,
- ICLASS_xt_iclass_l32e,
- ICLASS_xt_iclass_s32e,
- ICLASS_xt_iclass_rsr_windowbase,
- ICLASS_xt_iclass_wsr_windowbase,
- ICLASS_xt_iclass_xsr_windowbase,
- ICLASS_xt_iclass_rsr_windowstart,
- ICLASS_xt_iclass_wsr_windowstart,
- ICLASS_xt_iclass_xsr_windowstart,
- ICLASS_xt_iclass_add_n,
- ICLASS_xt_iclass_addi_n,
- ICLASS_xt_iclass_bz6,
- ICLASS_xt_iclass_ill_n,
- ICLASS_xt_iclass_loadi4,
- ICLASS_xt_iclass_mov_n,
- ICLASS_xt_iclass_movi_n,
- ICLASS_xt_iclass_nopn,
- ICLASS_xt_iclass_retn,
- ICLASS_xt_iclass_storei4,
- ICLASS_rur_threadptr,
- ICLASS_wur_threadptr,
- ICLASS_xt_iclass_addi,
- ICLASS_xt_iclass_addmi,
- ICLASS_xt_iclass_addsub,
- ICLASS_xt_iclass_bit,
- ICLASS_xt_iclass_bsi8,
- ICLASS_xt_iclass_bsi8b,
- ICLASS_xt_iclass_bsi8u,
- ICLASS_xt_iclass_bst8,
- ICLASS_xt_iclass_bsz12,
- ICLASS_xt_iclass_call0,
- ICLASS_xt_iclass_callx0,
- ICLASS_xt_iclass_exti,
- ICLASS_xt_iclass_ill,
- ICLASS_xt_iclass_jump,
- ICLASS_xt_iclass_jumpx,
- ICLASS_xt_iclass_l16ui,
- ICLASS_xt_iclass_l16si,
- ICLASS_xt_iclass_l32i,
- ICLASS_xt_iclass_l32r,
- ICLASS_xt_iclass_l8i,
- ICLASS_xt_iclass_loop,
- ICLASS_xt_iclass_loopz,
- ICLASS_xt_iclass_movi,
- ICLASS_xt_iclass_movz,
- ICLASS_xt_iclass_neg,
- ICLASS_xt_iclass_nop,
- ICLASS_xt_iclass_return,
- ICLASS_xt_iclass_simcall,
- ICLASS_xt_iclass_s16i,
- ICLASS_xt_iclass_s32i,
- ICLASS_xt_iclass_s32nb,
- ICLASS_xt_iclass_s8i,
- ICLASS_xt_iclass_sar,
- ICLASS_xt_iclass_sari,
- ICLASS_xt_iclass_shifts,
- ICLASS_xt_iclass_shiftst,
- ICLASS_xt_iclass_shiftt,
- ICLASS_xt_iclass_slli,
- ICLASS_xt_iclass_srai,
- ICLASS_xt_iclass_srli,
- ICLASS_xt_iclass_memw,
- ICLASS_xt_iclass_extw,
- ICLASS_xt_iclass_isync,
- ICLASS_xt_iclass_sync,
- ICLASS_xt_iclass_rsil,
- ICLASS_xt_iclass_rsr_lend,
- ICLASS_xt_iclass_wsr_lend,
- ICLASS_xt_iclass_xsr_lend,
- ICLASS_xt_iclass_rsr_lcount,
- ICLASS_xt_iclass_wsr_lcount,
- ICLASS_xt_iclass_xsr_lcount,
- ICLASS_xt_iclass_rsr_lbeg,
- ICLASS_xt_iclass_wsr_lbeg,
- ICLASS_xt_iclass_xsr_lbeg,
- ICLASS_xt_iclass_rsr_sar,
- ICLASS_xt_iclass_wsr_sar,
- ICLASS_xt_iclass_xsr_sar,
- ICLASS_xt_iclass_rsr_memctl,
- ICLASS_xt_iclass_wsr_memctl,
- ICLASS_xt_iclass_xsr_memctl,
- ICLASS_xt_iclass_rsr_litbase,
- ICLASS_xt_iclass_wsr_litbase,
- ICLASS_xt_iclass_xsr_litbase,
- ICLASS_xt_iclass_rsr_configid0,
- ICLASS_xt_iclass_wsr_configid0,
- ICLASS_xt_iclass_rsr_configid1,
- ICLASS_xt_iclass_rsr_243,
- ICLASS_xt_iclass_rsr_ps,
- ICLASS_xt_iclass_wsr_ps,
- ICLASS_xt_iclass_xsr_ps,
- ICLASS_xt_iclass_rsr_epc1,
- ICLASS_xt_iclass_wsr_epc1,
- ICLASS_xt_iclass_xsr_epc1,
- ICLASS_xt_iclass_rsr_excsave1,
- ICLASS_xt_iclass_wsr_excsave1,
- ICLASS_xt_iclass_xsr_excsave1,
- ICLASS_xt_iclass_rsr_epc2,
- ICLASS_xt_iclass_wsr_epc2,
- ICLASS_xt_iclass_xsr_epc2,
- ICLASS_xt_iclass_rsr_excsave2,
- ICLASS_xt_iclass_wsr_excsave2,
- ICLASS_xt_iclass_xsr_excsave2,
- ICLASS_xt_iclass_rsr_epc3,
- ICLASS_xt_iclass_wsr_epc3,
- ICLASS_xt_iclass_xsr_epc3,
- ICLASS_xt_iclass_rsr_excsave3,
- ICLASS_xt_iclass_wsr_excsave3,
- ICLASS_xt_iclass_xsr_excsave3,
- ICLASS_xt_iclass_rsr_epc4,
- ICLASS_xt_iclass_wsr_epc4,
- ICLASS_xt_iclass_xsr_epc4,
- ICLASS_xt_iclass_rsr_excsave4,
- ICLASS_xt_iclass_wsr_excsave4,
- ICLASS_xt_iclass_xsr_excsave4,
- ICLASS_xt_iclass_rsr_epc5,
- ICLASS_xt_iclass_wsr_epc5,
- ICLASS_xt_iclass_xsr_epc5,
- ICLASS_xt_iclass_rsr_excsave5,
- ICLASS_xt_iclass_wsr_excsave5,
- ICLASS_xt_iclass_xsr_excsave5,
- ICLASS_xt_iclass_rsr_epc6,
- ICLASS_xt_iclass_wsr_epc6,
- ICLASS_xt_iclass_xsr_epc6,
- ICLASS_xt_iclass_rsr_excsave6,
- ICLASS_xt_iclass_wsr_excsave6,
- ICLASS_xt_iclass_xsr_excsave6,
- ICLASS_xt_iclass_rsr_epc7,
- ICLASS_xt_iclass_wsr_epc7,
- ICLASS_xt_iclass_xsr_epc7,
- ICLASS_xt_iclass_rsr_excsave7,
- ICLASS_xt_iclass_wsr_excsave7,
- ICLASS_xt_iclass_xsr_excsave7,
- ICLASS_xt_iclass_rsr_eps2,
- ICLASS_xt_iclass_wsr_eps2,
- ICLASS_xt_iclass_xsr_eps2,
- ICLASS_xt_iclass_rsr_eps3,
- ICLASS_xt_iclass_wsr_eps3,
- ICLASS_xt_iclass_xsr_eps3,
- ICLASS_xt_iclass_rsr_eps4,
- ICLASS_xt_iclass_wsr_eps4,
- ICLASS_xt_iclass_xsr_eps4,
- ICLASS_xt_iclass_rsr_eps5,
- ICLASS_xt_iclass_wsr_eps5,
- ICLASS_xt_iclass_xsr_eps5,
- ICLASS_xt_iclass_rsr_eps6,
- ICLASS_xt_iclass_wsr_eps6,
- ICLASS_xt_iclass_xsr_eps6,
- ICLASS_xt_iclass_rsr_eps7,
- ICLASS_xt_iclass_wsr_eps7,
- ICLASS_xt_iclass_xsr_eps7,
- ICLASS_xt_iclass_rsr_excvaddr,
- ICLASS_xt_iclass_wsr_excvaddr,
- ICLASS_xt_iclass_xsr_excvaddr,
- ICLASS_xt_iclass_rsr_depc,
- ICLASS_xt_iclass_wsr_depc,
- ICLASS_xt_iclass_xsr_depc,
- ICLASS_xt_iclass_rsr_exccause,
- ICLASS_xt_iclass_wsr_exccause,
- ICLASS_xt_iclass_xsr_exccause,
- ICLASS_xt_iclass_rsr_misc0,
- ICLASS_xt_iclass_wsr_misc0,
- ICLASS_xt_iclass_xsr_misc0,
- ICLASS_xt_iclass_rsr_misc1,
- ICLASS_xt_iclass_wsr_misc1,
- ICLASS_xt_iclass_xsr_misc1,
- ICLASS_xt_iclass_rsr_prid,
- ICLASS_xt_iclass_rsr_vecbase,
- ICLASS_xt_iclass_wsr_vecbase,
- ICLASS_xt_iclass_xsr_vecbase,
- ICLASS_xt_mul16,
- ICLASS_xt_mul32,
- ICLASS_xt_mul32h,
- ICLASS_xt_iclass_mac16_aa,
- ICLASS_xt_iclass_mac16_ad,
- ICLASS_xt_iclass_mac16_da,
- ICLASS_xt_iclass_mac16_dd,
- ICLASS_xt_iclass_mac16a_aa,
- ICLASS_xt_iclass_mac16a_ad,
- ICLASS_xt_iclass_mac16a_da,
- ICLASS_xt_iclass_mac16a_dd,
- ICLASS_xt_iclass_mac16al_da,
- ICLASS_xt_iclass_mac16al_dd,
- ICLASS_xt_iclass_mac16_l,
- ICLASS_xt_iclass_rsr_m0,
- ICLASS_xt_iclass_wsr_m0,
- ICLASS_xt_iclass_xsr_m0,
- ICLASS_xt_iclass_rsr_m1,
- ICLASS_xt_iclass_wsr_m1,
- ICLASS_xt_iclass_xsr_m1,
- ICLASS_xt_iclass_rsr_m2,
- ICLASS_xt_iclass_wsr_m2,
- ICLASS_xt_iclass_xsr_m2,
- ICLASS_xt_iclass_rsr_m3,
- ICLASS_xt_iclass_wsr_m3,
- ICLASS_xt_iclass_xsr_m3,
- ICLASS_xt_iclass_rsr_acclo,
- ICLASS_xt_iclass_wsr_acclo,
- ICLASS_xt_iclass_xsr_acclo,
- ICLASS_xt_iclass_rsr_acchi,
- ICLASS_xt_iclass_wsr_acchi,
- ICLASS_xt_iclass_xsr_acchi,
- ICLASS_xt_iclass_rfi,
- ICLASS_xt_iclass_wait,
- ICLASS_xt_iclass_rsr_interrupt,
- ICLASS_xt_iclass_wsr_intset,
- ICLASS_xt_iclass_wsr_intclear,
- ICLASS_xt_iclass_rsr_intenable,
- ICLASS_xt_iclass_wsr_intenable,
- ICLASS_xt_iclass_xsr_intenable,
- ICLASS_xt_iclass_break,
- ICLASS_xt_iclass_break_n,
- ICLASS_xt_iclass_rsr_dbreaka0,
- ICLASS_xt_iclass_wsr_dbreaka0,
- ICLASS_xt_iclass_xsr_dbreaka0,
- ICLASS_xt_iclass_rsr_dbreakc0,
- ICLASS_xt_iclass_wsr_dbreakc0,
- ICLASS_xt_iclass_xsr_dbreakc0,
- ICLASS_xt_iclass_rsr_dbreaka1,
- ICLASS_xt_iclass_wsr_dbreaka1,
- ICLASS_xt_iclass_xsr_dbreaka1,
- ICLASS_xt_iclass_rsr_dbreakc1,
- ICLASS_xt_iclass_wsr_dbreakc1,
- ICLASS_xt_iclass_xsr_dbreakc1,
- ICLASS_xt_iclass_rsr_ibreaka0,
- ICLASS_xt_iclass_wsr_ibreaka0,
- ICLASS_xt_iclass_xsr_ibreaka0,
- ICLASS_xt_iclass_rsr_ibreaka1,
- ICLASS_xt_iclass_wsr_ibreaka1,
- ICLASS_xt_iclass_xsr_ibreaka1,
- ICLASS_xt_iclass_rsr_ibreakenable,
- ICLASS_xt_iclass_wsr_ibreakenable,
- ICLASS_xt_iclass_xsr_ibreakenable,
- ICLASS_xt_iclass_rsr_debugcause,
- ICLASS_xt_iclass_wsr_debugcause,
- ICLASS_xt_iclass_xsr_debugcause,
- ICLASS_xt_iclass_rsr_icount,
- ICLASS_xt_iclass_wsr_icount,
- ICLASS_xt_iclass_xsr_icount,
- ICLASS_xt_iclass_rsr_icountlevel,
- ICLASS_xt_iclass_wsr_icountlevel,
- ICLASS_xt_iclass_xsr_icountlevel,
- ICLASS_xt_iclass_rsr_ddr,
- ICLASS_xt_iclass_wsr_ddr,
- ICLASS_xt_iclass_xsr_ddr,
- ICLASS_xt_iclass_lddr32_p,
- ICLASS_xt_iclass_sddr32_p,
- ICLASS_xt_iclass_rfdo,
- ICLASS_xt_iclass_rfdd,
- ICLASS_xt_iclass_wsr_mmid,
- ICLASS_xt_iclass_bbool1,
- ICLASS_xt_iclass_bbool4,
- ICLASS_xt_iclass_bbool8,
- ICLASS_xt_iclass_bbranch,
- ICLASS_xt_iclass_bmove,
- ICLASS_xt_iclass_RSR_BR,
- ICLASS_xt_iclass_WSR_BR,
- ICLASS_xt_iclass_XSR_BR,
- ICLASS_xt_iclass_rsr_ccount,
- ICLASS_xt_iclass_wsr_ccount,
- ICLASS_xt_iclass_xsr_ccount,
- ICLASS_xt_iclass_rsr_ccompare0,
- ICLASS_xt_iclass_wsr_ccompare0,
- ICLASS_xt_iclass_xsr_ccompare0,
- ICLASS_xt_iclass_rsr_ccompare1,
- ICLASS_xt_iclass_wsr_ccompare1,
- ICLASS_xt_iclass_xsr_ccompare1,
- ICLASS_xt_iclass_rsr_ccompare2,
- ICLASS_xt_iclass_wsr_ccompare2,
- ICLASS_xt_iclass_xsr_ccompare2,
- ICLASS_xt_iclass_icache,
- ICLASS_xt_iclass_icache_lock,
- ICLASS_xt_iclass_icache_inv,
- ICLASS_xt_iclass_licx,
- ICLASS_xt_iclass_sicx,
- ICLASS_xt_iclass_dcache,
- ICLASS_xt_iclass_dcache_dyn,
- ICLASS_xt_iclass_dcache_ind,
- ICLASS_xt_iclass_dcache_inv,
- ICLASS_xt_iclass_dpf,
- ICLASS_xt_iclass_dcache_lock,
- ICLASS_xt_iclass_sdct,
- ICLASS_xt_iclass_ldct,
- ICLASS_xt_iclass_rsr_prefctl,
- ICLASS_xt_iclass_wsr_prefctl,
- ICLASS_xt_iclass_xsr_prefctl,
- ICLASS_xt_iclass_wsr_ptevaddr,
- ICLASS_xt_iclass_rsr_ptevaddr,
- ICLASS_xt_iclass_xsr_ptevaddr,
- ICLASS_xt_iclass_rsr_rasid,
- ICLASS_xt_iclass_wsr_rasid,
- ICLASS_xt_iclass_xsr_rasid,
- ICLASS_xt_iclass_rsr_itlbcfg,
- ICLASS_xt_iclass_wsr_itlbcfg,
- ICLASS_xt_iclass_xsr_itlbcfg,
- ICLASS_xt_iclass_rsr_dtlbcfg,
- ICLASS_xt_iclass_wsr_dtlbcfg,
- ICLASS_xt_iclass_xsr_dtlbcfg,
- ICLASS_xt_iclass_idtlb,
- ICLASS_xt_iclass_rdtlb,
- ICLASS_xt_iclass_wdtlb,
- ICLASS_xt_iclass_iitlb,
- ICLASS_xt_iclass_ritlb,
- ICLASS_xt_iclass_witlb,
- ICLASS_xt_iclass_ldpte,
- ICLASS_xt_iclass_hwwitlba,
- ICLASS_xt_iclass_hwwdtlba,
- ICLASS_xt_iclass_rsr_cpenable,
- ICLASS_xt_iclass_wsr_cpenable,
- ICLASS_xt_iclass_xsr_cpenable,
- ICLASS_xt_iclass_clamp,
- ICLASS_xt_iclass_minmax,
- ICLASS_xt_iclass_nsa,
- ICLASS_xt_iclass_sx,
- ICLASS_xt_iclass_l32ai,
- ICLASS_xt_iclass_s32ri,
- ICLASS_xt_iclass_s32c1i,
- ICLASS_xt_iclass_rsr_scompare1,
- ICLASS_xt_iclass_wsr_scompare1,
- ICLASS_xt_iclass_xsr_scompare1,
- ICLASS_xt_iclass_rsr_atomctl,
- ICLASS_xt_iclass_wsr_atomctl,
- ICLASS_xt_iclass_xsr_atomctl,
- ICLASS_xt_iclass_div,
- ICLASS_xt_iclass_rer,
- ICLASS_xt_iclass_wer,
- ICLASS_rur_ae_ovf_sar,
- ICLASS_wur_ae_ovf_sar,
- ICLASS_rur_ae_bithead,
- ICLASS_wur_ae_bithead,
- ICLASS_rur_ae_ts_fts_bu_bp,
- ICLASS_wur_ae_ts_fts_bu_bp,
- ICLASS_rur_ae_sd_no,
- ICLASS_wur_ae_sd_no,
- ICLASS_ae_iclass_rur_ae_overflow,
- ICLASS_ae_iclass_wur_ae_overflow,
- ICLASS_ae_iclass_rur_ae_sar,
- ICLASS_ae_iclass_wur_ae_sar,
- ICLASS_ae_iclass_rur_ae_bitptr,
- ICLASS_ae_iclass_wur_ae_bitptr,
- ICLASS_ae_iclass_rur_ae_bitsused,
- ICLASS_ae_iclass_wur_ae_bitsused,
- ICLASS_ae_iclass_rur_ae_tablesize,
- ICLASS_ae_iclass_wur_ae_tablesize,
- ICLASS_ae_iclass_rur_ae_first_ts,
- ICLASS_ae_iclass_wur_ae_first_ts,
- ICLASS_ae_iclass_rur_ae_nextoffset,
- ICLASS_ae_iclass_wur_ae_nextoffset,
- ICLASS_ae_iclass_rur_ae_searchdone,
- ICLASS_ae_iclass_wur_ae_searchdone,
- ICLASS_ae_iclass_lp16f_i,
- ICLASS_ae_iclass_lp16f_iu,
- ICLASS_ae_iclass_lp16f_x,
- ICLASS_ae_iclass_lp16f_xu,
- ICLASS_ae_iclass_lp24_i,
- ICLASS_ae_iclass_lp24_iu,
- ICLASS_ae_iclass_lp24_x,
- ICLASS_ae_iclass_lp24_xu,
- ICLASS_ae_iclass_lp24f_i,
- ICLASS_ae_iclass_lp24f_iu,
- ICLASS_ae_iclass_lp24f_x,
- ICLASS_ae_iclass_lp24f_xu,
- ICLASS_ae_iclass_lp16x2f_i,
- ICLASS_ae_iclass_lp16x2f_iu,
- ICLASS_ae_iclass_lp16x2f_x,
- ICLASS_ae_iclass_lp16x2f_xu,
- ICLASS_ae_iclass_lp24x2f_i,
- ICLASS_ae_iclass_lp24x2f_iu,
- ICLASS_ae_iclass_lp24x2f_x,
- ICLASS_ae_iclass_lp24x2f_xu,
- ICLASS_ae_iclass_lp24x2_i,
- ICLASS_ae_iclass_lp24x2_iu,
- ICLASS_ae_iclass_lp24x2_x,
- ICLASS_ae_iclass_lp24x2_xu,
- ICLASS_ae_iclass_sp16x2f_i,
- ICLASS_ae_iclass_sp16x2f_iu,
- ICLASS_ae_iclass_sp16x2f_x,
- ICLASS_ae_iclass_sp16x2f_xu,
- ICLASS_ae_iclass_sp24x2s_i,
- ICLASS_ae_iclass_sp24x2s_iu,
- ICLASS_ae_iclass_sp24x2s_x,
- ICLASS_ae_iclass_sp24x2s_xu,
- ICLASS_ae_iclass_sp24x2f_i,
- ICLASS_ae_iclass_sp24x2f_iu,
- ICLASS_ae_iclass_sp24x2f_x,
- ICLASS_ae_iclass_sp24x2f_xu,
- ICLASS_ae_iclass_sp16f_l_i,
- ICLASS_ae_iclass_sp16f_l_iu,
- ICLASS_ae_iclass_sp16f_l_x,
- ICLASS_ae_iclass_sp16f_l_xu,
- ICLASS_ae_iclass_sp24s_l_i,
- ICLASS_ae_iclass_sp24s_l_iu,
- ICLASS_ae_iclass_sp24s_l_x,
- ICLASS_ae_iclass_sp24s_l_xu,
- ICLASS_ae_iclass_sp24f_l_i,
- ICLASS_ae_iclass_sp24f_l_iu,
- ICLASS_ae_iclass_sp24f_l_x,
- ICLASS_ae_iclass_sp24f_l_xu,
- ICLASS_ae_iclass_lq56_i,
- ICLASS_ae_iclass_lq56_iu,
- ICLASS_ae_iclass_lq56_x,
- ICLASS_ae_iclass_lq56_xu,
- ICLASS_ae_iclass_lq32f_i,
- ICLASS_ae_iclass_lq32f_iu,
- ICLASS_ae_iclass_lq32f_x,
- ICLASS_ae_iclass_lq32f_xu,
- ICLASS_ae_iclass_sq56s_i,
- ICLASS_ae_iclass_sq56s_iu,
- ICLASS_ae_iclass_sq56s_x,
- ICLASS_ae_iclass_sq56s_xu,
- ICLASS_ae_iclass_sq32f_i,
- ICLASS_ae_iclass_sq32f_iu,
- ICLASS_ae_iclass_sq32f_x,
- ICLASS_ae_iclass_sq32f_xu,
- ICLASS_ae_iclass_zerop48,
- ICLASS_ae_iclass_movp48,
- ICLASS_ae_iclass_selp24_ll,
- ICLASS_ae_iclass_selp24_lh,
- ICLASS_ae_iclass_selp24_hl,
- ICLASS_ae_iclass_selp24_hh,
- ICLASS_ae_iclass_movtp24x2,
- ICLASS_ae_iclass_movfp24x2,
- ICLASS_ae_iclass_movtp48,
- ICLASS_ae_iclass_movfp48,
- ICLASS_ae_iclass_movpa24x2,
- ICLASS_ae_iclass_truncp24a32x2,
- ICLASS_ae_iclass_cvta32p24_l,
- ICLASS_ae_iclass_cvta32p24_h,
- ICLASS_ae_iclass_cvtp24a16x2_ll,
- ICLASS_ae_iclass_cvtp24a16x2_lh,
- ICLASS_ae_iclass_cvtp24a16x2_hl,
- ICLASS_ae_iclass_cvtp24a16x2_hh,
- ICLASS_ae_iclass_truncp24q48x2,
- ICLASS_ae_iclass_truncp16,
- ICLASS_ae_iclass_roundsp24q48sym,
- ICLASS_ae_iclass_roundsp24q48asym,
- ICLASS_ae_iclass_roundsp16q48sym,
- ICLASS_ae_iclass_roundsp16q48asym,
- ICLASS_ae_iclass_roundsp16sym,
- ICLASS_ae_iclass_roundsp16asym,
- ICLASS_ae_iclass_zeroq56,
- ICLASS_ae_iclass_movq56,
- ICLASS_ae_iclass_movtq56,
- ICLASS_ae_iclass_movfq56,
- ICLASS_ae_iclass_cvtq48a32s,
- ICLASS_ae_iclass_cvtq48p24s_l,
- ICLASS_ae_iclass_cvtq48p24s_h,
- ICLASS_ae_iclass_satq48s,
- ICLASS_ae_iclass_truncq32,
- ICLASS_ae_iclass_roundsq32sym,
- ICLASS_ae_iclass_roundsq32asym,
- ICLASS_ae_iclass_trunca32q48,
- ICLASS_ae_iclass_movap24s_l,
- ICLASS_ae_iclass_movap24s_h,
- ICLASS_ae_iclass_trunca16p24s_l,
- ICLASS_ae_iclass_trunca16p24s_h,
- ICLASS_ae_iclass_addp24,
- ICLASS_ae_iclass_subp24,
- ICLASS_ae_iclass_negp24,
- ICLASS_ae_iclass_absp24,
- ICLASS_ae_iclass_maxp24s,
- ICLASS_ae_iclass_minp24s,
- ICLASS_ae_iclass_maxbp24s,
- ICLASS_ae_iclass_minbp24s,
- ICLASS_ae_iclass_addsp24s,
- ICLASS_ae_iclass_subsp24s,
- ICLASS_ae_iclass_negsp24s,
- ICLASS_ae_iclass_abssp24s,
- ICLASS_ae_iclass_andp48,
- ICLASS_ae_iclass_nandp48,
- ICLASS_ae_iclass_orp48,
- ICLASS_ae_iclass_xorp48,
- ICLASS_ae_iclass_ltp24s,
- ICLASS_ae_iclass_lep24s,
- ICLASS_ae_iclass_eqp24,
- ICLASS_ae_iclass_addq56,
- ICLASS_ae_iclass_subq56,
- ICLASS_ae_iclass_negq56,
- ICLASS_ae_iclass_absq56,
- ICLASS_ae_iclass_maxq56s,
- ICLASS_ae_iclass_minq56s,
- ICLASS_ae_iclass_maxbq56s,
- ICLASS_ae_iclass_minbq56s,
- ICLASS_ae_iclass_addsq56s,
- ICLASS_ae_iclass_subsq56s,
- ICLASS_ae_iclass_negsq56s,
- ICLASS_ae_iclass_abssq56s,
- ICLASS_ae_iclass_andq56,
- ICLASS_ae_iclass_nandq56,
- ICLASS_ae_iclass_orq56,
- ICLASS_ae_iclass_xorq56,
- ICLASS_ae_iclass_sllip24,
- ICLASS_ae_iclass_srlip24,
- ICLASS_ae_iclass_sraip24,
- ICLASS_ae_iclass_sllsp24,
- ICLASS_ae_iclass_srlsp24,
- ICLASS_ae_iclass_srasp24,
- ICLASS_ae_iclass_sllisp24s,
- ICLASS_ae_iclass_sllssp24s,
- ICLASS_ae_iclass_slliq56,
- ICLASS_ae_iclass_srliq56,
- ICLASS_ae_iclass_sraiq56,
- ICLASS_ae_iclass_sllsq56,
- ICLASS_ae_iclass_srlsq56,
- ICLASS_ae_iclass_srasq56,
- ICLASS_ae_iclass_sllaq56,
- ICLASS_ae_iclass_srlaq56,
- ICLASS_ae_iclass_sraaq56,
- ICLASS_ae_iclass_sllisq56s,
- ICLASS_ae_iclass_sllssq56s,
- ICLASS_ae_iclass_sllasq56s,
- ICLASS_ae_iclass_ltq56s,
- ICLASS_ae_iclass_leq56s,
- ICLASS_ae_iclass_eqq56,
- ICLASS_ae_iclass_nsaq56s,
- ICLASS_ae_iclass_mulsrfq32sp24s_h,
- ICLASS_ae_iclass_mulsrfq32sp24s_l,
- ICLASS_ae_iclass_mularfq32sp24s_h,
- ICLASS_ae_iclass_mularfq32sp24s_l,
- ICLASS_ae_iclass_mulrfq32sp24s_h,
- ICLASS_ae_iclass_mulrfq32sp24s_l,
- ICLASS_ae_iclass_mulsfq32sp24s_h,
- ICLASS_ae_iclass_mulsfq32sp24s_l,
- ICLASS_ae_iclass_mulafq32sp24s_h,
- ICLASS_ae_iclass_mulafq32sp24s_l,
- ICLASS_ae_iclass_mulfq32sp24s_h,
- ICLASS_ae_iclass_mulfq32sp24s_l,
- ICLASS_ae_iclass_mulfs32p16s_ll,
- ICLASS_ae_iclass_mulfp24s_ll,
- ICLASS_ae_iclass_mulp24s_ll,
- ICLASS_ae_iclass_mulfs32p16s_lh,
- ICLASS_ae_iclass_mulfp24s_lh,
- ICLASS_ae_iclass_mulp24s_lh,
- ICLASS_ae_iclass_mulfs32p16s_hl,
- ICLASS_ae_iclass_mulfp24s_hl,
- ICLASS_ae_iclass_mulp24s_hl,
- ICLASS_ae_iclass_mulfs32p16s_hh,
- ICLASS_ae_iclass_mulfp24s_hh,
- ICLASS_ae_iclass_mulp24s_hh,
- ICLASS_ae_iclass_mulafs32p16s_ll,
- ICLASS_ae_iclass_mulafp24s_ll,
- ICLASS_ae_iclass_mulap24s_ll,
- ICLASS_ae_iclass_mulafs32p16s_lh,
- ICLASS_ae_iclass_mulafp24s_lh,
- ICLASS_ae_iclass_mulap24s_lh,
- ICLASS_ae_iclass_mulafs32p16s_hl,
- ICLASS_ae_iclass_mulafp24s_hl,
- ICLASS_ae_iclass_mulap24s_hl,
- ICLASS_ae_iclass_mulafs32p16s_hh,
- ICLASS_ae_iclass_mulafp24s_hh,
- ICLASS_ae_iclass_mulap24s_hh,
- ICLASS_ae_iclass_mulsfs32p16s_ll,
- ICLASS_ae_iclass_mulsfp24s_ll,
- ICLASS_ae_iclass_mulsp24s_ll,
- ICLASS_ae_iclass_mulsfs32p16s_lh,
- ICLASS_ae_iclass_mulsfp24s_lh,
- ICLASS_ae_iclass_mulsp24s_lh,
- ICLASS_ae_iclass_mulsfs32p16s_hl,
- ICLASS_ae_iclass_mulsfp24s_hl,
- ICLASS_ae_iclass_mulsp24s_hl,
- ICLASS_ae_iclass_mulsfs32p16s_hh,
- ICLASS_ae_iclass_mulsfp24s_hh,
- ICLASS_ae_iclass_mulsp24s_hh,
- ICLASS_ae_iclass_mulafs56p24s_ll,
- ICLASS_ae_iclass_mulas56p24s_ll,
- ICLASS_ae_iclass_mulafs56p24s_lh,
- ICLASS_ae_iclass_mulas56p24s_lh,
- ICLASS_ae_iclass_mulafs56p24s_hl,
- ICLASS_ae_iclass_mulas56p24s_hl,
- ICLASS_ae_iclass_mulafs56p24s_hh,
- ICLASS_ae_iclass_mulas56p24s_hh,
- ICLASS_ae_iclass_mulsfs56p24s_ll,
- ICLASS_ae_iclass_mulss56p24s_ll,
- ICLASS_ae_iclass_mulsfs56p24s_lh,
- ICLASS_ae_iclass_mulss56p24s_lh,
- ICLASS_ae_iclass_mulsfs56p24s_hl,
- ICLASS_ae_iclass_mulss56p24s_hl,
- ICLASS_ae_iclass_mulsfs56p24s_hh,
- ICLASS_ae_iclass_mulss56p24s_hh,
- ICLASS_ae_iclass_mulfq32sp16s_l,
- ICLASS_ae_iclass_mulfq32sp16s_h,
- ICLASS_ae_iclass_mulfq32sp16u_l,
- ICLASS_ae_iclass_mulfq32sp16u_h,
- ICLASS_ae_iclass_mulq32sp16s_l,
- ICLASS_ae_iclass_mulq32sp16s_h,
- ICLASS_ae_iclass_mulq32sp16u_l,
- ICLASS_ae_iclass_mulq32sp16u_h,
- ICLASS_ae_iclass_mulafq32sp16s_l,
- ICLASS_ae_iclass_mulafq32sp16s_h,
- ICLASS_ae_iclass_mulafq32sp16u_l,
- ICLASS_ae_iclass_mulafq32sp16u_h,
- ICLASS_ae_iclass_mulaq32sp16s_l,
- ICLASS_ae_iclass_mulaq32sp16s_h,
- ICLASS_ae_iclass_mulaq32sp16u_l,
- ICLASS_ae_iclass_mulaq32sp16u_h,
- ICLASS_ae_iclass_mulsfq32sp16s_l,
- ICLASS_ae_iclass_mulsfq32sp16s_h,
- ICLASS_ae_iclass_mulsfq32sp16u_l,
- ICLASS_ae_iclass_mulsfq32sp16u_h,
- ICLASS_ae_iclass_mulsq32sp16s_l,
- ICLASS_ae_iclass_mulsq32sp16s_h,
- ICLASS_ae_iclass_mulsq32sp16u_l,
- ICLASS_ae_iclass_mulsq32sp16u_h,
- ICLASS_ae_iclass_mulzaaq32sp16s_ll,
- ICLASS_ae_iclass_mulzaafq32sp16s_ll,
- ICLASS_ae_iclass_mulzaaq32sp16u_ll,
- ICLASS_ae_iclass_mulzaafq32sp16u_ll,
- ICLASS_ae_iclass_mulzaaq32sp16s_hh,
- ICLASS_ae_iclass_mulzaafq32sp16s_hh,
- ICLASS_ae_iclass_mulzaaq32sp16u_hh,
- ICLASS_ae_iclass_mulzaafq32sp16u_hh,
- ICLASS_ae_iclass_mulzaaq32sp16s_lh,
- ICLASS_ae_iclass_mulzaafq32sp16s_lh,
- ICLASS_ae_iclass_mulzaaq32sp16u_lh,
- ICLASS_ae_iclass_mulzaafq32sp16u_lh,
- ICLASS_ae_iclass_mulzasq32sp16s_ll,
- ICLASS_ae_iclass_mulzasfq32sp16s_ll,
- ICLASS_ae_iclass_mulzasq32sp16u_ll,
- ICLASS_ae_iclass_mulzasfq32sp16u_ll,
- ICLASS_ae_iclass_mulzasq32sp16s_hh,
- ICLASS_ae_iclass_mulzasfq32sp16s_hh,
- ICLASS_ae_iclass_mulzasq32sp16u_hh,
- ICLASS_ae_iclass_mulzasfq32sp16u_hh,
- ICLASS_ae_iclass_mulzasq32sp16s_lh,
- ICLASS_ae_iclass_mulzasfq32sp16s_lh,
- ICLASS_ae_iclass_mulzasq32sp16u_lh,
- ICLASS_ae_iclass_mulzasfq32sp16u_lh,
- ICLASS_ae_iclass_mulzsaq32sp16s_ll,
- ICLASS_ae_iclass_mulzsafq32sp16s_ll,
- ICLASS_ae_iclass_mulzsaq32sp16u_ll,
- ICLASS_ae_iclass_mulzsafq32sp16u_ll,
- ICLASS_ae_iclass_mulzsaq32sp16s_hh,
- ICLASS_ae_iclass_mulzsafq32sp16s_hh,
- ICLASS_ae_iclass_mulzsaq32sp16u_hh,
- ICLASS_ae_iclass_mulzsafq32sp16u_hh,
- ICLASS_ae_iclass_mulzsaq32sp16s_lh,
- ICLASS_ae_iclass_mulzsafq32sp16s_lh,
- ICLASS_ae_iclass_mulzsaq32sp16u_lh,
- ICLASS_ae_iclass_mulzsafq32sp16u_lh,
- ICLASS_ae_iclass_mulzssq32sp16s_ll,
- ICLASS_ae_iclass_mulzssfq32sp16s_ll,
- ICLASS_ae_iclass_mulzssq32sp16u_ll,
- ICLASS_ae_iclass_mulzssfq32sp16u_ll,
- ICLASS_ae_iclass_mulzssq32sp16s_hh,
- ICLASS_ae_iclass_mulzssfq32sp16s_hh,
- ICLASS_ae_iclass_mulzssq32sp16u_hh,
- ICLASS_ae_iclass_mulzssfq32sp16u_hh,
- ICLASS_ae_iclass_mulzssq32sp16s_lh,
- ICLASS_ae_iclass_mulzssfq32sp16s_lh,
- ICLASS_ae_iclass_mulzssq32sp16u_lh,
- ICLASS_ae_iclass_mulzssfq32sp16u_lh,
- ICLASS_ae_iclass_mulzaafp24s_hh_ll,
- ICLASS_ae_iclass_mulzaap24s_hh_ll,
- ICLASS_ae_iclass_mulzaafp24s_hl_lh,
- ICLASS_ae_iclass_mulzaap24s_hl_lh,
- ICLASS_ae_iclass_mulzasfp24s_hh_ll,
- ICLASS_ae_iclass_mulzasp24s_hh_ll,
- ICLASS_ae_iclass_mulzasfp24s_hl_lh,
- ICLASS_ae_iclass_mulzasp24s_hl_lh,
- ICLASS_ae_iclass_mulzsafp24s_hh_ll,
- ICLASS_ae_iclass_mulzsap24s_hh_ll,
- ICLASS_ae_iclass_mulzsafp24s_hl_lh,
- ICLASS_ae_iclass_mulzsap24s_hl_lh,
- ICLASS_ae_iclass_mulzssfp24s_hh_ll,
- ICLASS_ae_iclass_mulzssp24s_hh_ll,
- ICLASS_ae_iclass_mulzssfp24s_hl_lh,
- ICLASS_ae_iclass_mulzssp24s_hl_lh,
- ICLASS_ae_iclass_mulaafp24s_hh_ll,
- ICLASS_ae_iclass_mulaap24s_hh_ll,
- ICLASS_ae_iclass_mulaafp24s_hl_lh,
- ICLASS_ae_iclass_mulaap24s_hl_lh,
- ICLASS_ae_iclass_mulasfp24s_hh_ll,
- ICLASS_ae_iclass_mulasp24s_hh_ll,
- ICLASS_ae_iclass_mulasfp24s_hl_lh,
- ICLASS_ae_iclass_mulasp24s_hl_lh,
- ICLASS_ae_iclass_mulsafp24s_hh_ll,
- ICLASS_ae_iclass_mulsap24s_hh_ll,
- ICLASS_ae_iclass_mulsafp24s_hl_lh,
- ICLASS_ae_iclass_mulsap24s_hl_lh,
- ICLASS_ae_iclass_mulssfp24s_hh_ll,
- ICLASS_ae_iclass_mulssp24s_hh_ll,
- ICLASS_ae_iclass_mulssfp24s_hl_lh,
- ICLASS_ae_iclass_mulssp24s_hl_lh,
- ICLASS_ae_iclass_sha32,
- ICLASS_ae_iclass_vldl32t,
- ICLASS_ae_iclass_vldl16t,
- ICLASS_ae_iclass_vldl16c,
- ICLASS_ae_iclass_vldsht,
- ICLASS_ae_iclass_lb,
- ICLASS_ae_iclass_lbi,
- ICLASS_ae_iclass_lbk,
- ICLASS_ae_iclass_lbki,
- ICLASS_ae_iclass_db,
- ICLASS_ae_iclass_dbi,
- ICLASS_ae_iclass_vlel32t,
- ICLASS_ae_iclass_vlel16t,
- ICLASS_ae_iclass_sb,
- ICLASS_ae_iclass_sbi,
- ICLASS_ae_iclass_vles16c,
- ICLASS_ae_iclass_sbf,
- ICLASS_icls_AE_SLAASQ56S,
- ICLASS_icls_AE_ADDBRBA32,
- ICLASS_icls_AE_MINABSSP24S,
- ICLASS_icls_AE_MAXABSSP24S,
- ICLASS_icls_AE_MINABSSQ56S,
- ICLASS_icls_AE_MAXABSSQ56S,
- ICLASS_rur_ae_cbegin0,
- ICLASS_wur_ae_cbegin0,
- ICLASS_rur_ae_cend0,
- ICLASS_wur_ae_cend0,
- ICLASS_icls_AE_LP24X2_C,
- ICLASS_icls_AE_SP24X2S_C,
- ICLASS_icls_AE_LP24X2F_C,
- ICLASS_icls_AE_SP24X2F_C,
- ICLASS_icls_AE_LP16X2F_C,
- ICLASS_icls_AE_SP16X2F_C,
- ICLASS_icls_AE_LP24_C,
- ICLASS_icls_AE_SP24S_L_C,
- ICLASS_icls_AE_LP24F_C,
- ICLASS_icls_AE_SP24F_L_C,
- ICLASS_icls_AE_LP16F_C,
- ICLASS_icls_AE_SP16F_L_C,
- ICLASS_icls_AE_LQ56_C,
- ICLASS_icls_AE_SQ56S_C,
- ICLASS_icls_AE_LQ32F_C,
- ICLASS_icls_AE_SQ32F_C,
- ICLASS_rur_expstate,
- ICLASS_wur_expstate,
- ICLASS_iclass_READ_IMPWIRE,
- ICLASS_iclass_SETB_EXPSTATE,
- ICLASS_iclass_CLRB_EXPSTATE,
- ICLASS_iclass_WRMSK_EXPSTATE
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80200;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2300;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c0000;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580000;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x540000;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0000;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb0000;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70000;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6c0000;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x804;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60000;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10f;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4300;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5300;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x94;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4830;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4831;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4816;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4930;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4931;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4916;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa000;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb000;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc800;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc00;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd60f;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8000;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd000;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc000;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd30f;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00f;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9000;
-}
-
-static void
-Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7e03e;
-}
-
-static void
-Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe73f;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200c00;
-}
-
-static void
-Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100002;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200d00;
-}
-
-static void
-Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200002;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb81;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1381;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2381;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4b81;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4d01;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe;
-}
-
-static void
-Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf81;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf;
-}
-
-static void
-Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4d81;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b81;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2501;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3;
-}
-
-static void
-Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4f01;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680000;
-}
-
-static void
-Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x690000;
-}
-
-static void
-Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1800003;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6b0000;
-}
-
-static void
-Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800003;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6a0000;
-}
-
-static void
-Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000003;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700600;
-}
-
-static void
-Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700e00;
-}
-
-static void
-Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80002;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f0000;
-}
-
-static void
-Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1000003;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6e0000;
-}
-
-static void
-Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000003;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700100;
-}
-
-static void
-Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300002;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700900;
-}
-
-static void
-Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700a00;
-}
-
-static void
-Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600002;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700200;
-}
-
-static void
-Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680002;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700b00;
-}
-
-static void
-Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380002;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700300;
-}
-
-static void
-Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700002;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700800;
-}
-
-static void
-Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500002;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700000;
-}
-
-static void
-Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80004;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700400;
-}
-
-static void
-Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180002;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700c00;
-}
-
-static void
-Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780002;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700500;
-}
-
-static void
-Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580002;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700d00;
-}
-
-static void
-Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280002;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x640000;
-}
-
-static void
-Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x101;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x650000;
-}
-
-static void
-Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x181;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x670000;
-}
-
-static void
-Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x281;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x660000;
-}
-
-static void
-Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x681;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500000;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40;
-}
-
-static void
-Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0000;
-}
-
-static void
-Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x983d01;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200100;
-}
-
-static void
-Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200004;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200900;
-}
-
-static void
-Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100004;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200200;
-}
-
-static void
-Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400004;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180004;
-}
-
-static void
-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0800;
-}
-
-static void
-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0900;
-}
-
-static void
-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0a00;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200a00;
-}
-
-static void
-Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x301;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x38;
-}
-
-static void
-Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7381;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x39;
-}
-
-static void
-Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd01;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a;
-}
-
-static void
-Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x701;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b;
-}
-
-static void
-Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x581;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ed81;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1006;
-}
-
-static void
-Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ed81;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0200;
-}
-
-static void
-Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36001;
-}
-
-static void
-Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb83d01;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20000;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1500;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200500;
-}
-
-static void
-Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280004;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200600;
-}
-
-static void
-Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300004;
-}
-
-static void
-Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x95;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200400;
-}
-
-static void
-Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380004;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4;
-}
-
-static void
-Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x983d81;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x104;
-}
-
-static void
-Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4183d01;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x204;
-}
-
-static void
-Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2183d01;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x304;
-}
-
-static void
-Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1183d01;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404;
-}
-
-static void
-Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18e501;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1a;
-}
-
-static void
-Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2806f81;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18;
-}
-
-static void
-Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4781;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x19;
-}
-
-static void
-Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7ed81;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b;
-}
-
-static void
-Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5ed81;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10;
-}
-
-static void
-Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x501;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x12;
-}
-
-static void
-Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x381;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x14;
-}
-
-static void
-Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd81;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0200;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0200;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10200;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20200;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30200;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600;
-}
-
-static void
-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130;
-}
-
-static void
-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x131;
-}
-
-static void
-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x116;
-}
-
-static void
-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230;
-}
-
-static void
-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x231;
-}
-
-static void
-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x216;
-}
-
-static void
-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30;
-}
-
-static void
-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31;
-}
-
-static void
-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x330;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x331;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x316;
-}
-
-static void
-Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6130;
-}
-
-static void
-Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6131;
-}
-
-static void
-Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6116;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x531;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x516;
-}
-
-static void
-Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb030;
-}
-
-static void
-Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb031;
-}
-
-static void
-Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd030;
-}
-
-static void
-Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf330;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe630;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe631;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe616;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb130;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb131;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb116;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd130;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd131;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd116;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb230;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb231;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb216;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd230;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd231;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd216;
-}
-
-static void
-Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb330;
-}
-
-static void
-Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb331;
-}
-
-static void
-Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb316;
-}
-
-static void
-Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd330;
-}
-
-static void
-Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd331;
-}
-
-static void
-Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd316;
-}
-
-static void
-Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb430;
-}
-
-static void
-Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb431;
-}
-
-static void
-Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb416;
-}
-
-static void
-Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd430;
-}
-
-static void
-Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd431;
-}
-
-static void
-Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd416;
-}
-
-static void
-Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb530;
-}
-
-static void
-Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb531;
-}
-
-static void
-Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb516;
-}
-
-static void
-Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd530;
-}
-
-static void
-Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd531;
-}
-
-static void
-Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd516;
-}
-
-static void
-Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb630;
-}
-
-static void
-Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb631;
-}
-
-static void
-Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb616;
-}
-
-static void
-Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd630;
-}
-
-static void
-Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd631;
-}
-
-static void
-Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd616;
-}
-
-static void
-Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb730;
-}
-
-static void
-Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb731;
-}
-
-static void
-Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb716;
-}
-
-static void
-Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd730;
-}
-
-static void
-Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd731;
-}
-
-static void
-Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd716;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc230;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc231;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc216;
-}
-
-static void
-Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc330;
-}
-
-static void
-Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc331;
-}
-
-static void
-Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc316;
-}
-
-static void
-Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc430;
-}
-
-static void
-Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc431;
-}
-
-static void
-Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc416;
-}
-
-static void
-Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc530;
-}
-
-static void
-Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc531;
-}
-
-static void
-Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc516;
-}
-
-static void
-Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc630;
-}
-
-static void
-Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc631;
-}
-
-static void
-Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc616;
-}
-
-static void
-Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc730;
-}
-
-static void
-Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc731;
-}
-
-static void
-Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc716;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xee30;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xee31;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xee16;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc030;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc031;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc016;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe830;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe831;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe816;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf430;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf431;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf416;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf530;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf531;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf516;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xeb30;
-}
-
-static void
-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe730;
-}
-
-static void
-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe731;
-}
-
-static void
-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe716;
-}
-
-static void
-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c;
-}
-
-static void
-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d;
-}
-
-static void
-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x28;
-}
-
-static void
-Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2a;
-}
-
-static void
-Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2b;
-}
-
-static void
-Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400047;
-}
-
-static void
-Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400057;
-}
-
-static void
-Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400067;
-}
-
-static void
-Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400077;
-}
-
-static void
-Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400007;
-}
-
-static void
-Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400017;
-}
-
-static void
-Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400027;
-}
-
-static void
-Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400037;
-}
-
-static void
-Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400043;
-}
-
-static void
-Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400053;
-}
-
-static void
-Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400063;
-}
-
-static void
-Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400073;
-}
-
-static void
-Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400046;
-}
-
-static void
-Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400056;
-}
-
-static void
-Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400066;
-}
-
-static void
-Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400076;
-}
-
-static void
-Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400042;
-}
-
-static void
-Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400052;
-}
-
-static void
-Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400062;
-}
-
-static void
-Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400072;
-}
-
-static void
-Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400087;
-}
-
-static void
-Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400097;
-}
-
-static void
-Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a7;
-}
-
-static void
-Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b7;
-}
-
-static void
-Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000c7;
-}
-
-static void
-Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000d7;
-}
-
-static void
-Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000e7;
-}
-
-static void
-Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000f7;
-}
-
-static void
-Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400083;
-}
-
-static void
-Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400093;
-}
-
-static void
-Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a3;
-}
-
-static void
-Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b3;
-}
-
-static void
-Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000c3;
-}
-
-static void
-Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000d3;
-}
-
-static void
-Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000e3;
-}
-
-static void
-Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000f3;
-}
-
-static void
-Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400086;
-}
-
-static void
-Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400096;
-}
-
-static void
-Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a6;
-}
-
-static void
-Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b6;
-}
-
-static void
-Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000c6;
-}
-
-static void
-Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000d6;
-}
-
-static void
-Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000e6;
-}
-
-static void
-Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000f6;
-}
-
-static void
-Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400082;
-}
-
-static void
-Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400092;
-}
-
-static void
-Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a2;
-}
-
-static void
-Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b2;
-}
-
-static void
-Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000c2;
-}
-
-static void
-Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000d2;
-}
-
-static void
-Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000e2;
-}
-
-static void
-Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000f2;
-}
-
-static void
-Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400085;
-}
-
-static void
-Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400084;
-}
-
-static void
-Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400095;
-}
-
-static void
-Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400094;
-}
-
-static void
-Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a5;
-}
-
-static void
-Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a4;
-}
-
-static void
-Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b5;
-}
-
-static void
-Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b4;
-}
-
-static void
-Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400081;
-}
-
-static void
-Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400080;
-}
-
-static void
-Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400091;
-}
-
-static void
-Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400090;
-}
-
-static void
-Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a1;
-}
-
-static void
-Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a0;
-}
-
-static void
-Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b1;
-}
-
-static void
-Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b0;
-}
-
-static void
-Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400009;
-}
-
-static void
-Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400008;
-}
-
-static void
-Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2030;
-}
-
-static void
-Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2031;
-}
-
-static void
-Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2016;
-}
-
-static void
-Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2130;
-}
-
-static void
-Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2131;
-}
-
-static void
-Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2116;
-}
-
-static void
-Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2230;
-}
-
-static void
-Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2231;
-}
-
-static void
-Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2216;
-}
-
-static void
-Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2330;
-}
-
-static void
-Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2331;
-}
-
-static void
-Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2316;
-}
-
-static void
-Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1030;
-}
-
-static void
-Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1031;
-}
-
-static void
-Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1016;
-}
-
-static void
-Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1130;
-}
-
-static void
-Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1131;
-}
-
-static void
-Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1116;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10300;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe230;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe231;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe331;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe430;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe431;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe416;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd20f;
-}
-
-static void
-Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9030;
-}
-
-static void
-Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9031;
-}
-
-static void
-Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9016;
-}
-
-static void
-Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa030;
-}
-
-static void
-Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa031;
-}
-
-static void
-Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa016;
-}
-
-static void
-Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9130;
-}
-
-static void
-Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9131;
-}
-
-static void
-Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9116;
-}
-
-static void
-Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa130;
-}
-
-static void
-Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa131;
-}
-
-static void
-Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa116;
-}
-
-static void
-Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8030;
-}
-
-static void
-Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8031;
-}
-
-static void
-Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8016;
-}
-
-static void
-Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8130;
-}
-
-static void
-Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8131;
-}
-
-static void
-Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8116;
-}
-
-static void
-Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6030;
-}
-
-static void
-Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6031;
-}
-
-static void
-Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6016;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe930;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe931;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe916;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xec30;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xec31;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xec16;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed30;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed31;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed16;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6830;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6831;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6816;
-}
-
-static void
-Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0700;
-}
-
-static void
-Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0700;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe1f;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10e1f;
-}
-
-static void
-Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5931;
-}
-
-static void
-Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20;
-}
-
-static void
-Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5381;
-}
-
-static void
-Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x21;
-}
-
-static void
-Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b81;
-}
-
-static void
-Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x22;
-}
-
-static void
-Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4581;
-}
-
-static void
-Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x23;
-}
-
-static void
-Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x781;
-}
-
-static void
-Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x24;
-}
-
-static void
-Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4f81;
-}
-
-static void
-Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800;
-}
-
-static void
-Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x96501;
-}
-
-static void
-Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900;
-}
-
-static void
-Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8e501;
-}
-
-static void
-Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00;
-}
-
-static void
-Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc6501;
-}
-
-static void
-Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00;
-}
-
-static void
-Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa6501;
-}
-
-static void
-Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0000;
-}
-
-static void
-Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2800003;
-}
-
-static void
-Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d0100;
-}
-
-static void
-Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000003;
-}
-
-static void
-Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c;
-}
-
-static void
-Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7b81;
-}
-
-static void
-Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d;
-}
-
-static void
-Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1501;
-}
-
-static void
-Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x430;
-}
-
-static void
-Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x431;
-}
-
-static void
-Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x416;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xea30;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xea31;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xea16;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf030;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf031;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf016;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf130;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf131;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf116;
-}
-
-static void
-Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf230;
-}
-
-static void
-Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf231;
-}
-
-static void
-Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf216;
-}
-
-static void
-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2c0700;
-}
-
-static void
-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e0700;
-}
-
-static void
-Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d0700;
-}
-
-static void
-Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d0720;
-}
-
-static void
-Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d0730;
-}
-
-static void
-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f0700;
-}
-
-static void
-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f;
-}
-
-static void
-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x21f;
-}
-
-static void
-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x11f;
-}
-
-static void
-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x31f;
-}
-
-static void
-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x240700;
-}
-
-static void
-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x250700;
-}
-
-static void
-Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2807f0;
-}
-
-static void
-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280740;
-}
-
-static void
-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280750;
-}
-
-static void
-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x260700;
-}
-
-static void
-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x270700;
-}
-
-static void
-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200700;
-}
-
-static void
-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210700;
-}
-
-static void
-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x220700;
-}
-
-static void
-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230700;
-}
-
-static void
-Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280700;
-}
-
-static void
-Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280720;
-}
-
-static void
-Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280730;
-}
-
-static void
-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x91f;
-}
-
-static void
-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81f;
-}
-
-static void
-Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2830;
-}
-
-static void
-Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2831;
-}
-
-static void
-Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2816;
-}
-
-static void
-Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5331;
-}
-
-static void
-Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5330;
-}
-
-static void
-Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5316;
-}
-
-static void
-Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a30;
-}
-
-static void
-Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a31;
-}
-
-static void
-Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5a16;
-}
-
-static void
-Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b30;
-}
-
-static void
-Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b31;
-}
-
-static void
-Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5b16;
-}
-
-static void
-Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c30;
-}
-
-static void
-Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c31;
-}
-
-static void
-Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5c16;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc05;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd05;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb05;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf05;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe05;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x405;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x305;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x705;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x605;
-}
-
-static void
-Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1f;
-}
-
-static void
-Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x105;
-}
-
-static void
-Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x905;
-}
-
-static void
-Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe030;
-}
-
-static void
-Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe031;
-}
-
-static void
-Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe016;
-}
-
-static void
-Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x33;
-}
-
-static void
-Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2b81;
-}
-
-static void
-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34;
-}
-
-static void
-Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b81;
-}
-
-static void
-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35;
-}
-
-static void
-Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3381;
-}
-
-static void
-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36;
-}
-
-static void
-Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6b81;
-}
-
-static void
-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x37;
-}
-
-static void
-Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6381;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe04;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf04;
-}
-
-static void
-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x32;
-}
-
-static void
-Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4701;
-}
-
-static void
-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200b00;
-}
-
-static void
-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200f00;
-}
-
-static void
-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200e00;
-}
-
-static void
-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc30;
-}
-
-static void
-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc31;
-}
-
-static void
-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc16;
-}
-
-static void
-Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6330;
-}
-
-static void
-Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6331;
-}
-
-static void
-Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6316;
-}
-
-static void
-Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2c;
-}
-
-static void
-Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d;
-}
-
-static void
-Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e;
-}
-
-static void
-Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f;
-}
-
-static void
-Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x604;
-}
-
-static void
-Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x704;
-}
-
-static void
-Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03e;
-}
-
-static void
-Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03f;
-}
-
-static void
-Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f03e;
-}
-
-static void
-Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf13f;
-}
-
-static void
-Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f03e;
-}
-
-static void
-Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf23f;
-}
-
-static void
-Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f03e;
-}
-
-static void
-Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf33f;
-}
-
-static void
-Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40809c;
-}
-
-static void
-Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000ac;
-}
-
-static void
-Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40909c;
-}
-
-static void
-Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4001ac;
-}
-
-static void
-Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40a09c;
-}
-
-static void
-Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4002ac;
-}
-
-static void
-Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40b09c;
-}
-
-static void
-Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4003ac;
-}
-
-static void
-Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40c09c;
-}
-
-static void
-Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4004ac;
-}
-
-static void
-Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40d09c;
-}
-
-static void
-Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4005ac;
-}
-
-static void
-Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40e09c;
-}
-
-static void
-Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4006ac;
-}
-
-static void
-Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40f09c;
-}
-
-static void
-Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4007ac;
-}
-
-static void
-Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81581;
-}
-
-static void
-Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40005a;
-}
-
-static void
-Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1781;
-}
-
-static void
-Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40009a;
-}
-
-static void
-Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81701;
-}
-
-static void
-Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000ca;
-}
-
-static void
-Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81781;
-}
-
-static void
-Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000fa;
-}
-
-static void
-Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81d81;
-}
-
-static void
-Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40085a;
-}
-
-static void
-Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81f01;
-}
-
-static void
-Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40089a;
-}
-
-static void
-Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81f81;
-}
-
-static void
-Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008ca;
-}
-
-static void
-Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5581;
-}
-
-static void
-Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008fa;
-}
-
-static void
-Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5701;
-}
-
-static void
-Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40006a;
-}
-
-static void
-Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5d01;
-}
-
-static void
-Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000aa;
-}
-
-static void
-Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85501;
-}
-
-static void
-Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000da;
-}
-
-static void
-Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5781;
-}
-
-static void
-Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000b;
-}
-
-static void
-Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d81;
-}
-
-static void
-Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40086a;
-}
-
-static void
-Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f01;
-}
-
-static void
-Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008aa;
-}
-
-static void
-Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81d01;
-}
-
-static void
-Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008da;
-}
-
-static void
-Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f81;
-}
-
-static void
-Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40080b;
-}
-
-static void
-Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85701;
-}
-
-static void
-Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40007a;
-}
-
-static void
-Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85d01;
-}
-
-static void
-Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000ba;
-}
-
-static void
-Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85781;
-}
-
-static void
-Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000ea;
-}
-
-static void
-Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85d81;
-}
-
-static void
-Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40001b;
-}
-
-static void
-Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5d81;
-}
-
-static void
-Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40087a;
-}
-
-static void
-Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5f01;
-}
-
-static void
-Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008ba;
-}
-
-static void
-Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5f81;
-}
-
-static void
-Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008ea;
-}
-
-static void
-Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85581;
-}
-
-static void
-Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40081b;
-}
-
-static void
-Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3501;
-}
-
-static void
-Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40002b;
-}
-
-static void
-Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6501;
-}
-
-static void
-Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40005b;
-}
-
-static void
-Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82581;
-}
-
-static void
-Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40008b;
-}
-
-static void
-Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2781;
-}
-
-static void
-Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000bb;
-}
-
-static void
-Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83501;
-}
-
-static void
-Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40082b;
-}
-
-static void
-Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3781;
-}
-
-static void
-Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40085b;
-}
-
-static void
-Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d81;
-}
-
-static void
-Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40088b;
-}
-
-static void
-Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f01;
-}
-
-static void
-Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008bb;
-}
-
-static void
-Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82f81;
-}
-
-static void
-Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40003b;
-}
-
-static void
-Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3581;
-}
-
-static void
-Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40006b;
-}
-
-static void
-Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3701;
-}
-
-static void
-Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40009b;
-}
-
-static void
-Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d01;
-}
-
-static void
-Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000cb;
-}
-
-static void
-Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85f81;
-}
-
-static void
-Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40083b;
-}
-
-static void
-Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2581;
-}
-
-static void
-Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40086b;
-}
-
-static void
-Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2701;
-}
-
-static void
-Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40089b;
-}
-
-static void
-Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d01;
-}
-
-static void
-Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008cb;
-}
-
-static void
-Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82d01;
-}
-
-static void
-Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40004b;
-}
-
-static void
-Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f81;
-}
-
-static void
-Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40007b;
-}
-
-static void
-Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82d81;
-}
-
-static void
-Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000ab;
-}
-
-static void
-Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82f01;
-}
-
-static void
-Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000db;
-}
-
-static void
-Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82701;
-}
-
-static void
-Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40084b;
-}
-
-static void
-Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x82781;
-}
-
-static void
-Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40087b;
-}
-
-static void
-Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2d81;
-}
-
-static void
-Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008ab;
-}
-
-static void
-Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2f01;
-}
-
-static void
-Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008db;
-}
-
-static void
-Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x206581;
-}
-
-static void
-Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40001c;
-}
-
-static void
-Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x406581;
-}
-
-static void
-Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40021c;
-}
-
-static void
-Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x606581;
-}
-
-static void
-Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40002c;
-}
-
-static void
-Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6781;
-}
-
-static void
-Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40022c;
-}
-
-static void
-Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6581;
-}
-
-static void
-Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40011c;
-}
-
-static void
-Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6701;
-}
-
-static void
-Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40031c;
-}
-
-static void
-Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d01;
-}
-
-static void
-Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40012c;
-}
-
-static void
-Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7501;
-}
-
-static void
-Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40032c;
-}
-
-static void
-Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83781;
-}
-
-static void
-Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40003c;
-}
-
-static void
-Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x183701;
-}
-
-static void
-Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40083c;
-}
-
-static void
-Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x183781;
-}
-
-static void
-Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40004c;
-}
-
-static void
-Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83d81;
-}
-
-static void
-Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40084c;
-}
-
-static void
-Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83581;
-}
-
-static void
-Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40043c;
-}
-
-static void
-Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83701;
-}
-
-static void
-Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400c3c;
-}
-
-static void
-Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83d01;
-}
-
-static void
-Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40044c;
-}
-
-static void
-Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x183581;
-}
-
-static void
-Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400c4c;
-}
-
-static void
-Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x46001;
-}
-
-static void
-Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86001;
-}
-
-static void
-Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86501;
-}
-
-static void
-Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40009c;
-}
-
-static void
-Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd081;
-}
-
-static void
-Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x24000;
-}
-
-static void
-Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x89001;
-}
-
-static void
-Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x14000;
-}
-
-static void
-Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd001;
-}
-
-static void
-Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc000;
-}
-
-static void
-Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9081;
-}
-
-static void
-Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000;
-}
-
-static void
-Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x402081;
-}
-
-static void
-Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x202081;
-}
-
-static void
-Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2001;
-}
-
-static void
-Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1001;
-}
-
-static void
-Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85f01;
-}
-
-static void
-Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000c;
-}
-
-static void
-Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f81;
-}
-
-static void
-Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40080c;
-}
-
-static void
-Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83f81;
-}
-
-static void
-Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000bc;
-}
-
-static void
-Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x83f01;
-}
-
-static void
-Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008bc;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5501;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000eb;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d01;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008eb;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1701;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000fb;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1581;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008fb;
-}
-
-static void
-Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20005;
-}
-
-static void
-Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86e01;
-}
-
-static void
-Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3881;
-}
-
-static void
-Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3481;
-}
-
-static void
-Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3281;
-}
-
-static void
-Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3081;
-}
-
-static void
-Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86401;
-}
-
-static void
-Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86201;
-}
-
-static void
-Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x284581;
-}
-
-static void
-Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380581;
-}
-
-static void
-Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xef01;
-}
-
-static void
-Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41409c;
-}
-
-static void
-Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x806f81;
-}
-
-static void
-Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41005e;
-}
-
-static void
-Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f81;
-}
-
-static void
-Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41006e;
-}
-
-static void
-Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x206701;
-}
-
-static void
-Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x43027e;
-}
-
-static void
-Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300581;
-}
-
-static void
-Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280581;
-}
-
-static void
-Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x488605;
-}
-
-static void
-Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c0581;
-}
-
-static void
-Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3a0581;
-}
-
-static void
-Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x390581;
-}
-
-static void
-Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x183d81;
-}
-
-static void
-Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41007e;
-}
-
-static void
-Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1083f01;
-}
-
-static void
-Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40007c;
-}
-
-static void
-Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x883f01;
-}
-
-static void
-Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40087c;
-}
-
-static void
-Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4083f01;
-}
-
-static void
-Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40008c;
-}
-
-static void
-Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2083f01;
-}
-
-static void
-Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40088c;
-}
-
-static void
-Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1081;
-}
-
-static void
-Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x89081;
-}
-
-static void
-Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16001;
-}
-
-static void
-Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6001;
-}
-
-static void
-Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81081;
-}
-
-static void
-Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5081;
-}
-
-static void
-Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x81;
-}
-
-static void
-Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5001;
-}
-
-static void
-Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8d001;
-}
-
-static void
-Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x26001;
-}
-
-static void
-Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa001;
-}
-
-static void
-Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9001;
-}
-
-static void
-Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85001;
-}
-
-static void
-Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x85081;
-}
-
-static void
-Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8d081;
-}
-
-static void
-Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x102081;
-}
-
-static void
-Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3001;
-}
-
-static void
-Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2081;
-}
-
-static void
-Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40005;
-}
-
-static void
-Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280605;
-}
-
-static void
-Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600605;
-}
-
-static void
-Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480605;
-}
-
-static void
-Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100605;
-}
-
-static void
-Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200605;
-}
-
-static void
-Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x205;
-}
-
-static void
-Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x605;
-}
-
-static void
-Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300605;
-}
-
-static void
-Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x484605;
-}
-
-static void
-Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500605;
-}
-
-static void
-Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80605;
-}
-
-static void
-Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400605;
-}
-
-static void
-Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180605;
-}
-
-static void
-Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380605;
-}
-
-static void
-Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x101;
-}
-
-static void
-Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x501;
-}
-
-static void
-Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x301;
-}
-
-static void
-Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86801;
-}
-
-static void
-Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86c01;
-}
-
-static void
-Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86a01;
-}
-
-static void
-Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x181;
-}
-
-static void
-Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86601;
-}
-
-static void
-Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6d81;
-}
-
-static void
-Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40005c;
-}
-
-static void
-Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16d81;
-}
-
-static void
-Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40105c;
-}
-
-static void
-Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xed81;
-}
-
-static void
-Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40205c;
-}
-
-static void
-Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16f01;
-}
-
-static void
-Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41009c;
-}
-
-static void
-Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80ef01;
-}
-
-static void
-Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41109c;
-}
-
-static void
-Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4ef01;
-}
-
-static void
-Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41209c;
-}
-
-static void
-Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1006f81;
-}
-
-static void
-Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41001e;
-}
-
-static void
-Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1806f81;
-}
-
-static void
-Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41002e;
-}
-
-static void
-Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4006f81;
-}
-
-static void
-Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41003e;
-}
-
-static void
-Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f01;
-}
-
-static void
-Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40305c;
-}
-
-static void
-Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2ef01;
-}
-
-static void
-Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41309c;
-}
-
-static void
-Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2006f81;
-}
-
-static void
-Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41004e;
-}
-
-static void
-Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10005;
-}
-
-static void
-Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x805;
-}
-
-static void
-Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x405;
-}
-
-static void
-Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x183d01;
-}
-
-static void
-Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41047e;
-}
-
-static void
-Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500901;
-}
-
-static void
-Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300901;
-}
-
-static void
-Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600901;
-}
-
-static void
-Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100901;
-}
-
-static void
-Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400901;
-}
-
-static void
-Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200901;
-}
-
-static void
-Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680901;
-}
-
-static void
-Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180901;
-}
-
-static void
-Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480901;
-}
-
-static void
-Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280901;
-}
-
-static void
-Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700901;
-}
-
-static void
-Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80901;
-}
-
-static void
-Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100086;
-}
-
-static void
-Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x88186;
-}
-
-static void
-Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180006;
-}
-
-static void
-Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c186;
-}
-
-static void
-Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c006;
-}
-
-static void
-Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x108006;
-}
-
-static void
-Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c106;
-}
-
-static void
-Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x88106;
-}
-
-static void
-Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x104006;
-}
-
-static void
-Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c086;
-}
-
-static void
-Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x88086;
-}
-
-static void
-Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100106;
-}
-
-static void
-Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4106;
-}
-
-static void
-Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200006;
-}
-
-static void
-Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc186;
-}
-
-static void
-Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4086;
-}
-
-static void
-Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100006;
-}
-
-static void
-Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc106;
-}
-
-static void
-Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x186;
-}
-
-static void
-Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80006;
-}
-
-static void
-Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc086;
-}
-
-static void
-Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400006;
-}
-
-static void
-Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8006;
-}
-
-static void
-Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8186;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180086;
-}
-
-static void
-Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x108186;
-}
-
-static void
-Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x188086;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10c186;
-}
-
-static void
-Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10c006;
-}
-
-static void
-Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x184186;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10c106;
-}
-
-static void
-Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x108106;
-}
-
-static void
-Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x184106;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10c086;
-}
-
-static void
-Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x108086;
-}
-
-static void
-Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x184086;
-}
-
-static void
-Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc006;
-}
-
-static void
-Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x88006;
-}
-
-static void
-Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8106;
-}
-
-static void
-Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x84006;
-}
-
-static void
-Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8086;
-}
-
-static void
-Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80106;
-}
-
-static void
-Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4186;
-}
-
-static void
-Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80086;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180186;
-}
-
-static void
-Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18c086;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x188006;
-}
-
-static void
-Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x188186;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x184006;
-}
-
-static void
-Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18c006;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180106;
-}
-
-static void
-Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x188106;
-}
-
-static void
-Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380381;
-}
-
-static void
-Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300381;
-}
-
-static void
-Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500381;
-}
-
-static void
-Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480381;
-}
-
-static void
-Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580381;
-}
-
-static void
-Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600381;
-}
-
-static void
-Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700381;
-}
-
-static void
-Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680381;
-}
-
-static void
-Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x381;
-}
-
-static void
-Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x901;
-}
-
-static void
-Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100381;
-}
-
-static void
-Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80381;
-}
-
-static void
-Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400381;
-}
-
-static void
-Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200381;
-}
-
-static void
-Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280381;
-}
-
-static void
-Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180381;
-}
-
-static void
-Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x581;
-}
-
-static void
-Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780381;
-}
-
-static void
-Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80581;
-}
-
-static void
-Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x701;
-}
-
-static void
-Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200581;
-}
-
-static void
-Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100581;
-}
-
-static void
-Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180581;
-}
-
-static void
-Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400581;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380002;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100002;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600002;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180002;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280002;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480002;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200002;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300002;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80002;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500002;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400002;
-}
-
-static void
-Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700002;
-}
-
-static void
-Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80003;
-}
-
-static void
-Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580002;
-}
-
-static void
-Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780002;
-}
-
-static void
-Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680002;
-}
-
-static void
-Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500003;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200004;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680003;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700003;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380003;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80004;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600003;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780003;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480003;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100004;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580003;
-}
-
-static void
-Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x580004;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280004;
-}
-
-static void
-Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x780004;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x480004;
-}
-
-static void
-Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500004;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400004;
-}
-
-static void
-Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x680004;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300004;
-}
-
-static void
-Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600004;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180004;
-}
-
-static void
-Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x700004;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x380004;
-}
-
-static void
-Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x204006;
-}
-
-static void
-Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280006;
-}
-
-static void
-Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x208006;
-}
-
-static void
-Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300006;
-}
-
-static void
-Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200186;
-}
-
-static void
-Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x204106;
-}
-
-static void
-Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x204086;
-}
-
-static void
-Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x204186;
-}
-
-static void
-Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x208086;
-}
-
-static void
-Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c006;
-}
-
-static void
-Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x208106;
-}
-
-static void
-Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x208186;
-}
-
-static void
-Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c086;
-}
-
-static void
-Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c186;
-}
-
-static void
-Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c106;
-}
-
-static void
-Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x280086;
-}
-
-static void
-Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x106;
-}
-
-static void
-Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x86;
-}
-
-static void
-Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4006;
-}
-
-static void
-Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80186;
-}
-
-static void
-Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x84106;
-}
-
-static void
-Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x84086;
-}
-
-static void
-Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x84186;
-}
-
-static void
-Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100186;
-}
-
-static void
-Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x104106;
-}
-
-static void
-Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x104086;
-}
-
-static void
-Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x104186;
-}
-
-static void
-Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18c106;
-}
-
-static void
-Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200086;
-}
-
-static void
-Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18c186;
-}
-
-static void
-Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200106;
-}
-
-static void
-Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x41000e;
-}
-
-static void
-Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000a;
-}
-
-static void
-Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40001a;
-}
-
-static void
-Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410e7e;
-}
-
-static void
-Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4008ac;
-}
-
-static void
-Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40006c;
-}
-
-static void
-Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x42000e;
-}
-
-static void
-Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40002a;
-}
-
-static void
-Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000e;
-}
-
-static void
-Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40010f;
-}
-
-static void
-Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40020f;
-}
-
-static void
-Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40003a;
-}
-
-static void
-Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40004a;
-}
-
-static void
-Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40011f;
-}
-
-static void
-Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000f;
-}
-
-static void
-Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410c7e;
-}
-
-static void
-Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410d7e;
-}
-
-static void
-Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6006f81;
-}
-
-static void
-Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8e001;
-}
-
-static void
-Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe001;
-}
-
-static void
-Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x240005;
-}
-
-static void
-Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x440005;
-}
-
-static void
-Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6f03e;
-}
-
-static void
-Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf63f;
-}
-
-static void
-Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7f03e;
-}
-
-static void
-Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf73f;
-}
-
-static void
-Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7f01;
-}
-
-static void
-Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87781;
-}
-
-static void
-Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87f01;
-}
-
-static void
-Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7781;
-}
-
-static void
-Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87d01;
-}
-
-static void
-Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87581;
-}
-
-static void
-Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7701;
-}
-
-static void
-Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87d81;
-}
-
-static void
-Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87701;
-}
-
-static void
-Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7d81;
-}
-
-static void
-Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7d01;
-}
-
-static void
-Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7581;
-}
-
-static void
-Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x207501;
-}
-
-static void
-Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x87f81;
-}
-
-static void
-Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x407501;
-}
-
-static void
-Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7f81;
-}
-
-static void
-Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6e03e;
-}
-
-static void
-Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe63f;
-}
-
-static void
-Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0;
-}
-
-static void
-Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e0;
-}
-
-static void
-Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x21e0;
-}
-
-static void
-Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2e0;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
- Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
- Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
- Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
- Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
- Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
- Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
- Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
- Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
- Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = {
- Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
- Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
- Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
- Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
- Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
- Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
- Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
- Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
- Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
- Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
- Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
- Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
- Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
- Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
- Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
- Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
- Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
- Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
- Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
- Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
- Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
- Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
- Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
- Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
- Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
- Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
- Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
- Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
- Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
- Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
- Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
- Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
- Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
- Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
- Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
- Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
- Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
- Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
- Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
- Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
- Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
- Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
- Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
- Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
- Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
- Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
- Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
- Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
- Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
- Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
- Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
- Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
- Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
- Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
- Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
- Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
- Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
- Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
- Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
- Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
- Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
- Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
- Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
- Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
- Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
- Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
- Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
- Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
- Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
- Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
- Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
- Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
- Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
- Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
- Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
- Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
- Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
- Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
- Opcode_diu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = {
- Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = {
- Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = {
- Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
- Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
- Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
- Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
- Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
- Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
- Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
- Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
- Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
- Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
- Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
- Opcode_quou_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
- Opcode_quos_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
- Opcode_remu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
- Opcode_rems_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
- Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
- Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
- Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
- Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
- Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
- Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
- Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
- Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
- Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
- Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
- Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
- Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
- Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
- Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
- Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
- Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
- Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
- Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
- Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
- Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
- Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
- Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
- Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
- Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
- Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
- Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
- Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
- Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
- Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
- Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
- Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
- Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
- Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
- Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
- Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
- Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
- Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
- Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
- Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
- Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
- Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
- Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
- Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
- Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
- Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
- Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
- Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
- Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
- Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
- Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
- Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
- Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
- Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
- Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
- Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
- Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
- Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
- Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
- Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
- Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
- Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
- Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
- Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
- Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
- Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
- Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
- Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
- Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
- Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
- Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
- Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
- Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
- Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
- Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
- Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
- Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
- Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
- Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
- Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
- Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
- Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
- Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
- Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
- Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
- Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
- Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
- Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
- Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
- Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
- Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
- Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
- Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
- Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
- Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
- Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
- 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
- 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
- Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
- Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
- Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
- Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
- 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
- Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
- Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
- Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
- Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
- Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
- Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
- Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
- Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
- Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
- Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
- Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
- Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
- Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
- Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
- Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
- Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
- Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
- Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
- Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
- Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
- Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
- Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
- Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
- Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
- Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
- Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
- Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
- Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
- Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
- Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
- Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
- Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
- Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
- Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
- Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = {
- Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = {
- Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = {
- Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = {
- Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = {
- 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
- Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
- Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
- Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
- Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
- Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
- Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0
-};
-
-
-
-
-\f
-/* Opcode table. */
-
-static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_shift32x5, 3 },
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_shift32x5, 3 },
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", ICLASS_xt_iclass_excw,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", ICLASS_xt_iclass_rfe,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", ICLASS_xt_iclass_rfde,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", ICLASS_xt_iclass_syscall,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "call12", ICLASS_xt_iclass_call12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", ICLASS_xt_iclass_call8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", ICLASS_xt_iclass_call4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", ICLASS_xt_iclass_callx12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", ICLASS_xt_iclass_callx8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", ICLASS_xt_iclass_callx4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", ICLASS_xt_iclass_entry,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", ICLASS_xt_iclass_movsp,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", ICLASS_xt_iclass_rotw,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", ICLASS_xt_iclass_l32e,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", ICLASS_xt_iclass_s32e,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", ICLASS_xt_iclass_add_n,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", ICLASS_xt_iclass_addi_n,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", ICLASS_xt_iclass_ill_n,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", ICLASS_xt_iclass_loadi4,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", ICLASS_xt_iclass_mov_n,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", ICLASS_xt_iclass_movi_n,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", ICLASS_xt_iclass_nopn,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", ICLASS_xt_iclass_retn,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", ICLASS_xt_iclass_storei4,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "rur.threadptr", ICLASS_rur_threadptr,
- 0,
- Opcode_rur_threadptr_encode_fns, 0, 0 },
- { "wur.threadptr", ICLASS_wur_threadptr,
- 0,
- Opcode_wur_threadptr_encode_fns, 0, 0 },
- { "addi", ICLASS_xt_iclass_addi,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", ICLASS_xt_iclass_addmi,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", ICLASS_xt_iclass_bit,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", ICLASS_xt_iclass_bit,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", ICLASS_xt_iclass_bit,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", ICLASS_xt_iclass_call0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", ICLASS_xt_iclass_callx0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", ICLASS_xt_iclass_exti,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", ICLASS_xt_iclass_ill,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", ICLASS_xt_iclass_jump,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", ICLASS_xt_iclass_jumpx,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", ICLASS_xt_iclass_l16ui,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", ICLASS_xt_iclass_l16si,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", ICLASS_xt_iclass_l32i,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", ICLASS_xt_iclass_l32r,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", ICLASS_xt_iclass_l8i,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", ICLASS_xt_iclass_loop,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", ICLASS_xt_iclass_movi,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", ICLASS_xt_iclass_neg,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", ICLASS_xt_iclass_neg,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", ICLASS_xt_iclass_nop,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", ICLASS_xt_iclass_return,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "simcall", ICLASS_xt_iclass_simcall,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "s16i", ICLASS_xt_iclass_s16i,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", ICLASS_xt_iclass_s32i,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s32nb", ICLASS_xt_iclass_s32nb,
- 0,
- Opcode_s32nb_encode_fns, 0, 0 },
- { "s8i", ICLASS_xt_iclass_s8i,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", ICLASS_xt_iclass_sari,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", ICLASS_xt_iclass_shifts,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", ICLASS_xt_iclass_shiftst,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", ICLASS_xt_iclass_slli,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", ICLASS_xt_iclass_srai,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", ICLASS_xt_iclass_srli,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", ICLASS_xt_iclass_memw,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", ICLASS_xt_iclass_extw,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", ICLASS_xt_iclass_isync,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", ICLASS_xt_iclass_rsil,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
- 0,
- Opcode_rsr_memctl_encode_fns, 0, 0 },
- { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
- 0,
- Opcode_wsr_memctl_encode_fns, 0, 0 },
- { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
- 0,
- Opcode_xsr_memctl_encode_fns, 0, 0 },
- { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
- 0,
- Opcode_rsr_configid0_encode_fns, 0, 0 },
- { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
- 0,
- Opcode_wsr_configid0_encode_fns, 0, 0 },
- { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
- 0,
- Opcode_rsr_configid1_encode_fns, 0, 0 },
- { "rsr.243", ICLASS_xt_iclass_rsr_243,
- 0,
- Opcode_rsr_243_encode_fns, 0, 0 },
- { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
- 0,
- Opcode_rsr_epc5_encode_fns, 0, 0 },
- { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
- 0,
- Opcode_wsr_epc5_encode_fns, 0, 0 },
- { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
- 0,
- Opcode_xsr_epc5_encode_fns, 0, 0 },
- { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
- 0,
- Opcode_rsr_excsave5_encode_fns, 0, 0 },
- { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
- 0,
- Opcode_wsr_excsave5_encode_fns, 0, 0 },
- { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
- 0,
- Opcode_xsr_excsave5_encode_fns, 0, 0 },
- { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
- 0,
- Opcode_rsr_epc6_encode_fns, 0, 0 },
- { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
- 0,
- Opcode_wsr_epc6_encode_fns, 0, 0 },
- { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
- 0,
- Opcode_xsr_epc6_encode_fns, 0, 0 },
- { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
- 0,
- Opcode_rsr_excsave6_encode_fns, 0, 0 },
- { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
- 0,
- Opcode_wsr_excsave6_encode_fns, 0, 0 },
- { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
- 0,
- Opcode_xsr_excsave6_encode_fns, 0, 0 },
- { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
- 0,
- Opcode_rsr_epc7_encode_fns, 0, 0 },
- { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
- 0,
- Opcode_wsr_epc7_encode_fns, 0, 0 },
- { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
- 0,
- Opcode_xsr_epc7_encode_fns, 0, 0 },
- { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
- 0,
- Opcode_rsr_excsave7_encode_fns, 0, 0 },
- { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
- 0,
- Opcode_wsr_excsave7_encode_fns, 0, 0 },
- { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
- 0,
- Opcode_xsr_excsave7_encode_fns, 0, 0 },
- { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
- 0,
- Opcode_rsr_eps5_encode_fns, 0, 0 },
- { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
- 0,
- Opcode_wsr_eps5_encode_fns, 0, 0 },
- { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
- 0,
- Opcode_xsr_eps5_encode_fns, 0, 0 },
- { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
- 0,
- Opcode_rsr_eps6_encode_fns, 0, 0 },
- { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
- 0,
- Opcode_wsr_eps6_encode_fns, 0, 0 },
- { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
- 0,
- Opcode_xsr_eps6_encode_fns, 0, 0 },
- { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
- 0,
- Opcode_rsr_eps7_encode_fns, 0, 0 },
- { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
- 0,
- Opcode_wsr_eps7_encode_fns, 0, 0 },
- { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
- 0,
- Opcode_xsr_eps7_encode_fns, 0, 0 },
- { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "mul16u", ICLASS_xt_mul16,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", ICLASS_xt_mul16,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "mull", ICLASS_xt_mul32,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "muluh", ICLASS_xt_mul32h,
- 0,
- Opcode_muluh_encode_fns, 0, 0 },
- { "mulsh", ICLASS_xt_mul32h,
- 0,
- Opcode_mulsh_encode_fns, 0, 0 },
- { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_ll_encode_fns, 0, 0 },
- { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_hl_encode_fns, 0, 0 },
- { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_lh_encode_fns, 0, 0 },
- { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_mul_aa_hh_encode_fns, 0, 0 },
- { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_ll_encode_fns, 0, 0 },
- { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_hl_encode_fns, 0, 0 },
- { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_lh_encode_fns, 0, 0 },
- { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
- 0,
- Opcode_umul_aa_hh_encode_fns, 0, 0 },
- { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_ll_encode_fns, 0, 0 },
- { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_hl_encode_fns, 0, 0 },
- { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_lh_encode_fns, 0, 0 },
- { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
- 0,
- Opcode_mul_ad_hh_encode_fns, 0, 0 },
- { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_ll_encode_fns, 0, 0 },
- { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_hl_encode_fns, 0, 0 },
- { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_lh_encode_fns, 0, 0 },
- { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
- 0,
- Opcode_mul_da_hh_encode_fns, 0, 0 },
- { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_ll_encode_fns, 0, 0 },
- { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_hl_encode_fns, 0, 0 },
- { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_lh_encode_fns, 0, 0 },
- { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
- 0,
- Opcode_mul_dd_hh_encode_fns, 0, 0 },
- { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_ll_encode_fns, 0, 0 },
- { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_hl_encode_fns, 0, 0 },
- { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_lh_encode_fns, 0, 0 },
- { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_mula_aa_hh_encode_fns, 0, 0 },
- { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_ll_encode_fns, 0, 0 },
- { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_hl_encode_fns, 0, 0 },
- { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_lh_encode_fns, 0, 0 },
- { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
- 0,
- Opcode_muls_aa_hh_encode_fns, 0, 0 },
- { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_ll_encode_fns, 0, 0 },
- { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_hl_encode_fns, 0, 0 },
- { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_lh_encode_fns, 0, 0 },
- { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_mula_ad_hh_encode_fns, 0, 0 },
- { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_ll_encode_fns, 0, 0 },
- { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_hl_encode_fns, 0, 0 },
- { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_lh_encode_fns, 0, 0 },
- { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
- 0,
- Opcode_muls_ad_hh_encode_fns, 0, 0 },
- { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_ll_encode_fns, 0, 0 },
- { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_hl_encode_fns, 0, 0 },
- { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_lh_encode_fns, 0, 0 },
- { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_mula_da_hh_encode_fns, 0, 0 },
- { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_ll_encode_fns, 0, 0 },
- { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_hl_encode_fns, 0, 0 },
- { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_lh_encode_fns, 0, 0 },
- { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
- 0,
- Opcode_muls_da_hh_encode_fns, 0, 0 },
- { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_ll_encode_fns, 0, 0 },
- { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_hl_encode_fns, 0, 0 },
- { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_lh_encode_fns, 0, 0 },
- { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_mula_dd_hh_encode_fns, 0, 0 },
- { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_ll_encode_fns, 0, 0 },
- { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_hl_encode_fns, 0, 0 },
- { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_lh_encode_fns, 0, 0 },
- { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
- 0,
- Opcode_muls_dd_hh_encode_fns, 0, 0 },
- { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
- { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
- { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
- { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
- { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
- { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
- { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
- { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
- 0,
- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
- { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
- { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
- { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
- { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
- { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
- 0,
- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
- { "lddec", ICLASS_xt_iclass_mac16_l,
- 0,
- Opcode_lddec_encode_fns, 0, 0 },
- { "ldinc", ICLASS_xt_iclass_mac16_l,
- 0,
- Opcode_ldinc_encode_fns, 0, 0 },
- { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
- 0,
- Opcode_rsr_m0_encode_fns, 0, 0 },
- { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
- 0,
- Opcode_wsr_m0_encode_fns, 0, 0 },
- { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
- 0,
- Opcode_xsr_m0_encode_fns, 0, 0 },
- { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
- 0,
- Opcode_rsr_m1_encode_fns, 0, 0 },
- { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
- 0,
- Opcode_wsr_m1_encode_fns, 0, 0 },
- { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
- 0,
- Opcode_xsr_m1_encode_fns, 0, 0 },
- { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
- 0,
- Opcode_rsr_m2_encode_fns, 0, 0 },
- { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
- 0,
- Opcode_wsr_m2_encode_fns, 0, 0 },
- { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
- 0,
- Opcode_xsr_m2_encode_fns, 0, 0 },
- { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
- 0,
- Opcode_rsr_m3_encode_fns, 0, 0 },
- { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
- 0,
- Opcode_wsr_m3_encode_fns, 0, 0 },
- { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
- 0,
- Opcode_xsr_m3_encode_fns, 0, 0 },
- { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
- 0,
- Opcode_rsr_acclo_encode_fns, 0, 0 },
- { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
- 0,
- Opcode_wsr_acclo_encode_fns, 0, 0 },
- { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
- 0,
- Opcode_xsr_acclo_encode_fns, 0, 0 },
- { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
- 0,
- Opcode_rsr_acchi_encode_fns, 0, 0 },
- { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
- 0,
- Opcode_wsr_acchi_encode_fns, 0, 0 },
- { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
- 0,
- Opcode_xsr_acchi_encode_fns, 0, 0 },
- { "rfi", ICLASS_xt_iclass_rfi,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", ICLASS_xt_iclass_wait,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", ICLASS_xt_iclass_break,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", ICLASS_xt_iclass_break_n,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
- 0,
- Opcode_lddr32_p_encode_fns, 0, 0 },
- { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
- 0,
- Opcode_sddr32_p_encode_fns, 0, 0 },
- { "rfdo", ICLASS_xt_iclass_rfdo,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", ICLASS_xt_iclass_rfdd,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
- 0,
- Opcode_wsr_mmid_encode_fns, 0, 0 },
- { "andb", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_andb_encode_fns, 0, 0 },
- { "andbc", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_andbc_encode_fns, 0, 0 },
- { "orb", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_orb_encode_fns, 0, 0 },
- { "orbc", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_orbc_encode_fns, 0, 0 },
- { "xorb", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_xorb_encode_fns, 0, 0 },
- { "any4", ICLASS_xt_iclass_bbool4,
- 0,
- Opcode_any4_encode_fns, 0, 0 },
- { "all4", ICLASS_xt_iclass_bbool4,
- 0,
- Opcode_all4_encode_fns, 0, 0 },
- { "any8", ICLASS_xt_iclass_bbool8,
- 0,
- Opcode_any8_encode_fns, 0, 0 },
- { "all8", ICLASS_xt_iclass_bbool8,
- 0,
- Opcode_all8_encode_fns, 0, 0 },
- { "bf", ICLASS_xt_iclass_bbranch,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bf_encode_fns, 0, 0 },
- { "bt", ICLASS_xt_iclass_bbranch,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bt_encode_fns, 0, 0 },
- { "movf", ICLASS_xt_iclass_bmove,
- 0,
- Opcode_movf_encode_fns, 0, 0 },
- { "movt", ICLASS_xt_iclass_bmove,
- 0,
- Opcode_movt_encode_fns, 0, 0 },
- { "rsr.br", ICLASS_xt_iclass_RSR_BR,
- 0,
- Opcode_rsr_br_encode_fns, 0, 0 },
- { "wsr.br", ICLASS_xt_iclass_WSR_BR,
- 0,
- Opcode_wsr_br_encode_fns, 0, 0 },
- { "xsr.br", ICLASS_xt_iclass_XSR_BR,
- 0,
- Opcode_xsr_br_encode_fns, 0, 0 },
- { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "ipf", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "ipfl", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_ipfl_encode_fns, 0, 0 },
- { "ihu", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_ihu_encode_fns, 0, 0 },
- { "iiu", ICLASS_xt_iclass_icache_lock,
- 0,
- Opcode_iiu_encode_fns, 0, 0 },
- { "iii", ICLASS_xt_iclass_icache_inv,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", ICLASS_xt_iclass_licx,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", ICLASS_xt_iclass_licx,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
- 0,
- Opcode_diwbui_p_encode_fns, 0, 0 },
- { "diwb", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "dpfl", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_dpfl_encode_fns, 0, 0 },
- { "dhu", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_dhu_encode_fns, 0, 0 },
- { "diu", ICLASS_xt_iclass_dcache_lock,
- 0,
- Opcode_diu_encode_fns, 0, 0 },
- { "sdct", ICLASS_xt_iclass_sdct,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", ICLASS_xt_iclass_ldct,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl,
- 0,
- Opcode_rsr_prefctl_encode_fns, 0, 0 },
- { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl,
- 0,
- Opcode_wsr_prefctl_encode_fns, 0, 0 },
- { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl,
- 0,
- Opcode_xsr_prefctl_encode_fns, 0, 0 },
- { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
- 0,
- Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
- 0,
- Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
- { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
- 0,
- Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
- 0,
- Opcode_rsr_rasid_encode_fns, 0, 0 },
- { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
- 0,
- Opcode_wsr_rasid_encode_fns, 0, 0 },
- { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
- 0,
- Opcode_xsr_rasid_encode_fns, 0, 0 },
- { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
- 0,
- Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
- { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
- 0,
- Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
- { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
- 0,
- Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
- { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
- 0,
- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
- { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
- 0,
- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
- { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
- 0,
- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
- { "idtlb", ICLASS_xt_iclass_idtlb,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", ICLASS_xt_iclass_wdtlb,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", ICLASS_xt_iclass_iitlb,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", ICLASS_xt_iclass_witlb,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "ldpte", ICLASS_xt_iclass_ldpte,
- 0,
- Opcode_ldpte_encode_fns, 0, 0 },
- { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_hwwitlba_encode_fns, 0, 0 },
- { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
- 0,
- Opcode_hwwdtlba_encode_fns, 0, 0 },
- { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
- 0,
- Opcode_rsr_cpenable_encode_fns, 0, 0 },
- { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
- 0,
- Opcode_wsr_cpenable_encode_fns, 0, 0 },
- { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
- 0,
- Opcode_xsr_cpenable_encode_fns, 0, 0 },
- { "clamps", ICLASS_xt_iclass_clamp,
- 0,
- Opcode_clamps_encode_fns, 0, 0 },
- { "min", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", ICLASS_xt_iclass_sx,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", ICLASS_xt_iclass_l32ai,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", ICLASS_xt_iclass_s32ri,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", ICLASS_xt_iclass_s32c1i,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
- 0,
- Opcode_rsr_atomctl_encode_fns, 0, 0 },
- { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
- 0,
- Opcode_wsr_atomctl_encode_fns, 0, 0 },
- { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
- 0,
- Opcode_xsr_atomctl_encode_fns, 0, 0 },
- { "quou", ICLASS_xt_iclass_div,
- 0,
- Opcode_quou_encode_fns, 0, 0 },
- { "quos", ICLASS_xt_iclass_div,
- 0,
- Opcode_quos_encode_fns, 0, 0 },
- { "remu", ICLASS_xt_iclass_div,
- 0,
- Opcode_remu_encode_fns, 0, 0 },
- { "rems", ICLASS_xt_iclass_div,
- 0,
- Opcode_rems_encode_fns, 0, 0 },
- { "rer", ICLASS_xt_iclass_rer,
- 0,
- Opcode_rer_encode_fns, 0, 0 },
- { "wer", ICLASS_xt_iclass_wer,
- 0,
- Opcode_wer_encode_fns, 0, 0 },
- { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
- 0,
- Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
- { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
- 0,
- Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
- { "rur.ae_bithead", ICLASS_rur_ae_bithead,
- 0,
- Opcode_rur_ae_bithead_encode_fns, 0, 0 },
- { "wur.ae_bithead", ICLASS_wur_ae_bithead,
- 0,
- Opcode_wur_ae_bithead_encode_fns, 0, 0 },
- { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
- 0,
- Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
- { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
- 0,
- Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
- { "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
- 0,
- Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
- { "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
- 0,
- Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
- { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
- 0,
- Opcode_rur_ae_overflow_encode_fns, 0, 0 },
- { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
- 0,
- Opcode_wur_ae_overflow_encode_fns, 0, 0 },
- { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
- 0,
- Opcode_rur_ae_sar_encode_fns, 0, 0 },
- { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
- 0,
- Opcode_wur_ae_sar_encode_fns, 0, 0 },
- { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
- 0,
- Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
- { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
- 0,
- Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
- { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
- 0,
- Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
- { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
- 0,
- Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
- { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
- 0,
- Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
- { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
- 0,
- Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
- { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
- 0,
- Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
- { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
- 0,
- Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
- { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
- 0,
- Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
- { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
- 0,
- Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
- { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
- 0,
- Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
- { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
- 0,
- Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
- { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
- 0,
- Opcode_ae_lp16f_i_encode_fns, 0, 0 },
- { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
- 0,
- Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
- { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
- 0,
- Opcode_ae_lp16f_x_encode_fns, 0, 0 },
- { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
- 0,
- Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
- { "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
- 0,
- Opcode_ae_lp24_i_encode_fns, 0, 0 },
- { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
- 0,
- Opcode_ae_lp24_iu_encode_fns, 0, 0 },
- { "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
- 0,
- Opcode_ae_lp24_x_encode_fns, 0, 0 },
- { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
- 0,
- Opcode_ae_lp24_xu_encode_fns, 0, 0 },
- { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
- 0,
- Opcode_ae_lp24f_i_encode_fns, 0, 0 },
- { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
- 0,
- Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
- { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
- 0,
- Opcode_ae_lp24f_x_encode_fns, 0, 0 },
- { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
- 0,
- Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
- { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
- 0,
- Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
- { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
- 0,
- Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
- { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
- 0,
- Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
- { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
- 0,
- Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
- { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
- 0,
- Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
- { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
- 0,
- Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
- { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
- 0,
- Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
- { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
- 0,
- Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
- { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
- 0,
- Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
- { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
- 0,
- Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
- { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
- 0,
- Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
- { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
- 0,
- Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
- { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
- 0,
- Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
- { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
- 0,
- Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
- { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
- 0,
- Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
- { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
- 0,
- Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
- { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
- 0,
- Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
- { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
- 0,
- Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
- { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
- 0,
- Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
- { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
- 0,
- Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
- { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
- 0,
- Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
- { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
- 0,
- Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
- { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
- 0,
- Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
- { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
- 0,
- Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
- { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
- 0,
- Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
- { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
- 0,
- Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
- { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
- 0,
- Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
- { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
- 0,
- Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
- { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
- 0,
- Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
- { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
- 0,
- Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
- { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
- 0,
- Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
- { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
- 0,
- Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
- { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
- 0,
- Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
- { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
- 0,
- Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
- { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
- 0,
- Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
- { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
- 0,
- Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
- { "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
- 0,
- Opcode_ae_lq56_i_encode_fns, 0, 0 },
- { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
- 0,
- Opcode_ae_lq56_iu_encode_fns, 0, 0 },
- { "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
- 0,
- Opcode_ae_lq56_x_encode_fns, 0, 0 },
- { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
- 0,
- Opcode_ae_lq56_xu_encode_fns, 0, 0 },
- { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
- 0,
- Opcode_ae_lq32f_i_encode_fns, 0, 0 },
- { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
- 0,
- Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
- { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
- 0,
- Opcode_ae_lq32f_x_encode_fns, 0, 0 },
- { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
- 0,
- Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
- { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
- 0,
- Opcode_ae_sq56s_i_encode_fns, 0, 0 },
- { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
- 0,
- Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
- { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
- 0,
- Opcode_ae_sq56s_x_encode_fns, 0, 0 },
- { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
- 0,
- Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
- { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
- 0,
- Opcode_ae_sq32f_i_encode_fns, 0, 0 },
- { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
- 0,
- Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
- { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
- 0,
- Opcode_ae_sq32f_x_encode_fns, 0, 0 },
- { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
- 0,
- Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
- { "ae_zerop48", ICLASS_ae_iclass_zerop48,
- 0,
- Opcode_ae_zerop48_encode_fns, 0, 0 },
- { "ae_movp48", ICLASS_ae_iclass_movp48,
- 0,
- Opcode_ae_movp48_encode_fns, 0, 0 },
- { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
- 0,
- Opcode_ae_selp24_ll_encode_fns, 0, 0 },
- { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
- 0,
- Opcode_ae_selp24_lh_encode_fns, 0, 0 },
- { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
- 0,
- Opcode_ae_selp24_hl_encode_fns, 0, 0 },
- { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
- 0,
- Opcode_ae_selp24_hh_encode_fns, 0, 0 },
- { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
- 0,
- Opcode_ae_movtp24x2_encode_fns, 0, 0 },
- { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
- 0,
- Opcode_ae_movfp24x2_encode_fns, 0, 0 },
- { "ae_movtp48", ICLASS_ae_iclass_movtp48,
- 0,
- Opcode_ae_movtp48_encode_fns, 0, 0 },
- { "ae_movfp48", ICLASS_ae_iclass_movfp48,
- 0,
- Opcode_ae_movfp48_encode_fns, 0, 0 },
- { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
- 0,
- Opcode_ae_movpa24x2_encode_fns, 0, 0 },
- { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
- 0,
- Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
- { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
- 0,
- Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
- { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
- 0,
- Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
- 0,
- Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
- 0,
- Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
- 0,
- Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
- 0,
- Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
- { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
- 0,
- Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
- { "ae_truncp16", ICLASS_ae_iclass_truncp16,
- 0,
- Opcode_ae_truncp16_encode_fns, 0, 0 },
- { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
- 0,
- Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
- { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
- 0,
- Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
- { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
- 0,
- Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
- { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
- 0,
- Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
- { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
- 0,
- Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
- { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
- 0,
- Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
- { "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
- 0,
- Opcode_ae_zeroq56_encode_fns, 0, 0 },
- { "ae_movq56", ICLASS_ae_iclass_movq56,
- 0,
- Opcode_ae_movq56_encode_fns, 0, 0 },
- { "ae_movtq56", ICLASS_ae_iclass_movtq56,
- 0,
- Opcode_ae_movtq56_encode_fns, 0, 0 },
- { "ae_movfq56", ICLASS_ae_iclass_movfq56,
- 0,
- Opcode_ae_movfq56_encode_fns, 0, 0 },
- { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
- 0,
- Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
- { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
- 0,
- Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
- { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
- 0,
- Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
- { "ae_satq48s", ICLASS_ae_iclass_satq48s,
- 0,
- Opcode_ae_satq48s_encode_fns, 0, 0 },
- { "ae_truncq32", ICLASS_ae_iclass_truncq32,
- 0,
- Opcode_ae_truncq32_encode_fns, 0, 0 },
- { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
- 0,
- Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
- { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
- 0,
- Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
- { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
- 0,
- Opcode_ae_trunca32q48_encode_fns, 0, 0 },
- { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
- 0,
- Opcode_ae_movap24s_l_encode_fns, 0, 0 },
- { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
- 0,
- Opcode_ae_movap24s_h_encode_fns, 0, 0 },
- { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
- 0,
- Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
- { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
- 0,
- Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
- { "ae_addp24", ICLASS_ae_iclass_addp24,
- 0,
- Opcode_ae_addp24_encode_fns, 0, 0 },
- { "ae_subp24", ICLASS_ae_iclass_subp24,
- 0,
- Opcode_ae_subp24_encode_fns, 0, 0 },
- { "ae_negp24", ICLASS_ae_iclass_negp24,
- 0,
- Opcode_ae_negp24_encode_fns, 0, 0 },
- { "ae_absp24", ICLASS_ae_iclass_absp24,
- 0,
- Opcode_ae_absp24_encode_fns, 0, 0 },
- { "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
- 0,
- Opcode_ae_maxp24s_encode_fns, 0, 0 },
- { "ae_minp24s", ICLASS_ae_iclass_minp24s,
- 0,
- Opcode_ae_minp24s_encode_fns, 0, 0 },
- { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
- 0,
- Opcode_ae_maxbp24s_encode_fns, 0, 0 },
- { "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
- 0,
- Opcode_ae_minbp24s_encode_fns, 0, 0 },
- { "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
- 0,
- Opcode_ae_addsp24s_encode_fns, 0, 0 },
- { "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
- 0,
- Opcode_ae_subsp24s_encode_fns, 0, 0 },
- { "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
- 0,
- Opcode_ae_negsp24s_encode_fns, 0, 0 },
- { "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
- 0,
- Opcode_ae_abssp24s_encode_fns, 0, 0 },
- { "ae_andp48", ICLASS_ae_iclass_andp48,
- 0,
- Opcode_ae_andp48_encode_fns, 0, 0 },
- { "ae_nandp48", ICLASS_ae_iclass_nandp48,
- 0,
- Opcode_ae_nandp48_encode_fns, 0, 0 },
- { "ae_orp48", ICLASS_ae_iclass_orp48,
- 0,
- Opcode_ae_orp48_encode_fns, 0, 0 },
- { "ae_xorp48", ICLASS_ae_iclass_xorp48,
- 0,
- Opcode_ae_xorp48_encode_fns, 0, 0 },
- { "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
- 0,
- Opcode_ae_ltp24s_encode_fns, 0, 0 },
- { "ae_lep24s", ICLASS_ae_iclass_lep24s,
- 0,
- Opcode_ae_lep24s_encode_fns, 0, 0 },
- { "ae_eqp24", ICLASS_ae_iclass_eqp24,
- 0,
- Opcode_ae_eqp24_encode_fns, 0, 0 },
- { "ae_addq56", ICLASS_ae_iclass_addq56,
- 0,
- Opcode_ae_addq56_encode_fns, 0, 0 },
- { "ae_subq56", ICLASS_ae_iclass_subq56,
- 0,
- Opcode_ae_subq56_encode_fns, 0, 0 },
- { "ae_negq56", ICLASS_ae_iclass_negq56,
- 0,
- Opcode_ae_negq56_encode_fns, 0, 0 },
- { "ae_absq56", ICLASS_ae_iclass_absq56,
- 0,
- Opcode_ae_absq56_encode_fns, 0, 0 },
- { "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
- 0,
- Opcode_ae_maxq56s_encode_fns, 0, 0 },
- { "ae_minq56s", ICLASS_ae_iclass_minq56s,
- 0,
- Opcode_ae_minq56s_encode_fns, 0, 0 },
- { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
- 0,
- Opcode_ae_maxbq56s_encode_fns, 0, 0 },
- { "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
- 0,
- Opcode_ae_minbq56s_encode_fns, 0, 0 },
- { "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
- 0,
- Opcode_ae_addsq56s_encode_fns, 0, 0 },
- { "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
- 0,
- Opcode_ae_subsq56s_encode_fns, 0, 0 },
- { "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
- 0,
- Opcode_ae_negsq56s_encode_fns, 0, 0 },
- { "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
- 0,
- Opcode_ae_abssq56s_encode_fns, 0, 0 },
- { "ae_andq56", ICLASS_ae_iclass_andq56,
- 0,
- Opcode_ae_andq56_encode_fns, 0, 0 },
- { "ae_nandq56", ICLASS_ae_iclass_nandq56,
- 0,
- Opcode_ae_nandq56_encode_fns, 0, 0 },
- { "ae_orq56", ICLASS_ae_iclass_orq56,
- 0,
- Opcode_ae_orq56_encode_fns, 0, 0 },
- { "ae_xorq56", ICLASS_ae_iclass_xorq56,
- 0,
- Opcode_ae_xorq56_encode_fns, 0, 0 },
- { "ae_sllip24", ICLASS_ae_iclass_sllip24,
- 0,
- Opcode_ae_sllip24_encode_fns, 0, 0 },
- { "ae_srlip24", ICLASS_ae_iclass_srlip24,
- 0,
- Opcode_ae_srlip24_encode_fns, 0, 0 },
- { "ae_sraip24", ICLASS_ae_iclass_sraip24,
- 0,
- Opcode_ae_sraip24_encode_fns, 0, 0 },
- { "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
- 0,
- Opcode_ae_sllsp24_encode_fns, 0, 0 },
- { "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
- 0,
- Opcode_ae_srlsp24_encode_fns, 0, 0 },
- { "ae_srasp24", ICLASS_ae_iclass_srasp24,
- 0,
- Opcode_ae_srasp24_encode_fns, 0, 0 },
- { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
- 0,
- Opcode_ae_sllisp24s_encode_fns, 0, 0 },
- { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
- 0,
- Opcode_ae_sllssp24s_encode_fns, 0, 0 },
- { "ae_slliq56", ICLASS_ae_iclass_slliq56,
- 0,
- Opcode_ae_slliq56_encode_fns, 0, 0 },
- { "ae_srliq56", ICLASS_ae_iclass_srliq56,
- 0,
- Opcode_ae_srliq56_encode_fns, 0, 0 },
- { "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
- 0,
- Opcode_ae_sraiq56_encode_fns, 0, 0 },
- { "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
- 0,
- Opcode_ae_sllsq56_encode_fns, 0, 0 },
- { "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
- 0,
- Opcode_ae_srlsq56_encode_fns, 0, 0 },
- { "ae_srasq56", ICLASS_ae_iclass_srasq56,
- 0,
- Opcode_ae_srasq56_encode_fns, 0, 0 },
- { "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
- 0,
- Opcode_ae_sllaq56_encode_fns, 0, 0 },
- { "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
- 0,
- Opcode_ae_srlaq56_encode_fns, 0, 0 },
- { "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
- 0,
- Opcode_ae_sraaq56_encode_fns, 0, 0 },
- { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
- 0,
- Opcode_ae_sllisq56s_encode_fns, 0, 0 },
- { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
- 0,
- Opcode_ae_sllssq56s_encode_fns, 0, 0 },
- { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
- 0,
- Opcode_ae_sllasq56s_encode_fns, 0, 0 },
- { "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
- 0,
- Opcode_ae_ltq56s_encode_fns, 0, 0 },
- { "ae_leq56s", ICLASS_ae_iclass_leq56s,
- 0,
- Opcode_ae_leq56s_encode_fns, 0, 0 },
- { "ae_eqq56", ICLASS_ae_iclass_eqq56,
- 0,
- Opcode_ae_eqq56_encode_fns, 0, 0 },
- { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
- 0,
- Opcode_ae_nsaq56s_encode_fns, 0, 0 },
- { "ae_mulsrfq32sp24s.h", ICLASS_ae_iclass_mulsrfq32sp24s_h,
- 0,
- Opcode_ae_mulsrfq32sp24s_h_encode_fns, 0, 0 },
- { "ae_mulsrfq32sp24s.l", ICLASS_ae_iclass_mulsrfq32sp24s_l,
- 0,
- Opcode_ae_mulsrfq32sp24s_l_encode_fns, 0, 0 },
- { "ae_mularfq32sp24s.h", ICLASS_ae_iclass_mularfq32sp24s_h,
- 0,
- Opcode_ae_mularfq32sp24s_h_encode_fns, 0, 0 },
- { "ae_mularfq32sp24s.l", ICLASS_ae_iclass_mularfq32sp24s_l,
- 0,
- Opcode_ae_mularfq32sp24s_l_encode_fns, 0, 0 },
- { "ae_mulrfq32sp24s.h", ICLASS_ae_iclass_mulrfq32sp24s_h,
- 0,
- Opcode_ae_mulrfq32sp24s_h_encode_fns, 0, 0 },
- { "ae_mulrfq32sp24s.l", ICLASS_ae_iclass_mulrfq32sp24s_l,
- 0,
- Opcode_ae_mulrfq32sp24s_l_encode_fns, 0, 0 },
- { "ae_mulsfq32sp24s.h", ICLASS_ae_iclass_mulsfq32sp24s_h,
- 0,
- Opcode_ae_mulsfq32sp24s_h_encode_fns, 0, 0 },
- { "ae_mulsfq32sp24s.l", ICLASS_ae_iclass_mulsfq32sp24s_l,
- 0,
- Opcode_ae_mulsfq32sp24s_l_encode_fns, 0, 0 },
- { "ae_mulafq32sp24s.h", ICLASS_ae_iclass_mulafq32sp24s_h,
- 0,
- Opcode_ae_mulafq32sp24s_h_encode_fns, 0, 0 },
- { "ae_mulafq32sp24s.l", ICLASS_ae_iclass_mulafq32sp24s_l,
- 0,
- Opcode_ae_mulafq32sp24s_l_encode_fns, 0, 0 },
- { "ae_mulfq32sp24s.h", ICLASS_ae_iclass_mulfq32sp24s_h,
- 0,
- Opcode_ae_mulfq32sp24s_h_encode_fns, 0, 0 },
- { "ae_mulfq32sp24s.l", ICLASS_ae_iclass_mulfq32sp24s_l,
- 0,
- Opcode_ae_mulfq32sp24s_l_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
- 0,
- Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
- { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
- 0,
- Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
- { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
- 0,
- Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
- 0,
- Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
- { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
- 0,
- Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
- { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
- 0,
- Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
- 0,
- Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
- { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
- 0,
- Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
- { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
- 0,
- Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
- 0,
- Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
- { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
- 0,
- Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
- { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
- 0,
- Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
- 0,
- Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
- { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
- 0,
- Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
- { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
- 0,
- Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
- 0,
- Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
- { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
- 0,
- Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
- { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
- 0,
- Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
- 0,
- Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
- { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
- 0,
- Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
- { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
- 0,
- Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
- 0,
- Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
- { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
- 0,
- Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
- { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
- 0,
- Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
- 0,
- Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
- { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
- 0,
- Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
- { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
- 0,
- Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
- 0,
- Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
- { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
- 0,
- Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
- { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
- 0,
- Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
- 0,
- Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
- { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
- 0,
- Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
- { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
- 0,
- Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
- 0,
- Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
- { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
- 0,
- Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
- { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
- 0,
- Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
- 0,
- Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
- 0,
- Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
- 0,
- Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
- 0,
- Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
- 0,
- Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
- 0,
- Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
- 0,
- Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
- 0,
- Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
- 0,
- Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
- 0,
- Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
- 0,
- Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
- 0,
- Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
- 0,
- Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
- 0,
- Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
- 0,
- Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
- 0,
- Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
- 0,
- Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
- 0,
- Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
- 0,
- Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
- 0,
- Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
- 0,
- Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
- 0,
- Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
- 0,
- Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
- 0,
- Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
- 0,
- Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
- 0,
- Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
- 0,
- Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
- 0,
- Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
- 0,
- Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
- 0,
- Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
- 0,
- Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
- 0,
- Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
- 0,
- Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
- 0,
- Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
- 0,
- Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
- 0,
- Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
- 0,
- Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
- 0,
- Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
- 0,
- Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
- 0,
- Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
- 0,
- Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
- 0,
- Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
- 0,
- Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
- 0,
- Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
- 0,
- Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
- 0,
- Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
- 0,
- Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
- 0,
- Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
- 0,
- Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
- 0,
- Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
- 0,
- Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
- 0,
- Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
- 0,
- Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
- 0,
- Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
- 0,
- Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
- 0,
- Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
- 0,
- Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
- 0,
- Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
- 0,
- Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
- 0,
- Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
- 0,
- Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
- 0,
- Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
- 0,
- Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
- 0,
- Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
- 0,
- Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
- 0,
- Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
- 0,
- Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
- 0,
- Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
- 0,
- Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
- 0,
- Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
- 0,
- Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
- 0,
- Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
- 0,
- Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
- 0,
- Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
- 0,
- Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
- 0,
- Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
- 0,
- Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
- 0,
- Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
- 0,
- Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
- 0,
- Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
- 0,
- Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
- 0,
- Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
- 0,
- Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
- 0,
- Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
- 0,
- Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
- 0,
- Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
- 0,
- Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
- 0,
- Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
- 0,
- Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
- 0,
- Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
- 0,
- Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
- 0,
- Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
- 0,
- Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
- 0,
- Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
- 0,
- Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
- 0,
- Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
- 0,
- Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
- 0,
- Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
- 0,
- Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
- 0,
- Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
- 0,
- Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
- 0,
- Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
- 0,
- Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
- 0,
- Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
- 0,
- Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
- 0,
- Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
- 0,
- Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
- 0,
- Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
- 0,
- Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
- 0,
- Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
- 0,
- Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
- 0,
- Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
- 0,
- Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
- 0,
- Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
- 0,
- Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
- 0,
- Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
- 0,
- Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
- 0,
- Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
- 0,
- Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
- 0,
- Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_sha32", ICLASS_ae_iclass_sha32,
- 0,
- Opcode_ae_sha32_encode_fns, 0, 0 },
- { "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
- 0,
- Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
- { "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
- 0,
- Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
- { "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
- 0,
- Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
- { "ae_vldsht", ICLASS_ae_iclass_vldsht,
- 0,
- Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
- { "ae_lb", ICLASS_ae_iclass_lb,
- 0,
- Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
- { "ae_lbi", ICLASS_ae_iclass_lbi,
- 0,
- Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
- { "ae_lbk", ICLASS_ae_iclass_lbk,
- 0,
- Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
- { "ae_lbki", ICLASS_ae_iclass_lbki,
- 0,
- Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
- { "ae_db", ICLASS_ae_iclass_db,
- 0,
- Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
- { "ae_dbi", ICLASS_ae_iclass_dbi,
- 0,
- Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
- { "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
- 0,
- Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
- { "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
- 0,
- Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
- { "ae_sb", ICLASS_ae_iclass_sb,
- 0,
- Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
- { "ae_sbi", ICLASS_ae_iclass_sbi,
- 0,
- Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
- { "ae_vles16c", ICLASS_ae_iclass_vles16c,
- 0,
- Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
- { "ae_sbf", ICLASS_ae_iclass_sbf,
- 0,
- Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses },
- { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S,
- 0,
- Opcode_ae_slaasq56s_encode_fns, 0, 0 },
- { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32,
- 0,
- Opcode_ae_addbrba32_encode_fns, 0, 0 },
- { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S,
- 0,
- Opcode_ae_minabssp24s_encode_fns, 0, 0 },
- { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S,
- 0,
- Opcode_ae_maxabssp24s_encode_fns, 0, 0 },
- { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S,
- 0,
- Opcode_ae_minabssq56s_encode_fns, 0, 0 },
- { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S,
- 0,
- Opcode_ae_maxabssq56s_encode_fns, 0, 0 },
- { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0,
- 0,
- Opcode_rur_ae_cbegin0_encode_fns, 0, 0 },
- { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0,
- 0,
- Opcode_wur_ae_cbegin0_encode_fns, 0, 0 },
- { "rur.ae_cend0", ICLASS_rur_ae_cend0,
- 0,
- Opcode_rur_ae_cend0_encode_fns, 0, 0 },
- { "wur.ae_cend0", ICLASS_wur_ae_cend0,
- 0,
- Opcode_wur_ae_cend0_encode_fns, 0, 0 },
- { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C,
- 0,
- Opcode_ae_lp24x2_c_encode_fns, 0, 0 },
- { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C,
- 0,
- Opcode_ae_sp24x2s_c_encode_fns, 0, 0 },
- { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C,
- 0,
- Opcode_ae_lp24x2f_c_encode_fns, 0, 0 },
- { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C,
- 0,
- Opcode_ae_sp24x2f_c_encode_fns, 0, 0 },
- { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C,
- 0,
- Opcode_ae_lp16x2f_c_encode_fns, 0, 0 },
- { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C,
- 0,
- Opcode_ae_sp16x2f_c_encode_fns, 0, 0 },
- { "ae_lp24.c", ICLASS_icls_AE_LP24_C,
- 0,
- Opcode_ae_lp24_c_encode_fns, 0, 0 },
- { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C,
- 0,
- Opcode_ae_sp24s_l_c_encode_fns, 0, 0 },
- { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C,
- 0,
- Opcode_ae_lp24f_c_encode_fns, 0, 0 },
- { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C,
- 0,
- Opcode_ae_sp24f_l_c_encode_fns, 0, 0 },
- { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C,
- 0,
- Opcode_ae_lp16f_c_encode_fns, 0, 0 },
- { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C,
- 0,
- Opcode_ae_sp16f_l_c_encode_fns, 0, 0 },
- { "ae_lq56.c", ICLASS_icls_AE_LQ56_C,
- 0,
- Opcode_ae_lq56_c_encode_fns, 0, 0 },
- { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C,
- 0,
- Opcode_ae_sq56s_c_encode_fns, 0, 0 },
- { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C,
- 0,
- Opcode_ae_lq32f_c_encode_fns, 0, 0 },
- { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C,
- 0,
- Opcode_ae_sq32f_c_encode_fns, 0, 0 },
- { "rur.expstate", ICLASS_rur_expstate,
- 0,
- Opcode_rur_expstate_encode_fns, 0, 0 },
- { "wur.expstate", ICLASS_wur_expstate,
- 0,
- Opcode_wur_expstate_encode_fns, 0, 0 },
- { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
- 0,
- Opcode_read_impwire_encode_fns, 0, 0 },
- { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
- 0,
- Opcode_setb_expstate_encode_fns, 0, 0 },
- { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
- 0,
- Opcode_clrb_expstate_encode_fns, 0, 0 },
- { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
- 0,
- Opcode_wrmsk_expstate_encode_fns, 0, 0 }
-};
-
-enum xtensa_opcode_id {
- OPCODE_EXCW,
- OPCODE_RFE,
- OPCODE_RFDE,
- OPCODE_SYSCALL,
- OPCODE_CALL12,
- OPCODE_CALL8,
- OPCODE_CALL4,
- OPCODE_CALLX12,
- OPCODE_CALLX8,
- OPCODE_CALLX4,
- OPCODE_ENTRY,
- OPCODE_MOVSP,
- OPCODE_ROTW,
- OPCODE_RETW,
- OPCODE_RETW_N,
- OPCODE_RFWO,
- OPCODE_RFWU,
- OPCODE_L32E,
- OPCODE_S32E,
- OPCODE_RSR_WINDOWBASE,
- OPCODE_WSR_WINDOWBASE,
- OPCODE_XSR_WINDOWBASE,
- OPCODE_RSR_WINDOWSTART,
- OPCODE_WSR_WINDOWSTART,
- OPCODE_XSR_WINDOWSTART,
- OPCODE_ADD_N,
- OPCODE_ADDI_N,
- OPCODE_BEQZ_N,
- OPCODE_BNEZ_N,
- OPCODE_ILL_N,
- OPCODE_L32I_N,
- OPCODE_MOV_N,
- OPCODE_MOVI_N,
- OPCODE_NOP_N,
- OPCODE_RET_N,
- OPCODE_S32I_N,
- OPCODE_RUR_THREADPTR,
- OPCODE_WUR_THREADPTR,
- OPCODE_ADDI,
- OPCODE_ADDMI,
- OPCODE_ADD,
- OPCODE_SUB,
- OPCODE_ADDX2,
- OPCODE_ADDX4,
- OPCODE_ADDX8,
- OPCODE_SUBX2,
- OPCODE_SUBX4,
- OPCODE_SUBX8,
- OPCODE_AND,
- OPCODE_OR,
- OPCODE_XOR,
- OPCODE_BEQI,
- OPCODE_BNEI,
- OPCODE_BGEI,
- OPCODE_BLTI,
- OPCODE_BBCI,
- OPCODE_BBSI,
- OPCODE_BGEUI,
- OPCODE_BLTUI,
- OPCODE_BEQ,
- OPCODE_BNE,
- OPCODE_BGE,
- OPCODE_BLT,
- OPCODE_BGEU,
- OPCODE_BLTU,
- OPCODE_BANY,
- OPCODE_BNONE,
- OPCODE_BALL,
- OPCODE_BNALL,
- OPCODE_BBC,
- OPCODE_BBS,
- OPCODE_BEQZ,
- OPCODE_BNEZ,
- OPCODE_BGEZ,
- OPCODE_BLTZ,
- OPCODE_CALL0,
- OPCODE_CALLX0,
- OPCODE_EXTUI,
- OPCODE_ILL,
- OPCODE_J,
- OPCODE_JX,
- OPCODE_L16UI,
- OPCODE_L16SI,
- OPCODE_L32I,
- OPCODE_L32R,
- OPCODE_L8UI,
- OPCODE_LOOP,
- OPCODE_LOOPNEZ,
- OPCODE_LOOPGTZ,
- OPCODE_MOVI,
- OPCODE_MOVEQZ,
- OPCODE_MOVNEZ,
- OPCODE_MOVLTZ,
- OPCODE_MOVGEZ,
- OPCODE_NEG,
- OPCODE_ABS,
- OPCODE_NOP,
- OPCODE_RET,
- OPCODE_SIMCALL,
- OPCODE_S16I,
- OPCODE_S32I,
- OPCODE_S32NB,
- OPCODE_S8I,
- OPCODE_SSR,
- OPCODE_SSL,
- OPCODE_SSA8L,
- OPCODE_SSA8B,
- OPCODE_SSAI,
- OPCODE_SLL,
- OPCODE_SRC,
- OPCODE_SRL,
- OPCODE_SRA,
- OPCODE_SLLI,
- OPCODE_SRAI,
- OPCODE_SRLI,
- OPCODE_MEMW,
- OPCODE_EXTW,
- OPCODE_ISYNC,
- OPCODE_RSYNC,
- OPCODE_ESYNC,
- OPCODE_DSYNC,
- OPCODE_RSIL,
- OPCODE_RSR_LEND,
- OPCODE_WSR_LEND,
- OPCODE_XSR_LEND,
- OPCODE_RSR_LCOUNT,
- OPCODE_WSR_LCOUNT,
- OPCODE_XSR_LCOUNT,
- OPCODE_RSR_LBEG,
- OPCODE_WSR_LBEG,
- OPCODE_XSR_LBEG,
- OPCODE_RSR_SAR,
- OPCODE_WSR_SAR,
- OPCODE_XSR_SAR,
- OPCODE_RSR_MEMCTL,
- OPCODE_WSR_MEMCTL,
- OPCODE_XSR_MEMCTL,
- OPCODE_RSR_LITBASE,
- OPCODE_WSR_LITBASE,
- OPCODE_XSR_LITBASE,
- OPCODE_RSR_CONFIGID0,
- OPCODE_WSR_CONFIGID0,
- OPCODE_RSR_CONFIGID1,
- OPCODE_RSR_243,
- OPCODE_RSR_PS,
- OPCODE_WSR_PS,
- OPCODE_XSR_PS,
- OPCODE_RSR_EPC1,
- OPCODE_WSR_EPC1,
- OPCODE_XSR_EPC1,
- OPCODE_RSR_EXCSAVE1,
- OPCODE_WSR_EXCSAVE1,
- OPCODE_XSR_EXCSAVE1,
- OPCODE_RSR_EPC2,
- OPCODE_WSR_EPC2,
- OPCODE_XSR_EPC2,
- OPCODE_RSR_EXCSAVE2,
- OPCODE_WSR_EXCSAVE2,
- OPCODE_XSR_EXCSAVE2,
- OPCODE_RSR_EPC3,
- OPCODE_WSR_EPC3,
- OPCODE_XSR_EPC3,
- OPCODE_RSR_EXCSAVE3,
- OPCODE_WSR_EXCSAVE3,
- OPCODE_XSR_EXCSAVE3,
- OPCODE_RSR_EPC4,
- OPCODE_WSR_EPC4,
- OPCODE_XSR_EPC4,
- OPCODE_RSR_EXCSAVE4,
- OPCODE_WSR_EXCSAVE4,
- OPCODE_XSR_EXCSAVE4,
- OPCODE_RSR_EPC5,
- OPCODE_WSR_EPC5,
- OPCODE_XSR_EPC5,
- OPCODE_RSR_EXCSAVE5,
- OPCODE_WSR_EXCSAVE5,
- OPCODE_XSR_EXCSAVE5,
- OPCODE_RSR_EPC6,
- OPCODE_WSR_EPC6,
- OPCODE_XSR_EPC6,
- OPCODE_RSR_EXCSAVE6,
- OPCODE_WSR_EXCSAVE6,
- OPCODE_XSR_EXCSAVE6,
- OPCODE_RSR_EPC7,
- OPCODE_WSR_EPC7,
- OPCODE_XSR_EPC7,
- OPCODE_RSR_EXCSAVE7,
- OPCODE_WSR_EXCSAVE7,
- OPCODE_XSR_EXCSAVE7,
- OPCODE_RSR_EPS2,
- OPCODE_WSR_EPS2,
- OPCODE_XSR_EPS2,
- OPCODE_RSR_EPS3,
- OPCODE_WSR_EPS3,
- OPCODE_XSR_EPS3,
- OPCODE_RSR_EPS4,
- OPCODE_WSR_EPS4,
- OPCODE_XSR_EPS4,
- OPCODE_RSR_EPS5,
- OPCODE_WSR_EPS5,
- OPCODE_XSR_EPS5,
- OPCODE_RSR_EPS6,
- OPCODE_WSR_EPS6,
- OPCODE_XSR_EPS6,
- OPCODE_RSR_EPS7,
- OPCODE_WSR_EPS7,
- OPCODE_XSR_EPS7,
- OPCODE_RSR_EXCVADDR,
- OPCODE_WSR_EXCVADDR,
- OPCODE_XSR_EXCVADDR,
- OPCODE_RSR_DEPC,
- OPCODE_WSR_DEPC,
- OPCODE_XSR_DEPC,
- OPCODE_RSR_EXCCAUSE,
- OPCODE_WSR_EXCCAUSE,
- OPCODE_XSR_EXCCAUSE,
- OPCODE_RSR_MISC0,
- OPCODE_WSR_MISC0,
- OPCODE_XSR_MISC0,
- OPCODE_RSR_MISC1,
- OPCODE_WSR_MISC1,
- OPCODE_XSR_MISC1,
- OPCODE_RSR_PRID,
- OPCODE_RSR_VECBASE,
- OPCODE_WSR_VECBASE,
- OPCODE_XSR_VECBASE,
- OPCODE_MUL16U,
- OPCODE_MUL16S,
- OPCODE_MULL,
- OPCODE_MULUH,
- OPCODE_MULSH,
- OPCODE_MUL_AA_LL,
- OPCODE_MUL_AA_HL,
- OPCODE_MUL_AA_LH,
- OPCODE_MUL_AA_HH,
- OPCODE_UMUL_AA_LL,
- OPCODE_UMUL_AA_HL,
- OPCODE_UMUL_AA_LH,
- OPCODE_UMUL_AA_HH,
- OPCODE_MUL_AD_LL,
- OPCODE_MUL_AD_HL,
- OPCODE_MUL_AD_LH,
- OPCODE_MUL_AD_HH,
- OPCODE_MUL_DA_LL,
- OPCODE_MUL_DA_HL,
- OPCODE_MUL_DA_LH,
- OPCODE_MUL_DA_HH,
- OPCODE_MUL_DD_LL,
- OPCODE_MUL_DD_HL,
- OPCODE_MUL_DD_LH,
- OPCODE_MUL_DD_HH,
- OPCODE_MULA_AA_LL,
- OPCODE_MULA_AA_HL,
- OPCODE_MULA_AA_LH,
- OPCODE_MULA_AA_HH,
- OPCODE_MULS_AA_LL,
- OPCODE_MULS_AA_HL,
- OPCODE_MULS_AA_LH,
- OPCODE_MULS_AA_HH,
- OPCODE_MULA_AD_LL,
- OPCODE_MULA_AD_HL,
- OPCODE_MULA_AD_LH,
- OPCODE_MULA_AD_HH,
- OPCODE_MULS_AD_LL,
- OPCODE_MULS_AD_HL,
- OPCODE_MULS_AD_LH,
- OPCODE_MULS_AD_HH,
- OPCODE_MULA_DA_LL,
- OPCODE_MULA_DA_HL,
- OPCODE_MULA_DA_LH,
- OPCODE_MULA_DA_HH,
- OPCODE_MULS_DA_LL,
- OPCODE_MULS_DA_HL,
- OPCODE_MULS_DA_LH,
- OPCODE_MULS_DA_HH,
- OPCODE_MULA_DD_LL,
- OPCODE_MULA_DD_HL,
- OPCODE_MULA_DD_LH,
- OPCODE_MULA_DD_HH,
- OPCODE_MULS_DD_LL,
- OPCODE_MULS_DD_HL,
- OPCODE_MULS_DD_LH,
- OPCODE_MULS_DD_HH,
- OPCODE_MULA_DA_LL_LDDEC,
- OPCODE_MULA_DA_LL_LDINC,
- OPCODE_MULA_DA_HL_LDDEC,
- OPCODE_MULA_DA_HL_LDINC,
- OPCODE_MULA_DA_LH_LDDEC,
- OPCODE_MULA_DA_LH_LDINC,
- OPCODE_MULA_DA_HH_LDDEC,
- OPCODE_MULA_DA_HH_LDINC,
- OPCODE_MULA_DD_LL_LDDEC,
- OPCODE_MULA_DD_LL_LDINC,
- OPCODE_MULA_DD_HL_LDDEC,
- OPCODE_MULA_DD_HL_LDINC,
- OPCODE_MULA_DD_LH_LDDEC,
- OPCODE_MULA_DD_LH_LDINC,
- OPCODE_MULA_DD_HH_LDDEC,
- OPCODE_MULA_DD_HH_LDINC,
- OPCODE_LDDEC,
- OPCODE_LDINC,
- OPCODE_RSR_M0,
- OPCODE_WSR_M0,
- OPCODE_XSR_M0,
- OPCODE_RSR_M1,
- OPCODE_WSR_M1,
- OPCODE_XSR_M1,
- OPCODE_RSR_M2,
- OPCODE_WSR_M2,
- OPCODE_XSR_M2,
- OPCODE_RSR_M3,
- OPCODE_WSR_M3,
- OPCODE_XSR_M3,
- OPCODE_RSR_ACCLO,
- OPCODE_WSR_ACCLO,
- OPCODE_XSR_ACCLO,
- OPCODE_RSR_ACCHI,
- OPCODE_WSR_ACCHI,
- OPCODE_XSR_ACCHI,
- OPCODE_RFI,
- OPCODE_WAITI,
- OPCODE_RSR_INTERRUPT,
- OPCODE_WSR_INTSET,
- OPCODE_WSR_INTCLEAR,
- OPCODE_RSR_INTENABLE,
- OPCODE_WSR_INTENABLE,
- OPCODE_XSR_INTENABLE,
- OPCODE_BREAK,
- OPCODE_BREAK_N,
- OPCODE_RSR_DBREAKA0,
- OPCODE_WSR_DBREAKA0,
- OPCODE_XSR_DBREAKA0,
- OPCODE_RSR_DBREAKC0,
- OPCODE_WSR_DBREAKC0,
- OPCODE_XSR_DBREAKC0,
- OPCODE_RSR_DBREAKA1,
- OPCODE_WSR_DBREAKA1,
- OPCODE_XSR_DBREAKA1,
- OPCODE_RSR_DBREAKC1,
- OPCODE_WSR_DBREAKC1,
- OPCODE_XSR_DBREAKC1,
- OPCODE_RSR_IBREAKA0,
- OPCODE_WSR_IBREAKA0,
- OPCODE_XSR_IBREAKA0,
- OPCODE_RSR_IBREAKA1,
- OPCODE_WSR_IBREAKA1,
- OPCODE_XSR_IBREAKA1,
- OPCODE_RSR_IBREAKENABLE,
- OPCODE_WSR_IBREAKENABLE,
- OPCODE_XSR_IBREAKENABLE,
- OPCODE_RSR_DEBUGCAUSE,
- OPCODE_WSR_DEBUGCAUSE,
- OPCODE_XSR_DEBUGCAUSE,
- OPCODE_RSR_ICOUNT,
- OPCODE_WSR_ICOUNT,
- OPCODE_XSR_ICOUNT,
- OPCODE_RSR_ICOUNTLEVEL,
- OPCODE_WSR_ICOUNTLEVEL,
- OPCODE_XSR_ICOUNTLEVEL,
- OPCODE_RSR_DDR,
- OPCODE_WSR_DDR,
- OPCODE_XSR_DDR,
- OPCODE_LDDR32_P,
- OPCODE_SDDR32_P,
- OPCODE_RFDO,
- OPCODE_RFDD,
- OPCODE_WSR_MMID,
- OPCODE_ANDB,
- OPCODE_ANDBC,
- OPCODE_ORB,
- OPCODE_ORBC,
- OPCODE_XORB,
- OPCODE_ANY4,
- OPCODE_ALL4,
- OPCODE_ANY8,
- OPCODE_ALL8,
- OPCODE_BF,
- OPCODE_BT,
- OPCODE_MOVF,
- OPCODE_MOVT,
- OPCODE_RSR_BR,
- OPCODE_WSR_BR,
- OPCODE_XSR_BR,
- OPCODE_RSR_CCOUNT,
- OPCODE_WSR_CCOUNT,
- OPCODE_XSR_CCOUNT,
- OPCODE_RSR_CCOMPARE0,
- OPCODE_WSR_CCOMPARE0,
- OPCODE_XSR_CCOMPARE0,
- OPCODE_RSR_CCOMPARE1,
- OPCODE_WSR_CCOMPARE1,
- OPCODE_XSR_CCOMPARE1,
- OPCODE_RSR_CCOMPARE2,
- OPCODE_WSR_CCOMPARE2,
- OPCODE_XSR_CCOMPARE2,
- OPCODE_IPF,
- OPCODE_IHI,
- OPCODE_IPFL,
- OPCODE_IHU,
- OPCODE_IIU,
- OPCODE_III,
- OPCODE_LICT,
- OPCODE_LICW,
- OPCODE_SICT,
- OPCODE_SICW,
- OPCODE_DHWB,
- OPCODE_DHWBI,
- OPCODE_DIWBUI_P,
- OPCODE_DIWB,
- OPCODE_DIWBI,
- OPCODE_DHI,
- OPCODE_DII,
- OPCODE_DPFR,
- OPCODE_DPFW,
- OPCODE_DPFRO,
- OPCODE_DPFWO,
- OPCODE_DPFL,
- OPCODE_DHU,
- OPCODE_DIU,
- OPCODE_SDCT,
- OPCODE_LDCT,
- OPCODE_RSR_PREFCTL,
- OPCODE_WSR_PREFCTL,
- OPCODE_XSR_PREFCTL,
- OPCODE_WSR_PTEVADDR,
- OPCODE_RSR_PTEVADDR,
- OPCODE_XSR_PTEVADDR,
- OPCODE_RSR_RASID,
- OPCODE_WSR_RASID,
- OPCODE_XSR_RASID,
- OPCODE_RSR_ITLBCFG,
- OPCODE_WSR_ITLBCFG,
- OPCODE_XSR_ITLBCFG,
- OPCODE_RSR_DTLBCFG,
- OPCODE_WSR_DTLBCFG,
- OPCODE_XSR_DTLBCFG,
- OPCODE_IDTLB,
- OPCODE_PDTLB,
- OPCODE_RDTLB0,
- OPCODE_RDTLB1,
- OPCODE_WDTLB,
- OPCODE_IITLB,
- OPCODE_PITLB,
- OPCODE_RITLB0,
- OPCODE_RITLB1,
- OPCODE_WITLB,
- OPCODE_LDPTE,
- OPCODE_HWWITLBA,
- OPCODE_HWWDTLBA,
- OPCODE_RSR_CPENABLE,
- OPCODE_WSR_CPENABLE,
- OPCODE_XSR_CPENABLE,
- OPCODE_CLAMPS,
- OPCODE_MIN,
- OPCODE_MAX,
- OPCODE_MINU,
- OPCODE_MAXU,
- OPCODE_NSA,
- OPCODE_NSAU,
- OPCODE_SEXT,
- OPCODE_L32AI,
- OPCODE_S32RI,
- OPCODE_S32C1I,
- OPCODE_RSR_SCOMPARE1,
- OPCODE_WSR_SCOMPARE1,
- OPCODE_XSR_SCOMPARE1,
- OPCODE_RSR_ATOMCTL,
- OPCODE_WSR_ATOMCTL,
- OPCODE_XSR_ATOMCTL,
- OPCODE_QUOU,
- OPCODE_QUOS,
- OPCODE_REMU,
- OPCODE_REMS,
- OPCODE_RER,
- OPCODE_WER,
- OPCODE_RUR_AE_OVF_SAR,
- OPCODE_WUR_AE_OVF_SAR,
- OPCODE_RUR_AE_BITHEAD,
- OPCODE_WUR_AE_BITHEAD,
- OPCODE_RUR_AE_TS_FTS_BU_BP,
- OPCODE_WUR_AE_TS_FTS_BU_BP,
- OPCODE_RUR_AE_SD_NO,
- OPCODE_WUR_AE_SD_NO,
- OPCODE_RUR_AE_OVERFLOW,
- OPCODE_WUR_AE_OVERFLOW,
- OPCODE_RUR_AE_SAR,
- OPCODE_WUR_AE_SAR,
- OPCODE_RUR_AE_BITPTR,
- OPCODE_WUR_AE_BITPTR,
- OPCODE_RUR_AE_BITSUSED,
- OPCODE_WUR_AE_BITSUSED,
- OPCODE_RUR_AE_TABLESIZE,
- OPCODE_WUR_AE_TABLESIZE,
- OPCODE_RUR_AE_FIRST_TS,
- OPCODE_WUR_AE_FIRST_TS,
- OPCODE_RUR_AE_NEXTOFFSET,
- OPCODE_WUR_AE_NEXTOFFSET,
- OPCODE_RUR_AE_SEARCHDONE,
- OPCODE_WUR_AE_SEARCHDONE,
- OPCODE_AE_LP16F_I,
- OPCODE_AE_LP16F_IU,
- OPCODE_AE_LP16F_X,
- OPCODE_AE_LP16F_XU,
- OPCODE_AE_LP24_I,
- OPCODE_AE_LP24_IU,
- OPCODE_AE_LP24_X,
- OPCODE_AE_LP24_XU,
- OPCODE_AE_LP24F_I,
- OPCODE_AE_LP24F_IU,
- OPCODE_AE_LP24F_X,
- OPCODE_AE_LP24F_XU,
- OPCODE_AE_LP16X2F_I,
- OPCODE_AE_LP16X2F_IU,
- OPCODE_AE_LP16X2F_X,
- OPCODE_AE_LP16X2F_XU,
- OPCODE_AE_LP24X2F_I,
- OPCODE_AE_LP24X2F_IU,
- OPCODE_AE_LP24X2F_X,
- OPCODE_AE_LP24X2F_XU,
- OPCODE_AE_LP24X2_I,
- OPCODE_AE_LP24X2_IU,
- OPCODE_AE_LP24X2_X,
- OPCODE_AE_LP24X2_XU,
- OPCODE_AE_SP16X2F_I,
- OPCODE_AE_SP16X2F_IU,
- OPCODE_AE_SP16X2F_X,
- OPCODE_AE_SP16X2F_XU,
- OPCODE_AE_SP24X2S_I,
- OPCODE_AE_SP24X2S_IU,
- OPCODE_AE_SP24X2S_X,
- OPCODE_AE_SP24X2S_XU,
- OPCODE_AE_SP24X2F_I,
- OPCODE_AE_SP24X2F_IU,
- OPCODE_AE_SP24X2F_X,
- OPCODE_AE_SP24X2F_XU,
- OPCODE_AE_SP16F_L_I,
- OPCODE_AE_SP16F_L_IU,
- OPCODE_AE_SP16F_L_X,
- OPCODE_AE_SP16F_L_XU,
- OPCODE_AE_SP24S_L_I,
- OPCODE_AE_SP24S_L_IU,
- OPCODE_AE_SP24S_L_X,
- OPCODE_AE_SP24S_L_XU,
- OPCODE_AE_SP24F_L_I,
- OPCODE_AE_SP24F_L_IU,
- OPCODE_AE_SP24F_L_X,
- OPCODE_AE_SP24F_L_XU,
- OPCODE_AE_LQ56_I,
- OPCODE_AE_LQ56_IU,
- OPCODE_AE_LQ56_X,
- OPCODE_AE_LQ56_XU,
- OPCODE_AE_LQ32F_I,
- OPCODE_AE_LQ32F_IU,
- OPCODE_AE_LQ32F_X,
- OPCODE_AE_LQ32F_XU,
- OPCODE_AE_SQ56S_I,
- OPCODE_AE_SQ56S_IU,
- OPCODE_AE_SQ56S_X,
- OPCODE_AE_SQ56S_XU,
- OPCODE_AE_SQ32F_I,
- OPCODE_AE_SQ32F_IU,
- OPCODE_AE_SQ32F_X,
- OPCODE_AE_SQ32F_XU,
- OPCODE_AE_ZEROP48,
- OPCODE_AE_MOVP48,
- OPCODE_AE_SELP24_LL,
- OPCODE_AE_SELP24_LH,
- OPCODE_AE_SELP24_HL,
- OPCODE_AE_SELP24_HH,
- OPCODE_AE_MOVTP24X2,
- OPCODE_AE_MOVFP24X2,
- OPCODE_AE_MOVTP48,
- OPCODE_AE_MOVFP48,
- OPCODE_AE_MOVPA24X2,
- OPCODE_AE_TRUNCP24A32X2,
- OPCODE_AE_CVTA32P24_L,
- OPCODE_AE_CVTA32P24_H,
- OPCODE_AE_CVTP24A16X2_LL,
- OPCODE_AE_CVTP24A16X2_LH,
- OPCODE_AE_CVTP24A16X2_HL,
- OPCODE_AE_CVTP24A16X2_HH,
- OPCODE_AE_TRUNCP24Q48X2,
- OPCODE_AE_TRUNCP16,
- OPCODE_AE_ROUNDSP24Q48SYM,
- OPCODE_AE_ROUNDSP24Q48ASYM,
- OPCODE_AE_ROUNDSP16Q48SYM,
- OPCODE_AE_ROUNDSP16Q48ASYM,
- OPCODE_AE_ROUNDSP16SYM,
- OPCODE_AE_ROUNDSP16ASYM,
- OPCODE_AE_ZEROQ56,
- OPCODE_AE_MOVQ56,
- OPCODE_AE_MOVTQ56,
- OPCODE_AE_MOVFQ56,
- OPCODE_AE_CVTQ48A32S,
- OPCODE_AE_CVTQ48P24S_L,
- OPCODE_AE_CVTQ48P24S_H,
- OPCODE_AE_SATQ48S,
- OPCODE_AE_TRUNCQ32,
- OPCODE_AE_ROUNDSQ32SYM,
- OPCODE_AE_ROUNDSQ32ASYM,
- OPCODE_AE_TRUNCA32Q48,
- OPCODE_AE_MOVAP24S_L,
- OPCODE_AE_MOVAP24S_H,
- OPCODE_AE_TRUNCA16P24S_L,
- OPCODE_AE_TRUNCA16P24S_H,
- OPCODE_AE_ADDP24,
- OPCODE_AE_SUBP24,
- OPCODE_AE_NEGP24,
- OPCODE_AE_ABSP24,
- OPCODE_AE_MAXP24S,
- OPCODE_AE_MINP24S,
- OPCODE_AE_MAXBP24S,
- OPCODE_AE_MINBP24S,
- OPCODE_AE_ADDSP24S,
- OPCODE_AE_SUBSP24S,
- OPCODE_AE_NEGSP24S,
- OPCODE_AE_ABSSP24S,
- OPCODE_AE_ANDP48,
- OPCODE_AE_NANDP48,
- OPCODE_AE_ORP48,
- OPCODE_AE_XORP48,
- OPCODE_AE_LTP24S,
- OPCODE_AE_LEP24S,
- OPCODE_AE_EQP24,
- OPCODE_AE_ADDQ56,
- OPCODE_AE_SUBQ56,
- OPCODE_AE_NEGQ56,
- OPCODE_AE_ABSQ56,
- OPCODE_AE_MAXQ56S,
- OPCODE_AE_MINQ56S,
- OPCODE_AE_MAXBQ56S,
- OPCODE_AE_MINBQ56S,
- OPCODE_AE_ADDSQ56S,
- OPCODE_AE_SUBSQ56S,
- OPCODE_AE_NEGSQ56S,
- OPCODE_AE_ABSSQ56S,
- OPCODE_AE_ANDQ56,
- OPCODE_AE_NANDQ56,
- OPCODE_AE_ORQ56,
- OPCODE_AE_XORQ56,
- OPCODE_AE_SLLIP24,
- OPCODE_AE_SRLIP24,
- OPCODE_AE_SRAIP24,
- OPCODE_AE_SLLSP24,
- OPCODE_AE_SRLSP24,
- OPCODE_AE_SRASP24,
- OPCODE_AE_SLLISP24S,
- OPCODE_AE_SLLSSP24S,
- OPCODE_AE_SLLIQ56,
- OPCODE_AE_SRLIQ56,
- OPCODE_AE_SRAIQ56,
- OPCODE_AE_SLLSQ56,
- OPCODE_AE_SRLSQ56,
- OPCODE_AE_SRASQ56,
- OPCODE_AE_SLLAQ56,
- OPCODE_AE_SRLAQ56,
- OPCODE_AE_SRAAQ56,
- OPCODE_AE_SLLISQ56S,
- OPCODE_AE_SLLSSQ56S,
- OPCODE_AE_SLLASQ56S,
- OPCODE_AE_LTQ56S,
- OPCODE_AE_LEQ56S,
- OPCODE_AE_EQQ56,
- OPCODE_AE_NSAQ56S,
- OPCODE_AE_MULSRFQ32SP24S_H,
- OPCODE_AE_MULSRFQ32SP24S_L,
- OPCODE_AE_MULARFQ32SP24S_H,
- OPCODE_AE_MULARFQ32SP24S_L,
- OPCODE_AE_MULRFQ32SP24S_H,
- OPCODE_AE_MULRFQ32SP24S_L,
- OPCODE_AE_MULSFQ32SP24S_H,
- OPCODE_AE_MULSFQ32SP24S_L,
- OPCODE_AE_MULAFQ32SP24S_H,
- OPCODE_AE_MULAFQ32SP24S_L,
- OPCODE_AE_MULFQ32SP24S_H,
- OPCODE_AE_MULFQ32SP24S_L,
- OPCODE_AE_MULFS32P16S_LL,
- OPCODE_AE_MULFP24S_LL,
- OPCODE_AE_MULP24S_LL,
- OPCODE_AE_MULFS32P16S_LH,
- OPCODE_AE_MULFP24S_LH,
- OPCODE_AE_MULP24S_LH,
- OPCODE_AE_MULFS32P16S_HL,
- OPCODE_AE_MULFP24S_HL,
- OPCODE_AE_MULP24S_HL,
- OPCODE_AE_MULFS32P16S_HH,
- OPCODE_AE_MULFP24S_HH,
- OPCODE_AE_MULP24S_HH,
- OPCODE_AE_MULAFS32P16S_LL,
- OPCODE_AE_MULAFP24S_LL,
- OPCODE_AE_MULAP24S_LL,
- OPCODE_AE_MULAFS32P16S_LH,
- OPCODE_AE_MULAFP24S_LH,
- OPCODE_AE_MULAP24S_LH,
- OPCODE_AE_MULAFS32P16S_HL,
- OPCODE_AE_MULAFP24S_HL,
- OPCODE_AE_MULAP24S_HL,
- OPCODE_AE_MULAFS32P16S_HH,
- OPCODE_AE_MULAFP24S_HH,
- OPCODE_AE_MULAP24S_HH,
- OPCODE_AE_MULSFS32P16S_LL,
- OPCODE_AE_MULSFP24S_LL,
- OPCODE_AE_MULSP24S_LL,
- OPCODE_AE_MULSFS32P16S_LH,
- OPCODE_AE_MULSFP24S_LH,
- OPCODE_AE_MULSP24S_LH,
- OPCODE_AE_MULSFS32P16S_HL,
- OPCODE_AE_MULSFP24S_HL,
- OPCODE_AE_MULSP24S_HL,
- OPCODE_AE_MULSFS32P16S_HH,
- OPCODE_AE_MULSFP24S_HH,
- OPCODE_AE_MULSP24S_HH,
- OPCODE_AE_MULAFS56P24S_LL,
- OPCODE_AE_MULAS56P24S_LL,
- OPCODE_AE_MULAFS56P24S_LH,
- OPCODE_AE_MULAS56P24S_LH,
- OPCODE_AE_MULAFS56P24S_HL,
- OPCODE_AE_MULAS56P24S_HL,
- OPCODE_AE_MULAFS56P24S_HH,
- OPCODE_AE_MULAS56P24S_HH,
- OPCODE_AE_MULSFS56P24S_LL,
- OPCODE_AE_MULSS56P24S_LL,
- OPCODE_AE_MULSFS56P24S_LH,
- OPCODE_AE_MULSS56P24S_LH,
- OPCODE_AE_MULSFS56P24S_HL,
- OPCODE_AE_MULSS56P24S_HL,
- OPCODE_AE_MULSFS56P24S_HH,
- OPCODE_AE_MULSS56P24S_HH,
- OPCODE_AE_MULFQ32SP16S_L,
- OPCODE_AE_MULFQ32SP16S_H,
- OPCODE_AE_MULFQ32SP16U_L,
- OPCODE_AE_MULFQ32SP16U_H,
- OPCODE_AE_MULQ32SP16S_L,
- OPCODE_AE_MULQ32SP16S_H,
- OPCODE_AE_MULQ32SP16U_L,
- OPCODE_AE_MULQ32SP16U_H,
- OPCODE_AE_MULAFQ32SP16S_L,
- OPCODE_AE_MULAFQ32SP16S_H,
- OPCODE_AE_MULAFQ32SP16U_L,
- OPCODE_AE_MULAFQ32SP16U_H,
- OPCODE_AE_MULAQ32SP16S_L,
- OPCODE_AE_MULAQ32SP16S_H,
- OPCODE_AE_MULAQ32SP16U_L,
- OPCODE_AE_MULAQ32SP16U_H,
- OPCODE_AE_MULSFQ32SP16S_L,
- OPCODE_AE_MULSFQ32SP16S_H,
- OPCODE_AE_MULSFQ32SP16U_L,
- OPCODE_AE_MULSFQ32SP16U_H,
- OPCODE_AE_MULSQ32SP16S_L,
- OPCODE_AE_MULSQ32SP16S_H,
- OPCODE_AE_MULSQ32SP16U_L,
- OPCODE_AE_MULSQ32SP16U_H,
- OPCODE_AE_MULZAAQ32SP16S_LL,
- OPCODE_AE_MULZAAFQ32SP16S_LL,
- OPCODE_AE_MULZAAQ32SP16U_LL,
- OPCODE_AE_MULZAAFQ32SP16U_LL,
- OPCODE_AE_MULZAAQ32SP16S_HH,
- OPCODE_AE_MULZAAFQ32SP16S_HH,
- OPCODE_AE_MULZAAQ32SP16U_HH,
- OPCODE_AE_MULZAAFQ32SP16U_HH,
- OPCODE_AE_MULZAAQ32SP16S_LH,
- OPCODE_AE_MULZAAFQ32SP16S_LH,
- OPCODE_AE_MULZAAQ32SP16U_LH,
- OPCODE_AE_MULZAAFQ32SP16U_LH,
- OPCODE_AE_MULZASQ32SP16S_LL,
- OPCODE_AE_MULZASFQ32SP16S_LL,
- OPCODE_AE_MULZASQ32SP16U_LL,
- OPCODE_AE_MULZASFQ32SP16U_LL,
- OPCODE_AE_MULZASQ32SP16S_HH,
- OPCODE_AE_MULZASFQ32SP16S_HH,
- OPCODE_AE_MULZASQ32SP16U_HH,
- OPCODE_AE_MULZASFQ32SP16U_HH,
- OPCODE_AE_MULZASQ32SP16S_LH,
- OPCODE_AE_MULZASFQ32SP16S_LH,
- OPCODE_AE_MULZASQ32SP16U_LH,
- OPCODE_AE_MULZASFQ32SP16U_LH,
- OPCODE_AE_MULZSAQ32SP16S_LL,
- OPCODE_AE_MULZSAFQ32SP16S_LL,
- OPCODE_AE_MULZSAQ32SP16U_LL,
- OPCODE_AE_MULZSAFQ32SP16U_LL,
- OPCODE_AE_MULZSAQ32SP16S_HH,
- OPCODE_AE_MULZSAFQ32SP16S_HH,
- OPCODE_AE_MULZSAQ32SP16U_HH,
- OPCODE_AE_MULZSAFQ32SP16U_HH,
- OPCODE_AE_MULZSAQ32SP16S_LH,
- OPCODE_AE_MULZSAFQ32SP16S_LH,
- OPCODE_AE_MULZSAQ32SP16U_LH,
- OPCODE_AE_MULZSAFQ32SP16U_LH,
- OPCODE_AE_MULZSSQ32SP16S_LL,
- OPCODE_AE_MULZSSFQ32SP16S_LL,
- OPCODE_AE_MULZSSQ32SP16U_LL,
- OPCODE_AE_MULZSSFQ32SP16U_LL,
- OPCODE_AE_MULZSSQ32SP16S_HH,
- OPCODE_AE_MULZSSFQ32SP16S_HH,
- OPCODE_AE_MULZSSQ32SP16U_HH,
- OPCODE_AE_MULZSSFQ32SP16U_HH,
- OPCODE_AE_MULZSSQ32SP16S_LH,
- OPCODE_AE_MULZSSFQ32SP16S_LH,
- OPCODE_AE_MULZSSQ32SP16U_LH,
- OPCODE_AE_MULZSSFQ32SP16U_LH,
- OPCODE_AE_MULZAAFP24S_HH_LL,
- OPCODE_AE_MULZAAP24S_HH_LL,
- OPCODE_AE_MULZAAFP24S_HL_LH,
- OPCODE_AE_MULZAAP24S_HL_LH,
- OPCODE_AE_MULZASFP24S_HH_LL,
- OPCODE_AE_MULZASP24S_HH_LL,
- OPCODE_AE_MULZASFP24S_HL_LH,
- OPCODE_AE_MULZASP24S_HL_LH,
- OPCODE_AE_MULZSAFP24S_HH_LL,
- OPCODE_AE_MULZSAP24S_HH_LL,
- OPCODE_AE_MULZSAFP24S_HL_LH,
- OPCODE_AE_MULZSAP24S_HL_LH,
- OPCODE_AE_MULZSSFP24S_HH_LL,
- OPCODE_AE_MULZSSP24S_HH_LL,
- OPCODE_AE_MULZSSFP24S_HL_LH,
- OPCODE_AE_MULZSSP24S_HL_LH,
- OPCODE_AE_MULAAFP24S_HH_LL,
- OPCODE_AE_MULAAP24S_HH_LL,
- OPCODE_AE_MULAAFP24S_HL_LH,
- OPCODE_AE_MULAAP24S_HL_LH,
- OPCODE_AE_MULASFP24S_HH_LL,
- OPCODE_AE_MULASP24S_HH_LL,
- OPCODE_AE_MULASFP24S_HL_LH,
- OPCODE_AE_MULASP24S_HL_LH,
- OPCODE_AE_MULSAFP24S_HH_LL,
- OPCODE_AE_MULSAP24S_HH_LL,
- OPCODE_AE_MULSAFP24S_HL_LH,
- OPCODE_AE_MULSAP24S_HL_LH,
- OPCODE_AE_MULSSFP24S_HH_LL,
- OPCODE_AE_MULSSP24S_HH_LL,
- OPCODE_AE_MULSSFP24S_HL_LH,
- OPCODE_AE_MULSSP24S_HL_LH,
- OPCODE_AE_SHA32,
- OPCODE_AE_VLDL32T,
- OPCODE_AE_VLDL16T,
- OPCODE_AE_VLDL16C,
- OPCODE_AE_VLDSHT,
- OPCODE_AE_LB,
- OPCODE_AE_LBI,
- OPCODE_AE_LBK,
- OPCODE_AE_LBKI,
- OPCODE_AE_DB,
- OPCODE_AE_DBI,
- OPCODE_AE_VLEL32T,
- OPCODE_AE_VLEL16T,
- OPCODE_AE_SB,
- OPCODE_AE_SBI,
- OPCODE_AE_VLES16C,
- OPCODE_AE_SBF,
- OPCODE_AE_SLAASQ56S,
- OPCODE_AE_ADDBRBA32,
- OPCODE_AE_MINABSSP24S,
- OPCODE_AE_MAXABSSP24S,
- OPCODE_AE_MINABSSQ56S,
- OPCODE_AE_MAXABSSQ56S,
- OPCODE_RUR_AE_CBEGIN0,
- OPCODE_WUR_AE_CBEGIN0,
- OPCODE_RUR_AE_CEND0,
- OPCODE_WUR_AE_CEND0,
- OPCODE_AE_LP24X2_C,
- OPCODE_AE_SP24X2S_C,
- OPCODE_AE_LP24X2F_C,
- OPCODE_AE_SP24X2F_C,
- OPCODE_AE_LP16X2F_C,
- OPCODE_AE_SP16X2F_C,
- OPCODE_AE_LP24_C,
- OPCODE_AE_SP24S_L_C,
- OPCODE_AE_LP24F_C,
- OPCODE_AE_SP24F_L_C,
- OPCODE_AE_LP16F_C,
- OPCODE_AE_SP16F_L_C,
- OPCODE_AE_LQ56_C,
- OPCODE_AE_SQ56S_C,
- OPCODE_AE_LQ32F_C,
- OPCODE_AE_SQ32F_C,
- OPCODE_RUR_EXPSTATE,
- OPCODE_WUR_EXPSTATE,
- OPCODE_READ_IMPWIRE,
- OPCODE_SETB_EXPSTATE,
- OPCODE_CLRB_EXPSTATE,
- OPCODE_WRMSK_EXPSTATE
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst_get (insn) == 0)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- {
- if (Field_m_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_ILL;
- if (Field_m_Slot_inst_get (insn) == 2)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_RET;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_RETW;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_JX;
- }
- if (Field_m_Slot_inst_get (insn) == 3)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALLX0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALLX4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALLX8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALLX12;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_MOVSP;
- if (Field_r_Slot_inst_get (insn) == 2)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_ISYNC;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RSYNC;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_ESYNC;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DSYNC;
- if (Field_t_Slot_inst_get (insn) == 8)
- return OPCODE_EXCW;
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_MEMW;
- if (Field_t_Slot_inst_get (insn) == 13)
- return OPCODE_EXTW;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_NOP;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 3)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_RFE;
- if (Field_s_Slot_inst_get (insn) == 2)
- return OPCODE_RFDE;
- if (Field_s_Slot_inst_get (insn) == 4)
- return OPCODE_RFWO;
- if (Field_s_Slot_inst_get (insn) == 5)
- return OPCODE_RFWU;
- }
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFI;
- }
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BREAK;
- if (Field_r_Slot_inst_get (insn) == 5)
- {
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SYSCALL;
- if (Field_s_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SIMCALL;
- }
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RSIL;
- if (Field_r_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_WAITI;
- if (Field_r_Slot_inst_get (insn) == 7)
- {
- if (Field_t_Slot_inst_get (insn) == 14)
- return OPCODE_LDDR32_P;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_SDDR32_P;
- }
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_ANY4;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_ALL4;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_ANY8;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_ALL8;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- return OPCODE_AND;
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_OR;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_XOR;
- if (Field_op2_Slot_inst_get (insn) == 4)
- {
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSR;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSL;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8L;
- if (Field_r_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8B;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_thi3_Slot_inst_get (insn) == 0)
- return OPCODE_SSAI;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RER;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_WER;
- if (Field_r_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_ROTW;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_NSA;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_NSAU;
- }
- if (Field_op2_Slot_inst_get (insn) == 5)
- {
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_HWWITLBA;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_RITLB0;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IITLB;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_PITLB;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_WITLB;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_RITLB1;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_HWWDTLBA;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_RDTLB0;
- if (Field_r_Slot_inst_get (insn) == 12 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IDTLB;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_PDTLB;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_WDTLB;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_RDTLB1;
- }
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_NEG;
- if (Field_s_Slot_inst_get (insn) == 1)
- return OPCODE_ABS;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_ADD;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_ADDX2;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_ADDX4;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_ADDX8;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_SUB;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_SUBX2;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_SUBX4;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_SUBX8;
- }
- if (Field_op1_Slot_inst_get (insn) == 1)
- {
- if ((Field_op2_Slot_inst_get (insn) == 0 ||
- Field_op2_Slot_inst_get (insn) == 1))
- return OPCODE_SLLI;
- if ((Field_op2_Slot_inst_get (insn) == 2 ||
- Field_op2_Slot_inst_get (insn) == 3))
- return OPCODE_SRAI;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_SRLI;
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_XSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_XSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_XSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_XSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 4)
- return OPCODE_XSR_BR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_XSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_XSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 16)
- return OPCODE_XSR_ACCLO;
- if (Field_sr_Slot_inst_get (insn) == 17)
- return OPCODE_XSR_ACCHI;
- if (Field_sr_Slot_inst_get (insn) == 32)
- return OPCODE_XSR_M0;
- if (Field_sr_Slot_inst_get (insn) == 33)
- return OPCODE_XSR_M1;
- if (Field_sr_Slot_inst_get (insn) == 34)
- return OPCODE_XSR_M2;
- if (Field_sr_Slot_inst_get (insn) == 35)
- return OPCODE_XSR_M3;
- if (Field_sr_Slot_inst_get (insn) == 40)
- return OPCODE_XSR_PREFCTL;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_XSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_XSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 83)
- return OPCODE_XSR_PTEVADDR;
- if (Field_sr_Slot_inst_get (insn) == 90)
- return OPCODE_XSR_RASID;
- if (Field_sr_Slot_inst_get (insn) == 91)
- return OPCODE_XSR_ITLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 92)
- return OPCODE_XSR_DTLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_XSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_XSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_XSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_XSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_XSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_XSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_XSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_XSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_XSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_XSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_XSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_XSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_XSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_XSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_XSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_XSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_XSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_XSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_XSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_XSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_XSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_XSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_XSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_XSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_XSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_XSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_XSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_XSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_XSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_XSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_XSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 224)
- return OPCODE_XSR_CPENABLE;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_XSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_XSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_XSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_XSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_XSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_XSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_XSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_XSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_XSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_XSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_XSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_XSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_XSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_XSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_SRC;
- if (Field_op2_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRL;
- if (Field_op2_Slot_inst_get (insn) == 10 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SLL;
- if (Field_op2_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRA;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_MUL16U;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_MUL16S;
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_LICT;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_SICT;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_LICW;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_SICW;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_LDCT;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_SDCT;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_RFDO;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFDD;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_LDPTE;
- }
- }
- if (Field_op1_Slot_inst_get (insn) == 2)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_ANDB;
- if (Field_op2_Slot_inst_get (insn) == 1)
- return OPCODE_ANDBC;
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_ORB;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_ORBC;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_XORB;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MULL;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_MULUH;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_MULSH;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_QUOU;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_QUOS;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_REMU;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_REMS;
- }
- if (Field_op1_Slot_inst_get (insn) == 3)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_RSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_RSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_RSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_RSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 4)
- return OPCODE_RSR_BR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_RSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_RSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 16)
- return OPCODE_RSR_ACCLO;
- if (Field_sr_Slot_inst_get (insn) == 17)
- return OPCODE_RSR_ACCHI;
- if (Field_sr_Slot_inst_get (insn) == 32)
- return OPCODE_RSR_M0;
- if (Field_sr_Slot_inst_get (insn) == 33)
- return OPCODE_RSR_M1;
- if (Field_sr_Slot_inst_get (insn) == 34)
- return OPCODE_RSR_M2;
- if (Field_sr_Slot_inst_get (insn) == 35)
- return OPCODE_RSR_M3;
- if (Field_sr_Slot_inst_get (insn) == 40)
- return OPCODE_RSR_PREFCTL;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_RSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_RSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 83)
- return OPCODE_RSR_PTEVADDR;
- if (Field_sr_Slot_inst_get (insn) == 90)
- return OPCODE_RSR_RASID;
- if (Field_sr_Slot_inst_get (insn) == 91)
- return OPCODE_RSR_ITLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 92)
- return OPCODE_RSR_DTLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_RSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_RSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_RSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_RSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_RSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_RSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_RSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_RSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_RSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_RSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_RSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_RSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_RSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_RSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_RSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_RSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_RSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_RSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_RSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_RSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_RSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_RSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_RSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_RSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_RSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 208)
- return OPCODE_RSR_CONFIGID1;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_RSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_RSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_RSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_RSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_RSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_RSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_RSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 224)
- return OPCODE_RSR_CPENABLE;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_RSR_INTERRUPT;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_RSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_RSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_RSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_RSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_RSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_RSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 235)
- return OPCODE_RSR_PRID;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_RSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_RSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_RSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_RSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_RSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_RSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 243)
- return OPCODE_RSR_243;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_RSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_RSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_WSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_WSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_WSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_WSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 4)
- return OPCODE_WSR_BR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_WSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_WSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 16)
- return OPCODE_WSR_ACCLO;
- if (Field_sr_Slot_inst_get (insn) == 17)
- return OPCODE_WSR_ACCHI;
- if (Field_sr_Slot_inst_get (insn) == 32)
- return OPCODE_WSR_M0;
- if (Field_sr_Slot_inst_get (insn) == 33)
- return OPCODE_WSR_M1;
- if (Field_sr_Slot_inst_get (insn) == 34)
- return OPCODE_WSR_M2;
- if (Field_sr_Slot_inst_get (insn) == 35)
- return OPCODE_WSR_M3;
- if (Field_sr_Slot_inst_get (insn) == 40)
- return OPCODE_WSR_PREFCTL;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_WSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_WSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 83)
- return OPCODE_WSR_PTEVADDR;
- if (Field_sr_Slot_inst_get (insn) == 89)
- return OPCODE_WSR_MMID;
- if (Field_sr_Slot_inst_get (insn) == 90)
- return OPCODE_WSR_RASID;
- if (Field_sr_Slot_inst_get (insn) == 91)
- return OPCODE_WSR_ITLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 92)
- return OPCODE_WSR_DTLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 96)
- return OPCODE_WSR_IBREAKENABLE;
- if (Field_sr_Slot_inst_get (insn) == 97)
- return OPCODE_WSR_MEMCTL;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_WSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_WSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 128)
- return OPCODE_WSR_IBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 129)
- return OPCODE_WSR_IBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 144)
- return OPCODE_WSR_DBREAKA0;
- if (Field_sr_Slot_inst_get (insn) == 145)
- return OPCODE_WSR_DBREAKA1;
- if (Field_sr_Slot_inst_get (insn) == 160)
- return OPCODE_WSR_DBREAKC0;
- if (Field_sr_Slot_inst_get (insn) == 161)
- return OPCODE_WSR_DBREAKC1;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_WSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_WSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_WSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 179)
- return OPCODE_WSR_EPC3;
- if (Field_sr_Slot_inst_get (insn) == 180)
- return OPCODE_WSR_EPC4;
- if (Field_sr_Slot_inst_get (insn) == 181)
- return OPCODE_WSR_EPC5;
- if (Field_sr_Slot_inst_get (insn) == 182)
- return OPCODE_WSR_EPC6;
- if (Field_sr_Slot_inst_get (insn) == 183)
- return OPCODE_WSR_EPC7;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_WSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_WSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 195)
- return OPCODE_WSR_EPS3;
- if (Field_sr_Slot_inst_get (insn) == 196)
- return OPCODE_WSR_EPS4;
- if (Field_sr_Slot_inst_get (insn) == 197)
- return OPCODE_WSR_EPS5;
- if (Field_sr_Slot_inst_get (insn) == 198)
- return OPCODE_WSR_EPS6;
- if (Field_sr_Slot_inst_get (insn) == 199)
- return OPCODE_WSR_EPS7;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_WSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_WSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 211)
- return OPCODE_WSR_EXCSAVE3;
- if (Field_sr_Slot_inst_get (insn) == 212)
- return OPCODE_WSR_EXCSAVE4;
- if (Field_sr_Slot_inst_get (insn) == 213)
- return OPCODE_WSR_EXCSAVE5;
- if (Field_sr_Slot_inst_get (insn) == 214)
- return OPCODE_WSR_EXCSAVE6;
- if (Field_sr_Slot_inst_get (insn) == 215)
- return OPCODE_WSR_EXCSAVE7;
- if (Field_sr_Slot_inst_get (insn) == 224)
- return OPCODE_WSR_CPENABLE;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_WSR_INTSET;
- if (Field_sr_Slot_inst_get (insn) == 227)
- return OPCODE_WSR_INTCLEAR;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_WSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_WSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_WSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_WSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_WSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_WSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_WSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_WSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_WSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_WSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_WSR_CCOMPARE2;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_WSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_WSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_SEXT;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_CLAMPS;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_MIN;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_MAX;
- if (Field_op2_Slot_inst_get (insn) == 6)
- return OPCODE_MINU;
- if (Field_op2_Slot_inst_get (insn) == 7)
- return OPCODE_MAXU;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MOVEQZ;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_MOVNEZ;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_MOVLTZ;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_MOVGEZ;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_MOVF;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_MOVT;
- if (Field_op2_Slot_inst_get (insn) == 14)
- {
- if (Field_st_Slot_inst_get (insn) == 230)
- return OPCODE_RUR_EXPSTATE;
- if (Field_st_Slot_inst_get (insn) == 231)
- return OPCODE_RUR_THREADPTR;
- if (Field_st_Slot_inst_get (insn) == 240)
- return OPCODE_RUR_AE_OVF_SAR;
- if (Field_st_Slot_inst_get (insn) == 241)
- return OPCODE_RUR_AE_BITHEAD;
- if (Field_st_Slot_inst_get (insn) == 242)
- return OPCODE_RUR_AE_TS_FTS_BU_BP;
- if (Field_st_Slot_inst_get (insn) == 243)
- return OPCODE_RUR_AE_SD_NO;
- if (Field_st_Slot_inst_get (insn) == 246)
- return OPCODE_RUR_AE_CBEGIN0;
- if (Field_st_Slot_inst_get (insn) == 247)
- return OPCODE_RUR_AE_CEND0;
- }
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WUR_EXPSTATE;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_WUR_THREADPTR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_WUR_AE_OVF_SAR;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_WUR_AE_BITHEAD;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_WUR_AE_TS_FTS_BU_BP;
- if (Field_sr_Slot_inst_get (insn) == 243)
- return OPCODE_WUR_AE_SD_NO;
- if (Field_sr_Slot_inst_get (insn) == 246)
- return OPCODE_WUR_AE_CBEGIN0;
- if (Field_sr_Slot_inst_get (insn) == 247)
- return OPCODE_WUR_AE_CEND0;
- }
- }
- if ((Field_op1_Slot_inst_get (insn) == 4 ||
- Field_op1_Slot_inst_get (insn) == 5))
- return OPCODE_EXTUI;
- if (Field_op1_Slot_inst_get (insn) == 9)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_L32E;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_S32E;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_S32NB;
- }
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_READ_IMPWIRE;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s3to1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_SETB_EXPSTATE;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s3to1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_CLRB_EXPSTATE;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14)
- return OPCODE_WRMSK_EXPSTATE;
- }
- if (Field_op0_Slot_inst_get (insn) == 1)
- return OPCODE_L32R;
- if (Field_op0_Slot_inst_get (insn) == 2)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_L8UI;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_L16UI;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_L32I;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_S8I;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_S16I;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_S32I;
- if (Field_r_Slot_inst_get (insn) == 7)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_DPFR;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_DPFW;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_DPFRO;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DPFWO;
- if (Field_t_Slot_inst_get (insn) == 4)
- return OPCODE_DHWB;
- if (Field_t_Slot_inst_get (insn) == 5)
- return OPCODE_DHWBI;
- if (Field_t_Slot_inst_get (insn) == 6)
- return OPCODE_DHI;
- if (Field_t_Slot_inst_get (insn) == 7)
- return OPCODE_DII;
- if (Field_t_Slot_inst_get (insn) == 8)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- return OPCODE_DPFL;
- if (Field_op1_Slot_inst_get (insn) == 2)
- return OPCODE_DHU;
- if (Field_op1_Slot_inst_get (insn) == 3)
- return OPCODE_DIU;
- if (Field_op1_Slot_inst_get (insn) == 4)
- return OPCODE_DIWB;
- if (Field_op1_Slot_inst_get (insn) == 5)
- return OPCODE_DIWBI;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_DIWBUI_P;
- }
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_IPF;
- if (Field_t_Slot_inst_get (insn) == 13)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- return OPCODE_IPFL;
- if (Field_op1_Slot_inst_get (insn) == 2)
- return OPCODE_IHU;
- if (Field_op1_Slot_inst_get (insn) == 3)
- return OPCODE_IIU;
- }
- if (Field_t_Slot_inst_get (insn) == 14)
- return OPCODE_IHI;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_III;
- }
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_L16SI;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_MOVI;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_L32AI;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_ADDI;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_ADDMI;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_S32C1I;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_S32RI;
- }
- if (Field_op0_Slot_inst_get (insn) == 4)
- {
- if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_I;
- if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_X;
- if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_I;
- if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_X;
- if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_IU;
- if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_XU;
- if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_CVTQ48A32S;
- if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_IU;
- if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP24F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP24X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_ae_s3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVP48;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVPA24X2;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_CVTA32P24_L;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_LL;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_HL;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVAP24S_L;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_TRUNCA16P24S_L;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP16X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP24X2_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_TRUNCP24A32X2;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_CVTA32P24_H;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_LH;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_HH;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVAP24S_H;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_TRUNCA16P24S_H;
- if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_I;
- if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_X;
- if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_TRUNCA32Q48;
- if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_I;
- if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_X;
- if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_NSAQ56S;
- if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_IU;
- if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_XU;
- if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_IU;
- if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_XU;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLIQ56;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRLIQ56;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRAIQ56;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLISQ56S;
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SHA32;
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLDL32T;
- if (Field_op1_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SLLAQ56;
- if (Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLDL16T;
- if (Field_op1_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SRLAQ56;
- if (Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LBK;
- if (Field_op1_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SRAAQ56;
- if (Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLEL32T;
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SLLASQ56S;
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLEL16T;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_MOVTQ56;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_MOVFQ56;
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH_LDINC;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH_LDDEC;
- }
- if (Field_op2_Slot_inst_get (insn) == 2)
- {
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DD_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DD_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DD_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 3)
- {
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AD_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AD_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AD_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 4)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH_LDINC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH_LDINC;
- }
- if (Field_op2_Slot_inst_get (insn) == 5)
- {
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH_LDDEC;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH_LDDEC;
- }
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_DA_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_DA_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_DA_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 7)
- {
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 1 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 2 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 3 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_UMUL_AA_HH;
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 7 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MUL_AA_HH;
- if (Field_op1_Slot_inst_get (insn) == 8 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 9 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 10 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 11 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULA_AA_HH;
- if (Field_op1_Slot_inst_get (insn) == 12 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_LL;
- if (Field_op1_Slot_inst_get (insn) == 13 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_HL;
- if (Field_op1_Slot_inst_get (insn) == 14 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_LH;
- if (Field_op1_Slot_inst_get (insn) == 15 &&
- Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_MULS_AA_HH;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- {
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return OPCODE_LDINC;
- }
- if (Field_op2_Slot_inst_get (insn) == 9)
- {
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return OPCODE_LDDEC;
- }
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_OVERFLOW;
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_SBI;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_SAR;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_DB;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_SB;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_BITPTR;
- if (Field_r_Slot_inst_get (insn) == 3 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_BITSUSED;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_TABLESIZE;
- if (Field_r_Slot_inst_get (insn) == 5 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_FIRST_TS;
- if (Field_r_Slot_inst_get (insn) == 6 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_NEXTOFFSET;
- if (Field_r_Slot_inst_get (insn) == 7 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_SEARCHDONE;
- if (Field_r_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_VLDSHT;
- if (Field_r_Slot_inst_get (insn) == 12 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_VLES16C;
- if (Field_r_Slot_inst_get (insn) == 13 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SBF;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_VLDL16C;
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLSQ56;
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LB;
- if (Field_s_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRLSQ56;
- if (Field_s_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRASQ56;
- if (Field_s_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLSSQ56S;
- if (Field_s_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVQ56;
- if (Field_s_Slot_inst_get (insn) == 8 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_OVERFLOW;
- if (Field_s_Slot_inst_get (insn) == 9 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_SAR;
- if (Field_s_Slot_inst_get (insn) == 10 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_BITPTR;
- if (Field_s_Slot_inst_get (insn) == 11 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_BITSUSED;
- if (Field_s_Slot_inst_get (insn) == 12 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_TABLESIZE;
- if (Field_s_Slot_inst_get (insn) == 13 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_FIRST_TS;
- if (Field_s_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_NEXTOFFSET;
- if (Field_s_Slot_inst_get (insn) == 15 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_SEARCHDONE;
- if (Field_t_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_LBKI;
- if (Field_t_Slot_inst_get (insn) == 0 &&
- Field_r_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_DBI;
- if (Field_t_Slot_inst_get (insn) == 2 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_LBI;
- }
- if (Field_op0_Slot_inst_get (insn) == 5)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALL0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALL4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALL8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALL12;
- }
- if (Field_op0_Slot_inst_get (insn) == 6)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_J;
- if (Field_n_Slot_inst_get (insn) == 1)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQZ;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEZ;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTZ;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEZ;
- }
- if (Field_n_Slot_inst_get (insn) == 2)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQI;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEI;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEI;
- }
- if (Field_n_Slot_inst_get (insn) == 3)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_ENTRY;
- if (Field_m_Slot_inst_get (insn) == 1)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_BF;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_BT;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_LOOP;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_LOOPNEZ;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_LOOPGTZ;
- }
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTUI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEUI;
- }
- }
- if (Field_op0_Slot_inst_get (insn) == 7)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_BNONE;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_BEQ;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_BLT;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_BLTU;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BALL;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_BBC;
- if ((Field_r_Slot_inst_get (insn) == 6 ||
- Field_r_Slot_inst_get (insn) == 7))
- return OPCODE_BBCI;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_BANY;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_BNE;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_BGE;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_BGEU;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_BNALL;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_BBS;
- if ((Field_r_Slot_inst_get (insn) == 14 ||
- Field_r_Slot_inst_get (insn) == 15))
- return OPCODE_BBSI;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16b_get (insn) == 12)
- {
- if (Field_i_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOVI_N;
- if (Field_i_Slot_inst16b_get (insn) == 1)
- {
- if (Field_z_Slot_inst16b_get (insn) == 0)
- return OPCODE_BEQZ_N;
- if (Field_z_Slot_inst16b_get (insn) == 1)
- return OPCODE_BNEZ_N;
- }
- }
- if (Field_op0_Slot_inst16b_get (insn) == 13)
- {
- if (Field_r_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOV_N;
- if (Field_r_Slot_inst16b_get (insn) == 15)
- {
- if (Field_t_Slot_inst16b_get (insn) == 0)
- return OPCODE_RET_N;
- if (Field_t_Slot_inst16b_get (insn) == 1)
- return OPCODE_RETW_N;
- if (Field_t_Slot_inst16b_get (insn) == 2)
- return OPCODE_BREAK_N;
- if (Field_t_Slot_inst16b_get (insn) == 3 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_NOP_N;
- if (Field_t_Slot_inst16b_get (insn) == 6 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_ILL_N;
- }
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16a_get (insn) == 8)
- return OPCODE_L32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 9)
- return OPCODE_S32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 10)
- return OPCODE_ADD_N;
- if (Field_op0_Slot_inst16a_get (insn) == 11)
- return OPCODE_ADDI_N;
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_ae_slot0_decode (const xtensa_insnbuf insn)
-{
- if (Field_ae_s20_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
- Field_ftsf378ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_BT;
- if (Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SELP24_HH;
- if (Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SELP24_HL;
- if (Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SELP24_LH;
- if (Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_ftsf315_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 2 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLAASQ56S;
- if (Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_C;
- if (Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_C;
- if (Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_C;
- if (Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_C;
- if (Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_C;
- if (Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_C;
- if (Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_C;
- if (Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_C;
- if (Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_C;
- if (Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_C;
- if (Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_C;
- if (Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_C;
- if (Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SQ32F_C;
- if (Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SQ56S_C;
- if (Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SELP24_LL;
- if (Field_ftsf211ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_J;
- if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_EXTUI;
- if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BEQZ;
- if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BNEZ;
- if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BGEZ;
- if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVI;
- if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 13 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BLTZ;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRAI;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SLLI;
- if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 43 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_HH;
- if (Field_ftsf217ae_slot0_Slot_ae_slot0_get (insn) == 299 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_I;
- if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 46 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_HL;
- if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 47 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_IU;
- if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 302 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_X;
- if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 303 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_XU;
- if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 58 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_LH;
- if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 59 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_I;
- if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 62 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_IU;
- if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 63 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_XU;
- if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 314 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_X;
- if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 315 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_I;
- if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 318 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_IU;
- if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 319 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_X;
- if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 170 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_LL;
- if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 171 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_XU;
- if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 174 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_I;
- if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 175 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_XU;
- if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 186 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_IU;
- if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 187 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_I;
- if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 190 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_IU;
- if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 191 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_X;
- if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_X;
- if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_XU;
- if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_I;
- if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_X;
- if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_IU;
- if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_XU;
- if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVPA24X2;
- if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_I;
- if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 75 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_IU;
- if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 331 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_X;
- if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 78 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_X;
- if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 79 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_XU;
- if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 334 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_I;
- if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 335 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_IU;
- if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 90 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_XU;
- if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 91 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_X;
- if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 94 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_XU;
- if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 95 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_IU;
- if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 346 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_I;
- if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 347 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_X;
- if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 350 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_XU;
- if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 351 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_I;
- if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 106 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_I;
- if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 107 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_IU;
- if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 110 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_X;
- if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 111 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_IU;
- if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 122 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_XU;
- if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_X;
- if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 126 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_XU;
- if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 127 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_TRUNCP24A32X2;
- if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 362 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_I;
- if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 363 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ32F_I;
- if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 875 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ32F_XU;
- if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 366 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ32F_IU;
- if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 367 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_I;
- if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 878 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_IU;
- if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 879 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_X;
- if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 378 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ32F_X;
- if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 379 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_XU;
- if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 890 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_NSAQ56S;
- if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 891 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_TRUNCA32Q48;
- if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 2938 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s8_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_JX;
- if (Field_ftsf280_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBCI;
- if (Field_ftsf280_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBSI;
- if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 2939 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s8_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSR;
- if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 1981 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_NOP;
- if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 957 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSA8B;
- if (Field_ftsf285ae_slot0_Slot_ae_slot0_get (insn) == 957 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSA8L;
- if (Field_ftsf287ae_slot0_Slot_ae_slot0_get (insn) == 957 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSL;
- if (Field_ftsf288_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
- Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_BLTUI;
- if (Field_ftsf289ae_slot0_Slot_ae_slot0_get (insn) == 382 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTA32P24_H;
- if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 383 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTA32P24_L;
- if (Field_ftsf291ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVAP24S_H;
- if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf382ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVAP24S_L;
- if (Field_ftsf293ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf384ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_TRUNCA16P24S_H;
- if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf383ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_TRUNCA16P24S_L;
- if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 202 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_IU;
- if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 4298 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf315_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVP48;
- if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 4554 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ALL4;
- if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 12746 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf309_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSAI;
- if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 2506 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf373ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ANY4;
- if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 1482 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf370ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ALL8;
- if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 970 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf376ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ANY8;
- if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 203 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ32F_I;
- if (Field_ftsf305ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ56_I;
- if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 715 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ56_IU;
- if (Field_ftsf307ae_slot0_Slot_ae_slot0_get (insn) == 971 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ56_X;
- if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 206 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s8_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_LQ32F_IU;
- if (Field_ftsf309_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s8_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_LQ56_C;
- if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 207 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s8_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_LQ56_XU;
- if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 231 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf386ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_CVTQ48A32S;
- if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 219 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLIQ56;
- if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 222 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLISQ56S;
- if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 475 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SRAIQ56;
- if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 731 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SRLIQ56;
- if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 987 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ABS;
- if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 2011 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_NEG;
- if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 3035 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRA;
- if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 4059 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRL;
- if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVQ56;
- if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 1502 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SLLSSQ56S;
- if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 1502 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf389ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRASQ56;
- if (Field_ftsf319ae_slot0_Slot_ae_slot0_get (insn) == 1502 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf388ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRLSQ56;
- if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf387ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SLLSQ56;
- if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 223 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVFQ56;
- if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 479 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVTQ56;
- if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 735 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLAQ56;
- if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 991 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SRLAQ56;
- if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 735 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SLLASQ56S;
- if (Field_ftsf327ae_slot0_Slot_ae_slot0_get (insn) == 991 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SLL;
- if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 479 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRAAQ56;
- if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf379ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_LQ32F_XU;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 11 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVGEZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 14 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVLTZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 15 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ORBC;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 23 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADD;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 26 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVNEZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 27 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRLI;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 30 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 31 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUBX4;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 39 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADDX2;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 42 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVT;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 55 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AND;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 71 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADDX4;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 74 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_OR;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 87 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_CLAMPS;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 103 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MAX;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 119 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MIN;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 139 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ORB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 142 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SEXT;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 143 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRC;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 151 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADDX8;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 154 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUBX2;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 155 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUBX8;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 158 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_XOR;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 159 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_XORB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 167 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ANDB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ANDBC;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MAXU;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 215 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MINU;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 218 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ae_r10_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_LQ32F_X;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 231 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVEQZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 247 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVF;
- if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
- return OPCODE_L32R;
- if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_ADDBRBA32;
- if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_BNE;
- if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_BNONE;
- if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_ADDI;
- if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_L16SI;
- if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BALL;
- if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_L8UI;
- if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_ADDMI;
- if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_L16UI;
- if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBS;
- if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_S16I;
- if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BEQ;
- if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_S32I;
- if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BGEU;
- if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_S8I;
- if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BANY;
- if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBC;
- if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BGE;
- if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BLT;
- if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BLTU;
- if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BNALL;
- if (Field_s8_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
- Field_ftsf280_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_L32I;
- if (Field_s8_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf309_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 &&
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 &&
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 &&
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ32F_C;
- if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BEQI;
- if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BGEI;
- if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BGEUI;
- if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BNEI;
- if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BLTI;
- if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
- Field_r_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_BF;
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_ae_slot1_decode (const xtensa_insnbuf insn)
-{
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 50 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP24S_L;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 82 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULARFQ32SP24S_L;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 114 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP24S_L;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 146 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULRFQ32SP24S_L;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 178 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP24S_L;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 210 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSRFQ32SP24S_L;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 274 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULRFQ32SP24S_H;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 306 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP24S_H;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 338 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSRFQ32SP24S_H;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 402 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULARFQ32SP24S_H;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 434 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP24S_H;
- if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 466 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP24S_H;
- if (Field_ae_r20_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_LTQ56S;
- if (Field_ae_s20_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf340ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULZAAP24S_HL_LH;
- if (Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf91_Slot_ae_slot1_get (insn) == 1 &&
- Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 &&
- Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MAXABSSP24S;
- if (Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf91_Slot_ae_slot1_get (insn) == 1 &&
- Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 &&
- Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MINABSSP24S;
- if (Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 &&
- Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MINABSSQ56S;
- if (Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (insn) == 1 &&
- Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 0 &&
- Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 &&
- Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 &&
- Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MAXABSSQ56S;
- if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf335_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULSQ32SP16U_H;
- if (Field_ftsf102ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULSFQ32SP16U_H;
- if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULAFQ32SP16S_H;
- if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MAXBQ56S;
- if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MINBQ56S;
- if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_EQQ56;
- if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ADDSQ56S;
- if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ANDQ56;
- if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 131 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MAXQ56S;
- if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ORQ56;
- if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 259 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MINQ56S;
- if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 323 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_SUBQ56;
- if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 387 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_SUBSQ56S;
- if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 451 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_XORQ56;
- if (Field_ftsf117ae_slot1_Slot_ae_slot1_get (insn) == 515 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_NANDQ56;
- if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 2307 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ABSQ56;
- if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 2315 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_NEGSQ56S;
- if (Field_ftsf121ae_slot1_Slot_ae_slot1_get (insn) == 1163 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf91_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_SATQ48S;
- if (Field_ftsf123ae_slot1_Slot_ae_slot1_get (insn) == 323 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ABSSQ56S;
- if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf352ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_NEGQ56;
- if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_LEQ56S;
- if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf357ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_TRUNCP24Q48X2;
- if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ADDQ56;
- if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAFP24S_HH_LL;
- if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAFP24S_HL_LH;
- if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAP24S_HH_LL;
- if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS32P16S_HL;
- if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAP24S_HL_LH;
- if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS32P16S_LH;
- if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS32P16S_LL;
- if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_HH;
- if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_HH;
- if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_HL;
- if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_LH;
- if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_HH;
- if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_LL;
- if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_HL;
- if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_LH;
- if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_LL;
- if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_HL;
- if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_HH;
- if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_HL;
- if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASFP24S_HH_LL;
- if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_LH;
- if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASFP24S_HL_LH;
- if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASP24S_HH_LL;
- if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASP24S_HL_LH;
- if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_LL;
- if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_HH;
- if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_HL;
- if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_LL;
- if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_LH;
- if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_HH;
- if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_HL;
- if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_LH;
- if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_LH;
- if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_LL;
- if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_HH;
- if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAFP24S_HH_LL;
- if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_HL;
- if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAFP24S_HL_LH;
- if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAP24S_HH_LL;
- if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAP24S_HL_LH;
- if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_LH;
- if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_HH;
- if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_HL;
- if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_LL;
- if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_LH;
- if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_HH;
- if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_HL;
- if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_LH;
- if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_LL;
- if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_LL;
- if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_HH;
- if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_LL;
- if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_HL;
- if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_HH;
- if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_HL;
- if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_LH;
- if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_LH;
- if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_LL;
- if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_HH;
- if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_LH;
- if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_HL;
- if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_LL;
- if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSFP24S_HH_LL;
- if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSFP24S_HL_LH;
- if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_LL;
- if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSP24S_HH_LL;
- if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSP24S_HL_LH;
- if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASFP24S_HH_LL;
- if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZAAFP24S_HH_LL;
- if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASFP24S_HL_LH;
- if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASP24S_HH_LL;
- if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASP24S_HL_LH;
- if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZAAFP24S_HL_LH;
- if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAFP24S_HH_LL;
- if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAFP24S_HL_LH;
- if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAP24S_HL_LH;
- if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAP24S_HH_LL;
- if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSSFP24S_HH_LL;
- if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSSFP24S_HL_LH;
- if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSSP24S_HH_LL;
- if (Field_ftsf208ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULZAAP24S_HH_LL;
- if (Field_ftsf20ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MAXBP24S;
- if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULZSSP24S_HL_LH;
- if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MINBP24S;
- if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVFP48;
- if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ADDP24;
- if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MAXP24S;
- if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ADDSP24S;
- if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MINP24S;
- if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 84 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_NANDP48;
- if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 85 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ORP48;
- if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ANDP48;
- if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_HH;
- if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_HL;
- if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_LL;
- if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 100 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_LH;
- if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 101 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SUBP24;
- if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 116 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SUBSP24S;
- if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 117 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_XORP48;
- if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVTP48;
- if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ABSP24;
- if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 88 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_NEGP24;
- if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 152 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_NEGSP24S;
- if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 216 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf333ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_NOP;
- if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 88 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf359ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ZEROP48;
- if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 704 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVP48;
- if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 708 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSP16ASYM;
- if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 712 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSP16SYM;
- if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 716 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SLLSSP24S;
- if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 720 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SLLSP24;
- if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 724 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRASP24;
- if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 728 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRLSP24;
- if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 732 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_TRUNCP16;
- if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf356ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ABSSP24S;
- if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_EQP24;
- if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_LTP24S;
- if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MOVFP24X2;
- if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf355ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MOVTP24X2;
- if (Field_ftsf61_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULAFS32P16S_HH;
- if (Field_ftsf62ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_LEP24S;
- if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSP16Q48ASYM;
- if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 101 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSP16Q48SYM;
- if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf345ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSP24Q48ASYM;
- if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf347ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSP24Q48SYM;
- if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SLLIP24;
- if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SLLISP24S;
- if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRAIP24;
- if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRLIP24;
- if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16S_L;
- if (Field_ftsf70ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16U_H;
- if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16U_L;
- if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 103 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16U_H;
- if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 135 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16S_H;
- if (Field_ftsf74ae_slot1_Slot_ae_slot1_get (insn) == 167 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16U_L;
- if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 199 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16S_H;
- if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 231 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16S_L;
- if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 263 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16S_L;
- if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 295 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16U_H;
- if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 327 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16U_L;
- if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 359 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16S_L;
- if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 391 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16S_H;
- if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16U_H;
- if (Field_ftsf83ae_slot1_Slot_ae_slot1_get (insn) == 455 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16U_L;
- if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 487 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16S_H;
- if (Field_ftsf85ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16S_L;
- if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16U_L;
- if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSQ32SP16S_H;
- if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 107 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSQ32SP16U_L;
- if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 139 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSQ32SP16S_L;
- if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 331 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf55_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_CVTQ48P24S_H;
- if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 363 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf358ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ZEROQ56;
- if (Field_ftsf93ae_slot1_Slot_ae_slot1_get (insn) == 203 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_CVTQ48P24S_L;
- if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 1803 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVQ56;
- if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 1835 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSQ32ASYM;
- if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 939 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSQ32SYM;
- if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 491 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf351_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_TRUNCQ32;
- if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16U_LL;
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[1] & 0xffffff00) >> 8);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[1] = (insn[1] & ~0xffffff00) | ((slotbuf[0] & 0xffffff) << 8);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
-}
-
-static void
-Slot_ae_format_Format_ae_slot1_10_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[0] & 0xfffffc00) >> 10);
- slotbuf[0] = (slotbuf[0] & ~0x400000) | ((insn[1] & 0x1) << 22);
-}
-
-static void
-Slot_ae_format_Format_ae_slot1_10_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xfffffc00) | ((slotbuf[0] & 0x3fffff) << 10);
- insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x400000) >> 22);
-}
-
-static void
-Slot_ae_format_Format_ae_slot0_33_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[1] & 0xffffffe) >> 1);
-}
-
-static void
-Slot_ae_format_Format_ae_slot0_33_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[1] = (insn[1] & ~0xffffffe) | ((slotbuf[0] & 0x7ffffff) << 1);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_get,
- Field_rbit2_Slot_inst_get,
- Field_rhi_Slot_inst_get,
- Field_t3_Slot_inst_get,
- Field_tbit2_Slot_inst_get,
- Field_tlo_Slot_inst_get,
- Field_w_Slot_inst_get,
- Field_y_Slot_inst_get,
- Field_x_Slot_inst_get,
- Field_t2_Slot_inst_get,
- Field_s2_Slot_inst_get,
- Field_r2_Slot_inst_get,
- Field_t4_Slot_inst_get,
- Field_s4_Slot_inst_get,
- Field_r4_Slot_inst_get,
- Field_t8_Slot_inst_get,
- Field_s8_Slot_inst_get,
- Field_r8_Slot_inst_get,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- Field_ae_r3_Slot_inst_get,
- Field_ae_s_non_samt_Slot_inst_get,
- Field_ae_s3_Slot_inst_get,
- Field_ae_r32_Slot_inst_get,
- Field_ae_samt_s_t_Slot_inst_get,
- Field_ae_r20_Slot_inst_get,
- Field_ae_r10_Slot_inst_get,
- Field_ae_s20_Slot_inst_get,
- Field_ae_fld_ohba_Slot_inst_get,
- Field_ae_fld_ohba2_Slot_inst_get,
- 0,
- Field_ftsf11_Slot_inst_get,
- Field_ftsf12_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst_get,
- Field_s3to1_Slot_inst_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_set,
- Field_rbit2_Slot_inst_set,
- Field_rhi_Slot_inst_set,
- Field_t3_Slot_inst_set,
- Field_tbit2_Slot_inst_set,
- Field_tlo_Slot_inst_set,
- Field_w_Slot_inst_set,
- Field_y_Slot_inst_set,
- Field_x_Slot_inst_set,
- Field_t2_Slot_inst_set,
- Field_s2_Slot_inst_set,
- Field_r2_Slot_inst_set,
- Field_t4_Slot_inst_set,
- Field_s4_Slot_inst_set,
- Field_r4_Slot_inst_set,
- Field_t8_Slot_inst_set,
- Field_s8_Slot_inst_set,
- Field_r8_Slot_inst_set,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- Field_ae_r3_Slot_inst_set,
- Field_ae_s_non_samt_Slot_inst_set,
- Field_ae_s3_Slot_inst_set,
- Field_ae_r32_Slot_inst_set,
- Field_ae_samt_s_t_Slot_inst_set,
- Field_ae_r20_Slot_inst_set,
- Field_ae_r10_Slot_inst_set,
- Field_ae_s20_Slot_inst_set,
- Field_ae_fld_ohba_Slot_inst_set,
- Field_ae_fld_ohba2_Slot_inst_set,
- 0,
- Field_ftsf11_Slot_inst_set,
- Field_ftsf12_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst_set,
- Field_s3to1_Slot_inst_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16a_get,
- Field_s2_Slot_inst16a_get,
- Field_r2_Slot_inst16a_get,
- Field_t4_Slot_inst16a_get,
- Field_s4_Slot_inst16a_get,
- Field_r4_Slot_inst16a_get,
- Field_t8_Slot_inst16a_get,
- Field_s8_Slot_inst16a_get,
- Field_r8_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_get,
- Field_s3to1_Slot_inst16a_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16a_set,
- Field_s2_Slot_inst16a_set,
- Field_r2_Slot_inst16a_set,
- Field_t4_Slot_inst16a_set,
- Field_s4_Slot_inst16a_set,
- Field_r4_Slot_inst16a_set,
- Field_t8_Slot_inst16a_set,
- Field_s8_Slot_inst16a_set,
- Field_r8_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16a_set,
- Field_s3to1_Slot_inst16a_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16b_get,
- Field_s2_Slot_inst16b_get,
- Field_r2_Slot_inst16b_get,
- Field_t4_Slot_inst16b_get,
- Field_s4_Slot_inst16b_get,
- Field_r4_Slot_inst16b_get,
- Field_t8_Slot_inst16b_get,
- Field_s8_Slot_inst16b_get,
- Field_r8_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
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- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_get,
- Field_s3to1_Slot_inst16b_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16b_set,
- Field_s2_Slot_inst16b_set,
- Field_r2_Slot_inst16b_set,
- Field_t4_Slot_inst16b_set,
- Field_s4_Slot_inst16b_set,
- Field_r4_Slot_inst16b_set,
- Field_t8_Slot_inst16b_set,
- Field_s8_Slot_inst16b_set,
- Field_r8_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
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- 0,
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- 0,
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- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_inst16b_set,
- Field_s3to1_Slot_inst16b_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_ae_slot1_get_field_fns[] = {
- Field_t_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot1_get,
- 0,
- Field_ae_r20_Slot_ae_slot1_get,
- Field_ae_r10_Slot_ae_slot1_get,
- Field_ae_s20_Slot_ae_slot1_get,
- 0,
- 0,
- Field_op0_s3_Slot_ae_slot1_get,
- Field_ftsf11_Slot_ae_slot1_get,
- Field_ftsf12_Slot_ae_slot1_get,
- Field_ftsf13_Slot_ae_slot1_get,
- Field_ftsf20ae_slot1_Slot_ae_slot1_get,
- Field_ftsf21ae_slot1_Slot_ae_slot1_get,
- Field_ftsf22ae_slot1_Slot_ae_slot1_get,
- Field_ftsf23ae_slot1_Slot_ae_slot1_get,
- Field_ftsf24ae_slot1_Slot_ae_slot1_get,
- Field_ftsf25ae_slot1_Slot_ae_slot1_get,
- Field_ftsf26ae_slot1_Slot_ae_slot1_get,
- Field_ftsf27ae_slot1_Slot_ae_slot1_get,
- Field_ftsf28ae_slot1_Slot_ae_slot1_get,
- Field_ftsf29ae_slot1_Slot_ae_slot1_get,
- Field_ftsf30ae_slot1_Slot_ae_slot1_get,
- Field_ftsf31ae_slot1_Slot_ae_slot1_get,
- Field_ftsf32ae_slot1_Slot_ae_slot1_get,
- Field_ftsf33ae_slot1_Slot_ae_slot1_get,
- Field_ftsf34ae_slot1_Slot_ae_slot1_get,
- Field_ftsf35ae_slot1_Slot_ae_slot1_get,
- Field_ftsf36ae_slot1_Slot_ae_slot1_get,
- Field_ftsf37ae_slot1_Slot_ae_slot1_get,
- Field_ftsf38ae_slot1_Slot_ae_slot1_get,
- Field_ftsf40ae_slot1_Slot_ae_slot1_get,
- Field_ftsf41ae_slot1_Slot_ae_slot1_get,
- Field_ftsf42ae_slot1_Slot_ae_slot1_get,
- Field_ftsf43ae_slot1_Slot_ae_slot1_get,
- Field_ftsf45ae_slot1_Slot_ae_slot1_get,
- Field_ftsf47ae_slot1_Slot_ae_slot1_get,
- Field_ftsf48ae_slot1_Slot_ae_slot1_get,
- Field_ftsf49ae_slot1_Slot_ae_slot1_get,
- Field_ftsf50ae_slot1_Slot_ae_slot1_get,
- Field_ftsf51ae_slot1_Slot_ae_slot1_get,
- Field_ftsf52ae_slot1_Slot_ae_slot1_get,
- Field_ftsf53ae_slot1_Slot_ae_slot1_get,
- Field_ftsf54ae_slot1_Slot_ae_slot1_get,
- Field_ftsf55_Slot_ae_slot1_get,
- Field_ftsf56ae_slot1_Slot_ae_slot1_get,
- Field_ftsf57ae_slot1_Slot_ae_slot1_get,
- Field_ftsf58ae_slot1_Slot_ae_slot1_get,
- Field_ftsf60ae_slot1_Slot_ae_slot1_get,
- Field_ftsf61_Slot_ae_slot1_get,
- Field_ftsf62ae_slot1_Slot_ae_slot1_get,
- Field_ftsf63ae_slot1_Slot_ae_slot1_get,
- Field_ftsf64ae_slot1_Slot_ae_slot1_get,
- Field_ftsf66ae_slot1_Slot_ae_slot1_get,
- Field_ftsf68ae_slot1_Slot_ae_slot1_get,
- Field_ftsf69ae_slot1_Slot_ae_slot1_get,
- Field_ftsf70ae_slot1_Slot_ae_slot1_get,
- Field_ftsf71ae_slot1_Slot_ae_slot1_get,
- Field_ftsf72ae_slot1_Slot_ae_slot1_get,
- Field_ftsf73ae_slot1_Slot_ae_slot1_get,
- Field_ftsf74ae_slot1_Slot_ae_slot1_get,
- Field_ftsf75ae_slot1_Slot_ae_slot1_get,
- Field_ftsf76ae_slot1_Slot_ae_slot1_get,
- Field_ftsf77ae_slot1_Slot_ae_slot1_get,
- Field_ftsf78ae_slot1_Slot_ae_slot1_get,
- Field_ftsf79ae_slot1_Slot_ae_slot1_get,
- Field_ftsf80ae_slot1_Slot_ae_slot1_get,
- Field_ftsf81ae_slot1_Slot_ae_slot1_get,
- Field_ftsf82ae_slot1_Slot_ae_slot1_get,
- Field_ftsf83ae_slot1_Slot_ae_slot1_get,
- Field_ftsf84ae_slot1_Slot_ae_slot1_get,
- Field_ftsf85ae_slot1_Slot_ae_slot1_get,
- Field_ftsf86ae_slot1_Slot_ae_slot1_get,
- Field_ftsf87ae_slot1_Slot_ae_slot1_get,
- Field_ftsf88ae_slot1_Slot_ae_slot1_get,
- Field_ftsf89ae_slot1_Slot_ae_slot1_get,
- Field_ftsf90ae_slot1_Slot_ae_slot1_get,
- Field_ftsf91_Slot_ae_slot1_get,
- Field_ftsf92ae_slot1_Slot_ae_slot1_get,
- Field_ftsf93ae_slot1_Slot_ae_slot1_get,
- Field_ftsf94ae_slot1_Slot_ae_slot1_get,
- Field_ftsf96ae_slot1_Slot_ae_slot1_get,
- Field_ftsf97ae_slot1_Slot_ae_slot1_get,
- Field_ftsf99ae_slot1_Slot_ae_slot1_get,
- Field_ftsf101ae_slot1_Slot_ae_slot1_get,
- Field_ftsf102ae_slot1_Slot_ae_slot1_get,
- Field_ftsf103ae_slot1_Slot_ae_slot1_get,
- Field_ftsf106ae_slot1_Slot_ae_slot1_get,
- Field_ftsf107ae_slot1_Slot_ae_slot1_get,
- Field_ftsf108ae_slot1_Slot_ae_slot1_get,
- Field_ftsf109ae_slot1_Slot_ae_slot1_get,
- Field_ftsf110ae_slot1_Slot_ae_slot1_get,
- Field_ftsf111ae_slot1_Slot_ae_slot1_get,
- Field_ftsf112ae_slot1_Slot_ae_slot1_get,
- Field_ftsf113ae_slot1_Slot_ae_slot1_get,
- Field_ftsf114ae_slot1_Slot_ae_slot1_get,
- Field_ftsf115ae_slot1_Slot_ae_slot1_get,
- Field_ftsf116ae_slot1_Slot_ae_slot1_get,
- Field_ftsf117ae_slot1_Slot_ae_slot1_get,
- Field_ftsf118ae_slot1_Slot_ae_slot1_get,
- Field_ftsf120ae_slot1_Slot_ae_slot1_get,
- Field_ftsf121ae_slot1_Slot_ae_slot1_get,
- Field_ftsf123ae_slot1_Slot_ae_slot1_get,
- Field_ftsf124ae_slot1_Slot_ae_slot1_get,
- Field_ftsf125ae_slot1_Slot_ae_slot1_get,
- Field_ftsf126ae_slot1_Slot_ae_slot1_get,
- Field_ftsf127ae_slot1_Slot_ae_slot1_get,
- Field_ftsf128ae_slot1_Slot_ae_slot1_get,
- Field_ftsf129ae_slot1_Slot_ae_slot1_get,
- Field_ftsf130ae_slot1_Slot_ae_slot1_get,
- Field_ftsf131ae_slot1_Slot_ae_slot1_get,
- Field_ftsf132ae_slot1_Slot_ae_slot1_get,
- Field_ftsf133ae_slot1_Slot_ae_slot1_get,
- Field_ftsf134ae_slot1_Slot_ae_slot1_get,
- Field_ftsf135ae_slot1_Slot_ae_slot1_get,
- Field_ftsf136ae_slot1_Slot_ae_slot1_get,
- Field_ftsf137ae_slot1_Slot_ae_slot1_get,
- Field_ftsf138ae_slot1_Slot_ae_slot1_get,
- Field_ftsf139ae_slot1_Slot_ae_slot1_get,
- Field_ftsf140ae_slot1_Slot_ae_slot1_get,
- Field_ftsf141ae_slot1_Slot_ae_slot1_get,
- Field_ftsf142ae_slot1_Slot_ae_slot1_get,
- Field_ftsf143ae_slot1_Slot_ae_slot1_get,
- Field_ftsf144ae_slot1_Slot_ae_slot1_get,
- Field_ftsf145ae_slot1_Slot_ae_slot1_get,
- Field_ftsf146ae_slot1_Slot_ae_slot1_get,
- Field_ftsf147ae_slot1_Slot_ae_slot1_get,
- Field_ftsf148ae_slot1_Slot_ae_slot1_get,
- Field_ftsf149ae_slot1_Slot_ae_slot1_get,
- Field_ftsf150ae_slot1_Slot_ae_slot1_get,
- Field_ftsf151ae_slot1_Slot_ae_slot1_get,
- Field_ftsf152ae_slot1_Slot_ae_slot1_get,
- Field_ftsf153ae_slot1_Slot_ae_slot1_get,
- Field_ftsf154ae_slot1_Slot_ae_slot1_get,
- Field_ftsf155ae_slot1_Slot_ae_slot1_get,
- Field_ftsf156ae_slot1_Slot_ae_slot1_get,
- Field_ftsf157ae_slot1_Slot_ae_slot1_get,
- Field_ftsf158ae_slot1_Slot_ae_slot1_get,
- Field_ftsf159ae_slot1_Slot_ae_slot1_get,
- Field_ftsf160ae_slot1_Slot_ae_slot1_get,
- Field_ftsf161ae_slot1_Slot_ae_slot1_get,
- Field_ftsf162ae_slot1_Slot_ae_slot1_get,
- Field_ftsf163ae_slot1_Slot_ae_slot1_get,
- Field_ftsf164ae_slot1_Slot_ae_slot1_get,
- Field_ftsf165ae_slot1_Slot_ae_slot1_get,
- Field_ftsf166ae_slot1_Slot_ae_slot1_get,
- Field_ftsf167ae_slot1_Slot_ae_slot1_get,
- Field_ftsf168ae_slot1_Slot_ae_slot1_get,
- Field_ftsf169ae_slot1_Slot_ae_slot1_get,
- Field_ftsf170ae_slot1_Slot_ae_slot1_get,
- Field_ftsf171ae_slot1_Slot_ae_slot1_get,
- Field_ftsf172ae_slot1_Slot_ae_slot1_get,
- Field_ftsf173ae_slot1_Slot_ae_slot1_get,
- Field_ftsf174ae_slot1_Slot_ae_slot1_get,
- Field_ftsf175ae_slot1_Slot_ae_slot1_get,
- Field_ftsf176ae_slot1_Slot_ae_slot1_get,
- Field_ftsf177ae_slot1_Slot_ae_slot1_get,
- Field_ftsf178ae_slot1_Slot_ae_slot1_get,
- Field_ftsf179ae_slot1_Slot_ae_slot1_get,
- Field_ftsf180ae_slot1_Slot_ae_slot1_get,
- Field_ftsf181ae_slot1_Slot_ae_slot1_get,
- Field_ftsf182ae_slot1_Slot_ae_slot1_get,
- Field_ftsf183ae_slot1_Slot_ae_slot1_get,
- Field_ftsf184ae_slot1_Slot_ae_slot1_get,
- Field_ftsf185ae_slot1_Slot_ae_slot1_get,
- Field_ftsf186ae_slot1_Slot_ae_slot1_get,
- Field_ftsf187ae_slot1_Slot_ae_slot1_get,
- Field_ftsf188ae_slot1_Slot_ae_slot1_get,
- Field_ftsf189ae_slot1_Slot_ae_slot1_get,
- Field_ftsf190ae_slot1_Slot_ae_slot1_get,
- Field_ftsf191ae_slot1_Slot_ae_slot1_get,
- Field_ftsf192ae_slot1_Slot_ae_slot1_get,
- Field_ftsf193ae_slot1_Slot_ae_slot1_get,
- Field_ftsf194ae_slot1_Slot_ae_slot1_get,
- Field_ftsf195ae_slot1_Slot_ae_slot1_get,
- Field_ftsf196ae_slot1_Slot_ae_slot1_get,
- Field_ftsf197ae_slot1_Slot_ae_slot1_get,
- Field_ftsf198ae_slot1_Slot_ae_slot1_get,
- Field_ftsf199ae_slot1_Slot_ae_slot1_get,
- Field_ftsf200ae_slot1_Slot_ae_slot1_get,
- Field_ftsf201ae_slot1_Slot_ae_slot1_get,
- Field_ftsf202ae_slot1_Slot_ae_slot1_get,
- Field_ftsf203ae_slot1_Slot_ae_slot1_get,
- Field_ftsf204ae_slot1_Slot_ae_slot1_get,
- Field_ftsf205ae_slot1_Slot_ae_slot1_get,
- Field_ftsf206ae_slot1_Slot_ae_slot1_get,
- Field_ftsf207ae_slot1_Slot_ae_slot1_get,
- Field_ftsf208ae_slot1_Slot_ae_slot1_get,
- Field_ftsf210ae_slot1_Slot_ae_slot1_get,
- Field_ftsf333ae_slot1_Slot_ae_slot1_get,
- Field_ftsf334ae_slot1_Slot_ae_slot1_get,
- Field_ftsf335_Slot_ae_slot1_get,
- Field_ftsf336ae_slot1_Slot_ae_slot1_get,
- Field_ftsf337ae_slot1_Slot_ae_slot1_get,
- Field_ftsf339ae_slot1_Slot_ae_slot1_get,
- Field_ftsf340ae_slot1_Slot_ae_slot1_get,
- Field_ftsf341ae_slot1_Slot_ae_slot1_get,
- Field_ftsf342ae_slot1_Slot_ae_slot1_get,
- Field_ftsf343ae_slot1_Slot_ae_slot1_get,
- Field_ftsf344ae_slot1_Slot_ae_slot1_get,
- Field_ftsf345ae_slot1_Slot_ae_slot1_get,
- Field_ftsf347ae_slot1_Slot_ae_slot1_get,
- Field_ftsf348ae_slot1_Slot_ae_slot1_get,
- Field_ftsf349ae_slot1_Slot_ae_slot1_get,
- Field_ftsf350ae_slot1_Slot_ae_slot1_get,
- Field_ftsf351_Slot_ae_slot1_get,
- Field_ftsf352ae_slot1_Slot_ae_slot1_get,
- Field_ftsf354ae_slot1_Slot_ae_slot1_get,
- Field_ftsf355ae_slot1_Slot_ae_slot1_get,
- Field_ftsf356ae_slot1_Slot_ae_slot1_get,
- Field_ftsf357ae_slot1_Slot_ae_slot1_get,
- Field_ftsf358ae_slot1_Slot_ae_slot1_get,
- Field_ftsf359ae_slot1_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_mul32x24fld_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s3_s3_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld19_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld22_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld24_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld65_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld66_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld68_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld69_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld74_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld79_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld88_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld90_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld91_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get,
- Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_ae_slot1_set_field_fns[] = {
- Field_t_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot1_set,
- 0,
- Field_ae_r20_Slot_ae_slot1_set,
- Field_ae_r10_Slot_ae_slot1_set,
- Field_ae_s20_Slot_ae_slot1_set,
- 0,
- 0,
- Field_op0_s3_Slot_ae_slot1_set,
- Field_ftsf11_Slot_ae_slot1_set,
- Field_ftsf12_Slot_ae_slot1_set,
- Field_ftsf13_Slot_ae_slot1_set,
- Field_ftsf20ae_slot1_Slot_ae_slot1_set,
- Field_ftsf21ae_slot1_Slot_ae_slot1_set,
- Field_ftsf22ae_slot1_Slot_ae_slot1_set,
- Field_ftsf23ae_slot1_Slot_ae_slot1_set,
- Field_ftsf24ae_slot1_Slot_ae_slot1_set,
- Field_ftsf25ae_slot1_Slot_ae_slot1_set,
- Field_ftsf26ae_slot1_Slot_ae_slot1_set,
- Field_ftsf27ae_slot1_Slot_ae_slot1_set,
- Field_ftsf28ae_slot1_Slot_ae_slot1_set,
- Field_ftsf29ae_slot1_Slot_ae_slot1_set,
- Field_ftsf30ae_slot1_Slot_ae_slot1_set,
- Field_ftsf31ae_slot1_Slot_ae_slot1_set,
- Field_ftsf32ae_slot1_Slot_ae_slot1_set,
- Field_ftsf33ae_slot1_Slot_ae_slot1_set,
- Field_ftsf34ae_slot1_Slot_ae_slot1_set,
- Field_ftsf35ae_slot1_Slot_ae_slot1_set,
- Field_ftsf36ae_slot1_Slot_ae_slot1_set,
- Field_ftsf37ae_slot1_Slot_ae_slot1_set,
- Field_ftsf38ae_slot1_Slot_ae_slot1_set,
- Field_ftsf40ae_slot1_Slot_ae_slot1_set,
- Field_ftsf41ae_slot1_Slot_ae_slot1_set,
- Field_ftsf42ae_slot1_Slot_ae_slot1_set,
- Field_ftsf43ae_slot1_Slot_ae_slot1_set,
- Field_ftsf45ae_slot1_Slot_ae_slot1_set,
- Field_ftsf47ae_slot1_Slot_ae_slot1_set,
- Field_ftsf48ae_slot1_Slot_ae_slot1_set,
- Field_ftsf49ae_slot1_Slot_ae_slot1_set,
- Field_ftsf50ae_slot1_Slot_ae_slot1_set,
- Field_ftsf51ae_slot1_Slot_ae_slot1_set,
- Field_ftsf52ae_slot1_Slot_ae_slot1_set,
- Field_ftsf53ae_slot1_Slot_ae_slot1_set,
- Field_ftsf54ae_slot1_Slot_ae_slot1_set,
- Field_ftsf55_Slot_ae_slot1_set,
- Field_ftsf56ae_slot1_Slot_ae_slot1_set,
- Field_ftsf57ae_slot1_Slot_ae_slot1_set,
- Field_ftsf58ae_slot1_Slot_ae_slot1_set,
- Field_ftsf60ae_slot1_Slot_ae_slot1_set,
- Field_ftsf61_Slot_ae_slot1_set,
- Field_ftsf62ae_slot1_Slot_ae_slot1_set,
- Field_ftsf63ae_slot1_Slot_ae_slot1_set,
- Field_ftsf64ae_slot1_Slot_ae_slot1_set,
- Field_ftsf66ae_slot1_Slot_ae_slot1_set,
- Field_ftsf68ae_slot1_Slot_ae_slot1_set,
- Field_ftsf69ae_slot1_Slot_ae_slot1_set,
- Field_ftsf70ae_slot1_Slot_ae_slot1_set,
- Field_ftsf71ae_slot1_Slot_ae_slot1_set,
- Field_ftsf72ae_slot1_Slot_ae_slot1_set,
- Field_ftsf73ae_slot1_Slot_ae_slot1_set,
- Field_ftsf74ae_slot1_Slot_ae_slot1_set,
- Field_ftsf75ae_slot1_Slot_ae_slot1_set,
- Field_ftsf76ae_slot1_Slot_ae_slot1_set,
- Field_ftsf77ae_slot1_Slot_ae_slot1_set,
- Field_ftsf78ae_slot1_Slot_ae_slot1_set,
- Field_ftsf79ae_slot1_Slot_ae_slot1_set,
- Field_ftsf80ae_slot1_Slot_ae_slot1_set,
- Field_ftsf81ae_slot1_Slot_ae_slot1_set,
- Field_ftsf82ae_slot1_Slot_ae_slot1_set,
- Field_ftsf83ae_slot1_Slot_ae_slot1_set,
- Field_ftsf84ae_slot1_Slot_ae_slot1_set,
- Field_ftsf85ae_slot1_Slot_ae_slot1_set,
- Field_ftsf86ae_slot1_Slot_ae_slot1_set,
- Field_ftsf87ae_slot1_Slot_ae_slot1_set,
- Field_ftsf88ae_slot1_Slot_ae_slot1_set,
- Field_ftsf89ae_slot1_Slot_ae_slot1_set,
- Field_ftsf90ae_slot1_Slot_ae_slot1_set,
- Field_ftsf91_Slot_ae_slot1_set,
- Field_ftsf92ae_slot1_Slot_ae_slot1_set,
- Field_ftsf93ae_slot1_Slot_ae_slot1_set,
- Field_ftsf94ae_slot1_Slot_ae_slot1_set,
- Field_ftsf96ae_slot1_Slot_ae_slot1_set,
- Field_ftsf97ae_slot1_Slot_ae_slot1_set,
- Field_ftsf99ae_slot1_Slot_ae_slot1_set,
- Field_ftsf101ae_slot1_Slot_ae_slot1_set,
- Field_ftsf102ae_slot1_Slot_ae_slot1_set,
- Field_ftsf103ae_slot1_Slot_ae_slot1_set,
- Field_ftsf106ae_slot1_Slot_ae_slot1_set,
- Field_ftsf107ae_slot1_Slot_ae_slot1_set,
- Field_ftsf108ae_slot1_Slot_ae_slot1_set,
- Field_ftsf109ae_slot1_Slot_ae_slot1_set,
- Field_ftsf110ae_slot1_Slot_ae_slot1_set,
- Field_ftsf111ae_slot1_Slot_ae_slot1_set,
- Field_ftsf112ae_slot1_Slot_ae_slot1_set,
- Field_ftsf113ae_slot1_Slot_ae_slot1_set,
- Field_ftsf114ae_slot1_Slot_ae_slot1_set,
- Field_ftsf115ae_slot1_Slot_ae_slot1_set,
- Field_ftsf116ae_slot1_Slot_ae_slot1_set,
- Field_ftsf117ae_slot1_Slot_ae_slot1_set,
- Field_ftsf118ae_slot1_Slot_ae_slot1_set,
- Field_ftsf120ae_slot1_Slot_ae_slot1_set,
- Field_ftsf121ae_slot1_Slot_ae_slot1_set,
- Field_ftsf123ae_slot1_Slot_ae_slot1_set,
- Field_ftsf124ae_slot1_Slot_ae_slot1_set,
- Field_ftsf125ae_slot1_Slot_ae_slot1_set,
- Field_ftsf126ae_slot1_Slot_ae_slot1_set,
- Field_ftsf127ae_slot1_Slot_ae_slot1_set,
- Field_ftsf128ae_slot1_Slot_ae_slot1_set,
- Field_ftsf129ae_slot1_Slot_ae_slot1_set,
- Field_ftsf130ae_slot1_Slot_ae_slot1_set,
- Field_ftsf131ae_slot1_Slot_ae_slot1_set,
- Field_ftsf132ae_slot1_Slot_ae_slot1_set,
- Field_ftsf133ae_slot1_Slot_ae_slot1_set,
- Field_ftsf134ae_slot1_Slot_ae_slot1_set,
- Field_ftsf135ae_slot1_Slot_ae_slot1_set,
- Field_ftsf136ae_slot1_Slot_ae_slot1_set,
- Field_ftsf137ae_slot1_Slot_ae_slot1_set,
- Field_ftsf138ae_slot1_Slot_ae_slot1_set,
- Field_ftsf139ae_slot1_Slot_ae_slot1_set,
- Field_ftsf140ae_slot1_Slot_ae_slot1_set,
- Field_ftsf141ae_slot1_Slot_ae_slot1_set,
- Field_ftsf142ae_slot1_Slot_ae_slot1_set,
- Field_ftsf143ae_slot1_Slot_ae_slot1_set,
- Field_ftsf144ae_slot1_Slot_ae_slot1_set,
- Field_ftsf145ae_slot1_Slot_ae_slot1_set,
- Field_ftsf146ae_slot1_Slot_ae_slot1_set,
- Field_ftsf147ae_slot1_Slot_ae_slot1_set,
- Field_ftsf148ae_slot1_Slot_ae_slot1_set,
- Field_ftsf149ae_slot1_Slot_ae_slot1_set,
- Field_ftsf150ae_slot1_Slot_ae_slot1_set,
- Field_ftsf151ae_slot1_Slot_ae_slot1_set,
- Field_ftsf152ae_slot1_Slot_ae_slot1_set,
- Field_ftsf153ae_slot1_Slot_ae_slot1_set,
- Field_ftsf154ae_slot1_Slot_ae_slot1_set,
- Field_ftsf155ae_slot1_Slot_ae_slot1_set,
- Field_ftsf156ae_slot1_Slot_ae_slot1_set,
- Field_ftsf157ae_slot1_Slot_ae_slot1_set,
- Field_ftsf158ae_slot1_Slot_ae_slot1_set,
- Field_ftsf159ae_slot1_Slot_ae_slot1_set,
- Field_ftsf160ae_slot1_Slot_ae_slot1_set,
- Field_ftsf161ae_slot1_Slot_ae_slot1_set,
- Field_ftsf162ae_slot1_Slot_ae_slot1_set,
- Field_ftsf163ae_slot1_Slot_ae_slot1_set,
- Field_ftsf164ae_slot1_Slot_ae_slot1_set,
- Field_ftsf165ae_slot1_Slot_ae_slot1_set,
- Field_ftsf166ae_slot1_Slot_ae_slot1_set,
- Field_ftsf167ae_slot1_Slot_ae_slot1_set,
- Field_ftsf168ae_slot1_Slot_ae_slot1_set,
- Field_ftsf169ae_slot1_Slot_ae_slot1_set,
- Field_ftsf170ae_slot1_Slot_ae_slot1_set,
- Field_ftsf171ae_slot1_Slot_ae_slot1_set,
- Field_ftsf172ae_slot1_Slot_ae_slot1_set,
- Field_ftsf173ae_slot1_Slot_ae_slot1_set,
- Field_ftsf174ae_slot1_Slot_ae_slot1_set,
- Field_ftsf175ae_slot1_Slot_ae_slot1_set,
- Field_ftsf176ae_slot1_Slot_ae_slot1_set,
- Field_ftsf177ae_slot1_Slot_ae_slot1_set,
- Field_ftsf178ae_slot1_Slot_ae_slot1_set,
- Field_ftsf179ae_slot1_Slot_ae_slot1_set,
- Field_ftsf180ae_slot1_Slot_ae_slot1_set,
- Field_ftsf181ae_slot1_Slot_ae_slot1_set,
- Field_ftsf182ae_slot1_Slot_ae_slot1_set,
- Field_ftsf183ae_slot1_Slot_ae_slot1_set,
- Field_ftsf184ae_slot1_Slot_ae_slot1_set,
- Field_ftsf185ae_slot1_Slot_ae_slot1_set,
- Field_ftsf186ae_slot1_Slot_ae_slot1_set,
- Field_ftsf187ae_slot1_Slot_ae_slot1_set,
- Field_ftsf188ae_slot1_Slot_ae_slot1_set,
- Field_ftsf189ae_slot1_Slot_ae_slot1_set,
- Field_ftsf190ae_slot1_Slot_ae_slot1_set,
- Field_ftsf191ae_slot1_Slot_ae_slot1_set,
- Field_ftsf192ae_slot1_Slot_ae_slot1_set,
- Field_ftsf193ae_slot1_Slot_ae_slot1_set,
- Field_ftsf194ae_slot1_Slot_ae_slot1_set,
- Field_ftsf195ae_slot1_Slot_ae_slot1_set,
- Field_ftsf196ae_slot1_Slot_ae_slot1_set,
- Field_ftsf197ae_slot1_Slot_ae_slot1_set,
- Field_ftsf198ae_slot1_Slot_ae_slot1_set,
- Field_ftsf199ae_slot1_Slot_ae_slot1_set,
- Field_ftsf200ae_slot1_Slot_ae_slot1_set,
- Field_ftsf201ae_slot1_Slot_ae_slot1_set,
- Field_ftsf202ae_slot1_Slot_ae_slot1_set,
- Field_ftsf203ae_slot1_Slot_ae_slot1_set,
- Field_ftsf204ae_slot1_Slot_ae_slot1_set,
- Field_ftsf205ae_slot1_Slot_ae_slot1_set,
- Field_ftsf206ae_slot1_Slot_ae_slot1_set,
- Field_ftsf207ae_slot1_Slot_ae_slot1_set,
- Field_ftsf208ae_slot1_Slot_ae_slot1_set,
- Field_ftsf210ae_slot1_Slot_ae_slot1_set,
- Field_ftsf333ae_slot1_Slot_ae_slot1_set,
- Field_ftsf334ae_slot1_Slot_ae_slot1_set,
- Field_ftsf335_Slot_ae_slot1_set,
- Field_ftsf336ae_slot1_Slot_ae_slot1_set,
- Field_ftsf337ae_slot1_Slot_ae_slot1_set,
- Field_ftsf339ae_slot1_Slot_ae_slot1_set,
- Field_ftsf340ae_slot1_Slot_ae_slot1_set,
- Field_ftsf341ae_slot1_Slot_ae_slot1_set,
- Field_ftsf342ae_slot1_Slot_ae_slot1_set,
- Field_ftsf343ae_slot1_Slot_ae_slot1_set,
- Field_ftsf344ae_slot1_Slot_ae_slot1_set,
- Field_ftsf345ae_slot1_Slot_ae_slot1_set,
- Field_ftsf347ae_slot1_Slot_ae_slot1_set,
- Field_ftsf348ae_slot1_Slot_ae_slot1_set,
- Field_ftsf349ae_slot1_Slot_ae_slot1_set,
- Field_ftsf350ae_slot1_Slot_ae_slot1_set,
- Field_ftsf351_Slot_ae_slot1_set,
- Field_ftsf352ae_slot1_Slot_ae_slot1_set,
- Field_ftsf354ae_slot1_Slot_ae_slot1_set,
- Field_ftsf355ae_slot1_Slot_ae_slot1_set,
- Field_ftsf356ae_slot1_Slot_ae_slot1_set,
- Field_ftsf357ae_slot1_Slot_ae_slot1_set,
- Field_ftsf358ae_slot1_Slot_ae_slot1_set,
- Field_ftsf359ae_slot1_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_mul32x24fld_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s3_s3_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld19_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld22_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld24_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld65_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld66_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld68_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld69_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld74_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld79_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld88_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld90_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld91_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set,
- Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_ae_slot0_get_field_fns[] = {
- Field_t_Slot_ae_slot0_get,
- 0,
- Field_bbi_Slot_ae_slot0_get,
- Field_imm12_Slot_ae_slot0_get,
- Field_imm8_Slot_ae_slot0_get,
- Field_s_Slot_ae_slot0_get,
- Field_imm12b_Slot_ae_slot0_get,
- Field_imm16_Slot_ae_slot0_get,
- 0,
- 0,
- Field_offset_Slot_ae_slot0_get,
- 0,
- 0,
- Field_op2_Slot_ae_slot0_get,
- Field_r_Slot_ae_slot0_get,
- 0,
- 0,
- Field_sae_Slot_ae_slot0_get,
- Field_sal_Slot_ae_slot0_get,
- Field_sargt_Slot_ae_slot0_get,
- 0,
- Field_sas_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_s4_Slot_ae_slot0_get,
- 0,
- 0,
- Field_s8_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot0_get,
- Field_ae_samt_s_t_Slot_ae_slot0_get,
- Field_ae_r20_Slot_ae_slot0_get,
- Field_ae_r10_Slot_ae_slot0_get,
- Field_ae_s20_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- Field_ftsf11_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s4_Slot_ae_slot0_get,
- Field_ftsf211ae_slot0_Slot_ae_slot0_get,
- Field_ftsf212ae_slot0_Slot_ae_slot0_get,
- Field_ftsf213ae_slot0_Slot_ae_slot0_get,
- Field_ftsf214ae_slot0_Slot_ae_slot0_get,
- Field_ftsf215ae_slot0_Slot_ae_slot0_get,
- Field_ftsf217ae_slot0_Slot_ae_slot0_get,
- Field_ftsf218ae_slot0_Slot_ae_slot0_get,
- Field_ftsf219ae_slot0_Slot_ae_slot0_get,
- Field_ftsf220ae_slot0_Slot_ae_slot0_get,
- Field_ftsf221ae_slot0_Slot_ae_slot0_get,
- Field_ftsf222ae_slot0_Slot_ae_slot0_get,
- Field_ftsf223ae_slot0_Slot_ae_slot0_get,
- Field_ftsf224ae_slot0_Slot_ae_slot0_get,
- Field_ftsf225ae_slot0_Slot_ae_slot0_get,
- Field_ftsf226ae_slot0_Slot_ae_slot0_get,
- Field_ftsf227ae_slot0_Slot_ae_slot0_get,
- Field_ftsf228ae_slot0_Slot_ae_slot0_get,
- Field_ftsf229ae_slot0_Slot_ae_slot0_get,
- Field_ftsf230ae_slot0_Slot_ae_slot0_get,
- Field_ftsf231ae_slot0_Slot_ae_slot0_get,
- Field_ftsf232ae_slot0_Slot_ae_slot0_get,
- Field_ftsf233ae_slot0_Slot_ae_slot0_get,
- Field_ftsf234ae_slot0_Slot_ae_slot0_get,
- Field_ftsf235ae_slot0_Slot_ae_slot0_get,
- Field_ftsf236ae_slot0_Slot_ae_slot0_get,
- Field_ftsf237ae_slot0_Slot_ae_slot0_get,
- Field_ftsf238ae_slot0_Slot_ae_slot0_get,
- Field_ftsf239ae_slot0_Slot_ae_slot0_get,
- Field_ftsf240ae_slot0_Slot_ae_slot0_get,
- Field_ftsf241ae_slot0_Slot_ae_slot0_get,
- Field_ftsf242ae_slot0_Slot_ae_slot0_get,
- Field_ftsf243ae_slot0_Slot_ae_slot0_get,
- Field_ftsf244ae_slot0_Slot_ae_slot0_get,
- Field_ftsf245ae_slot0_Slot_ae_slot0_get,
- Field_ftsf246ae_slot0_Slot_ae_slot0_get,
- Field_ftsf247ae_slot0_Slot_ae_slot0_get,
- Field_ftsf248ae_slot0_Slot_ae_slot0_get,
- Field_ftsf249ae_slot0_Slot_ae_slot0_get,
- Field_ftsf250ae_slot0_Slot_ae_slot0_get,
- Field_ftsf251ae_slot0_Slot_ae_slot0_get,
- Field_ftsf252ae_slot0_Slot_ae_slot0_get,
- Field_ftsf253ae_slot0_Slot_ae_slot0_get,
- Field_ftsf254ae_slot0_Slot_ae_slot0_get,
- Field_ftsf255ae_slot0_Slot_ae_slot0_get,
- Field_ftsf256ae_slot0_Slot_ae_slot0_get,
- Field_ftsf257ae_slot0_Slot_ae_slot0_get,
- Field_ftsf258ae_slot0_Slot_ae_slot0_get,
- Field_ftsf259ae_slot0_Slot_ae_slot0_get,
- Field_ftsf260ae_slot0_Slot_ae_slot0_get,
- Field_ftsf261ae_slot0_Slot_ae_slot0_get,
- Field_ftsf262ae_slot0_Slot_ae_slot0_get,
- Field_ftsf263ae_slot0_Slot_ae_slot0_get,
- Field_ftsf264ae_slot0_Slot_ae_slot0_get,
- Field_ftsf265ae_slot0_Slot_ae_slot0_get,
- Field_ftsf266ae_slot0_Slot_ae_slot0_get,
- Field_ftsf267ae_slot0_Slot_ae_slot0_get,
- Field_ftsf268ae_slot0_Slot_ae_slot0_get,
- Field_ftsf269ae_slot0_Slot_ae_slot0_get,
- Field_ftsf270ae_slot0_Slot_ae_slot0_get,
- Field_ftsf271ae_slot0_Slot_ae_slot0_get,
- Field_ftsf272ae_slot0_Slot_ae_slot0_get,
- Field_ftsf273ae_slot0_Slot_ae_slot0_get,
- Field_ftsf274ae_slot0_Slot_ae_slot0_get,
- Field_ftsf275ae_slot0_Slot_ae_slot0_get,
- Field_ftsf276ae_slot0_Slot_ae_slot0_get,
- Field_ftsf277ae_slot0_Slot_ae_slot0_get,
- Field_ftsf278ae_slot0_Slot_ae_slot0_get,
- Field_ftsf279ae_slot0_Slot_ae_slot0_get,
- Field_ftsf280_Slot_ae_slot0_get,
- Field_ftsf281ae_slot0_Slot_ae_slot0_get,
- Field_ftsf282ae_slot0_Slot_ae_slot0_get,
- Field_ftsf284ae_slot0_Slot_ae_slot0_get,
- Field_ftsf285ae_slot0_Slot_ae_slot0_get,
- Field_ftsf287ae_slot0_Slot_ae_slot0_get,
- Field_ftsf288_Slot_ae_slot0_get,
- Field_ftsf289ae_slot0_Slot_ae_slot0_get,
- Field_ftsf290ae_slot0_Slot_ae_slot0_get,
- Field_ftsf291ae_slot0_Slot_ae_slot0_get,
- Field_ftsf292ae_slot0_Slot_ae_slot0_get,
- Field_ftsf293ae_slot0_Slot_ae_slot0_get,
- Field_ftsf294ae_slot0_Slot_ae_slot0_get,
- Field_ftsf295ae_slot0_Slot_ae_slot0_get,
- Field_ftsf296ae_slot0_Slot_ae_slot0_get,
- Field_ftsf297ae_slot0_Slot_ae_slot0_get,
- Field_ftsf298ae_slot0_Slot_ae_slot0_get,
- Field_ftsf300ae_slot0_Slot_ae_slot0_get,
- Field_ftsf302ae_slot0_Slot_ae_slot0_get,
- Field_ftsf304ae_slot0_Slot_ae_slot0_get,
- Field_ftsf305ae_slot0_Slot_ae_slot0_get,
- Field_ftsf306ae_slot0_Slot_ae_slot0_get,
- Field_ftsf307ae_slot0_Slot_ae_slot0_get,
- Field_ftsf308ae_slot0_Slot_ae_slot0_get,
- Field_ftsf309_Slot_ae_slot0_get,
- Field_ftsf310ae_slot0_Slot_ae_slot0_get,
- Field_ftsf311ae_slot0_Slot_ae_slot0_get,
- Field_ftsf312ae_slot0_Slot_ae_slot0_get,
- Field_ftsf313ae_slot0_Slot_ae_slot0_get,
- Field_ftsf314ae_slot0_Slot_ae_slot0_get,
- Field_ftsf315_Slot_ae_slot0_get,
- Field_ftsf316ae_slot0_Slot_ae_slot0_get,
- Field_ftsf317ae_slot0_Slot_ae_slot0_get,
- Field_ftsf319ae_slot0_Slot_ae_slot0_get,
- Field_ftsf320ae_slot0_Slot_ae_slot0_get,
- Field_ftsf322ae_slot0_Slot_ae_slot0_get,
- Field_ftsf323ae_slot0_Slot_ae_slot0_get,
- Field_ftsf324ae_slot0_Slot_ae_slot0_get,
- Field_ftsf325ae_slot0_Slot_ae_slot0_get,
- Field_ftsf326ae_slot0_Slot_ae_slot0_get,
- Field_ftsf327ae_slot0_Slot_ae_slot0_get,
- Field_ftsf328ae_slot0_Slot_ae_slot0_get,
- Field_ftsf329ae_slot0_Slot_ae_slot0_get,
- Field_ftsf360ae_slot0_Slot_ae_slot0_get,
- Field_ftsf361ae_slot0_Slot_ae_slot0_get,
- Field_ftsf362_Slot_ae_slot0_get,
- Field_ftsf363ae_slot0_Slot_ae_slot0_get,
- Field_ftsf364ae_slot0_Slot_ae_slot0_get,
- Field_ftsf366ae_slot0_Slot_ae_slot0_get,
- Field_ftsf368ae_slot0_Slot_ae_slot0_get,
- Field_ftsf370ae_slot0_Slot_ae_slot0_get,
- Field_ftsf373ae_slot0_Slot_ae_slot0_get,
- Field_ftsf376ae_slot0_Slot_ae_slot0_get,
- Field_ftsf378ae_slot0_Slot_ae_slot0_get,
- Field_ftsf379ae_slot0_Slot_ae_slot0_get,
- Field_ftsf382ae_slot0_Slot_ae_slot0_get,
- Field_ftsf383ae_slot0_Slot_ae_slot0_get,
- Field_ftsf384ae_slot0_Slot_ae_slot0_get,
- Field_ftsf386ae_slot0_Slot_ae_slot0_get,
- Field_ftsf387ae_slot0_Slot_ae_slot0_get,
- Field_ftsf388ae_slot0_Slot_ae_slot0_get,
- Field_ftsf389ae_slot0_Slot_ae_slot0_get,
- 0,
- Field_op0_s4_s4_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld37_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld46_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld47_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld52_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld121_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld123_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get,
- Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get,
- Field_op0_s4_s4_s4_Slot_ae_slot0_get,
- Field_combined1e9fefee_fld96_Slot_ae_slot0_get,
- Field_combined1e9fefee_fld98_Slot_ae_slot0_get,
- Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get,
- Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get,
- Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get,
- Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_ae_slot0_get,
- Field_s3to1_Slot_ae_slot0_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_ae_slot0_set_field_fns[] = {
- Field_t_Slot_ae_slot0_set,
- 0,
- Field_bbi_Slot_ae_slot0_set,
- Field_imm12_Slot_ae_slot0_set,
- Field_imm8_Slot_ae_slot0_set,
- Field_s_Slot_ae_slot0_set,
- Field_imm12b_Slot_ae_slot0_set,
- Field_imm16_Slot_ae_slot0_set,
- 0,
- 0,
- Field_offset_Slot_ae_slot0_set,
- 0,
- 0,
- Field_op2_Slot_ae_slot0_set,
- Field_r_Slot_ae_slot0_set,
- 0,
- 0,
- Field_sae_Slot_ae_slot0_set,
- Field_sal_Slot_ae_slot0_set,
- Field_sargt_Slot_ae_slot0_set,
- 0,
- Field_sas_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_s4_Slot_ae_slot0_set,
- 0,
- 0,
- Field_s8_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot0_set,
- Field_ae_samt_s_t_Slot_ae_slot0_set,
- Field_ae_r20_Slot_ae_slot0_set,
- Field_ae_r10_Slot_ae_slot0_set,
- Field_ae_s20_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- Field_ftsf11_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s4_Slot_ae_slot0_set,
- Field_ftsf211ae_slot0_Slot_ae_slot0_set,
- Field_ftsf212ae_slot0_Slot_ae_slot0_set,
- Field_ftsf213ae_slot0_Slot_ae_slot0_set,
- Field_ftsf214ae_slot0_Slot_ae_slot0_set,
- Field_ftsf215ae_slot0_Slot_ae_slot0_set,
- Field_ftsf217ae_slot0_Slot_ae_slot0_set,
- Field_ftsf218ae_slot0_Slot_ae_slot0_set,
- Field_ftsf219ae_slot0_Slot_ae_slot0_set,
- Field_ftsf220ae_slot0_Slot_ae_slot0_set,
- Field_ftsf221ae_slot0_Slot_ae_slot0_set,
- Field_ftsf222ae_slot0_Slot_ae_slot0_set,
- Field_ftsf223ae_slot0_Slot_ae_slot0_set,
- Field_ftsf224ae_slot0_Slot_ae_slot0_set,
- Field_ftsf225ae_slot0_Slot_ae_slot0_set,
- Field_ftsf226ae_slot0_Slot_ae_slot0_set,
- Field_ftsf227ae_slot0_Slot_ae_slot0_set,
- Field_ftsf228ae_slot0_Slot_ae_slot0_set,
- Field_ftsf229ae_slot0_Slot_ae_slot0_set,
- Field_ftsf230ae_slot0_Slot_ae_slot0_set,
- Field_ftsf231ae_slot0_Slot_ae_slot0_set,
- Field_ftsf232ae_slot0_Slot_ae_slot0_set,
- Field_ftsf233ae_slot0_Slot_ae_slot0_set,
- Field_ftsf234ae_slot0_Slot_ae_slot0_set,
- Field_ftsf235ae_slot0_Slot_ae_slot0_set,
- Field_ftsf236ae_slot0_Slot_ae_slot0_set,
- Field_ftsf237ae_slot0_Slot_ae_slot0_set,
- Field_ftsf238ae_slot0_Slot_ae_slot0_set,
- Field_ftsf239ae_slot0_Slot_ae_slot0_set,
- Field_ftsf240ae_slot0_Slot_ae_slot0_set,
- Field_ftsf241ae_slot0_Slot_ae_slot0_set,
- Field_ftsf242ae_slot0_Slot_ae_slot0_set,
- Field_ftsf243ae_slot0_Slot_ae_slot0_set,
- Field_ftsf244ae_slot0_Slot_ae_slot0_set,
- Field_ftsf245ae_slot0_Slot_ae_slot0_set,
- Field_ftsf246ae_slot0_Slot_ae_slot0_set,
- Field_ftsf247ae_slot0_Slot_ae_slot0_set,
- Field_ftsf248ae_slot0_Slot_ae_slot0_set,
- Field_ftsf249ae_slot0_Slot_ae_slot0_set,
- Field_ftsf250ae_slot0_Slot_ae_slot0_set,
- Field_ftsf251ae_slot0_Slot_ae_slot0_set,
- Field_ftsf252ae_slot0_Slot_ae_slot0_set,
- Field_ftsf253ae_slot0_Slot_ae_slot0_set,
- Field_ftsf254ae_slot0_Slot_ae_slot0_set,
- Field_ftsf255ae_slot0_Slot_ae_slot0_set,
- Field_ftsf256ae_slot0_Slot_ae_slot0_set,
- Field_ftsf257ae_slot0_Slot_ae_slot0_set,
- Field_ftsf258ae_slot0_Slot_ae_slot0_set,
- Field_ftsf259ae_slot0_Slot_ae_slot0_set,
- Field_ftsf260ae_slot0_Slot_ae_slot0_set,
- Field_ftsf261ae_slot0_Slot_ae_slot0_set,
- Field_ftsf262ae_slot0_Slot_ae_slot0_set,
- Field_ftsf263ae_slot0_Slot_ae_slot0_set,
- Field_ftsf264ae_slot0_Slot_ae_slot0_set,
- Field_ftsf265ae_slot0_Slot_ae_slot0_set,
- Field_ftsf266ae_slot0_Slot_ae_slot0_set,
- Field_ftsf267ae_slot0_Slot_ae_slot0_set,
- Field_ftsf268ae_slot0_Slot_ae_slot0_set,
- Field_ftsf269ae_slot0_Slot_ae_slot0_set,
- Field_ftsf270ae_slot0_Slot_ae_slot0_set,
- Field_ftsf271ae_slot0_Slot_ae_slot0_set,
- Field_ftsf272ae_slot0_Slot_ae_slot0_set,
- Field_ftsf273ae_slot0_Slot_ae_slot0_set,
- Field_ftsf274ae_slot0_Slot_ae_slot0_set,
- Field_ftsf275ae_slot0_Slot_ae_slot0_set,
- Field_ftsf276ae_slot0_Slot_ae_slot0_set,
- Field_ftsf277ae_slot0_Slot_ae_slot0_set,
- Field_ftsf278ae_slot0_Slot_ae_slot0_set,
- Field_ftsf279ae_slot0_Slot_ae_slot0_set,
- Field_ftsf280_Slot_ae_slot0_set,
- Field_ftsf281ae_slot0_Slot_ae_slot0_set,
- Field_ftsf282ae_slot0_Slot_ae_slot0_set,
- Field_ftsf284ae_slot0_Slot_ae_slot0_set,
- Field_ftsf285ae_slot0_Slot_ae_slot0_set,
- Field_ftsf287ae_slot0_Slot_ae_slot0_set,
- Field_ftsf288_Slot_ae_slot0_set,
- Field_ftsf289ae_slot0_Slot_ae_slot0_set,
- Field_ftsf290ae_slot0_Slot_ae_slot0_set,
- Field_ftsf291ae_slot0_Slot_ae_slot0_set,
- Field_ftsf292ae_slot0_Slot_ae_slot0_set,
- Field_ftsf293ae_slot0_Slot_ae_slot0_set,
- Field_ftsf294ae_slot0_Slot_ae_slot0_set,
- Field_ftsf295ae_slot0_Slot_ae_slot0_set,
- Field_ftsf296ae_slot0_Slot_ae_slot0_set,
- Field_ftsf297ae_slot0_Slot_ae_slot0_set,
- Field_ftsf298ae_slot0_Slot_ae_slot0_set,
- Field_ftsf300ae_slot0_Slot_ae_slot0_set,
- Field_ftsf302ae_slot0_Slot_ae_slot0_set,
- Field_ftsf304ae_slot0_Slot_ae_slot0_set,
- Field_ftsf305ae_slot0_Slot_ae_slot0_set,
- Field_ftsf306ae_slot0_Slot_ae_slot0_set,
- Field_ftsf307ae_slot0_Slot_ae_slot0_set,
- Field_ftsf308ae_slot0_Slot_ae_slot0_set,
- Field_ftsf309_Slot_ae_slot0_set,
- Field_ftsf310ae_slot0_Slot_ae_slot0_set,
- Field_ftsf311ae_slot0_Slot_ae_slot0_set,
- Field_ftsf312ae_slot0_Slot_ae_slot0_set,
- Field_ftsf313ae_slot0_Slot_ae_slot0_set,
- Field_ftsf314ae_slot0_Slot_ae_slot0_set,
- Field_ftsf315_Slot_ae_slot0_set,
- Field_ftsf316ae_slot0_Slot_ae_slot0_set,
- Field_ftsf317ae_slot0_Slot_ae_slot0_set,
- Field_ftsf319ae_slot0_Slot_ae_slot0_set,
- Field_ftsf320ae_slot0_Slot_ae_slot0_set,
- Field_ftsf322ae_slot0_Slot_ae_slot0_set,
- Field_ftsf323ae_slot0_Slot_ae_slot0_set,
- Field_ftsf324ae_slot0_Slot_ae_slot0_set,
- Field_ftsf325ae_slot0_Slot_ae_slot0_set,
- Field_ftsf326ae_slot0_Slot_ae_slot0_set,
- Field_ftsf327ae_slot0_Slot_ae_slot0_set,
- Field_ftsf328ae_slot0_Slot_ae_slot0_set,
- Field_ftsf329ae_slot0_Slot_ae_slot0_set,
- Field_ftsf360ae_slot0_Slot_ae_slot0_set,
- Field_ftsf361ae_slot0_Slot_ae_slot0_set,
- Field_ftsf362_Slot_ae_slot0_set,
- Field_ftsf363ae_slot0_Slot_ae_slot0_set,
- Field_ftsf364ae_slot0_Slot_ae_slot0_set,
- Field_ftsf366ae_slot0_Slot_ae_slot0_set,
- Field_ftsf368ae_slot0_Slot_ae_slot0_set,
- Field_ftsf370ae_slot0_Slot_ae_slot0_set,
- Field_ftsf373ae_slot0_Slot_ae_slot0_set,
- Field_ftsf376ae_slot0_Slot_ae_slot0_set,
- Field_ftsf378ae_slot0_Slot_ae_slot0_set,
- Field_ftsf379ae_slot0_Slot_ae_slot0_set,
- Field_ftsf382ae_slot0_Slot_ae_slot0_set,
- Field_ftsf383ae_slot0_Slot_ae_slot0_set,
- Field_ftsf384ae_slot0_Slot_ae_slot0_set,
- Field_ftsf386ae_slot0_Slot_ae_slot0_set,
- Field_ftsf387ae_slot0_Slot_ae_slot0_set,
- Field_ftsf388ae_slot0_Slot_ae_slot0_set,
- Field_ftsf389ae_slot0_Slot_ae_slot0_set,
- 0,
- Field_op0_s4_s4_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld28_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld37_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld39_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld40_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld46_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld47_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld49_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld50_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld52_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld121_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld123_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld127_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set,
- Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set,
- Field_op0_s4_s4_s4_Slot_ae_slot0_set,
- Field_combined1e9fefee_fld96_Slot_ae_slot0_set,
- Field_combined1e9fefee_fld98_Slot_ae_slot0_set,
- Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set,
- Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set,
- Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set,
- Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_bitindex_Slot_ae_slot0_set,
- Field_s3to1_Slot_ae_slot0_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" },
- { "ae_slot1", "ae_format", 1,
- Slot_ae_format_Format_ae_slot1_10_get, Slot_ae_format_Format_ae_slot1_10_set,
- Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
- Slot_ae_slot1_decode, "nop" },
- { "ae_slot0", "ae_format", 0,
- Slot_ae_format_Format_ae_slot0_33_get, Slot_ae_format_Format_ae_slot0_33_set,
- Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
- Slot_ae_slot0_decode, "nop" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
- insn[1] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
- insn[1] = 0x80000000;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
- insn[1] = 0xc0000000;
-}
-
-static void
-Format_ae_format_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
- insn[1] = 0xf0000000;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static int Format_ae_format_slots[] = { 3, 4 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
- { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0) == 0 && (insn[1] & 0x80000000) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0) == 0 && (insn[1] & 0xc0000000) == 0x80000000)
- return 1; /* x16a */
- if ((insn[0] & 0) == 0 && (insn[1] & 0xe0000000) == 0xc0000000)
- return 2; /* x16b */
- if ((insn[0] & 0x3ff) == 0 && (insn[1] & 0xf0000000) == 0xf0000000)
- return 3; /* ae_format */
- return -1;
-}
-
-static int length_table[256] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- -1,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int l = insn[0];
- return length_table[l];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 1 /* big-endian */,
- 8 /* insn_size */, 0,
- 4, formats, format_decoder, length_decoder,
- 5, slots,
- 468 /* num_fields */,
- 536, operands,
- 746, iclasses,
- 881, opcodes, 0,
- 9, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 6, interfaces, 0,
- 4, funcUnits, 0
-};
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_test_mmuhifi_c3
-#include "core-test_mmuhifi_c3/xtensa-modules.inc.c"
+#include "core-test_mmuhifi_c3/xtensa-modules.c.inc"
static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
.name = "test_mmuhifi_c3",
.gdb_regmap = {
.reg = {
-#include "core-test_mmuhifi_c3/gdb-config.inc.c"
+#include "core-test_mmuhifi_c3/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
--- /dev/null
+/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
+
+ Copyright (c) 2003-2019 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
+ XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
+ XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
+ XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
+ XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
+ XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
+ XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
+ XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
+ XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
+ XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
+ XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
+ XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
+ XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
+ XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
+ XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
+ XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
+ XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
+ XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
+ XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
+ XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
+ XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
+ XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
+ XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
+ XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
+ XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
+ XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
+ XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
+ XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
+ XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
+ XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
+ XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
+ XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
+ XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
+ XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
+ XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
+ XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
+ XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
+ XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
+ "03:04:84:b2","03:04:84:a7",0,0,0,0)
+ XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
+ "03:04:94:b2","03:04:94:a7",0,0,0,0)
+ XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
+ "03:04:a4:b2","03:04:a4:a7",0,0,0,0)
+ XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
+ "03:04:b4:b2","03:04:b4:a7",0,0,0,0)
+ XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
+ "03:04:c4:b2","03:04:c4:a7",0,0,0,0)
+ XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
+ "03:04:d4:b2","03:04:d4:a7",0,0,0,0)
+ XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
+ "03:04:e4:b2","03:04:e4:a7",0,0,0,0)
+ XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
+ "03:04:f4:b2","03:04:f4:a7",0,0,0,0)
+ XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
+ "03:04:04:c3","03:04:04:c1",0,0,0,0)
+ XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
+ "03:04:14:c3","03:04:44:c1",0,0,0,0)
+ XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
+ "03:04:24:c3","03:04:84:c1",0,0,0,0)
+ XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
+ "03:04:34:c3","03:04:c4:c1",0,0,0,0)
+ XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
+ XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
+ XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
+ XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
+ XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
+ XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
+ XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
+ XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
+ XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
+ XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
+ XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
+ XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
+ XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
+ XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
+ XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
+ XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
+ XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
+ XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
+ XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
+ XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
+ XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
+ XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
+ XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
+ XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
+ XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
+ XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
+ 0,0,&xtensa_mask0,0,0,0)
+ XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
+ 0,0,&xtensa_mask1,0,0,0)
+ XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
+ 0,0,&xtensa_mask2,0,0,0)
+ XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
+ 0,0,&xtensa_mask3,0,0,0)
+ XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
+ 0,0,&xtensa_mask4,0,0,0)
+ XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
+ 0,0,&xtensa_mask5,0,0,0)
+ XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
+ 0,0,&xtensa_mask6,0,0,0)
+ XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
+ 0,0,&xtensa_mask7,0,0,0)
+ XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
+ 0,0,&xtensa_mask8,0,0,0)
+ XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
+ 0,0,&xtensa_mask9,0,0,0)
+ XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
+ 0,0,&xtensa_mask10,0,0,0)
+ XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
+ 0,0,&xtensa_mask11,0,0,0)
+ XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
+ 0,0,&xtensa_mask12,0,0,0)
+ XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
+ 0,0,&xtensa_mask13,0,0,0)
+ XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
+ 0,0,&xtensa_mask14,0,0,0)
+ XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
+ 0,0,&xtensa_mask15,0,0,0)
+ XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask16,0,0,0)
+ XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask17,0,0,0)
+ XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask18,0,0,0)
+ XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
+ 0,0,&xtensa_mask19,0,0,0)
+ XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask20,0,0,0)
+ XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask21,0,0,0)
+ XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask22,0,0,0)
+ XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
+ 0,0,&xtensa_mask23,0,0,0)
+ XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
+ 0,0,&xtensa_mask24,0,0,0)
+ XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
+ 0,0,&xtensa_mask25,0,0,0)
+ XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
+ 0,0,&xtensa_mask26,0,0,0)
+ XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
+ 0,0,&xtensa_mask27,0,0,0)
+ XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
+ 0,0,&xtensa_mask28,0,0,0)
+ XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
+ 0,0,&xtensa_mask29,0,0,0)
+ XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
+ 0,0,&xtensa_mask30,0,0,0)
+ XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
+ 0,0,&xtensa_mask31,0,0,0)
+ XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
+ 0,0,&xtensa_mask32,0,0,0)
+ XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
+ 0,0,&xtensa_mask33,0,0,0)
+ XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
+ 0,0,&xtensa_mask34,0,0,0)
+ XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
+ 0,0,&xtensa_mask35,0,0,0)
+ XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
+ 0,0,&xtensa_mask36,0,0,0)
+ XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
+ 0,0,&xtensa_mask37,0,0,0)
+ XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
+ 0,0,&xtensa_mask38,0,0,0)
+ XTREG_END
+++ /dev/null
-/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
-
- Copyright (c) 2003-2019 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
- XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
- XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
- XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
- XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
- XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
- XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
- XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
- XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
- XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
- XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
- XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
- XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
- XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
- XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
- XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
- XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
- XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
- XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
- XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
- XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
- XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
- XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
- XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
- XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
- XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
- XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
- XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
- XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
- XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
- XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
- XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
- XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
- XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
- XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
- XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
- XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
- XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
- XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
- XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
- XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
- XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
- XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
- "03:04:84:b2","03:04:84:a7",0,0,0,0)
- XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
- "03:04:94:b2","03:04:94:a7",0,0,0,0)
- XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
- "03:04:a4:b2","03:04:a4:a7",0,0,0,0)
- XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
- "03:04:b4:b2","03:04:b4:a7",0,0,0,0)
- XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
- "03:04:c4:b2","03:04:c4:a7",0,0,0,0)
- XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
- "03:04:d4:b2","03:04:d4:a7",0,0,0,0)
- XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
- "03:04:e4:b2","03:04:e4:a7",0,0,0,0)
- XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
- "03:04:f4:b2","03:04:f4:a7",0,0,0,0)
- XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
- "03:04:04:c3","03:04:04:c1",0,0,0,0)
- XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
- "03:04:14:c3","03:04:44:c1",0,0,0,0)
- XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
- "03:04:24:c3","03:04:84:c1",0,0,0,0)
- XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
- "03:04:34:c3","03:04:c4:c1",0,0,0,0)
- XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
- XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
- XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
- XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
- XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
- XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
- XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
- XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
- XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
- XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
- XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
- XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
- XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
- XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
- XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
- XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
- XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
- XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
- XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
- XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
- XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
- XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
- XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
- XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
- XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
- XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
- XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
- XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
- XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
- XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
- XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
- XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
- XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
- XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
- XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
- XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
- XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
- XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
- XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
- XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
- XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
- XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
- XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
- XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
- XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
- XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
- XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
- XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
- XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
- XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
- 0,0,&xtensa_mask0,0,0,0)
- XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
- 0,0,&xtensa_mask1,0,0,0)
- XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
- 0,0,&xtensa_mask2,0,0,0)
- XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
- 0,0,&xtensa_mask3,0,0,0)
- XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
- 0,0,&xtensa_mask4,0,0,0)
- XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
- 0,0,&xtensa_mask5,0,0,0)
- XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
- 0,0,&xtensa_mask6,0,0,0)
- XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
- 0,0,&xtensa_mask7,0,0,0)
- XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
- 0,0,&xtensa_mask8,0,0,0)
- XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
- 0,0,&xtensa_mask9,0,0,0)
- XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
- 0,0,&xtensa_mask10,0,0,0)
- XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
- 0,0,&xtensa_mask11,0,0,0)
- XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
- 0,0,&xtensa_mask12,0,0,0)
- XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
- 0,0,&xtensa_mask13,0,0,0)
- XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
- 0,0,&xtensa_mask14,0,0,0)
- XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
- 0,0,&xtensa_mask15,0,0,0)
- XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
- 0,0,&xtensa_mask16,0,0,0)
- XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
- 0,0,&xtensa_mask17,0,0,0)
- XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
- 0,0,&xtensa_mask18,0,0,0)
- XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
- 0,0,&xtensa_mask19,0,0,0)
- XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
- 0,0,&xtensa_mask20,0,0,0)
- XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
- 0,0,&xtensa_mask21,0,0,0)
- XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
- 0,0,&xtensa_mask22,0,0,0)
- XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
- 0,0,&xtensa_mask23,0,0,0)
- XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
- 0,0,&xtensa_mask24,0,0,0)
- XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
- 0,0,&xtensa_mask25,0,0,0)
- XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
- 0,0,&xtensa_mask26,0,0,0)
- XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
- 0,0,&xtensa_mask27,0,0,0)
- XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
- 0,0,&xtensa_mask28,0,0,0)
- XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
- 0,0,&xtensa_mask29,0,0,0)
- XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
- 0,0,&xtensa_mask30,0,0,0)
- XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
- 0,0,&xtensa_mask31,0,0,0)
- XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
- 0,0,&xtensa_mask32,0,0,0)
- XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
- 0,0,&xtensa_mask33,0,0,0)
- XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
- 0,0,&xtensa_mask34,0,0,0)
- XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
- 0,0,&xtensa_mask35,0,0,0)
- XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
- 0,0,&xtensa_mask36,0,0,0)
- XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
- 0,0,&xtensa_mask37,0,0,0)
- XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
- 0,0,&xtensa_mask38,0,0,0)
- XTREG_END
--- /dev/null
+/* Xtensa configuration-specific ISA information.
+
+ Copyright (c) 2003-2019 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-isa.h"
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs. */
+
+static xtensa_sysreg_internal sysregs[] = {
+ { "LBEG", 0, 0 },
+ { "LEND", 1, 0 },
+ { "LCOUNT", 2, 0 },
+ { "BR", 4, 0 },
+ { "PTEVADDR", 83, 0 },
+ { "DDR", 104, 0 },
+ { "CONFIGID0", 176, 0 },
+ { "CONFIGID1", 208, 0 },
+ { "INTERRUPT", 226, 0 },
+ { "INTCLEAR", 227, 0 },
+ { "CCOUNT", 234, 0 },
+ { "PRID", 235, 0 },
+ { "ICOUNT", 236, 0 },
+ { "CCOMPARE0", 240, 0 },
+ { "CCOMPARE1", 241, 0 },
+ { "VECBASE", 231, 0 },
+ { "EPC1", 177, 0 },
+ { "EPC2", 178, 0 },
+ { "EXCSAVE1", 209, 0 },
+ { "EXCSAVE2", 210, 0 },
+ { "EPS2", 194, 0 },
+ { "EXCCAUSE", 232, 0 },
+ { "DEPC", 192, 0 },
+ { "EXCVADDR", 238, 0 },
+ { "WINDOWBASE", 72, 0 },
+ { "WINDOWSTART", 73, 0 },
+ { "SAR", 3, 0 },
+ { "LITBASE", 5, 0 },
+ { "PS", 230, 0 },
+ { "MISC0", 244, 0 },
+ { "MISC1", 245, 0 },
+ { "INTENABLE", 228, 0 },
+ { "ICOUNTLEVEL", 237, 0 },
+ { "DEBUGCAUSE", 233, 0 },
+ { "RASID", 90, 0 },
+ { "ITLBCFG", 91, 0 },
+ { "DTLBCFG", 92, 0 },
+ { "CPENABLE", 224, 0 },
+ { "SCOMPARE1", 12, 0 },
+ { "ATOMCTL", 99, 0 },
+ { "THREADPTR", 231, 1 },
+ { "AE_OVF_SAR", 240, 1 },
+ { "AE_BITHEAD", 241, 1 },
+ { "AE_TS_FTS_BU_BP", 242, 1 },
+ { "AE_SD_NO", 243, 1 }
+};
+
+#define NUM_SYSREGS 45
+#define MAX_SPECIAL_REG 245
+#define MAX_USER_REG 243
+
+\f
+/* Processor states. */
+
+static xtensa_state_internal states[] = {
+ { "LCOUNT", 32, 0 },
+ { "PC", 32, 0 },
+ { "ICOUNT", 32, 0 },
+ { "DDR", 32, 0 },
+ { "INTERRUPT", 12, 0 },
+ { "CCOUNT", 32, 0 },
+ { "XTSYNC", 1, 0 },
+ { "VECBASE", 22, 0 },
+ { "EPC1", 32, 0 },
+ { "EPC2", 32, 0 },
+ { "EXCSAVE1", 32, 0 },
+ { "EXCSAVE2", 32, 0 },
+ { "EPS2", 15, 0 },
+ { "EXCCAUSE", 6, 0 },
+ { "PSINTLEVEL", 4, 0 },
+ { "PSUM", 1, 0 },
+ { "PSWOE", 1, 0 },
+ { "PSRING", 2, 0 },
+ { "PSEXCM", 1, 0 },
+ { "DEPC", 32, 0 },
+ { "EXCVADDR", 32, 0 },
+ { "WindowBase", 3, 0 },
+ { "WindowStart", 8, 0 },
+ { "PSCALLINC", 2, 0 },
+ { "PSOWB", 4, 0 },
+ { "LBEG", 32, 0 },
+ { "LEND", 32, 0 },
+ { "SAR", 6, 0 },
+ { "THREADPTR", 32, 0 },
+ { "LITBADDR", 20, 0 },
+ { "LITBEN", 1, 0 },
+ { "MISC0", 32, 0 },
+ { "MISC1", 32, 0 },
+ { "InOCDMode", 1, 0 },
+ { "INTENABLE", 12, 0 },
+ { "ICOUNTLEVEL", 4, 0 },
+ { "DEBUGCAUSE", 6, 0 },
+ { "DBNUM", 4, 0 },
+ { "CCOMPARE0", 32, 0 },
+ { "CCOMPARE1", 32, 0 },
+ { "ASID3", 8, 0 },
+ { "ASID2", 8, 0 },
+ { "ASID1", 8, 0 },
+ { "INSTPGSZID4", 2, 0 },
+ { "DATAPGSZID4", 2, 0 },
+ { "PTBASE", 10, 0 },
+ { "CPENABLE", 2, 0 },
+ { "SCOMPARE1", 32, 0 },
+ { "ATOMCTL", 6, 0 },
+ { "CCON", 1, XTENSA_STATE_IS_EXPORTED },
+ { "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED },
+ { "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED },
+ { "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED },
+ { "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED },
+ { "AE_OVERFLOW", 1, 0 },
+ { "AE_SAR", 6, 0 },
+ { "AE_BITHEAD", 32, 0 },
+ { "AE_BITPTR", 4, 0 },
+ { "AE_BITSUSED", 4, 0 },
+ { "AE_TABLESIZE", 4, 0 },
+ { "AE_FIRST_TS", 4, 0 },
+ { "AE_NEXTOFFSET", 27, 0 },
+ { "AE_SEARCHDONE", 1, 0 }
+};
+
+#define NUM_STATES 63
+
+enum xtensa_state_id {
+ STATE_LCOUNT,
+ STATE_PC,
+ STATE_ICOUNT,
+ STATE_DDR,
+ STATE_INTERRUPT,
+ STATE_CCOUNT,
+ STATE_XTSYNC,
+ STATE_VECBASE,
+ STATE_EPC1,
+ STATE_EPC2,
+ STATE_EXCSAVE1,
+ STATE_EXCSAVE2,
+ STATE_EPS2,
+ STATE_EXCCAUSE,
+ STATE_PSINTLEVEL,
+ STATE_PSUM,
+ STATE_PSWOE,
+ STATE_PSRING,
+ STATE_PSEXCM,
+ STATE_DEPC,
+ STATE_EXCVADDR,
+ STATE_WindowBase,
+ STATE_WindowStart,
+ STATE_PSCALLINC,
+ STATE_PSOWB,
+ STATE_LBEG,
+ STATE_LEND,
+ STATE_SAR,
+ STATE_THREADPTR,
+ STATE_LITBADDR,
+ STATE_LITBEN,
+ STATE_MISC0,
+ STATE_MISC1,
+ STATE_InOCDMode,
+ STATE_INTENABLE,
+ STATE_ICOUNTLEVEL,
+ STATE_DEBUGCAUSE,
+ STATE_DBNUM,
+ STATE_CCOMPARE0,
+ STATE_CCOMPARE1,
+ STATE_ASID3,
+ STATE_ASID2,
+ STATE_ASID1,
+ STATE_INSTPGSZID4,
+ STATE_DATAPGSZID4,
+ STATE_PTBASE,
+ STATE_CPENABLE,
+ STATE_SCOMPARE1,
+ STATE_ATOMCTL,
+ STATE_CCON,
+ STATE_MPSCORE,
+ STATE_WMPINT_ADDR,
+ STATE_WMPINT_DATA,
+ STATE_WMPINT_TOGGLEEN,
+ STATE_AE_OVERFLOW,
+ STATE_AE_SAR,
+ STATE_AE_BITHEAD,
+ STATE_AE_BITPTR,
+ STATE_AE_BITSUSED,
+ STATE_AE_TABLESIZE,
+ STATE_AE_FIRST_TS,
+ STATE_AE_NEXTOFFSET,
+ STATE_AE_SEARCHDONE
+};
+
+\f
+/* Field definitions. */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 22) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+ tie_t = (val << 23) >> 25;
+ insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
+ tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
+ tie_t = (val << 22) >> 25;
+ insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
+ tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
+ tie_t = (val << 21) >> 25;
+ insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
+ tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
+ tie_t = (val << 21) >> 25;
+ insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 21) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 20) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 21) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 24) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 21) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+ tie_t = (val << 22) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
+ tie_t = (val << 21) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 20) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26);
+ return tie_t;
+}
+
+static void
+Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 26) >> 26;
+ insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3);
+}
+
+static unsigned
+Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf8) | (tie_t << 3);
+}
+
+static unsigned
+Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+ tie_t = (val << 25) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
+}
+
+static unsigned
+Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 23) >> 30;
+ insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x7c) | (tie_t << 2);
+ tie_t = (val << 24) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
+ tie_t = (val << 20) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
+ tie_t = (val << 20) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26);
+ return tie_t;
+}
+
+static void
+Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 26) >> 26;
+ insn[0] = (insn[0] & ~0x7e) | (tie_t << 1);
+ tie_t = (val << 23) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
+ tie_t = (val << 22) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 22) >> 23;
+ insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 24) >> 25;
+ insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+ tie_t = (val << 28) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+ tie_t = (val << 26) >> 29;
+ insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 26) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 26) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 23) >> 27;
+ insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
+}
+
+static unsigned
+Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+ tie_t = (val << 24) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25);
+ return tie_t;
+}
+
+static void
+Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+}
+
+static unsigned
+Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
+}
+
+static unsigned
+Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+ tie_t = (val << 16) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
+ return tie_t;
+}
+
+static void
+Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
+ return tie_t;
+}
+
+static void
+Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 26) >> 26;
+ insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
+ tie_t = (val << 25) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 17) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+ tie_t = (val << 16) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x38) | (tie_t << 3);
+ tie_t = (val << 21) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+ tie_t = (val << 27) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0x3c) | (tie_t << 2);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x3e) | (tie_t << 1);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25);
+ return tie_t;
+}
+
+static void
+Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 25) >> 25;
+ insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
+ return tie_t;
+}
+
+static void
+Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 19) >> 19;
+ insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
+}
+
+static unsigned
+Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23);
+ return tie_t;
+}
+
+static void
+Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 23) >> 23;
+ insn[0] = (insn[0] & ~0xff800) | (tie_t << 11);
+}
+
+static unsigned
+Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+ tie_t = (val << 21) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+ tie_t = (val << 21) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
+}
+
+static unsigned
+Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27);
+ return tie_t;
+}
+
+static void
+Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+ tie_t = (val << 27) >> 29;
+ insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+ tie_t = (val << 17) >> 20;
+ insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
+ return tie_t;
+}
+
+static void
+Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 26) >> 26;
+ insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
+ tie_t = (val << 18) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
+ tie_t = (val << 28) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22);
+ return tie_t;
+}
+
+static void
+Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 22) >> 22;
+ insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21);
+ return tie_t;
+}
+
+static void
+Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 21) >> 21;
+ insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
+ tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
+ tie_t = (val << 19) >> 20;
+ insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
+ tie_t = (val << 29) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+}
+
+static unsigned
+Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
+ tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
+ tie_t = (val << 18) >> 20;
+ insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
+ tie_t = (val << 30) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+}
+
+static unsigned
+Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 23) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
+ tie_t = (val << 22) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
+}
+
+static unsigned
+Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
+ tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
+ tie_t = (val << 17) >> 20;
+ insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 20) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+ tie_t = (val << 19) >> 24;
+ insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
+ return tie_t;
+}
+
+static void
+Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 24) >> 24;
+ insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+ tie_t = (val << 20) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
+ return tie_t;
+}
+
+static void
+Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 20) >> 20;
+ insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
+ return tie_t;
+}
+
+static void
+Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 16) >> 16;
+ insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
+ return tie_t;
+}
+
+static void
+Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
+}
+
+static unsigned
+Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
+ return tie_t;
+}
+
+static void
+Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
+ return tie_t;
+}
+
+static void
+Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 27) >> 31;
+ insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
+ return tie_t;
+}
+
+static void
+Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 27) >> 27;
+ insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+ tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+ return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+ tie_t = (val << 24) >> 28;
+ insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+ tie_t = (val << 28) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+ return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+ return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+ tie_t = (val << 25) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 29) >> 30;
+ insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
+}
+
+static unsigned
+Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+ return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+ return tie_t;
+}
+
+static void
+Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+ return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+ return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+ return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+ return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+ return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+ return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+ return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 17) >> 17;
+ insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+ return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 14) >> 14;
+ insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26);
+ return tie_t;
+}
+
+static void
+Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 26) >> 26;
+ insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4);
+}
+
+static unsigned
+Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+ tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+ tie_t = (val << 26) >> 30;
+ insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+ return tie_t;
+}
+
+static void
+Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 28) >> 28;
+ insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+ return tie_t;
+}
+
+static void
+Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 29) >> 29;
+ insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+ return tie_t;
+}
+
+static void
+Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 30) >> 30;
+ insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn)
+{
+ unsigned tie_t = 0;
+ tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
+ tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
+ return tie_t;
+}
+
+static void
+Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
+{
+ uint32 tie_t;
+ tie_t = (val << 31) >> 31;
+ insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
+ tie_t = (val << 27) >> 28;
+ insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+ uint32 val ATTRIBUTE_UNUSED)
+{
+ /* Do nothing. */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 12;
+}
+
+static unsigned
+Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static unsigned
+Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+enum xtensa_field_id {
+ FIELD_t,
+ FIELD_bbi4,
+ FIELD_bbi,
+ FIELD_imm12,
+ FIELD_imm8,
+ FIELD_s,
+ FIELD_imm12b,
+ FIELD_imm16,
+ FIELD_m,
+ FIELD_n,
+ FIELD_offset,
+ FIELD_op0,
+ FIELD_op1,
+ FIELD_op2,
+ FIELD_r,
+ FIELD_sa4,
+ FIELD_sae4,
+ FIELD_sae,
+ FIELD_sal,
+ FIELD_sargt,
+ FIELD_sas4,
+ FIELD_sas,
+ FIELD_sr,
+ FIELD_st,
+ FIELD_thi3,
+ FIELD_imm4,
+ FIELD_mn,
+ FIELD_i,
+ FIELD_imm6lo,
+ FIELD_imm6hi,
+ FIELD_imm7lo,
+ FIELD_imm7hi,
+ FIELD_z,
+ FIELD_imm6,
+ FIELD_imm7,
+ FIELD_t2,
+ FIELD_s2,
+ FIELD_r2,
+ FIELD_t4,
+ FIELD_s4,
+ FIELD_r4,
+ FIELD_t8,
+ FIELD_s8,
+ FIELD_r8,
+ FIELD_xt_wbr15_imm,
+ FIELD_xt_wbr18_imm,
+ FIELD_ae_r3,
+ FIELD_ae_s_non_samt,
+ FIELD_ae_s3,
+ FIELD_ae_r32,
+ FIELD_ae_samt_s_t,
+ FIELD_ae_r20,
+ FIELD_ae_r10,
+ FIELD_ae_s20,
+ FIELD_ae_fld_ohba,
+ FIELD_ae_fld_ohba2,
+ FIELD_op0_s3,
+ FIELD_ftsf12,
+ FIELD_ftsf13,
+ FIELD_ftsf14,
+ FIELD_ftsf21ae_slot1,
+ FIELD_ftsf22ae_slot1,
+ FIELD_ftsf23ae_slot1,
+ FIELD_ftsf24ae_slot1,
+ FIELD_ftsf25ae_slot1,
+ FIELD_ftsf26ae_slot1,
+ FIELD_ftsf27ae_slot1,
+ FIELD_ftsf28ae_slot1,
+ FIELD_ftsf29ae_slot1,
+ FIELD_ftsf30ae_slot1,
+ FIELD_ftsf31ae_slot1,
+ FIELD_ftsf32ae_slot1,
+ FIELD_ftsf33ae_slot1,
+ FIELD_ftsf34ae_slot1,
+ FIELD_ftsf35ae_slot1,
+ FIELD_ftsf36ae_slot1,
+ FIELD_ftsf37ae_slot1,
+ FIELD_ftsf38ae_slot1,
+ FIELD_ftsf39ae_slot1,
+ FIELD_ftsf40ae_slot1,
+ FIELD_ftsf41ae_slot1,
+ FIELD_ftsf42ae_slot1,
+ FIELD_ftsf43ae_slot1,
+ FIELD_ftsf44ae_slot1,
+ FIELD_ftsf45ae_slot1,
+ FIELD_ftsf46ae_slot1,
+ FIELD_ftsf47ae_slot1,
+ FIELD_ftsf48ae_slot1,
+ FIELD_ftsf49ae_slot1,
+ FIELD_ftsf50ae_slot1,
+ FIELD_ftsf51ae_slot1,
+ FIELD_ftsf52ae_slot1,
+ FIELD_ftsf53ae_slot1,
+ FIELD_ftsf54ae_slot1,
+ FIELD_ftsf55ae_slot1,
+ FIELD_ftsf56ae_slot1,
+ FIELD_ftsf57ae_slot1,
+ FIELD_ftsf58ae_slot1,
+ FIELD_ftsf59ae_slot1,
+ FIELD_ftsf60ae_slot1,
+ FIELD_ftsf61ae_slot1,
+ FIELD_ftsf63ae_slot1,
+ FIELD_ftsf64ae_slot1,
+ FIELD_ftsf66ae_slot1,
+ FIELD_ftsf67ae_slot1,
+ FIELD_ftsf69ae_slot1,
+ FIELD_ftsf71ae_slot1,
+ FIELD_ftsf72ae_slot1,
+ FIELD_ftsf73ae_slot1,
+ FIELD_ftsf75ae_slot1,
+ FIELD_ftsf76ae_slot1,
+ FIELD_ftsf77ae_slot1,
+ FIELD_ftsf78ae_slot1,
+ FIELD_ftsf79ae_slot1,
+ FIELD_ftsf80ae_slot1,
+ FIELD_ftsf81ae_slot1,
+ FIELD_ftsf82ae_slot1,
+ FIELD_ftsf84ae_slot1,
+ FIELD_ftsf86ae_slot1,
+ FIELD_ftsf87ae_slot1,
+ FIELD_ftsf88ae_slot1,
+ FIELD_ftsf89ae_slot1,
+ FIELD_ftsf90ae_slot1,
+ FIELD_ftsf91ae_slot1,
+ FIELD_ftsf92ae_slot1,
+ FIELD_ftsf94ae_slot1,
+ FIELD_ftsf96ae_slot1,
+ FIELD_ftsf97ae_slot1,
+ FIELD_ftsf98ae_slot1,
+ FIELD_ftsf99ae_slot1,
+ FIELD_ftsf100ae_slot1,
+ FIELD_ftsf101ae_slot1,
+ FIELD_ftsf103ae_slot1,
+ FIELD_ftsf104ae_slot1,
+ FIELD_ftsf105ae_slot1,
+ FIELD_ftsf106ae_slot1,
+ FIELD_ftsf107ae_slot1,
+ FIELD_ftsf108ae_slot1,
+ FIELD_ftsf109ae_slot1,
+ FIELD_ftsf110ae_slot1,
+ FIELD_ftsf111ae_slot1,
+ FIELD_ftsf112ae_slot1,
+ FIELD_ftsf113ae_slot1,
+ FIELD_ftsf114ae_slot1,
+ FIELD_ftsf115ae_slot1,
+ FIELD_ftsf116ae_slot1,
+ FIELD_ftsf118ae_slot1,
+ FIELD_ftsf119ae_slot1,
+ FIELD_ftsf120ae_slot1,
+ FIELD_ftsf122ae_slot1,
+ FIELD_ftsf124ae_slot1,
+ FIELD_ftsf125ae_slot1,
+ FIELD_ftsf126ae_slot1,
+ FIELD_ftsf127ae_slot1,
+ FIELD_ftsf128ae_slot1,
+ FIELD_ftsf129ae_slot1,
+ FIELD_ftsf130ae_slot1,
+ FIELD_ftsf131ae_slot1,
+ FIELD_ftsf132ae_slot1,
+ FIELD_ftsf133ae_slot1,
+ FIELD_ftsf134ae_slot1,
+ FIELD_ftsf135ae_slot1,
+ FIELD_ftsf136ae_slot1,
+ FIELD_ftsf137ae_slot1,
+ FIELD_ftsf138ae_slot1,
+ FIELD_ftsf139ae_slot1,
+ FIELD_ftsf140ae_slot1,
+ FIELD_ftsf141ae_slot1,
+ FIELD_ftsf142ae_slot1,
+ FIELD_ftsf143ae_slot1,
+ FIELD_ftsf144ae_slot1,
+ FIELD_ftsf145ae_slot1,
+ FIELD_ftsf146ae_slot1,
+ FIELD_ftsf147ae_slot1,
+ FIELD_ftsf148ae_slot1,
+ FIELD_ftsf149ae_slot1,
+ FIELD_ftsf150ae_slot1,
+ FIELD_ftsf151ae_slot1,
+ FIELD_ftsf152ae_slot1,
+ FIELD_ftsf153ae_slot1,
+ FIELD_ftsf154ae_slot1,
+ FIELD_ftsf155ae_slot1,
+ FIELD_ftsf156ae_slot1,
+ FIELD_ftsf157ae_slot1,
+ FIELD_ftsf158ae_slot1,
+ FIELD_ftsf159ae_slot1,
+ FIELD_ftsf160ae_slot1,
+ FIELD_ftsf161ae_slot1,
+ FIELD_ftsf162ae_slot1,
+ FIELD_ftsf163ae_slot1,
+ FIELD_ftsf164ae_slot1,
+ FIELD_ftsf165ae_slot1,
+ FIELD_ftsf166ae_slot1,
+ FIELD_ftsf167ae_slot1,
+ FIELD_ftsf168ae_slot1,
+ FIELD_ftsf169ae_slot1,
+ FIELD_ftsf170ae_slot1,
+ FIELD_ftsf171ae_slot1,
+ FIELD_ftsf172ae_slot1,
+ FIELD_ftsf173ae_slot1,
+ FIELD_ftsf174ae_slot1,
+ FIELD_ftsf175ae_slot1,
+ FIELD_ftsf176ae_slot1,
+ FIELD_ftsf177ae_slot1,
+ FIELD_ftsf178ae_slot1,
+ FIELD_ftsf179ae_slot1,
+ FIELD_ftsf180ae_slot1,
+ FIELD_ftsf181ae_slot1,
+ FIELD_ftsf182ae_slot1,
+ FIELD_ftsf183ae_slot1,
+ FIELD_ftsf184ae_slot1,
+ FIELD_ftsf185ae_slot1,
+ FIELD_ftsf186ae_slot1,
+ FIELD_ftsf187ae_slot1,
+ FIELD_ftsf188ae_slot1,
+ FIELD_ftsf189ae_slot1,
+ FIELD_ftsf190ae_slot1,
+ FIELD_ftsf191ae_slot1,
+ FIELD_ftsf192ae_slot1,
+ FIELD_ftsf193ae_slot1,
+ FIELD_ftsf194ae_slot1,
+ FIELD_ftsf195ae_slot1,
+ FIELD_ftsf196ae_slot1,
+ FIELD_ftsf197ae_slot1,
+ FIELD_ftsf198ae_slot1,
+ FIELD_ftsf199ae_slot1,
+ FIELD_ftsf200ae_slot1,
+ FIELD_ftsf201ae_slot1,
+ FIELD_ftsf202ae_slot1,
+ FIELD_ftsf203ae_slot1,
+ FIELD_ftsf204ae_slot1,
+ FIELD_ftsf205ae_slot1,
+ FIELD_ftsf206ae_slot1,
+ FIELD_ftsf207ae_slot1,
+ FIELD_ftsf208,
+ FIELD_ftsf209ae_slot1,
+ FIELD_ftsf210ae_slot1,
+ FIELD_ftsf211ae_slot1,
+ FIELD_ftsf330ae_slot1,
+ FIELD_ftsf332ae_slot1,
+ FIELD_ftsf334ae_slot1,
+ FIELD_ftsf336ae_slot1,
+ FIELD_ftsf337ae_slot1,
+ FIELD_ftsf338,
+ FIELD_ftsf339ae_slot1,
+ FIELD_ftsf340,
+ FIELD_ftsf341ae_slot1,
+ FIELD_ftsf342ae_slot1,
+ FIELD_ftsf343ae_slot1,
+ FIELD_ftsf344ae_slot1,
+ FIELD_ftsf346ae_slot1,
+ FIELD_ftsf347,
+ FIELD_ftsf348ae_slot1,
+ FIELD_ftsf349ae_slot1,
+ FIELD_ftsf350ae_slot1,
+ FIELD_op0_s4,
+ FIELD_ftsf212ae_slot0,
+ FIELD_ftsf213ae_slot0,
+ FIELD_ftsf214ae_slot0,
+ FIELD_ftsf215ae_slot0,
+ FIELD_ftsf216ae_slot0,
+ FIELD_ftsf217,
+ FIELD_ftsf218ae_slot0,
+ FIELD_ftsf219ae_slot0,
+ FIELD_ftsf220ae_slot0,
+ FIELD_ftsf221ae_slot0,
+ FIELD_ftsf222ae_slot0,
+ FIELD_ftsf223ae_slot0,
+ FIELD_ftsf224ae_slot0,
+ FIELD_ftsf225ae_slot0,
+ FIELD_ftsf226ae_slot0,
+ FIELD_ftsf227ae_slot0,
+ FIELD_ftsf228ae_slot0,
+ FIELD_ftsf229ae_slot0,
+ FIELD_ftsf230ae_slot0,
+ FIELD_ftsf231ae_slot0,
+ FIELD_ftsf232ae_slot0,
+ FIELD_ftsf233ae_slot0,
+ FIELD_ftsf234ae_slot0,
+ FIELD_ftsf235ae_slot0,
+ FIELD_ftsf236ae_slot0,
+ FIELD_ftsf237ae_slot0,
+ FIELD_ftsf238ae_slot0,
+ FIELD_ftsf239ae_slot0,
+ FIELD_ftsf240ae_slot0,
+ FIELD_ftsf241ae_slot0,
+ FIELD_ftsf242ae_slot0,
+ FIELD_ftsf243ae_slot0,
+ FIELD_ftsf244ae_slot0,
+ FIELD_ftsf245ae_slot0,
+ FIELD_ftsf246ae_slot0,
+ FIELD_ftsf247ae_slot0,
+ FIELD_ftsf248ae_slot0,
+ FIELD_ftsf249ae_slot0,
+ FIELD_ftsf250ae_slot0,
+ FIELD_ftsf251ae_slot0,
+ FIELD_ftsf252ae_slot0,
+ FIELD_ftsf253ae_slot0,
+ FIELD_ftsf254ae_slot0,
+ FIELD_ftsf255ae_slot0,
+ FIELD_ftsf256ae_slot0,
+ FIELD_ftsf257ae_slot0,
+ FIELD_ftsf258ae_slot0,
+ FIELD_ftsf259ae_slot0,
+ FIELD_ftsf260ae_slot0,
+ FIELD_ftsf261ae_slot0,
+ FIELD_ftsf262ae_slot0,
+ FIELD_ftsf263ae_slot0,
+ FIELD_ftsf264ae_slot0,
+ FIELD_ftsf265ae_slot0,
+ FIELD_ftsf266ae_slot0,
+ FIELD_ftsf267ae_slot0,
+ FIELD_ftsf268ae_slot0,
+ FIELD_ftsf269ae_slot0,
+ FIELD_ftsf270ae_slot0,
+ FIELD_ftsf271ae_slot0,
+ FIELD_ftsf272ae_slot0,
+ FIELD_ftsf273ae_slot0,
+ FIELD_ftsf274ae_slot0,
+ FIELD_ftsf275ae_slot0,
+ FIELD_ftsf276ae_slot0,
+ FIELD_ftsf277ae_slot0,
+ FIELD_ftsf278ae_slot0,
+ FIELD_ftsf279ae_slot0,
+ FIELD_ftsf281ae_slot0,
+ FIELD_ftsf282ae_slot0,
+ FIELD_ftsf283ae_slot0,
+ FIELD_ftsf284ae_slot0,
+ FIELD_ftsf286ae_slot0,
+ FIELD_ftsf288ae_slot0,
+ FIELD_ftsf290ae_slot0,
+ FIELD_ftsf292ae_slot0,
+ FIELD_ftsf293,
+ FIELD_ftsf294ae_slot0,
+ FIELD_ftsf295ae_slot0,
+ FIELD_ftsf296ae_slot0,
+ FIELD_ftsf297ae_slot0,
+ FIELD_ftsf298ae_slot0,
+ FIELD_ftsf299ae_slot0,
+ FIELD_ftsf300ae_slot0,
+ FIELD_ftsf301ae_slot0,
+ FIELD_ftsf302ae_slot0,
+ FIELD_ftsf303ae_slot0,
+ FIELD_ftsf304ae_slot0,
+ FIELD_ftsf306ae_slot0,
+ FIELD_ftsf308ae_slot0,
+ FIELD_ftsf309ae_slot0,
+ FIELD_ftsf310ae_slot0,
+ FIELD_ftsf311ae_slot0,
+ FIELD_ftsf312ae_slot0,
+ FIELD_ftsf313ae_slot0,
+ FIELD_ftsf314ae_slot0,
+ FIELD_ftsf315ae_slot0,
+ FIELD_ftsf316ae_slot0,
+ FIELD_ftsf317ae_slot0,
+ FIELD_ftsf318ae_slot0,
+ FIELD_ftsf319,
+ FIELD_ftsf320ae_slot0,
+ FIELD_ftsf321,
+ FIELD_ftsf322ae_slot0,
+ FIELD_ftsf323ae_slot0,
+ FIELD_ftsf324ae_slot0,
+ FIELD_ftsf325ae_slot0,
+ FIELD_ftsf326ae_slot0,
+ FIELD_ftsf328ae_slot0,
+ FIELD_ftsf329ae_slot0,
+ FIELD_ftsf352ae_slot0,
+ FIELD_ftsf353,
+ FIELD_ftsf354ae_slot0,
+ FIELD_ftsf356ae_slot0,
+ FIELD_ftsf357,
+ FIELD_ftsf358ae_slot0,
+ FIELD_ftsf359ae_slot0,
+ FIELD_ftsf360ae_slot0,
+ FIELD_ftsf361ae_slot0,
+ FIELD_ftsf362ae_slot0,
+ FIELD_ftsf364ae_slot0,
+ FIELD_ftsf365ae_slot0,
+ FIELD_ftsf366ae_slot0,
+ FIELD_ftsf368ae_slot0,
+ FIELD_ftsf369ae_slot0,
+ FIELD__ar0,
+ FIELD__ar4,
+ FIELD__ar8,
+ FIELD__ar12,
+ FIELD__bt16,
+ FIELD__bs16,
+ FIELD__br16,
+ FIELD__brall
+};
+
+\f
+/* Functional units. */
+
+static xtensa_funcUnit_internal funcUnits[] = {
+ { "ae_add32", 1 },
+ { "ae_shift32x4", 1 },
+ { "ae_shift32x5", 1 },
+ { "ae_subshift", 1 }
+};
+
+enum xtensa_funcUnit_id {
+ FUNCUNIT_ae_add32,
+ FUNCUNIT_ae_shift32x4,
+ FUNCUNIT_ae_shift32x5,
+ FUNCUNIT_ae_subshift
+};
+
+\f
+/* Register files. */
+
+enum xtensa_regfile_id {
+ REGFILE_AR,
+ REGFILE_BR,
+ REGFILE_AE_PR,
+ REGFILE_AE_QR,
+ REGFILE_BR2,
+ REGFILE_BR4,
+ REGFILE_BR8,
+ REGFILE_BR16
+};
+
+static xtensa_regfile_internal regfiles[] = {
+ { "AR", "a", REGFILE_AR, 32, 32 },
+ { "BR", "b", REGFILE_BR, 1, 16 },
+ { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
+ { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
+ { "BR2", "b", REGFILE_BR, 2, 8 },
+ { "BR4", "b", REGFILE_BR, 4, 4 },
+ { "BR8", "b", REGFILE_BR, 8, 2 },
+ { "BR16", "b", REGFILE_BR, 16, 1 }
+};
+
+\f
+/* Interfaces. */
+
+static xtensa_interface_internal interfaces[] = {
+ { "RMPINT_Out", 12, 0, 0, 'o' },
+ { "RMPINT_In", 32, 0, 1, 'i' }
+};
+
+enum xtensa_interface_id {
+ INTERFACE_RMPINT_Out,
+ INTERFACE_RMPINT_In
+};
+
+
+/* Constant tables. */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ 0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+ 0xffffffff,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+ 0x8000,
+ 0x10000,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0xa,
+ 0xc,
+ 0x10,
+ 0x20,
+ 0x40,
+ 0x80,
+ 0x100,
+ 0
+};
+
+\f
+/* Instruction operands. */
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+ unsigned soffsetx4_out_0;
+ unsigned soffsetx4_in_0;
+ soffsetx4_in_0 = *valp & 0x3ffff;
+ soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+ *valp = soffsetx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+ unsigned soffsetx4_in_0;
+ unsigned soffsetx4_out_0;
+ soffsetx4_out_0 = *valp;
+ soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+ *valp = soffsetx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+ unsigned uimm12x8_out_0;
+ unsigned uimm12x8_in_0;
+ uimm12x8_in_0 = *valp & 0xfff;
+ uimm12x8_out_0 = uimm12x8_in_0 << 3;
+ *valp = uimm12x8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+ unsigned uimm12x8_in_0;
+ unsigned uimm12x8_out_0;
+ uimm12x8_out_0 = *valp;
+ uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+ *valp = uimm12x8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+ unsigned simm4_out_0;
+ unsigned simm4_in_0;
+ simm4_in_0 = *valp & 0xf;
+ simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+ *valp = simm4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+ unsigned simm4_in_0;
+ unsigned simm4_out_0;
+ simm4_out_0 = *valp;
+ simm4_in_0 = (simm4_out_0 & 0xf);
+ *valp = simm4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 32);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+ unsigned immrx4_out_0;
+ unsigned immrx4_in_0;
+ immrx4_in_0 = *valp & 0xf;
+ immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+ *valp = immrx4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+ unsigned immrx4_in_0;
+ unsigned immrx4_out_0;
+ immrx4_out_0 = *valp;
+ immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+ *valp = immrx4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+ unsigned lsi4x4_out_0;
+ unsigned lsi4x4_in_0;
+ lsi4x4_in_0 = *valp & 0xf;
+ lsi4x4_out_0 = lsi4x4_in_0 << 2;
+ *valp = lsi4x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+ unsigned lsi4x4_in_0;
+ unsigned lsi4x4_out_0;
+ lsi4x4_out_0 = *valp;
+ lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+ *valp = lsi4x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+ unsigned simm7_out_0;
+ unsigned simm7_in_0;
+ simm7_in_0 = *valp & 0x7f;
+ simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+ *valp = simm7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+ unsigned simm7_in_0;
+ unsigned simm7_out_0;
+ simm7_out_0 = *valp;
+ simm7_in_0 = (simm7_out_0 & 0x7f);
+ *valp = simm7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+ unsigned uimm6_out_0;
+ unsigned uimm6_in_0;
+ uimm6_in_0 = *valp & 0x3f;
+ uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+ *valp = uimm6_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+ unsigned uimm6_in_0;
+ unsigned uimm6_out_0;
+ uimm6_out_0 = *valp;
+ uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+ *valp = uimm6_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+ unsigned ai4const_out_0;
+ unsigned ai4const_in_0;
+ ai4const_in_0 = *valp & 0xf;
+ ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+ *valp = ai4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+ unsigned ai4const_in_0;
+ unsigned ai4const_out_0;
+ ai4const_out_0 = *valp;
+ switch (ai4const_out_0)
+ {
+ case 0xffffffff: ai4const_in_0 = 0; break;
+ case 0x1: ai4const_in_0 = 0x1; break;
+ case 0x2: ai4const_in_0 = 0x2; break;
+ case 0x3: ai4const_in_0 = 0x3; break;
+ case 0x4: ai4const_in_0 = 0x4; break;
+ case 0x5: ai4const_in_0 = 0x5; break;
+ case 0x6: ai4const_in_0 = 0x6; break;
+ case 0x7: ai4const_in_0 = 0x7; break;
+ case 0x8: ai4const_in_0 = 0x8; break;
+ case 0x9: ai4const_in_0 = 0x9; break;
+ case 0xa: ai4const_in_0 = 0xa; break;
+ case 0xb: ai4const_in_0 = 0xb; break;
+ case 0xc: ai4const_in_0 = 0xc; break;
+ case 0xd: ai4const_in_0 = 0xd; break;
+ case 0xe: ai4const_in_0 = 0xe; break;
+ default: ai4const_in_0 = 0xf; break;
+ }
+ *valp = ai4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+ unsigned b4const_out_0;
+ unsigned b4const_in_0;
+ b4const_in_0 = *valp & 0xf;
+ b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+ *valp = b4const_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+ unsigned b4const_in_0;
+ unsigned b4const_out_0;
+ b4const_out_0 = *valp;
+ switch (b4const_out_0)
+ {
+ case 0xffffffff: b4const_in_0 = 0; break;
+ case 0x1: b4const_in_0 = 0x1; break;
+ case 0x2: b4const_in_0 = 0x2; break;
+ case 0x3: b4const_in_0 = 0x3; break;
+ case 0x4: b4const_in_0 = 0x4; break;
+ case 0x5: b4const_in_0 = 0x5; break;
+ case 0x6: b4const_in_0 = 0x6; break;
+ case 0x7: b4const_in_0 = 0x7; break;
+ case 0x8: b4const_in_0 = 0x8; break;
+ case 0xa: b4const_in_0 = 0x9; break;
+ case 0xc: b4const_in_0 = 0xa; break;
+ case 0x10: b4const_in_0 = 0xb; break;
+ case 0x20: b4const_in_0 = 0xc; break;
+ case 0x40: b4const_in_0 = 0xd; break;
+ case 0x80: b4const_in_0 = 0xe; break;
+ default: b4const_in_0 = 0xf; break;
+ }
+ *valp = b4const_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+ unsigned b4constu_out_0;
+ unsigned b4constu_in_0;
+ b4constu_in_0 = *valp & 0xf;
+ b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+ *valp = b4constu_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+ unsigned b4constu_in_0;
+ unsigned b4constu_out_0;
+ b4constu_out_0 = *valp;
+ switch (b4constu_out_0)
+ {
+ case 0x8000: b4constu_in_0 = 0; break;
+ case 0x10000: b4constu_in_0 = 0x1; break;
+ case 0x2: b4constu_in_0 = 0x2; break;
+ case 0x3: b4constu_in_0 = 0x3; break;
+ case 0x4: b4constu_in_0 = 0x4; break;
+ case 0x5: b4constu_in_0 = 0x5; break;
+ case 0x6: b4constu_in_0 = 0x6; break;
+ case 0x7: b4constu_in_0 = 0x7; break;
+ case 0x8: b4constu_in_0 = 0x8; break;
+ case 0xa: b4constu_in_0 = 0x9; break;
+ case 0xc: b4constu_in_0 = 0xa; break;
+ case 0x10: b4constu_in_0 = 0xb; break;
+ case 0x20: b4constu_in_0 = 0xc; break;
+ case 0x40: b4constu_in_0 = 0xd; break;
+ case 0x80: b4constu_in_0 = 0xe; break;
+ default: b4constu_in_0 = 0xf; break;
+ }
+ *valp = b4constu_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+ unsigned uimm8_out_0;
+ unsigned uimm8_in_0;
+ uimm8_in_0 = *valp & 0xff;
+ uimm8_out_0 = uimm8_in_0;
+ *valp = uimm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+ unsigned uimm8_in_0;
+ unsigned uimm8_out_0;
+ uimm8_out_0 = *valp;
+ uimm8_in_0 = (uimm8_out_0 & 0xff);
+ *valp = uimm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+ unsigned uimm8x2_out_0;
+ unsigned uimm8x2_in_0;
+ uimm8x2_in_0 = *valp & 0xff;
+ uimm8x2_out_0 = uimm8x2_in_0 << 1;
+ *valp = uimm8x2_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+ unsigned uimm8x2_in_0;
+ unsigned uimm8x2_out_0;
+ uimm8x2_out_0 = *valp;
+ uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+ *valp = uimm8x2_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+ unsigned uimm8x4_out_0;
+ unsigned uimm8x4_in_0;
+ uimm8x4_in_0 = *valp & 0xff;
+ uimm8x4_out_0 = uimm8x4_in_0 << 2;
+ *valp = uimm8x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+ unsigned uimm8x4_in_0;
+ unsigned uimm8x4_out_0;
+ uimm8x4_out_0 = *valp;
+ uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+ *valp = uimm8x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+ unsigned uimm4x16_out_0;
+ unsigned uimm4x16_in_0;
+ uimm4x16_in_0 = *valp & 0xf;
+ uimm4x16_out_0 = uimm4x16_in_0 << 4;
+ *valp = uimm4x16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+ unsigned uimm4x16_in_0;
+ unsigned uimm4x16_out_0;
+ uimm4x16_out_0 = *valp;
+ uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+ *valp = uimm4x16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+ unsigned simm8_out_0;
+ unsigned simm8_in_0;
+ simm8_in_0 = *valp & 0xff;
+ simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+ *valp = simm8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+ unsigned simm8_in_0;
+ unsigned simm8_out_0;
+ simm8_out_0 = *valp;
+ simm8_in_0 = (simm8_out_0 & 0xff);
+ *valp = simm8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+ unsigned simm8x256_out_0;
+ unsigned simm8x256_in_0;
+ simm8x256_in_0 = *valp & 0xff;
+ simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+ *valp = simm8x256_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+ unsigned simm8x256_in_0;
+ unsigned simm8x256_out_0;
+ simm8x256_out_0 = *valp;
+ simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+ *valp = simm8x256_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+ unsigned simm12b_out_0;
+ unsigned simm12b_in_0;
+ simm12b_in_0 = *valp & 0xfff;
+ simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+ *valp = simm12b_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+ unsigned simm12b_in_0;
+ unsigned simm12b_out_0;
+ simm12b_out_0 = *valp;
+ simm12b_in_0 = (simm12b_out_0 & 0xfff);
+ *valp = simm12b_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+ unsigned msalp32_out_0;
+ unsigned msalp32_in_0;
+ msalp32_in_0 = *valp & 0x1f;
+ msalp32_out_0 = 0x20 - msalp32_in_0;
+ *valp = msalp32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+ unsigned msalp32_in_0;
+ unsigned msalp32_out_0;
+ msalp32_out_0 = *valp;
+ msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+ *valp = msalp32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+ unsigned op2p1_out_0;
+ unsigned op2p1_in_0;
+ op2p1_in_0 = *valp & 0xf;
+ op2p1_out_0 = op2p1_in_0 + 0x1;
+ *valp = op2p1_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+ unsigned op2p1_in_0;
+ unsigned op2p1_out_0;
+ op2p1_out_0 = *valp;
+ op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+ *valp = op2p1_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+ unsigned label8_out_0;
+ unsigned label8_in_0;
+ label8_in_0 = *valp & 0xff;
+ label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+ *valp = label8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+ unsigned label8_in_0;
+ unsigned label8_out_0;
+ label8_out_0 = *valp;
+ label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+ *valp = label8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+ unsigned ulabel8_out_0;
+ unsigned ulabel8_in_0;
+ ulabel8_in_0 = *valp & 0xff;
+ ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+ *valp = ulabel8_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+ unsigned ulabel8_in_0;
+ unsigned ulabel8_out_0;
+ ulabel8_out_0 = *valp;
+ ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+ *valp = ulabel8_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+ unsigned label12_out_0;
+ unsigned label12_in_0;
+ label12_in_0 = *valp & 0xfff;
+ label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+ *valp = label12_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+ unsigned label12_in_0;
+ unsigned label12_out_0;
+ label12_out_0 = *valp;
+ label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+ *valp = label12_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+ unsigned soffset_out_0;
+ unsigned soffset_in_0;
+ soffset_in_0 = *valp & 0x3ffff;
+ soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+ *valp = soffset_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+ unsigned soffset_in_0;
+ unsigned soffset_out_0;
+ soffset_out_0 = *valp;
+ soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+ *valp = soffset_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+ unsigned uimm16x4_out_0;
+ unsigned uimm16x4_in_0;
+ uimm16x4_in_0 = *valp & 0xffff;
+ uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+ *valp = uimm16x4_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+ unsigned uimm16x4_in_0;
+ unsigned uimm16x4_out_0;
+ uimm16x4_out_0 = *valp;
+ uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+ *valp = uimm16x4_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+ unsigned bbi_out_0;
+ unsigned bbi_in_0;
+ bbi_in_0 = *valp & 0x1f;
+ bbi_out_0 = (0 << 5) | bbi_in_0;
+ *valp = bbi_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+ unsigned bbi_in_0;
+ unsigned bbi_out_0;
+ bbi_out_0 = *valp;
+ bbi_in_0 = (bbi_out_0 & 0x1f);
+ *valp = bbi_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+ unsigned s_out_0;
+ unsigned s_in_0;
+ s_in_0 = *valp & 0xf;
+ s_out_0 = (0 << 4) | s_in_0;
+ *valp = s_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+ unsigned s_in_0;
+ unsigned s_out_0;
+ s_out_0 = *valp;
+ s_in_0 = (s_out_0 & 0xf);
+ *valp = s_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+ unsigned immt_out_0;
+ unsigned immt_in_0;
+ immt_in_0 = *valp & 0xf;
+ immt_out_0 = immt_in_0;
+ *valp = immt_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+ unsigned immt_in_0;
+ unsigned immt_out_0;
+ immt_out_0 = *valp;
+ immt_in_0 = immt_out_0 & 0xf;
+ *valp = immt_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR2_decode (uint32 *valp)
+{
+ *valp = *valp << 1;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR2_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 1) != 0);
+ *valp = *valp >> 1;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR4_decode (uint32 *valp)
+{
+ *valp = *valp << 2;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR4_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 3) != 0);
+ *valp = *valp >> 2;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR8_decode (uint32 *valp)
+{
+ *valp = *valp << 3;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR8_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 7) != 0);
+ *valp = *valp >> 3;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_BR16_decode (uint32 *valp)
+{
+ *valp = *valp << 4;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR16_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 16) || ((*valp & 15) != 0);
+ *valp = *valp >> 4;
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+ unsigned tp7_out_0;
+ unsigned tp7_in_0;
+ tp7_in_0 = *valp & 0xf;
+ tp7_out_0 = tp7_in_0 + 0x7;
+ *valp = tp7_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+ unsigned tp7_in_0;
+ unsigned tp7_out_0;
+ tp7_out_0 = *valp;
+ tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+ *valp = tp7_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_out_0;
+ unsigned xt_wbr15_label_in_0;
+ xt_wbr15_label_in_0 = *valp & 0x7fff;
+ xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+ *valp = xt_wbr15_label_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+ unsigned xt_wbr15_label_in_0;
+ unsigned xt_wbr15_label_out_0;
+ xt_wbr15_label_out_0 = *valp;
+ xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+ *valp = xt_wbr15_label_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
+{
+ unsigned ae_samt32_out_0;
+ unsigned ae_samt32_in_0;
+ ae_samt32_in_0 = *valp & 0x1f;
+ ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
+ *valp = ae_samt32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
+{
+ unsigned ae_samt32_in_0;
+ unsigned ae_samt32_out_0;
+ ae_samt32_out_0 = *valp;
+ ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
+ *valp = ae_samt32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 8);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
+{
+ int error;
+ error = (*valp >= 4);
+ return error;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
+{
+ unsigned ae_lsimm16_out_0;
+ unsigned ae_lsimm16_in_0;
+ ae_lsimm16_in_0 = *valp & 0xf;
+ ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
+ *valp = ae_lsimm16_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
+{
+ unsigned ae_lsimm16_in_0;
+ unsigned ae_lsimm16_out_0;
+ ae_lsimm16_out_0 = *valp;
+ ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
+ *valp = ae_lsimm16_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
+{
+ unsigned ae_lsimm32_out_0;
+ unsigned ae_lsimm32_in_0;
+ ae_lsimm32_in_0 = *valp & 0xf;
+ ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
+ *valp = ae_lsimm32_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
+{
+ unsigned ae_lsimm32_in_0;
+ unsigned ae_lsimm32_out_0;
+ ae_lsimm32_out_0 = *valp;
+ ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
+ *valp = ae_lsimm32_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
+{
+ unsigned ae_lsimm64_out_0;
+ unsigned ae_lsimm64_in_0;
+ ae_lsimm64_in_0 = *valp & 0xf;
+ ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
+ *valp = ae_lsimm64_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
+{
+ unsigned ae_lsimm64_in_0;
+ unsigned ae_lsimm64_out_0;
+ ae_lsimm64_out_0 = *valp;
+ ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
+ *valp = ae_lsimm64_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
+{
+ unsigned ae_samt64_out_0;
+ unsigned ae_samt64_in_0;
+ ae_samt64_in_0 = *valp & 0x3f;
+ ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
+ *valp = ae_samt64_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
+{
+ unsigned ae_samt64_in_0;
+ unsigned ae_samt64_out_0;
+ ae_samt64_out_0 = *valp;
+ ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
+ *valp = ae_samt64_in_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
+{
+ unsigned ae_ohba_out_0;
+ unsigned ae_ohba_in_0;
+ ae_ohba_in_0 = *valp & 0xf;
+ ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
+ *valp = ae_ohba_out_0;
+ return 0;
+}
+
+static int
+OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
+{
+ unsigned ae_ohba_in_0;
+ unsigned ae_ohba_out_0;
+ ae_ohba_out_0 = *valp;
+ ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
+ *valp = ae_ohba_in_0;
+ return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += (pc & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += ((pc + 3) & ~0x3);
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+ *valp -= pc;
+ return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+ *valp += pc;
+ return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+ { "soffsetx4", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+ Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+ { "uimm12x8", FIELD_imm12, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+ 0, 0 },
+ { "simm4", FIELD_mn, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+ 0, 0 },
+ { "arr", FIELD_r, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ars", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "art", FIELD_t, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+ 0, 0 },
+ { "ar0", FIELD__ar0, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+ 0, 0 },
+ { "ar4", FIELD__ar4, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+ 0, 0 },
+ { "ar8", FIELD__ar8, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+ 0, 0 },
+ { "ar12", FIELD__ar12, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+ 0, 0 },
+ { "ars_entry", FIELD_s, REGFILE_AR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+ 0, 0 },
+ { "immrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+ 0, 0 },
+ { "lsi4x4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm7", FIELD_imm7, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+ 0, 0 },
+ { "uimm6", FIELD_imm6, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+ Operand_uimm6_ator, Operand_uimm6_rtoa },
+ { "ai4const", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+ 0, 0 },
+ { "b4const", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+ 0, 0 },
+ { "b4constu", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+ 0, 0 },
+ { "uimm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+ 0, 0 },
+ { "uimm8x2", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+ 0, 0 },
+ { "uimm8x4", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+ 0, 0 },
+ { "uimm4x16", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+ 0, 0 },
+ { "uimmrx4", FIELD_r, -1, 0,
+ 0,
+ OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+ 0, 0 },
+ { "simm8", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+ 0, 0 },
+ { "simm8x256", FIELD_imm8, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+ 0, 0 },
+ { "simm12b", FIELD_imm12b, -1, 0,
+ 0,
+ OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+ 0, 0 },
+ { "msalp32", FIELD_sal, -1, 0,
+ 0,
+ OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+ 0, 0 },
+ { "op2p1", FIELD_op2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+ 0, 0 },
+ { "label8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+ Operand_label8_ator, Operand_label8_rtoa },
+ { "ulabel8", FIELD_imm8, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
+ Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+ { "label12", FIELD_imm12, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+ Operand_label12_ator, Operand_label12_rtoa },
+ { "soffset", FIELD_offset, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_soffset_ator, Operand_soffset_rtoa },
+ { "uimm16x4", FIELD_imm16, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+ Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+ { "bbi", FIELD_bbi, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sae", FIELD_sae, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sas", FIELD_sas, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "sargt", FIELD_sargt, -1, 0,
+ 0,
+ OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+ 0, 0 },
+ { "s", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+ 0, 0 },
+ { "immt", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "imms", FIELD_s, -1, 0,
+ 0,
+ OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+ 0, 0 },
+ { "bt", FIELD_t, REGFILE_BR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+ 0, 0 },
+ { "bs", FIELD_s, REGFILE_BR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+ 0, 0 },
+ { "br", FIELD_r, REGFILE_BR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+ 0, 0 },
+ { "bt2", FIELD_t2, REGFILE_BR, 2,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+ 0, 0 },
+ { "bs2", FIELD_s2, REGFILE_BR, 2,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+ 0, 0 },
+ { "br2", FIELD_r2, REGFILE_BR, 2,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+ 0, 0 },
+ { "bt4", FIELD_t4, REGFILE_BR, 4,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+ 0, 0 },
+ { "bs4", FIELD_s4, REGFILE_BR, 4,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+ 0, 0 },
+ { "br4", FIELD_r4, REGFILE_BR, 4,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+ 0, 0 },
+ { "bt8", FIELD_t8, REGFILE_BR, 8,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+ 0, 0 },
+ { "bs8", FIELD_s8, REGFILE_BR, 8,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+ 0, 0 },
+ { "br8", FIELD_r8, REGFILE_BR, 8,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+ 0, 0 },
+ { "bt16", FIELD__bt16, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "bs16", FIELD__bs16, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "br16", FIELD__br16, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "brall", FIELD__brall, REGFILE_BR, 16,
+ XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+ OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+ 0, 0 },
+ { "tp7", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+ 0, 0 },
+ { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+ Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+ { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+ XTENSA_OPERAND_IS_PCRELATIVE,
+ OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+ Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+ { "ae_samt32", FIELD_ftsf14, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
+ 0, 0 },
+ { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "ae_lsimm16", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
+ 0, 0 },
+ { "ae_lsimm32", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
+ 0, 0 },
+ { "ae_lsimm64", FIELD_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
+ 0, 0 },
+ { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
+ 0, 0 },
+ { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
+ 0, 0 },
+ { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
+ 0,
+ OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
+ 0, 0 },
+ { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+ 0, 0 },
+ { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
+ XTENSA_OPERAND_IS_REGISTER,
+ OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+ 0, 0 },
+ { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+ { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+ { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+ { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+ { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+ { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+ { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+ { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+ { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+ { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+ { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+ { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+ { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+ { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+ { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
+ { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
+ { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
+ { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
+ { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
+ { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
+ { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
+ { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
+ { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
+ { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf208", FIELD_ftsf208, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf209ae_slot1", FIELD_ftsf209ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf211ae_slot1", FIELD_ftsf211ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf330ae_slot1", FIELD_ftsf330ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf332ae_slot1", FIELD_ftsf332ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf338", FIELD_ftsf338, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf340", FIELD_ftsf340, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf346ae_slot1", FIELD_ftsf346ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf347", FIELD_ftsf347, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
+ { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf216ae_slot0", FIELD_ftsf216ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf217", FIELD_ftsf217, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
+ { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+ OPERAND_soffsetx4,
+ OPERAND_uimm12x8,
+ OPERAND_simm4,
+ OPERAND_arr,
+ OPERAND_ars,
+ OPERAND__ars_invisible,
+ OPERAND_art,
+ OPERAND_ar0,
+ OPERAND_ar4,
+ OPERAND_ar8,
+ OPERAND_ar12,
+ OPERAND_ars_entry,
+ OPERAND_immrx4,
+ OPERAND_lsi4x4,
+ OPERAND_simm7,
+ OPERAND_uimm6,
+ OPERAND_ai4const,
+ OPERAND_b4const,
+ OPERAND_b4constu,
+ OPERAND_uimm8,
+ OPERAND_uimm8x2,
+ OPERAND_uimm8x4,
+ OPERAND_uimm4x16,
+ OPERAND_uimmrx4,
+ OPERAND_simm8,
+ OPERAND_simm8x256,
+ OPERAND_simm12b,
+ OPERAND_msalp32,
+ OPERAND_op2p1,
+ OPERAND_label8,
+ OPERAND_ulabel8,
+ OPERAND_label12,
+ OPERAND_soffset,
+ OPERAND_uimm16x4,
+ OPERAND_bbi,
+ OPERAND_sae,
+ OPERAND_sas,
+ OPERAND_sargt,
+ OPERAND_s,
+ OPERAND_immt,
+ OPERAND_imms,
+ OPERAND_bt,
+ OPERAND_bs,
+ OPERAND_br,
+ OPERAND_bt2,
+ OPERAND_bs2,
+ OPERAND_br2,
+ OPERAND_bt4,
+ OPERAND_bs4,
+ OPERAND_br4,
+ OPERAND_bt8,
+ OPERAND_bs8,
+ OPERAND_br8,
+ OPERAND_bt16,
+ OPERAND_bs16,
+ OPERAND_br16,
+ OPERAND_brall,
+ OPERAND_tp7,
+ OPERAND_xt_wbr15_label,
+ OPERAND_xt_wbr18_label,
+ OPERAND_ae_samt32,
+ OPERAND_pr0,
+ OPERAND_qr0,
+ OPERAND_mac_qr0,
+ OPERAND_ae_lsimm16,
+ OPERAND_ae_lsimm32,
+ OPERAND_ae_lsimm64,
+ OPERAND_ae_samt64,
+ OPERAND_ae_ohba,
+ OPERAND_ae_ohba2,
+ OPERAND_pr,
+ OPERAND_cvt_pr,
+ OPERAND_qr0_rw,
+ OPERAND_mac_qr0_rw,
+ OPERAND_qr1_w,
+ OPERAND_mac_qr1_w,
+ OPERAND_ps,
+ OPERAND_alupppb_ps,
+ OPERAND_t,
+ OPERAND_bbi4,
+ OPERAND_imm12,
+ OPERAND_imm8,
+ OPERAND_imm12b,
+ OPERAND_imm16,
+ OPERAND_m,
+ OPERAND_n,
+ OPERAND_offset,
+ OPERAND_op0,
+ OPERAND_op1,
+ OPERAND_op2,
+ OPERAND_r,
+ OPERAND_sa4,
+ OPERAND_sae4,
+ OPERAND_sal,
+ OPERAND_sas4,
+ OPERAND_sr,
+ OPERAND_st,
+ OPERAND_thi3,
+ OPERAND_imm4,
+ OPERAND_mn,
+ OPERAND_i,
+ OPERAND_imm6lo,
+ OPERAND_imm6hi,
+ OPERAND_imm7lo,
+ OPERAND_imm7hi,
+ OPERAND_z,
+ OPERAND_imm6,
+ OPERAND_imm7,
+ OPERAND_t2,
+ OPERAND_s2,
+ OPERAND_r2,
+ OPERAND_t4,
+ OPERAND_s4,
+ OPERAND_r4,
+ OPERAND_t8,
+ OPERAND_s8,
+ OPERAND_r8,
+ OPERAND_xt_wbr15_imm,
+ OPERAND_xt_wbr18_imm,
+ OPERAND_ae_r3,
+ OPERAND_ae_s_non_samt,
+ OPERAND_ae_s3,
+ OPERAND_ae_r32,
+ OPERAND_ae_samt_s_t,
+ OPERAND_ae_r20,
+ OPERAND_ae_r10,
+ OPERAND_ae_s20,
+ OPERAND_ae_fld_ohba,
+ OPERAND_ae_fld_ohba2,
+ OPERAND_op0_s3,
+ OPERAND_ftsf12,
+ OPERAND_ftsf13,
+ OPERAND_ftsf14,
+ OPERAND_ftsf21ae_slot1,
+ OPERAND_ftsf22ae_slot1,
+ OPERAND_ftsf23ae_slot1,
+ OPERAND_ftsf24ae_slot1,
+ OPERAND_ftsf25ae_slot1,
+ OPERAND_ftsf26ae_slot1,
+ OPERAND_ftsf27ae_slot1,
+ OPERAND_ftsf28ae_slot1,
+ OPERAND_ftsf29ae_slot1,
+ OPERAND_ftsf30ae_slot1,
+ OPERAND_ftsf31ae_slot1,
+ OPERAND_ftsf32ae_slot1,
+ OPERAND_ftsf33ae_slot1,
+ OPERAND_ftsf34ae_slot1,
+ OPERAND_ftsf35ae_slot1,
+ OPERAND_ftsf36ae_slot1,
+ OPERAND_ftsf37ae_slot1,
+ OPERAND_ftsf38ae_slot1,
+ OPERAND_ftsf39ae_slot1,
+ OPERAND_ftsf40ae_slot1,
+ OPERAND_ftsf41ae_slot1,
+ OPERAND_ftsf42ae_slot1,
+ OPERAND_ftsf43ae_slot1,
+ OPERAND_ftsf44ae_slot1,
+ OPERAND_ftsf45ae_slot1,
+ OPERAND_ftsf46ae_slot1,
+ OPERAND_ftsf47ae_slot1,
+ OPERAND_ftsf48ae_slot1,
+ OPERAND_ftsf49ae_slot1,
+ OPERAND_ftsf50ae_slot1,
+ OPERAND_ftsf51ae_slot1,
+ OPERAND_ftsf52ae_slot1,
+ OPERAND_ftsf53ae_slot1,
+ OPERAND_ftsf54ae_slot1,
+ OPERAND_ftsf55ae_slot1,
+ OPERAND_ftsf56ae_slot1,
+ OPERAND_ftsf57ae_slot1,
+ OPERAND_ftsf58ae_slot1,
+ OPERAND_ftsf59ae_slot1,
+ OPERAND_ftsf60ae_slot1,
+ OPERAND_ftsf61ae_slot1,
+ OPERAND_ftsf63ae_slot1,
+ OPERAND_ftsf64ae_slot1,
+ OPERAND_ftsf66ae_slot1,
+ OPERAND_ftsf67ae_slot1,
+ OPERAND_ftsf69ae_slot1,
+ OPERAND_ftsf71ae_slot1,
+ OPERAND_ftsf72ae_slot1,
+ OPERAND_ftsf73ae_slot1,
+ OPERAND_ftsf75ae_slot1,
+ OPERAND_ftsf76ae_slot1,
+ OPERAND_ftsf77ae_slot1,
+ OPERAND_ftsf78ae_slot1,
+ OPERAND_ftsf79ae_slot1,
+ OPERAND_ftsf80ae_slot1,
+ OPERAND_ftsf81ae_slot1,
+ OPERAND_ftsf82ae_slot1,
+ OPERAND_ftsf84ae_slot1,
+ OPERAND_ftsf86ae_slot1,
+ OPERAND_ftsf87ae_slot1,
+ OPERAND_ftsf88ae_slot1,
+ OPERAND_ftsf89ae_slot1,
+ OPERAND_ftsf90ae_slot1,
+ OPERAND_ftsf91ae_slot1,
+ OPERAND_ftsf92ae_slot1,
+ OPERAND_ftsf94ae_slot1,
+ OPERAND_ftsf96ae_slot1,
+ OPERAND_ftsf97ae_slot1,
+ OPERAND_ftsf98ae_slot1,
+ OPERAND_ftsf99ae_slot1,
+ OPERAND_ftsf100ae_slot1,
+ OPERAND_ftsf101ae_slot1,
+ OPERAND_ftsf103ae_slot1,
+ OPERAND_ftsf104ae_slot1,
+ OPERAND_ftsf105ae_slot1,
+ OPERAND_ftsf106ae_slot1,
+ OPERAND_ftsf107ae_slot1,
+ OPERAND_ftsf108ae_slot1,
+ OPERAND_ftsf109ae_slot1,
+ OPERAND_ftsf110ae_slot1,
+ OPERAND_ftsf111ae_slot1,
+ OPERAND_ftsf112ae_slot1,
+ OPERAND_ftsf113ae_slot1,
+ OPERAND_ftsf114ae_slot1,
+ OPERAND_ftsf115ae_slot1,
+ OPERAND_ftsf116ae_slot1,
+ OPERAND_ftsf118ae_slot1,
+ OPERAND_ftsf119ae_slot1,
+ OPERAND_ftsf120ae_slot1,
+ OPERAND_ftsf122ae_slot1,
+ OPERAND_ftsf124ae_slot1,
+ OPERAND_ftsf125ae_slot1,
+ OPERAND_ftsf126ae_slot1,
+ OPERAND_ftsf127ae_slot1,
+ OPERAND_ftsf128ae_slot1,
+ OPERAND_ftsf129ae_slot1,
+ OPERAND_ftsf130ae_slot1,
+ OPERAND_ftsf131ae_slot1,
+ OPERAND_ftsf132ae_slot1,
+ OPERAND_ftsf133ae_slot1,
+ OPERAND_ftsf134ae_slot1,
+ OPERAND_ftsf135ae_slot1,
+ OPERAND_ftsf136ae_slot1,
+ OPERAND_ftsf137ae_slot1,
+ OPERAND_ftsf138ae_slot1,
+ OPERAND_ftsf139ae_slot1,
+ OPERAND_ftsf140ae_slot1,
+ OPERAND_ftsf141ae_slot1,
+ OPERAND_ftsf142ae_slot1,
+ OPERAND_ftsf143ae_slot1,
+ OPERAND_ftsf144ae_slot1,
+ OPERAND_ftsf145ae_slot1,
+ OPERAND_ftsf146ae_slot1,
+ OPERAND_ftsf147ae_slot1,
+ OPERAND_ftsf148ae_slot1,
+ OPERAND_ftsf149ae_slot1,
+ OPERAND_ftsf150ae_slot1,
+ OPERAND_ftsf151ae_slot1,
+ OPERAND_ftsf152ae_slot1,
+ OPERAND_ftsf153ae_slot1,
+ OPERAND_ftsf154ae_slot1,
+ OPERAND_ftsf155ae_slot1,
+ OPERAND_ftsf156ae_slot1,
+ OPERAND_ftsf157ae_slot1,
+ OPERAND_ftsf158ae_slot1,
+ OPERAND_ftsf159ae_slot1,
+ OPERAND_ftsf160ae_slot1,
+ OPERAND_ftsf161ae_slot1,
+ OPERAND_ftsf162ae_slot1,
+ OPERAND_ftsf163ae_slot1,
+ OPERAND_ftsf164ae_slot1,
+ OPERAND_ftsf165ae_slot1,
+ OPERAND_ftsf166ae_slot1,
+ OPERAND_ftsf167ae_slot1,
+ OPERAND_ftsf168ae_slot1,
+ OPERAND_ftsf169ae_slot1,
+ OPERAND_ftsf170ae_slot1,
+ OPERAND_ftsf171ae_slot1,
+ OPERAND_ftsf172ae_slot1,
+ OPERAND_ftsf173ae_slot1,
+ OPERAND_ftsf174ae_slot1,
+ OPERAND_ftsf175ae_slot1,
+ OPERAND_ftsf176ae_slot1,
+ OPERAND_ftsf177ae_slot1,
+ OPERAND_ftsf178ae_slot1,
+ OPERAND_ftsf179ae_slot1,
+ OPERAND_ftsf180ae_slot1,
+ OPERAND_ftsf181ae_slot1,
+ OPERAND_ftsf182ae_slot1,
+ OPERAND_ftsf183ae_slot1,
+ OPERAND_ftsf184ae_slot1,
+ OPERAND_ftsf185ae_slot1,
+ OPERAND_ftsf186ae_slot1,
+ OPERAND_ftsf187ae_slot1,
+ OPERAND_ftsf188ae_slot1,
+ OPERAND_ftsf189ae_slot1,
+ OPERAND_ftsf190ae_slot1,
+ OPERAND_ftsf191ae_slot1,
+ OPERAND_ftsf192ae_slot1,
+ OPERAND_ftsf193ae_slot1,
+ OPERAND_ftsf194ae_slot1,
+ OPERAND_ftsf195ae_slot1,
+ OPERAND_ftsf196ae_slot1,
+ OPERAND_ftsf197ae_slot1,
+ OPERAND_ftsf198ae_slot1,
+ OPERAND_ftsf199ae_slot1,
+ OPERAND_ftsf200ae_slot1,
+ OPERAND_ftsf201ae_slot1,
+ OPERAND_ftsf202ae_slot1,
+ OPERAND_ftsf203ae_slot1,
+ OPERAND_ftsf204ae_slot1,
+ OPERAND_ftsf205ae_slot1,
+ OPERAND_ftsf206ae_slot1,
+ OPERAND_ftsf207ae_slot1,
+ OPERAND_ftsf208,
+ OPERAND_ftsf209ae_slot1,
+ OPERAND_ftsf210ae_slot1,
+ OPERAND_ftsf211ae_slot1,
+ OPERAND_ftsf330ae_slot1,
+ OPERAND_ftsf332ae_slot1,
+ OPERAND_ftsf334ae_slot1,
+ OPERAND_ftsf336ae_slot1,
+ OPERAND_ftsf337ae_slot1,
+ OPERAND_ftsf338,
+ OPERAND_ftsf339ae_slot1,
+ OPERAND_ftsf340,
+ OPERAND_ftsf341ae_slot1,
+ OPERAND_ftsf342ae_slot1,
+ OPERAND_ftsf343ae_slot1,
+ OPERAND_ftsf344ae_slot1,
+ OPERAND_ftsf346ae_slot1,
+ OPERAND_ftsf347,
+ OPERAND_ftsf348ae_slot1,
+ OPERAND_ftsf349ae_slot1,
+ OPERAND_ftsf350ae_slot1,
+ OPERAND_op0_s4,
+ OPERAND_ftsf212ae_slot0,
+ OPERAND_ftsf213ae_slot0,
+ OPERAND_ftsf214ae_slot0,
+ OPERAND_ftsf215ae_slot0,
+ OPERAND_ftsf216ae_slot0,
+ OPERAND_ftsf217,
+ OPERAND_ftsf218ae_slot0,
+ OPERAND_ftsf219ae_slot0,
+ OPERAND_ftsf220ae_slot0,
+ OPERAND_ftsf221ae_slot0,
+ OPERAND_ftsf222ae_slot0,
+ OPERAND_ftsf223ae_slot0,
+ OPERAND_ftsf224ae_slot0,
+ OPERAND_ftsf225ae_slot0,
+ OPERAND_ftsf226ae_slot0,
+ OPERAND_ftsf227ae_slot0,
+ OPERAND_ftsf228ae_slot0,
+ OPERAND_ftsf229ae_slot0,
+ OPERAND_ftsf230ae_slot0,
+ OPERAND_ftsf231ae_slot0,
+ OPERAND_ftsf232ae_slot0,
+ OPERAND_ftsf233ae_slot0,
+ OPERAND_ftsf234ae_slot0,
+ OPERAND_ftsf235ae_slot0,
+ OPERAND_ftsf236ae_slot0,
+ OPERAND_ftsf237ae_slot0,
+ OPERAND_ftsf238ae_slot0,
+ OPERAND_ftsf239ae_slot0,
+ OPERAND_ftsf240ae_slot0,
+ OPERAND_ftsf241ae_slot0,
+ OPERAND_ftsf242ae_slot0,
+ OPERAND_ftsf243ae_slot0,
+ OPERAND_ftsf244ae_slot0,
+ OPERAND_ftsf245ae_slot0,
+ OPERAND_ftsf246ae_slot0,
+ OPERAND_ftsf247ae_slot0,
+ OPERAND_ftsf248ae_slot0,
+ OPERAND_ftsf249ae_slot0,
+ OPERAND_ftsf250ae_slot0,
+ OPERAND_ftsf251ae_slot0,
+ OPERAND_ftsf252ae_slot0,
+ OPERAND_ftsf253ae_slot0,
+ OPERAND_ftsf254ae_slot0,
+ OPERAND_ftsf255ae_slot0,
+ OPERAND_ftsf256ae_slot0,
+ OPERAND_ftsf257ae_slot0,
+ OPERAND_ftsf258ae_slot0,
+ OPERAND_ftsf259ae_slot0,
+ OPERAND_ftsf260ae_slot0,
+ OPERAND_ftsf261ae_slot0,
+ OPERAND_ftsf262ae_slot0,
+ OPERAND_ftsf263ae_slot0,
+ OPERAND_ftsf264ae_slot0,
+ OPERAND_ftsf265ae_slot0,
+ OPERAND_ftsf266ae_slot0,
+ OPERAND_ftsf267ae_slot0,
+ OPERAND_ftsf268ae_slot0,
+ OPERAND_ftsf269ae_slot0,
+ OPERAND_ftsf270ae_slot0,
+ OPERAND_ftsf271ae_slot0,
+ OPERAND_ftsf272ae_slot0,
+ OPERAND_ftsf273ae_slot0,
+ OPERAND_ftsf274ae_slot0,
+ OPERAND_ftsf275ae_slot0,
+ OPERAND_ftsf276ae_slot0,
+ OPERAND_ftsf277ae_slot0,
+ OPERAND_ftsf278ae_slot0,
+ OPERAND_ftsf279ae_slot0,
+ OPERAND_ftsf281ae_slot0,
+ OPERAND_ftsf282ae_slot0,
+ OPERAND_ftsf283ae_slot0,
+ OPERAND_ftsf284ae_slot0,
+ OPERAND_ftsf286ae_slot0,
+ OPERAND_ftsf288ae_slot0,
+ OPERAND_ftsf290ae_slot0,
+ OPERAND_ftsf292ae_slot0,
+ OPERAND_ftsf293,
+ OPERAND_ftsf294ae_slot0,
+ OPERAND_ftsf295ae_slot0,
+ OPERAND_ftsf296ae_slot0,
+ OPERAND_ftsf297ae_slot0,
+ OPERAND_ftsf298ae_slot0,
+ OPERAND_ftsf299ae_slot0,
+ OPERAND_ftsf300ae_slot0,
+ OPERAND_ftsf301ae_slot0,
+ OPERAND_ftsf302ae_slot0,
+ OPERAND_ftsf303ae_slot0,
+ OPERAND_ftsf304ae_slot0,
+ OPERAND_ftsf306ae_slot0,
+ OPERAND_ftsf308ae_slot0,
+ OPERAND_ftsf309ae_slot0,
+ OPERAND_ftsf310ae_slot0,
+ OPERAND_ftsf311ae_slot0,
+ OPERAND_ftsf312ae_slot0,
+ OPERAND_ftsf313ae_slot0,
+ OPERAND_ftsf314ae_slot0,
+ OPERAND_ftsf315ae_slot0,
+ OPERAND_ftsf316ae_slot0,
+ OPERAND_ftsf317ae_slot0,
+ OPERAND_ftsf318ae_slot0,
+ OPERAND_ftsf319,
+ OPERAND_ftsf320ae_slot0,
+ OPERAND_ftsf321,
+ OPERAND_ftsf322ae_slot0,
+ OPERAND_ftsf323ae_slot0,
+ OPERAND_ftsf324ae_slot0,
+ OPERAND_ftsf325ae_slot0,
+ OPERAND_ftsf326ae_slot0,
+ OPERAND_ftsf328ae_slot0,
+ OPERAND_ftsf329ae_slot0,
+ OPERAND_ftsf352ae_slot0,
+ OPERAND_ftsf353,
+ OPERAND_ftsf354ae_slot0,
+ OPERAND_ftsf356ae_slot0,
+ OPERAND_ftsf357,
+ OPERAND_ftsf358ae_slot0,
+ OPERAND_ftsf359ae_slot0,
+ OPERAND_ftsf360ae_slot0,
+ OPERAND_ftsf361ae_slot0,
+ OPERAND_ftsf362ae_slot0,
+ OPERAND_ftsf364ae_slot0,
+ OPERAND_ftsf365ae_slot0,
+ OPERAND_ftsf366ae_slot0,
+ OPERAND_ftsf368ae_slot0,
+ OPERAND_ftsf369ae_slot0
+};
+
+\f
+/* Iclass table. */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+ { { OPERAND_ars_entry }, 's' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+ { { STATE_WindowBase }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+ { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' },
+ { { STATE_WindowStart }, 'm' },
+ { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+ { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4const }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bbi }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_b4constu }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+ { { OPERAND_soffsetx4 }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sae }, 'i' },
+ { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+ { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+ { { STATE_LBEG }, 'o' },
+ { { STATE_LEND }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+ { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+ { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+ { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+ { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+ { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+ { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+ { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'i' },
+ { { STATE_LITBEN }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'o' },
+ { { STATE_LITBEN }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
+ { { STATE_LITBADDR }, 'm' },
+ { { STATE_LITBEN }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'i' },
+ { { STATE_PSCALLINC }, 'i' },
+ { { STATE_PSOWB }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSUM }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+ { { STATE_PSWOE }, 'm' },
+ { { STATE_PSCALLINC }, 'm' },
+ { { STATE_PSOWB }, 'm' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'm' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'i' },
+ { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'm' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'm' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPC1 }, 'i' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_EPS2 }, 'i' },
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+ { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+ { { OPERAND_imms }, 'i' },
+ { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'i' },
+ { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'o' },
+ { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DEBUGCAUSE }, 'm' },
+ { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+ { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' },
+ { { STATE_EPC2 }, 'i' },
+ { { STATE_PSWOE }, 'o' },
+ { { STATE_PSCALLINC }, 'o' },
+ { { STATE_PSOWB }, 'o' },
+ { { STATE_PSRING }, 'o' },
+ { { STATE_PSUM }, 'o' },
+ { { STATE_PSEXCM }, 'o' },
+ { { STATE_PSINTLEVEL }, 'o' },
+ { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+ { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_bs }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_bs4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_bs8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
+ { { OPERAND_bs }, 'i' },
+ { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
+ { { OPERAND_arr }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_brall }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_brall }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_brall }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE0 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'o' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CCOMPARE1 }, 'm' },
+ { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm4x16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_PTBASE }, 'm' },
+ { { STATE_EXCVADDR }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'i' },
+ { { STATE_ASID2 }, 'i' },
+ { { STATE_ASID1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'o' },
+ { { STATE_ASID2 }, 'o' },
+ { { STATE_ASID1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ASID3 }, 'm' },
+ { { STATE_ASID2 }, 'm' },
+ { { STATE_ASID1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_XTSYNC }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+ { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'o' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+ { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_ATOMCTL }, 'm' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+ { { STATE_CCON }, 'i' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_MPSCORE }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+ INTERFACE_RMPINT_Out,
+ INTERFACE_RMPINT_In
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+ { { STATE_CCON }, 'm' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_WMPINT_DATA }, 'o' },
+ { { STATE_WMPINT_ADDR }, 'o' },
+ { { STATE_MPSCORE }, 'm' },
+ { { STATE_WMPINT_TOGGLEEN }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'i' },
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'o' },
+ { { STATE_AE_SAR }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
+ { { STATE_AE_BITHEAD }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_TABLESIZE }, 'i' },
+ { { STATE_AE_FIRST_TS }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'o' },
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_TABLESIZE }, 'o' },
+ { { STATE_AE_FIRST_TS }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'i' },
+ { { STATE_AE_SEARCHDONE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
+ { { STATE_AE_SAR }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
+ { { STATE_AE_FIRST_TS }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
+ { { STATE_AE_FIRST_TS }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
+ { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
+ { { STATE_AE_SEARCHDONE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_lsimm32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
+ { { OPERAND_ps }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
+ { { OPERAND_pr }, 'm' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
+ { { OPERAND_pr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
+ { { OPERAND_qr1_w }, 'm' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
+ { { OPERAND_qr1_w }, 'm' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_cvt_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_cvt_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
+ { { OPERAND_alupppb_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
+ { { OPERAND_alupppb_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' },
+ { { OPERAND_bt2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
+ { { OPERAND_bt2 }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
+ { { OPERAND_bt2 }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
+ { { OPERAND_bt2 }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bt }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_bt }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_ae_samt32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
+ { { OPERAND_ps }, 'o' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ae_samt64 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_AE_SAR }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
+ { { OPERAND_qr1_w }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
+ { { OPERAND_bt }, 'o' },
+ { { OPERAND_qr0 }, 'i' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
+ { { OPERAND_ars }, 'o' },
+ { { OPERAND_qr0_rw }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
+ { { STATE_AE_OVERFLOW }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_mac_qr0_rw }, 'i' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_mac_qr0 }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'o' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
+ { { OPERAND_mac_qr1_w }, 'm' },
+ { { OPERAND_pr }, 'i' },
+ { { OPERAND_pr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'm' },
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'm' },
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'o' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
+ { { STATE_AE_TABLESIZE }, 'm' },
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'm' },
+ { { STATE_AE_SEARCHDONE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
+ { { STATE_AE_NEXTOFFSET }, 'm' },
+ { { STATE_AE_TABLESIZE }, 'm' },
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_AE_FIRST_TS }, 'i' },
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_SEARCHDONE }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_AE_FIRST_TS }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_AE_TABLESIZE }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ae_ohba2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
+ { { OPERAND_arr }, 'o' },
+ { { OPERAND_ars }, 'i' },
+ { { OPERAND_ae_ohba2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_ae_ohba }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
+ { { OPERAND_br }, 'o' },
+ { { OPERAND_art }, 'm' },
+ { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'o' },
+ { { STATE_AE_NEXTOFFSET }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
+ { { OPERAND_ars }, 'm' },
+ { { OPERAND_art }, 'i' },
+ { { OPERAND_ae_ohba }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'm' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_AE_BITSUSED }, 'i' },
+ { { STATE_AE_NEXTOFFSET }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
+ { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
+ { { STATE_AE_BITPTR }, 'i' },
+ { { STATE_AE_BITHEAD }, 'm' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_threadptr_args,
+ 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_threadptr_args,
+ 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid0_args,
+ 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_configid0_args,
+ 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_configid1_args,
+ 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 3, Iclass_xt_mul16_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_bbool1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbool4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbool8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbranch_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bmove_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_RSR_BR_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_WSR_BR_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_XSR_BR_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
+ 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_rasid_args,
+ 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_rasid_args,
+ 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_rasid_args,
+ 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_ldpte */,
+ 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwitlba */,
+ 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwdtlba */,
+ 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_cpenable_args,
+ 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_cpenable_args,
+ 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_cpenable_args,
+ 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_atomctl_args,
+ 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_atomctl_args,
+ 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_atomctl_args,
+ 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rer_args,
+ 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+ { 2, Iclass_xt_iclass_wer_args,
+ 7, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_ovf_sar_args,
+ 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_ovf_sar_args,
+ 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_bithead_args,
+ 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_bithead_args,
+ 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_ts_fts_bu_bp_args,
+ 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_ts_fts_bu_bp_args,
+ 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
+ { 1, Iclass_rur_ae_sd_no_args,
+ 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 },
+ { 1, Iclass_wur_ae_sd_no_args,
+ 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_overflow_args,
+ 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_overflow_args,
+ 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_sar_args,
+ 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_sar_args,
+ 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_bitptr_args,
+ 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_bitptr_args,
+ 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_bitsused_args,
+ 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_bitsused_args,
+ 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_tablesize_args,
+ 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_tablesize_args,
+ 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_first_ts_args,
+ 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_first_ts_args,
+ 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_nextoffset_args,
+ 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_nextoffset_args,
+ 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_rur_ae_searchdone_args,
+ 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_wur_ae_searchdone_args,
+ 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16f_i_args,
+ 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16f_iu_args,
+ 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16f_x_args,
+ 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16f_xu_args,
+ 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24_i_args,
+ 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24_iu_args,
+ 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24_x_args,
+ 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24_xu_args,
+ 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24f_i_args,
+ 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24f_iu_args,
+ 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24f_x_args,
+ 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24f_xu_args,
+ 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16x2f_i_args,
+ 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16x2f_iu_args,
+ 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16x2f_x_args,
+ 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp16x2f_xu_args,
+ 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2f_i_args,
+ 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2f_iu_args,
+ 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2f_x_args,
+ 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2f_xu_args,
+ 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2_i_args,
+ 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2_iu_args,
+ 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2_x_args,
+ 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lp24x2_xu_args,
+ 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16x2f_i_args,
+ 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16x2f_iu_args,
+ 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16x2f_x_args,
+ 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16x2f_xu_args,
+ 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2s_i_args,
+ 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2s_iu_args,
+ 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2s_x_args,
+ 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2s_xu_args,
+ 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2f_i_args,
+ 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2f_iu_args,
+ 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2f_x_args,
+ 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24x2f_xu_args,
+ 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16f_l_i_args,
+ 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16f_l_iu_args,
+ 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16f_l_x_args,
+ 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp16f_l_xu_args,
+ 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24s_l_i_args,
+ 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24s_l_iu_args,
+ 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24s_l_x_args,
+ 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24s_l_xu_args,
+ 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24f_l_i_args,
+ 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24f_l_iu_args,
+ 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24f_l_x_args,
+ 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sp24f_l_xu_args,
+ 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq56_i_args,
+ 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq56_iu_args,
+ 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq56_x_args,
+ 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq56_xu_args,
+ 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq32f_i_args,
+ 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq32f_iu_args,
+ 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq32f_x_args,
+ 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lq32f_xu_args,
+ 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq56s_i_args,
+ 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq56s_iu_args,
+ 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq56s_x_args,
+ 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq56s_xu_args,
+ 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq32f_i_args,
+ 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq32f_iu_args,
+ 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq32f_x_args,
+ 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sq32f_xu_args,
+ 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_zerop48_args,
+ 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_movp48_args,
+ 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_selp24_ll_args,
+ 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_selp24_lh_args,
+ 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_selp24_hl_args,
+ 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_selp24_hh_args,
+ 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_movtp24x2_args,
+ 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_movfp24x2_args,
+ 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_movtp48_args,
+ 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_movfp48_args,
+ 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_movpa24x2_args,
+ 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_truncp24a32x2_args,
+ 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_cvta32p24_l_args,
+ 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_cvta32p24_h_args,
+ 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args,
+ 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 },
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+ { 4, Iclass_ae_iclass_maxbp24s_args,
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+ { 2, Iclass_ae_iclass_negsq56s_args,
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+ { 3, Iclass_ae_iclass_sraip24_args,
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+ { 2, Iclass_ae_iclass_srasp24_args,
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+ { 3, Iclass_ae_iclass_sllisp24s_args,
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+ { 2, Iclass_ae_iclass_sllssp24s_args,
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+ { 3, Iclass_ae_iclass_slliq56_args,
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+ { 3, Iclass_ae_iclass_sraiq56_args,
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+ { 3, Iclass_ae_iclass_sllaq56_args,
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+ { 3, Iclass_ae_iclass_sraaq56_args,
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+ { 3, Iclass_ae_iclass_sllasq56s_args,
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+ { 3, Iclass_ae_iclass_ltq56s_args,
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+ { 3, Iclass_ae_iclass_leq56s_args,
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+ { 3, Iclass_ae_iclass_eqq56_args,
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+ { 2, Iclass_ae_iclass_nsaq56s_args,
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+ { 3, Iclass_ae_iclass_mulfs32p16s_ll_args,
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+ { 3, Iclass_ae_iclass_mulp24s_ll_args,
+ 1, Iclass_ae_iclass_mulp24s_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulfs32p16s_lh_args,
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+ { 3, Iclass_ae_iclass_mulp24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulfs32p16s_hl_args,
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+ { 3, Iclass_ae_iclass_mulfs32p16s_hh_args,
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+ { 3, Iclass_ae_iclass_mulfp24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulp24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulafs32p16s_ll_args,
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+ { 3, Iclass_ae_iclass_mulafp24s_ll_args,
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+ { 3, Iclass_ae_iclass_mulap24s_ll_args,
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+ { 3, Iclass_ae_iclass_mulafs32p16s_lh_args,
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+ { 3, Iclass_ae_iclass_mulafp24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulap24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulafs32p16s_hl_args,
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+ { 3, Iclass_ae_iclass_mulsfp24s_ll_args,
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+ { 3, Iclass_ae_iclass_mulsp24s_ll_args,
+ 1, Iclass_ae_iclass_mulsp24s_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsfs32p16s_lh_args,
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+ { 3, Iclass_ae_iclass_mulsfp24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulsp24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulsfs32p16s_hl_args,
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+ { 3, Iclass_ae_iclass_mulsfp24s_hl_args,
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+ { 3, Iclass_ae_iclass_mulsp24s_hl_args,
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+ { 3, Iclass_ae_iclass_mulsp24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulafs56p24s_ll_args,
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+ { 3, Iclass_ae_iclass_mulas56p24s_ll_args,
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+ { 3, Iclass_ae_iclass_mulafs56p24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulas56p24s_lh_args,
+ 2, Iclass_ae_iclass_mulas56p24s_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulafs56p24s_hl_args,
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+ { 3, Iclass_ae_iclass_mulas56p24s_hl_args,
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+ { 3, Iclass_ae_iclass_mulafs56p24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulas56p24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulsfs56p24s_ll_args,
+ 2, Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulss56p24s_ll_args,
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+ { 3, Iclass_ae_iclass_mulsfs56p24s_lh_args,
+ 2, Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulss56p24s_lh_args,
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+ { 3, Iclass_ae_iclass_mulsfs56p24s_hl_args,
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+ { 3, Iclass_ae_iclass_mulss56p24s_hl_args,
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+ { 3, Iclass_ae_iclass_mulsfs56p24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulss56p24s_hh_args,
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+ { 3, Iclass_ae_iclass_mulfq32sp16s_h_args,
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+ { 3, Iclass_ae_iclass_mulfq32sp16u_l_args,
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+ { 3, Iclass_ae_iclass_mulfq32sp16u_h_args,
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+ { 3, Iclass_ae_iclass_mulq32sp16s_l_args,
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+ { 3, Iclass_ae_iclass_mulq32sp16s_h_args,
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+ { 3, Iclass_ae_iclass_mulq32sp16u_l_args,
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+ { 3, Iclass_ae_iclass_mulq32sp16u_h_args,
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+ { 3, Iclass_ae_iclass_mulafq32sp16s_l_args,
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+ { 3, Iclass_ae_iclass_mulafq32sp16s_h_args,
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+ { 3, Iclass_ae_iclass_mulafq32sp16u_l_args,
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+ { 3, Iclass_ae_iclass_mulafq32sp16u_h_args,
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+ { 3, Iclass_ae_iclass_mulaq32sp16s_l_args,
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+ { 3, Iclass_ae_iclass_mulaq32sp16s_h_args,
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+ { 3, Iclass_ae_iclass_mulaq32sp16u_l_args,
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+ { 3, Iclass_ae_iclass_mulaq32sp16u_h_args,
+ 1, Iclass_ae_iclass_mulaq32sp16u_h_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsfq32sp16s_l_args,
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+ { 3, Iclass_ae_iclass_mulsfq32sp16s_h_args,
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+ { 3, Iclass_ae_iclass_mulsfq32sp16u_l_args,
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+ { 3, Iclass_ae_iclass_mulsfq32sp16u_h_args,
+ 1, Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsq32sp16s_l_args,
+ 1, Iclass_ae_iclass_mulsq32sp16s_l_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsq32sp16s_h_args,
+ 1, Iclass_ae_iclass_mulsq32sp16s_h_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsq32sp16u_l_args,
+ 1, Iclass_ae_iclass_mulsq32sp16u_l_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsq32sp16u_h_args,
+ 1, Iclass_ae_iclass_mulsq32sp16u_h_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaaq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaafq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaaq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaafq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaaq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaafq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaaq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaafq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaaq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaafq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaaq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args,
+ 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args,
+ 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args,
+ 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args,
+ 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args,
+ 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 },
+ { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args,
+ 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
+ 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
+ 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_sha32_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_ae_iclass_vldl32t_args,
+ 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_vldl16t_args,
+ 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_vldl16c_args,
+ 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_vldsht_args,
+ 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_lb_args,
+ 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_lbi_args,
+ 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lbk_args,
+ 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_lbki_args,
+ 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_db_args,
+ 3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_dbi_args,
+ 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_vlel32t_args,
+ 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_vlel16t_args,
+ 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
+ { 2, Iclass_ae_iclass_sb_args,
+ 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
+ { 3, Iclass_ae_iclass_sbi_args,
+ 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_vles16c_args,
+ 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
+ { 1, Iclass_ae_iclass_sbf_args,
+ 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+ ICLASS_xt_iclass_excw,
+ ICLASS_xt_iclass_rfe,
+ ICLASS_xt_iclass_rfde,
+ ICLASS_xt_iclass_syscall,
+ ICLASS_xt_iclass_call12,
+ ICLASS_xt_iclass_call8,
+ ICLASS_xt_iclass_call4,
+ ICLASS_xt_iclass_callx12,
+ ICLASS_xt_iclass_callx8,
+ ICLASS_xt_iclass_callx4,
+ ICLASS_xt_iclass_entry,
+ ICLASS_xt_iclass_movsp,
+ ICLASS_xt_iclass_rotw,
+ ICLASS_xt_iclass_retw,
+ ICLASS_xt_iclass_rfwou,
+ ICLASS_xt_iclass_l32e,
+ ICLASS_xt_iclass_s32e,
+ ICLASS_xt_iclass_rsr_windowbase,
+ ICLASS_xt_iclass_wsr_windowbase,
+ ICLASS_xt_iclass_xsr_windowbase,
+ ICLASS_xt_iclass_rsr_windowstart,
+ ICLASS_xt_iclass_wsr_windowstart,
+ ICLASS_xt_iclass_xsr_windowstart,
+ ICLASS_xt_iclass_add_n,
+ ICLASS_xt_iclass_addi_n,
+ ICLASS_xt_iclass_bz6,
+ ICLASS_xt_iclass_ill_n,
+ ICLASS_xt_iclass_loadi4,
+ ICLASS_xt_iclass_mov_n,
+ ICLASS_xt_iclass_movi_n,
+ ICLASS_xt_iclass_nopn,
+ ICLASS_xt_iclass_retn,
+ ICLASS_xt_iclass_storei4,
+ ICLASS_rur_threadptr,
+ ICLASS_wur_threadptr,
+ ICLASS_xt_iclass_addi,
+ ICLASS_xt_iclass_addmi,
+ ICLASS_xt_iclass_addsub,
+ ICLASS_xt_iclass_bit,
+ ICLASS_xt_iclass_bsi8,
+ ICLASS_xt_iclass_bsi8b,
+ ICLASS_xt_iclass_bsi8u,
+ ICLASS_xt_iclass_bst8,
+ ICLASS_xt_iclass_bsz12,
+ ICLASS_xt_iclass_call0,
+ ICLASS_xt_iclass_callx0,
+ ICLASS_xt_iclass_exti,
+ ICLASS_xt_iclass_ill,
+ ICLASS_xt_iclass_jump,
+ ICLASS_xt_iclass_jumpx,
+ ICLASS_xt_iclass_l16ui,
+ ICLASS_xt_iclass_l16si,
+ ICLASS_xt_iclass_l32i,
+ ICLASS_xt_iclass_l32r,
+ ICLASS_xt_iclass_l8i,
+ ICLASS_xt_iclass_loop,
+ ICLASS_xt_iclass_loopz,
+ ICLASS_xt_iclass_movi,
+ ICLASS_xt_iclass_movz,
+ ICLASS_xt_iclass_neg,
+ ICLASS_xt_iclass_nop,
+ ICLASS_xt_iclass_return,
+ ICLASS_xt_iclass_simcall,
+ ICLASS_xt_iclass_s16i,
+ ICLASS_xt_iclass_s32i,
+ ICLASS_xt_iclass_s8i,
+ ICLASS_xt_iclass_sar,
+ ICLASS_xt_iclass_sari,
+ ICLASS_xt_iclass_shifts,
+ ICLASS_xt_iclass_shiftst,
+ ICLASS_xt_iclass_shiftt,
+ ICLASS_xt_iclass_slli,
+ ICLASS_xt_iclass_srai,
+ ICLASS_xt_iclass_srli,
+ ICLASS_xt_iclass_memw,
+ ICLASS_xt_iclass_extw,
+ ICLASS_xt_iclass_isync,
+ ICLASS_xt_iclass_sync,
+ ICLASS_xt_iclass_rsil,
+ ICLASS_xt_iclass_rsr_lend,
+ ICLASS_xt_iclass_wsr_lend,
+ ICLASS_xt_iclass_xsr_lend,
+ ICLASS_xt_iclass_rsr_lcount,
+ ICLASS_xt_iclass_wsr_lcount,
+ ICLASS_xt_iclass_xsr_lcount,
+ ICLASS_xt_iclass_rsr_lbeg,
+ ICLASS_xt_iclass_wsr_lbeg,
+ ICLASS_xt_iclass_xsr_lbeg,
+ ICLASS_xt_iclass_rsr_sar,
+ ICLASS_xt_iclass_wsr_sar,
+ ICLASS_xt_iclass_xsr_sar,
+ ICLASS_xt_iclass_rsr_litbase,
+ ICLASS_xt_iclass_wsr_litbase,
+ ICLASS_xt_iclass_xsr_litbase,
+ ICLASS_xt_iclass_rsr_configid0,
+ ICLASS_xt_iclass_wsr_configid0,
+ ICLASS_xt_iclass_rsr_configid1,
+ ICLASS_xt_iclass_rsr_ps,
+ ICLASS_xt_iclass_wsr_ps,
+ ICLASS_xt_iclass_xsr_ps,
+ ICLASS_xt_iclass_rsr_epc1,
+ ICLASS_xt_iclass_wsr_epc1,
+ ICLASS_xt_iclass_xsr_epc1,
+ ICLASS_xt_iclass_rsr_excsave1,
+ ICLASS_xt_iclass_wsr_excsave1,
+ ICLASS_xt_iclass_xsr_excsave1,
+ ICLASS_xt_iclass_rsr_epc2,
+ ICLASS_xt_iclass_wsr_epc2,
+ ICLASS_xt_iclass_xsr_epc2,
+ ICLASS_xt_iclass_rsr_excsave2,
+ ICLASS_xt_iclass_wsr_excsave2,
+ ICLASS_xt_iclass_xsr_excsave2,
+ ICLASS_xt_iclass_rsr_eps2,
+ ICLASS_xt_iclass_wsr_eps2,
+ ICLASS_xt_iclass_xsr_eps2,
+ ICLASS_xt_iclass_rsr_excvaddr,
+ ICLASS_xt_iclass_wsr_excvaddr,
+ ICLASS_xt_iclass_xsr_excvaddr,
+ ICLASS_xt_iclass_rsr_depc,
+ ICLASS_xt_iclass_wsr_depc,
+ ICLASS_xt_iclass_xsr_depc,
+ ICLASS_xt_iclass_rsr_exccause,
+ ICLASS_xt_iclass_wsr_exccause,
+ ICLASS_xt_iclass_xsr_exccause,
+ ICLASS_xt_iclass_rsr_misc0,
+ ICLASS_xt_iclass_wsr_misc0,
+ ICLASS_xt_iclass_xsr_misc0,
+ ICLASS_xt_iclass_rsr_misc1,
+ ICLASS_xt_iclass_wsr_misc1,
+ ICLASS_xt_iclass_xsr_misc1,
+ ICLASS_xt_iclass_rsr_prid,
+ ICLASS_xt_iclass_rsr_vecbase,
+ ICLASS_xt_iclass_wsr_vecbase,
+ ICLASS_xt_iclass_xsr_vecbase,
+ ICLASS_xt_mul16,
+ ICLASS_xt_mul32,
+ ICLASS_xt_iclass_rfi,
+ ICLASS_xt_iclass_wait,
+ ICLASS_xt_iclass_rsr_interrupt,
+ ICLASS_xt_iclass_wsr_intset,
+ ICLASS_xt_iclass_wsr_intclear,
+ ICLASS_xt_iclass_rsr_intenable,
+ ICLASS_xt_iclass_wsr_intenable,
+ ICLASS_xt_iclass_xsr_intenable,
+ ICLASS_xt_iclass_break,
+ ICLASS_xt_iclass_break_n,
+ ICLASS_xt_iclass_rsr_debugcause,
+ ICLASS_xt_iclass_wsr_debugcause,
+ ICLASS_xt_iclass_xsr_debugcause,
+ ICLASS_xt_iclass_rsr_icount,
+ ICLASS_xt_iclass_wsr_icount,
+ ICLASS_xt_iclass_xsr_icount,
+ ICLASS_xt_iclass_rsr_icountlevel,
+ ICLASS_xt_iclass_wsr_icountlevel,
+ ICLASS_xt_iclass_xsr_icountlevel,
+ ICLASS_xt_iclass_rsr_ddr,
+ ICLASS_xt_iclass_wsr_ddr,
+ ICLASS_xt_iclass_xsr_ddr,
+ ICLASS_xt_iclass_rfdo,
+ ICLASS_xt_iclass_rfdd,
+ ICLASS_xt_iclass_bbool1,
+ ICLASS_xt_iclass_bbool4,
+ ICLASS_xt_iclass_bbool8,
+ ICLASS_xt_iclass_bbranch,
+ ICLASS_xt_iclass_bmove,
+ ICLASS_xt_iclass_RSR_BR,
+ ICLASS_xt_iclass_WSR_BR,
+ ICLASS_xt_iclass_XSR_BR,
+ ICLASS_xt_iclass_rsr_ccount,
+ ICLASS_xt_iclass_wsr_ccount,
+ ICLASS_xt_iclass_xsr_ccount,
+ ICLASS_xt_iclass_rsr_ccompare0,
+ ICLASS_xt_iclass_wsr_ccompare0,
+ ICLASS_xt_iclass_xsr_ccompare0,
+ ICLASS_xt_iclass_rsr_ccompare1,
+ ICLASS_xt_iclass_wsr_ccompare1,
+ ICLASS_xt_iclass_xsr_ccompare1,
+ ICLASS_xt_iclass_icache,
+ ICLASS_xt_iclass_icache_inv,
+ ICLASS_xt_iclass_licx,
+ ICLASS_xt_iclass_sicx,
+ ICLASS_xt_iclass_dcache,
+ ICLASS_xt_iclass_dcache_ind,
+ ICLASS_xt_iclass_dcache_inv,
+ ICLASS_xt_iclass_dpf,
+ ICLASS_xt_iclass_sdct,
+ ICLASS_xt_iclass_ldct,
+ ICLASS_xt_iclass_wsr_ptevaddr,
+ ICLASS_xt_iclass_rsr_ptevaddr,
+ ICLASS_xt_iclass_xsr_ptevaddr,
+ ICLASS_xt_iclass_rsr_rasid,
+ ICLASS_xt_iclass_wsr_rasid,
+ ICLASS_xt_iclass_xsr_rasid,
+ ICLASS_xt_iclass_rsr_itlbcfg,
+ ICLASS_xt_iclass_wsr_itlbcfg,
+ ICLASS_xt_iclass_xsr_itlbcfg,
+ ICLASS_xt_iclass_rsr_dtlbcfg,
+ ICLASS_xt_iclass_wsr_dtlbcfg,
+ ICLASS_xt_iclass_xsr_dtlbcfg,
+ ICLASS_xt_iclass_idtlb,
+ ICLASS_xt_iclass_rdtlb,
+ ICLASS_xt_iclass_wdtlb,
+ ICLASS_xt_iclass_iitlb,
+ ICLASS_xt_iclass_ritlb,
+ ICLASS_xt_iclass_witlb,
+ ICLASS_xt_iclass_ldpte,
+ ICLASS_xt_iclass_hwwitlba,
+ ICLASS_xt_iclass_hwwdtlba,
+ ICLASS_xt_iclass_rsr_cpenable,
+ ICLASS_xt_iclass_wsr_cpenable,
+ ICLASS_xt_iclass_xsr_cpenable,
+ ICLASS_xt_iclass_clamp,
+ ICLASS_xt_iclass_minmax,
+ ICLASS_xt_iclass_nsa,
+ ICLASS_xt_iclass_sx,
+ ICLASS_xt_iclass_l32ai,
+ ICLASS_xt_iclass_s32ri,
+ ICLASS_xt_iclass_s32c1i,
+ ICLASS_xt_iclass_rsr_scompare1,
+ ICLASS_xt_iclass_wsr_scompare1,
+ ICLASS_xt_iclass_xsr_scompare1,
+ ICLASS_xt_iclass_rsr_atomctl,
+ ICLASS_xt_iclass_wsr_atomctl,
+ ICLASS_xt_iclass_xsr_atomctl,
+ ICLASS_xt_iclass_rer,
+ ICLASS_xt_iclass_wer,
+ ICLASS_rur_ae_ovf_sar,
+ ICLASS_wur_ae_ovf_sar,
+ ICLASS_rur_ae_bithead,
+ ICLASS_wur_ae_bithead,
+ ICLASS_rur_ae_ts_fts_bu_bp,
+ ICLASS_wur_ae_ts_fts_bu_bp,
+ ICLASS_rur_ae_sd_no,
+ ICLASS_wur_ae_sd_no,
+ ICLASS_ae_iclass_rur_ae_overflow,
+ ICLASS_ae_iclass_wur_ae_overflow,
+ ICLASS_ae_iclass_rur_ae_sar,
+ ICLASS_ae_iclass_wur_ae_sar,
+ ICLASS_ae_iclass_rur_ae_bitptr,
+ ICLASS_ae_iclass_wur_ae_bitptr,
+ ICLASS_ae_iclass_rur_ae_bitsused,
+ ICLASS_ae_iclass_wur_ae_bitsused,
+ ICLASS_ae_iclass_rur_ae_tablesize,
+ ICLASS_ae_iclass_wur_ae_tablesize,
+ ICLASS_ae_iclass_rur_ae_first_ts,
+ ICLASS_ae_iclass_wur_ae_first_ts,
+ ICLASS_ae_iclass_rur_ae_nextoffset,
+ ICLASS_ae_iclass_wur_ae_nextoffset,
+ ICLASS_ae_iclass_rur_ae_searchdone,
+ ICLASS_ae_iclass_wur_ae_searchdone,
+ ICLASS_ae_iclass_lp16f_i,
+ ICLASS_ae_iclass_lp16f_iu,
+ ICLASS_ae_iclass_lp16f_x,
+ ICLASS_ae_iclass_lp16f_xu,
+ ICLASS_ae_iclass_lp24_i,
+ ICLASS_ae_iclass_lp24_iu,
+ ICLASS_ae_iclass_lp24_x,
+ ICLASS_ae_iclass_lp24_xu,
+ ICLASS_ae_iclass_lp24f_i,
+ ICLASS_ae_iclass_lp24f_iu,
+ ICLASS_ae_iclass_lp24f_x,
+ ICLASS_ae_iclass_lp24f_xu,
+ ICLASS_ae_iclass_lp16x2f_i,
+ ICLASS_ae_iclass_lp16x2f_iu,
+ ICLASS_ae_iclass_lp16x2f_x,
+ ICLASS_ae_iclass_lp16x2f_xu,
+ ICLASS_ae_iclass_lp24x2f_i,
+ ICLASS_ae_iclass_lp24x2f_iu,
+ ICLASS_ae_iclass_lp24x2f_x,
+ ICLASS_ae_iclass_lp24x2f_xu,
+ ICLASS_ae_iclass_lp24x2_i,
+ ICLASS_ae_iclass_lp24x2_iu,
+ ICLASS_ae_iclass_lp24x2_x,
+ ICLASS_ae_iclass_lp24x2_xu,
+ ICLASS_ae_iclass_sp16x2f_i,
+ ICLASS_ae_iclass_sp16x2f_iu,
+ ICLASS_ae_iclass_sp16x2f_x,
+ ICLASS_ae_iclass_sp16x2f_xu,
+ ICLASS_ae_iclass_sp24x2s_i,
+ ICLASS_ae_iclass_sp24x2s_iu,
+ ICLASS_ae_iclass_sp24x2s_x,
+ ICLASS_ae_iclass_sp24x2s_xu,
+ ICLASS_ae_iclass_sp24x2f_i,
+ ICLASS_ae_iclass_sp24x2f_iu,
+ ICLASS_ae_iclass_sp24x2f_x,
+ ICLASS_ae_iclass_sp24x2f_xu,
+ ICLASS_ae_iclass_sp16f_l_i,
+ ICLASS_ae_iclass_sp16f_l_iu,
+ ICLASS_ae_iclass_sp16f_l_x,
+ ICLASS_ae_iclass_sp16f_l_xu,
+ ICLASS_ae_iclass_sp24s_l_i,
+ ICLASS_ae_iclass_sp24s_l_iu,
+ ICLASS_ae_iclass_sp24s_l_x,
+ ICLASS_ae_iclass_sp24s_l_xu,
+ ICLASS_ae_iclass_sp24f_l_i,
+ ICLASS_ae_iclass_sp24f_l_iu,
+ ICLASS_ae_iclass_sp24f_l_x,
+ ICLASS_ae_iclass_sp24f_l_xu,
+ ICLASS_ae_iclass_lq56_i,
+ ICLASS_ae_iclass_lq56_iu,
+ ICLASS_ae_iclass_lq56_x,
+ ICLASS_ae_iclass_lq56_xu,
+ ICLASS_ae_iclass_lq32f_i,
+ ICLASS_ae_iclass_lq32f_iu,
+ ICLASS_ae_iclass_lq32f_x,
+ ICLASS_ae_iclass_lq32f_xu,
+ ICLASS_ae_iclass_sq56s_i,
+ ICLASS_ae_iclass_sq56s_iu,
+ ICLASS_ae_iclass_sq56s_x,
+ ICLASS_ae_iclass_sq56s_xu,
+ ICLASS_ae_iclass_sq32f_i,
+ ICLASS_ae_iclass_sq32f_iu,
+ ICLASS_ae_iclass_sq32f_x,
+ ICLASS_ae_iclass_sq32f_xu,
+ ICLASS_ae_iclass_zerop48,
+ ICLASS_ae_iclass_movp48,
+ ICLASS_ae_iclass_selp24_ll,
+ ICLASS_ae_iclass_selp24_lh,
+ ICLASS_ae_iclass_selp24_hl,
+ ICLASS_ae_iclass_selp24_hh,
+ ICLASS_ae_iclass_movtp24x2,
+ ICLASS_ae_iclass_movfp24x2,
+ ICLASS_ae_iclass_movtp48,
+ ICLASS_ae_iclass_movfp48,
+ ICLASS_ae_iclass_movpa24x2,
+ ICLASS_ae_iclass_truncp24a32x2,
+ ICLASS_ae_iclass_cvta32p24_l,
+ ICLASS_ae_iclass_cvta32p24_h,
+ ICLASS_ae_iclass_cvtp24a16x2_ll,
+ ICLASS_ae_iclass_cvtp24a16x2_lh,
+ ICLASS_ae_iclass_cvtp24a16x2_hl,
+ ICLASS_ae_iclass_cvtp24a16x2_hh,
+ ICLASS_ae_iclass_truncp24q48x2,
+ ICLASS_ae_iclass_truncp16,
+ ICLASS_ae_iclass_roundsp24q48sym,
+ ICLASS_ae_iclass_roundsp24q48asym,
+ ICLASS_ae_iclass_roundsp16q48sym,
+ ICLASS_ae_iclass_roundsp16q48asym,
+ ICLASS_ae_iclass_roundsp16sym,
+ ICLASS_ae_iclass_roundsp16asym,
+ ICLASS_ae_iclass_zeroq56,
+ ICLASS_ae_iclass_movq56,
+ ICLASS_ae_iclass_movtq56,
+ ICLASS_ae_iclass_movfq56,
+ ICLASS_ae_iclass_cvtq48a32s,
+ ICLASS_ae_iclass_cvtq48p24s_l,
+ ICLASS_ae_iclass_cvtq48p24s_h,
+ ICLASS_ae_iclass_satq48s,
+ ICLASS_ae_iclass_truncq32,
+ ICLASS_ae_iclass_roundsq32sym,
+ ICLASS_ae_iclass_roundsq32asym,
+ ICLASS_ae_iclass_trunca32q48,
+ ICLASS_ae_iclass_movap24s_l,
+ ICLASS_ae_iclass_movap24s_h,
+ ICLASS_ae_iclass_trunca16p24s_l,
+ ICLASS_ae_iclass_trunca16p24s_h,
+ ICLASS_ae_iclass_addp24,
+ ICLASS_ae_iclass_subp24,
+ ICLASS_ae_iclass_negp24,
+ ICLASS_ae_iclass_absp24,
+ ICLASS_ae_iclass_maxp24s,
+ ICLASS_ae_iclass_minp24s,
+ ICLASS_ae_iclass_maxbp24s,
+ ICLASS_ae_iclass_minbp24s,
+ ICLASS_ae_iclass_addsp24s,
+ ICLASS_ae_iclass_subsp24s,
+ ICLASS_ae_iclass_negsp24s,
+ ICLASS_ae_iclass_abssp24s,
+ ICLASS_ae_iclass_andp48,
+ ICLASS_ae_iclass_nandp48,
+ ICLASS_ae_iclass_orp48,
+ ICLASS_ae_iclass_xorp48,
+ ICLASS_ae_iclass_ltp24s,
+ ICLASS_ae_iclass_lep24s,
+ ICLASS_ae_iclass_eqp24,
+ ICLASS_ae_iclass_addq56,
+ ICLASS_ae_iclass_subq56,
+ ICLASS_ae_iclass_negq56,
+ ICLASS_ae_iclass_absq56,
+ ICLASS_ae_iclass_maxq56s,
+ ICLASS_ae_iclass_minq56s,
+ ICLASS_ae_iclass_maxbq56s,
+ ICLASS_ae_iclass_minbq56s,
+ ICLASS_ae_iclass_addsq56s,
+ ICLASS_ae_iclass_subsq56s,
+ ICLASS_ae_iclass_negsq56s,
+ ICLASS_ae_iclass_abssq56s,
+ ICLASS_ae_iclass_andq56,
+ ICLASS_ae_iclass_nandq56,
+ ICLASS_ae_iclass_orq56,
+ ICLASS_ae_iclass_xorq56,
+ ICLASS_ae_iclass_sllip24,
+ ICLASS_ae_iclass_srlip24,
+ ICLASS_ae_iclass_sraip24,
+ ICLASS_ae_iclass_sllsp24,
+ ICLASS_ae_iclass_srlsp24,
+ ICLASS_ae_iclass_srasp24,
+ ICLASS_ae_iclass_sllisp24s,
+ ICLASS_ae_iclass_sllssp24s,
+ ICLASS_ae_iclass_slliq56,
+ ICLASS_ae_iclass_srliq56,
+ ICLASS_ae_iclass_sraiq56,
+ ICLASS_ae_iclass_sllsq56,
+ ICLASS_ae_iclass_srlsq56,
+ ICLASS_ae_iclass_srasq56,
+ ICLASS_ae_iclass_sllaq56,
+ ICLASS_ae_iclass_srlaq56,
+ ICLASS_ae_iclass_sraaq56,
+ ICLASS_ae_iclass_sllisq56s,
+ ICLASS_ae_iclass_sllssq56s,
+ ICLASS_ae_iclass_sllasq56s,
+ ICLASS_ae_iclass_ltq56s,
+ ICLASS_ae_iclass_leq56s,
+ ICLASS_ae_iclass_eqq56,
+ ICLASS_ae_iclass_nsaq56s,
+ ICLASS_ae_iclass_mulfs32p16s_ll,
+ ICLASS_ae_iclass_mulfp24s_ll,
+ ICLASS_ae_iclass_mulp24s_ll,
+ ICLASS_ae_iclass_mulfs32p16s_lh,
+ ICLASS_ae_iclass_mulfp24s_lh,
+ ICLASS_ae_iclass_mulp24s_lh,
+ ICLASS_ae_iclass_mulfs32p16s_hl,
+ ICLASS_ae_iclass_mulfp24s_hl,
+ ICLASS_ae_iclass_mulp24s_hl,
+ ICLASS_ae_iclass_mulfs32p16s_hh,
+ ICLASS_ae_iclass_mulfp24s_hh,
+ ICLASS_ae_iclass_mulp24s_hh,
+ ICLASS_ae_iclass_mulafs32p16s_ll,
+ ICLASS_ae_iclass_mulafp24s_ll,
+ ICLASS_ae_iclass_mulap24s_ll,
+ ICLASS_ae_iclass_mulafs32p16s_lh,
+ ICLASS_ae_iclass_mulafp24s_lh,
+ ICLASS_ae_iclass_mulap24s_lh,
+ ICLASS_ae_iclass_mulafs32p16s_hl,
+ ICLASS_ae_iclass_mulafp24s_hl,
+ ICLASS_ae_iclass_mulap24s_hl,
+ ICLASS_ae_iclass_mulafs32p16s_hh,
+ ICLASS_ae_iclass_mulafp24s_hh,
+ ICLASS_ae_iclass_mulap24s_hh,
+ ICLASS_ae_iclass_mulsfs32p16s_ll,
+ ICLASS_ae_iclass_mulsfp24s_ll,
+ ICLASS_ae_iclass_mulsp24s_ll,
+ ICLASS_ae_iclass_mulsfs32p16s_lh,
+ ICLASS_ae_iclass_mulsfp24s_lh,
+ ICLASS_ae_iclass_mulsp24s_lh,
+ ICLASS_ae_iclass_mulsfs32p16s_hl,
+ ICLASS_ae_iclass_mulsfp24s_hl,
+ ICLASS_ae_iclass_mulsp24s_hl,
+ ICLASS_ae_iclass_mulsfs32p16s_hh,
+ ICLASS_ae_iclass_mulsfp24s_hh,
+ ICLASS_ae_iclass_mulsp24s_hh,
+ ICLASS_ae_iclass_mulafs56p24s_ll,
+ ICLASS_ae_iclass_mulas56p24s_ll,
+ ICLASS_ae_iclass_mulafs56p24s_lh,
+ ICLASS_ae_iclass_mulas56p24s_lh,
+ ICLASS_ae_iclass_mulafs56p24s_hl,
+ ICLASS_ae_iclass_mulas56p24s_hl,
+ ICLASS_ae_iclass_mulafs56p24s_hh,
+ ICLASS_ae_iclass_mulas56p24s_hh,
+ ICLASS_ae_iclass_mulsfs56p24s_ll,
+ ICLASS_ae_iclass_mulss56p24s_ll,
+ ICLASS_ae_iclass_mulsfs56p24s_lh,
+ ICLASS_ae_iclass_mulss56p24s_lh,
+ ICLASS_ae_iclass_mulsfs56p24s_hl,
+ ICLASS_ae_iclass_mulss56p24s_hl,
+ ICLASS_ae_iclass_mulsfs56p24s_hh,
+ ICLASS_ae_iclass_mulss56p24s_hh,
+ ICLASS_ae_iclass_mulfq32sp16s_l,
+ ICLASS_ae_iclass_mulfq32sp16s_h,
+ ICLASS_ae_iclass_mulfq32sp16u_l,
+ ICLASS_ae_iclass_mulfq32sp16u_h,
+ ICLASS_ae_iclass_mulq32sp16s_l,
+ ICLASS_ae_iclass_mulq32sp16s_h,
+ ICLASS_ae_iclass_mulq32sp16u_l,
+ ICLASS_ae_iclass_mulq32sp16u_h,
+ ICLASS_ae_iclass_mulafq32sp16s_l,
+ ICLASS_ae_iclass_mulafq32sp16s_h,
+ ICLASS_ae_iclass_mulafq32sp16u_l,
+ ICLASS_ae_iclass_mulafq32sp16u_h,
+ ICLASS_ae_iclass_mulaq32sp16s_l,
+ ICLASS_ae_iclass_mulaq32sp16s_h,
+ ICLASS_ae_iclass_mulaq32sp16u_l,
+ ICLASS_ae_iclass_mulaq32sp16u_h,
+ ICLASS_ae_iclass_mulsfq32sp16s_l,
+ ICLASS_ae_iclass_mulsfq32sp16s_h,
+ ICLASS_ae_iclass_mulsfq32sp16u_l,
+ ICLASS_ae_iclass_mulsfq32sp16u_h,
+ ICLASS_ae_iclass_mulsq32sp16s_l,
+ ICLASS_ae_iclass_mulsq32sp16s_h,
+ ICLASS_ae_iclass_mulsq32sp16u_l,
+ ICLASS_ae_iclass_mulsq32sp16u_h,
+ ICLASS_ae_iclass_mulzaaq32sp16s_ll,
+ ICLASS_ae_iclass_mulzaafq32sp16s_ll,
+ ICLASS_ae_iclass_mulzaaq32sp16u_ll,
+ ICLASS_ae_iclass_mulzaafq32sp16u_ll,
+ ICLASS_ae_iclass_mulzaaq32sp16s_hh,
+ ICLASS_ae_iclass_mulzaafq32sp16s_hh,
+ ICLASS_ae_iclass_mulzaaq32sp16u_hh,
+ ICLASS_ae_iclass_mulzaafq32sp16u_hh,
+ ICLASS_ae_iclass_mulzaaq32sp16s_lh,
+ ICLASS_ae_iclass_mulzaafq32sp16s_lh,
+ ICLASS_ae_iclass_mulzaaq32sp16u_lh,
+ ICLASS_ae_iclass_mulzaafq32sp16u_lh,
+ ICLASS_ae_iclass_mulzasq32sp16s_ll,
+ ICLASS_ae_iclass_mulzasfq32sp16s_ll,
+ ICLASS_ae_iclass_mulzasq32sp16u_ll,
+ ICLASS_ae_iclass_mulzasfq32sp16u_ll,
+ ICLASS_ae_iclass_mulzasq32sp16s_hh,
+ ICLASS_ae_iclass_mulzasfq32sp16s_hh,
+ ICLASS_ae_iclass_mulzasq32sp16u_hh,
+ ICLASS_ae_iclass_mulzasfq32sp16u_hh,
+ ICLASS_ae_iclass_mulzasq32sp16s_lh,
+ ICLASS_ae_iclass_mulzasfq32sp16s_lh,
+ ICLASS_ae_iclass_mulzasq32sp16u_lh,
+ ICLASS_ae_iclass_mulzasfq32sp16u_lh,
+ ICLASS_ae_iclass_mulzsaq32sp16s_ll,
+ ICLASS_ae_iclass_mulzsafq32sp16s_ll,
+ ICLASS_ae_iclass_mulzsaq32sp16u_ll,
+ ICLASS_ae_iclass_mulzsafq32sp16u_ll,
+ ICLASS_ae_iclass_mulzsaq32sp16s_hh,
+ ICLASS_ae_iclass_mulzsafq32sp16s_hh,
+ ICLASS_ae_iclass_mulzsaq32sp16u_hh,
+ ICLASS_ae_iclass_mulzsafq32sp16u_hh,
+ ICLASS_ae_iclass_mulzsaq32sp16s_lh,
+ ICLASS_ae_iclass_mulzsafq32sp16s_lh,
+ ICLASS_ae_iclass_mulzsaq32sp16u_lh,
+ ICLASS_ae_iclass_mulzsafq32sp16u_lh,
+ ICLASS_ae_iclass_mulzssq32sp16s_ll,
+ ICLASS_ae_iclass_mulzssfq32sp16s_ll,
+ ICLASS_ae_iclass_mulzssq32sp16u_ll,
+ ICLASS_ae_iclass_mulzssfq32sp16u_ll,
+ ICLASS_ae_iclass_mulzssq32sp16s_hh,
+ ICLASS_ae_iclass_mulzssfq32sp16s_hh,
+ ICLASS_ae_iclass_mulzssq32sp16u_hh,
+ ICLASS_ae_iclass_mulzssfq32sp16u_hh,
+ ICLASS_ae_iclass_mulzssq32sp16s_lh,
+ ICLASS_ae_iclass_mulzssfq32sp16s_lh,
+ ICLASS_ae_iclass_mulzssq32sp16u_lh,
+ ICLASS_ae_iclass_mulzssfq32sp16u_lh,
+ ICLASS_ae_iclass_mulzaafp24s_hh_ll,
+ ICLASS_ae_iclass_mulzaap24s_hh_ll,
+ ICLASS_ae_iclass_mulzaafp24s_hl_lh,
+ ICLASS_ae_iclass_mulzaap24s_hl_lh,
+ ICLASS_ae_iclass_mulzasfp24s_hh_ll,
+ ICLASS_ae_iclass_mulzasp24s_hh_ll,
+ ICLASS_ae_iclass_mulzasfp24s_hl_lh,
+ ICLASS_ae_iclass_mulzasp24s_hl_lh,
+ ICLASS_ae_iclass_mulzsafp24s_hh_ll,
+ ICLASS_ae_iclass_mulzsap24s_hh_ll,
+ ICLASS_ae_iclass_mulzsafp24s_hl_lh,
+ ICLASS_ae_iclass_mulzsap24s_hl_lh,
+ ICLASS_ae_iclass_mulzssfp24s_hh_ll,
+ ICLASS_ae_iclass_mulzssp24s_hh_ll,
+ ICLASS_ae_iclass_mulzssfp24s_hl_lh,
+ ICLASS_ae_iclass_mulzssp24s_hl_lh,
+ ICLASS_ae_iclass_mulaafp24s_hh_ll,
+ ICLASS_ae_iclass_mulaap24s_hh_ll,
+ ICLASS_ae_iclass_mulaafp24s_hl_lh,
+ ICLASS_ae_iclass_mulaap24s_hl_lh,
+ ICLASS_ae_iclass_mulasfp24s_hh_ll,
+ ICLASS_ae_iclass_mulasp24s_hh_ll,
+ ICLASS_ae_iclass_mulasfp24s_hl_lh,
+ ICLASS_ae_iclass_mulasp24s_hl_lh,
+ ICLASS_ae_iclass_mulsafp24s_hh_ll,
+ ICLASS_ae_iclass_mulsap24s_hh_ll,
+ ICLASS_ae_iclass_mulsafp24s_hl_lh,
+ ICLASS_ae_iclass_mulsap24s_hl_lh,
+ ICLASS_ae_iclass_mulssfp24s_hh_ll,
+ ICLASS_ae_iclass_mulssp24s_hh_ll,
+ ICLASS_ae_iclass_mulssfp24s_hl_lh,
+ ICLASS_ae_iclass_mulssp24s_hl_lh,
+ ICLASS_ae_iclass_sha32,
+ ICLASS_ae_iclass_vldl32t,
+ ICLASS_ae_iclass_vldl16t,
+ ICLASS_ae_iclass_vldl16c,
+ ICLASS_ae_iclass_vldsht,
+ ICLASS_ae_iclass_lb,
+ ICLASS_ae_iclass_lbi,
+ ICLASS_ae_iclass_lbk,
+ ICLASS_ae_iclass_lbki,
+ ICLASS_ae_iclass_db,
+ ICLASS_ae_iclass_dbi,
+ ICLASS_ae_iclass_vlel32t,
+ ICLASS_ae_iclass_vlel16t,
+ ICLASS_ae_iclass_sb,
+ ICLASS_ae_iclass_sbi,
+ ICLASS_ae_iclass_vles16c,
+ ICLASS_ae_iclass_sbf
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200040;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200080;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b2000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ca000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b4000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b8000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b3000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1cc000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1cb000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1cd000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b5000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e0000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ce000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300003;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300001;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300004;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200020;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300002;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300008;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000a0;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000c0;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000d0;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000b0;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000e0;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200060;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400010;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200050;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000f0;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200070;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200090;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180000;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x190000;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x160000;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x170000;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x140000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee031;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400040;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400020;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400080;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500000;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400030;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0000;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1be000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c8000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c4000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c2000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1d00;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1c00;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16105;
+}
+
+static void
+Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee0b1;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400050;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400060;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400070;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee071;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee038;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee034;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee032;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ef0a0;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f5003;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c7000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1f00;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1e00;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c0000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c9000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b6000;
+}
+
+static void
+Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x120000;
+}
+
+static void
+Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b7000;
+}
+
+static void
+Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x220000;
+}
+
+static void
+Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c3000;
+}
+
+static void
+Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x320000;
+}
+
+static void
+Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c5000;
+}
+
+static void
+Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x420000;
+}
+
+static void
+Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1cf000;
+}
+
+static void
+Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2480;
+}
+
+static void
+Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2800;
+}
+
+static void
+Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ef060;
+}
+
+static void
+Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ef020;
+}
+
+static void
+Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x76;
+}
+
+static void
+Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300005;
+}
+
+static void
+Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1076;
+}
+
+static void
+Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300006;
+}
+
+static void
+Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc30000;
+}
+
+static void
+Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1bf000;
+}
+
+static void
+Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd30000;
+}
+
+static void
+Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d0000;
+}
+
+static void
+Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30400;
+}
+
+static void
+Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130400;
+}
+
+static void
+Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610400;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70c2;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e2;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f2;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf10000;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf12000;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11000;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13000;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7042;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7052;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x47082;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x57082;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7062;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7072;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7002;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7012;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7022;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7032;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf19000;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf18000;
+}
+
+static void
+Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135300;
+}
+
+static void
+Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35300;
+}
+
+static void
+Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615300;
+}
+
+static void
+Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35a00;
+}
+
+static void
+Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135a00;
+}
+
+static void
+Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615a00;
+}
+
+static void
+Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35b00;
+}
+
+static void
+Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135b00;
+}
+
+static void
+Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615b00;
+}
+
+static void
+Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35c00;
+}
+
+static void
+Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135c00;
+}
+
+static void
+Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615c00;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1f000;
+}
+
+static void
+Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x501000;
+}
+
+static void
+Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x509000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b9000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1bb000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ba000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1bd000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1bc000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c6000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30f00;
+}
+
+static void
+Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3f000;
+}
+
+static void
+Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30f10;
+}
+
+static void
+Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3f100;
+}
+
+static void
+Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30f20;
+}
+
+static void
+Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3f200;
+}
+
+static void
+Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30f30;
+}
+
+static void
+Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3f300;
+}
+
+static void
+Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90804;
+}
+
+static void
+Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca0004;
+}
+
+static void
+Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90904;
+}
+
+static void
+Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca1004;
+}
+
+static void
+Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90a04;
+}
+
+static void
+Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca2004;
+}
+
+static void
+Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90b04;
+}
+
+static void
+Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca3004;
+}
+
+static void
+Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90c04;
+}
+
+static void
+Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca4004;
+}
+
+static void
+Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90d04;
+}
+
+static void
+Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca5004;
+}
+
+static void
+Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90e04;
+}
+
+static void
+Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca6004;
+}
+
+static void
+Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90f04;
+}
+
+static void
+Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca7004;
+}
+
+static void
+Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d1080;
+}
+
+static void
+Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa50004;
+}
+
+static void
+Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d2080;
+}
+
+static void
+Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa90004;
+}
+
+static void
+Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d3000;
+}
+
+static void
+Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xac0004;
+}
+
+static void
+Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d3080;
+}
+
+static void
+Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xaf0004;
+}
+
+static void
+Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d6080;
+}
+
+static void
+Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa58004;
+}
+
+static void
+Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d7000;
+}
+
+static void
+Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa98004;
+}
+
+static void
+Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d7080;
+}
+
+static void
+Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xac8004;
+}
+
+static void
+Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d8080;
+}
+
+static void
+Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xaf8004;
+}
+
+static void
+Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d9000;
+}
+
+static void
+Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa60004;
+}
+
+static void
+Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1da000;
+}
+
+static void
+Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xaa0004;
+}
+
+static void
+Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1dc000;
+}
+
+static void
+Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xad0004;
+}
+
+static void
+Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d9080;
+}
+
+static void
+Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00004;
+}
+
+static void
+Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d4080;
+}
+
+static void
+Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa68004;
+}
+
+static void
+Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d5000;
+}
+
+static void
+Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xaa8004;
+}
+
+static void
+Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d6000;
+}
+
+static void
+Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xad8004;
+}
+
+static void
+Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d5080;
+}
+
+static void
+Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb08004;
+}
+
+static void
+Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1dd000;
+}
+
+static void
+Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa70004;
+}
+
+static void
+Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1de000;
+}
+
+static void
+Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xab0004;
+}
+
+static void
+Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1dd080;
+}
+
+static void
+Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xae0004;
+}
+
+static void
+Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1de080;
+}
+
+static void
+Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10004;
+}
+
+static void
+Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1da080;
+}
+
+static void
+Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa78004;
+}
+
+static void
+Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1db000;
+}
+
+static void
+Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xab8004;
+}
+
+static void
+Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1db080;
+}
+
+static void
+Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xae8004;
+}
+
+static void
+Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1dc080;
+}
+
+static void
+Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb18004;
+}
+
+static void
+Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e8000;
+}
+
+static void
+Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb20004;
+}
+
+static void
+Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f0000;
+}
+
+static void
+Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb50004;
+}
+
+static void
+Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e1080;
+}
+
+static void
+Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb80004;
+}
+
+static void
+Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e2080;
+}
+
+static void
+Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbb0004;
+}
+
+static void
+Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ec000;
+}
+
+static void
+Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb28004;
+}
+
+static void
+Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e9080;
+}
+
+static void
+Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb58004;
+}
+
+static void
+Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ea080;
+}
+
+static void
+Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb88004;
+}
+
+static void
+Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1eb000;
+}
+
+static void
+Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbb8004;
+}
+
+static void
+Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e7080;
+}
+
+static void
+Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30004;
+}
+
+static void
+Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e8080;
+}
+
+static void
+Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb60004;
+}
+
+static void
+Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e9000;
+}
+
+static void
+Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb90004;
+}
+
+static void
+Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ea000;
+}
+
+static void
+Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbc0004;
+}
+
+static void
+Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1df080;
+}
+
+static void
+Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb38004;
+}
+
+static void
+Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e1000;
+}
+
+static void
+Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb68004;
+}
+
+static void
+Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e2000;
+}
+
+static void
+Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb98004;
+}
+
+static void
+Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e4000;
+}
+
+static void
+Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbc8004;
+}
+
+static void
+Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e6000;
+}
+
+static void
+Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb40004;
+}
+
+static void
+Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e5080;
+}
+
+static void
+Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb70004;
+}
+
+static void
+Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e6080;
+}
+
+static void
+Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xba0004;
+}
+
+static void
+Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e7000;
+}
+
+static void
+Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbd0004;
+}
+
+static void
+Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e3000;
+}
+
+static void
+Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb48004;
+}
+
+static void
+Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e3080;
+}
+
+static void
+Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb78004;
+}
+
+static void
+Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e4080;
+}
+
+static void
+Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xba8004;
+}
+
+static void
+Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1e5000;
+}
+
+static void
+Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbd8004;
+}
+
+static void
+Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ed030;
+}
+
+static void
+Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10004;
+}
+
+static void
+Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee010;
+}
+
+static void
+Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc12004;
+}
+
+static void
+Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee020;
+}
+
+static void
+Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20004;
+}
+
+static void
+Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ef000;
+}
+
+static void
+Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc22004;
+}
+
+static void
+Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ed000;
+}
+
+static void
+Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc11004;
+}
+
+static void
+Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee000;
+}
+
+static void
+Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc13004;
+}
+
+static void
+Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ed010;
+}
+
+static void
+Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc21004;
+}
+
+static void
+Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ed020;
+}
+
+static void
+Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc23004;
+}
+
+static void
+Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f0080;
+}
+
+static void
+Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc30004;
+}
+
+static void
+Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f00c0;
+}
+
+static void
+Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc38004;
+}
+
+static void
+Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3000;
+}
+
+static void
+Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc40004;
+}
+
+static void
+Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3040;
+}
+
+static void
+Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc48004;
+}
+
+static void
+Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ec080;
+}
+
+static void
+Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc34004;
+}
+
+static void
+Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ec0c0;
+}
+
+static void
+Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc3c004;
+}
+
+static void
+Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f4000;
+}
+
+static void
+Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc44004;
+}
+
+static void
+Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f8000;
+}
+
+static void
+Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc4c004;
+}
+
+static void
+Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16b88;
+}
+
+static void
+Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16808;
+}
+
+static void
+Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2400;
+}
+
+static void
+Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90004;
+}
+
+static void
+Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10780;
+}
+
+static void
+Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10708;
+}
+
+static void
+Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10688;
+}
+
+static void
+Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10700;
+}
+
+static void
+Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c200;
+}
+
+static void
+Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c004;
+}
+
+static void
+Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10480;
+}
+
+static void
+Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10400;
+}
+
+static void
+Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1df000;
+}
+
+static void
+Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00004;
+}
+
+static void
+Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1eb080;
+}
+
+static void
+Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc08004;
+}
+
+static void
+Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3081;
+}
+
+static void
+Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcb0004;
+}
+
+static void
+Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3080;
+}
+
+static void
+Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcb8004;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d8000;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbe0004;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d4000;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbe8004;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d2000;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbf0004;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1d1000;
+}
+
+static void
+Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbf8004;
+}
+
+static void
+Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x51000;
+}
+
+static void
+Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16b08;
+}
+
+static void
+Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16e48;
+}
+
+static void
+Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16e28;
+}
+
+static void
+Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16e18;
+}
+
+static void
+Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16e08;
+}
+
+static void
+Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16908;
+}
+
+static void
+Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16888;
+}
+
+static void
+Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16085;
+}
+
+static void
+Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16007;
+}
+
+static void
+Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2500;
+}
+
+static void
+Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90414;
+}
+
+static void
+Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f6000;
+}
+
+static void
+Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe50014;
+}
+
+static void
+Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f5000;
+}
+
+static void
+Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe60014;
+}
+
+static void
+Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1ee030;
+}
+
+static void
+Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe72034;
+}
+
+static void
+Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16006;
+}
+
+static void
+Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16005;
+}
+
+static void
+Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50139;
+}
+
+static void
+Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16047;
+}
+
+static void
+Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16027;
+}
+
+static void
+Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16017;
+}
+
+static void
+Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3086;
+}
+
+static void
+Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe70014;
+}
+
+static void
+Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3084;
+}
+
+static void
+Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc70004;
+}
+
+static void
+Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3082;
+}
+
+static void
+Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc78004;
+}
+
+static void
+Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3083;
+}
+
+static void
+Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc80004;
+}
+
+static void
+Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3088;
+}
+
+static void
+Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc88004;
+}
+
+static void
+Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10500;
+}
+
+static void
+Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10788;
+}
+
+static void
+Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c600;
+}
+
+static void
+Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c480;
+}
+
+static void
+Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10580;
+}
+
+static void
+Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10588;
+}
+
+static void
+Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10200;
+}
+
+static void
+Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10600;
+}
+
+static void
+Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c400;
+}
+
+static void
+Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c488;
+}
+
+static void
+Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c500;
+}
+
+static void
+Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10508;
+}
+
+static void
+Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10608;
+}
+
+static void
+Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10680;
+}
+
+static void
+Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c408;
+}
+
+static void
+Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c002;
+}
+
+static void
+Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c001;
+}
+
+static void
+Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1c000;
+}
+
+static void
+Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x52000;
+}
+
+static void
+Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50035;
+}
+
+static void
+Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5003c;
+}
+
+static void
+Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50039;
+}
+
+static void
+Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50032;
+}
+
+static void
+Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50034;
+}
+
+static void
+Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50000;
+}
+
+static void
+Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50010;
+}
+
+static void
+Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50030;
+}
+
+static void
+Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50036;
+}
+
+static void
+Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x500b9;
+}
+
+static void
+Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5003a;
+}
+
+static void
+Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50031;
+}
+
+static void
+Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50038;
+}
+
+static void
+Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50033;
+}
+
+static void
+Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50037;
+}
+
+static void
+Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x14000;
+}
+
+static void
+Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15000;
+}
+
+static void
+Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x14800;
+}
+
+static void
+Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16a08;
+}
+
+static void
+Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16a88;
+}
+
+static void
+Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16988;
+}
+
+static void
+Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18000;
+}
+
+static void
+Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16c08;
+}
+
+static void
+Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1000;
+}
+
+static void
+Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc50004;
+}
+
+static void
+Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1800;
+}
+
+static void
+Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc50404;
+}
+
+static void
+Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f1400;
+}
+
+static void
+Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc50804;
+}
+
+static void
+Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2600;
+}
+
+static void
+Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90014;
+}
+
+static void
+Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2504;
+}
+
+static void
+Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90114;
+}
+
+static void
+Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2502;
+}
+
+static void
+Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90214;
+}
+
+static void
+Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f5001;
+}
+
+static void
+Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe10014;
+}
+
+static void
+Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f5008;
+}
+
+static void
+Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20014;
+}
+
+static void
+Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f5004;
+}
+
+static void
+Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30014;
+}
+
+static void
+Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2000;
+}
+
+static void
+Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc50c04;
+}
+
+static void
+Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f2501;
+}
+
+static void
+Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc90314;
+}
+
+static void
+Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f5002;
+}
+
+static void
+Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe40014;
+}
+
+static void
+Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50800;
+}
+
+static void
+Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50040;
+}
+
+static void
+Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50020;
+}
+
+static void
+Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1f3085;
+}
+
+static void
+Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe74014;
+}
+
+static void
+Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60101;
+}
+
+static void
+Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6008b;
+}
+
+static void
+Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60180;
+}
+
+static void
+Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6008f;
+}
+
+static void
+Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6008c;
+}
+
+static void
+Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60108;
+}
+
+static void
+Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6008e;
+}
+
+static void
+Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6008a;
+}
+
+static void
+Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60104;
+}
+
+static void
+Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6008d;
+}
+
+static void
+Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60089;
+}
+
+static void
+Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60102;
+}
+
+static void
+Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60006;
+}
+
+static void
+Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64000;
+}
+
+static void
+Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000f;
+}
+
+static void
+Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60005;
+}
+
+static void
+Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60100;
+}
+
+static void
+Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000e;
+}
+
+static void
+Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60003;
+}
+
+static void
+Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60080;
+}
+
+static void
+Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000d;
+}
+
+static void
+Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x68000;
+}
+
+static void
+Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60008;
+}
+
+static void
+Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000b;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60181;
+}
+
+static void
+Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6010b;
+}
+
+static void
+Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60189;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6010f;
+}
+
+static void
+Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6010c;
+}
+
+static void
+Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60187;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6010e;
+}
+
+static void
+Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6010a;
+}
+
+static void
+Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60186;
+}
+
+static void
+Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6010d;
+}
+
+static void
+Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60109;
+}
+
+static void
+Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60185;
+}
+
+static void
+Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000c;
+}
+
+static void
+Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60088;
+}
+
+static void
+Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000a;
+}
+
+static void
+Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60084;
+}
+
+static void
+Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60009;
+}
+
+static void
+Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60082;
+}
+
+static void
+Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60007;
+}
+
+static void
+Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60081;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60183;
+}
+
+static void
+Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6018d;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60188;
+}
+
+static void
+Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6018b;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60184;
+}
+
+static void
+Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6018c;
+}
+
+static void
+Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60182;
+}
+
+static void
+Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6018a;
+}
+
+static void
+Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15807;
+}
+
+static void
+Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15806;
+}
+
+static void
+Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1580a;
+}
+
+static void
+Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15809;
+}
+
+static void
+Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1580b;
+}
+
+static void
+Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1580c;
+}
+
+static void
+Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1580e;
+}
+
+static void
+Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1580d;
+}
+
+static void
+Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15800;
+}
+
+static void
+Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16000;
+}
+
+static void
+Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15802;
+}
+
+static void
+Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15801;
+}
+
+static void
+Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15808;
+}
+
+static void
+Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15804;
+}
+
+static void
+Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15805;
+}
+
+static void
+Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15803;
+}
+
+static void
+Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16001;
+}
+
+static void
+Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1580f;
+}
+
+static void
+Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16004;
+}
+
+static void
+Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16002;
+}
+
+static void
+Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16800;
+}
+
+static void
+Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16008;
+}
+
+static void
+Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16003;
+}
+
+static void
+Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x17000;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20007;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20002;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000c;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20003;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20005;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20009;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20004;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20006;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20001;
+}
+
+static void
+Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000a;
+}
+
+static void
+Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20008;
+}
+
+static void
+Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30008;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000e;
+}
+
+static void
+Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30006;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30001;
+}
+
+static void
+Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30002;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000b;
+}
+
+static void
+Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30003;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000f;
+}
+
+static void
+Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30004;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000d;
+}
+
+static void
+Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30005;
+}
+
+static void
+Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000a;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40004;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000d;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000e;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30007;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40001;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000c;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000f;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30009;
+}
+
+static void
+Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40002;
+}
+
+static void
+Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000b;
+}
+
+static void
+Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000b;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40005;
+}
+
+static void
+Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000f;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40009;
+}
+
+static void
+Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000a;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40008;
+}
+
+static void
+Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000d;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40006;
+}
+
+static void
+Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000c;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40003;
+}
+
+static void
+Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000e;
+}
+
+static void
+Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40007;
+}
+
+static void
+Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64004;
+}
+
+static void
+Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64080;
+}
+
+static void
+Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64008;
+}
+
+static void
+Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64100;
+}
+
+static void
+Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64003;
+}
+
+static void
+Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64006;
+}
+
+static void
+Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64005;
+}
+
+static void
+Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64007;
+}
+
+static void
+Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64009;
+}
+
+static void
+Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6400c;
+}
+
+static void
+Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6400a;
+}
+
+static void
+Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6400b;
+}
+
+static void
+Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6400d;
+}
+
+static void
+Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6400f;
+}
+
+static void
+Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6400e;
+}
+
+static void
+Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64081;
+}
+
+static void
+Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60002;
+}
+
+static void
+Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60001;
+}
+
+static void
+Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60004;
+}
+
+static void
+Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60083;
+}
+
+static void
+Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60086;
+}
+
+static void
+Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60085;
+}
+
+static void
+Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60087;
+}
+
+static void
+Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60103;
+}
+
+static void
+Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60106;
+}
+
+static void
+Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60105;
+}
+
+static void
+Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60107;
+}
+
+static void
+Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6018e;
+}
+
+static void
+Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64001;
+}
+
+static void
+Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6018f;
+}
+
+static void
+Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x64002;
+}
+
+static void
+Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00014;
+}
+
+static void
+Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00004;
+}
+
+static void
+Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10004;
+}
+
+static void
+Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe7e014;
+}
+
+static void
+Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca8004;
+}
+
+static void
+Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc60004;
+}
+
+static void
+Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00024;
+}
+
+static void
+Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa20004;
+}
+
+static void
+Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00004;
+}
+
+static void
+Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01004;
+}
+
+static void
+Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02004;
+}
+
+static void
+Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30004;
+}
+
+static void
+Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa40004;
+}
+
+static void
+Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11004;
+}
+
+static void
+Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00004;
+}
+
+static void
+Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe7c014;
+}
+
+static void
+Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe7d014;
+}
+
+static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+ Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+ Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+ Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+ Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+ Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
+ Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
+ Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
+ Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
+ Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
+ Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
+ Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
+ Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
+ Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
+ Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
+ Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
+ Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
+ Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
+ Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
+ Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
+ Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
+ Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
+ Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
+ Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
+ Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
+ Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
+ Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
+ Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
+ Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
+ Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
+ Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
+ Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
+ Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
+ Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
+ Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
+ Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
+ Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+ Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+ Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+ Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+ Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+ Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+ Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+ Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+ Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
+ Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
+ Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
+ Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
+ Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
+ Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
+ Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
+ Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
+ Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
+ Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
+ Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
+ Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
+ Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
+ Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
+ Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
+ Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
+ Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
+ Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
+ Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
+ Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
+ Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
+ Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
+ Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
+ Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
+ Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
+ Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
+ Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
+ Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
+ Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
+ Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
+ Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
+ Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
+ Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
+ Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
+ Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
+ Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
+ Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
+ Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
+ Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
+ Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
+ Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
+ Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
+ Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
+ Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
+ Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
+ Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
+ Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
+ Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
+ Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
+ Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
+ Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
+ Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
+ Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
+ Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
+ Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
+ Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
+ Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
+ Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
+ Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
+ Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
+ Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
+ Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
+ Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
+ Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
+ Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
+ Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
+ Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
+ Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
+ Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
+ Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
+ Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
+ Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
+ Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
+ Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
+ Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
+ Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
+ Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
+ Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
+ Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
+ Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
+ Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
+ Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
+ Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
+ Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
+ Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
+ Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
+ Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
+ Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
+ Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
+ Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
+ Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
+ Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
+ Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
+ Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
+ Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
+ Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
+ Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
+ Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
+ Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
+ Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
+ Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
+ Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
+ Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
+ Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
+ Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
+ Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
+ Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
+ Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
+ Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
+ Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
+ Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
+ Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
+ Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
+ Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
+ Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
+ Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
+ Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
+ 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
+ Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
+ Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
+ Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
+ Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
+ Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
+ Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
+ Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
+ Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
+ Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
+ Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
+ Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
+ Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
+ Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
+ Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
+ Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
+ Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
+};
+
+static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
+ Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
+};
+
+\f
+/* Opcode table. */
+
+static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_shift32x5, 3 },
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_shift32x5, 3 },
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
+ { FUNCUNIT_ae_add32, 3 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
+ { FUNCUNIT_ae_shift32x4, 2 },
+ { FUNCUNIT_ae_subshift, 2 }
+};
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", ICLASS_xt_iclass_excw,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", ICLASS_xt_iclass_rfe,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", ICLASS_xt_iclass_rfde,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", ICLASS_xt_iclass_syscall,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "call12", ICLASS_xt_iclass_call12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", ICLASS_xt_iclass_call8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", ICLASS_xt_iclass_call4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", ICLASS_xt_iclass_callx12,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", ICLASS_xt_iclass_callx8,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", ICLASS_xt_iclass_callx4,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", ICLASS_xt_iclass_entry,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", ICLASS_xt_iclass_movsp,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", ICLASS_xt_iclass_rotw,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", ICLASS_xt_iclass_retw,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", ICLASS_xt_iclass_rfwou,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", ICLASS_xt_iclass_l32e,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", ICLASS_xt_iclass_s32e,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+ 0,
+ Opcode_rsr_windowstart_encode_fns, 0, 0 },
+ { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+ 0,
+ Opcode_wsr_windowstart_encode_fns, 0, 0 },
+ { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+ 0,
+ Opcode_xsr_windowstart_encode_fns, 0, 0 },
+ { "add.n", ICLASS_xt_iclass_add_n,
+ 0,
+ Opcode_add_n_encode_fns, 0, 0 },
+ { "addi.n", ICLASS_xt_iclass_addi_n,
+ 0,
+ Opcode_addi_n_encode_fns, 0, 0 },
+ { "beqz.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_n_encode_fns, 0, 0 },
+ { "bnez.n", ICLASS_xt_iclass_bz6,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_n_encode_fns, 0, 0 },
+ { "ill.n", ICLASS_xt_iclass_ill_n,
+ 0,
+ Opcode_ill_n_encode_fns, 0, 0 },
+ { "l32i.n", ICLASS_xt_iclass_loadi4,
+ 0,
+ Opcode_l32i_n_encode_fns, 0, 0 },
+ { "mov.n", ICLASS_xt_iclass_mov_n,
+ 0,
+ Opcode_mov_n_encode_fns, 0, 0 },
+ { "movi.n", ICLASS_xt_iclass_movi_n,
+ 0,
+ Opcode_movi_n_encode_fns, 0, 0 },
+ { "nop.n", ICLASS_xt_iclass_nopn,
+ 0,
+ Opcode_nop_n_encode_fns, 0, 0 },
+ { "ret.n", ICLASS_xt_iclass_retn,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_n_encode_fns, 0, 0 },
+ { "s32i.n", ICLASS_xt_iclass_storei4,
+ 0,
+ Opcode_s32i_n_encode_fns, 0, 0 },
+ { "rur.threadptr", ICLASS_rur_threadptr,
+ 0,
+ Opcode_rur_threadptr_encode_fns, 0, 0 },
+ { "wur.threadptr", ICLASS_wur_threadptr,
+ 0,
+ Opcode_wur_threadptr_encode_fns, 0, 0 },
+ { "addi", ICLASS_xt_iclass_addi,
+ 0,
+ Opcode_addi_encode_fns, 0, 0 },
+ { "addmi", ICLASS_xt_iclass_addmi,
+ 0,
+ Opcode_addmi_encode_fns, 0, 0 },
+ { "add", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_add_encode_fns, 0, 0 },
+ { "sub", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_sub_encode_fns, 0, 0 },
+ { "addx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx2_encode_fns, 0, 0 },
+ { "addx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx4_encode_fns, 0, 0 },
+ { "addx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_addx8_encode_fns, 0, 0 },
+ { "subx2", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx2_encode_fns, 0, 0 },
+ { "subx4", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx4_encode_fns, 0, 0 },
+ { "subx8", ICLASS_xt_iclass_addsub,
+ 0,
+ Opcode_subx8_encode_fns, 0, 0 },
+ { "and", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_and_encode_fns, 0, 0 },
+ { "or", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_or_encode_fns, 0, 0 },
+ { "xor", ICLASS_xt_iclass_bit,
+ 0,
+ Opcode_xor_encode_fns, 0, 0 },
+ { "beqi", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqi_encode_fns, 0, 0 },
+ { "bnei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnei_encode_fns, 0, 0 },
+ { "bgei", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgei_encode_fns, 0, 0 },
+ { "blti", ICLASS_xt_iclass_bsi8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blti_encode_fns, 0, 0 },
+ { "bbci", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbci_encode_fns, 0, 0 },
+ { "bbsi", ICLASS_xt_iclass_bsi8b,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbsi_encode_fns, 0, 0 },
+ { "bgeui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeui_encode_fns, 0, 0 },
+ { "bltui", ICLASS_xt_iclass_bsi8u,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltui_encode_fns, 0, 0 },
+ { "beq", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beq_encode_fns, 0, 0 },
+ { "bne", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bne_encode_fns, 0, 0 },
+ { "bge", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bge_encode_fns, 0, 0 },
+ { "blt", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_blt_encode_fns, 0, 0 },
+ { "bgeu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgeu_encode_fns, 0, 0 },
+ { "bltu", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltu_encode_fns, 0, 0 },
+ { "bany", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bany_encode_fns, 0, 0 },
+ { "bnone", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnone_encode_fns, 0, 0 },
+ { "ball", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_ball_encode_fns, 0, 0 },
+ { "bnall", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnall_encode_fns, 0, 0 },
+ { "bbc", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbc_encode_fns, 0, 0 },
+ { "bbs", ICLASS_xt_iclass_bst8,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bbs_encode_fns, 0, 0 },
+ { "beqz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_beqz_encode_fns, 0, 0 },
+ { "bnez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bnez_encode_fns, 0, 0 },
+ { "bgez", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bgez_encode_fns, 0, 0 },
+ { "bltz", ICLASS_xt_iclass_bsz12,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bltz_encode_fns, 0, 0 },
+ { "call0", ICLASS_xt_iclass_call0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call0_encode_fns, 0, 0 },
+ { "callx0", ICLASS_xt_iclass_callx0,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx0_encode_fns, 0, 0 },
+ { "extui", ICLASS_xt_iclass_exti,
+ 0,
+ Opcode_extui_encode_fns, 0, 0 },
+ { "ill", ICLASS_xt_iclass_ill,
+ 0,
+ Opcode_ill_encode_fns, 0, 0 },
+ { "j", ICLASS_xt_iclass_jump,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_j_encode_fns, 0, 0 },
+ { "jx", ICLASS_xt_iclass_jumpx,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_jx_encode_fns, 0, 0 },
+ { "l16ui", ICLASS_xt_iclass_l16ui,
+ 0,
+ Opcode_l16ui_encode_fns, 0, 0 },
+ { "l16si", ICLASS_xt_iclass_l16si,
+ 0,
+ Opcode_l16si_encode_fns, 0, 0 },
+ { "l32i", ICLASS_xt_iclass_l32i,
+ 0,
+ Opcode_l32i_encode_fns, 0, 0 },
+ { "l32r", ICLASS_xt_iclass_l32r,
+ 0,
+ Opcode_l32r_encode_fns, 0, 0 },
+ { "l8ui", ICLASS_xt_iclass_l8i,
+ 0,
+ Opcode_l8ui_encode_fns, 0, 0 },
+ { "loop", ICLASS_xt_iclass_loop,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loop_encode_fns, 0, 0 },
+ { "loopnez", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopnez_encode_fns, 0, 0 },
+ { "loopgtz", ICLASS_xt_iclass_loopz,
+ XTENSA_OPCODE_IS_LOOP,
+ Opcode_loopgtz_encode_fns, 0, 0 },
+ { "movi", ICLASS_xt_iclass_movi,
+ 0,
+ Opcode_movi_encode_fns, 0, 0 },
+ { "moveqz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_moveqz_encode_fns, 0, 0 },
+ { "movnez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movnez_encode_fns, 0, 0 },
+ { "movltz", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movltz_encode_fns, 0, 0 },
+ { "movgez", ICLASS_xt_iclass_movz,
+ 0,
+ Opcode_movgez_encode_fns, 0, 0 },
+ { "neg", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_neg_encode_fns, 0, 0 },
+ { "abs", ICLASS_xt_iclass_neg,
+ 0,
+ Opcode_abs_encode_fns, 0, 0 },
+ { "nop", ICLASS_xt_iclass_nop,
+ 0,
+ Opcode_nop_encode_fns, 0, 0 },
+ { "ret", ICLASS_xt_iclass_return,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_ret_encode_fns, 0, 0 },
+ { "simcall", ICLASS_xt_iclass_simcall,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "s16i", ICLASS_xt_iclass_s16i,
+ 0,
+ Opcode_s16i_encode_fns, 0, 0 },
+ { "s32i", ICLASS_xt_iclass_s32i,
+ 0,
+ Opcode_s32i_encode_fns, 0, 0 },
+ { "s8i", ICLASS_xt_iclass_s8i,
+ 0,
+ Opcode_s8i_encode_fns, 0, 0 },
+ { "ssr", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssr_encode_fns, 0, 0 },
+ { "ssl", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssl_encode_fns, 0, 0 },
+ { "ssa8l", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8l_encode_fns, 0, 0 },
+ { "ssa8b", ICLASS_xt_iclass_sar,
+ 0,
+ Opcode_ssa8b_encode_fns, 0, 0 },
+ { "ssai", ICLASS_xt_iclass_sari,
+ 0,
+ Opcode_ssai_encode_fns, 0, 0 },
+ { "sll", ICLASS_xt_iclass_shifts,
+ 0,
+ Opcode_sll_encode_fns, 0, 0 },
+ { "src", ICLASS_xt_iclass_shiftst,
+ 0,
+ Opcode_src_encode_fns, 0, 0 },
+ { "srl", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_srl_encode_fns, 0, 0 },
+ { "sra", ICLASS_xt_iclass_shiftt,
+ 0,
+ Opcode_sra_encode_fns, 0, 0 },
+ { "slli", ICLASS_xt_iclass_slli,
+ 0,
+ Opcode_slli_encode_fns, 0, 0 },
+ { "srai", ICLASS_xt_iclass_srai,
+ 0,
+ Opcode_srai_encode_fns, 0, 0 },
+ { "srli", ICLASS_xt_iclass_srli,
+ 0,
+ Opcode_srli_encode_fns, 0, 0 },
+ { "memw", ICLASS_xt_iclass_memw,
+ 0,
+ Opcode_memw_encode_fns, 0, 0 },
+ { "extw", ICLASS_xt_iclass_extw,
+ 0,
+ Opcode_extw_encode_fns, 0, 0 },
+ { "isync", ICLASS_xt_iclass_isync,
+ 0,
+ Opcode_isync_encode_fns, 0, 0 },
+ { "rsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_rsync_encode_fns, 0, 0 },
+ { "esync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_esync_encode_fns, 0, 0 },
+ { "dsync", ICLASS_xt_iclass_sync,
+ 0,
+ Opcode_dsync_encode_fns, 0, 0 },
+ { "rsil", ICLASS_xt_iclass_rsil,
+ 0,
+ Opcode_rsil_encode_fns, 0, 0 },
+ { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+ 0,
+ Opcode_rsr_lend_encode_fns, 0, 0 },
+ { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+ 0,
+ Opcode_wsr_lend_encode_fns, 0, 0 },
+ { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+ 0,
+ Opcode_xsr_lend_encode_fns, 0, 0 },
+ { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+ 0,
+ Opcode_rsr_lcount_encode_fns, 0, 0 },
+ { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+ 0,
+ Opcode_wsr_lcount_encode_fns, 0, 0 },
+ { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+ 0,
+ Opcode_xsr_lcount_encode_fns, 0, 0 },
+ { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+ 0,
+ Opcode_rsr_lbeg_encode_fns, 0, 0 },
+ { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+ 0,
+ Opcode_wsr_lbeg_encode_fns, 0, 0 },
+ { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+ 0,
+ Opcode_xsr_lbeg_encode_fns, 0, 0 },
+ { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+ 0,
+ Opcode_rsr_sar_encode_fns, 0, 0 },
+ { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+ 0,
+ Opcode_wsr_sar_encode_fns, 0, 0 },
+ { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+ 0,
+ Opcode_xsr_sar_encode_fns, 0, 0 },
+ { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+ 0,
+ Opcode_rsr_litbase_encode_fns, 0, 0 },
+ { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+ 0,
+ Opcode_wsr_litbase_encode_fns, 0, 0 },
+ { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+ 0,
+ Opcode_xsr_litbase_encode_fns, 0, 0 },
+ { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+ 0,
+ Opcode_rsr_configid0_encode_fns, 0, 0 },
+ { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+ 0,
+ Opcode_wsr_configid0_encode_fns, 0, 0 },
+ { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+ 0,
+ Opcode_rsr_configid1_encode_fns, 0, 0 },
+ { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+ 0,
+ Opcode_rsr_ps_encode_fns, 0, 0 },
+ { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+ 0,
+ Opcode_wsr_ps_encode_fns, 0, 0 },
+ { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+ 0,
+ Opcode_xsr_ps_encode_fns, 0, 0 },
+ { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+ 0,
+ Opcode_rsr_epc1_encode_fns, 0, 0 },
+ { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+ 0,
+ Opcode_wsr_epc1_encode_fns, 0, 0 },
+ { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+ 0,
+ Opcode_xsr_epc1_encode_fns, 0, 0 },
+ { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+ 0,
+ Opcode_rsr_excsave1_encode_fns, 0, 0 },
+ { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+ 0,
+ Opcode_wsr_excsave1_encode_fns, 0, 0 },
+ { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+ 0,
+ Opcode_xsr_excsave1_encode_fns, 0, 0 },
+ { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+ 0,
+ Opcode_rsr_epc2_encode_fns, 0, 0 },
+ { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+ 0,
+ Opcode_wsr_epc2_encode_fns, 0, 0 },
+ { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+ 0,
+ Opcode_xsr_epc2_encode_fns, 0, 0 },
+ { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+ 0,
+ Opcode_rsr_excsave2_encode_fns, 0, 0 },
+ { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+ 0,
+ Opcode_wsr_excsave2_encode_fns, 0, 0 },
+ { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+ 0,
+ Opcode_xsr_excsave2_encode_fns, 0, 0 },
+ { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+ 0,
+ Opcode_rsr_eps2_encode_fns, 0, 0 },
+ { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+ 0,
+ Opcode_wsr_eps2_encode_fns, 0, 0 },
+ { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+ 0,
+ Opcode_xsr_eps2_encode_fns, 0, 0 },
+ { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+ 0,
+ Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+ { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+ 0,
+ Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+ { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+ 0,
+ Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+ { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+ 0,
+ Opcode_rsr_depc_encode_fns, 0, 0 },
+ { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+ 0,
+ Opcode_wsr_depc_encode_fns, 0, 0 },
+ { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+ 0,
+ Opcode_xsr_depc_encode_fns, 0, 0 },
+ { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+ 0,
+ Opcode_rsr_exccause_encode_fns, 0, 0 },
+ { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+ 0,
+ Opcode_wsr_exccause_encode_fns, 0, 0 },
+ { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+ 0,
+ Opcode_xsr_exccause_encode_fns, 0, 0 },
+ { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+ 0,
+ Opcode_rsr_misc0_encode_fns, 0, 0 },
+ { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+ 0,
+ Opcode_wsr_misc0_encode_fns, 0, 0 },
+ { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+ 0,
+ Opcode_xsr_misc0_encode_fns, 0, 0 },
+ { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+ 0,
+ Opcode_rsr_misc1_encode_fns, 0, 0 },
+ { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+ 0,
+ Opcode_wsr_misc1_encode_fns, 0, 0 },
+ { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+ 0,
+ Opcode_xsr_misc1_encode_fns, 0, 0 },
+ { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+ 0,
+ Opcode_rsr_prid_encode_fns, 0, 0 },
+ { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+ 0,
+ Opcode_rsr_vecbase_encode_fns, 0, 0 },
+ { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+ 0,
+ Opcode_wsr_vecbase_encode_fns, 0, 0 },
+ { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+ 0,
+ Opcode_xsr_vecbase_encode_fns, 0, 0 },
+ { "mul16u", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16u_encode_fns, 0, 0 },
+ { "mul16s", ICLASS_xt_mul16,
+ 0,
+ Opcode_mul16s_encode_fns, 0, 0 },
+ { "mull", ICLASS_xt_mul32,
+ 0,
+ Opcode_mull_encode_fns, 0, 0 },
+ { "rfi", ICLASS_xt_iclass_rfi,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfi_encode_fns, 0, 0 },
+ { "waiti", ICLASS_xt_iclass_wait,
+ 0,
+ Opcode_waiti_encode_fns, 0, 0 },
+ { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+ 0,
+ Opcode_rsr_interrupt_encode_fns, 0, 0 },
+ { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+ 0,
+ Opcode_wsr_intset_encode_fns, 0, 0 },
+ { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+ 0,
+ Opcode_wsr_intclear_encode_fns, 0, 0 },
+ { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+ 0,
+ Opcode_rsr_intenable_encode_fns, 0, 0 },
+ { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+ 0,
+ Opcode_wsr_intenable_encode_fns, 0, 0 },
+ { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+ 0,
+ Opcode_xsr_intenable_encode_fns, 0, 0 },
+ { "break", ICLASS_xt_iclass_break,
+ 0,
+ Opcode_break_encode_fns, 0, 0 },
+ { "break.n", ICLASS_xt_iclass_break_n,
+ 0,
+ Opcode_break_n_encode_fns, 0, 0 },
+ { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+ 0,
+ Opcode_rsr_debugcause_encode_fns, 0, 0 },
+ { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+ 0,
+ Opcode_wsr_debugcause_encode_fns, 0, 0 },
+ { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+ 0,
+ Opcode_xsr_debugcause_encode_fns, 0, 0 },
+ { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+ 0,
+ Opcode_rsr_icount_encode_fns, 0, 0 },
+ { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+ 0,
+ Opcode_wsr_icount_encode_fns, 0, 0 },
+ { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+ 0,
+ Opcode_xsr_icount_encode_fns, 0, 0 },
+ { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+ 0,
+ Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+ { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+ 0,
+ Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+ { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+ 0,
+ Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+ { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+ 0,
+ Opcode_rsr_ddr_encode_fns, 0, 0 },
+ { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+ 0,
+ Opcode_wsr_ddr_encode_fns, 0, 0 },
+ { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+ 0,
+ Opcode_xsr_ddr_encode_fns, 0, 0 },
+ { "rfdo", ICLASS_xt_iclass_rfdo,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdo_encode_fns, 0, 0 },
+ { "rfdd", ICLASS_xt_iclass_rfdd,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfdd_encode_fns, 0, 0 },
+ { "andb", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_andb_encode_fns, 0, 0 },
+ { "andbc", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_andbc_encode_fns, 0, 0 },
+ { "orb", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_orb_encode_fns, 0, 0 },
+ { "orbc", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_orbc_encode_fns, 0, 0 },
+ { "xorb", ICLASS_xt_iclass_bbool1,
+ 0,
+ Opcode_xorb_encode_fns, 0, 0 },
+ { "any4", ICLASS_xt_iclass_bbool4,
+ 0,
+ Opcode_any4_encode_fns, 0, 0 },
+ { "all4", ICLASS_xt_iclass_bbool4,
+ 0,
+ Opcode_all4_encode_fns, 0, 0 },
+ { "any8", ICLASS_xt_iclass_bbool8,
+ 0,
+ Opcode_any8_encode_fns, 0, 0 },
+ { "all8", ICLASS_xt_iclass_bbool8,
+ 0,
+ Opcode_all8_encode_fns, 0, 0 },
+ { "bf", ICLASS_xt_iclass_bbranch,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bf_encode_fns, 0, 0 },
+ { "bt", ICLASS_xt_iclass_bbranch,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_bt_encode_fns, 0, 0 },
+ { "movf", ICLASS_xt_iclass_bmove,
+ 0,
+ Opcode_movf_encode_fns, 0, 0 },
+ { "movt", ICLASS_xt_iclass_bmove,
+ 0,
+ Opcode_movt_encode_fns, 0, 0 },
+ { "rsr.br", ICLASS_xt_iclass_RSR_BR,
+ 0,
+ Opcode_rsr_br_encode_fns, 0, 0 },
+ { "wsr.br", ICLASS_xt_iclass_WSR_BR,
+ 0,
+ Opcode_wsr_br_encode_fns, 0, 0 },
+ { "xsr.br", ICLASS_xt_iclass_XSR_BR,
+ 0,
+ Opcode_xsr_br_encode_fns, 0, 0 },
+ { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+ 0,
+ Opcode_rsr_ccount_encode_fns, 0, 0 },
+ { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+ 0,
+ Opcode_wsr_ccount_encode_fns, 0, 0 },
+ { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+ 0,
+ Opcode_xsr_ccount_encode_fns, 0, 0 },
+ { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+ 0,
+ Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+ { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+ 0,
+ Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+ { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+ 0,
+ Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+ { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+ 0,
+ Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+ { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+ 0,
+ Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+ { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+ 0,
+ Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+ { "ipf", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ipf_encode_fns, 0, 0 },
+ { "ihi", ICLASS_xt_iclass_icache,
+ 0,
+ Opcode_ihi_encode_fns, 0, 0 },
+ { "iii", ICLASS_xt_iclass_icache_inv,
+ 0,
+ Opcode_iii_encode_fns, 0, 0 },
+ { "lict", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_lict_encode_fns, 0, 0 },
+ { "licw", ICLASS_xt_iclass_licx,
+ 0,
+ Opcode_licw_encode_fns, 0, 0 },
+ { "sict", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sict_encode_fns, 0, 0 },
+ { "sicw", ICLASS_xt_iclass_sicx,
+ 0,
+ Opcode_sicw_encode_fns, 0, 0 },
+ { "dhwb", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwb_encode_fns, 0, 0 },
+ { "dhwbi", ICLASS_xt_iclass_dcache,
+ 0,
+ Opcode_dhwbi_encode_fns, 0, 0 },
+ { "diwb", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwb_encode_fns, 0, 0 },
+ { "diwbi", ICLASS_xt_iclass_dcache_ind,
+ 0,
+ Opcode_diwbi_encode_fns, 0, 0 },
+ { "dhi", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dhi_encode_fns, 0, 0 },
+ { "dii", ICLASS_xt_iclass_dcache_inv,
+ 0,
+ Opcode_dii_encode_fns, 0, 0 },
+ { "dpfr", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfr_encode_fns, 0, 0 },
+ { "dpfw", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfw_encode_fns, 0, 0 },
+ { "dpfro", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfro_encode_fns, 0, 0 },
+ { "dpfwo", ICLASS_xt_iclass_dpf,
+ 0,
+ Opcode_dpfwo_encode_fns, 0, 0 },
+ { "sdct", ICLASS_xt_iclass_sdct,
+ 0,
+ Opcode_sdct_encode_fns, 0, 0 },
+ { "ldct", ICLASS_xt_iclass_ldct,
+ 0,
+ Opcode_ldct_encode_fns, 0, 0 },
+ { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
+ 0,
+ Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
+ 0,
+ Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
+ { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
+ 0,
+ Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
+ { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
+ 0,
+ Opcode_rsr_rasid_encode_fns, 0, 0 },
+ { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
+ 0,
+ Opcode_wsr_rasid_encode_fns, 0, 0 },
+ { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
+ 0,
+ Opcode_xsr_rasid_encode_fns, 0, 0 },
+ { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
+ 0,
+ Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
+ { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
+ 0,
+ Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
+ { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
+ 0,
+ Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
+ { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
+ 0,
+ Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
+ { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
+ 0,
+ Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
+ { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
+ 0,
+ Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
+ { "idtlb", ICLASS_xt_iclass_idtlb,
+ 0,
+ Opcode_idtlb_encode_fns, 0, 0 },
+ { "pdtlb", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_pdtlb_encode_fns, 0, 0 },
+ { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb0_encode_fns, 0, 0 },
+ { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+ 0,
+ Opcode_rdtlb1_encode_fns, 0, 0 },
+ { "wdtlb", ICLASS_xt_iclass_wdtlb,
+ 0,
+ Opcode_wdtlb_encode_fns, 0, 0 },
+ { "iitlb", ICLASS_xt_iclass_iitlb,
+ 0,
+ Opcode_iitlb_encode_fns, 0, 0 },
+ { "pitlb", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_pitlb_encode_fns, 0, 0 },
+ { "ritlb0", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb0_encode_fns, 0, 0 },
+ { "ritlb1", ICLASS_xt_iclass_ritlb,
+ 0,
+ Opcode_ritlb1_encode_fns, 0, 0 },
+ { "witlb", ICLASS_xt_iclass_witlb,
+ 0,
+ Opcode_witlb_encode_fns, 0, 0 },
+ { "ldpte", ICLASS_xt_iclass_ldpte,
+ 0,
+ Opcode_ldpte_encode_fns, 0, 0 },
+ { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
+ XTENSA_OPCODE_IS_BRANCH,
+ Opcode_hwwitlba_encode_fns, 0, 0 },
+ { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
+ 0,
+ Opcode_hwwdtlba_encode_fns, 0, 0 },
+ { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
+ 0,
+ Opcode_rsr_cpenable_encode_fns, 0, 0 },
+ { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
+ 0,
+ Opcode_wsr_cpenable_encode_fns, 0, 0 },
+ { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
+ 0,
+ Opcode_xsr_cpenable_encode_fns, 0, 0 },
+ { "clamps", ICLASS_xt_iclass_clamp,
+ 0,
+ Opcode_clamps_encode_fns, 0, 0 },
+ { "min", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_min_encode_fns, 0, 0 },
+ { "max", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_max_encode_fns, 0, 0 },
+ { "minu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_minu_encode_fns, 0, 0 },
+ { "maxu", ICLASS_xt_iclass_minmax,
+ 0,
+ Opcode_maxu_encode_fns, 0, 0 },
+ { "nsa", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsa_encode_fns, 0, 0 },
+ { "nsau", ICLASS_xt_iclass_nsa,
+ 0,
+ Opcode_nsau_encode_fns, 0, 0 },
+ { "sext", ICLASS_xt_iclass_sx,
+ 0,
+ Opcode_sext_encode_fns, 0, 0 },
+ { "l32ai", ICLASS_xt_iclass_l32ai,
+ 0,
+ Opcode_l32ai_encode_fns, 0, 0 },
+ { "s32ri", ICLASS_xt_iclass_s32ri,
+ 0,
+ Opcode_s32ri_encode_fns, 0, 0 },
+ { "s32c1i", ICLASS_xt_iclass_s32c1i,
+ 0,
+ Opcode_s32c1i_encode_fns, 0, 0 },
+ { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+ 0,
+ Opcode_rsr_scompare1_encode_fns, 0, 0 },
+ { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+ 0,
+ Opcode_wsr_scompare1_encode_fns, 0, 0 },
+ { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+ 0,
+ Opcode_xsr_scompare1_encode_fns, 0, 0 },
+ { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+ 0,
+ Opcode_rsr_atomctl_encode_fns, 0, 0 },
+ { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+ 0,
+ Opcode_wsr_atomctl_encode_fns, 0, 0 },
+ { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+ 0,
+ Opcode_xsr_atomctl_encode_fns, 0, 0 },
+ { "rer", ICLASS_xt_iclass_rer,
+ 0,
+ Opcode_rer_encode_fns, 0, 0 },
+ { "wer", ICLASS_xt_iclass_wer,
+ 0,
+ Opcode_wer_encode_fns, 0, 0 },
+ { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
+ 0,
+ Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
+ { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
+ 0,
+ Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
+ { "rur.ae_bithead", ICLASS_rur_ae_bithead,
+ 0,
+ Opcode_rur_ae_bithead_encode_fns, 0, 0 },
+ { "wur.ae_bithead", ICLASS_wur_ae_bithead,
+ 0,
+ Opcode_wur_ae_bithead_encode_fns, 0, 0 },
+ { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
+ 0,
+ Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
+ { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
+ 0,
+ Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
+ { "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
+ 0,
+ Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
+ { "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
+ 0,
+ Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
+ { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
+ 0,
+ Opcode_rur_ae_overflow_encode_fns, 0, 0 },
+ { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
+ 0,
+ Opcode_wur_ae_overflow_encode_fns, 0, 0 },
+ { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
+ 0,
+ Opcode_rur_ae_sar_encode_fns, 0, 0 },
+ { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
+ 0,
+ Opcode_wur_ae_sar_encode_fns, 0, 0 },
+ { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
+ 0,
+ Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
+ { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
+ 0,
+ Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
+ { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
+ 0,
+ Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
+ { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
+ 0,
+ Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
+ { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
+ 0,
+ Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
+ { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
+ 0,
+ Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
+ { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
+ 0,
+ Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
+ { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
+ 0,
+ Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
+ { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
+ 0,
+ Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
+ { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
+ 0,
+ Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
+ { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
+ 0,
+ Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
+ { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
+ 0,
+ Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
+ { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
+ 0,
+ Opcode_ae_lp16f_i_encode_fns, 0, 0 },
+ { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
+ 0,
+ Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
+ { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
+ 0,
+ Opcode_ae_lp16f_x_encode_fns, 0, 0 },
+ { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
+ 0,
+ Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
+ { "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
+ 0,
+ Opcode_ae_lp24_i_encode_fns, 0, 0 },
+ { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
+ 0,
+ Opcode_ae_lp24_iu_encode_fns, 0, 0 },
+ { "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
+ 0,
+ Opcode_ae_lp24_x_encode_fns, 0, 0 },
+ { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
+ 0,
+ Opcode_ae_lp24_xu_encode_fns, 0, 0 },
+ { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
+ 0,
+ Opcode_ae_lp24f_i_encode_fns, 0, 0 },
+ { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
+ 0,
+ Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
+ { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
+ 0,
+ Opcode_ae_lp24f_x_encode_fns, 0, 0 },
+ { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
+ 0,
+ Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
+ { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
+ 0,
+ Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
+ { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
+ 0,
+ Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
+ { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
+ 0,
+ Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
+ { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
+ 0,
+ Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
+ { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
+ 0,
+ Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
+ { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
+ 0,
+ Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
+ { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
+ 0,
+ Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
+ { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
+ 0,
+ Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
+ { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
+ 0,
+ Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
+ { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
+ 0,
+ Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
+ { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
+ 0,
+ Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
+ { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
+ 0,
+ Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
+ { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
+ 0,
+ Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
+ { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
+ 0,
+ Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
+ { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
+ 0,
+ Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
+ { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
+ 0,
+ Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
+ { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
+ 0,
+ Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
+ { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
+ 0,
+ Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
+ { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
+ 0,
+ Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
+ { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
+ 0,
+ Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
+ { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
+ 0,
+ Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
+ { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
+ 0,
+ Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
+ { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
+ 0,
+ Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
+ { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
+ 0,
+ Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
+ { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
+ 0,
+ Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
+ { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
+ 0,
+ Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
+ { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
+ 0,
+ Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
+ { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
+ 0,
+ Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
+ { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
+ 0,
+ Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
+ { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
+ 0,
+ Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
+ { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
+ 0,
+ Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
+ { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
+ 0,
+ Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
+ { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
+ 0,
+ Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
+ { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
+ 0,
+ Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
+ { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
+ 0,
+ Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
+ { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
+ 0,
+ Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
+ { "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
+ 0,
+ Opcode_ae_lq56_i_encode_fns, 0, 0 },
+ { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
+ 0,
+ Opcode_ae_lq56_iu_encode_fns, 0, 0 },
+ { "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
+ 0,
+ Opcode_ae_lq56_x_encode_fns, 0, 0 },
+ { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
+ 0,
+ Opcode_ae_lq56_xu_encode_fns, 0, 0 },
+ { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
+ 0,
+ Opcode_ae_lq32f_i_encode_fns, 0, 0 },
+ { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
+ 0,
+ Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
+ { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
+ 0,
+ Opcode_ae_lq32f_x_encode_fns, 0, 0 },
+ { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
+ 0,
+ Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
+ { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
+ 0,
+ Opcode_ae_sq56s_i_encode_fns, 0, 0 },
+ { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
+ 0,
+ Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
+ { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
+ 0,
+ Opcode_ae_sq56s_x_encode_fns, 0, 0 },
+ { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
+ 0,
+ Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
+ { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
+ 0,
+ Opcode_ae_sq32f_i_encode_fns, 0, 0 },
+ { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
+ 0,
+ Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
+ { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
+ 0,
+ Opcode_ae_sq32f_x_encode_fns, 0, 0 },
+ { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
+ 0,
+ Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
+ { "ae_zerop48", ICLASS_ae_iclass_zerop48,
+ 0,
+ Opcode_ae_zerop48_encode_fns, 0, 0 },
+ { "ae_movp48", ICLASS_ae_iclass_movp48,
+ 0,
+ Opcode_ae_movp48_encode_fns, 0, 0 },
+ { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
+ 0,
+ Opcode_ae_selp24_ll_encode_fns, 0, 0 },
+ { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
+ 0,
+ Opcode_ae_selp24_lh_encode_fns, 0, 0 },
+ { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
+ 0,
+ Opcode_ae_selp24_hl_encode_fns, 0, 0 },
+ { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
+ 0,
+ Opcode_ae_selp24_hh_encode_fns, 0, 0 },
+ { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
+ 0,
+ Opcode_ae_movtp24x2_encode_fns, 0, 0 },
+ { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
+ 0,
+ Opcode_ae_movfp24x2_encode_fns, 0, 0 },
+ { "ae_movtp48", ICLASS_ae_iclass_movtp48,
+ 0,
+ Opcode_ae_movtp48_encode_fns, 0, 0 },
+ { "ae_movfp48", ICLASS_ae_iclass_movfp48,
+ 0,
+ Opcode_ae_movfp48_encode_fns, 0, 0 },
+ { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
+ 0,
+ Opcode_ae_movpa24x2_encode_fns, 0, 0 },
+ { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
+ 0,
+ Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
+ { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
+ 0,
+ Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
+ { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
+ 0,
+ Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
+ 0,
+ Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
+ 0,
+ Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
+ 0,
+ Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
+ { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
+ 0,
+ Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
+ { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
+ 0,
+ Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
+ { "ae_truncp16", ICLASS_ae_iclass_truncp16,
+ 0,
+ Opcode_ae_truncp16_encode_fns, 0, 0 },
+ { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
+ 0,
+ Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
+ { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
+ 0,
+ Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
+ { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
+ 0,
+ Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
+ { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
+ 0,
+ Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
+ { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
+ 0,
+ Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
+ { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
+ 0,
+ Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
+ { "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
+ 0,
+ Opcode_ae_zeroq56_encode_fns, 0, 0 },
+ { "ae_movq56", ICLASS_ae_iclass_movq56,
+ 0,
+ Opcode_ae_movq56_encode_fns, 0, 0 },
+ { "ae_movtq56", ICLASS_ae_iclass_movtq56,
+ 0,
+ Opcode_ae_movtq56_encode_fns, 0, 0 },
+ { "ae_movfq56", ICLASS_ae_iclass_movfq56,
+ 0,
+ Opcode_ae_movfq56_encode_fns, 0, 0 },
+ { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
+ 0,
+ Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
+ { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
+ 0,
+ Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
+ { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
+ 0,
+ Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
+ { "ae_satq48s", ICLASS_ae_iclass_satq48s,
+ 0,
+ Opcode_ae_satq48s_encode_fns, 0, 0 },
+ { "ae_truncq32", ICLASS_ae_iclass_truncq32,
+ 0,
+ Opcode_ae_truncq32_encode_fns, 0, 0 },
+ { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
+ 0,
+ Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
+ { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
+ 0,
+ Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
+ { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
+ 0,
+ Opcode_ae_trunca32q48_encode_fns, 0, 0 },
+ { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
+ 0,
+ Opcode_ae_movap24s_l_encode_fns, 0, 0 },
+ { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
+ 0,
+ Opcode_ae_movap24s_h_encode_fns, 0, 0 },
+ { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
+ 0,
+ Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
+ { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
+ 0,
+ Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
+ { "ae_addp24", ICLASS_ae_iclass_addp24,
+ 0,
+ Opcode_ae_addp24_encode_fns, 0, 0 },
+ { "ae_subp24", ICLASS_ae_iclass_subp24,
+ 0,
+ Opcode_ae_subp24_encode_fns, 0, 0 },
+ { "ae_negp24", ICLASS_ae_iclass_negp24,
+ 0,
+ Opcode_ae_negp24_encode_fns, 0, 0 },
+ { "ae_absp24", ICLASS_ae_iclass_absp24,
+ 0,
+ Opcode_ae_absp24_encode_fns, 0, 0 },
+ { "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
+ 0,
+ Opcode_ae_maxp24s_encode_fns, 0, 0 },
+ { "ae_minp24s", ICLASS_ae_iclass_minp24s,
+ 0,
+ Opcode_ae_minp24s_encode_fns, 0, 0 },
+ { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
+ 0,
+ Opcode_ae_maxbp24s_encode_fns, 0, 0 },
+ { "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
+ 0,
+ Opcode_ae_minbp24s_encode_fns, 0, 0 },
+ { "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
+ 0,
+ Opcode_ae_addsp24s_encode_fns, 0, 0 },
+ { "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
+ 0,
+ Opcode_ae_subsp24s_encode_fns, 0, 0 },
+ { "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
+ 0,
+ Opcode_ae_negsp24s_encode_fns, 0, 0 },
+ { "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
+ 0,
+ Opcode_ae_abssp24s_encode_fns, 0, 0 },
+ { "ae_andp48", ICLASS_ae_iclass_andp48,
+ 0,
+ Opcode_ae_andp48_encode_fns, 0, 0 },
+ { "ae_nandp48", ICLASS_ae_iclass_nandp48,
+ 0,
+ Opcode_ae_nandp48_encode_fns, 0, 0 },
+ { "ae_orp48", ICLASS_ae_iclass_orp48,
+ 0,
+ Opcode_ae_orp48_encode_fns, 0, 0 },
+ { "ae_xorp48", ICLASS_ae_iclass_xorp48,
+ 0,
+ Opcode_ae_xorp48_encode_fns, 0, 0 },
+ { "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
+ 0,
+ Opcode_ae_ltp24s_encode_fns, 0, 0 },
+ { "ae_lep24s", ICLASS_ae_iclass_lep24s,
+ 0,
+ Opcode_ae_lep24s_encode_fns, 0, 0 },
+ { "ae_eqp24", ICLASS_ae_iclass_eqp24,
+ 0,
+ Opcode_ae_eqp24_encode_fns, 0, 0 },
+ { "ae_addq56", ICLASS_ae_iclass_addq56,
+ 0,
+ Opcode_ae_addq56_encode_fns, 0, 0 },
+ { "ae_subq56", ICLASS_ae_iclass_subq56,
+ 0,
+ Opcode_ae_subq56_encode_fns, 0, 0 },
+ { "ae_negq56", ICLASS_ae_iclass_negq56,
+ 0,
+ Opcode_ae_negq56_encode_fns, 0, 0 },
+ { "ae_absq56", ICLASS_ae_iclass_absq56,
+ 0,
+ Opcode_ae_absq56_encode_fns, 0, 0 },
+ { "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
+ 0,
+ Opcode_ae_maxq56s_encode_fns, 0, 0 },
+ { "ae_minq56s", ICLASS_ae_iclass_minq56s,
+ 0,
+ Opcode_ae_minq56s_encode_fns, 0, 0 },
+ { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
+ 0,
+ Opcode_ae_maxbq56s_encode_fns, 0, 0 },
+ { "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
+ 0,
+ Opcode_ae_minbq56s_encode_fns, 0, 0 },
+ { "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
+ 0,
+ Opcode_ae_addsq56s_encode_fns, 0, 0 },
+ { "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
+ 0,
+ Opcode_ae_subsq56s_encode_fns, 0, 0 },
+ { "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
+ 0,
+ Opcode_ae_negsq56s_encode_fns, 0, 0 },
+ { "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
+ 0,
+ Opcode_ae_abssq56s_encode_fns, 0, 0 },
+ { "ae_andq56", ICLASS_ae_iclass_andq56,
+ 0,
+ Opcode_ae_andq56_encode_fns, 0, 0 },
+ { "ae_nandq56", ICLASS_ae_iclass_nandq56,
+ 0,
+ Opcode_ae_nandq56_encode_fns, 0, 0 },
+ { "ae_orq56", ICLASS_ae_iclass_orq56,
+ 0,
+ Opcode_ae_orq56_encode_fns, 0, 0 },
+ { "ae_xorq56", ICLASS_ae_iclass_xorq56,
+ 0,
+ Opcode_ae_xorq56_encode_fns, 0, 0 },
+ { "ae_sllip24", ICLASS_ae_iclass_sllip24,
+ 0,
+ Opcode_ae_sllip24_encode_fns, 0, 0 },
+ { "ae_srlip24", ICLASS_ae_iclass_srlip24,
+ 0,
+ Opcode_ae_srlip24_encode_fns, 0, 0 },
+ { "ae_sraip24", ICLASS_ae_iclass_sraip24,
+ 0,
+ Opcode_ae_sraip24_encode_fns, 0, 0 },
+ { "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
+ 0,
+ Opcode_ae_sllsp24_encode_fns, 0, 0 },
+ { "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
+ 0,
+ Opcode_ae_srlsp24_encode_fns, 0, 0 },
+ { "ae_srasp24", ICLASS_ae_iclass_srasp24,
+ 0,
+ Opcode_ae_srasp24_encode_fns, 0, 0 },
+ { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
+ 0,
+ Opcode_ae_sllisp24s_encode_fns, 0, 0 },
+ { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
+ 0,
+ Opcode_ae_sllssp24s_encode_fns, 0, 0 },
+ { "ae_slliq56", ICLASS_ae_iclass_slliq56,
+ 0,
+ Opcode_ae_slliq56_encode_fns, 0, 0 },
+ { "ae_srliq56", ICLASS_ae_iclass_srliq56,
+ 0,
+ Opcode_ae_srliq56_encode_fns, 0, 0 },
+ { "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
+ 0,
+ Opcode_ae_sraiq56_encode_fns, 0, 0 },
+ { "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
+ 0,
+ Opcode_ae_sllsq56_encode_fns, 0, 0 },
+ { "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
+ 0,
+ Opcode_ae_srlsq56_encode_fns, 0, 0 },
+ { "ae_srasq56", ICLASS_ae_iclass_srasq56,
+ 0,
+ Opcode_ae_srasq56_encode_fns, 0, 0 },
+ { "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
+ 0,
+ Opcode_ae_sllaq56_encode_fns, 0, 0 },
+ { "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
+ 0,
+ Opcode_ae_srlaq56_encode_fns, 0, 0 },
+ { "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
+ 0,
+ Opcode_ae_sraaq56_encode_fns, 0, 0 },
+ { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
+ 0,
+ Opcode_ae_sllisq56s_encode_fns, 0, 0 },
+ { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
+ 0,
+ Opcode_ae_sllssq56s_encode_fns, 0, 0 },
+ { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
+ 0,
+ Opcode_ae_sllasq56s_encode_fns, 0, 0 },
+ { "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
+ 0,
+ Opcode_ae_ltq56s_encode_fns, 0, 0 },
+ { "ae_leq56s", ICLASS_ae_iclass_leq56s,
+ 0,
+ Opcode_ae_leq56s_encode_fns, 0, 0 },
+ { "ae_eqq56", ICLASS_ae_iclass_eqq56,
+ 0,
+ Opcode_ae_eqq56_encode_fns, 0, 0 },
+ { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
+ 0,
+ Opcode_ae_nsaq56s_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
+ 0,
+ Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
+ { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
+ 0,
+ Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
+ 0,
+ Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
+ 0,
+ Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
+ { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
+ 0,
+ Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
+ 0,
+ Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
+ 0,
+ Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
+ { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
+ 0,
+ Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
+ 0,
+ Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
+ 0,
+ Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
+ { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
+ 0,
+ Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
+ 0,
+ Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
+ 0,
+ Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
+ { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
+ 0,
+ Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
+ 0,
+ Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
+ 0,
+ Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
+ { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
+ 0,
+ Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
+ 0,
+ Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
+ 0,
+ Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
+ { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
+ 0,
+ Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
+ 0,
+ Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
+ { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
+ 0,
+ Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
+ { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
+ 0,
+ Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
+ 0,
+ Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
+ 0,
+ Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
+ 0,
+ Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
+ 0,
+ Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
+ 0,
+ Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
+ 0,
+ Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
+ 0,
+ Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
+ 0,
+ Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
+ 0,
+ Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
+ 0,
+ Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
+ { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
+ 0,
+ Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
+ { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
+ 0,
+ Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
+ 0,
+ Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
+ 0,
+ Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
+ 0,
+ Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
+ 0,
+ Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
+ 0,
+ Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
+ 0,
+ Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
+ 0,
+ Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
+ 0,
+ Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
+ 0,
+ Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
+ 0,
+ Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
+ 0,
+ Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
+ 0,
+ Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
+ 0,
+ Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
+ 0,
+ Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
+ 0,
+ Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
+ { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
+ 0,
+ Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
+ 0,
+ Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
+ 0,
+ Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
+ 0,
+ Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
+ 0,
+ Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
+ 0,
+ Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
+ 0,
+ Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
+ 0,
+ Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
+ 0,
+ Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
+ 0,
+ Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
+ 0,
+ Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
+ 0,
+ Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
+ 0,
+ Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
+ 0,
+ Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
+ 0,
+ Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
+ 0,
+ Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
+ 0,
+ Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
+ 0,
+ Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
+ 0,
+ Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
+ 0,
+ Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
+ 0,
+ Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
+ 0,
+ Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
+ 0,
+ Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
+ 0,
+ Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
+ 0,
+ Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
+ { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
+ 0,
+ Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
+ 0,
+ Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
+ 0,
+ Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
+ 0,
+ Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
+ 0,
+ Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
+ 0,
+ Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
+ { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
+ 0,
+ Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
+ { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
+ 0,
+ Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
+ 0,
+ Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
+ 0,
+ Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
+ 0,
+ Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
+ 0,
+ Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
+ 0,
+ Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
+ 0,
+ Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
+ 0,
+ Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
+ 0,
+ Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
+ 0,
+ Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
+ 0,
+ Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
+ 0,
+ Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
+ 0,
+ Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
+ 0,
+ Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
+ 0,
+ Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
+ 0,
+ Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
+ { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
+ 0,
+ Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
+ 0,
+ Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
+ { "ae_sha32", ICLASS_ae_iclass_sha32,
+ 0,
+ Opcode_ae_sha32_encode_fns, 0, 0 },
+ { "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
+ 0,
+ Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
+ { "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
+ 0,
+ Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
+ { "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
+ 0,
+ Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
+ { "ae_vldsht", ICLASS_ae_iclass_vldsht,
+ 0,
+ Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
+ { "ae_lb", ICLASS_ae_iclass_lb,
+ 0,
+ Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
+ { "ae_lbi", ICLASS_ae_iclass_lbi,
+ 0,
+ Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
+ { "ae_lbk", ICLASS_ae_iclass_lbk,
+ 0,
+ Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
+ { "ae_lbki", ICLASS_ae_iclass_lbki,
+ 0,
+ Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
+ { "ae_db", ICLASS_ae_iclass_db,
+ 0,
+ Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
+ { "ae_dbi", ICLASS_ae_iclass_dbi,
+ 0,
+ Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
+ { "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
+ 0,
+ Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
+ { "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
+ 0,
+ Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
+ { "ae_sb", ICLASS_ae_iclass_sb,
+ 0,
+ Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
+ { "ae_sbi", ICLASS_ae_iclass_sbi,
+ 0,
+ Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
+ { "ae_vles16c", ICLASS_ae_iclass_vles16c,
+ 0,
+ Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
+ { "ae_sbf", ICLASS_ae_iclass_sbf,
+ 0,
+ Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }
+};
+
+enum xtensa_opcode_id {
+ OPCODE_EXCW,
+ OPCODE_RFE,
+ OPCODE_RFDE,
+ OPCODE_SYSCALL,
+ OPCODE_CALL12,
+ OPCODE_CALL8,
+ OPCODE_CALL4,
+ OPCODE_CALLX12,
+ OPCODE_CALLX8,
+ OPCODE_CALLX4,
+ OPCODE_ENTRY,
+ OPCODE_MOVSP,
+ OPCODE_ROTW,
+ OPCODE_RETW,
+ OPCODE_RETW_N,
+ OPCODE_RFWO,
+ OPCODE_RFWU,
+ OPCODE_L32E,
+ OPCODE_S32E,
+ OPCODE_RSR_WINDOWBASE,
+ OPCODE_WSR_WINDOWBASE,
+ OPCODE_XSR_WINDOWBASE,
+ OPCODE_RSR_WINDOWSTART,
+ OPCODE_WSR_WINDOWSTART,
+ OPCODE_XSR_WINDOWSTART,
+ OPCODE_ADD_N,
+ OPCODE_ADDI_N,
+ OPCODE_BEQZ_N,
+ OPCODE_BNEZ_N,
+ OPCODE_ILL_N,
+ OPCODE_L32I_N,
+ OPCODE_MOV_N,
+ OPCODE_MOVI_N,
+ OPCODE_NOP_N,
+ OPCODE_RET_N,
+ OPCODE_S32I_N,
+ OPCODE_RUR_THREADPTR,
+ OPCODE_WUR_THREADPTR,
+ OPCODE_ADDI,
+ OPCODE_ADDMI,
+ OPCODE_ADD,
+ OPCODE_SUB,
+ OPCODE_ADDX2,
+ OPCODE_ADDX4,
+ OPCODE_ADDX8,
+ OPCODE_SUBX2,
+ OPCODE_SUBX4,
+ OPCODE_SUBX8,
+ OPCODE_AND,
+ OPCODE_OR,
+ OPCODE_XOR,
+ OPCODE_BEQI,
+ OPCODE_BNEI,
+ OPCODE_BGEI,
+ OPCODE_BLTI,
+ OPCODE_BBCI,
+ OPCODE_BBSI,
+ OPCODE_BGEUI,
+ OPCODE_BLTUI,
+ OPCODE_BEQ,
+ OPCODE_BNE,
+ OPCODE_BGE,
+ OPCODE_BLT,
+ OPCODE_BGEU,
+ OPCODE_BLTU,
+ OPCODE_BANY,
+ OPCODE_BNONE,
+ OPCODE_BALL,
+ OPCODE_BNALL,
+ OPCODE_BBC,
+ OPCODE_BBS,
+ OPCODE_BEQZ,
+ OPCODE_BNEZ,
+ OPCODE_BGEZ,
+ OPCODE_BLTZ,
+ OPCODE_CALL0,
+ OPCODE_CALLX0,
+ OPCODE_EXTUI,
+ OPCODE_ILL,
+ OPCODE_J,
+ OPCODE_JX,
+ OPCODE_L16UI,
+ OPCODE_L16SI,
+ OPCODE_L32I,
+ OPCODE_L32R,
+ OPCODE_L8UI,
+ OPCODE_LOOP,
+ OPCODE_LOOPNEZ,
+ OPCODE_LOOPGTZ,
+ OPCODE_MOVI,
+ OPCODE_MOVEQZ,
+ OPCODE_MOVNEZ,
+ OPCODE_MOVLTZ,
+ OPCODE_MOVGEZ,
+ OPCODE_NEG,
+ OPCODE_ABS,
+ OPCODE_NOP,
+ OPCODE_RET,
+ OPCODE_SIMCALL,
+ OPCODE_S16I,
+ OPCODE_S32I,
+ OPCODE_S8I,
+ OPCODE_SSR,
+ OPCODE_SSL,
+ OPCODE_SSA8L,
+ OPCODE_SSA8B,
+ OPCODE_SSAI,
+ OPCODE_SLL,
+ OPCODE_SRC,
+ OPCODE_SRL,
+ OPCODE_SRA,
+ OPCODE_SLLI,
+ OPCODE_SRAI,
+ OPCODE_SRLI,
+ OPCODE_MEMW,
+ OPCODE_EXTW,
+ OPCODE_ISYNC,
+ OPCODE_RSYNC,
+ OPCODE_ESYNC,
+ OPCODE_DSYNC,
+ OPCODE_RSIL,
+ OPCODE_RSR_LEND,
+ OPCODE_WSR_LEND,
+ OPCODE_XSR_LEND,
+ OPCODE_RSR_LCOUNT,
+ OPCODE_WSR_LCOUNT,
+ OPCODE_XSR_LCOUNT,
+ OPCODE_RSR_LBEG,
+ OPCODE_WSR_LBEG,
+ OPCODE_XSR_LBEG,
+ OPCODE_RSR_SAR,
+ OPCODE_WSR_SAR,
+ OPCODE_XSR_SAR,
+ OPCODE_RSR_LITBASE,
+ OPCODE_WSR_LITBASE,
+ OPCODE_XSR_LITBASE,
+ OPCODE_RSR_CONFIGID0,
+ OPCODE_WSR_CONFIGID0,
+ OPCODE_RSR_CONFIGID1,
+ OPCODE_RSR_PS,
+ OPCODE_WSR_PS,
+ OPCODE_XSR_PS,
+ OPCODE_RSR_EPC1,
+ OPCODE_WSR_EPC1,
+ OPCODE_XSR_EPC1,
+ OPCODE_RSR_EXCSAVE1,
+ OPCODE_WSR_EXCSAVE1,
+ OPCODE_XSR_EXCSAVE1,
+ OPCODE_RSR_EPC2,
+ OPCODE_WSR_EPC2,
+ OPCODE_XSR_EPC2,
+ OPCODE_RSR_EXCSAVE2,
+ OPCODE_WSR_EXCSAVE2,
+ OPCODE_XSR_EXCSAVE2,
+ OPCODE_RSR_EPS2,
+ OPCODE_WSR_EPS2,
+ OPCODE_XSR_EPS2,
+ OPCODE_RSR_EXCVADDR,
+ OPCODE_WSR_EXCVADDR,
+ OPCODE_XSR_EXCVADDR,
+ OPCODE_RSR_DEPC,
+ OPCODE_WSR_DEPC,
+ OPCODE_XSR_DEPC,
+ OPCODE_RSR_EXCCAUSE,
+ OPCODE_WSR_EXCCAUSE,
+ OPCODE_XSR_EXCCAUSE,
+ OPCODE_RSR_MISC0,
+ OPCODE_WSR_MISC0,
+ OPCODE_XSR_MISC0,
+ OPCODE_RSR_MISC1,
+ OPCODE_WSR_MISC1,
+ OPCODE_XSR_MISC1,
+ OPCODE_RSR_PRID,
+ OPCODE_RSR_VECBASE,
+ OPCODE_WSR_VECBASE,
+ OPCODE_XSR_VECBASE,
+ OPCODE_MUL16U,
+ OPCODE_MUL16S,
+ OPCODE_MULL,
+ OPCODE_RFI,
+ OPCODE_WAITI,
+ OPCODE_RSR_INTERRUPT,
+ OPCODE_WSR_INTSET,
+ OPCODE_WSR_INTCLEAR,
+ OPCODE_RSR_INTENABLE,
+ OPCODE_WSR_INTENABLE,
+ OPCODE_XSR_INTENABLE,
+ OPCODE_BREAK,
+ OPCODE_BREAK_N,
+ OPCODE_RSR_DEBUGCAUSE,
+ OPCODE_WSR_DEBUGCAUSE,
+ OPCODE_XSR_DEBUGCAUSE,
+ OPCODE_RSR_ICOUNT,
+ OPCODE_WSR_ICOUNT,
+ OPCODE_XSR_ICOUNT,
+ OPCODE_RSR_ICOUNTLEVEL,
+ OPCODE_WSR_ICOUNTLEVEL,
+ OPCODE_XSR_ICOUNTLEVEL,
+ OPCODE_RSR_DDR,
+ OPCODE_WSR_DDR,
+ OPCODE_XSR_DDR,
+ OPCODE_RFDO,
+ OPCODE_RFDD,
+ OPCODE_ANDB,
+ OPCODE_ANDBC,
+ OPCODE_ORB,
+ OPCODE_ORBC,
+ OPCODE_XORB,
+ OPCODE_ANY4,
+ OPCODE_ALL4,
+ OPCODE_ANY8,
+ OPCODE_ALL8,
+ OPCODE_BF,
+ OPCODE_BT,
+ OPCODE_MOVF,
+ OPCODE_MOVT,
+ OPCODE_RSR_BR,
+ OPCODE_WSR_BR,
+ OPCODE_XSR_BR,
+ OPCODE_RSR_CCOUNT,
+ OPCODE_WSR_CCOUNT,
+ OPCODE_XSR_CCOUNT,
+ OPCODE_RSR_CCOMPARE0,
+ OPCODE_WSR_CCOMPARE0,
+ OPCODE_XSR_CCOMPARE0,
+ OPCODE_RSR_CCOMPARE1,
+ OPCODE_WSR_CCOMPARE1,
+ OPCODE_XSR_CCOMPARE1,
+ OPCODE_IPF,
+ OPCODE_IHI,
+ OPCODE_III,
+ OPCODE_LICT,
+ OPCODE_LICW,
+ OPCODE_SICT,
+ OPCODE_SICW,
+ OPCODE_DHWB,
+ OPCODE_DHWBI,
+ OPCODE_DIWB,
+ OPCODE_DIWBI,
+ OPCODE_DHI,
+ OPCODE_DII,
+ OPCODE_DPFR,
+ OPCODE_DPFW,
+ OPCODE_DPFRO,
+ OPCODE_DPFWO,
+ OPCODE_SDCT,
+ OPCODE_LDCT,
+ OPCODE_WSR_PTEVADDR,
+ OPCODE_RSR_PTEVADDR,
+ OPCODE_XSR_PTEVADDR,
+ OPCODE_RSR_RASID,
+ OPCODE_WSR_RASID,
+ OPCODE_XSR_RASID,
+ OPCODE_RSR_ITLBCFG,
+ OPCODE_WSR_ITLBCFG,
+ OPCODE_XSR_ITLBCFG,
+ OPCODE_RSR_DTLBCFG,
+ OPCODE_WSR_DTLBCFG,
+ OPCODE_XSR_DTLBCFG,
+ OPCODE_IDTLB,
+ OPCODE_PDTLB,
+ OPCODE_RDTLB0,
+ OPCODE_RDTLB1,
+ OPCODE_WDTLB,
+ OPCODE_IITLB,
+ OPCODE_PITLB,
+ OPCODE_RITLB0,
+ OPCODE_RITLB1,
+ OPCODE_WITLB,
+ OPCODE_LDPTE,
+ OPCODE_HWWITLBA,
+ OPCODE_HWWDTLBA,
+ OPCODE_RSR_CPENABLE,
+ OPCODE_WSR_CPENABLE,
+ OPCODE_XSR_CPENABLE,
+ OPCODE_CLAMPS,
+ OPCODE_MIN,
+ OPCODE_MAX,
+ OPCODE_MINU,
+ OPCODE_MAXU,
+ OPCODE_NSA,
+ OPCODE_NSAU,
+ OPCODE_SEXT,
+ OPCODE_L32AI,
+ OPCODE_S32RI,
+ OPCODE_S32C1I,
+ OPCODE_RSR_SCOMPARE1,
+ OPCODE_WSR_SCOMPARE1,
+ OPCODE_XSR_SCOMPARE1,
+ OPCODE_RSR_ATOMCTL,
+ OPCODE_WSR_ATOMCTL,
+ OPCODE_XSR_ATOMCTL,
+ OPCODE_RER,
+ OPCODE_WER,
+ OPCODE_RUR_AE_OVF_SAR,
+ OPCODE_WUR_AE_OVF_SAR,
+ OPCODE_RUR_AE_BITHEAD,
+ OPCODE_WUR_AE_BITHEAD,
+ OPCODE_RUR_AE_TS_FTS_BU_BP,
+ OPCODE_WUR_AE_TS_FTS_BU_BP,
+ OPCODE_RUR_AE_SD_NO,
+ OPCODE_WUR_AE_SD_NO,
+ OPCODE_RUR_AE_OVERFLOW,
+ OPCODE_WUR_AE_OVERFLOW,
+ OPCODE_RUR_AE_SAR,
+ OPCODE_WUR_AE_SAR,
+ OPCODE_RUR_AE_BITPTR,
+ OPCODE_WUR_AE_BITPTR,
+ OPCODE_RUR_AE_BITSUSED,
+ OPCODE_WUR_AE_BITSUSED,
+ OPCODE_RUR_AE_TABLESIZE,
+ OPCODE_WUR_AE_TABLESIZE,
+ OPCODE_RUR_AE_FIRST_TS,
+ OPCODE_WUR_AE_FIRST_TS,
+ OPCODE_RUR_AE_NEXTOFFSET,
+ OPCODE_WUR_AE_NEXTOFFSET,
+ OPCODE_RUR_AE_SEARCHDONE,
+ OPCODE_WUR_AE_SEARCHDONE,
+ OPCODE_AE_LP16F_I,
+ OPCODE_AE_LP16F_IU,
+ OPCODE_AE_LP16F_X,
+ OPCODE_AE_LP16F_XU,
+ OPCODE_AE_LP24_I,
+ OPCODE_AE_LP24_IU,
+ OPCODE_AE_LP24_X,
+ OPCODE_AE_LP24_XU,
+ OPCODE_AE_LP24F_I,
+ OPCODE_AE_LP24F_IU,
+ OPCODE_AE_LP24F_X,
+ OPCODE_AE_LP24F_XU,
+ OPCODE_AE_LP16X2F_I,
+ OPCODE_AE_LP16X2F_IU,
+ OPCODE_AE_LP16X2F_X,
+ OPCODE_AE_LP16X2F_XU,
+ OPCODE_AE_LP24X2F_I,
+ OPCODE_AE_LP24X2F_IU,
+ OPCODE_AE_LP24X2F_X,
+ OPCODE_AE_LP24X2F_XU,
+ OPCODE_AE_LP24X2_I,
+ OPCODE_AE_LP24X2_IU,
+ OPCODE_AE_LP24X2_X,
+ OPCODE_AE_LP24X2_XU,
+ OPCODE_AE_SP16X2F_I,
+ OPCODE_AE_SP16X2F_IU,
+ OPCODE_AE_SP16X2F_X,
+ OPCODE_AE_SP16X2F_XU,
+ OPCODE_AE_SP24X2S_I,
+ OPCODE_AE_SP24X2S_IU,
+ OPCODE_AE_SP24X2S_X,
+ OPCODE_AE_SP24X2S_XU,
+ OPCODE_AE_SP24X2F_I,
+ OPCODE_AE_SP24X2F_IU,
+ OPCODE_AE_SP24X2F_X,
+ OPCODE_AE_SP24X2F_XU,
+ OPCODE_AE_SP16F_L_I,
+ OPCODE_AE_SP16F_L_IU,
+ OPCODE_AE_SP16F_L_X,
+ OPCODE_AE_SP16F_L_XU,
+ OPCODE_AE_SP24S_L_I,
+ OPCODE_AE_SP24S_L_IU,
+ OPCODE_AE_SP24S_L_X,
+ OPCODE_AE_SP24S_L_XU,
+ OPCODE_AE_SP24F_L_I,
+ OPCODE_AE_SP24F_L_IU,
+ OPCODE_AE_SP24F_L_X,
+ OPCODE_AE_SP24F_L_XU,
+ OPCODE_AE_LQ56_I,
+ OPCODE_AE_LQ56_IU,
+ OPCODE_AE_LQ56_X,
+ OPCODE_AE_LQ56_XU,
+ OPCODE_AE_LQ32F_I,
+ OPCODE_AE_LQ32F_IU,
+ OPCODE_AE_LQ32F_X,
+ OPCODE_AE_LQ32F_XU,
+ OPCODE_AE_SQ56S_I,
+ OPCODE_AE_SQ56S_IU,
+ OPCODE_AE_SQ56S_X,
+ OPCODE_AE_SQ56S_XU,
+ OPCODE_AE_SQ32F_I,
+ OPCODE_AE_SQ32F_IU,
+ OPCODE_AE_SQ32F_X,
+ OPCODE_AE_SQ32F_XU,
+ OPCODE_AE_ZEROP48,
+ OPCODE_AE_MOVP48,
+ OPCODE_AE_SELP24_LL,
+ OPCODE_AE_SELP24_LH,
+ OPCODE_AE_SELP24_HL,
+ OPCODE_AE_SELP24_HH,
+ OPCODE_AE_MOVTP24X2,
+ OPCODE_AE_MOVFP24X2,
+ OPCODE_AE_MOVTP48,
+ OPCODE_AE_MOVFP48,
+ OPCODE_AE_MOVPA24X2,
+ OPCODE_AE_TRUNCP24A32X2,
+ OPCODE_AE_CVTA32P24_L,
+ OPCODE_AE_CVTA32P24_H,
+ OPCODE_AE_CVTP24A16X2_LL,
+ OPCODE_AE_CVTP24A16X2_LH,
+ OPCODE_AE_CVTP24A16X2_HL,
+ OPCODE_AE_CVTP24A16X2_HH,
+ OPCODE_AE_TRUNCP24Q48X2,
+ OPCODE_AE_TRUNCP16,
+ OPCODE_AE_ROUNDSP24Q48SYM,
+ OPCODE_AE_ROUNDSP24Q48ASYM,
+ OPCODE_AE_ROUNDSP16Q48SYM,
+ OPCODE_AE_ROUNDSP16Q48ASYM,
+ OPCODE_AE_ROUNDSP16SYM,
+ OPCODE_AE_ROUNDSP16ASYM,
+ OPCODE_AE_ZEROQ56,
+ OPCODE_AE_MOVQ56,
+ OPCODE_AE_MOVTQ56,
+ OPCODE_AE_MOVFQ56,
+ OPCODE_AE_CVTQ48A32S,
+ OPCODE_AE_CVTQ48P24S_L,
+ OPCODE_AE_CVTQ48P24S_H,
+ OPCODE_AE_SATQ48S,
+ OPCODE_AE_TRUNCQ32,
+ OPCODE_AE_ROUNDSQ32SYM,
+ OPCODE_AE_ROUNDSQ32ASYM,
+ OPCODE_AE_TRUNCA32Q48,
+ OPCODE_AE_MOVAP24S_L,
+ OPCODE_AE_MOVAP24S_H,
+ OPCODE_AE_TRUNCA16P24S_L,
+ OPCODE_AE_TRUNCA16P24S_H,
+ OPCODE_AE_ADDP24,
+ OPCODE_AE_SUBP24,
+ OPCODE_AE_NEGP24,
+ OPCODE_AE_ABSP24,
+ OPCODE_AE_MAXP24S,
+ OPCODE_AE_MINP24S,
+ OPCODE_AE_MAXBP24S,
+ OPCODE_AE_MINBP24S,
+ OPCODE_AE_ADDSP24S,
+ OPCODE_AE_SUBSP24S,
+ OPCODE_AE_NEGSP24S,
+ OPCODE_AE_ABSSP24S,
+ OPCODE_AE_ANDP48,
+ OPCODE_AE_NANDP48,
+ OPCODE_AE_ORP48,
+ OPCODE_AE_XORP48,
+ OPCODE_AE_LTP24S,
+ OPCODE_AE_LEP24S,
+ OPCODE_AE_EQP24,
+ OPCODE_AE_ADDQ56,
+ OPCODE_AE_SUBQ56,
+ OPCODE_AE_NEGQ56,
+ OPCODE_AE_ABSQ56,
+ OPCODE_AE_MAXQ56S,
+ OPCODE_AE_MINQ56S,
+ OPCODE_AE_MAXBQ56S,
+ OPCODE_AE_MINBQ56S,
+ OPCODE_AE_ADDSQ56S,
+ OPCODE_AE_SUBSQ56S,
+ OPCODE_AE_NEGSQ56S,
+ OPCODE_AE_ABSSQ56S,
+ OPCODE_AE_ANDQ56,
+ OPCODE_AE_NANDQ56,
+ OPCODE_AE_ORQ56,
+ OPCODE_AE_XORQ56,
+ OPCODE_AE_SLLIP24,
+ OPCODE_AE_SRLIP24,
+ OPCODE_AE_SRAIP24,
+ OPCODE_AE_SLLSP24,
+ OPCODE_AE_SRLSP24,
+ OPCODE_AE_SRASP24,
+ OPCODE_AE_SLLISP24S,
+ OPCODE_AE_SLLSSP24S,
+ OPCODE_AE_SLLIQ56,
+ OPCODE_AE_SRLIQ56,
+ OPCODE_AE_SRAIQ56,
+ OPCODE_AE_SLLSQ56,
+ OPCODE_AE_SRLSQ56,
+ OPCODE_AE_SRASQ56,
+ OPCODE_AE_SLLAQ56,
+ OPCODE_AE_SRLAQ56,
+ OPCODE_AE_SRAAQ56,
+ OPCODE_AE_SLLISQ56S,
+ OPCODE_AE_SLLSSQ56S,
+ OPCODE_AE_SLLASQ56S,
+ OPCODE_AE_LTQ56S,
+ OPCODE_AE_LEQ56S,
+ OPCODE_AE_EQQ56,
+ OPCODE_AE_NSAQ56S,
+ OPCODE_AE_MULFS32P16S_LL,
+ OPCODE_AE_MULFP24S_LL,
+ OPCODE_AE_MULP24S_LL,
+ OPCODE_AE_MULFS32P16S_LH,
+ OPCODE_AE_MULFP24S_LH,
+ OPCODE_AE_MULP24S_LH,
+ OPCODE_AE_MULFS32P16S_HL,
+ OPCODE_AE_MULFP24S_HL,
+ OPCODE_AE_MULP24S_HL,
+ OPCODE_AE_MULFS32P16S_HH,
+ OPCODE_AE_MULFP24S_HH,
+ OPCODE_AE_MULP24S_HH,
+ OPCODE_AE_MULAFS32P16S_LL,
+ OPCODE_AE_MULAFP24S_LL,
+ OPCODE_AE_MULAP24S_LL,
+ OPCODE_AE_MULAFS32P16S_LH,
+ OPCODE_AE_MULAFP24S_LH,
+ OPCODE_AE_MULAP24S_LH,
+ OPCODE_AE_MULAFS32P16S_HL,
+ OPCODE_AE_MULAFP24S_HL,
+ OPCODE_AE_MULAP24S_HL,
+ OPCODE_AE_MULAFS32P16S_HH,
+ OPCODE_AE_MULAFP24S_HH,
+ OPCODE_AE_MULAP24S_HH,
+ OPCODE_AE_MULSFS32P16S_LL,
+ OPCODE_AE_MULSFP24S_LL,
+ OPCODE_AE_MULSP24S_LL,
+ OPCODE_AE_MULSFS32P16S_LH,
+ OPCODE_AE_MULSFP24S_LH,
+ OPCODE_AE_MULSP24S_LH,
+ OPCODE_AE_MULSFS32P16S_HL,
+ OPCODE_AE_MULSFP24S_HL,
+ OPCODE_AE_MULSP24S_HL,
+ OPCODE_AE_MULSFS32P16S_HH,
+ OPCODE_AE_MULSFP24S_HH,
+ OPCODE_AE_MULSP24S_HH,
+ OPCODE_AE_MULAFS56P24S_LL,
+ OPCODE_AE_MULAS56P24S_LL,
+ OPCODE_AE_MULAFS56P24S_LH,
+ OPCODE_AE_MULAS56P24S_LH,
+ OPCODE_AE_MULAFS56P24S_HL,
+ OPCODE_AE_MULAS56P24S_HL,
+ OPCODE_AE_MULAFS56P24S_HH,
+ OPCODE_AE_MULAS56P24S_HH,
+ OPCODE_AE_MULSFS56P24S_LL,
+ OPCODE_AE_MULSS56P24S_LL,
+ OPCODE_AE_MULSFS56P24S_LH,
+ OPCODE_AE_MULSS56P24S_LH,
+ OPCODE_AE_MULSFS56P24S_HL,
+ OPCODE_AE_MULSS56P24S_HL,
+ OPCODE_AE_MULSFS56P24S_HH,
+ OPCODE_AE_MULSS56P24S_HH,
+ OPCODE_AE_MULFQ32SP16S_L,
+ OPCODE_AE_MULFQ32SP16S_H,
+ OPCODE_AE_MULFQ32SP16U_L,
+ OPCODE_AE_MULFQ32SP16U_H,
+ OPCODE_AE_MULQ32SP16S_L,
+ OPCODE_AE_MULQ32SP16S_H,
+ OPCODE_AE_MULQ32SP16U_L,
+ OPCODE_AE_MULQ32SP16U_H,
+ OPCODE_AE_MULAFQ32SP16S_L,
+ OPCODE_AE_MULAFQ32SP16S_H,
+ OPCODE_AE_MULAFQ32SP16U_L,
+ OPCODE_AE_MULAFQ32SP16U_H,
+ OPCODE_AE_MULAQ32SP16S_L,
+ OPCODE_AE_MULAQ32SP16S_H,
+ OPCODE_AE_MULAQ32SP16U_L,
+ OPCODE_AE_MULAQ32SP16U_H,
+ OPCODE_AE_MULSFQ32SP16S_L,
+ OPCODE_AE_MULSFQ32SP16S_H,
+ OPCODE_AE_MULSFQ32SP16U_L,
+ OPCODE_AE_MULSFQ32SP16U_H,
+ OPCODE_AE_MULSQ32SP16S_L,
+ OPCODE_AE_MULSQ32SP16S_H,
+ OPCODE_AE_MULSQ32SP16U_L,
+ OPCODE_AE_MULSQ32SP16U_H,
+ OPCODE_AE_MULZAAQ32SP16S_LL,
+ OPCODE_AE_MULZAAFQ32SP16S_LL,
+ OPCODE_AE_MULZAAQ32SP16U_LL,
+ OPCODE_AE_MULZAAFQ32SP16U_LL,
+ OPCODE_AE_MULZAAQ32SP16S_HH,
+ OPCODE_AE_MULZAAFQ32SP16S_HH,
+ OPCODE_AE_MULZAAQ32SP16U_HH,
+ OPCODE_AE_MULZAAFQ32SP16U_HH,
+ OPCODE_AE_MULZAAQ32SP16S_LH,
+ OPCODE_AE_MULZAAFQ32SP16S_LH,
+ OPCODE_AE_MULZAAQ32SP16U_LH,
+ OPCODE_AE_MULZAAFQ32SP16U_LH,
+ OPCODE_AE_MULZASQ32SP16S_LL,
+ OPCODE_AE_MULZASFQ32SP16S_LL,
+ OPCODE_AE_MULZASQ32SP16U_LL,
+ OPCODE_AE_MULZASFQ32SP16U_LL,
+ OPCODE_AE_MULZASQ32SP16S_HH,
+ OPCODE_AE_MULZASFQ32SP16S_HH,
+ OPCODE_AE_MULZASQ32SP16U_HH,
+ OPCODE_AE_MULZASFQ32SP16U_HH,
+ OPCODE_AE_MULZASQ32SP16S_LH,
+ OPCODE_AE_MULZASFQ32SP16S_LH,
+ OPCODE_AE_MULZASQ32SP16U_LH,
+ OPCODE_AE_MULZASFQ32SP16U_LH,
+ OPCODE_AE_MULZSAQ32SP16S_LL,
+ OPCODE_AE_MULZSAFQ32SP16S_LL,
+ OPCODE_AE_MULZSAQ32SP16U_LL,
+ OPCODE_AE_MULZSAFQ32SP16U_LL,
+ OPCODE_AE_MULZSAQ32SP16S_HH,
+ OPCODE_AE_MULZSAFQ32SP16S_HH,
+ OPCODE_AE_MULZSAQ32SP16U_HH,
+ OPCODE_AE_MULZSAFQ32SP16U_HH,
+ OPCODE_AE_MULZSAQ32SP16S_LH,
+ OPCODE_AE_MULZSAFQ32SP16S_LH,
+ OPCODE_AE_MULZSAQ32SP16U_LH,
+ OPCODE_AE_MULZSAFQ32SP16U_LH,
+ OPCODE_AE_MULZSSQ32SP16S_LL,
+ OPCODE_AE_MULZSSFQ32SP16S_LL,
+ OPCODE_AE_MULZSSQ32SP16U_LL,
+ OPCODE_AE_MULZSSFQ32SP16U_LL,
+ OPCODE_AE_MULZSSQ32SP16S_HH,
+ OPCODE_AE_MULZSSFQ32SP16S_HH,
+ OPCODE_AE_MULZSSQ32SP16U_HH,
+ OPCODE_AE_MULZSSFQ32SP16U_HH,
+ OPCODE_AE_MULZSSQ32SP16S_LH,
+ OPCODE_AE_MULZSSFQ32SP16S_LH,
+ OPCODE_AE_MULZSSQ32SP16U_LH,
+ OPCODE_AE_MULZSSFQ32SP16U_LH,
+ OPCODE_AE_MULZAAFP24S_HH_LL,
+ OPCODE_AE_MULZAAP24S_HH_LL,
+ OPCODE_AE_MULZAAFP24S_HL_LH,
+ OPCODE_AE_MULZAAP24S_HL_LH,
+ OPCODE_AE_MULZASFP24S_HH_LL,
+ OPCODE_AE_MULZASP24S_HH_LL,
+ OPCODE_AE_MULZASFP24S_HL_LH,
+ OPCODE_AE_MULZASP24S_HL_LH,
+ OPCODE_AE_MULZSAFP24S_HH_LL,
+ OPCODE_AE_MULZSAP24S_HH_LL,
+ OPCODE_AE_MULZSAFP24S_HL_LH,
+ OPCODE_AE_MULZSAP24S_HL_LH,
+ OPCODE_AE_MULZSSFP24S_HH_LL,
+ OPCODE_AE_MULZSSP24S_HH_LL,
+ OPCODE_AE_MULZSSFP24S_HL_LH,
+ OPCODE_AE_MULZSSP24S_HL_LH,
+ OPCODE_AE_MULAAFP24S_HH_LL,
+ OPCODE_AE_MULAAP24S_HH_LL,
+ OPCODE_AE_MULAAFP24S_HL_LH,
+ OPCODE_AE_MULAAP24S_HL_LH,
+ OPCODE_AE_MULASFP24S_HH_LL,
+ OPCODE_AE_MULASP24S_HH_LL,
+ OPCODE_AE_MULASFP24S_HL_LH,
+ OPCODE_AE_MULASP24S_HL_LH,
+ OPCODE_AE_MULSAFP24S_HH_LL,
+ OPCODE_AE_MULSAP24S_HH_LL,
+ OPCODE_AE_MULSAFP24S_HL_LH,
+ OPCODE_AE_MULSAP24S_HL_LH,
+ OPCODE_AE_MULSSFP24S_HH_LL,
+ OPCODE_AE_MULSSP24S_HH_LL,
+ OPCODE_AE_MULSSFP24S_HL_LH,
+ OPCODE_AE_MULSSP24S_HL_LH,
+ OPCODE_AE_SHA32,
+ OPCODE_AE_VLDL32T,
+ OPCODE_AE_VLDL16T,
+ OPCODE_AE_VLDL16C,
+ OPCODE_AE_VLDSHT,
+ OPCODE_AE_LB,
+ OPCODE_AE_LBI,
+ OPCODE_AE_LBK,
+ OPCODE_AE_LBKI,
+ OPCODE_AE_DB,
+ OPCODE_AE_DBI,
+ OPCODE_AE_VLEL32T,
+ OPCODE_AE_VLEL16T,
+ OPCODE_AE_SB,
+ OPCODE_AE_SBI,
+ OPCODE_AE_VLES16C,
+ OPCODE_AE_SBF
+};
+
+\f
+/* Slot-specific opcode decode functions. */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 0)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_ILL;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_RET;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_RETW;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_JX;
+ }
+ if (Field_m_Slot_inst_get (insn) == 3)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALLX0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALLX4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALLX8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALLX12;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_MOVSP;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_ISYNC;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RSYNC;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_ESYNC;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DSYNC;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ return OPCODE_EXCW;
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_MEMW;
+ if (Field_t_Slot_inst_get (insn) == 13)
+ return OPCODE_EXTW;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_NOP;
+ }
+ }
+ if (Field_r_Slot_inst_get (insn) == 3)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_RFE;
+ if (Field_s_Slot_inst_get (insn) == 2)
+ return OPCODE_RFDE;
+ if (Field_s_Slot_inst_get (insn) == 4)
+ return OPCODE_RFWO;
+ if (Field_s_Slot_inst_get (insn) == 5)
+ return OPCODE_RFWU;
+ }
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFI;
+ }
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BREAK;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SYSCALL;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SIMCALL;
+ }
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RSIL;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_WAITI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_ANY4;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_ALL4;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_ANY8;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_ALL8;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_OR;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_XOR;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_thi3_Slot_inst_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_RER;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_WER;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_ROTW;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_NSA;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_NSAU;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ {
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_HWWITLBA;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_RITLB0;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IITLB;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_PITLB;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_WITLB;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ return OPCODE_RITLB1;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_HWWDTLBA;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_RDTLB0;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_IDTLB;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_PDTLB;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_WDTLB;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_RDTLB1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_NEG;
+ if (Field_s_Slot_inst_get (insn) == 1)
+ return OPCODE_ABS;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_ADD;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_ADDX2;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_ADDX4;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_ADDX8;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_SUB;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_SUBX2;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_SUBX4;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_SUBX8;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 1)
+ {
+ if ((Field_op2_Slot_inst_get (insn) == 0 ||
+ Field_op2_Slot_inst_get (insn) == 1))
+ return OPCODE_SLLI;
+ if ((Field_op2_Slot_inst_get (insn) == 2 ||
+ Field_op2_Slot_inst_get (insn) == 3))
+ return OPCODE_SRAI;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_SRLI;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_XSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_XSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_XSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_XSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 4)
+ return OPCODE_XSR_BR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_XSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_XSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_XSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_XSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 83)
+ return OPCODE_XSR_PTEVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 90)
+ return OPCODE_XSR_RASID;
+ if (Field_sr_Slot_inst_get (insn) == 91)
+ return OPCODE_XSR_ITLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 92)
+ return OPCODE_XSR_DTLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_XSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_XSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_XSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_XSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_XSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_XSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_XSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_XSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 224)
+ return OPCODE_XSR_CPENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_XSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_XSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_XSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_XSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_XSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_XSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_XSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_XSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_XSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_XSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_XSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_XSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_XSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_SRC;
+ if (Field_op2_Slot_inst_get (insn) == 9 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRL;
+ if (Field_op2_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_SLL;
+ if (Field_op2_Slot_inst_get (insn) == 11 &&
+ Field_s_Slot_inst_get (insn) == 0)
+ return OPCODE_SRA;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MUL16U;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MUL16S;
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_LICT;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_SICT;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_LICW;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_SICW;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LDCT;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_SDCT;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_RFDO;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_RFDD;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_LDPTE;
+ }
+ }
+ if (Field_op1_Slot_inst_get (insn) == 2)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_ANDB;
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ return OPCODE_ANDBC;
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_ORB;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_ORBC;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_XORB;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MULL;
+ }
+ if (Field_op1_Slot_inst_get (insn) == 3)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_RSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_RSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_RSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_RSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 4)
+ return OPCODE_RSR_BR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_RSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_RSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_RSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_RSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 83)
+ return OPCODE_RSR_PTEVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 90)
+ return OPCODE_RSR_RASID;
+ if (Field_sr_Slot_inst_get (insn) == 91)
+ return OPCODE_RSR_ITLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 92)
+ return OPCODE_RSR_DTLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_RSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_RSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_RSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_RSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_RSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_RSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_RSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 208)
+ return OPCODE_RSR_CONFIGID1;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_RSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_RSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 224)
+ return OPCODE_RSR_CPENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_RSR_INTERRUPT;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_RSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_RSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_RSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_RSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_RSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_RSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 235)
+ return OPCODE_RSR_PRID;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_RSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_RSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_RSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_RSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_RSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_RSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_RSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 1)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 0)
+ return OPCODE_WSR_LBEG;
+ if (Field_sr_Slot_inst_get (insn) == 1)
+ return OPCODE_WSR_LEND;
+ if (Field_sr_Slot_inst_get (insn) == 2)
+ return OPCODE_WSR_LCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 3)
+ return OPCODE_WSR_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 4)
+ return OPCODE_WSR_BR;
+ if (Field_sr_Slot_inst_get (insn) == 5)
+ return OPCODE_WSR_LITBASE;
+ if (Field_sr_Slot_inst_get (insn) == 12)
+ return OPCODE_WSR_SCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 72)
+ return OPCODE_WSR_WINDOWBASE;
+ if (Field_sr_Slot_inst_get (insn) == 73)
+ return OPCODE_WSR_WINDOWSTART;
+ if (Field_sr_Slot_inst_get (insn) == 83)
+ return OPCODE_WSR_PTEVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 90)
+ return OPCODE_WSR_RASID;
+ if (Field_sr_Slot_inst_get (insn) == 91)
+ return OPCODE_WSR_ITLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 92)
+ return OPCODE_WSR_DTLBCFG;
+ if (Field_sr_Slot_inst_get (insn) == 99)
+ return OPCODE_WSR_ATOMCTL;
+ if (Field_sr_Slot_inst_get (insn) == 104)
+ return OPCODE_WSR_DDR;
+ if (Field_sr_Slot_inst_get (insn) == 176)
+ return OPCODE_WSR_CONFIGID0;
+ if (Field_sr_Slot_inst_get (insn) == 177)
+ return OPCODE_WSR_EPC1;
+ if (Field_sr_Slot_inst_get (insn) == 178)
+ return OPCODE_WSR_EPC2;
+ if (Field_sr_Slot_inst_get (insn) == 192)
+ return OPCODE_WSR_DEPC;
+ if (Field_sr_Slot_inst_get (insn) == 194)
+ return OPCODE_WSR_EPS2;
+ if (Field_sr_Slot_inst_get (insn) == 209)
+ return OPCODE_WSR_EXCSAVE1;
+ if (Field_sr_Slot_inst_get (insn) == 210)
+ return OPCODE_WSR_EXCSAVE2;
+ if (Field_sr_Slot_inst_get (insn) == 224)
+ return OPCODE_WSR_CPENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 226)
+ return OPCODE_WSR_INTSET;
+ if (Field_sr_Slot_inst_get (insn) == 227)
+ return OPCODE_WSR_INTCLEAR;
+ if (Field_sr_Slot_inst_get (insn) == 228)
+ return OPCODE_WSR_INTENABLE;
+ if (Field_sr_Slot_inst_get (insn) == 230)
+ return OPCODE_WSR_PS;
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WSR_VECBASE;
+ if (Field_sr_Slot_inst_get (insn) == 232)
+ return OPCODE_WSR_EXCCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 233)
+ return OPCODE_WSR_DEBUGCAUSE;
+ if (Field_sr_Slot_inst_get (insn) == 234)
+ return OPCODE_WSR_CCOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 236)
+ return OPCODE_WSR_ICOUNT;
+ if (Field_sr_Slot_inst_get (insn) == 237)
+ return OPCODE_WSR_ICOUNTLEVEL;
+ if (Field_sr_Slot_inst_get (insn) == 238)
+ return OPCODE_WSR_EXCVADDR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WSR_CCOMPARE0;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WSR_CCOMPARE1;
+ if (Field_sr_Slot_inst_get (insn) == 244)
+ return OPCODE_WSR_MISC0;
+ if (Field_sr_Slot_inst_get (insn) == 245)
+ return OPCODE_WSR_MISC1;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 2)
+ return OPCODE_SEXT;
+ if (Field_op2_Slot_inst_get (insn) == 3)
+ return OPCODE_CLAMPS;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_MIN;
+ if (Field_op2_Slot_inst_get (insn) == 5)
+ return OPCODE_MAX;
+ if (Field_op2_Slot_inst_get (insn) == 6)
+ return OPCODE_MINU;
+ if (Field_op2_Slot_inst_get (insn) == 7)
+ return OPCODE_MAXU;
+ if (Field_op2_Slot_inst_get (insn) == 8)
+ return OPCODE_MOVEQZ;
+ if (Field_op2_Slot_inst_get (insn) == 9)
+ return OPCODE_MOVNEZ;
+ if (Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVLTZ;
+ if (Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_MOVGEZ;
+ if (Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_MOVF;
+ if (Field_op2_Slot_inst_get (insn) == 13)
+ return OPCODE_MOVT;
+ if (Field_op2_Slot_inst_get (insn) == 14)
+ {
+ if (Field_st_Slot_inst_get (insn) == 231)
+ return OPCODE_RUR_THREADPTR;
+ if (Field_st_Slot_inst_get (insn) == 240)
+ return OPCODE_RUR_AE_OVF_SAR;
+ if (Field_st_Slot_inst_get (insn) == 241)
+ return OPCODE_RUR_AE_BITHEAD;
+ if (Field_st_Slot_inst_get (insn) == 242)
+ return OPCODE_RUR_AE_TS_FTS_BU_BP;
+ if (Field_st_Slot_inst_get (insn) == 243)
+ return OPCODE_RUR_AE_SD_NO;
+ }
+ if (Field_op2_Slot_inst_get (insn) == 15)
+ {
+ if (Field_sr_Slot_inst_get (insn) == 231)
+ return OPCODE_WUR_THREADPTR;
+ if (Field_sr_Slot_inst_get (insn) == 240)
+ return OPCODE_WUR_AE_OVF_SAR;
+ if (Field_sr_Slot_inst_get (insn) == 241)
+ return OPCODE_WUR_AE_BITHEAD;
+ if (Field_sr_Slot_inst_get (insn) == 242)
+ return OPCODE_WUR_AE_TS_FTS_BU_BP;
+ if (Field_sr_Slot_inst_get (insn) == 243)
+ return OPCODE_WUR_AE_SD_NO;
+ }
+ }
+ if ((Field_op1_Slot_inst_get (insn) == 4 ||
+ Field_op1_Slot_inst_get (insn) == 5))
+ return OPCODE_EXTUI;
+ if (Field_op1_Slot_inst_get (insn) == 9)
+ {
+ if (Field_op2_Slot_inst_get (insn) == 0)
+ return OPCODE_L32E;
+ if (Field_op2_Slot_inst_get (insn) == 4)
+ return OPCODE_S32E;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 1)
+ return OPCODE_L32R;
+ if (Field_op0_Slot_inst_get (insn) == 2)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_L32I;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_S16I;
+ if (Field_r_Slot_inst_get (insn) == 6)
+ return OPCODE_S32I;
+ if (Field_r_Slot_inst_get (insn) == 7)
+ {
+ if (Field_t_Slot_inst_get (insn) == 0)
+ return OPCODE_DPFR;
+ if (Field_t_Slot_inst_get (insn) == 1)
+ return OPCODE_DPFW;
+ if (Field_t_Slot_inst_get (insn) == 2)
+ return OPCODE_DPFRO;
+ if (Field_t_Slot_inst_get (insn) == 3)
+ return OPCODE_DPFWO;
+ if (Field_t_Slot_inst_get (insn) == 4)
+ return OPCODE_DHWB;
+ if (Field_t_Slot_inst_get (insn) == 5)
+ return OPCODE_DHWBI;
+ if (Field_t_Slot_inst_get (insn) == 6)
+ return OPCODE_DHI;
+ if (Field_t_Slot_inst_get (insn) == 7)
+ return OPCODE_DII;
+ if (Field_t_Slot_inst_get (insn) == 8)
+ {
+ if (Field_op1_Slot_inst_get (insn) == 4)
+ return OPCODE_DIWB;
+ if (Field_op1_Slot_inst_get (insn) == 5)
+ return OPCODE_DIWBI;
+ }
+ if (Field_t_Slot_inst_get (insn) == 12)
+ return OPCODE_IPF;
+ if (Field_t_Slot_inst_get (insn) == 14)
+ return OPCODE_IHI;
+ if (Field_t_Slot_inst_get (insn) == 15)
+ return OPCODE_III;
+ }
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_MOVI;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_L32AI;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_inst_get (insn) == 14)
+ return OPCODE_S32C1I;
+ if (Field_r_Slot_inst_get (insn) == 15)
+ return OPCODE_S32RI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 4)
+ {
+ if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_I;
+ if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_X;
+ if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_I;
+ if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_X;
+ if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_IU;
+ if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ56_XU;
+ if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_CVTQ48A32S;
+ if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_IU;
+ if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LQ32F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP24F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP24X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24S_L_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_ae_s3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVP48;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVPA24X2;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_CVTA32P24_L;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_LL;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_HL;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVAP24S_L;
+ if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_TRUNCA16P24S_L;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16X2F_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16X2F_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP16X2F_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP16X2F_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LP24X2_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_LP24X2_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24X2S_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 12 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP16F_L_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_I;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_IU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_X;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 13 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_SP24F_L_XU;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_TRUNCP24A32X2;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 11 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_CVTA32P24_H;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 14 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_LH;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 15 &&
+ Field_op2_Slot_inst_get (insn) == 11)
+ return OPCODE_AE_CVTP24A16X2_HH;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVAP24S_H;
+ if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 8 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_TRUNCA16P24S_H;
+ if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_I;
+ if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_X;
+ if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_TRUNCA32Q48;
+ if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_I;
+ if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_X;
+ if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_NSAQ56S;
+ if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_IU;
+ if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ56S_XU;
+ if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_IU;
+ if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SQ32F_XU;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLIQ56;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRLIQ56;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRAIQ56;
+ if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
+ Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLISQ56S;
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SHA32;
+ if (Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLDL32T;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SLLAQ56;
+ if (Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLDL16T;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SRLAQ56;
+ if (Field_op1_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_LBK;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SRAAQ56;
+ if (Field_op1_Slot_inst_get (insn) == 3 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLEL32T;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SLLASQ56S;
+ if (Field_op1_Slot_inst_get (insn) == 4 &&
+ Field_op2_Slot_inst_get (insn) == 10)
+ return OPCODE_AE_VLEL16T;
+ if (Field_op1_Slot_inst_get (insn) == 5 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_MOVTQ56;
+ if (Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_MOVFQ56;
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_OVERFLOW;
+ if (Field_r_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_SBI;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_SAR;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_DB;
+ if (Field_r_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_SB;
+ if (Field_r_Slot_inst_get (insn) == 2 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_BITPTR;
+ if (Field_r_Slot_inst_get (insn) == 3 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_BITSUSED;
+ if (Field_r_Slot_inst_get (insn) == 4 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_TABLESIZE;
+ if (Field_r_Slot_inst_get (insn) == 5 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_FIRST_TS;
+ if (Field_r_Slot_inst_get (insn) == 6 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_NEXTOFFSET;
+ if (Field_r_Slot_inst_get (insn) == 7 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_WUR_AE_SEARCHDONE;
+ if (Field_r_Slot_inst_get (insn) == 8 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 10 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_VLDSHT;
+ if (Field_r_Slot_inst_get (insn) == 12 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_VLES16C;
+ if (Field_r_Slot_inst_get (insn) == 13 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_SBF;
+ if (Field_r_Slot_inst_get (insn) == 14 &&
+ Field_op1_Slot_inst_get (insn) == 7 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_VLDL16C;
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLSQ56;
+ if (Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 6 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_LB;
+ if (Field_s_Slot_inst_get (insn) == 1 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRLSQ56;
+ if (Field_s_Slot_inst_get (insn) == 2 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SRASQ56;
+ if (Field_s_Slot_inst_get (insn) == 3 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_SLLSSQ56S;
+ if (Field_s_Slot_inst_get (insn) == 4 &&
+ Field_t_Slot_inst_get (insn) == 1 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_AE_MOVQ56;
+ if (Field_s_Slot_inst_get (insn) == 8 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_OVERFLOW;
+ if (Field_s_Slot_inst_get (insn) == 9 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_SAR;
+ if (Field_s_Slot_inst_get (insn) == 10 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_BITPTR;
+ if (Field_s_Slot_inst_get (insn) == 11 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_BITSUSED;
+ if (Field_s_Slot_inst_get (insn) == 12 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_TABLESIZE;
+ if (Field_s_Slot_inst_get (insn) == 13 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_FIRST_TS;
+ if (Field_s_Slot_inst_get (insn) == 14 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_NEXTOFFSET;
+ if (Field_s_Slot_inst_get (insn) == 15 &&
+ Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op1_Slot_inst_get (insn) == 9 &&
+ Field_op2_Slot_inst_get (insn) == 12)
+ return OPCODE_RUR_AE_SEARCHDONE;
+ if (Field_t_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_LBKI;
+ if (Field_t_Slot_inst_get (insn) == 0 &&
+ Field_r_Slot_inst_get (insn) == 2 &&
+ Field_op2_Slot_inst_get (insn) == 15)
+ return OPCODE_AE_DBI;
+ if (Field_t_Slot_inst_get (insn) == 2 &&
+ Field_s_Slot_inst_get (insn) == 0 &&
+ Field_op2_Slot_inst_get (insn) == 14)
+ return OPCODE_AE_LBI;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 5)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_CALL0;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ return OPCODE_CALL4;
+ if (Field_n_Slot_inst_get (insn) == 2)
+ return OPCODE_CALL8;
+ if (Field_n_Slot_inst_get (insn) == 3)
+ return OPCODE_CALL12;
+ }
+ if (Field_op0_Slot_inst_get (insn) == 6)
+ {
+ if (Field_n_Slot_inst_get (insn) == 0)
+ return OPCODE_J;
+ if (Field_n_Slot_inst_get (insn) == 1)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQZ;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTZ;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEZ;
+ }
+ if (Field_n_Slot_inst_get (insn) == 2)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_BEQI;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ return OPCODE_BNEI;
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEI;
+ }
+ if (Field_n_Slot_inst_get (insn) == 3)
+ {
+ if (Field_m_Slot_inst_get (insn) == 0)
+ return OPCODE_ENTRY;
+ if (Field_m_Slot_inst_get (insn) == 1)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BF;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BT;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_LOOP;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_LOOPNEZ;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_LOOPGTZ;
+ }
+ if (Field_m_Slot_inst_get (insn) == 2)
+ return OPCODE_BLTUI;
+ if (Field_m_Slot_inst_get (insn) == 3)
+ return OPCODE_BGEUI;
+ }
+ }
+ if (Field_op0_Slot_inst_get (insn) == 7)
+ {
+ if (Field_r_Slot_inst_get (insn) == 0)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_inst_get (insn) == 1)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_inst_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_inst_get (insn) == 3)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_inst_get (insn) == 4)
+ return OPCODE_BALL;
+ if (Field_r_Slot_inst_get (insn) == 5)
+ return OPCODE_BBC;
+ if ((Field_r_Slot_inst_get (insn) == 6 ||
+ Field_r_Slot_inst_get (insn) == 7))
+ return OPCODE_BBCI;
+ if (Field_r_Slot_inst_get (insn) == 8)
+ return OPCODE_BANY;
+ if (Field_r_Slot_inst_get (insn) == 9)
+ return OPCODE_BNE;
+ if (Field_r_Slot_inst_get (insn) == 10)
+ return OPCODE_BGE;
+ if (Field_r_Slot_inst_get (insn) == 11)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_inst_get (insn) == 12)
+ return OPCODE_BNALL;
+ if (Field_r_Slot_inst_get (insn) == 13)
+ return OPCODE_BBS;
+ if ((Field_r_Slot_inst_get (insn) == 14 ||
+ Field_r_Slot_inst_get (insn) == 15))
+ return OPCODE_BBSI;
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16b_get (insn) == 12)
+ {
+ if (Field_i_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOVI_N;
+ if (Field_i_Slot_inst16b_get (insn) == 1)
+ {
+ if (Field_z_Slot_inst16b_get (insn) == 0)
+ return OPCODE_BEQZ_N;
+ if (Field_z_Slot_inst16b_get (insn) == 1)
+ return OPCODE_BNEZ_N;
+ }
+ }
+ if (Field_op0_Slot_inst16b_get (insn) == 13)
+ {
+ if (Field_r_Slot_inst16b_get (insn) == 0)
+ return OPCODE_MOV_N;
+ if (Field_r_Slot_inst16b_get (insn) == 15)
+ {
+ if (Field_t_Slot_inst16b_get (insn) == 0)
+ return OPCODE_RET_N;
+ if (Field_t_Slot_inst16b_get (insn) == 1)
+ return OPCODE_RETW_N;
+ if (Field_t_Slot_inst16b_get (insn) == 2)
+ return OPCODE_BREAK_N;
+ if (Field_t_Slot_inst16b_get (insn) == 3 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_NOP_N;
+ if (Field_t_Slot_inst16b_get (insn) == 6 &&
+ Field_s_Slot_inst16b_get (insn) == 0)
+ return OPCODE_ILL_N;
+ }
+ }
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+ if (Field_op0_Slot_inst16a_get (insn) == 8)
+ return OPCODE_L32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 9)
+ return OPCODE_S32I_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 10)
+ return OPCODE_ADD_N;
+ if (Field_op0_Slot_inst16a_get (insn) == 11)
+ return OPCODE_ADDI_N;
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_ae_slot0_decode (const xtensa_insnbuf insn)
+{
+ if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_J;
+ if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_EXTUI;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BGEZ;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BLTZ;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BEQZ;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_BNEZ;
+ if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVI;
+ if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRAI;
+ if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SLLI;
+ if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVTQ56;
+ if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_HH;
+ if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
+ Field_ae_r20_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_L32I;
+ if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_I;
+ if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_HL;
+ if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_IU;
+ if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_X;
+ if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16F_XU;
+ if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_LH;
+ if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_I;
+ if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_IU;
+ if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_XU;
+ if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP16X2F_X;
+ if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_I;
+ if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_IU;
+ if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_X;
+ if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTP24A16X2_LL;
+ if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24_XU;
+ if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_I;
+ if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_XU;
+ if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_IU;
+ if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_I;
+ if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_IU;
+ if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_X;
+ if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24F_X;
+ if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2_XU;
+ if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_I;
+ if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_X;
+ if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_IU;
+ if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LP24X2F_XU;
+ if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVPA24X2;
+ if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_I;
+ if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_IU;
+ if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_X;
+ if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_X;
+ if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_XU;
+ if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_I;
+ if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_IU;
+ if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16F_L_XU;
+ if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_X;
+ if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24F_L_XU;
+ if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_IU;
+ if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_I;
+ if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_X;
+ if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24S_L_XU;
+ if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_I;
+ if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_I;
+ if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_IU;
+ if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_X;
+ if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_IU;
+ if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2F_XU;
+ if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_X;
+ if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_XU;
+ if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_TRUNCP24A32X2;
+ if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP24X2S_I;
+ if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ32F_I;
+ if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ32F_IU;
+ if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ32F_I;
+ if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ32F_X;
+ if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ32F_XU;
+ if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ56_I;
+ if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ32F_IU;
+ if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ56_IU;
+ if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_LQ56_X;
+ if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTQ48A32S;
+ if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_JX;
+ if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SSR;
+ if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_NOP;
+ if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSA8B;
+ if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSA8L;
+ if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSL;
+ if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s8_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_LQ56_XU;
+ if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ALL8;
+ if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBCI;
+ if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBSI;
+ if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_s_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ANY8;
+ if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_SSAI;
+ if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SP16X2F_IU;
+ if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_I;
+ if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_IU;
+ if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLIQ56;
+ if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SRAIQ56;
+ if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SRLIQ56;
+ if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLISQ56S;
+ if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ABS;
+ if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_NEG;
+ if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRA;
+ if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRL;
+ if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVP48;
+ if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ANY4;
+ if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_MOVQ56;
+ if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SLLSSQ56S;
+ if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRASQ56;
+ if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRLSQ56;
+ if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SLLSQ56;
+ if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_ALL4;
+ if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_X;
+ if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SQ56S_XU;
+ if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTA32P24_H;
+ if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_CVTA32P24_L;
+ if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVAP24S_H;
+ if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_TRUNCA16P24S_L;
+ if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVAP24S_L;
+ if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_NSAQ56S;
+ if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_TRUNCA32Q48;
+ if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+ Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_BT;
+ if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_TRUNCA16P24S_H;
+ if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+ Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_BLTUI;
+ if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_MOVFQ56;
+ if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLAQ56;
+ if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AE_SLLASQ56S;
+ if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SLL;
+ if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf357_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRAAQ56;
+ if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SRLAQ56;
+ if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SQ32F_XU;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 178 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADD;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 179 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADDX8;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 180 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADDX2;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 181 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_AND;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 182 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ANDB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ANDBC;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 184 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ADDX4;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 185 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_CLAMPS;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 186 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MAX;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 187 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MIN;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 188 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MAXU;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 189 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MINU;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 190 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVEQZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 191 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVF;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 194 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVGEZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 195 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ORB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 196 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVLTZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 197 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_ORBC;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 198 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SEXT;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRC;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 200 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVNEZ;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 201 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SRLI;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 202 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 203 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUBX4;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 204 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUBX2;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 205 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_SUBX8;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 206 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_XOR;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 207 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_XORB;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 208 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_MOVT;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 224 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+ return OPCODE_OR;
+ if (Field_imm8_Slot_ae_slot0_get (insn) == 244 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+ Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_AE_SQ32F_X;
+ if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
+ return OPCODE_L32R;
+ if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_BNE;
+ if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_BNONE;
+ if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_L16SI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_L8UI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_ADDI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_L16UI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BALL;
+ if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_S16I;
+ if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BANY;
+ if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_S32I;
+ if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBC;
+ if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+ return OPCODE_S8I;
+ if (Field_r_Slot_ae_slot0_get (insn) == 8 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_ADDMI;
+ if (Field_r_Slot_ae_slot0_get (insn) == 9 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BBS;
+ if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BEQ;
+ if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BGEU;
+ if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BGE;
+ if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BLT;
+ if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BLTU;
+ if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+ return OPCODE_BNALL;
+ if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BEQI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BGEI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BGEUI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BNEI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+ return OPCODE_BLTI;
+ if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
+ Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+ Field_r_Slot_ae_slot0_get (insn) == 0)
+ return OPCODE_BF;
+ return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_ae_slot1_decode (const xtensa_insnbuf insn)
+{
+ if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_NEGSP24S;
+ if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ABSSP24S;
+ if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_NEGP24;
+ if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MAXBQ56S;
+ if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MINBQ56S;
+ if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_EQQ56;
+ if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ADDSQ56S;
+ if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ANDQ56;
+ if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MAXQ56S;
+ if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ORQ56;
+ if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_MINQ56S;
+ if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_SUBQ56;
+ if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_SUBSQ56S;
+ if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_XORQ56;
+ if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_NANDQ56;
+ if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_ABSQ56;
+ if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
+ return OPCODE_AE_NEGSQ56S;
+ if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf338_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_SATQ48S;
+ if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_LTQ56S;
+ if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ABSSQ56S;
+ if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_NEGQ56;
+ if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_LEQ56S;
+ if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_TRUNCP24Q48X2;
+ if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
+ Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ADDQ56;
+ if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAFP24S_HH_LL;
+ if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAFP24S_HL_LH;
+ if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAP24S_HH_LL;
+ if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf12_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_SLLISP24S;
+ if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS32P16S_HL;
+ if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAAP24S_HL_LH;
+ if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS32P16S_LH;
+ if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS32P16S_LL;
+ if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_HH;
+ if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_HH;
+ if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_HL;
+ if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_LH;
+ if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_HH;
+ if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFS56P24S_LL;
+ if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_HL;
+ if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_LH;
+ if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAP24S_LL;
+ if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_HL;
+ if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_HH;
+ if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_HL;
+ if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASFP24S_HH_LL;
+ if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_LH;
+ if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASFP24S_HL_LH;
+ if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASP24S_HH_LL;
+ if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULASP24S_HL_LH;
+ if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAS56P24S_LL;
+ if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_HH;
+ if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_HL;
+ if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_LL;
+ if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFP24S_LH;
+ if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_HH;
+ if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_HL;
+ if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_LH;
+ if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_LH;
+ if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULFS32P16S_LL;
+ if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_HH;
+ if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAFP24S_HH_LL;
+ if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_HL;
+ if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAFP24S_HL_LH;
+ if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAP24S_HH_LL;
+ if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSAP24S_HL_LH;
+ if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_LH;
+ if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_HH;
+ if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_HL;
+ if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_LL;
+ if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFP24S_LH;
+ if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_HH;
+ if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_HL;
+ if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_LH;
+ if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULP24S_LL;
+ if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS32P16S_LL;
+ if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_HH;
+ if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_LL;
+ if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_HL;
+ if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_HH;
+ if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_HL;
+ if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_LH;
+ if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSFS56P24S_LH;
+ if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSP24S_LL;
+ if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_HH;
+ if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_LH;
+ if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_HL;
+ if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSS56P24S_LL;
+ if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSFP24S_HH_LL;
+ if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSFP24S_HL_LH;
+ if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULAFP24S_LL;
+ if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSP24S_HH_LL;
+ if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULSSP24S_HL_LH;
+ if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASFP24S_HH_LL;
+ if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZAAFP24S_HH_LL;
+ if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASFP24S_HL_LH;
+ if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASP24S_HH_LL;
+ if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZASP24S_HL_LH;
+ if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZAAFP24S_HL_LH;
+ if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAFP24S_HH_LL;
+ if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAFP24S_HL_LH;
+ if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAP24S_HL_LH;
+ if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSAP24S_HH_LL;
+ if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSSFP24S_HH_LL;
+ if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSSFP24S_HL_LH;
+ if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
+ return OPCODE_AE_MULZSSP24S_HH_LL;
+ if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULZAAP24S_HH_LL;
+ if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULZSSP24S_HL_LH;
+ if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULZAAP24S_HL_LH;
+ if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
+ Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULAFS32P16S_HH;
+ if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MAXBP24S;
+ if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MINBP24S;
+ if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVFP48;
+ if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVTP48;
+ if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ADDP24;
+ if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ANDP48;
+ if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MAXP24S;
+ if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MINP24S;
+ if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ADDSP24S;
+ if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_NANDP48;
+ if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ORP48;
+ if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_HL;
+ if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_HH;
+ if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_LH;
+ if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SELP24_LL;
+ if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SUBP24;
+ if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SLLIP24;
+ if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRAIP24;
+ if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRLIP24;
+ if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16S_L;
+ if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16U_H;
+ if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16U_L;
+ if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16U_H;
+ if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16S_H;
+ if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16U_L;
+ if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16S_H;
+ if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16S_L;
+ if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAQ32SP16S_L;
+ if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16U_H;
+ if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULFQ32SP16U_L;
+ if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16S_L;
+ if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16S_H;
+ if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16U_H;
+ if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULQ32SP16U_L;
+ if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16S_H;
+ if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULAFQ32SP16S_H;
+ if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16S_L;
+ if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16U_H;
+ if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSQ32SP16U_L;
+ if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MULSFQ32SP16U_L;
+ if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_CVTQ48P24S_H;
+ if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ZEROQ56;
+ if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_NOP;
+ if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_CVTQ48P24S_L;
+ if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVQ56;
+ if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSQ32ASYM;
+ if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSQ32SYM;
+ if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_TRUNCQ32;
+ if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULSQ32SP16S_H;
+ if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULSQ32SP16S_L;
+ if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_MOVP48;
+ if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSP16ASYM;
+ if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSP16SYM;
+ if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRASP24;
+ if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SLLSP24;
+ if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SRLSP24;
+ if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_TRUNCP16;
+ if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ZEROP48;
+ if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_SLLSSP24S;
+ if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSP16Q48ASYM;
+ if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_ROUNDSP16Q48SYM;
+ if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSP24Q48ASYM;
+ if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ROUNDSP24Q48SYM;
+ if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MULSQ32SP16U_H;
+ if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_EQP24;
+ if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_LEP24S;
+ if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf208_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_LTP24S;
+ if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ftsf347_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MOVFP24X2;
+ if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_MOVTP24X2;
+ if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_SUBSP24S;
+ if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+ return OPCODE_AE_XORP48;
+ if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
+ Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
+ return OPCODE_AE_ABSP24;
+ if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSAQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZASQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZAAQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAFQ32SP16U_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16S_LL;
+ if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAQ32SP16S_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16U_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+ return OPCODE_AE_MULZASFQ32SP16U_HH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+ return OPCODE_AE_MULZSAQ32SP16S_LH;
+ if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+ Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+ return OPCODE_AE_MULZSSQ32SP16U_LL;
+ return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots. */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[0] & 0x80000000) >> 31);
+ slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1);
+}
+
+static void
+Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31);
+ insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1);
+}
+
+static void
+Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn,
+ xtensa_insnbuf slotbuf)
+{
+ slotbuf[1] = 0;
+ slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4);
+}
+
+static void
+Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn,
+ const xtensa_insnbuf slotbuf)
+{
+ insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+ Field_t_Slot_inst_get,
+ Field_bbi4_Slot_inst_get,
+ Field_bbi_Slot_inst_get,
+ Field_imm12_Slot_inst_get,
+ Field_imm8_Slot_inst_get,
+ Field_s_Slot_inst_get,
+ Field_imm12b_Slot_inst_get,
+ Field_imm16_Slot_inst_get,
+ Field_m_Slot_inst_get,
+ Field_n_Slot_inst_get,
+ Field_offset_Slot_inst_get,
+ Field_op0_Slot_inst_get,
+ Field_op1_Slot_inst_get,
+ Field_op2_Slot_inst_get,
+ Field_r_Slot_inst_get,
+ Field_sa4_Slot_inst_get,
+ Field_sae4_Slot_inst_get,
+ Field_sae_Slot_inst_get,
+ Field_sal_Slot_inst_get,
+ Field_sargt_Slot_inst_get,
+ Field_sas4_Slot_inst_get,
+ Field_sas_Slot_inst_get,
+ Field_sr_Slot_inst_get,
+ Field_st_Slot_inst_get,
+ Field_thi3_Slot_inst_get,
+ Field_imm4_Slot_inst_get,
+ Field_mn_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_inst_get,
+ Field_s2_Slot_inst_get,
+ Field_r2_Slot_inst_get,
+ Field_t4_Slot_inst_get,
+ Field_s4_Slot_inst_get,
+ Field_r4_Slot_inst_get,
+ Field_t8_Slot_inst_get,
+ Field_s8_Slot_inst_get,
+ Field_r8_Slot_inst_get,
+ Field_xt_wbr15_imm_Slot_inst_get,
+ Field_xt_wbr18_imm_Slot_inst_get,
+ Field_ae_r3_Slot_inst_get,
+ Field_ae_s_non_samt_Slot_inst_get,
+ Field_ae_s3_Slot_inst_get,
+ Field_ae_r32_Slot_inst_get,
+ Field_ae_samt_s_t_Slot_inst_get,
+ Field_ae_r20_Slot_inst_get,
+ Field_ae_r10_Slot_inst_get,
+ Field_ae_s20_Slot_inst_get,
+ Field_ae_fld_ohba_Slot_inst_get,
+ Field_ae_fld_ohba2_Slot_inst_get,
+ 0,
+ Field_ftsf12_Slot_inst_get,
+ Field_ftsf13_Slot_inst_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+ Field_t_Slot_inst_set,
+ Field_bbi4_Slot_inst_set,
+ Field_bbi_Slot_inst_set,
+ Field_imm12_Slot_inst_set,
+ Field_imm8_Slot_inst_set,
+ Field_s_Slot_inst_set,
+ Field_imm12b_Slot_inst_set,
+ Field_imm16_Slot_inst_set,
+ Field_m_Slot_inst_set,
+ Field_n_Slot_inst_set,
+ Field_offset_Slot_inst_set,
+ Field_op0_Slot_inst_set,
+ Field_op1_Slot_inst_set,
+ Field_op2_Slot_inst_set,
+ Field_r_Slot_inst_set,
+ Field_sa4_Slot_inst_set,
+ Field_sae4_Slot_inst_set,
+ Field_sae_Slot_inst_set,
+ Field_sal_Slot_inst_set,
+ Field_sargt_Slot_inst_set,
+ Field_sas4_Slot_inst_set,
+ Field_sas_Slot_inst_set,
+ Field_sr_Slot_inst_set,
+ Field_st_Slot_inst_set,
+ Field_thi3_Slot_inst_set,
+ Field_imm4_Slot_inst_set,
+ Field_mn_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_inst_set,
+ Field_s2_Slot_inst_set,
+ Field_r2_Slot_inst_set,
+ Field_t4_Slot_inst_set,
+ Field_s4_Slot_inst_set,
+ Field_r4_Slot_inst_set,
+ Field_t8_Slot_inst_set,
+ Field_s8_Slot_inst_set,
+ Field_r8_Slot_inst_set,
+ Field_xt_wbr15_imm_Slot_inst_set,
+ Field_xt_wbr18_imm_Slot_inst_set,
+ Field_ae_r3_Slot_inst_set,
+ Field_ae_s_non_samt_Slot_inst_set,
+ Field_ae_s3_Slot_inst_set,
+ Field_ae_r32_Slot_inst_set,
+ Field_ae_samt_s_t_Slot_inst_set,
+ Field_ae_r20_Slot_inst_set,
+ Field_ae_r10_Slot_inst_set,
+ Field_ae_s20_Slot_inst_set,
+ Field_ae_fld_ohba_Slot_inst_set,
+ Field_ae_fld_ohba2_Slot_inst_set,
+ 0,
+ Field_ftsf12_Slot_inst_set,
+ Field_ftsf13_Slot_inst_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+ Field_t_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_get,
+ Field_st_Slot_inst16a_get,
+ 0,
+ Field_imm4_Slot_inst16a_get,
+ 0,
+ Field_i_Slot_inst16a_get,
+ Field_imm6lo_Slot_inst16a_get,
+ Field_imm6hi_Slot_inst16a_get,
+ Field_imm7lo_Slot_inst16a_get,
+ Field_imm7hi_Slot_inst16a_get,
+ Field_z_Slot_inst16a_get,
+ Field_imm6_Slot_inst16a_get,
+ Field_imm7_Slot_inst16a_get,
+ Field_t2_Slot_inst16a_get,
+ Field_s2_Slot_inst16a_get,
+ Field_r2_Slot_inst16a_get,
+ Field_t4_Slot_inst16a_get,
+ Field_s4_Slot_inst16a_get,
+ Field_r4_Slot_inst16a_get,
+ Field_t8_Slot_inst16a_get,
+ Field_s8_Slot_inst16a_get,
+ Field_r8_Slot_inst16a_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+ Field_t_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16a_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16a_set,
+ Field_st_Slot_inst16a_set,
+ 0,
+ Field_imm4_Slot_inst16a_set,
+ 0,
+ Field_i_Slot_inst16a_set,
+ Field_imm6lo_Slot_inst16a_set,
+ Field_imm6hi_Slot_inst16a_set,
+ Field_imm7lo_Slot_inst16a_set,
+ Field_imm7hi_Slot_inst16a_set,
+ Field_z_Slot_inst16a_set,
+ Field_imm6_Slot_inst16a_set,
+ Field_imm7_Slot_inst16a_set,
+ Field_t2_Slot_inst16a_set,
+ Field_s2_Slot_inst16a_set,
+ Field_r2_Slot_inst16a_set,
+ Field_t4_Slot_inst16a_set,
+ Field_s4_Slot_inst16a_set,
+ Field_r4_Slot_inst16a_set,
+ Field_t8_Slot_inst16a_set,
+ Field_s8_Slot_inst16a_set,
+ Field_r8_Slot_inst16a_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+ Field_t_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_get,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_get,
+ Field_st_Slot_inst16b_get,
+ 0,
+ Field_imm4_Slot_inst16b_get,
+ 0,
+ Field_i_Slot_inst16b_get,
+ Field_imm6lo_Slot_inst16b_get,
+ Field_imm6hi_Slot_inst16b_get,
+ Field_imm7lo_Slot_inst16b_get,
+ Field_imm7hi_Slot_inst16b_get,
+ Field_z_Slot_inst16b_get,
+ Field_imm6_Slot_inst16b_get,
+ Field_imm7_Slot_inst16b_get,
+ Field_t2_Slot_inst16b_get,
+ Field_s2_Slot_inst16b_get,
+ Field_r2_Slot_inst16b_get,
+ Field_t4_Slot_inst16b_get,
+ Field_s4_Slot_inst16b_get,
+ Field_r4_Slot_inst16b_get,
+ Field_t8_Slot_inst16b_get,
+ Field_s8_Slot_inst16b_get,
+ Field_r8_Slot_inst16b_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+ Field_t_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_Slot_inst16b_set,
+ 0,
+ 0,
+ Field_r_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_sr_Slot_inst16b_set,
+ Field_st_Slot_inst16b_set,
+ 0,
+ Field_imm4_Slot_inst16b_set,
+ 0,
+ Field_i_Slot_inst16b_set,
+ Field_imm6lo_Slot_inst16b_set,
+ Field_imm6hi_Slot_inst16b_set,
+ Field_imm7lo_Slot_inst16b_set,
+ Field_imm7hi_Slot_inst16b_set,
+ Field_z_Slot_inst16b_set,
+ Field_imm6_Slot_inst16b_set,
+ Field_imm7_Slot_inst16b_set,
+ Field_t2_Slot_inst16b_set,
+ Field_s2_Slot_inst16b_set,
+ Field_r2_Slot_inst16b_set,
+ Field_t4_Slot_inst16b_set,
+ Field_s4_Slot_inst16b_set,
+ Field_r4_Slot_inst16b_set,
+ Field_t8_Slot_inst16b_set,
+ Field_s8_Slot_inst16b_set,
+ Field_r8_Slot_inst16b_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_ae_slot1_get_field_fns[] = {
+ Field_t_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot1_get,
+ 0,
+ Field_ae_r20_Slot_ae_slot1_get,
+ Field_ae_r10_Slot_ae_slot1_get,
+ Field_ae_s20_Slot_ae_slot1_get,
+ 0,
+ 0,
+ Field_op0_s3_Slot_ae_slot1_get,
+ Field_ftsf12_Slot_ae_slot1_get,
+ Field_ftsf13_Slot_ae_slot1_get,
+ Field_ftsf14_Slot_ae_slot1_get,
+ Field_ftsf21ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf22ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf23ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf24ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf25ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf26ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf27ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf28ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf29ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf30ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf31ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf32ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf33ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf34ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf35ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf36ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf37ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf38ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf39ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf40ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf41ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf42ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf43ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf44ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf45ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf46ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf47ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf48ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf49ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf50ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf51ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf52ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf53ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf54ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf55ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf56ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf57ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf58ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf59ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf60ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf61ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf63ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf64ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf66ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf67ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf69ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf71ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf72ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf73ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf75ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf76ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf77ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf78ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf79ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf80ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf81ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf82ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf84ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf86ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf87ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf88ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf89ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf90ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf91ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf92ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf94ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf96ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf97ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf98ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf99ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf100ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf101ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf103ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf104ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf105ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf106ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf107ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf108ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf109ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf110ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf111ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf112ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf113ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf114ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf115ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf116ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf118ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf119ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf120ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf122ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf124ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf125ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf126ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf127ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf128ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf129ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf130ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf131ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf132ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf133ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf134ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf135ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf136ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf137ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf138ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf139ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf140ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf141ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf142ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf143ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf144ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf145ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf146ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf147ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf148ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf149ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf150ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf151ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf152ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf153ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf154ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf155ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf156ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf157ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf158ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf159ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf160ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf161ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf162ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf163ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf164ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf165ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf166ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf167ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf168ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf169ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf170ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf171ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf172ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf173ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf174ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf175ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf176ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf177ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf178ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf179ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf180ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf181ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf182ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf183ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf184ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf185ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf186ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf187ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf188ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf189ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf190ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf191ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf192ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf193ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf194ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf195ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf196ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf197ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf198ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf199ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf200ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf201ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf202ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf203ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf204ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf205ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf206ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf207ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf208_Slot_ae_slot1_get,
+ Field_ftsf209ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf210ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf211ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf330ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf332ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf334ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf336ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf337ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf338_Slot_ae_slot1_get,
+ Field_ftsf339ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf340_Slot_ae_slot1_get,
+ Field_ftsf341ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf342ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf343ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf344ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf346ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf347_Slot_ae_slot1_get,
+ Field_ftsf348ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf349ae_slot1_Slot_ae_slot1_get,
+ Field_ftsf350ae_slot1_Slot_ae_slot1_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_ae_slot1_set_field_fns[] = {
+ Field_t_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_t2_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot1_set,
+ 0,
+ Field_ae_r20_Slot_ae_slot1_set,
+ Field_ae_r10_Slot_ae_slot1_set,
+ Field_ae_s20_Slot_ae_slot1_set,
+ 0,
+ 0,
+ Field_op0_s3_Slot_ae_slot1_set,
+ Field_ftsf12_Slot_ae_slot1_set,
+ Field_ftsf13_Slot_ae_slot1_set,
+ Field_ftsf14_Slot_ae_slot1_set,
+ Field_ftsf21ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf22ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf23ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf24ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf25ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf26ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf27ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf28ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf29ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf30ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf31ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf32ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf33ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf34ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf35ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf36ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf37ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf38ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf39ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf40ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf41ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf42ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf43ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf44ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf45ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf46ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf47ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf48ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf49ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf50ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf51ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf52ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf53ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf54ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf55ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf56ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf57ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf58ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf59ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf60ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf61ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf63ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf64ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf66ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf67ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf69ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf71ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf72ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf73ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf75ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf76ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf77ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf78ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf79ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf80ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf81ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf82ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf84ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf86ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf87ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf88ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf89ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf90ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf91ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf92ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf94ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf96ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf97ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf98ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf99ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf100ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf101ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf103ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf104ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf105ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf106ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf107ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf108ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf109ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf110ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf111ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf112ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf113ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf114ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf115ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf116ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf118ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf119ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf120ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf122ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf124ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf125ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf126ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf127ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf128ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf129ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf130ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf131ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf132ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf133ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf134ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf135ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf136ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf137ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf138ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf139ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf140ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf141ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf142ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf143ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf144ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf145ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf146ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf147ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf148ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf149ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf150ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf151ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf152ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf153ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf154ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf155ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf156ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf157ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf158ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf159ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf160ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf161ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf162ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf163ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf164ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf165ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf166ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf167ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf168ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf169ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf170ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf171ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf172ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf173ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf174ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf175ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf176ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf177ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf178ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf179ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf180ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf181ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf182ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf183ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf184ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf185ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf186ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf187ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf188ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf189ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf190ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf191ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf192ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf193ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf194ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf195ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf196ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf197ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf198ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf199ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf200ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf201ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf202ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf203ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf204ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf205ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf206ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf207ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf208_Slot_ae_slot1_set,
+ Field_ftsf209ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf210ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf211ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf330ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf332ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf334ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf336ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf337ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf338_Slot_ae_slot1_set,
+ Field_ftsf339ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf340_Slot_ae_slot1_set,
+ Field_ftsf341ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf342ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf343ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf344ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf346ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf347_Slot_ae_slot1_set,
+ Field_ftsf348ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf349ae_slot1_Slot_ae_slot1_set,
+ Field_ftsf350ae_slot1_Slot_ae_slot1_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_ae_slot0_get_field_fns[] = {
+ Field_t_Slot_ae_slot0_get,
+ 0,
+ Field_bbi_Slot_ae_slot0_get,
+ Field_imm12_Slot_ae_slot0_get,
+ Field_imm8_Slot_ae_slot0_get,
+ Field_s_Slot_ae_slot0_get,
+ Field_imm12b_Slot_ae_slot0_get,
+ Field_imm16_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_offset_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_op2_Slot_ae_slot0_get,
+ Field_r_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_sae_Slot_ae_slot0_get,
+ Field_sal_Slot_ae_slot0_get,
+ Field_sargt_Slot_ae_slot0_get,
+ 0,
+ Field_sas_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s4_Slot_ae_slot0_get,
+ 0,
+ 0,
+ Field_s8_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot0_get,
+ Field_ae_samt_s_t_Slot_ae_slot0_get,
+ Field_ae_r20_Slot_ae_slot0_get,
+ Field_ae_r10_Slot_ae_slot0_get,
+ Field_ae_s20_Slot_ae_slot0_get,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_s4_Slot_ae_slot0_get,
+ Field_ftsf212ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf213ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf214ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf215ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf216ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf217_Slot_ae_slot0_get,
+ Field_ftsf218ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf219ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf220ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf221ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf222ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf223ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf224ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf225ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf226ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf227ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf228ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf229ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf230ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf231ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf232ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf233ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf234ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf235ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf236ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf237ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf238ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf239ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf240ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf241ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf242ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf243ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf244ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf245ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf246ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf247ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf248ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf249ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf250ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf251ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf252ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf253ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf254ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf255ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf256ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf257ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf258ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf259ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf260ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf261ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf262ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf263ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf264ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf265ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf266ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf267ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf268ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf269ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf270ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf271ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf272ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf273ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf274ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf275ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf276ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf277ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf278ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf279ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf281ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf282ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf283ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf284ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf286ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf288ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf290ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf292ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf293_Slot_ae_slot0_get,
+ Field_ftsf294ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf295ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf296ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf297ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf298ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf299ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf300ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf301ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf302ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf303ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf304ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf306ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf308ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf309ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf310ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf311ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf312ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf313ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf314ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf315ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf316ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf317ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf318ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf319_Slot_ae_slot0_get,
+ Field_ftsf320ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf321_Slot_ae_slot0_get,
+ Field_ftsf322ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf323ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf324ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf325ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf326ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf328ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf329ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf352ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf353_Slot_ae_slot0_get,
+ Field_ftsf354ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf356ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf357_Slot_ae_slot0_get,
+ Field_ftsf358ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf359ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf360ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf361ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf362ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf364ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf365ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf366ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf368ae_slot0_Slot_ae_slot0_get,
+ Field_ftsf369ae_slot0_Slot_ae_slot0_get,
+ Implicit_Field_ar0_get,
+ Implicit_Field_ar4_get,
+ Implicit_Field_ar8_get,
+ Implicit_Field_ar12_get,
+ Implicit_Field_bt16_get,
+ Implicit_Field_bs16_get,
+ Implicit_Field_br16_get,
+ Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_ae_slot0_set_field_fns[] = {
+ Field_t_Slot_ae_slot0_set,
+ 0,
+ Field_bbi_Slot_ae_slot0_set,
+ Field_imm12_Slot_ae_slot0_set,
+ Field_imm8_Slot_ae_slot0_set,
+ Field_s_Slot_ae_slot0_set,
+ Field_imm12b_Slot_ae_slot0_set,
+ Field_imm16_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_offset_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_op2_Slot_ae_slot0_set,
+ Field_r_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_sae_Slot_ae_slot0_set,
+ Field_sal_Slot_ae_slot0_set,
+ Field_sargt_Slot_ae_slot0_set,
+ 0,
+ Field_sas_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_s4_Slot_ae_slot0_set,
+ 0,
+ 0,
+ Field_s8_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_ae_r32_Slot_ae_slot0_set,
+ Field_ae_samt_s_t_Slot_ae_slot0_set,
+ Field_ae_r20_Slot_ae_slot0_set,
+ Field_ae_r10_Slot_ae_slot0_set,
+ Field_ae_s20_Slot_ae_slot0_set,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ Field_op0_s4_Slot_ae_slot0_set,
+ Field_ftsf212ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf213ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf214ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf215ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf216ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf217_Slot_ae_slot0_set,
+ Field_ftsf218ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf219ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf220ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf221ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf222ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf223ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf224ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf225ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf226ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf227ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf228ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf229ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf230ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf231ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf232ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf233ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf234ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf235ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf236ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf237ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf238ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf239ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf240ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf241ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf242ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf243ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf244ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf245ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf246ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf247ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf248ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf249ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf250ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf251ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf252ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf253ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf254ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf255ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf256ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf257ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf258ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf259ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf260ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf261ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf262ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf263ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf264ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf265ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf266ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf267ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf268ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf269ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf270ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf271ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf272ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf273ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf274ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf275ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf276ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf277ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf278ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf279ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf281ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf282ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf283ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf284ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf286ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf288ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf290ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf292ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf293_Slot_ae_slot0_set,
+ Field_ftsf294ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf295ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf296ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf297ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf298ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf299ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf300ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf301ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf302ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf303ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf304ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf306ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf308ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf309ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf310ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf311ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf312ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf313ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf314ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf315ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf316ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf317ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf318ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf319_Slot_ae_slot0_set,
+ Field_ftsf320ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf321_Slot_ae_slot0_set,
+ Field_ftsf322ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf323ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf324ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf325ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf326ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf328ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf329ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf352ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf353_Slot_ae_slot0_set,
+ Field_ftsf354ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf356ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf357_Slot_ae_slot0_set,
+ Field_ftsf358ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf359ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf360ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf361ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf362ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf364ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf365ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf366ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf368ae_slot0_Slot_ae_slot0_set,
+ Field_ftsf369ae_slot0_Slot_ae_slot0_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set,
+ Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+ { "Inst", "x24", 0,
+ Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+ Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+ Slot_inst_decode, "nop" },
+ { "Inst16a", "x16a", 0,
+ Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+ Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+ Slot_inst16a_decode, "" },
+ { "Inst16b", "x16b", 0,
+ Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+ Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+ Slot_inst16b_decode, "nop.n" },
+ { "ae_slot1", "ae_format", 1,
+ Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set,
+ Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
+ Slot_ae_slot1_decode, "nop" },
+ { "ae_slot0", "ae_format", 0,
+ Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set,
+ Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
+ Slot_ae_slot0_decode, "nop" }
+};
+
+\f
+/* Instruction formats. */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0;
+ insn[1] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0x8;
+ insn[1] = 0;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xc;
+ insn[1] = 0;
+}
+
+static void
+Format_ae_format_encode (xtensa_insnbuf insn)
+{
+ insn[0] = 0xf;
+ insn[1] = 0;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static int Format_ae_format_slots[] = { 4, 3 };
+
+static xtensa_format_internal formats[] = {
+ { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+ { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+ { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
+ { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+ if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
+ return 0; /* x24 */
+ if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
+ return 1; /* x16a */
+ if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
+ return 2; /* x16b */
+ if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0)
+ return 3; /* ae_format */
+ return -1;
+}
+
+static int length_table[256] = {
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ 8
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+ int l = insn[0];
+ return length_table[l];
+}
+
+\f
+/* Top-level ISA structure. */
+
+xtensa_isa_internal xtensa_modules = {
+ 0 /* little-endian */,
+ 8 /* insn_size */, 0,
+ 4, formats, format_decoder, length_decoder,
+ 5, slots,
+ 389 /* num_fields */,
+ 454, operands,
+ 588, iclasses,
+ 656, opcodes, 0,
+ 8, regfiles,
+ NUM_STATES, states, 0,
+ NUM_SYSREGS, sysregs, 0,
+ { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+ 2, interfaces, 0,
+ 4, funcUnits, 0
+};
+++ /dev/null
-/* Xtensa configuration-specific ISA information.
-
- Copyright (c) 2003-2019 Tensilica Inc.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice shall be included
- in all copies or substantial portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
-#include "xtensa-isa.h"
-#include "xtensa-isa-internal.h"
-
-\f
-/* Sysregs. */
-
-static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "BR", 4, 0 },
- { "PTEVADDR", 83, 0 },
- { "DDR", 104, 0 },
- { "CONFIGID0", 176, 0 },
- { "CONFIGID1", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EPS2", 194, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "LITBASE", 5, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "INTENABLE", 228, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "RASID", 90, 0 },
- { "ITLBCFG", 91, 0 },
- { "DTLBCFG", 92, 0 },
- { "CPENABLE", 224, 0 },
- { "SCOMPARE1", 12, 0 },
- { "ATOMCTL", 99, 0 },
- { "THREADPTR", 231, 1 },
- { "AE_OVF_SAR", 240, 1 },
- { "AE_BITHEAD", 241, 1 },
- { "AE_TS_FTS_BU_BP", 242, 1 },
- { "AE_SD_NO", 243, 1 }
-};
-
-#define NUM_SYSREGS 45
-#define MAX_SPECIAL_REG 245
-#define MAX_USER_REG 243
-
-\f
-/* Processor states. */
-
-static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 12, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EPS2", 15, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSRING", 2, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 3, 0 },
- { "WindowStart", 8, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "THREADPTR", 32, 0 },
- { "LITBADDR", 20, 0 },
- { "LITBEN", 1, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 12, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "ASID3", 8, 0 },
- { "ASID2", 8, 0 },
- { "ASID1", 8, 0 },
- { "INSTPGSZID4", 2, 0 },
- { "DATAPGSZID4", 2, 0 },
- { "PTBASE", 10, 0 },
- { "CPENABLE", 2, 0 },
- { "SCOMPARE1", 32, 0 },
- { "ATOMCTL", 6, 0 },
- { "CCON", 1, XTENSA_STATE_IS_EXPORTED },
- { "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED },
- { "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED },
- { "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED },
- { "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED },
- { "AE_OVERFLOW", 1, 0 },
- { "AE_SAR", 6, 0 },
- { "AE_BITHEAD", 32, 0 },
- { "AE_BITPTR", 4, 0 },
- { "AE_BITSUSED", 4, 0 },
- { "AE_TABLESIZE", 4, 0 },
- { "AE_FIRST_TS", 4, 0 },
- { "AE_NEXTOFFSET", 27, 0 },
- { "AE_SEARCHDONE", 1, 0 }
-};
-
-#define NUM_STATES 63
-
-enum xtensa_state_id {
- STATE_LCOUNT,
- STATE_PC,
- STATE_ICOUNT,
- STATE_DDR,
- STATE_INTERRUPT,
- STATE_CCOUNT,
- STATE_XTSYNC,
- STATE_VECBASE,
- STATE_EPC1,
- STATE_EPC2,
- STATE_EXCSAVE1,
- STATE_EXCSAVE2,
- STATE_EPS2,
- STATE_EXCCAUSE,
- STATE_PSINTLEVEL,
- STATE_PSUM,
- STATE_PSWOE,
- STATE_PSRING,
- STATE_PSEXCM,
- STATE_DEPC,
- STATE_EXCVADDR,
- STATE_WindowBase,
- STATE_WindowStart,
- STATE_PSCALLINC,
- STATE_PSOWB,
- STATE_LBEG,
- STATE_LEND,
- STATE_SAR,
- STATE_THREADPTR,
- STATE_LITBADDR,
- STATE_LITBEN,
- STATE_MISC0,
- STATE_MISC1,
- STATE_InOCDMode,
- STATE_INTENABLE,
- STATE_ICOUNTLEVEL,
- STATE_DEBUGCAUSE,
- STATE_DBNUM,
- STATE_CCOMPARE0,
- STATE_CCOMPARE1,
- STATE_ASID3,
- STATE_ASID2,
- STATE_ASID1,
- STATE_INSTPGSZID4,
- STATE_DATAPGSZID4,
- STATE_PTBASE,
- STATE_CPENABLE,
- STATE_SCOMPARE1,
- STATE_ATOMCTL,
- STATE_CCON,
- STATE_MPSCORE,
- STATE_WMPINT_ADDR,
- STATE_WMPINT_DATA,
- STATE_WMPINT_TOGGLEEN,
- STATE_AE_OVERFLOW,
- STATE_AE_SAR,
- STATE_AE_BITHEAD,
- STATE_AE_BITPTR,
- STATE_AE_BITSUSED,
- STATE_AE_TABLESIZE,
- STATE_AE_FIRST_TS,
- STATE_AE_NEXTOFFSET,
- STATE_AE_SEARCHDONE
-};
-
-\f
-/* Field definitions. */
-
-static unsigned
-Field_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_s_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_n_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_m_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 22) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- tie_t = (val << 23) >> 25;
- insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
- tie_t = (val << 22) >> 25;
- insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
- tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
- tie_t = (val << 21) >> 25;
- insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
- tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x78) | (tie_t << 3);
- tie_t = (val << 21) >> 25;
- insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 21) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 20) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 21) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 24) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 21) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- tie_t = (val << 22) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
- tie_t = (val << 21) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 20) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26);
- return tie_t;
-}
-
-static void
-Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 26) >> 26;
- insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3);
-}
-
-static unsigned
-Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf8) | (tie_t << 3);
-}
-
-static unsigned
-Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val << 25) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
-}
-
-static unsigned
-Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 23) >> 30;
- insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x7c) | (tie_t << 2);
- tie_t = (val << 24) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
- tie_t = (val << 20) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0);
- tie_t = (val << 20) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26);
- return tie_t;
-}
-
-static void
-Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 26) >> 26;
- insn[0] = (insn[0] & ~0x7e) | (tie_t << 1);
- tie_t = (val << 23) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- tie_t = (val << 22) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 22) >> 23;
- insn[0] = (insn[0] & ~0xff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 24) >> 25;
- insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- tie_t = (val << 28) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- tie_t = (val << 26) >> 29;
- insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 26) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 26) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 23) >> 27;
- insn[0] = (insn[0] & ~0xf800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
-}
-
-static unsigned
-Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
- tie_t = (val << 24) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25);
- return tie_t;
-}
-
-static void
-Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20);
-}
-
-static unsigned
-Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
-}
-
-static unsigned
-Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
-}
-
-static unsigned
-Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
-}
-
-static unsigned
-Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
- tie_t = (val << 16) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
- return tie_t;
-}
-
-static void
-Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
- return tie_t;
-}
-
-static void
-Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 26) >> 26;
- insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
- tie_t = (val << 25) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 17) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
- tie_t = (val << 16) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x38) | (tie_t << 3);
- tie_t = (val << 21) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
- tie_t = (val << 27) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0x3c) | (tie_t << 2);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x3e) | (tie_t << 1);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25);
- return tie_t;
-}
-
-static void
-Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 25) >> 25;
- insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13);
-}
-
-static unsigned
-Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19);
- return tie_t;
-}
-
-static void
-Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 19) >> 19;
- insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7);
-}
-
-static unsigned
-Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23);
- return tie_t;
-}
-
-static void
-Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 23) >> 23;
- insn[0] = (insn[0] & ~0xff800) | (tie_t << 11);
-}
-
-static unsigned
-Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
- tie_t = (val << 21) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
- tie_t = (val << 21) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
-}
-
-static unsigned
-Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27);
- return tie_t;
-}
-
-static void
-Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- tie_t = (val << 27) >> 29;
- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
- tie_t = (val << 17) >> 20;
- insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
- return tie_t;
-}
-
-static void
-Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 26) >> 26;
- insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
- tie_t = (val << 18) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
- tie_t = (val << 28) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22);
- return tie_t;
-}
-
-static void
-Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 22) >> 22;
- insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21);
- return tie_t;
-}
-
-static void
-Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 21) >> 21;
- insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
- tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x4) | (tie_t << 2);
- tie_t = (val << 19) >> 20;
- insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
- tie_t = (val << 29) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
-}
-
-static unsigned
-Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
- tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x6) | (tie_t << 1);
- tie_t = (val << 18) >> 20;
- insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- tie_t = (val << 30) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
-}
-
-static unsigned
-Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 23) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
- tie_t = (val << 22) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
-}
-
-static unsigned
-Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20);
- tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7) | (tie_t << 0);
- tie_t = (val << 17) >> 20;
- insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 20) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val << 19) >> 24;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
-}
-
-static unsigned
-Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- return tie_t;
-}
-
-static void
-Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
- return tie_t;
-}
-
-static void
-Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
-}
-
-static unsigned
-Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 24) >> 24;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- tie_t = (val << 20) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
- return tie_t;
-}
-
-static void
-Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 20) >> 20;
- insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
- return tie_t;
-}
-
-static void
-Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 16) >> 16;
- insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
-}
-
-static unsigned
-Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
- return tie_t;
-}
-
-static void
-Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
-}
-
-static unsigned
-Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- return tie_t;
-}
-
-static void
-Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- return tie_t;
-}
-
-static void
-Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
-}
-
-static unsigned
-Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
- return tie_t;
-}
-
-static void
-Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
-}
-
-static unsigned
-Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
- return tie_t;
-}
-
-static void
-Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
-}
-
-static unsigned
-Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- return tie_t;
-}
-
-static void
-Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 27) >> 31;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
-}
-
-static unsigned
-Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
- return tie_t;
-}
-
-static void
-Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 27) >> 27;
- insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
-}
-
-static unsigned
-Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- return tie_t;
-}
-
-static void
-Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
- tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
- return tie_t;
-}
-
-static void
-Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val << 24) >> 28;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
-}
-
-static unsigned
-Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val << 28) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
- return tie_t;
-}
-
-static void
-Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
-}
-
-static unsigned
-Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
- return tie_t;
-}
-
-static void
-Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val << 25) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
-}
-
-static unsigned
-Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 29) >> 30;
- insn[0] = (insn[0] & ~0x180) | (tie_t << 7);
-}
-
-static unsigned
-Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
- return tie_t;
-}
-
-static void
-Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
- return tie_t;
-}
-
-static void
-Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
-}
-
-static unsigned
-Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
- return tie_t;
-}
-
-static void
-Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
-}
-
-static unsigned
-Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
- return tie_t;
-}
-
-static void
-Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
-}
-
-static unsigned
-Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
- return tie_t;
-}
-
-static void
-Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
-}
-
-static unsigned
-Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
- return tie_t;
-}
-
-static void
-Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
-}
-
-static unsigned
-Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
- return tie_t;
-}
-
-static void
-Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
-}
-
-static unsigned
-Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
- return tie_t;
-}
-
-static void
-Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
-}
-
-static unsigned
-Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
- return tie_t;
-}
-
-static void
-Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
-}
-
-static unsigned
-Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
- return tie_t;
-}
-
-static void
-Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 17) >> 17;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
-}
-
-static unsigned
-Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
- return tie_t;
-}
-
-static void
-Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 14) >> 14;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
-}
-
-static unsigned
-Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26);
- return tie_t;
-}
-
-static void
-Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 26) >> 26;
- insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4);
-}
-
-static unsigned
-Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
- tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
- return tie_t;
-}
-
-static void
-Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val << 26) >> 30;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
-}
-
-static unsigned
-Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
-}
-
-static unsigned
-Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
- return tie_t;
-}
-
-static void
-Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
-}
-
-static unsigned
-Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
- return tie_t;
-}
-
-static void
-Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 28) >> 28;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
-}
-
-static unsigned
-Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
- return tie_t;
-}
-
-static void
-Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 29) >> 29;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
- return tie_t;
-}
-
-static void
-Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 30) >> 30;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
-}
-
-static unsigned
-Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn)
-{
- unsigned tie_t = 0;
- tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28);
- tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31);
- return tie_t;
-}
-
-static void
-Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val)
-{
- uint32 tie_t;
- tie_t = (val << 31) >> 31;
- insn[0] = (insn[0] & ~0x8) | (tie_t << 3);
- tie_t = (val << 27) >> 28;
- insn[0] = (insn[0] & ~0x780) | (tie_t << 7);
-}
-
-static void
-Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
-{
- /* Do nothing. */
-}
-
-static unsigned
-Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-static unsigned
-Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 8;
-}
-
-static unsigned
-Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 12;
-}
-
-static unsigned
-Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static unsigned
-Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-enum xtensa_field_id {
- FIELD_t,
- FIELD_bbi4,
- FIELD_bbi,
- FIELD_imm12,
- FIELD_imm8,
- FIELD_s,
- FIELD_imm12b,
- FIELD_imm16,
- FIELD_m,
- FIELD_n,
- FIELD_offset,
- FIELD_op0,
- FIELD_op1,
- FIELD_op2,
- FIELD_r,
- FIELD_sa4,
- FIELD_sae4,
- FIELD_sae,
- FIELD_sal,
- FIELD_sargt,
- FIELD_sas4,
- FIELD_sas,
- FIELD_sr,
- FIELD_st,
- FIELD_thi3,
- FIELD_imm4,
- FIELD_mn,
- FIELD_i,
- FIELD_imm6lo,
- FIELD_imm6hi,
- FIELD_imm7lo,
- FIELD_imm7hi,
- FIELD_z,
- FIELD_imm6,
- FIELD_imm7,
- FIELD_t2,
- FIELD_s2,
- FIELD_r2,
- FIELD_t4,
- FIELD_s4,
- FIELD_r4,
- FIELD_t8,
- FIELD_s8,
- FIELD_r8,
- FIELD_xt_wbr15_imm,
- FIELD_xt_wbr18_imm,
- FIELD_ae_r3,
- FIELD_ae_s_non_samt,
- FIELD_ae_s3,
- FIELD_ae_r32,
- FIELD_ae_samt_s_t,
- FIELD_ae_r20,
- FIELD_ae_r10,
- FIELD_ae_s20,
- FIELD_ae_fld_ohba,
- FIELD_ae_fld_ohba2,
- FIELD_op0_s3,
- FIELD_ftsf12,
- FIELD_ftsf13,
- FIELD_ftsf14,
- FIELD_ftsf21ae_slot1,
- FIELD_ftsf22ae_slot1,
- FIELD_ftsf23ae_slot1,
- FIELD_ftsf24ae_slot1,
- FIELD_ftsf25ae_slot1,
- FIELD_ftsf26ae_slot1,
- FIELD_ftsf27ae_slot1,
- FIELD_ftsf28ae_slot1,
- FIELD_ftsf29ae_slot1,
- FIELD_ftsf30ae_slot1,
- FIELD_ftsf31ae_slot1,
- FIELD_ftsf32ae_slot1,
- FIELD_ftsf33ae_slot1,
- FIELD_ftsf34ae_slot1,
- FIELD_ftsf35ae_slot1,
- FIELD_ftsf36ae_slot1,
- FIELD_ftsf37ae_slot1,
- FIELD_ftsf38ae_slot1,
- FIELD_ftsf39ae_slot1,
- FIELD_ftsf40ae_slot1,
- FIELD_ftsf41ae_slot1,
- FIELD_ftsf42ae_slot1,
- FIELD_ftsf43ae_slot1,
- FIELD_ftsf44ae_slot1,
- FIELD_ftsf45ae_slot1,
- FIELD_ftsf46ae_slot1,
- FIELD_ftsf47ae_slot1,
- FIELD_ftsf48ae_slot1,
- FIELD_ftsf49ae_slot1,
- FIELD_ftsf50ae_slot1,
- FIELD_ftsf51ae_slot1,
- FIELD_ftsf52ae_slot1,
- FIELD_ftsf53ae_slot1,
- FIELD_ftsf54ae_slot1,
- FIELD_ftsf55ae_slot1,
- FIELD_ftsf56ae_slot1,
- FIELD_ftsf57ae_slot1,
- FIELD_ftsf58ae_slot1,
- FIELD_ftsf59ae_slot1,
- FIELD_ftsf60ae_slot1,
- FIELD_ftsf61ae_slot1,
- FIELD_ftsf63ae_slot1,
- FIELD_ftsf64ae_slot1,
- FIELD_ftsf66ae_slot1,
- FIELD_ftsf67ae_slot1,
- FIELD_ftsf69ae_slot1,
- FIELD_ftsf71ae_slot1,
- FIELD_ftsf72ae_slot1,
- FIELD_ftsf73ae_slot1,
- FIELD_ftsf75ae_slot1,
- FIELD_ftsf76ae_slot1,
- FIELD_ftsf77ae_slot1,
- FIELD_ftsf78ae_slot1,
- FIELD_ftsf79ae_slot1,
- FIELD_ftsf80ae_slot1,
- FIELD_ftsf81ae_slot1,
- FIELD_ftsf82ae_slot1,
- FIELD_ftsf84ae_slot1,
- FIELD_ftsf86ae_slot1,
- FIELD_ftsf87ae_slot1,
- FIELD_ftsf88ae_slot1,
- FIELD_ftsf89ae_slot1,
- FIELD_ftsf90ae_slot1,
- FIELD_ftsf91ae_slot1,
- FIELD_ftsf92ae_slot1,
- FIELD_ftsf94ae_slot1,
- FIELD_ftsf96ae_slot1,
- FIELD_ftsf97ae_slot1,
- FIELD_ftsf98ae_slot1,
- FIELD_ftsf99ae_slot1,
- FIELD_ftsf100ae_slot1,
- FIELD_ftsf101ae_slot1,
- FIELD_ftsf103ae_slot1,
- FIELD_ftsf104ae_slot1,
- FIELD_ftsf105ae_slot1,
- FIELD_ftsf106ae_slot1,
- FIELD_ftsf107ae_slot1,
- FIELD_ftsf108ae_slot1,
- FIELD_ftsf109ae_slot1,
- FIELD_ftsf110ae_slot1,
- FIELD_ftsf111ae_slot1,
- FIELD_ftsf112ae_slot1,
- FIELD_ftsf113ae_slot1,
- FIELD_ftsf114ae_slot1,
- FIELD_ftsf115ae_slot1,
- FIELD_ftsf116ae_slot1,
- FIELD_ftsf118ae_slot1,
- FIELD_ftsf119ae_slot1,
- FIELD_ftsf120ae_slot1,
- FIELD_ftsf122ae_slot1,
- FIELD_ftsf124ae_slot1,
- FIELD_ftsf125ae_slot1,
- FIELD_ftsf126ae_slot1,
- FIELD_ftsf127ae_slot1,
- FIELD_ftsf128ae_slot1,
- FIELD_ftsf129ae_slot1,
- FIELD_ftsf130ae_slot1,
- FIELD_ftsf131ae_slot1,
- FIELD_ftsf132ae_slot1,
- FIELD_ftsf133ae_slot1,
- FIELD_ftsf134ae_slot1,
- FIELD_ftsf135ae_slot1,
- FIELD_ftsf136ae_slot1,
- FIELD_ftsf137ae_slot1,
- FIELD_ftsf138ae_slot1,
- FIELD_ftsf139ae_slot1,
- FIELD_ftsf140ae_slot1,
- FIELD_ftsf141ae_slot1,
- FIELD_ftsf142ae_slot1,
- FIELD_ftsf143ae_slot1,
- FIELD_ftsf144ae_slot1,
- FIELD_ftsf145ae_slot1,
- FIELD_ftsf146ae_slot1,
- FIELD_ftsf147ae_slot1,
- FIELD_ftsf148ae_slot1,
- FIELD_ftsf149ae_slot1,
- FIELD_ftsf150ae_slot1,
- FIELD_ftsf151ae_slot1,
- FIELD_ftsf152ae_slot1,
- FIELD_ftsf153ae_slot1,
- FIELD_ftsf154ae_slot1,
- FIELD_ftsf155ae_slot1,
- FIELD_ftsf156ae_slot1,
- FIELD_ftsf157ae_slot1,
- FIELD_ftsf158ae_slot1,
- FIELD_ftsf159ae_slot1,
- FIELD_ftsf160ae_slot1,
- FIELD_ftsf161ae_slot1,
- FIELD_ftsf162ae_slot1,
- FIELD_ftsf163ae_slot1,
- FIELD_ftsf164ae_slot1,
- FIELD_ftsf165ae_slot1,
- FIELD_ftsf166ae_slot1,
- FIELD_ftsf167ae_slot1,
- FIELD_ftsf168ae_slot1,
- FIELD_ftsf169ae_slot1,
- FIELD_ftsf170ae_slot1,
- FIELD_ftsf171ae_slot1,
- FIELD_ftsf172ae_slot1,
- FIELD_ftsf173ae_slot1,
- FIELD_ftsf174ae_slot1,
- FIELD_ftsf175ae_slot1,
- FIELD_ftsf176ae_slot1,
- FIELD_ftsf177ae_slot1,
- FIELD_ftsf178ae_slot1,
- FIELD_ftsf179ae_slot1,
- FIELD_ftsf180ae_slot1,
- FIELD_ftsf181ae_slot1,
- FIELD_ftsf182ae_slot1,
- FIELD_ftsf183ae_slot1,
- FIELD_ftsf184ae_slot1,
- FIELD_ftsf185ae_slot1,
- FIELD_ftsf186ae_slot1,
- FIELD_ftsf187ae_slot1,
- FIELD_ftsf188ae_slot1,
- FIELD_ftsf189ae_slot1,
- FIELD_ftsf190ae_slot1,
- FIELD_ftsf191ae_slot1,
- FIELD_ftsf192ae_slot1,
- FIELD_ftsf193ae_slot1,
- FIELD_ftsf194ae_slot1,
- FIELD_ftsf195ae_slot1,
- FIELD_ftsf196ae_slot1,
- FIELD_ftsf197ae_slot1,
- FIELD_ftsf198ae_slot1,
- FIELD_ftsf199ae_slot1,
- FIELD_ftsf200ae_slot1,
- FIELD_ftsf201ae_slot1,
- FIELD_ftsf202ae_slot1,
- FIELD_ftsf203ae_slot1,
- FIELD_ftsf204ae_slot1,
- FIELD_ftsf205ae_slot1,
- FIELD_ftsf206ae_slot1,
- FIELD_ftsf207ae_slot1,
- FIELD_ftsf208,
- FIELD_ftsf209ae_slot1,
- FIELD_ftsf210ae_slot1,
- FIELD_ftsf211ae_slot1,
- FIELD_ftsf330ae_slot1,
- FIELD_ftsf332ae_slot1,
- FIELD_ftsf334ae_slot1,
- FIELD_ftsf336ae_slot1,
- FIELD_ftsf337ae_slot1,
- FIELD_ftsf338,
- FIELD_ftsf339ae_slot1,
- FIELD_ftsf340,
- FIELD_ftsf341ae_slot1,
- FIELD_ftsf342ae_slot1,
- FIELD_ftsf343ae_slot1,
- FIELD_ftsf344ae_slot1,
- FIELD_ftsf346ae_slot1,
- FIELD_ftsf347,
- FIELD_ftsf348ae_slot1,
- FIELD_ftsf349ae_slot1,
- FIELD_ftsf350ae_slot1,
- FIELD_op0_s4,
- FIELD_ftsf212ae_slot0,
- FIELD_ftsf213ae_slot0,
- FIELD_ftsf214ae_slot0,
- FIELD_ftsf215ae_slot0,
- FIELD_ftsf216ae_slot0,
- FIELD_ftsf217,
- FIELD_ftsf218ae_slot0,
- FIELD_ftsf219ae_slot0,
- FIELD_ftsf220ae_slot0,
- FIELD_ftsf221ae_slot0,
- FIELD_ftsf222ae_slot0,
- FIELD_ftsf223ae_slot0,
- FIELD_ftsf224ae_slot0,
- FIELD_ftsf225ae_slot0,
- FIELD_ftsf226ae_slot0,
- FIELD_ftsf227ae_slot0,
- FIELD_ftsf228ae_slot0,
- FIELD_ftsf229ae_slot0,
- FIELD_ftsf230ae_slot0,
- FIELD_ftsf231ae_slot0,
- FIELD_ftsf232ae_slot0,
- FIELD_ftsf233ae_slot0,
- FIELD_ftsf234ae_slot0,
- FIELD_ftsf235ae_slot0,
- FIELD_ftsf236ae_slot0,
- FIELD_ftsf237ae_slot0,
- FIELD_ftsf238ae_slot0,
- FIELD_ftsf239ae_slot0,
- FIELD_ftsf240ae_slot0,
- FIELD_ftsf241ae_slot0,
- FIELD_ftsf242ae_slot0,
- FIELD_ftsf243ae_slot0,
- FIELD_ftsf244ae_slot0,
- FIELD_ftsf245ae_slot0,
- FIELD_ftsf246ae_slot0,
- FIELD_ftsf247ae_slot0,
- FIELD_ftsf248ae_slot0,
- FIELD_ftsf249ae_slot0,
- FIELD_ftsf250ae_slot0,
- FIELD_ftsf251ae_slot0,
- FIELD_ftsf252ae_slot0,
- FIELD_ftsf253ae_slot0,
- FIELD_ftsf254ae_slot0,
- FIELD_ftsf255ae_slot0,
- FIELD_ftsf256ae_slot0,
- FIELD_ftsf257ae_slot0,
- FIELD_ftsf258ae_slot0,
- FIELD_ftsf259ae_slot0,
- FIELD_ftsf260ae_slot0,
- FIELD_ftsf261ae_slot0,
- FIELD_ftsf262ae_slot0,
- FIELD_ftsf263ae_slot0,
- FIELD_ftsf264ae_slot0,
- FIELD_ftsf265ae_slot0,
- FIELD_ftsf266ae_slot0,
- FIELD_ftsf267ae_slot0,
- FIELD_ftsf268ae_slot0,
- FIELD_ftsf269ae_slot0,
- FIELD_ftsf270ae_slot0,
- FIELD_ftsf271ae_slot0,
- FIELD_ftsf272ae_slot0,
- FIELD_ftsf273ae_slot0,
- FIELD_ftsf274ae_slot0,
- FIELD_ftsf275ae_slot0,
- FIELD_ftsf276ae_slot0,
- FIELD_ftsf277ae_slot0,
- FIELD_ftsf278ae_slot0,
- FIELD_ftsf279ae_slot0,
- FIELD_ftsf281ae_slot0,
- FIELD_ftsf282ae_slot0,
- FIELD_ftsf283ae_slot0,
- FIELD_ftsf284ae_slot0,
- FIELD_ftsf286ae_slot0,
- FIELD_ftsf288ae_slot0,
- FIELD_ftsf290ae_slot0,
- FIELD_ftsf292ae_slot0,
- FIELD_ftsf293,
- FIELD_ftsf294ae_slot0,
- FIELD_ftsf295ae_slot0,
- FIELD_ftsf296ae_slot0,
- FIELD_ftsf297ae_slot0,
- FIELD_ftsf298ae_slot0,
- FIELD_ftsf299ae_slot0,
- FIELD_ftsf300ae_slot0,
- FIELD_ftsf301ae_slot0,
- FIELD_ftsf302ae_slot0,
- FIELD_ftsf303ae_slot0,
- FIELD_ftsf304ae_slot0,
- FIELD_ftsf306ae_slot0,
- FIELD_ftsf308ae_slot0,
- FIELD_ftsf309ae_slot0,
- FIELD_ftsf310ae_slot0,
- FIELD_ftsf311ae_slot0,
- FIELD_ftsf312ae_slot0,
- FIELD_ftsf313ae_slot0,
- FIELD_ftsf314ae_slot0,
- FIELD_ftsf315ae_slot0,
- FIELD_ftsf316ae_slot0,
- FIELD_ftsf317ae_slot0,
- FIELD_ftsf318ae_slot0,
- FIELD_ftsf319,
- FIELD_ftsf320ae_slot0,
- FIELD_ftsf321,
- FIELD_ftsf322ae_slot0,
- FIELD_ftsf323ae_slot0,
- FIELD_ftsf324ae_slot0,
- FIELD_ftsf325ae_slot0,
- FIELD_ftsf326ae_slot0,
- FIELD_ftsf328ae_slot0,
- FIELD_ftsf329ae_slot0,
- FIELD_ftsf352ae_slot0,
- FIELD_ftsf353,
- FIELD_ftsf354ae_slot0,
- FIELD_ftsf356ae_slot0,
- FIELD_ftsf357,
- FIELD_ftsf358ae_slot0,
- FIELD_ftsf359ae_slot0,
- FIELD_ftsf360ae_slot0,
- FIELD_ftsf361ae_slot0,
- FIELD_ftsf362ae_slot0,
- FIELD_ftsf364ae_slot0,
- FIELD_ftsf365ae_slot0,
- FIELD_ftsf366ae_slot0,
- FIELD_ftsf368ae_slot0,
- FIELD_ftsf369ae_slot0,
- FIELD__ar0,
- FIELD__ar4,
- FIELD__ar8,
- FIELD__ar12,
- FIELD__bt16,
- FIELD__bs16,
- FIELD__br16,
- FIELD__brall
-};
-
-\f
-/* Functional units. */
-
-static xtensa_funcUnit_internal funcUnits[] = {
- { "ae_add32", 1 },
- { "ae_shift32x4", 1 },
- { "ae_shift32x5", 1 },
- { "ae_subshift", 1 }
-};
-
-enum xtensa_funcUnit_id {
- FUNCUNIT_ae_add32,
- FUNCUNIT_ae_shift32x4,
- FUNCUNIT_ae_shift32x5,
- FUNCUNIT_ae_subshift
-};
-
-\f
-/* Register files. */
-
-enum xtensa_regfile_id {
- REGFILE_AR,
- REGFILE_BR,
- REGFILE_AE_PR,
- REGFILE_AE_QR,
- REGFILE_BR2,
- REGFILE_BR4,
- REGFILE_BR8,
- REGFILE_BR16
-};
-
-static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", REGFILE_AR, 32, 32 },
- { "BR", "b", REGFILE_BR, 1, 16 },
- { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 },
- { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 },
- { "BR2", "b", REGFILE_BR, 2, 8 },
- { "BR4", "b", REGFILE_BR, 4, 4 },
- { "BR8", "b", REGFILE_BR, 8, 2 },
- { "BR16", "b", REGFILE_BR, 16, 1 }
-};
-
-\f
-/* Interfaces. */
-
-static xtensa_interface_internal interfaces[] = {
- { "RMPINT_Out", 12, 0, 0, 'o' },
- { "RMPINT_In", 32, 0, 1, 'i' }
-};
-
-enum xtensa_interface_id {
- INTERFACE_RMPINT_Out,
- INTERFACE_RMPINT_In
-};
-
-
-/* Constant tables. */
-
-/* constant table ai4c */
-static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
-};
-
-/* constant table b4c */
-static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-/* constant table b4cu */
-static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
-};
-
-\f
-/* Instruction operands. */
-
-static int
-OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
-{
- unsigned soffsetx4_out_0;
- unsigned soffsetx4_in_0;
- soffsetx4_in_0 = *valp & 0x3ffff;
- soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
- *valp = soffsetx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
-{
- unsigned soffsetx4_in_0;
- unsigned soffsetx4_out_0;
- soffsetx4_out_0 = *valp;
- soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
- *valp = soffsetx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
-{
- unsigned uimm12x8_out_0;
- unsigned uimm12x8_in_0;
- uimm12x8_in_0 = *valp & 0xfff;
- uimm12x8_out_0 = uimm12x8_in_0 << 3;
- *valp = uimm12x8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
-{
- unsigned uimm12x8_in_0;
- unsigned uimm12x8_out_0;
- uimm12x8_out_0 = *valp;
- uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
- *valp = uimm12x8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_decode (uint32 *valp)
-{
- unsigned simm4_out_0;
- unsigned simm4_in_0;
- simm4_in_0 = *valp & 0xf;
- simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
- *valp = simm4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm4_encode (uint32 *valp)
-{
- unsigned simm4_in_0;
- unsigned simm4_out_0;
- simm4_out_0 = *valp;
- simm4_in_0 = (simm4_out_0 & 0xf);
- *valp = simm4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 32);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
-{
- unsigned immrx4_out_0;
- unsigned immrx4_in_0;
- immrx4_in_0 = *valp & 0xf;
- immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
- *valp = immrx4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
-{
- unsigned immrx4_in_0;
- unsigned immrx4_out_0;
- immrx4_out_0 = *valp;
- immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
- *valp = immrx4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
-{
- unsigned lsi4x4_out_0;
- unsigned lsi4x4_in_0;
- lsi4x4_in_0 = *valp & 0xf;
- lsi4x4_out_0 = lsi4x4_in_0 << 2;
- *valp = lsi4x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
-{
- unsigned lsi4x4_in_0;
- unsigned lsi4x4_out_0;
- lsi4x4_out_0 = *valp;
- lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
- *valp = lsi4x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_decode (uint32 *valp)
-{
- unsigned simm7_out_0;
- unsigned simm7_in_0;
- simm7_in_0 = *valp & 0x7f;
- simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
- *valp = simm7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm7_encode (uint32 *valp)
-{
- unsigned simm7_in_0;
- unsigned simm7_out_0;
- simm7_out_0 = *valp;
- simm7_in_0 = (simm7_out_0 & 0x7f);
- *valp = simm7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
-{
- unsigned uimm6_out_0;
- unsigned uimm6_in_0;
- uimm6_in_0 = *valp & 0x3f;
- uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
- *valp = uimm6_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
-{
- unsigned uimm6_in_0;
- unsigned uimm6_out_0;
- uimm6_out_0 = *valp;
- uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
- *valp = uimm6_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
-{
- unsigned ai4const_out_0;
- unsigned ai4const_in_0;
- ai4const_in_0 = *valp & 0xf;
- ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
- *valp = ai4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
-{
- unsigned ai4const_in_0;
- unsigned ai4const_out_0;
- ai4const_out_0 = *valp;
- switch (ai4const_out_0)
- {
- case 0xffffffff: ai4const_in_0 = 0; break;
- case 0x1: ai4const_in_0 = 0x1; break;
- case 0x2: ai4const_in_0 = 0x2; break;
- case 0x3: ai4const_in_0 = 0x3; break;
- case 0x4: ai4const_in_0 = 0x4; break;
- case 0x5: ai4const_in_0 = 0x5; break;
- case 0x6: ai4const_in_0 = 0x6; break;
- case 0x7: ai4const_in_0 = 0x7; break;
- case 0x8: ai4const_in_0 = 0x8; break;
- case 0x9: ai4const_in_0 = 0x9; break;
- case 0xa: ai4const_in_0 = 0xa; break;
- case 0xb: ai4const_in_0 = 0xb; break;
- case 0xc: ai4const_in_0 = 0xc; break;
- case 0xd: ai4const_in_0 = 0xd; break;
- case 0xe: ai4const_in_0 = 0xe; break;
- default: ai4const_in_0 = 0xf; break;
- }
- *valp = ai4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_decode (uint32 *valp)
-{
- unsigned b4const_out_0;
- unsigned b4const_in_0;
- b4const_in_0 = *valp & 0xf;
- b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
- *valp = b4const_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4const_encode (uint32 *valp)
-{
- unsigned b4const_in_0;
- unsigned b4const_out_0;
- b4const_out_0 = *valp;
- switch (b4const_out_0)
- {
- case 0xffffffff: b4const_in_0 = 0; break;
- case 0x1: b4const_in_0 = 0x1; break;
- case 0x2: b4const_in_0 = 0x2; break;
- case 0x3: b4const_in_0 = 0x3; break;
- case 0x4: b4const_in_0 = 0x4; break;
- case 0x5: b4const_in_0 = 0x5; break;
- case 0x6: b4const_in_0 = 0x6; break;
- case 0x7: b4const_in_0 = 0x7; break;
- case 0x8: b4const_in_0 = 0x8; break;
- case 0xa: b4const_in_0 = 0x9; break;
- case 0xc: b4const_in_0 = 0xa; break;
- case 0x10: b4const_in_0 = 0xb; break;
- case 0x20: b4const_in_0 = 0xc; break;
- case 0x40: b4const_in_0 = 0xd; break;
- case 0x80: b4const_in_0 = 0xe; break;
- default: b4const_in_0 = 0xf; break;
- }
- *valp = b4const_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
-{
- unsigned b4constu_out_0;
- unsigned b4constu_in_0;
- b4constu_in_0 = *valp & 0xf;
- b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
- *valp = b4constu_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
-{
- unsigned b4constu_in_0;
- unsigned b4constu_out_0;
- b4constu_out_0 = *valp;
- switch (b4constu_out_0)
- {
- case 0x8000: b4constu_in_0 = 0; break;
- case 0x10000: b4constu_in_0 = 0x1; break;
- case 0x2: b4constu_in_0 = 0x2; break;
- case 0x3: b4constu_in_0 = 0x3; break;
- case 0x4: b4constu_in_0 = 0x4; break;
- case 0x5: b4constu_in_0 = 0x5; break;
- case 0x6: b4constu_in_0 = 0x6; break;
- case 0x7: b4constu_in_0 = 0x7; break;
- case 0x8: b4constu_in_0 = 0x8; break;
- case 0xa: b4constu_in_0 = 0x9; break;
- case 0xc: b4constu_in_0 = 0xa; break;
- case 0x10: b4constu_in_0 = 0xb; break;
- case 0x20: b4constu_in_0 = 0xc; break;
- case 0x40: b4constu_in_0 = 0xd; break;
- case 0x80: b4constu_in_0 = 0xe; break;
- default: b4constu_in_0 = 0xf; break;
- }
- *valp = b4constu_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
-{
- unsigned uimm8_out_0;
- unsigned uimm8_in_0;
- uimm8_in_0 = *valp & 0xff;
- uimm8_out_0 = uimm8_in_0;
- *valp = uimm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
-{
- unsigned uimm8_in_0;
- unsigned uimm8_out_0;
- uimm8_out_0 = *valp;
- uimm8_in_0 = (uimm8_out_0 & 0xff);
- *valp = uimm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
-{
- unsigned uimm8x2_out_0;
- unsigned uimm8x2_in_0;
- uimm8x2_in_0 = *valp & 0xff;
- uimm8x2_out_0 = uimm8x2_in_0 << 1;
- *valp = uimm8x2_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
-{
- unsigned uimm8x2_in_0;
- unsigned uimm8x2_out_0;
- uimm8x2_out_0 = *valp;
- uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
- *valp = uimm8x2_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
-{
- unsigned uimm8x4_out_0;
- unsigned uimm8x4_in_0;
- uimm8x4_in_0 = *valp & 0xff;
- uimm8x4_out_0 = uimm8x4_in_0 << 2;
- *valp = uimm8x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
-{
- unsigned uimm8x4_in_0;
- unsigned uimm8x4_out_0;
- uimm8x4_out_0 = *valp;
- uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
- *valp = uimm8x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
-{
- unsigned uimm4x16_out_0;
- unsigned uimm4x16_in_0;
- uimm4x16_in_0 = *valp & 0xf;
- uimm4x16_out_0 = uimm4x16_in_0 << 4;
- *valp = uimm4x16_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
-{
- unsigned uimm4x16_in_0;
- unsigned uimm4x16_out_0;
- uimm4x16_out_0 = *valp;
- uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
- *valp = uimm4x16_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_decode (uint32 *valp)
-{
- unsigned simm8_out_0;
- unsigned simm8_in_0;
- simm8_in_0 = *valp & 0xff;
- simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
- *valp = simm8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8_encode (uint32 *valp)
-{
- unsigned simm8_in_0;
- unsigned simm8_out_0;
- simm8_out_0 = *valp;
- simm8_in_0 = (simm8_out_0 & 0xff);
- *valp = simm8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
-{
- unsigned simm8x256_out_0;
- unsigned simm8x256_in_0;
- simm8x256_in_0 = *valp & 0xff;
- simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
- *valp = simm8x256_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
-{
- unsigned simm8x256_in_0;
- unsigned simm8x256_out_0;
- simm8x256_out_0 = *valp;
- simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
- *valp = simm8x256_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
-{
- unsigned simm12b_out_0;
- unsigned simm12b_in_0;
- simm12b_in_0 = *valp & 0xfff;
- simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
- *valp = simm12b_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
-{
- unsigned simm12b_in_0;
- unsigned simm12b_out_0;
- simm12b_out_0 = *valp;
- simm12b_in_0 = (simm12b_out_0 & 0xfff);
- *valp = simm12b_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
-{
- unsigned msalp32_out_0;
- unsigned msalp32_in_0;
- msalp32_in_0 = *valp & 0x1f;
- msalp32_out_0 = 0x20 - msalp32_in_0;
- *valp = msalp32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
-{
- unsigned msalp32_in_0;
- unsigned msalp32_out_0;
- msalp32_out_0 = *valp;
- msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
- *valp = msalp32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
-{
- unsigned op2p1_out_0;
- unsigned op2p1_in_0;
- op2p1_in_0 = *valp & 0xf;
- op2p1_out_0 = op2p1_in_0 + 0x1;
- *valp = op2p1_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
-{
- unsigned op2p1_in_0;
- unsigned op2p1_out_0;
- op2p1_out_0 = *valp;
- op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
- *valp = op2p1_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_decode (uint32 *valp)
-{
- unsigned label8_out_0;
- unsigned label8_in_0;
- label8_in_0 = *valp & 0xff;
- label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
- *valp = label8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label8_encode (uint32 *valp)
-{
- unsigned label8_in_0;
- unsigned label8_out_0;
- label8_out_0 = *valp;
- label8_in_0 = (label8_out_0 - 0x4) & 0xff;
- *valp = label8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
-{
- unsigned ulabel8_out_0;
- unsigned ulabel8_in_0;
- ulabel8_in_0 = *valp & 0xff;
- ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
- *valp = ulabel8_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
-{
- unsigned ulabel8_in_0;
- unsigned ulabel8_out_0;
- ulabel8_out_0 = *valp;
- ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
- *valp = ulabel8_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_decode (uint32 *valp)
-{
- unsigned label12_out_0;
- unsigned label12_in_0;
- label12_in_0 = *valp & 0xfff;
- label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
- *valp = label12_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_label12_encode (uint32 *valp)
-{
- unsigned label12_in_0;
- unsigned label12_out_0;
- label12_out_0 = *valp;
- label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
- *valp = label12_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_decode (uint32 *valp)
-{
- unsigned soffset_out_0;
- unsigned soffset_in_0;
- soffset_in_0 = *valp & 0x3ffff;
- soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
- *valp = soffset_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_soffset_encode (uint32 *valp)
-{
- unsigned soffset_in_0;
- unsigned soffset_out_0;
- soffset_out_0 = *valp;
- soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
- *valp = soffset_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
-{
- unsigned uimm16x4_out_0;
- unsigned uimm16x4_in_0;
- uimm16x4_in_0 = *valp & 0xffff;
- uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
- *valp = uimm16x4_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
-{
- unsigned uimm16x4_in_0;
- unsigned uimm16x4_out_0;
- uimm16x4_out_0 = *valp;
- uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
- *valp = uimm16x4_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_decode (uint32 *valp)
-{
- unsigned bbi_out_0;
- unsigned bbi_in_0;
- bbi_in_0 = *valp & 0x1f;
- bbi_out_0 = (0 << 5) | bbi_in_0;
- *valp = bbi_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_bbi_encode (uint32 *valp)
-{
- unsigned bbi_in_0;
- unsigned bbi_out_0;
- bbi_out_0 = *valp;
- bbi_in_0 = (bbi_out_0 & 0x1f);
- *valp = bbi_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_decode (uint32 *valp)
-{
- unsigned s_out_0;
- unsigned s_in_0;
- s_in_0 = *valp & 0xf;
- s_out_0 = (0 << 4) | s_in_0;
- *valp = s_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_s_encode (uint32 *valp)
-{
- unsigned s_in_0;
- unsigned s_out_0;
- s_out_0 = *valp;
- s_in_0 = (s_out_0 & 0xf);
- *valp = s_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immt_decode (uint32 *valp)
-{
- unsigned immt_out_0;
- unsigned immt_in_0;
- immt_in_0 = *valp & 0xf;
- immt_out_0 = immt_in_0;
- *valp = immt_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_immt_encode (uint32 *valp)
-{
- unsigned immt_in_0;
- unsigned immt_out_0;
- immt_out_0 = *valp;
- immt_in_0 = immt_out_0 & 0xf;
- *valp = immt_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR2_decode (uint32 *valp)
-{
- *valp = *valp << 1;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR2_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 1) != 0);
- *valp = *valp >> 1;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR4_decode (uint32 *valp)
-{
- *valp = *valp << 2;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR4_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 3) != 0);
- *valp = *valp >> 2;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR8_decode (uint32 *valp)
-{
- *valp = *valp << 3;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR8_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 7) != 0);
- *valp = *valp >> 3;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_BR16_decode (uint32 *valp)
-{
- *valp = *valp << 4;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_BR16_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 16) || ((*valp & 15) != 0);
- *valp = *valp >> 4;
- return error;
-}
-
-static int
-OperandSem_opnd_sem_tp7_decode (uint32 *valp)
-{
- unsigned tp7_out_0;
- unsigned tp7_in_0;
- tp7_in_0 = *valp & 0xf;
- tp7_out_0 = tp7_in_0 + 0x7;
- *valp = tp7_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_tp7_encode (uint32 *valp)
-{
- unsigned tp7_in_0;
- unsigned tp7_out_0;
- tp7_out_0 = *valp;
- tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
- *valp = tp7_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
-{
- unsigned xt_wbr15_label_out_0;
- unsigned xt_wbr15_label_in_0;
- xt_wbr15_label_in_0 = *valp & 0x7fff;
- xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
- *valp = xt_wbr15_label_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
-{
- unsigned xt_wbr15_label_in_0;
- unsigned xt_wbr15_label_out_0;
- xt_wbr15_label_out_0 = *valp;
- xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_label_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
-{
- unsigned ae_samt32_out_0;
- unsigned ae_samt32_in_0;
- ae_samt32_in_0 = *valp & 0x1f;
- ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
- *valp = ae_samt32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
-{
- unsigned ae_samt32_in_0;
- unsigned ae_samt32_out_0;
- ae_samt32_out_0 = *valp;
- ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
- *valp = ae_samt32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 8);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
-{
- int error;
- error = (*valp >= 4);
- return error;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
-{
- unsigned ae_lsimm16_out_0;
- unsigned ae_lsimm16_in_0;
- ae_lsimm16_in_0 = *valp & 0xf;
- ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
- *valp = ae_lsimm16_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
-{
- unsigned ae_lsimm16_in_0;
- unsigned ae_lsimm16_out_0;
- ae_lsimm16_out_0 = *valp;
- ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
- *valp = ae_lsimm16_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
-{
- unsigned ae_lsimm32_out_0;
- unsigned ae_lsimm32_in_0;
- ae_lsimm32_in_0 = *valp & 0xf;
- ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
- *valp = ae_lsimm32_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
-{
- unsigned ae_lsimm32_in_0;
- unsigned ae_lsimm32_out_0;
- ae_lsimm32_out_0 = *valp;
- ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
- *valp = ae_lsimm32_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
-{
- unsigned ae_lsimm64_out_0;
- unsigned ae_lsimm64_in_0;
- ae_lsimm64_in_0 = *valp & 0xf;
- ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
- *valp = ae_lsimm64_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
-{
- unsigned ae_lsimm64_in_0;
- unsigned ae_lsimm64_out_0;
- ae_lsimm64_out_0 = *valp;
- ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
- *valp = ae_lsimm64_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
-{
- unsigned ae_samt64_out_0;
- unsigned ae_samt64_in_0;
- ae_samt64_in_0 = *valp & 0x3f;
- ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
- *valp = ae_samt64_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
-{
- unsigned ae_samt64_in_0;
- unsigned ae_samt64_out_0;
- ae_samt64_out_0 = *valp;
- ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
- *valp = ae_samt64_in_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
-{
- unsigned ae_ohba_out_0;
- unsigned ae_ohba_in_0;
- ae_ohba_in_0 = *valp & 0xf;
- ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
- *valp = ae_ohba_out_0;
- return 0;
-}
-
-static int
-OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
-{
- unsigned ae_ohba_in_0;
- unsigned ae_ohba_out_0;
- ae_ohba_out_0 = *valp;
- ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
- *valp = ae_ohba_in_0;
- return 0;
-}
-
-static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += (pc & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_label12_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_label12_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_soffset_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_soffset_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
-{
- *valp -= ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += ((pc + 3) & ~0x3);
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
-{
- *valp -= pc;
- return 0;
-}
-
-static int
-Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
-{
- *valp += pc;
- return 0;
-}
-
-static xtensa_operand_internal operands[] = {
- { "soffsetx4", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", FIELD_imm12, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
- 0, 0 },
- { "simm4", FIELD_mn, -1, 0,
- 0,
- OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
- 0, 0 },
- { "arr", FIELD_r, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ars", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "art", FIELD_t, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
- 0, 0 },
- { "ar0", FIELD__ar0, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
- 0, 0 },
- { "ar4", FIELD__ar4, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
- 0, 0 },
- { "ar8", FIELD__ar8, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
- 0, 0 },
- { "ar12", FIELD__ar12, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
- 0, 0 },
- { "ars_entry", FIELD_s, REGFILE_AR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
- 0, 0 },
- { "immrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
- 0, 0 },
- { "lsi4x4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
- 0, 0 },
- { "simm7", FIELD_imm7, -1, 0,
- 0,
- OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
- 0, 0 },
- { "uimm6", FIELD_imm6, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
- 0, 0 },
- { "b4const", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
- 0, 0 },
- { "b4constu", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
- 0, 0 },
- { "uimm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
- 0, 0 },
- { "uimm8x2", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
- 0, 0 },
- { "uimmrx4", FIELD_r, -1, 0,
- 0,
- OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
- 0, 0 },
- { "simm8", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
- 0, 0 },
- { "simm8x256", FIELD_imm8, -1, 0,
- 0,
- OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
- 0, 0 },
- { "simm12b", FIELD_imm12b, -1, 0,
- 0,
- OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
- 0, 0 },
- { "msalp32", FIELD_sal, -1, 0,
- 0,
- OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
- 0, 0 },
- { "op2p1", FIELD_op2, -1, 0,
- 0,
- OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
- 0, 0 },
- { "label8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", FIELD_imm8, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", FIELD_imm12, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", FIELD_offset, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", FIELD_imm16, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "bbi", FIELD_bbi, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sae", FIELD_sae, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sas", FIELD_sas, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "sargt", FIELD_sargt, -1, 0,
- 0,
- OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
- 0, 0 },
- { "s", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
- 0, 0 },
- { "immt", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "imms", FIELD_s, -1, 0,
- 0,
- OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
- 0, 0 },
- { "bt", FIELD_t, REGFILE_BR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
- 0, 0 },
- { "bs", FIELD_s, REGFILE_BR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
- 0, 0 },
- { "br", FIELD_r, REGFILE_BR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
- 0, 0 },
- { "bt2", FIELD_t2, REGFILE_BR, 2,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
- 0, 0 },
- { "bs2", FIELD_s2, REGFILE_BR, 2,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
- 0, 0 },
- { "br2", FIELD_r2, REGFILE_BR, 2,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
- 0, 0 },
- { "bt4", FIELD_t4, REGFILE_BR, 4,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
- 0, 0 },
- { "bs4", FIELD_s4, REGFILE_BR, 4,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
- 0, 0 },
- { "br4", FIELD_r4, REGFILE_BR, 4,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
- 0, 0 },
- { "bt8", FIELD_t8, REGFILE_BR, 8,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
- 0, 0 },
- { "bs8", FIELD_s8, REGFILE_BR, 8,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
- 0, 0 },
- { "br8", FIELD_r8, REGFILE_BR, 8,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
- 0, 0 },
- { "bt16", FIELD__bt16, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "bs16", FIELD__bs16, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "br16", FIELD__br16, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "brall", FIELD__brall, REGFILE_BR, 16,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
- 0, 0 },
- { "tp7", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "ae_samt32", FIELD_ftsf14, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
- 0, 0 },
- { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "ae_lsimm16", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
- 0, 0 },
- { "ae_lsimm32", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
- 0, 0 },
- { "ae_lsimm64", FIELD_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
- 0, 0 },
- { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
- 0, 0 },
- { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
- 0, 0 },
- { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
- 0,
- OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
- 0, 0 },
- { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
- 0, 0 },
- { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
- XTENSA_OPERAND_IS_REGISTER,
- OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
- 0, 0 },
- { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
- { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
- { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
- { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
- { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
- { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
- { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
- { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
- { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
- { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
- { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
- { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
- { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
- { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
- { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
- { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
- { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf208", FIELD_ftsf208, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf338", FIELD_ftsf338, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf340", FIELD_ftsf340, -1, 0, 0, 0, 0, 0, 0 },
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- { "ftsf347", FIELD_ftsf347, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf216ae_slot0", FIELD_ftsf216ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf217", FIELD_ftsf217, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 },
- { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 }
-};
-
-enum xtensa_operand_id {
- OPERAND_soffsetx4,
- OPERAND_uimm12x8,
- OPERAND_simm4,
- OPERAND_arr,
- OPERAND_ars,
- OPERAND__ars_invisible,
- OPERAND_art,
- OPERAND_ar0,
- OPERAND_ar4,
- OPERAND_ar8,
- OPERAND_ar12,
- OPERAND_ars_entry,
- OPERAND_immrx4,
- OPERAND_lsi4x4,
- OPERAND_simm7,
- OPERAND_uimm6,
- OPERAND_ai4const,
- OPERAND_b4const,
- OPERAND_b4constu,
- OPERAND_uimm8,
- OPERAND_uimm8x2,
- OPERAND_uimm8x4,
- OPERAND_uimm4x16,
- OPERAND_uimmrx4,
- OPERAND_simm8,
- OPERAND_simm8x256,
- OPERAND_simm12b,
- OPERAND_msalp32,
- OPERAND_op2p1,
- OPERAND_label8,
- OPERAND_ulabel8,
- OPERAND_label12,
- OPERAND_soffset,
- OPERAND_uimm16x4,
- OPERAND_bbi,
- OPERAND_sae,
- OPERAND_sas,
- OPERAND_sargt,
- OPERAND_s,
- OPERAND_immt,
- OPERAND_imms,
- OPERAND_bt,
- OPERAND_bs,
- OPERAND_br,
- OPERAND_bt2,
- OPERAND_bs2,
- OPERAND_br2,
- OPERAND_bt4,
- OPERAND_bs4,
- OPERAND_br4,
- OPERAND_bt8,
- OPERAND_bs8,
- OPERAND_br8,
- OPERAND_bt16,
- OPERAND_bs16,
- OPERAND_br16,
- OPERAND_brall,
- OPERAND_tp7,
- OPERAND_xt_wbr15_label,
- OPERAND_xt_wbr18_label,
- OPERAND_ae_samt32,
- OPERAND_pr0,
- OPERAND_qr0,
- OPERAND_mac_qr0,
- OPERAND_ae_lsimm16,
- OPERAND_ae_lsimm32,
- OPERAND_ae_lsimm64,
- OPERAND_ae_samt64,
- OPERAND_ae_ohba,
- OPERAND_ae_ohba2,
- OPERAND_pr,
- OPERAND_cvt_pr,
- OPERAND_qr0_rw,
- OPERAND_mac_qr0_rw,
- OPERAND_qr1_w,
- OPERAND_mac_qr1_w,
- OPERAND_ps,
- OPERAND_alupppb_ps,
- OPERAND_t,
- OPERAND_bbi4,
- OPERAND_imm12,
- OPERAND_imm8,
- OPERAND_imm12b,
- OPERAND_imm16,
- OPERAND_m,
- OPERAND_n,
- OPERAND_offset,
- OPERAND_op0,
- OPERAND_op1,
- OPERAND_op2,
- OPERAND_r,
- OPERAND_sa4,
- OPERAND_sae4,
- OPERAND_sal,
- OPERAND_sas4,
- OPERAND_sr,
- OPERAND_st,
- OPERAND_thi3,
- OPERAND_imm4,
- OPERAND_mn,
- OPERAND_i,
- OPERAND_imm6lo,
- OPERAND_imm6hi,
- OPERAND_imm7lo,
- OPERAND_imm7hi,
- OPERAND_z,
- OPERAND_imm6,
- OPERAND_imm7,
- OPERAND_t2,
- OPERAND_s2,
- OPERAND_r2,
- OPERAND_t4,
- OPERAND_s4,
- OPERAND_r4,
- OPERAND_t8,
- OPERAND_s8,
- OPERAND_r8,
- OPERAND_xt_wbr15_imm,
- OPERAND_xt_wbr18_imm,
- OPERAND_ae_r3,
- OPERAND_ae_s_non_samt,
- OPERAND_ae_s3,
- OPERAND_ae_r32,
- OPERAND_ae_samt_s_t,
- OPERAND_ae_r20,
- OPERAND_ae_r10,
- OPERAND_ae_s20,
- OPERAND_ae_fld_ohba,
- OPERAND_ae_fld_ohba2,
- OPERAND_op0_s3,
- OPERAND_ftsf12,
- OPERAND_ftsf13,
- OPERAND_ftsf14,
- OPERAND_ftsf21ae_slot1,
- OPERAND_ftsf22ae_slot1,
- OPERAND_ftsf23ae_slot1,
- OPERAND_ftsf24ae_slot1,
- OPERAND_ftsf25ae_slot1,
- OPERAND_ftsf26ae_slot1,
- OPERAND_ftsf27ae_slot1,
- OPERAND_ftsf28ae_slot1,
- OPERAND_ftsf29ae_slot1,
- OPERAND_ftsf30ae_slot1,
- OPERAND_ftsf31ae_slot1,
- OPERAND_ftsf32ae_slot1,
- OPERAND_ftsf33ae_slot1,
- OPERAND_ftsf34ae_slot1,
- OPERAND_ftsf35ae_slot1,
- OPERAND_ftsf36ae_slot1,
- OPERAND_ftsf37ae_slot1,
- OPERAND_ftsf38ae_slot1,
- OPERAND_ftsf39ae_slot1,
- OPERAND_ftsf40ae_slot1,
- OPERAND_ftsf41ae_slot1,
- OPERAND_ftsf42ae_slot1,
- OPERAND_ftsf43ae_slot1,
- OPERAND_ftsf44ae_slot1,
- OPERAND_ftsf45ae_slot1,
- OPERAND_ftsf46ae_slot1,
- OPERAND_ftsf47ae_slot1,
- OPERAND_ftsf48ae_slot1,
- OPERAND_ftsf49ae_slot1,
- OPERAND_ftsf50ae_slot1,
- OPERAND_ftsf51ae_slot1,
- OPERAND_ftsf52ae_slot1,
- OPERAND_ftsf53ae_slot1,
- OPERAND_ftsf54ae_slot1,
- OPERAND_ftsf55ae_slot1,
- OPERAND_ftsf56ae_slot1,
- OPERAND_ftsf57ae_slot1,
- OPERAND_ftsf58ae_slot1,
- OPERAND_ftsf59ae_slot1,
- OPERAND_ftsf60ae_slot1,
- OPERAND_ftsf61ae_slot1,
- OPERAND_ftsf63ae_slot1,
- OPERAND_ftsf64ae_slot1,
- OPERAND_ftsf66ae_slot1,
- OPERAND_ftsf67ae_slot1,
- OPERAND_ftsf69ae_slot1,
- OPERAND_ftsf71ae_slot1,
- OPERAND_ftsf72ae_slot1,
- OPERAND_ftsf73ae_slot1,
- OPERAND_ftsf75ae_slot1,
- OPERAND_ftsf76ae_slot1,
- OPERAND_ftsf77ae_slot1,
- OPERAND_ftsf78ae_slot1,
- OPERAND_ftsf79ae_slot1,
- OPERAND_ftsf80ae_slot1,
- OPERAND_ftsf81ae_slot1,
- OPERAND_ftsf82ae_slot1,
- OPERAND_ftsf84ae_slot1,
- OPERAND_ftsf86ae_slot1,
- OPERAND_ftsf87ae_slot1,
- OPERAND_ftsf88ae_slot1,
- OPERAND_ftsf89ae_slot1,
- OPERAND_ftsf90ae_slot1,
- OPERAND_ftsf91ae_slot1,
- OPERAND_ftsf92ae_slot1,
- OPERAND_ftsf94ae_slot1,
- OPERAND_ftsf96ae_slot1,
- OPERAND_ftsf97ae_slot1,
- OPERAND_ftsf98ae_slot1,
- OPERAND_ftsf99ae_slot1,
- OPERAND_ftsf100ae_slot1,
- OPERAND_ftsf101ae_slot1,
- OPERAND_ftsf103ae_slot1,
- OPERAND_ftsf104ae_slot1,
- OPERAND_ftsf105ae_slot1,
- OPERAND_ftsf106ae_slot1,
- OPERAND_ftsf107ae_slot1,
- OPERAND_ftsf108ae_slot1,
- OPERAND_ftsf109ae_slot1,
- OPERAND_ftsf110ae_slot1,
- OPERAND_ftsf111ae_slot1,
- OPERAND_ftsf112ae_slot1,
- OPERAND_ftsf113ae_slot1,
- OPERAND_ftsf114ae_slot1,
- OPERAND_ftsf115ae_slot1,
- OPERAND_ftsf116ae_slot1,
- OPERAND_ftsf118ae_slot1,
- OPERAND_ftsf119ae_slot1,
- OPERAND_ftsf120ae_slot1,
- OPERAND_ftsf122ae_slot1,
- OPERAND_ftsf124ae_slot1,
- OPERAND_ftsf125ae_slot1,
- OPERAND_ftsf126ae_slot1,
- OPERAND_ftsf127ae_slot1,
- OPERAND_ftsf128ae_slot1,
- OPERAND_ftsf129ae_slot1,
- OPERAND_ftsf130ae_slot1,
- OPERAND_ftsf131ae_slot1,
- OPERAND_ftsf132ae_slot1,
- OPERAND_ftsf133ae_slot1,
- OPERAND_ftsf134ae_slot1,
- OPERAND_ftsf135ae_slot1,
- OPERAND_ftsf136ae_slot1,
- OPERAND_ftsf137ae_slot1,
- OPERAND_ftsf138ae_slot1,
- OPERAND_ftsf139ae_slot1,
- OPERAND_ftsf140ae_slot1,
- OPERAND_ftsf141ae_slot1,
- OPERAND_ftsf142ae_slot1,
- OPERAND_ftsf143ae_slot1,
- OPERAND_ftsf144ae_slot1,
- OPERAND_ftsf145ae_slot1,
- OPERAND_ftsf146ae_slot1,
- OPERAND_ftsf147ae_slot1,
- OPERAND_ftsf148ae_slot1,
- OPERAND_ftsf149ae_slot1,
- OPERAND_ftsf150ae_slot1,
- OPERAND_ftsf151ae_slot1,
- OPERAND_ftsf152ae_slot1,
- OPERAND_ftsf153ae_slot1,
- OPERAND_ftsf154ae_slot1,
- OPERAND_ftsf155ae_slot1,
- OPERAND_ftsf156ae_slot1,
- OPERAND_ftsf157ae_slot1,
- OPERAND_ftsf158ae_slot1,
- OPERAND_ftsf159ae_slot1,
- OPERAND_ftsf160ae_slot1,
- OPERAND_ftsf161ae_slot1,
- OPERAND_ftsf162ae_slot1,
- OPERAND_ftsf163ae_slot1,
- OPERAND_ftsf164ae_slot1,
- OPERAND_ftsf165ae_slot1,
- OPERAND_ftsf166ae_slot1,
- OPERAND_ftsf167ae_slot1,
- OPERAND_ftsf168ae_slot1,
- OPERAND_ftsf169ae_slot1,
- OPERAND_ftsf170ae_slot1,
- OPERAND_ftsf171ae_slot1,
- OPERAND_ftsf172ae_slot1,
- OPERAND_ftsf173ae_slot1,
- OPERAND_ftsf174ae_slot1,
- OPERAND_ftsf175ae_slot1,
- OPERAND_ftsf176ae_slot1,
- OPERAND_ftsf177ae_slot1,
- OPERAND_ftsf178ae_slot1,
- OPERAND_ftsf179ae_slot1,
- OPERAND_ftsf180ae_slot1,
- OPERAND_ftsf181ae_slot1,
- OPERAND_ftsf182ae_slot1,
- OPERAND_ftsf183ae_slot1,
- OPERAND_ftsf184ae_slot1,
- OPERAND_ftsf185ae_slot1,
- OPERAND_ftsf186ae_slot1,
- OPERAND_ftsf187ae_slot1,
- OPERAND_ftsf188ae_slot1,
- OPERAND_ftsf189ae_slot1,
- OPERAND_ftsf190ae_slot1,
- OPERAND_ftsf191ae_slot1,
- OPERAND_ftsf192ae_slot1,
- OPERAND_ftsf193ae_slot1,
- OPERAND_ftsf194ae_slot1,
- OPERAND_ftsf195ae_slot1,
- OPERAND_ftsf196ae_slot1,
- OPERAND_ftsf197ae_slot1,
- OPERAND_ftsf198ae_slot1,
- OPERAND_ftsf199ae_slot1,
- OPERAND_ftsf200ae_slot1,
- OPERAND_ftsf201ae_slot1,
- OPERAND_ftsf202ae_slot1,
- OPERAND_ftsf203ae_slot1,
- OPERAND_ftsf204ae_slot1,
- OPERAND_ftsf205ae_slot1,
- OPERAND_ftsf206ae_slot1,
- OPERAND_ftsf207ae_slot1,
- OPERAND_ftsf208,
- OPERAND_ftsf209ae_slot1,
- OPERAND_ftsf210ae_slot1,
- OPERAND_ftsf211ae_slot1,
- OPERAND_ftsf330ae_slot1,
- OPERAND_ftsf332ae_slot1,
- OPERAND_ftsf334ae_slot1,
- OPERAND_ftsf336ae_slot1,
- OPERAND_ftsf337ae_slot1,
- OPERAND_ftsf338,
- OPERAND_ftsf339ae_slot1,
- OPERAND_ftsf340,
- OPERAND_ftsf341ae_slot1,
- OPERAND_ftsf342ae_slot1,
- OPERAND_ftsf343ae_slot1,
- OPERAND_ftsf344ae_slot1,
- OPERAND_ftsf346ae_slot1,
- OPERAND_ftsf347,
- OPERAND_ftsf348ae_slot1,
- OPERAND_ftsf349ae_slot1,
- OPERAND_ftsf350ae_slot1,
- OPERAND_op0_s4,
- OPERAND_ftsf212ae_slot0,
- OPERAND_ftsf213ae_slot0,
- OPERAND_ftsf214ae_slot0,
- OPERAND_ftsf215ae_slot0,
- OPERAND_ftsf216ae_slot0,
- OPERAND_ftsf217,
- OPERAND_ftsf218ae_slot0,
- OPERAND_ftsf219ae_slot0,
- OPERAND_ftsf220ae_slot0,
- OPERAND_ftsf221ae_slot0,
- OPERAND_ftsf222ae_slot0,
- OPERAND_ftsf223ae_slot0,
- OPERAND_ftsf224ae_slot0,
- OPERAND_ftsf225ae_slot0,
- OPERAND_ftsf226ae_slot0,
- OPERAND_ftsf227ae_slot0,
- OPERAND_ftsf228ae_slot0,
- OPERAND_ftsf229ae_slot0,
- OPERAND_ftsf230ae_slot0,
- OPERAND_ftsf231ae_slot0,
- OPERAND_ftsf232ae_slot0,
- OPERAND_ftsf233ae_slot0,
- OPERAND_ftsf234ae_slot0,
- OPERAND_ftsf235ae_slot0,
- OPERAND_ftsf236ae_slot0,
- OPERAND_ftsf237ae_slot0,
- OPERAND_ftsf238ae_slot0,
- OPERAND_ftsf239ae_slot0,
- OPERAND_ftsf240ae_slot0,
- OPERAND_ftsf241ae_slot0,
- OPERAND_ftsf242ae_slot0,
- OPERAND_ftsf243ae_slot0,
- OPERAND_ftsf244ae_slot0,
- OPERAND_ftsf245ae_slot0,
- OPERAND_ftsf246ae_slot0,
- OPERAND_ftsf247ae_slot0,
- OPERAND_ftsf248ae_slot0,
- OPERAND_ftsf249ae_slot0,
- OPERAND_ftsf250ae_slot0,
- OPERAND_ftsf251ae_slot0,
- OPERAND_ftsf252ae_slot0,
- OPERAND_ftsf253ae_slot0,
- OPERAND_ftsf254ae_slot0,
- OPERAND_ftsf255ae_slot0,
- OPERAND_ftsf256ae_slot0,
- OPERAND_ftsf257ae_slot0,
- OPERAND_ftsf258ae_slot0,
- OPERAND_ftsf259ae_slot0,
- OPERAND_ftsf260ae_slot0,
- OPERAND_ftsf261ae_slot0,
- OPERAND_ftsf262ae_slot0,
- OPERAND_ftsf263ae_slot0,
- OPERAND_ftsf264ae_slot0,
- OPERAND_ftsf265ae_slot0,
- OPERAND_ftsf266ae_slot0,
- OPERAND_ftsf267ae_slot0,
- OPERAND_ftsf268ae_slot0,
- OPERAND_ftsf269ae_slot0,
- OPERAND_ftsf270ae_slot0,
- OPERAND_ftsf271ae_slot0,
- OPERAND_ftsf272ae_slot0,
- OPERAND_ftsf273ae_slot0,
- OPERAND_ftsf274ae_slot0,
- OPERAND_ftsf275ae_slot0,
- OPERAND_ftsf276ae_slot0,
- OPERAND_ftsf277ae_slot0,
- OPERAND_ftsf278ae_slot0,
- OPERAND_ftsf279ae_slot0,
- OPERAND_ftsf281ae_slot0,
- OPERAND_ftsf282ae_slot0,
- OPERAND_ftsf283ae_slot0,
- OPERAND_ftsf284ae_slot0,
- OPERAND_ftsf286ae_slot0,
- OPERAND_ftsf288ae_slot0,
- OPERAND_ftsf290ae_slot0,
- OPERAND_ftsf292ae_slot0,
- OPERAND_ftsf293,
- OPERAND_ftsf294ae_slot0,
- OPERAND_ftsf295ae_slot0,
- OPERAND_ftsf296ae_slot0,
- OPERAND_ftsf297ae_slot0,
- OPERAND_ftsf298ae_slot0,
- OPERAND_ftsf299ae_slot0,
- OPERAND_ftsf300ae_slot0,
- OPERAND_ftsf301ae_slot0,
- OPERAND_ftsf302ae_slot0,
- OPERAND_ftsf303ae_slot0,
- OPERAND_ftsf304ae_slot0,
- OPERAND_ftsf306ae_slot0,
- OPERAND_ftsf308ae_slot0,
- OPERAND_ftsf309ae_slot0,
- OPERAND_ftsf310ae_slot0,
- OPERAND_ftsf311ae_slot0,
- OPERAND_ftsf312ae_slot0,
- OPERAND_ftsf313ae_slot0,
- OPERAND_ftsf314ae_slot0,
- OPERAND_ftsf315ae_slot0,
- OPERAND_ftsf316ae_slot0,
- OPERAND_ftsf317ae_slot0,
- OPERAND_ftsf318ae_slot0,
- OPERAND_ftsf319,
- OPERAND_ftsf320ae_slot0,
- OPERAND_ftsf321,
- OPERAND_ftsf322ae_slot0,
- OPERAND_ftsf323ae_slot0,
- OPERAND_ftsf324ae_slot0,
- OPERAND_ftsf325ae_slot0,
- OPERAND_ftsf326ae_slot0,
- OPERAND_ftsf328ae_slot0,
- OPERAND_ftsf329ae_slot0,
- OPERAND_ftsf352ae_slot0,
- OPERAND_ftsf353,
- OPERAND_ftsf354ae_slot0,
- OPERAND_ftsf356ae_slot0,
- OPERAND_ftsf357,
- OPERAND_ftsf358ae_slot0,
- OPERAND_ftsf359ae_slot0,
- OPERAND_ftsf360ae_slot0,
- OPERAND_ftsf361ae_slot0,
- OPERAND_ftsf362ae_slot0,
- OPERAND_ftsf364ae_slot0,
- OPERAND_ftsf365ae_slot0,
- OPERAND_ftsf366ae_slot0,
- OPERAND_ftsf368ae_slot0,
- OPERAND_ftsf369ae_slot0
-};
-
-\f
-/* Iclass table. */
-
-static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSRING }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar12 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar8 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { OPERAND_ars_entry }, 's' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm12x8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { OPERAND_simm4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_immrx4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ai4const }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm6 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_simm7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_lsi4x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_simm8x256 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4const }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bbi }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_b4constu }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_label12 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { OPERAND_soffsetx4 }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ar0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sae }, 'i' },
- { { OPERAND_op2p1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { OPERAND_soffset }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_uimm16x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ulabel8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_simm12b }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { OPERAND__ars_invisible }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { OPERAND_sas }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_msalp32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_sargt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'o' },
- { { STATE_LITBEN }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'm' },
- { { STATE_LITBEN }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul16_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { OPERAND_s }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSINTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTERRUPT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { OPERAND_imms }, 'i' },
- { { OPERAND_immt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { OPERAND_imms }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_bs }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_bs4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_bs8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
- { { OPERAND_bs }, 'i' },
- { { OPERAND_label8 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
- { { OPERAND_arr }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_brall }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_brall }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_brall }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOUNT }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm4x16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'm' },
- { { STATE_EXCVADDR }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'i' },
- { { STATE_ASID2 }, 'i' },
- { { STATE_ASID1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'o' },
- { { STATE_ASID2 }, 'o' },
- { { STATE_ASID1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'm' },
- { { STATE_ASID2 }, 'm' },
- { { STATE_ASID1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_tp7 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_uimm8x4 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_XTSYNC }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
- { { OPERAND_art }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'o' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
- { { OPERAND_art }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ATOMCTL }, 'm' },
- { { STATE_XTSYNC }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
- { { STATE_CCON }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MPSCORE }, 'i' }
-};
-
-static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
- INTERFACE_RMPINT_Out,
- INTERFACE_RMPINT_In
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
- { { OPERAND_art }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
- { { STATE_CCON }, 'm' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WMPINT_DATA }, 'o' },
- { { STATE_WMPINT_ADDR }, 'o' },
- { { STATE_MPSCORE }, 'm' },
- { { STATE_WMPINT_TOGGLEEN }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'i' },
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'o' },
- { { STATE_AE_SAR }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = {
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = {
- { { STATE_AE_BITHEAD }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_TABLESIZE }, 'i' },
- { { STATE_AE_FIRST_TS }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'o' },
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_TABLESIZE }, 'o' },
- { { STATE_AE_FIRST_TS }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'i' },
- { { STATE_AE_SEARCHDONE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = {
- { { STATE_AE_SAR }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = {
- { { STATE_AE_FIRST_TS }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = {
- { { STATE_AE_FIRST_TS }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = {
- { { OPERAND_arr }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = {
- { { STATE_AE_SEARCHDONE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = {
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm16 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = {
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_lsimm32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = {
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = {
- { { OPERAND_ps }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = {
- { { OPERAND_pr }, 'm' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = {
- { { OPERAND_pr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = {
- { { OPERAND_qr1_w }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = {
- { { OPERAND_qr1_w }, 'm' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bs }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = {
- { { OPERAND_qr1_w }, 'm' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bs }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_cvt_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_cvt_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
- { { OPERAND_alupppb_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
- { { OPERAND_alupppb_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' },
- { { OPERAND_bt2 }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = {
- { { OPERAND_bt2 }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = {
- { { OPERAND_bt2 }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = {
- { { OPERAND_bt2 }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bt }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_bt }, 'o' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_ae_samt32 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = {
- { { OPERAND_ps }, 'o' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = {
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ae_samt64 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_AE_SAR }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = {
- { { OPERAND_qr1_w }, 'o' },
- { { OPERAND_qr0_rw }, 'i' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = {
- { { OPERAND_bt }, 'o' },
- { { OPERAND_qr0 }, 'i' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = {
- { { OPERAND_ars }, 'o' },
- { { OPERAND_qr0_rw }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
- { { STATE_AE_OVERFLOW }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_mac_qr0_rw }, 'i' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_mac_qr0 }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'o' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
- { { OPERAND_mac_qr1_w }, 'm' },
- { { OPERAND_pr }, 'i' },
- { { OPERAND_pr0 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'm' },
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'm' },
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'o' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = {
- { { STATE_AE_TABLESIZE }, 'm' },
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'm' },
- { { STATE_AE_SEARCHDONE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = {
- { { STATE_AE_NEXTOFFSET }, 'm' },
- { { STATE_AE_TABLESIZE }, 'm' },
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_AE_FIRST_TS }, 'i' },
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_SEARCHDONE }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = {
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_AE_FIRST_TS }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_AE_TABLESIZE }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ae_ohba2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
- { { OPERAND_arr }, 'o' },
- { { OPERAND_ars }, 'i' },
- { { OPERAND_ae_ohba2 }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_db_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_ae_ohba }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = {
- { { OPERAND_br }, 'o' },
- { { OPERAND_art }, 'm' },
- { { OPERAND_ars }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'o' },
- { { STATE_AE_NEXTOFFSET }, 'o' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = {
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = {
- { { OPERAND_ars }, 'm' },
- { { OPERAND_art }, 'i' },
- { { OPERAND_ae_ohba }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'm' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_AE_BITSUSED }, 'i' },
- { { STATE_AE_NEXTOFFSET }, 'i' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = {
- { { OPERAND_ars }, 'm' }
-};
-
-static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = {
- { { STATE_AE_BITPTR }, 'i' },
- { { STATE_AE_BITHEAD }, 'm' },
- { { STATE_CPENABLE }, 'i' }
-};
-
-static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_threadptr_args,
- 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
- { 1, Iclass_wur_threadptr_args,
- 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid0_args,
- 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_configid0_args,
- 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_configid1_args,
- 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 3, Iclass_xt_mul16_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_bbool1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbool4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbool8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbranch_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bmove_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_RSR_BR_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_WSR_BR_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_XSR_BR_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_rasid_args,
- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_rasid_args,
- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_rasid_args,
- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
- 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
- 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
- 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
- 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_ldpte */,
- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwitlba */,
- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwdtlba */,
- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_cpenable_args,
- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_cpenable_args,
- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_cpenable_args,
- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_clamp_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_atomctl_args,
- 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_atomctl_args,
- 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_atomctl_args,
- 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rer_args,
- 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
- { 2, Iclass_xt_iclass_wer_args,
- 7, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
- { 1, Iclass_rur_ae_ovf_sar_args,
- 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 },
- { 1, Iclass_wur_ae_ovf_sar_args,
- 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 },
- { 1, Iclass_rur_ae_bithead_args,
- 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 },
- { 1, Iclass_wur_ae_bithead_args,
- 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 },
- { 1, Iclass_rur_ae_ts_fts_bu_bp_args,
- 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
- { 1, Iclass_wur_ae_ts_fts_bu_bp_args,
- 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 },
- { 1, Iclass_rur_ae_sd_no_args,
- 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 },
- { 1, Iclass_wur_ae_sd_no_args,
- 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_overflow_args,
- 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_overflow_args,
- 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_sar_args,
- 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_sar_args,
- 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_bitptr_args,
- 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_bitptr_args,
- 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_bitsused_args,
- 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_bitsused_args,
- 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_tablesize_args,
- 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_tablesize_args,
- 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_first_ts_args,
- 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_first_ts_args,
- 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_nextoffset_args,
- 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_nextoffset_args,
- 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_rur_ae_searchdone_args,
- 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_wur_ae_searchdone_args,
- 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16f_i_args,
- 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16f_iu_args,
- 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16f_x_args,
- 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16f_xu_args,
- 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24_i_args,
- 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24_iu_args,
- 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24_x_args,
- 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24_xu_args,
- 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24f_i_args,
- 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24f_iu_args,
- 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24f_x_args,
- 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24f_xu_args,
- 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16x2f_i_args,
- 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16x2f_iu_args,
- 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16x2f_x_args,
- 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp16x2f_xu_args,
- 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2f_i_args,
- 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2f_iu_args,
- 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2f_x_args,
- 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2f_xu_args,
- 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2_i_args,
- 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2_iu_args,
- 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2_x_args,
- 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lp24x2_xu_args,
- 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16x2f_i_args,
- 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16x2f_iu_args,
- 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16x2f_x_args,
- 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16x2f_xu_args,
- 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2s_i_args,
- 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2s_iu_args,
- 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2s_x_args,
- 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2s_xu_args,
- 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2f_i_args,
- 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2f_iu_args,
- 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2f_x_args,
- 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24x2f_xu_args,
- 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16f_l_i_args,
- 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16f_l_iu_args,
- 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16f_l_x_args,
- 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp16f_l_xu_args,
- 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24s_l_i_args,
- 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24s_l_iu_args,
- 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24s_l_x_args,
- 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24s_l_xu_args,
- 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24f_l_i_args,
- 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24f_l_iu_args,
- 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24f_l_x_args,
- 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sp24f_l_xu_args,
- 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq56_i_args,
- 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq56_iu_args,
- 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq56_x_args,
- 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq56_xu_args,
- 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq32f_i_args,
- 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq32f_iu_args,
- 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq32f_x_args,
- 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lq32f_xu_args,
- 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq56s_i_args,
- 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq56s_iu_args,
- 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq56s_x_args,
- 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq56s_xu_args,
- 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq32f_i_args,
- 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq32f_iu_args,
- 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq32f_x_args,
- 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sq32f_xu_args,
- 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_zerop48_args,
- 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_movp48_args,
- 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_selp24_ll_args,
- 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_selp24_lh_args,
- 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_selp24_hl_args,
- 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_selp24_hh_args,
- 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_movtp24x2_args,
- 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_movfp24x2_args,
- 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_movtp48_args,
- 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_movfp48_args,
- 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_movpa24x2_args,
- 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_truncp24a32x2_args,
- 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_cvta32p24_l_args,
- 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_cvta32p24_h_args,
- 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args,
- 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args,
- 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args,
- 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args,
- 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_truncp24q48x2_args,
- 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_truncp16_args,
- 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_roundsp24q48sym_args,
- 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_roundsp24q48asym_args,
- 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_roundsp16q48sym_args,
- 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_roundsp16q48asym_args,
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- 1, Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzaaq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzaafq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzaaq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzaafq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzaaq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args,
- 1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args,
- 1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args,
- 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args,
- 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args,
- 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 },
- { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args,
- 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args,
- 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args,
- 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_sha32_args,
- 0, 0, 0, 0 },
- { 3, Iclass_ae_iclass_vldl32t_args,
- 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_vldl16t_args,
- 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_vldl16c_args,
- 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_vldsht_args,
- 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_lb_args,
- 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_lbi_args,
- 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lbk_args,
- 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_lbki_args,
- 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_db_args,
- 3, Iclass_ae_iclass_db_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_dbi_args,
- 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_vlel32t_args,
- 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_vlel16t_args,
- 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 },
- { 2, Iclass_ae_iclass_sb_args,
- 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 },
- { 3, Iclass_ae_iclass_sbi_args,
- 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_vles16c_args,
- 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 },
- { 1, Iclass_ae_iclass_sbf_args,
- 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }
-};
-
-enum xtensa_iclass_id {
- ICLASS_xt_iclass_excw,
- ICLASS_xt_iclass_rfe,
- ICLASS_xt_iclass_rfde,
- ICLASS_xt_iclass_syscall,
- ICLASS_xt_iclass_call12,
- ICLASS_xt_iclass_call8,
- ICLASS_xt_iclass_call4,
- ICLASS_xt_iclass_callx12,
- ICLASS_xt_iclass_callx8,
- ICLASS_xt_iclass_callx4,
- ICLASS_xt_iclass_entry,
- ICLASS_xt_iclass_movsp,
- ICLASS_xt_iclass_rotw,
- ICLASS_xt_iclass_retw,
- ICLASS_xt_iclass_rfwou,
- ICLASS_xt_iclass_l32e,
- ICLASS_xt_iclass_s32e,
- ICLASS_xt_iclass_rsr_windowbase,
- ICLASS_xt_iclass_wsr_windowbase,
- ICLASS_xt_iclass_xsr_windowbase,
- ICLASS_xt_iclass_rsr_windowstart,
- ICLASS_xt_iclass_wsr_windowstart,
- ICLASS_xt_iclass_xsr_windowstart,
- ICLASS_xt_iclass_add_n,
- ICLASS_xt_iclass_addi_n,
- ICLASS_xt_iclass_bz6,
- ICLASS_xt_iclass_ill_n,
- ICLASS_xt_iclass_loadi4,
- ICLASS_xt_iclass_mov_n,
- ICLASS_xt_iclass_movi_n,
- ICLASS_xt_iclass_nopn,
- ICLASS_xt_iclass_retn,
- ICLASS_xt_iclass_storei4,
- ICLASS_rur_threadptr,
- ICLASS_wur_threadptr,
- ICLASS_xt_iclass_addi,
- ICLASS_xt_iclass_addmi,
- ICLASS_xt_iclass_addsub,
- ICLASS_xt_iclass_bit,
- ICLASS_xt_iclass_bsi8,
- ICLASS_xt_iclass_bsi8b,
- ICLASS_xt_iclass_bsi8u,
- ICLASS_xt_iclass_bst8,
- ICLASS_xt_iclass_bsz12,
- ICLASS_xt_iclass_call0,
- ICLASS_xt_iclass_callx0,
- ICLASS_xt_iclass_exti,
- ICLASS_xt_iclass_ill,
- ICLASS_xt_iclass_jump,
- ICLASS_xt_iclass_jumpx,
- ICLASS_xt_iclass_l16ui,
- ICLASS_xt_iclass_l16si,
- ICLASS_xt_iclass_l32i,
- ICLASS_xt_iclass_l32r,
- ICLASS_xt_iclass_l8i,
- ICLASS_xt_iclass_loop,
- ICLASS_xt_iclass_loopz,
- ICLASS_xt_iclass_movi,
- ICLASS_xt_iclass_movz,
- ICLASS_xt_iclass_neg,
- ICLASS_xt_iclass_nop,
- ICLASS_xt_iclass_return,
- ICLASS_xt_iclass_simcall,
- ICLASS_xt_iclass_s16i,
- ICLASS_xt_iclass_s32i,
- ICLASS_xt_iclass_s8i,
- ICLASS_xt_iclass_sar,
- ICLASS_xt_iclass_sari,
- ICLASS_xt_iclass_shifts,
- ICLASS_xt_iclass_shiftst,
- ICLASS_xt_iclass_shiftt,
- ICLASS_xt_iclass_slli,
- ICLASS_xt_iclass_srai,
- ICLASS_xt_iclass_srli,
- ICLASS_xt_iclass_memw,
- ICLASS_xt_iclass_extw,
- ICLASS_xt_iclass_isync,
- ICLASS_xt_iclass_sync,
- ICLASS_xt_iclass_rsil,
- ICLASS_xt_iclass_rsr_lend,
- ICLASS_xt_iclass_wsr_lend,
- ICLASS_xt_iclass_xsr_lend,
- ICLASS_xt_iclass_rsr_lcount,
- ICLASS_xt_iclass_wsr_lcount,
- ICLASS_xt_iclass_xsr_lcount,
- ICLASS_xt_iclass_rsr_lbeg,
- ICLASS_xt_iclass_wsr_lbeg,
- ICLASS_xt_iclass_xsr_lbeg,
- ICLASS_xt_iclass_rsr_sar,
- ICLASS_xt_iclass_wsr_sar,
- ICLASS_xt_iclass_xsr_sar,
- ICLASS_xt_iclass_rsr_litbase,
- ICLASS_xt_iclass_wsr_litbase,
- ICLASS_xt_iclass_xsr_litbase,
- ICLASS_xt_iclass_rsr_configid0,
- ICLASS_xt_iclass_wsr_configid0,
- ICLASS_xt_iclass_rsr_configid1,
- ICLASS_xt_iclass_rsr_ps,
- ICLASS_xt_iclass_wsr_ps,
- ICLASS_xt_iclass_xsr_ps,
- ICLASS_xt_iclass_rsr_epc1,
- ICLASS_xt_iclass_wsr_epc1,
- ICLASS_xt_iclass_xsr_epc1,
- ICLASS_xt_iclass_rsr_excsave1,
- ICLASS_xt_iclass_wsr_excsave1,
- ICLASS_xt_iclass_xsr_excsave1,
- ICLASS_xt_iclass_rsr_epc2,
- ICLASS_xt_iclass_wsr_epc2,
- ICLASS_xt_iclass_xsr_epc2,
- ICLASS_xt_iclass_rsr_excsave2,
- ICLASS_xt_iclass_wsr_excsave2,
- ICLASS_xt_iclass_xsr_excsave2,
- ICLASS_xt_iclass_rsr_eps2,
- ICLASS_xt_iclass_wsr_eps2,
- ICLASS_xt_iclass_xsr_eps2,
- ICLASS_xt_iclass_rsr_excvaddr,
- ICLASS_xt_iclass_wsr_excvaddr,
- ICLASS_xt_iclass_xsr_excvaddr,
- ICLASS_xt_iclass_rsr_depc,
- ICLASS_xt_iclass_wsr_depc,
- ICLASS_xt_iclass_xsr_depc,
- ICLASS_xt_iclass_rsr_exccause,
- ICLASS_xt_iclass_wsr_exccause,
- ICLASS_xt_iclass_xsr_exccause,
- ICLASS_xt_iclass_rsr_misc0,
- ICLASS_xt_iclass_wsr_misc0,
- ICLASS_xt_iclass_xsr_misc0,
- ICLASS_xt_iclass_rsr_misc1,
- ICLASS_xt_iclass_wsr_misc1,
- ICLASS_xt_iclass_xsr_misc1,
- ICLASS_xt_iclass_rsr_prid,
- ICLASS_xt_iclass_rsr_vecbase,
- ICLASS_xt_iclass_wsr_vecbase,
- ICLASS_xt_iclass_xsr_vecbase,
- ICLASS_xt_mul16,
- ICLASS_xt_mul32,
- ICLASS_xt_iclass_rfi,
- ICLASS_xt_iclass_wait,
- ICLASS_xt_iclass_rsr_interrupt,
- ICLASS_xt_iclass_wsr_intset,
- ICLASS_xt_iclass_wsr_intclear,
- ICLASS_xt_iclass_rsr_intenable,
- ICLASS_xt_iclass_wsr_intenable,
- ICLASS_xt_iclass_xsr_intenable,
- ICLASS_xt_iclass_break,
- ICLASS_xt_iclass_break_n,
- ICLASS_xt_iclass_rsr_debugcause,
- ICLASS_xt_iclass_wsr_debugcause,
- ICLASS_xt_iclass_xsr_debugcause,
- ICLASS_xt_iclass_rsr_icount,
- ICLASS_xt_iclass_wsr_icount,
- ICLASS_xt_iclass_xsr_icount,
- ICLASS_xt_iclass_rsr_icountlevel,
- ICLASS_xt_iclass_wsr_icountlevel,
- ICLASS_xt_iclass_xsr_icountlevel,
- ICLASS_xt_iclass_rsr_ddr,
- ICLASS_xt_iclass_wsr_ddr,
- ICLASS_xt_iclass_xsr_ddr,
- ICLASS_xt_iclass_rfdo,
- ICLASS_xt_iclass_rfdd,
- ICLASS_xt_iclass_bbool1,
- ICLASS_xt_iclass_bbool4,
- ICLASS_xt_iclass_bbool8,
- ICLASS_xt_iclass_bbranch,
- ICLASS_xt_iclass_bmove,
- ICLASS_xt_iclass_RSR_BR,
- ICLASS_xt_iclass_WSR_BR,
- ICLASS_xt_iclass_XSR_BR,
- ICLASS_xt_iclass_rsr_ccount,
- ICLASS_xt_iclass_wsr_ccount,
- ICLASS_xt_iclass_xsr_ccount,
- ICLASS_xt_iclass_rsr_ccompare0,
- ICLASS_xt_iclass_wsr_ccompare0,
- ICLASS_xt_iclass_xsr_ccompare0,
- ICLASS_xt_iclass_rsr_ccompare1,
- ICLASS_xt_iclass_wsr_ccompare1,
- ICLASS_xt_iclass_xsr_ccompare1,
- ICLASS_xt_iclass_icache,
- ICLASS_xt_iclass_icache_inv,
- ICLASS_xt_iclass_licx,
- ICLASS_xt_iclass_sicx,
- ICLASS_xt_iclass_dcache,
- ICLASS_xt_iclass_dcache_ind,
- ICLASS_xt_iclass_dcache_inv,
- ICLASS_xt_iclass_dpf,
- ICLASS_xt_iclass_sdct,
- ICLASS_xt_iclass_ldct,
- ICLASS_xt_iclass_wsr_ptevaddr,
- ICLASS_xt_iclass_rsr_ptevaddr,
- ICLASS_xt_iclass_xsr_ptevaddr,
- ICLASS_xt_iclass_rsr_rasid,
- ICLASS_xt_iclass_wsr_rasid,
- ICLASS_xt_iclass_xsr_rasid,
- ICLASS_xt_iclass_rsr_itlbcfg,
- ICLASS_xt_iclass_wsr_itlbcfg,
- ICLASS_xt_iclass_xsr_itlbcfg,
- ICLASS_xt_iclass_rsr_dtlbcfg,
- ICLASS_xt_iclass_wsr_dtlbcfg,
- ICLASS_xt_iclass_xsr_dtlbcfg,
- ICLASS_xt_iclass_idtlb,
- ICLASS_xt_iclass_rdtlb,
- ICLASS_xt_iclass_wdtlb,
- ICLASS_xt_iclass_iitlb,
- ICLASS_xt_iclass_ritlb,
- ICLASS_xt_iclass_witlb,
- ICLASS_xt_iclass_ldpte,
- ICLASS_xt_iclass_hwwitlba,
- ICLASS_xt_iclass_hwwdtlba,
- ICLASS_xt_iclass_rsr_cpenable,
- ICLASS_xt_iclass_wsr_cpenable,
- ICLASS_xt_iclass_xsr_cpenable,
- ICLASS_xt_iclass_clamp,
- ICLASS_xt_iclass_minmax,
- ICLASS_xt_iclass_nsa,
- ICLASS_xt_iclass_sx,
- ICLASS_xt_iclass_l32ai,
- ICLASS_xt_iclass_s32ri,
- ICLASS_xt_iclass_s32c1i,
- ICLASS_xt_iclass_rsr_scompare1,
- ICLASS_xt_iclass_wsr_scompare1,
- ICLASS_xt_iclass_xsr_scompare1,
- ICLASS_xt_iclass_rsr_atomctl,
- ICLASS_xt_iclass_wsr_atomctl,
- ICLASS_xt_iclass_xsr_atomctl,
- ICLASS_xt_iclass_rer,
- ICLASS_xt_iclass_wer,
- ICLASS_rur_ae_ovf_sar,
- ICLASS_wur_ae_ovf_sar,
- ICLASS_rur_ae_bithead,
- ICLASS_wur_ae_bithead,
- ICLASS_rur_ae_ts_fts_bu_bp,
- ICLASS_wur_ae_ts_fts_bu_bp,
- ICLASS_rur_ae_sd_no,
- ICLASS_wur_ae_sd_no,
- ICLASS_ae_iclass_rur_ae_overflow,
- ICLASS_ae_iclass_wur_ae_overflow,
- ICLASS_ae_iclass_rur_ae_sar,
- ICLASS_ae_iclass_wur_ae_sar,
- ICLASS_ae_iclass_rur_ae_bitptr,
- ICLASS_ae_iclass_wur_ae_bitptr,
- ICLASS_ae_iclass_rur_ae_bitsused,
- ICLASS_ae_iclass_wur_ae_bitsused,
- ICLASS_ae_iclass_rur_ae_tablesize,
- ICLASS_ae_iclass_wur_ae_tablesize,
- ICLASS_ae_iclass_rur_ae_first_ts,
- ICLASS_ae_iclass_wur_ae_first_ts,
- ICLASS_ae_iclass_rur_ae_nextoffset,
- ICLASS_ae_iclass_wur_ae_nextoffset,
- ICLASS_ae_iclass_rur_ae_searchdone,
- ICLASS_ae_iclass_wur_ae_searchdone,
- ICLASS_ae_iclass_lp16f_i,
- ICLASS_ae_iclass_lp16f_iu,
- ICLASS_ae_iclass_lp16f_x,
- ICLASS_ae_iclass_lp16f_xu,
- ICLASS_ae_iclass_lp24_i,
- ICLASS_ae_iclass_lp24_iu,
- ICLASS_ae_iclass_lp24_x,
- ICLASS_ae_iclass_lp24_xu,
- ICLASS_ae_iclass_lp24f_i,
- ICLASS_ae_iclass_lp24f_iu,
- ICLASS_ae_iclass_lp24f_x,
- ICLASS_ae_iclass_lp24f_xu,
- ICLASS_ae_iclass_lp16x2f_i,
- ICLASS_ae_iclass_lp16x2f_iu,
- ICLASS_ae_iclass_lp16x2f_x,
- ICLASS_ae_iclass_lp16x2f_xu,
- ICLASS_ae_iclass_lp24x2f_i,
- ICLASS_ae_iclass_lp24x2f_iu,
- ICLASS_ae_iclass_lp24x2f_x,
- ICLASS_ae_iclass_lp24x2f_xu,
- ICLASS_ae_iclass_lp24x2_i,
- ICLASS_ae_iclass_lp24x2_iu,
- ICLASS_ae_iclass_lp24x2_x,
- ICLASS_ae_iclass_lp24x2_xu,
- ICLASS_ae_iclass_sp16x2f_i,
- ICLASS_ae_iclass_sp16x2f_iu,
- ICLASS_ae_iclass_sp16x2f_x,
- ICLASS_ae_iclass_sp16x2f_xu,
- ICLASS_ae_iclass_sp24x2s_i,
- ICLASS_ae_iclass_sp24x2s_iu,
- ICLASS_ae_iclass_sp24x2s_x,
- ICLASS_ae_iclass_sp24x2s_xu,
- ICLASS_ae_iclass_sp24x2f_i,
- ICLASS_ae_iclass_sp24x2f_iu,
- ICLASS_ae_iclass_sp24x2f_x,
- ICLASS_ae_iclass_sp24x2f_xu,
- ICLASS_ae_iclass_sp16f_l_i,
- ICLASS_ae_iclass_sp16f_l_iu,
- ICLASS_ae_iclass_sp16f_l_x,
- ICLASS_ae_iclass_sp16f_l_xu,
- ICLASS_ae_iclass_sp24s_l_i,
- ICLASS_ae_iclass_sp24s_l_iu,
- ICLASS_ae_iclass_sp24s_l_x,
- ICLASS_ae_iclass_sp24s_l_xu,
- ICLASS_ae_iclass_sp24f_l_i,
- ICLASS_ae_iclass_sp24f_l_iu,
- ICLASS_ae_iclass_sp24f_l_x,
- ICLASS_ae_iclass_sp24f_l_xu,
- ICLASS_ae_iclass_lq56_i,
- ICLASS_ae_iclass_lq56_iu,
- ICLASS_ae_iclass_lq56_x,
- ICLASS_ae_iclass_lq56_xu,
- ICLASS_ae_iclass_lq32f_i,
- ICLASS_ae_iclass_lq32f_iu,
- ICLASS_ae_iclass_lq32f_x,
- ICLASS_ae_iclass_lq32f_xu,
- ICLASS_ae_iclass_sq56s_i,
- ICLASS_ae_iclass_sq56s_iu,
- ICLASS_ae_iclass_sq56s_x,
- ICLASS_ae_iclass_sq56s_xu,
- ICLASS_ae_iclass_sq32f_i,
- ICLASS_ae_iclass_sq32f_iu,
- ICLASS_ae_iclass_sq32f_x,
- ICLASS_ae_iclass_sq32f_xu,
- ICLASS_ae_iclass_zerop48,
- ICLASS_ae_iclass_movp48,
- ICLASS_ae_iclass_selp24_ll,
- ICLASS_ae_iclass_selp24_lh,
- ICLASS_ae_iclass_selp24_hl,
- ICLASS_ae_iclass_selp24_hh,
- ICLASS_ae_iclass_movtp24x2,
- ICLASS_ae_iclass_movfp24x2,
- ICLASS_ae_iclass_movtp48,
- ICLASS_ae_iclass_movfp48,
- ICLASS_ae_iclass_movpa24x2,
- ICLASS_ae_iclass_truncp24a32x2,
- ICLASS_ae_iclass_cvta32p24_l,
- ICLASS_ae_iclass_cvta32p24_h,
- ICLASS_ae_iclass_cvtp24a16x2_ll,
- ICLASS_ae_iclass_cvtp24a16x2_lh,
- ICLASS_ae_iclass_cvtp24a16x2_hl,
- ICLASS_ae_iclass_cvtp24a16x2_hh,
- ICLASS_ae_iclass_truncp24q48x2,
- ICLASS_ae_iclass_truncp16,
- ICLASS_ae_iclass_roundsp24q48sym,
- ICLASS_ae_iclass_roundsp24q48asym,
- ICLASS_ae_iclass_roundsp16q48sym,
- ICLASS_ae_iclass_roundsp16q48asym,
- ICLASS_ae_iclass_roundsp16sym,
- ICLASS_ae_iclass_roundsp16asym,
- ICLASS_ae_iclass_zeroq56,
- ICLASS_ae_iclass_movq56,
- ICLASS_ae_iclass_movtq56,
- ICLASS_ae_iclass_movfq56,
- ICLASS_ae_iclass_cvtq48a32s,
- ICLASS_ae_iclass_cvtq48p24s_l,
- ICLASS_ae_iclass_cvtq48p24s_h,
- ICLASS_ae_iclass_satq48s,
- ICLASS_ae_iclass_truncq32,
- ICLASS_ae_iclass_roundsq32sym,
- ICLASS_ae_iclass_roundsq32asym,
- ICLASS_ae_iclass_trunca32q48,
- ICLASS_ae_iclass_movap24s_l,
- ICLASS_ae_iclass_movap24s_h,
- ICLASS_ae_iclass_trunca16p24s_l,
- ICLASS_ae_iclass_trunca16p24s_h,
- ICLASS_ae_iclass_addp24,
- ICLASS_ae_iclass_subp24,
- ICLASS_ae_iclass_negp24,
- ICLASS_ae_iclass_absp24,
- ICLASS_ae_iclass_maxp24s,
- ICLASS_ae_iclass_minp24s,
- ICLASS_ae_iclass_maxbp24s,
- ICLASS_ae_iclass_minbp24s,
- ICLASS_ae_iclass_addsp24s,
- ICLASS_ae_iclass_subsp24s,
- ICLASS_ae_iclass_negsp24s,
- ICLASS_ae_iclass_abssp24s,
- ICLASS_ae_iclass_andp48,
- ICLASS_ae_iclass_nandp48,
- ICLASS_ae_iclass_orp48,
- ICLASS_ae_iclass_xorp48,
- ICLASS_ae_iclass_ltp24s,
- ICLASS_ae_iclass_lep24s,
- ICLASS_ae_iclass_eqp24,
- ICLASS_ae_iclass_addq56,
- ICLASS_ae_iclass_subq56,
- ICLASS_ae_iclass_negq56,
- ICLASS_ae_iclass_absq56,
- ICLASS_ae_iclass_maxq56s,
- ICLASS_ae_iclass_minq56s,
- ICLASS_ae_iclass_maxbq56s,
- ICLASS_ae_iclass_minbq56s,
- ICLASS_ae_iclass_addsq56s,
- ICLASS_ae_iclass_subsq56s,
- ICLASS_ae_iclass_negsq56s,
- ICLASS_ae_iclass_abssq56s,
- ICLASS_ae_iclass_andq56,
- ICLASS_ae_iclass_nandq56,
- ICLASS_ae_iclass_orq56,
- ICLASS_ae_iclass_xorq56,
- ICLASS_ae_iclass_sllip24,
- ICLASS_ae_iclass_srlip24,
- ICLASS_ae_iclass_sraip24,
- ICLASS_ae_iclass_sllsp24,
- ICLASS_ae_iclass_srlsp24,
- ICLASS_ae_iclass_srasp24,
- ICLASS_ae_iclass_sllisp24s,
- ICLASS_ae_iclass_sllssp24s,
- ICLASS_ae_iclass_slliq56,
- ICLASS_ae_iclass_srliq56,
- ICLASS_ae_iclass_sraiq56,
- ICLASS_ae_iclass_sllsq56,
- ICLASS_ae_iclass_srlsq56,
- ICLASS_ae_iclass_srasq56,
- ICLASS_ae_iclass_sllaq56,
- ICLASS_ae_iclass_srlaq56,
- ICLASS_ae_iclass_sraaq56,
- ICLASS_ae_iclass_sllisq56s,
- ICLASS_ae_iclass_sllssq56s,
- ICLASS_ae_iclass_sllasq56s,
- ICLASS_ae_iclass_ltq56s,
- ICLASS_ae_iclass_leq56s,
- ICLASS_ae_iclass_eqq56,
- ICLASS_ae_iclass_nsaq56s,
- ICLASS_ae_iclass_mulfs32p16s_ll,
- ICLASS_ae_iclass_mulfp24s_ll,
- ICLASS_ae_iclass_mulp24s_ll,
- ICLASS_ae_iclass_mulfs32p16s_lh,
- ICLASS_ae_iclass_mulfp24s_lh,
- ICLASS_ae_iclass_mulp24s_lh,
- ICLASS_ae_iclass_mulfs32p16s_hl,
- ICLASS_ae_iclass_mulfp24s_hl,
- ICLASS_ae_iclass_mulp24s_hl,
- ICLASS_ae_iclass_mulfs32p16s_hh,
- ICLASS_ae_iclass_mulfp24s_hh,
- ICLASS_ae_iclass_mulp24s_hh,
- ICLASS_ae_iclass_mulafs32p16s_ll,
- ICLASS_ae_iclass_mulafp24s_ll,
- ICLASS_ae_iclass_mulap24s_ll,
- ICLASS_ae_iclass_mulafs32p16s_lh,
- ICLASS_ae_iclass_mulafp24s_lh,
- ICLASS_ae_iclass_mulap24s_lh,
- ICLASS_ae_iclass_mulafs32p16s_hl,
- ICLASS_ae_iclass_mulafp24s_hl,
- ICLASS_ae_iclass_mulap24s_hl,
- ICLASS_ae_iclass_mulafs32p16s_hh,
- ICLASS_ae_iclass_mulafp24s_hh,
- ICLASS_ae_iclass_mulap24s_hh,
- ICLASS_ae_iclass_mulsfs32p16s_ll,
- ICLASS_ae_iclass_mulsfp24s_ll,
- ICLASS_ae_iclass_mulsp24s_ll,
- ICLASS_ae_iclass_mulsfs32p16s_lh,
- ICLASS_ae_iclass_mulsfp24s_lh,
- ICLASS_ae_iclass_mulsp24s_lh,
- ICLASS_ae_iclass_mulsfs32p16s_hl,
- ICLASS_ae_iclass_mulsfp24s_hl,
- ICLASS_ae_iclass_mulsp24s_hl,
- ICLASS_ae_iclass_mulsfs32p16s_hh,
- ICLASS_ae_iclass_mulsfp24s_hh,
- ICLASS_ae_iclass_mulsp24s_hh,
- ICLASS_ae_iclass_mulafs56p24s_ll,
- ICLASS_ae_iclass_mulas56p24s_ll,
- ICLASS_ae_iclass_mulafs56p24s_lh,
- ICLASS_ae_iclass_mulas56p24s_lh,
- ICLASS_ae_iclass_mulafs56p24s_hl,
- ICLASS_ae_iclass_mulas56p24s_hl,
- ICLASS_ae_iclass_mulafs56p24s_hh,
- ICLASS_ae_iclass_mulas56p24s_hh,
- ICLASS_ae_iclass_mulsfs56p24s_ll,
- ICLASS_ae_iclass_mulss56p24s_ll,
- ICLASS_ae_iclass_mulsfs56p24s_lh,
- ICLASS_ae_iclass_mulss56p24s_lh,
- ICLASS_ae_iclass_mulsfs56p24s_hl,
- ICLASS_ae_iclass_mulss56p24s_hl,
- ICLASS_ae_iclass_mulsfs56p24s_hh,
- ICLASS_ae_iclass_mulss56p24s_hh,
- ICLASS_ae_iclass_mulfq32sp16s_l,
- ICLASS_ae_iclass_mulfq32sp16s_h,
- ICLASS_ae_iclass_mulfq32sp16u_l,
- ICLASS_ae_iclass_mulfq32sp16u_h,
- ICLASS_ae_iclass_mulq32sp16s_l,
- ICLASS_ae_iclass_mulq32sp16s_h,
- ICLASS_ae_iclass_mulq32sp16u_l,
- ICLASS_ae_iclass_mulq32sp16u_h,
- ICLASS_ae_iclass_mulafq32sp16s_l,
- ICLASS_ae_iclass_mulafq32sp16s_h,
- ICLASS_ae_iclass_mulafq32sp16u_l,
- ICLASS_ae_iclass_mulafq32sp16u_h,
- ICLASS_ae_iclass_mulaq32sp16s_l,
- ICLASS_ae_iclass_mulaq32sp16s_h,
- ICLASS_ae_iclass_mulaq32sp16u_l,
- ICLASS_ae_iclass_mulaq32sp16u_h,
- ICLASS_ae_iclass_mulsfq32sp16s_l,
- ICLASS_ae_iclass_mulsfq32sp16s_h,
- ICLASS_ae_iclass_mulsfq32sp16u_l,
- ICLASS_ae_iclass_mulsfq32sp16u_h,
- ICLASS_ae_iclass_mulsq32sp16s_l,
- ICLASS_ae_iclass_mulsq32sp16s_h,
- ICLASS_ae_iclass_mulsq32sp16u_l,
- ICLASS_ae_iclass_mulsq32sp16u_h,
- ICLASS_ae_iclass_mulzaaq32sp16s_ll,
- ICLASS_ae_iclass_mulzaafq32sp16s_ll,
- ICLASS_ae_iclass_mulzaaq32sp16u_ll,
- ICLASS_ae_iclass_mulzaafq32sp16u_ll,
- ICLASS_ae_iclass_mulzaaq32sp16s_hh,
- ICLASS_ae_iclass_mulzaafq32sp16s_hh,
- ICLASS_ae_iclass_mulzaaq32sp16u_hh,
- ICLASS_ae_iclass_mulzaafq32sp16u_hh,
- ICLASS_ae_iclass_mulzaaq32sp16s_lh,
- ICLASS_ae_iclass_mulzaafq32sp16s_lh,
- ICLASS_ae_iclass_mulzaaq32sp16u_lh,
- ICLASS_ae_iclass_mulzaafq32sp16u_lh,
- ICLASS_ae_iclass_mulzasq32sp16s_ll,
- ICLASS_ae_iclass_mulzasfq32sp16s_ll,
- ICLASS_ae_iclass_mulzasq32sp16u_ll,
- ICLASS_ae_iclass_mulzasfq32sp16u_ll,
- ICLASS_ae_iclass_mulzasq32sp16s_hh,
- ICLASS_ae_iclass_mulzasfq32sp16s_hh,
- ICLASS_ae_iclass_mulzasq32sp16u_hh,
- ICLASS_ae_iclass_mulzasfq32sp16u_hh,
- ICLASS_ae_iclass_mulzasq32sp16s_lh,
- ICLASS_ae_iclass_mulzasfq32sp16s_lh,
- ICLASS_ae_iclass_mulzasq32sp16u_lh,
- ICLASS_ae_iclass_mulzasfq32sp16u_lh,
- ICLASS_ae_iclass_mulzsaq32sp16s_ll,
- ICLASS_ae_iclass_mulzsafq32sp16s_ll,
- ICLASS_ae_iclass_mulzsaq32sp16u_ll,
- ICLASS_ae_iclass_mulzsafq32sp16u_ll,
- ICLASS_ae_iclass_mulzsaq32sp16s_hh,
- ICLASS_ae_iclass_mulzsafq32sp16s_hh,
- ICLASS_ae_iclass_mulzsaq32sp16u_hh,
- ICLASS_ae_iclass_mulzsafq32sp16u_hh,
- ICLASS_ae_iclass_mulzsaq32sp16s_lh,
- ICLASS_ae_iclass_mulzsafq32sp16s_lh,
- ICLASS_ae_iclass_mulzsaq32sp16u_lh,
- ICLASS_ae_iclass_mulzsafq32sp16u_lh,
- ICLASS_ae_iclass_mulzssq32sp16s_ll,
- ICLASS_ae_iclass_mulzssfq32sp16s_ll,
- ICLASS_ae_iclass_mulzssq32sp16u_ll,
- ICLASS_ae_iclass_mulzssfq32sp16u_ll,
- ICLASS_ae_iclass_mulzssq32sp16s_hh,
- ICLASS_ae_iclass_mulzssfq32sp16s_hh,
- ICLASS_ae_iclass_mulzssq32sp16u_hh,
- ICLASS_ae_iclass_mulzssfq32sp16u_hh,
- ICLASS_ae_iclass_mulzssq32sp16s_lh,
- ICLASS_ae_iclass_mulzssfq32sp16s_lh,
- ICLASS_ae_iclass_mulzssq32sp16u_lh,
- ICLASS_ae_iclass_mulzssfq32sp16u_lh,
- ICLASS_ae_iclass_mulzaafp24s_hh_ll,
- ICLASS_ae_iclass_mulzaap24s_hh_ll,
- ICLASS_ae_iclass_mulzaafp24s_hl_lh,
- ICLASS_ae_iclass_mulzaap24s_hl_lh,
- ICLASS_ae_iclass_mulzasfp24s_hh_ll,
- ICLASS_ae_iclass_mulzasp24s_hh_ll,
- ICLASS_ae_iclass_mulzasfp24s_hl_lh,
- ICLASS_ae_iclass_mulzasp24s_hl_lh,
- ICLASS_ae_iclass_mulzsafp24s_hh_ll,
- ICLASS_ae_iclass_mulzsap24s_hh_ll,
- ICLASS_ae_iclass_mulzsafp24s_hl_lh,
- ICLASS_ae_iclass_mulzsap24s_hl_lh,
- ICLASS_ae_iclass_mulzssfp24s_hh_ll,
- ICLASS_ae_iclass_mulzssp24s_hh_ll,
- ICLASS_ae_iclass_mulzssfp24s_hl_lh,
- ICLASS_ae_iclass_mulzssp24s_hl_lh,
- ICLASS_ae_iclass_mulaafp24s_hh_ll,
- ICLASS_ae_iclass_mulaap24s_hh_ll,
- ICLASS_ae_iclass_mulaafp24s_hl_lh,
- ICLASS_ae_iclass_mulaap24s_hl_lh,
- ICLASS_ae_iclass_mulasfp24s_hh_ll,
- ICLASS_ae_iclass_mulasp24s_hh_ll,
- ICLASS_ae_iclass_mulasfp24s_hl_lh,
- ICLASS_ae_iclass_mulasp24s_hl_lh,
- ICLASS_ae_iclass_mulsafp24s_hh_ll,
- ICLASS_ae_iclass_mulsap24s_hh_ll,
- ICLASS_ae_iclass_mulsafp24s_hl_lh,
- ICLASS_ae_iclass_mulsap24s_hl_lh,
- ICLASS_ae_iclass_mulssfp24s_hh_ll,
- ICLASS_ae_iclass_mulssp24s_hh_ll,
- ICLASS_ae_iclass_mulssfp24s_hl_lh,
- ICLASS_ae_iclass_mulssp24s_hl_lh,
- ICLASS_ae_iclass_sha32,
- ICLASS_ae_iclass_vldl32t,
- ICLASS_ae_iclass_vldl16t,
- ICLASS_ae_iclass_vldl16c,
- ICLASS_ae_iclass_vldsht,
- ICLASS_ae_iclass_lb,
- ICLASS_ae_iclass_lbi,
- ICLASS_ae_iclass_lbk,
- ICLASS_ae_iclass_lbki,
- ICLASS_ae_iclass_db,
- ICLASS_ae_iclass_dbi,
- ICLASS_ae_iclass_vlel32t,
- ICLASS_ae_iclass_vlel16t,
- ICLASS_ae_iclass_sb,
- ICLASS_ae_iclass_sbi,
- ICLASS_ae_iclass_vles16c,
- ICLASS_ae_iclass_sbf
-};
-
-\f
-/* Opcode encodings. */
-
-static void
-Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2080;
-}
-
-static void
-Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000;
-}
-
-static void
-Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3200;
-}
-
-static void
-Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5000;
-}
-
-static void
-Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35;
-}
-
-static void
-Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x25;
-}
-
-static void
-Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15;
-}
-
-static void
-Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf0;
-}
-
-static void
-Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe0;
-}
-
-static void
-Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd0;
-}
-
-static void
-Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36;
-}
-
-static void
-Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1000;
-}
-
-static void
-Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x408000;
-}
-
-static void
-Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90;
-}
-
-static void
-Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01d;
-}
-
-static void
-Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3400;
-}
-
-static void
-Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3500;
-}
-
-static void
-Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x90000;
-}
-
-static void
-Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x490000;
-}
-
-static void
-Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34800;
-}
-
-static void
-Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134800;
-}
-
-static void
-Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614800;
-}
-
-static void
-Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x34900;
-}
-
-static void
-Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x134900;
-}
-
-static void
-Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x614900;
-}
-
-static void
-Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa;
-}
-
-static void
-Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb;
-}
-
-static void
-Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8c;
-}
-
-static void
-Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcc;
-}
-
-static void
-Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf06d;
-}
-
-static void
-Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8;
-}
-
-static void
-Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd;
-}
-
-static void
-Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc;
-}
-
-static void
-Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf03d;
-}
-
-static void
-Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00d;
-}
-
-static void
-Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9;
-}
-
-static void
-Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30e70;
-}
-
-static void
-Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3e700;
-}
-
-static void
-Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc002;
-}
-
-static void
-Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200040;
-}
-
-static void
-Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd002;
-}
-
-static void
-Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200080;
-}
-
-static void
-Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x800000;
-}
-
-static void
-Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b2000;
-}
-
-static void
-Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc00000;
-}
-
-static void
-Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ca000;
-}
-
-static void
-Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x900000;
-}
-
-static void
-Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b4000;
-}
-
-static void
-Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00000;
-}
-
-static void
-Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b8000;
-}
-
-static void
-Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00000;
-}
-
-static void
-Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b3000;
-}
-
-static void
-Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd00000;
-}
-
-static void
-Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1cc000;
-}
-
-static void
-Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00000;
-}
-
-static void
-Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1cb000;
-}
-
-static void
-Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00000;
-}
-
-static void
-Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1cd000;
-}
-
-static void
-Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b5000;
-}
-
-static void
-Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e0000;
-}
-
-static void
-Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300000;
-}
-
-static void
-Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ce000;
-}
-
-static void
-Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x26;
-}
-
-static void
-Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300000;
-}
-
-static void
-Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x66;
-}
-
-static void
-Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300003;
-}
-
-static void
-Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe6;
-}
-
-static void
-Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300001;
-}
-
-static void
-Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa6;
-}
-
-static void
-Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300004;
-}
-
-static void
-Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6007;
-}
-
-static void
-Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200000;
-}
-
-static void
-Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe007;
-}
-
-static void
-Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200020;
-}
-
-static void
-Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf6;
-}
-
-static void
-Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300002;
-}
-
-static void
-Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb6;
-}
-
-static void
-Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300008;
-}
-
-static void
-Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1007;
-}
-
-static void
-Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000a0;
-}
-
-static void
-Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9007;
-}
-
-static void
-Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400000;
-}
-
-static void
-Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa007;
-}
-
-static void
-Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000c0;
-}
-
-static void
-Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2007;
-}
-
-static void
-Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000d0;
-}
-
-static void
-Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb007;
-}
-
-static void
-Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000b0;
-}
-
-static void
-Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3007;
-}
-
-static void
-Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000e0;
-}
-
-static void
-Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8007;
-}
-
-static void
-Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200060;
-}
-
-static void
-Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7;
-}
-
-static void
-Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400010;
-}
-
-static void
-Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4007;
-}
-
-static void
-Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200050;
-}
-
-static void
-Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc007;
-}
-
-static void
-Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000f0;
-}
-
-static void
-Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5007;
-}
-
-static void
-Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200070;
-}
-
-static void
-Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd007;
-}
-
-static void
-Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x200090;
-}
-
-static void
-Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16;
-}
-
-static void
-Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x180000;
-}
-
-static void
-Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x56;
-}
-
-static void
-Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x190000;
-}
-
-static void
-Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd6;
-}
-
-static void
-Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x160000;
-}
-
-static void
-Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x96;
-}
-
-static void
-Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x170000;
-}
-
-static void
-Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5;
-}
-
-static void
-Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc0;
-}
-
-static void
-Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000;
-}
-
-static void
-Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x140000;
-}
-
-static void
-Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0;
-}
-
-static void
-Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6;
-}
-
-static void
-Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x100000;
-}
-
-static void
-Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa0;
-}
-
-static void
-Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee031;
-}
-
-static void
-Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1002;
-}
-
-static void
-Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400040;
-}
-
-static void
-Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9002;
-}
-
-static void
-Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400020;
-}
-
-static void
-Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2002;
-}
-
-static void
-Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400080;
-}
-
-static void
-Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1;
-}
-
-static void
-Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500000;
-}
-
-static void
-Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2;
-}
-
-static void
-Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400030;
-}
-
-static void
-Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8076;
-}
-
-static void
-Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9076;
-}
-
-static void
-Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa076;
-}
-
-static void
-Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa002;
-}
-
-static void
-Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1a0000;
-}
-
-static void
-Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x830000;
-}
-
-static void
-Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1be000;
-}
-
-static void
-Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x930000;
-}
-
-static void
-Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c8000;
-}
-
-static void
-Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa30000;
-}
-
-static void
-Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c4000;
-}
-
-static void
-Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb30000;
-}
-
-static void
-Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c2000;
-}
-
-static void
-Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600000;
-}
-
-static void
-Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1d00;
-}
-
-static void
-Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x600100;
-}
-
-static void
-Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1c00;
-}
-
-static void
-Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20f0;
-}
-
-static void
-Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16105;
-}
-
-static void
-Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee0b1;
-}
-
-static void
-Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x80;
-}
-
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5100;
-}
-
-static void
-Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5002;
-}
-
-static void
-Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400050;
-}
-
-static void
-Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6002;
-}
-
-static void
-Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400060;
-}
-
-static void
-Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4002;
-}
-
-static void
-Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400070;
-}
-
-static void
-Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x400000;
-}
-
-static void
-Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee071;
-}
-
-static void
-Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x401000;
-}
-
-static void
-Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee038;
-}
-
-static void
-Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x402000;
-}
-
-static void
-Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee034;
-}
-
-static void
-Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x403000;
-}
-
-static void
-Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee032;
-}
-
-static void
-Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x404000;
-}
-
-static void
-Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ef0a0;
-}
-
-static void
-Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa10000;
-}
-
-static void
-Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f5003;
-}
-
-static void
-Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x810000;
-}
-
-static void
-Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c7000;
-}
-
-static void
-Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x910000;
-}
-
-static void
-Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1f00;
-}
-
-static void
-Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb10000;
-}
-
-static void
-Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1e00;
-}
-
-static void
-Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10000;
-}
-
-static void
-Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c0000;
-}
-
-static void
-Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x210000;
-}
-
-static void
-Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b0000;
-}
-
-static void
-Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x410000;
-}
-
-static void
-Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c9000;
-}
-
-static void
-Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20c0;
-}
-
-static void
-Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20d0;
-}
-
-static void
-Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000;
-}
-
-static void
-Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2010;
-}
-
-static void
-Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2020;
-}
-
-static void
-Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2030;
-}
-
-static void
-Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000;
-}
-
-static void
-Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30100;
-}
-
-static void
-Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130100;
-}
-
-static void
-Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610100;
-}
-
-static void
-Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30200;
-}
-
-static void
-Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130200;
-}
-
-static void
-Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610200;
-}
-
-static void
-Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130000;
-}
-
-static void
-Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610000;
-}
-
-static void
-Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30300;
-}
-
-static void
-Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130300;
-}
-
-static void
-Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610300;
-}
-
-static void
-Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30500;
-}
-
-static void
-Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130500;
-}
-
-static void
-Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610500;
-}
-
-static void
-Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b000;
-}
-
-static void
-Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b000;
-}
-
-static void
-Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d000;
-}
-
-static void
-Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e600;
-}
-
-static void
-Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e600;
-}
-
-static void
-Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e600;
-}
-
-static void
-Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b100;
-}
-
-static void
-Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b100;
-}
-
-static void
-Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b100;
-}
-
-static void
-Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d100;
-}
-
-static void
-Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d100;
-}
-
-static void
-Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d100;
-}
-
-static void
-Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3b200;
-}
-
-static void
-Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13b200;
-}
-
-static void
-Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61b200;
-}
-
-static void
-Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3d200;
-}
-
-static void
-Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13d200;
-}
-
-static void
-Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61d200;
-}
-
-static void
-Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c200;
-}
-
-static void
-Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c200;
-}
-
-static void
-Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c200;
-}
-
-static void
-Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ee00;
-}
-
-static void
-Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ee00;
-}
-
-static void
-Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ee00;
-}
-
-static void
-Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3c000;
-}
-
-static void
-Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13c000;
-}
-
-static void
-Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61c000;
-}
-
-static void
-Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e800;
-}
-
-static void
-Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e800;
-}
-
-static void
-Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e800;
-}
-
-static void
-Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f400;
-}
-
-static void
-Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f400;
-}
-
-static void
-Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f400;
-}
-
-static void
-Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f500;
-}
-
-static void
-Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f500;
-}
-
-static void
-Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f500;
-}
-
-static void
-Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3eb00;
-}
-
-static void
-Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e700;
-}
-
-static void
-Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e700;
-}
-
-static void
-Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e700;
-}
-
-static void
-Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc10000;
-}
-
-static void
-Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd10000;
-}
-
-static void
-Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x820000;
-}
-
-static void
-Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3010;
-}
-
-static void
-Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7000;
-}
-
-static void
-Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e200;
-}
-
-static void
-Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e200;
-}
-
-static void
-Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e300;
-}
-
-static void
-Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e400;
-}
-
-static void
-Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e400;
-}
-
-static void
-Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e400;
-}
-
-static void
-Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000;
-}
-
-static void
-Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf02d;
-}
-
-static void
-Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e900;
-}
-
-static void
-Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e900;
-}
-
-static void
-Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e900;
-}
-
-static void
-Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ec00;
-}
-
-static void
-Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ec00;
-}
-
-static void
-Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ec00;
-}
-
-static void
-Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ed00;
-}
-
-static void
-Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ed00;
-}
-
-static void
-Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ed00;
-}
-
-static void
-Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36800;
-}
-
-static void
-Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136800;
-}
-
-static void
-Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616800;
-}
-
-static void
-Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e000;
-}
-
-static void
-Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1e010;
-}
-
-static void
-Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20000;
-}
-
-static void
-Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b6000;
-}
-
-static void
-Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x120000;
-}
-
-static void
-Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b7000;
-}
-
-static void
-Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x220000;
-}
-
-static void
-Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c3000;
-}
-
-static void
-Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x320000;
-}
-
-static void
-Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c5000;
-}
-
-static void
-Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x420000;
-}
-
-static void
-Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1cf000;
-}
-
-static void
-Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x8000;
-}
-
-static void
-Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2480;
-}
-
-static void
-Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x9000;
-}
-
-static void
-Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2800;
-}
-
-static void
-Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa000;
-}
-
-static void
-Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ef060;
-}
-
-static void
-Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb000;
-}
-
-static void
-Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ef020;
-}
-
-static void
-Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x76;
-}
-
-static void
-Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300005;
-}
-
-static void
-Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1076;
-}
-
-static void
-Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x300006;
-}
-
-static void
-Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc30000;
-}
-
-static void
-Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1bf000;
-}
-
-static void
-Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xd30000;
-}
-
-static void
-Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d0000;
-}
-
-static void
-Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30400;
-}
-
-static void
-Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130400;
-}
-
-static void
-Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610400;
-}
-
-static void
-Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3ea00;
-}
-
-static void
-Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13ea00;
-}
-
-static void
-Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61ea00;
-}
-
-static void
-Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f000;
-}
-
-static void
-Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f000;
-}
-
-static void
-Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f000;
-}
-
-static void
-Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3f100;
-}
-
-static void
-Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13f100;
-}
-
-static void
-Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61f100;
-}
-
-static void
-Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70c2;
-}
-
-static void
-Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70e2;
-}
-
-static void
-Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x70f2;
-}
-
-static void
-Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf10000;
-}
-
-static void
-Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf12000;
-}
-
-static void
-Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf11000;
-}
-
-static void
-Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf13000;
-}
-
-static void
-Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7042;
-}
-
-static void
-Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7052;
-}
-
-static void
-Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x47082;
-}
-
-static void
-Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x57082;
-}
-
-static void
-Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7062;
-}
-
-static void
-Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7072;
-}
-
-static void
-Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7002;
-}
-
-static void
-Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7012;
-}
-
-static void
-Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7022;
-}
-
-static void
-Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x7032;
-}
-
-static void
-Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf19000;
-}
-
-static void
-Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf18000;
-}
-
-static void
-Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135300;
-}
-
-static void
-Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35300;
-}
-
-static void
-Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615300;
-}
-
-static void
-Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35a00;
-}
-
-static void
-Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135a00;
-}
-
-static void
-Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615a00;
-}
-
-static void
-Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35b00;
-}
-
-static void
-Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135b00;
-}
-
-static void
-Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615b00;
-}
-
-static void
-Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x35c00;
-}
-
-static void
-Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x135c00;
-}
-
-static void
-Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x615c00;
-}
-
-static void
-Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50c000;
-}
-
-static void
-Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50d000;
-}
-
-static void
-Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50b000;
-}
-
-static void
-Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50f000;
-}
-
-static void
-Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50e000;
-}
-
-static void
-Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x504000;
-}
-
-static void
-Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x505000;
-}
-
-static void
-Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x503000;
-}
-
-static void
-Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x507000;
-}
-
-static void
-Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x506000;
-}
-
-static void
-Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf1f000;
-}
-
-static void
-Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x501000;
-}
-
-static void
-Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x509000;
-}
-
-static void
-Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3e000;
-}
-
-static void
-Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x13e000;
-}
-
-static void
-Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x61e000;
-}
-
-static void
-Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x330000;
-}
-
-static void
-Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1b9000;
-}
-
-static void
-Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x430000;
-}
-
-static void
-Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1bb000;
-}
-
-static void
-Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x530000;
-}
-
-static void
-Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ba000;
-}
-
-static void
-Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x630000;
-}
-
-static void
-Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1bd000;
-}
-
-static void
-Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x730000;
-}
-
-static void
-Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1bc000;
-}
-
-static void
-Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40e000;
-}
-
-static void
-Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40f000;
-}
-
-static void
-Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x230000;
-}
-
-static void
-Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c6000;
-}
-
-static void
-Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb002;
-}
-
-static void
-Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf002;
-}
-
-static void
-Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe002;
-}
-
-static void
-Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30c00;
-}
-
-static void
-Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x130c00;
-}
-
-static void
-Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x610c00;
-}
-
-static void
-Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x36300;
-}
-
-static void
-Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x136300;
-}
-
-static void
-Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x616300;
-}
-
-static void
-Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x406000;
-}
-
-static void
-Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x407000;
-}
-
-static void
-Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30f00;
-}
-
-static void
-Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3f000;
-}
-
-static void
-Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30f10;
-}
-
-static void
-Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3f100;
-}
-
-static void
-Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30f20;
-}
-
-static void
-Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3f200;
-}
-
-static void
-Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30f30;
-}
-
-static void
-Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf3f300;
-}
-
-static void
-Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90804;
-}
-
-static void
-Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca0004;
-}
-
-static void
-Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90904;
-}
-
-static void
-Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca1004;
-}
-
-static void
-Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90a04;
-}
-
-static void
-Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca2004;
-}
-
-static void
-Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90b04;
-}
-
-static void
-Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca3004;
-}
-
-static void
-Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90c04;
-}
-
-static void
-Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca4004;
-}
-
-static void
-Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90d04;
-}
-
-static void
-Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca5004;
-}
-
-static void
-Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90e04;
-}
-
-static void
-Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca6004;
-}
-
-static void
-Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90f04;
-}
-
-static void
-Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca7004;
-}
-
-static void
-Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d1080;
-}
-
-static void
-Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa50004;
-}
-
-static void
-Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d2080;
-}
-
-static void
-Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa90004;
-}
-
-static void
-Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d3000;
-}
-
-static void
-Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xac0004;
-}
-
-static void
-Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d3080;
-}
-
-static void
-Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xaf0004;
-}
-
-static void
-Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d6080;
-}
-
-static void
-Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa58004;
-}
-
-static void
-Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d7000;
-}
-
-static void
-Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa98004;
-}
-
-static void
-Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d7080;
-}
-
-static void
-Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xac8004;
-}
-
-static void
-Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d8080;
-}
-
-static void
-Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xaf8004;
-}
-
-static void
-Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d9000;
-}
-
-static void
-Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa60004;
-}
-
-static void
-Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1da000;
-}
-
-static void
-Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xaa0004;
-}
-
-static void
-Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1dc000;
-}
-
-static void
-Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xad0004;
-}
-
-static void
-Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d9080;
-}
-
-static void
-Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb00004;
-}
-
-static void
-Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d4080;
-}
-
-static void
-Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa68004;
-}
-
-static void
-Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d5000;
-}
-
-static void
-Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xaa8004;
-}
-
-static void
-Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d6000;
-}
-
-static void
-Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xad8004;
-}
-
-static void
-Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d5080;
-}
-
-static void
-Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb08004;
-}
-
-static void
-Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1dd000;
-}
-
-static void
-Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa70004;
-}
-
-static void
-Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1de000;
-}
-
-static void
-Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xab0004;
-}
-
-static void
-Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1dd080;
-}
-
-static void
-Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xae0004;
-}
-
-static void
-Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1de080;
-}
-
-static void
-Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb10004;
-}
-
-static void
-Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1da080;
-}
-
-static void
-Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa78004;
-}
-
-static void
-Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1db000;
-}
-
-static void
-Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xab8004;
-}
-
-static void
-Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1db080;
-}
-
-static void
-Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xae8004;
-}
-
-static void
-Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1dc080;
-}
-
-static void
-Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb18004;
-}
-
-static void
-Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e8000;
-}
-
-static void
-Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb20004;
-}
-
-static void
-Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f0000;
-}
-
-static void
-Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb50004;
-}
-
-static void
-Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e1080;
-}
-
-static void
-Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb80004;
-}
-
-static void
-Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e2080;
-}
-
-static void
-Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbb0004;
-}
-
-static void
-Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ec000;
-}
-
-static void
-Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb28004;
-}
-
-static void
-Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e9080;
-}
-
-static void
-Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb58004;
-}
-
-static void
-Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ea080;
-}
-
-static void
-Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb88004;
-}
-
-static void
-Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1eb000;
-}
-
-static void
-Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbb8004;
-}
-
-static void
-Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e7080;
-}
-
-static void
-Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb30004;
-}
-
-static void
-Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e8080;
-}
-
-static void
-Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb60004;
-}
-
-static void
-Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e9000;
-}
-
-static void
-Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb90004;
-}
-
-static void
-Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ea000;
-}
-
-static void
-Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbc0004;
-}
-
-static void
-Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1df080;
-}
-
-static void
-Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb38004;
-}
-
-static void
-Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e1000;
-}
-
-static void
-Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb68004;
-}
-
-static void
-Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e2000;
-}
-
-static void
-Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb98004;
-}
-
-static void
-Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e4000;
-}
-
-static void
-Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbc8004;
-}
-
-static void
-Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e6000;
-}
-
-static void
-Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb40004;
-}
-
-static void
-Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e5080;
-}
-
-static void
-Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb70004;
-}
-
-static void
-Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e6080;
-}
-
-static void
-Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xba0004;
-}
-
-static void
-Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e7000;
-}
-
-static void
-Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbd0004;
-}
-
-static void
-Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e3000;
-}
-
-static void
-Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb48004;
-}
-
-static void
-Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e3080;
-}
-
-static void
-Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xb78004;
-}
-
-static void
-Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e4080;
-}
-
-static void
-Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xba8004;
-}
-
-static void
-Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1e5000;
-}
-
-static void
-Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbd8004;
-}
-
-static void
-Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ed030;
-}
-
-static void
-Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc10004;
-}
-
-static void
-Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee010;
-}
-
-static void
-Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc12004;
-}
-
-static void
-Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee020;
-}
-
-static void
-Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc20004;
-}
-
-static void
-Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ef000;
-}
-
-static void
-Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc22004;
-}
-
-static void
-Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ed000;
-}
-
-static void
-Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc11004;
-}
-
-static void
-Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee000;
-}
-
-static void
-Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc13004;
-}
-
-static void
-Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ed010;
-}
-
-static void
-Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc21004;
-}
-
-static void
-Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ed020;
-}
-
-static void
-Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc23004;
-}
-
-static void
-Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f0080;
-}
-
-static void
-Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc30004;
-}
-
-static void
-Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f00c0;
-}
-
-static void
-Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc38004;
-}
-
-static void
-Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3000;
-}
-
-static void
-Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc40004;
-}
-
-static void
-Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3040;
-}
-
-static void
-Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc48004;
-}
-
-static void
-Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ec080;
-}
-
-static void
-Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc34004;
-}
-
-static void
-Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ec0c0;
-}
-
-static void
-Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc3c004;
-}
-
-static void
-Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f4000;
-}
-
-static void
-Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc44004;
-}
-
-static void
-Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f8000;
-}
-
-static void
-Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc4c004;
-}
-
-static void
-Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16b88;
-}
-
-static void
-Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16808;
-}
-
-static void
-Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2400;
-}
-
-static void
-Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90004;
-}
-
-static void
-Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10780;
-}
-
-static void
-Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10708;
-}
-
-static void
-Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10688;
-}
-
-static void
-Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10700;
-}
-
-static void
-Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c200;
-}
-
-static void
-Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c004;
-}
-
-static void
-Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10480;
-}
-
-static void
-Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10400;
-}
-
-static void
-Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1df000;
-}
-
-static void
-Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc00004;
-}
-
-static void
-Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1eb080;
-}
-
-static void
-Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc08004;
-}
-
-static void
-Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3081;
-}
-
-static void
-Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcb0004;
-}
-
-static void
-Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3080;
-}
-
-static void
-Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xcb8004;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d8000;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbe0004;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d4000;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbe8004;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d2000;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbf0004;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1d1000;
-}
-
-static void
-Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xbf8004;
-}
-
-static void
-Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x51000;
-}
-
-static void
-Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16b08;
-}
-
-static void
-Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16e48;
-}
-
-static void
-Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16e28;
-}
-
-static void
-Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16e18;
-}
-
-static void
-Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16e08;
-}
-
-static void
-Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16908;
-}
-
-static void
-Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16888;
-}
-
-static void
-Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16085;
-}
-
-static void
-Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16007;
-}
-
-static void
-Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2500;
-}
-
-static void
-Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90414;
-}
-
-static void
-Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f6000;
-}
-
-static void
-Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe50014;
-}
-
-static void
-Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f5000;
-}
-
-static void
-Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe60014;
-}
-
-static void
-Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1ee030;
-}
-
-static void
-Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe72034;
-}
-
-static void
-Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16006;
-}
-
-static void
-Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16005;
-}
-
-static void
-Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50139;
-}
-
-static void
-Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16047;
-}
-
-static void
-Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16027;
-}
-
-static void
-Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16017;
-}
-
-static void
-Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3086;
-}
-
-static void
-Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe70014;
-}
-
-static void
-Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3084;
-}
-
-static void
-Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc70004;
-}
-
-static void
-Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3082;
-}
-
-static void
-Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc78004;
-}
-
-static void
-Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3083;
-}
-
-static void
-Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc80004;
-}
-
-static void
-Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3088;
-}
-
-static void
-Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc88004;
-}
-
-static void
-Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10500;
-}
-
-static void
-Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10788;
-}
-
-static void
-Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c600;
-}
-
-static void
-Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c480;
-}
-
-static void
-Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10580;
-}
-
-static void
-Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10588;
-}
-
-static void
-Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10000;
-}
-
-static void
-Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10200;
-}
-
-static void
-Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10600;
-}
-
-static void
-Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c400;
-}
-
-static void
-Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c488;
-}
-
-static void
-Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c500;
-}
-
-static void
-Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10508;
-}
-
-static void
-Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10608;
-}
-
-static void
-Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x10680;
-}
-
-static void
-Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c408;
-}
-
-static void
-Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c002;
-}
-
-static void
-Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c001;
-}
-
-static void
-Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1c000;
-}
-
-static void
-Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x52000;
-}
-
-static void
-Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50035;
-}
-
-static void
-Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5003c;
-}
-
-static void
-Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50039;
-}
-
-static void
-Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50032;
-}
-
-static void
-Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50034;
-}
-
-static void
-Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50000;
-}
-
-static void
-Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50010;
-}
-
-static void
-Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50030;
-}
-
-static void
-Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50036;
-}
-
-static void
-Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x500b9;
-}
-
-static void
-Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x5003a;
-}
-
-static void
-Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50031;
-}
-
-static void
-Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50038;
-}
-
-static void
-Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50033;
-}
-
-static void
-Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50037;
-}
-
-static void
-Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x14000;
-}
-
-static void
-Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15000;
-}
-
-static void
-Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x14800;
-}
-
-static void
-Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16a08;
-}
-
-static void
-Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16a88;
-}
-
-static void
-Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16988;
-}
-
-static void
-Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x18000;
-}
-
-static void
-Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16c08;
-}
-
-static void
-Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1000;
-}
-
-static void
-Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc50004;
-}
-
-static void
-Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1800;
-}
-
-static void
-Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc50404;
-}
-
-static void
-Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f1400;
-}
-
-static void
-Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc50804;
-}
-
-static void
-Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2600;
-}
-
-static void
-Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90014;
-}
-
-static void
-Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2504;
-}
-
-static void
-Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90114;
-}
-
-static void
-Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2502;
-}
-
-static void
-Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90214;
-}
-
-static void
-Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f5001;
-}
-
-static void
-Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe10014;
-}
-
-static void
-Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f5008;
-}
-
-static void
-Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe20014;
-}
-
-static void
-Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f5004;
-}
-
-static void
-Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe30014;
-}
-
-static void
-Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2000;
-}
-
-static void
-Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc50c04;
-}
-
-static void
-Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f2501;
-}
-
-static void
-Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc90314;
-}
-
-static void
-Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f5002;
-}
-
-static void
-Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe40014;
-}
-
-static void
-Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50800;
-}
-
-static void
-Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50040;
-}
-
-static void
-Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x50020;
-}
-
-static void
-Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1f3085;
-}
-
-static void
-Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe74014;
-}
-
-static void
-Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60101;
-}
-
-static void
-Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6008b;
-}
-
-static void
-Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60180;
-}
-
-static void
-Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6008f;
-}
-
-static void
-Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6008c;
-}
-
-static void
-Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60108;
-}
-
-static void
-Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6008e;
-}
-
-static void
-Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6008a;
-}
-
-static void
-Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60104;
-}
-
-static void
-Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6008d;
-}
-
-static void
-Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60089;
-}
-
-static void
-Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60102;
-}
-
-static void
-Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60006;
-}
-
-static void
-Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64000;
-}
-
-static void
-Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000f;
-}
-
-static void
-Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60005;
-}
-
-static void
-Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60100;
-}
-
-static void
-Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000e;
-}
-
-static void
-Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60003;
-}
-
-static void
-Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60080;
-}
-
-static void
-Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000d;
-}
-
-static void
-Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x68000;
-}
-
-static void
-Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60008;
-}
-
-static void
-Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000b;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60181;
-}
-
-static void
-Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6010b;
-}
-
-static void
-Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60189;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6010f;
-}
-
-static void
-Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6010c;
-}
-
-static void
-Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60187;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6010e;
-}
-
-static void
-Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6010a;
-}
-
-static void
-Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60186;
-}
-
-static void
-Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6010d;
-}
-
-static void
-Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60109;
-}
-
-static void
-Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60185;
-}
-
-static void
-Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000c;
-}
-
-static void
-Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60088;
-}
-
-static void
-Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6000a;
-}
-
-static void
-Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60084;
-}
-
-static void
-Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60009;
-}
-
-static void
-Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60082;
-}
-
-static void
-Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60007;
-}
-
-static void
-Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60081;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60183;
-}
-
-static void
-Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6018d;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60188;
-}
-
-static void
-Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6018b;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60184;
-}
-
-static void
-Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6018c;
-}
-
-static void
-Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60182;
-}
-
-static void
-Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6018a;
-}
-
-static void
-Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15807;
-}
-
-static void
-Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15806;
-}
-
-static void
-Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1580a;
-}
-
-static void
-Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15809;
-}
-
-static void
-Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1580b;
-}
-
-static void
-Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1580c;
-}
-
-static void
-Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1580e;
-}
-
-static void
-Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1580d;
-}
-
-static void
-Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15800;
-}
-
-static void
-Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16000;
-}
-
-static void
-Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15802;
-}
-
-static void
-Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15801;
-}
-
-static void
-Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15808;
-}
-
-static void
-Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15804;
-}
-
-static void
-Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15805;
-}
-
-static void
-Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x15803;
-}
-
-static void
-Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16001;
-}
-
-static void
-Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x1580f;
-}
-
-static void
-Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16004;
-}
-
-static void
-Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16002;
-}
-
-static void
-Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16800;
-}
-
-static void
-Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16008;
-}
-
-static void
-Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x16003;
-}
-
-static void
-Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x17000;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20007;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20002;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000c;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20003;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20005;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20000;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20009;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20004;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20006;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20001;
-}
-
-static void
-Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000a;
-}
-
-static void
-Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x20008;
-}
-
-static void
-Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30008;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000e;
-}
-
-static void
-Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30006;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30001;
-}
-
-static void
-Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30002;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000b;
-}
-
-static void
-Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30003;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000f;
-}
-
-static void
-Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30004;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x2000d;
-}
-
-static void
-Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30005;
-}
-
-static void
-Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30000;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40000;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000a;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40004;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000d;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000e;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30007;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40001;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000c;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000f;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x30009;
-}
-
-static void
-Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40002;
-}
-
-static void
-Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x3000b;
-}
-
-static void
-Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000b;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40005;
-}
-
-static void
-Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000f;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40009;
-}
-
-static void
-Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000a;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40008;
-}
-
-static void
-Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000d;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40006;
-}
-
-static void
-Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000c;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40003;
-}
-
-static void
-Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x4000e;
-}
-
-static void
-Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x40007;
-}
-
-static void
-Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64004;
-}
-
-static void
-Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64080;
-}
-
-static void
-Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64008;
-}
-
-static void
-Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64100;
-}
-
-static void
-Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64003;
-}
-
-static void
-Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64006;
-}
-
-static void
-Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64005;
-}
-
-static void
-Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64007;
-}
-
-static void
-Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64009;
-}
-
-static void
-Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6400c;
-}
-
-static void
-Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6400a;
-}
-
-static void
-Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6400b;
-}
-
-static void
-Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6400d;
-}
-
-static void
-Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6400f;
-}
-
-static void
-Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6400e;
-}
-
-static void
-Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64081;
-}
-
-static void
-Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60000;
-}
-
-static void
-Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60002;
-}
-
-static void
-Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60001;
-}
-
-static void
-Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60004;
-}
-
-static void
-Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60083;
-}
-
-static void
-Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60086;
-}
-
-static void
-Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60085;
-}
-
-static void
-Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60087;
-}
-
-static void
-Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60103;
-}
-
-static void
-Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60106;
-}
-
-static void
-Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60105;
-}
-
-static void
-Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x60107;
-}
-
-static void
-Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6018e;
-}
-
-static void
-Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64001;
-}
-
-static void
-Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x6018f;
-}
-
-static void
-Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0x64002;
-}
-
-static void
-Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00014;
-}
-
-static void
-Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa00004;
-}
-
-static void
-Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa10004;
-}
-
-static void
-Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe7e014;
-}
-
-static void
-Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xca8004;
-}
-
-static void
-Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xc60004;
-}
-
-static void
-Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00024;
-}
-
-static void
-Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa20004;
-}
-
-static void
-Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe00004;
-}
-
-static void
-Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf01004;
-}
-
-static void
-Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf02004;
-}
-
-static void
-Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa30004;
-}
-
-static void
-Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xa40004;
-}
-
-static void
-Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf11004;
-}
-
-static void
-Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xf00004;
-}
-
-static void
-Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe7c014;
-}
-
-static void
-Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
- slotbuf[0] = 0xe7d014;
-}
-
-static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
- Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
- Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
- Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
- Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
- Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
- Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
- Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
- Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
- Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
- Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
- Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
- Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
- Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
- Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
- Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
- Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
- Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
- Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
- Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
- Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
- Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
- Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
- Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
- Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
- Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
- Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
- Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
- Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
- Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
- Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
- Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
- Opcode_rer_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
- Opcode_wer_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = {
- Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = {
- Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = {
- Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = {
- Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = {
- Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = {
- Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = {
- Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = {
- Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = {
- Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = {
- Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = {
- Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = {
- Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = {
- Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = {
- Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = {
- Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = {
- Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = {
- Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = {
- Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = {
- Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = {
- Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = {
- Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = {
- Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = {
- Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = {
- Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = {
- Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = {
- Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = {
- Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = {
- Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = {
- Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = {
- Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = {
- Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = {
- Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = {
- Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = {
- Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = {
- Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = {
- Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = {
- Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = {
- Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = {
- Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = {
- Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = {
- Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = {
- Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = {
- Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = {
- Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = {
- Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = {
- Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = {
- Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = {
- Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = {
- Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = {
- Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = {
- Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = {
- Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = {
- Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = {
- Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = {
- Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = {
- Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = {
- Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = {
- Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = {
- Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = {
- Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = {
- Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = {
- Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = {
- Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = {
- Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = {
- Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = {
- Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = {
- Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = {
- Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = {
- Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = {
- Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = {
- Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = {
- Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = {
- Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = {
- Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = {
- Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = {
- Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = {
- Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = {
- Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = {
- Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = {
- Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = {
- Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = {
- Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = {
- Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = {
- Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = {
- Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = {
- Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = {
- Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = {
- Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = {
- Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = {
- Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = {
- Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = {
- Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = {
- Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = {
- Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = {
- 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = {
- 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = {
- Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = {
- Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = {
- Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = {
- Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = {
- 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = {
- 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = {
- Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = {
- Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = {
- Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = {
- Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = {
- Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = {
- 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = {
- 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = {
- Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = {
- Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = {
- Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = {
- Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = {
- Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = {
- Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = {
- Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = {
- Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = {
- Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = {
- Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = {
- Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = {
- Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = {
- 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = {
- 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = {
- Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = {
- 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = {
- Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = {
- Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = {
- Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = {
- Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = {
- Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = {
- Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = {
- Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = {
- Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = {
- Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = {
- Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = {
- Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = {
- Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = {
- Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = {
- Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = {
- Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = {
- Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0
-};
-
-static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = {
- Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0
-};
-
-\f
-/* Opcode table. */
-
-static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_shift32x5, 3 },
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_shift32x5, 3 },
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = {
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = {
- { FUNCUNIT_ae_add32, 3 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = {
- { FUNCUNIT_ae_shift32x4, 2 },
- { FUNCUNIT_ae_subshift, 2 }
-};
-
-static xtensa_opcode_internal opcodes[] = {
- { "excw", ICLASS_xt_iclass_excw,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", ICLASS_xt_iclass_rfe,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", ICLASS_xt_iclass_rfde,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", ICLASS_xt_iclass_syscall,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "call12", ICLASS_xt_iclass_call12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", ICLASS_xt_iclass_call8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", ICLASS_xt_iclass_call4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", ICLASS_xt_iclass_callx12,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", ICLASS_xt_iclass_callx8,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", ICLASS_xt_iclass_callx4,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", ICLASS_xt_iclass_entry,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", ICLASS_xt_iclass_movsp,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", ICLASS_xt_iclass_rotw,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", ICLASS_xt_iclass_retw,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", ICLASS_xt_iclass_rfwou,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", ICLASS_xt_iclass_l32e,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", ICLASS_xt_iclass_s32e,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", ICLASS_xt_iclass_add_n,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", ICLASS_xt_iclass_addi_n,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", ICLASS_xt_iclass_bz6,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", ICLASS_xt_iclass_ill_n,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", ICLASS_xt_iclass_loadi4,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", ICLASS_xt_iclass_mov_n,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", ICLASS_xt_iclass_movi_n,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", ICLASS_xt_iclass_nopn,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", ICLASS_xt_iclass_retn,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", ICLASS_xt_iclass_storei4,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "rur.threadptr", ICLASS_rur_threadptr,
- 0,
- Opcode_rur_threadptr_encode_fns, 0, 0 },
- { "wur.threadptr", ICLASS_wur_threadptr,
- 0,
- Opcode_wur_threadptr_encode_fns, 0, 0 },
- { "addi", ICLASS_xt_iclass_addi,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", ICLASS_xt_iclass_addmi,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", ICLASS_xt_iclass_addsub,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", ICLASS_xt_iclass_bit,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", ICLASS_xt_iclass_bit,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", ICLASS_xt_iclass_bit,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", ICLASS_xt_iclass_bsi8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", ICLASS_xt_iclass_bsi8b,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", ICLASS_xt_iclass_bsi8u,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", ICLASS_xt_iclass_bst8,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", ICLASS_xt_iclass_bsz12,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", ICLASS_xt_iclass_call0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", ICLASS_xt_iclass_callx0,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", ICLASS_xt_iclass_exti,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", ICLASS_xt_iclass_ill,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", ICLASS_xt_iclass_jump,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", ICLASS_xt_iclass_jumpx,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", ICLASS_xt_iclass_l16ui,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", ICLASS_xt_iclass_l16si,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", ICLASS_xt_iclass_l32i,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", ICLASS_xt_iclass_l32r,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", ICLASS_xt_iclass_l8i,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", ICLASS_xt_iclass_loop,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", ICLASS_xt_iclass_loopz,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", ICLASS_xt_iclass_movi,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", ICLASS_xt_iclass_movz,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", ICLASS_xt_iclass_neg,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", ICLASS_xt_iclass_neg,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", ICLASS_xt_iclass_nop,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", ICLASS_xt_iclass_return,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "simcall", ICLASS_xt_iclass_simcall,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "s16i", ICLASS_xt_iclass_s16i,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", ICLASS_xt_iclass_s32i,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s8i", ICLASS_xt_iclass_s8i,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", ICLASS_xt_iclass_sar,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", ICLASS_xt_iclass_sari,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", ICLASS_xt_iclass_shifts,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", ICLASS_xt_iclass_shiftst,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", ICLASS_xt_iclass_shiftt,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", ICLASS_xt_iclass_slli,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", ICLASS_xt_iclass_srai,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", ICLASS_xt_iclass_srli,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", ICLASS_xt_iclass_memw,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", ICLASS_xt_iclass_extw,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", ICLASS_xt_iclass_isync,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", ICLASS_xt_iclass_sync,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", ICLASS_xt_iclass_rsil,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
- 0,
- Opcode_rsr_configid0_encode_fns, 0, 0 },
- { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
- 0,
- Opcode_wsr_configid0_encode_fns, 0, 0 },
- { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
- 0,
- Opcode_rsr_configid1_encode_fns, 0, 0 },
- { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "mul16u", ICLASS_xt_mul16,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", ICLASS_xt_mul16,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "mull", ICLASS_xt_mul32,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "rfi", ICLASS_xt_iclass_rfi,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", ICLASS_xt_iclass_wait,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", ICLASS_xt_iclass_break,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", ICLASS_xt_iclass_break_n,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "rfdo", ICLASS_xt_iclass_rfdo,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", ICLASS_xt_iclass_rfdd,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "andb", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_andb_encode_fns, 0, 0 },
- { "andbc", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_andbc_encode_fns, 0, 0 },
- { "orb", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_orb_encode_fns, 0, 0 },
- { "orbc", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_orbc_encode_fns, 0, 0 },
- { "xorb", ICLASS_xt_iclass_bbool1,
- 0,
- Opcode_xorb_encode_fns, 0, 0 },
- { "any4", ICLASS_xt_iclass_bbool4,
- 0,
- Opcode_any4_encode_fns, 0, 0 },
- { "all4", ICLASS_xt_iclass_bbool4,
- 0,
- Opcode_all4_encode_fns, 0, 0 },
- { "any8", ICLASS_xt_iclass_bbool8,
- 0,
- Opcode_any8_encode_fns, 0, 0 },
- { "all8", ICLASS_xt_iclass_bbool8,
- 0,
- Opcode_all8_encode_fns, 0, 0 },
- { "bf", ICLASS_xt_iclass_bbranch,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bf_encode_fns, 0, 0 },
- { "bt", ICLASS_xt_iclass_bbranch,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bt_encode_fns, 0, 0 },
- { "movf", ICLASS_xt_iclass_bmove,
- 0,
- Opcode_movf_encode_fns, 0, 0 },
- { "movt", ICLASS_xt_iclass_bmove,
- 0,
- Opcode_movt_encode_fns, 0, 0 },
- { "rsr.br", ICLASS_xt_iclass_RSR_BR,
- 0,
- Opcode_rsr_br_encode_fns, 0, 0 },
- { "wsr.br", ICLASS_xt_iclass_WSR_BR,
- 0,
- Opcode_wsr_br_encode_fns, 0, 0 },
- { "xsr.br", ICLASS_xt_iclass_XSR_BR,
- 0,
- Opcode_xsr_br_encode_fns, 0, 0 },
- { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "ipf", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", ICLASS_xt_iclass_icache,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "iii", ICLASS_xt_iclass_icache_inv,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", ICLASS_xt_iclass_licx,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", ICLASS_xt_iclass_licx,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", ICLASS_xt_iclass_sicx,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", ICLASS_xt_iclass_dcache,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwb", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", ICLASS_xt_iclass_dcache_ind,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", ICLASS_xt_iclass_dcache_inv,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", ICLASS_xt_iclass_dpf,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "sdct", ICLASS_xt_iclass_sdct,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", ICLASS_xt_iclass_ldct,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
- 0,
- Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
- 0,
- Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
- { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
- 0,
- Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
- 0,
- Opcode_rsr_rasid_encode_fns, 0, 0 },
- { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
- 0,
- Opcode_wsr_rasid_encode_fns, 0, 0 },
- { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
- 0,
- Opcode_xsr_rasid_encode_fns, 0, 0 },
- { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
- 0,
- Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
- { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
- 0,
- Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
- { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
- 0,
- Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
- { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
- 0,
- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
- { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
- 0,
- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
- { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
- 0,
- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
- { "idtlb", ICLASS_xt_iclass_idtlb,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", ICLASS_xt_iclass_rdtlb,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", ICLASS_xt_iclass_wdtlb,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", ICLASS_xt_iclass_iitlb,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", ICLASS_xt_iclass_ritlb,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", ICLASS_xt_iclass_witlb,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "ldpte", ICLASS_xt_iclass_ldpte,
- 0,
- Opcode_ldpte_encode_fns, 0, 0 },
- { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_hwwitlba_encode_fns, 0, 0 },
- { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
- 0,
- Opcode_hwwdtlba_encode_fns, 0, 0 },
- { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
- 0,
- Opcode_rsr_cpenable_encode_fns, 0, 0 },
- { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
- 0,
- Opcode_wsr_cpenable_encode_fns, 0, 0 },
- { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
- 0,
- Opcode_xsr_cpenable_encode_fns, 0, 0 },
- { "clamps", ICLASS_xt_iclass_clamp,
- 0,
- Opcode_clamps_encode_fns, 0, 0 },
- { "min", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", ICLASS_xt_iclass_minmax,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", ICLASS_xt_iclass_nsa,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", ICLASS_xt_iclass_sx,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", ICLASS_xt_iclass_l32ai,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", ICLASS_xt_iclass_s32ri,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", ICLASS_xt_iclass_s32c1i,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
- 0,
- Opcode_rsr_atomctl_encode_fns, 0, 0 },
- { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
- 0,
- Opcode_wsr_atomctl_encode_fns, 0, 0 },
- { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
- 0,
- Opcode_xsr_atomctl_encode_fns, 0, 0 },
- { "rer", ICLASS_xt_iclass_rer,
- 0,
- Opcode_rer_encode_fns, 0, 0 },
- { "wer", ICLASS_xt_iclass_wer,
- 0,
- Opcode_wer_encode_fns, 0, 0 },
- { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar,
- 0,
- Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 },
- { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar,
- 0,
- Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 },
- { "rur.ae_bithead", ICLASS_rur_ae_bithead,
- 0,
- Opcode_rur_ae_bithead_encode_fns, 0, 0 },
- { "wur.ae_bithead", ICLASS_wur_ae_bithead,
- 0,
- Opcode_wur_ae_bithead_encode_fns, 0, 0 },
- { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp,
- 0,
- Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
- { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp,
- 0,
- Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 },
- { "rur.ae_sd_no", ICLASS_rur_ae_sd_no,
- 0,
- Opcode_rur_ae_sd_no_encode_fns, 0, 0 },
- { "wur.ae_sd_no", ICLASS_wur_ae_sd_no,
- 0,
- Opcode_wur_ae_sd_no_encode_fns, 0, 0 },
- { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow,
- 0,
- Opcode_rur_ae_overflow_encode_fns, 0, 0 },
- { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow,
- 0,
- Opcode_wur_ae_overflow_encode_fns, 0, 0 },
- { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar,
- 0,
- Opcode_rur_ae_sar_encode_fns, 0, 0 },
- { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar,
- 0,
- Opcode_wur_ae_sar_encode_fns, 0, 0 },
- { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr,
- 0,
- Opcode_rur_ae_bitptr_encode_fns, 0, 0 },
- { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr,
- 0,
- Opcode_wur_ae_bitptr_encode_fns, 0, 0 },
- { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused,
- 0,
- Opcode_rur_ae_bitsused_encode_fns, 0, 0 },
- { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused,
- 0,
- Opcode_wur_ae_bitsused_encode_fns, 0, 0 },
- { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize,
- 0,
- Opcode_rur_ae_tablesize_encode_fns, 0, 0 },
- { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize,
- 0,
- Opcode_wur_ae_tablesize_encode_fns, 0, 0 },
- { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts,
- 0,
- Opcode_rur_ae_first_ts_encode_fns, 0, 0 },
- { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts,
- 0,
- Opcode_wur_ae_first_ts_encode_fns, 0, 0 },
- { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset,
- 0,
- Opcode_rur_ae_nextoffset_encode_fns, 0, 0 },
- { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset,
- 0,
- Opcode_wur_ae_nextoffset_encode_fns, 0, 0 },
- { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone,
- 0,
- Opcode_rur_ae_searchdone_encode_fns, 0, 0 },
- { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone,
- 0,
- Opcode_wur_ae_searchdone_encode_fns, 0, 0 },
- { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i,
- 0,
- Opcode_ae_lp16f_i_encode_fns, 0, 0 },
- { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu,
- 0,
- Opcode_ae_lp16f_iu_encode_fns, 0, 0 },
- { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x,
- 0,
- Opcode_ae_lp16f_x_encode_fns, 0, 0 },
- { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu,
- 0,
- Opcode_ae_lp16f_xu_encode_fns, 0, 0 },
- { "ae_lp24.i", ICLASS_ae_iclass_lp24_i,
- 0,
- Opcode_ae_lp24_i_encode_fns, 0, 0 },
- { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu,
- 0,
- Opcode_ae_lp24_iu_encode_fns, 0, 0 },
- { "ae_lp24.x", ICLASS_ae_iclass_lp24_x,
- 0,
- Opcode_ae_lp24_x_encode_fns, 0, 0 },
- { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu,
- 0,
- Opcode_ae_lp24_xu_encode_fns, 0, 0 },
- { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i,
- 0,
- Opcode_ae_lp24f_i_encode_fns, 0, 0 },
- { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu,
- 0,
- Opcode_ae_lp24f_iu_encode_fns, 0, 0 },
- { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x,
- 0,
- Opcode_ae_lp24f_x_encode_fns, 0, 0 },
- { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu,
- 0,
- Opcode_ae_lp24f_xu_encode_fns, 0, 0 },
- { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i,
- 0,
- Opcode_ae_lp16x2f_i_encode_fns, 0, 0 },
- { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu,
- 0,
- Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 },
- { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x,
- 0,
- Opcode_ae_lp16x2f_x_encode_fns, 0, 0 },
- { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu,
- 0,
- Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 },
- { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i,
- 0,
- Opcode_ae_lp24x2f_i_encode_fns, 0, 0 },
- { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu,
- 0,
- Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 },
- { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x,
- 0,
- Opcode_ae_lp24x2f_x_encode_fns, 0, 0 },
- { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu,
- 0,
- Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 },
- { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i,
- 0,
- Opcode_ae_lp24x2_i_encode_fns, 0, 0 },
- { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu,
- 0,
- Opcode_ae_lp24x2_iu_encode_fns, 0, 0 },
- { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x,
- 0,
- Opcode_ae_lp24x2_x_encode_fns, 0, 0 },
- { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu,
- 0,
- Opcode_ae_lp24x2_xu_encode_fns, 0, 0 },
- { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i,
- 0,
- Opcode_ae_sp16x2f_i_encode_fns, 0, 0 },
- { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu,
- 0,
- Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 },
- { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x,
- 0,
- Opcode_ae_sp16x2f_x_encode_fns, 0, 0 },
- { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu,
- 0,
- Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 },
- { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i,
- 0,
- Opcode_ae_sp24x2s_i_encode_fns, 0, 0 },
- { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu,
- 0,
- Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 },
- { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x,
- 0,
- Opcode_ae_sp24x2s_x_encode_fns, 0, 0 },
- { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu,
- 0,
- Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 },
- { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i,
- 0,
- Opcode_ae_sp24x2f_i_encode_fns, 0, 0 },
- { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu,
- 0,
- Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 },
- { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x,
- 0,
- Opcode_ae_sp24x2f_x_encode_fns, 0, 0 },
- { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu,
- 0,
- Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 },
- { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i,
- 0,
- Opcode_ae_sp16f_l_i_encode_fns, 0, 0 },
- { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu,
- 0,
- Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 },
- { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x,
- 0,
- Opcode_ae_sp16f_l_x_encode_fns, 0, 0 },
- { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu,
- 0,
- Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 },
- { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i,
- 0,
- Opcode_ae_sp24s_l_i_encode_fns, 0, 0 },
- { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu,
- 0,
- Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 },
- { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x,
- 0,
- Opcode_ae_sp24s_l_x_encode_fns, 0, 0 },
- { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu,
- 0,
- Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 },
- { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i,
- 0,
- Opcode_ae_sp24f_l_i_encode_fns, 0, 0 },
- { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu,
- 0,
- Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 },
- { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x,
- 0,
- Opcode_ae_sp24f_l_x_encode_fns, 0, 0 },
- { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu,
- 0,
- Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 },
- { "ae_lq56.i", ICLASS_ae_iclass_lq56_i,
- 0,
- Opcode_ae_lq56_i_encode_fns, 0, 0 },
- { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu,
- 0,
- Opcode_ae_lq56_iu_encode_fns, 0, 0 },
- { "ae_lq56.x", ICLASS_ae_iclass_lq56_x,
- 0,
- Opcode_ae_lq56_x_encode_fns, 0, 0 },
- { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu,
- 0,
- Opcode_ae_lq56_xu_encode_fns, 0, 0 },
- { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i,
- 0,
- Opcode_ae_lq32f_i_encode_fns, 0, 0 },
- { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu,
- 0,
- Opcode_ae_lq32f_iu_encode_fns, 0, 0 },
- { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x,
- 0,
- Opcode_ae_lq32f_x_encode_fns, 0, 0 },
- { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu,
- 0,
- Opcode_ae_lq32f_xu_encode_fns, 0, 0 },
- { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i,
- 0,
- Opcode_ae_sq56s_i_encode_fns, 0, 0 },
- { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu,
- 0,
- Opcode_ae_sq56s_iu_encode_fns, 0, 0 },
- { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x,
- 0,
- Opcode_ae_sq56s_x_encode_fns, 0, 0 },
- { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu,
- 0,
- Opcode_ae_sq56s_xu_encode_fns, 0, 0 },
- { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i,
- 0,
- Opcode_ae_sq32f_i_encode_fns, 0, 0 },
- { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu,
- 0,
- Opcode_ae_sq32f_iu_encode_fns, 0, 0 },
- { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x,
- 0,
- Opcode_ae_sq32f_x_encode_fns, 0, 0 },
- { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu,
- 0,
- Opcode_ae_sq32f_xu_encode_fns, 0, 0 },
- { "ae_zerop48", ICLASS_ae_iclass_zerop48,
- 0,
- Opcode_ae_zerop48_encode_fns, 0, 0 },
- { "ae_movp48", ICLASS_ae_iclass_movp48,
- 0,
- Opcode_ae_movp48_encode_fns, 0, 0 },
- { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll,
- 0,
- Opcode_ae_selp24_ll_encode_fns, 0, 0 },
- { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh,
- 0,
- Opcode_ae_selp24_lh_encode_fns, 0, 0 },
- { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl,
- 0,
- Opcode_ae_selp24_hl_encode_fns, 0, 0 },
- { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh,
- 0,
- Opcode_ae_selp24_hh_encode_fns, 0, 0 },
- { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2,
- 0,
- Opcode_ae_movtp24x2_encode_fns, 0, 0 },
- { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2,
- 0,
- Opcode_ae_movfp24x2_encode_fns, 0, 0 },
- { "ae_movtp48", ICLASS_ae_iclass_movtp48,
- 0,
- Opcode_ae_movtp48_encode_fns, 0, 0 },
- { "ae_movfp48", ICLASS_ae_iclass_movfp48,
- 0,
- Opcode_ae_movfp48_encode_fns, 0, 0 },
- { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2,
- 0,
- Opcode_ae_movpa24x2_encode_fns, 0, 0 },
- { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2,
- 0,
- Opcode_ae_truncp24a32x2_encode_fns, 0, 0 },
- { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l,
- 0,
- Opcode_ae_cvta32p24_l_encode_fns, 0, 0 },
- { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h,
- 0,
- Opcode_ae_cvta32p24_h_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll,
- 0,
- Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh,
- 0,
- Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl,
- 0,
- Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 },
- { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh,
- 0,
- Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 },
- { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2,
- 0,
- Opcode_ae_truncp24q48x2_encode_fns, 0, 0 },
- { "ae_truncp16", ICLASS_ae_iclass_truncp16,
- 0,
- Opcode_ae_truncp16_encode_fns, 0, 0 },
- { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym,
- 0,
- Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 },
- { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym,
- 0,
- Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 },
- { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym,
- 0,
- Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 },
- { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym,
- 0,
- Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 },
- { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym,
- 0,
- Opcode_ae_roundsp16sym_encode_fns, 0, 0 },
- { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym,
- 0,
- Opcode_ae_roundsp16asym_encode_fns, 0, 0 },
- { "ae_zeroq56", ICLASS_ae_iclass_zeroq56,
- 0,
- Opcode_ae_zeroq56_encode_fns, 0, 0 },
- { "ae_movq56", ICLASS_ae_iclass_movq56,
- 0,
- Opcode_ae_movq56_encode_fns, 0, 0 },
- { "ae_movtq56", ICLASS_ae_iclass_movtq56,
- 0,
- Opcode_ae_movtq56_encode_fns, 0, 0 },
- { "ae_movfq56", ICLASS_ae_iclass_movfq56,
- 0,
- Opcode_ae_movfq56_encode_fns, 0, 0 },
- { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s,
- 0,
- Opcode_ae_cvtq48a32s_encode_fns, 0, 0 },
- { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l,
- 0,
- Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 },
- { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h,
- 0,
- Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 },
- { "ae_satq48s", ICLASS_ae_iclass_satq48s,
- 0,
- Opcode_ae_satq48s_encode_fns, 0, 0 },
- { "ae_truncq32", ICLASS_ae_iclass_truncq32,
- 0,
- Opcode_ae_truncq32_encode_fns, 0, 0 },
- { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym,
- 0,
- Opcode_ae_roundsq32sym_encode_fns, 0, 0 },
- { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym,
- 0,
- Opcode_ae_roundsq32asym_encode_fns, 0, 0 },
- { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48,
- 0,
- Opcode_ae_trunca32q48_encode_fns, 0, 0 },
- { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l,
- 0,
- Opcode_ae_movap24s_l_encode_fns, 0, 0 },
- { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h,
- 0,
- Opcode_ae_movap24s_h_encode_fns, 0, 0 },
- { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l,
- 0,
- Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 },
- { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h,
- 0,
- Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 },
- { "ae_addp24", ICLASS_ae_iclass_addp24,
- 0,
- Opcode_ae_addp24_encode_fns, 0, 0 },
- { "ae_subp24", ICLASS_ae_iclass_subp24,
- 0,
- Opcode_ae_subp24_encode_fns, 0, 0 },
- { "ae_negp24", ICLASS_ae_iclass_negp24,
- 0,
- Opcode_ae_negp24_encode_fns, 0, 0 },
- { "ae_absp24", ICLASS_ae_iclass_absp24,
- 0,
- Opcode_ae_absp24_encode_fns, 0, 0 },
- { "ae_maxp24s", ICLASS_ae_iclass_maxp24s,
- 0,
- Opcode_ae_maxp24s_encode_fns, 0, 0 },
- { "ae_minp24s", ICLASS_ae_iclass_minp24s,
- 0,
- Opcode_ae_minp24s_encode_fns, 0, 0 },
- { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s,
- 0,
- Opcode_ae_maxbp24s_encode_fns, 0, 0 },
- { "ae_minbp24s", ICLASS_ae_iclass_minbp24s,
- 0,
- Opcode_ae_minbp24s_encode_fns, 0, 0 },
- { "ae_addsp24s", ICLASS_ae_iclass_addsp24s,
- 0,
- Opcode_ae_addsp24s_encode_fns, 0, 0 },
- { "ae_subsp24s", ICLASS_ae_iclass_subsp24s,
- 0,
- Opcode_ae_subsp24s_encode_fns, 0, 0 },
- { "ae_negsp24s", ICLASS_ae_iclass_negsp24s,
- 0,
- Opcode_ae_negsp24s_encode_fns, 0, 0 },
- { "ae_abssp24s", ICLASS_ae_iclass_abssp24s,
- 0,
- Opcode_ae_abssp24s_encode_fns, 0, 0 },
- { "ae_andp48", ICLASS_ae_iclass_andp48,
- 0,
- Opcode_ae_andp48_encode_fns, 0, 0 },
- { "ae_nandp48", ICLASS_ae_iclass_nandp48,
- 0,
- Opcode_ae_nandp48_encode_fns, 0, 0 },
- { "ae_orp48", ICLASS_ae_iclass_orp48,
- 0,
- Opcode_ae_orp48_encode_fns, 0, 0 },
- { "ae_xorp48", ICLASS_ae_iclass_xorp48,
- 0,
- Opcode_ae_xorp48_encode_fns, 0, 0 },
- { "ae_ltp24s", ICLASS_ae_iclass_ltp24s,
- 0,
- Opcode_ae_ltp24s_encode_fns, 0, 0 },
- { "ae_lep24s", ICLASS_ae_iclass_lep24s,
- 0,
- Opcode_ae_lep24s_encode_fns, 0, 0 },
- { "ae_eqp24", ICLASS_ae_iclass_eqp24,
- 0,
- Opcode_ae_eqp24_encode_fns, 0, 0 },
- { "ae_addq56", ICLASS_ae_iclass_addq56,
- 0,
- Opcode_ae_addq56_encode_fns, 0, 0 },
- { "ae_subq56", ICLASS_ae_iclass_subq56,
- 0,
- Opcode_ae_subq56_encode_fns, 0, 0 },
- { "ae_negq56", ICLASS_ae_iclass_negq56,
- 0,
- Opcode_ae_negq56_encode_fns, 0, 0 },
- { "ae_absq56", ICLASS_ae_iclass_absq56,
- 0,
- Opcode_ae_absq56_encode_fns, 0, 0 },
- { "ae_maxq56s", ICLASS_ae_iclass_maxq56s,
- 0,
- Opcode_ae_maxq56s_encode_fns, 0, 0 },
- { "ae_minq56s", ICLASS_ae_iclass_minq56s,
- 0,
- Opcode_ae_minq56s_encode_fns, 0, 0 },
- { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s,
- 0,
- Opcode_ae_maxbq56s_encode_fns, 0, 0 },
- { "ae_minbq56s", ICLASS_ae_iclass_minbq56s,
- 0,
- Opcode_ae_minbq56s_encode_fns, 0, 0 },
- { "ae_addsq56s", ICLASS_ae_iclass_addsq56s,
- 0,
- Opcode_ae_addsq56s_encode_fns, 0, 0 },
- { "ae_subsq56s", ICLASS_ae_iclass_subsq56s,
- 0,
- Opcode_ae_subsq56s_encode_fns, 0, 0 },
- { "ae_negsq56s", ICLASS_ae_iclass_negsq56s,
- 0,
- Opcode_ae_negsq56s_encode_fns, 0, 0 },
- { "ae_abssq56s", ICLASS_ae_iclass_abssq56s,
- 0,
- Opcode_ae_abssq56s_encode_fns, 0, 0 },
- { "ae_andq56", ICLASS_ae_iclass_andq56,
- 0,
- Opcode_ae_andq56_encode_fns, 0, 0 },
- { "ae_nandq56", ICLASS_ae_iclass_nandq56,
- 0,
- Opcode_ae_nandq56_encode_fns, 0, 0 },
- { "ae_orq56", ICLASS_ae_iclass_orq56,
- 0,
- Opcode_ae_orq56_encode_fns, 0, 0 },
- { "ae_xorq56", ICLASS_ae_iclass_xorq56,
- 0,
- Opcode_ae_xorq56_encode_fns, 0, 0 },
- { "ae_sllip24", ICLASS_ae_iclass_sllip24,
- 0,
- Opcode_ae_sllip24_encode_fns, 0, 0 },
- { "ae_srlip24", ICLASS_ae_iclass_srlip24,
- 0,
- Opcode_ae_srlip24_encode_fns, 0, 0 },
- { "ae_sraip24", ICLASS_ae_iclass_sraip24,
- 0,
- Opcode_ae_sraip24_encode_fns, 0, 0 },
- { "ae_sllsp24", ICLASS_ae_iclass_sllsp24,
- 0,
- Opcode_ae_sllsp24_encode_fns, 0, 0 },
- { "ae_srlsp24", ICLASS_ae_iclass_srlsp24,
- 0,
- Opcode_ae_srlsp24_encode_fns, 0, 0 },
- { "ae_srasp24", ICLASS_ae_iclass_srasp24,
- 0,
- Opcode_ae_srasp24_encode_fns, 0, 0 },
- { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s,
- 0,
- Opcode_ae_sllisp24s_encode_fns, 0, 0 },
- { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s,
- 0,
- Opcode_ae_sllssp24s_encode_fns, 0, 0 },
- { "ae_slliq56", ICLASS_ae_iclass_slliq56,
- 0,
- Opcode_ae_slliq56_encode_fns, 0, 0 },
- { "ae_srliq56", ICLASS_ae_iclass_srliq56,
- 0,
- Opcode_ae_srliq56_encode_fns, 0, 0 },
- { "ae_sraiq56", ICLASS_ae_iclass_sraiq56,
- 0,
- Opcode_ae_sraiq56_encode_fns, 0, 0 },
- { "ae_sllsq56", ICLASS_ae_iclass_sllsq56,
- 0,
- Opcode_ae_sllsq56_encode_fns, 0, 0 },
- { "ae_srlsq56", ICLASS_ae_iclass_srlsq56,
- 0,
- Opcode_ae_srlsq56_encode_fns, 0, 0 },
- { "ae_srasq56", ICLASS_ae_iclass_srasq56,
- 0,
- Opcode_ae_srasq56_encode_fns, 0, 0 },
- { "ae_sllaq56", ICLASS_ae_iclass_sllaq56,
- 0,
- Opcode_ae_sllaq56_encode_fns, 0, 0 },
- { "ae_srlaq56", ICLASS_ae_iclass_srlaq56,
- 0,
- Opcode_ae_srlaq56_encode_fns, 0, 0 },
- { "ae_sraaq56", ICLASS_ae_iclass_sraaq56,
- 0,
- Opcode_ae_sraaq56_encode_fns, 0, 0 },
- { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s,
- 0,
- Opcode_ae_sllisq56s_encode_fns, 0, 0 },
- { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s,
- 0,
- Opcode_ae_sllssq56s_encode_fns, 0, 0 },
- { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s,
- 0,
- Opcode_ae_sllasq56s_encode_fns, 0, 0 },
- { "ae_ltq56s", ICLASS_ae_iclass_ltq56s,
- 0,
- Opcode_ae_ltq56s_encode_fns, 0, 0 },
- { "ae_leq56s", ICLASS_ae_iclass_leq56s,
- 0,
- Opcode_ae_leq56s_encode_fns, 0, 0 },
- { "ae_eqq56", ICLASS_ae_iclass_eqq56,
- 0,
- Opcode_ae_eqq56_encode_fns, 0, 0 },
- { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s,
- 0,
- Opcode_ae_nsaq56s_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll,
- 0,
- Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 },
- { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll,
- 0,
- Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 },
- { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll,
- 0,
- Opcode_ae_mulp24s_ll_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh,
- 0,
- Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 },
- { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh,
- 0,
- Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 },
- { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh,
- 0,
- Opcode_ae_mulp24s_lh_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl,
- 0,
- Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 },
- { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl,
- 0,
- Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 },
- { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl,
- 0,
- Opcode_ae_mulp24s_hl_encode_fns, 0, 0 },
- { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh,
- 0,
- Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 },
- { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh,
- 0,
- Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 },
- { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh,
- 0,
- Opcode_ae_mulp24s_hh_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll,
- 0,
- Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 },
- { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll,
- 0,
- Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 },
- { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll,
- 0,
- Opcode_ae_mulap24s_ll_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh,
- 0,
- Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 },
- { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh,
- 0,
- Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 },
- { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh,
- 0,
- Opcode_ae_mulap24s_lh_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl,
- 0,
- Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 },
- { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl,
- 0,
- Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 },
- { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl,
- 0,
- Opcode_ae_mulap24s_hl_encode_fns, 0, 0 },
- { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh,
- 0,
- Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 },
- { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh,
- 0,
- Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 },
- { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh,
- 0,
- Opcode_ae_mulap24s_hh_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll,
- 0,
- Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 },
- { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll,
- 0,
- Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 },
- { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll,
- 0,
- Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh,
- 0,
- Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 },
- { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh,
- 0,
- Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 },
- { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh,
- 0,
- Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl,
- 0,
- Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 },
- { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl,
- 0,
- Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 },
- { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl,
- 0,
- Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 },
- { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh,
- 0,
- Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 },
- { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh,
- 0,
- Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 },
- { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh,
- 0,
- Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll,
- 0,
- Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll,
- 0,
- Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh,
- 0,
- Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh,
- 0,
- Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl,
- 0,
- Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl,
- 0,
- Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh,
- 0,
- Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh,
- 0,
- Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll,
- 0,
- Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll,
- 0,
- Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh,
- 0,
- Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh,
- 0,
- Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl,
- 0,
- Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl,
- 0,
- Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 },
- { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh,
- 0,
- Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh,
- 0,
- Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 },
- { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l,
- 0,
- Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h,
- 0,
- Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l,
- 0,
- Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h,
- 0,
- Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l,
- 0,
- Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h,
- 0,
- Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l,
- 0,
- Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h,
- 0,
- Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l,
- 0,
- Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h,
- 0,
- Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l,
- 0,
- Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h,
- 0,
- Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l,
- 0,
- Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h,
- 0,
- Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l,
- 0,
- Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h,
- 0,
- Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l,
- 0,
- Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h,
- 0,
- Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l,
- 0,
- Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h,
- 0,
- Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l,
- 0,
- Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 },
- { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h,
- 0,
- Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 },
- { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l,
- 0,
- Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 },
- { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h,
- 0,
- Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll,
- 0,
- Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll,
- 0,
- Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll,
- 0,
- Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll,
- 0,
- Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh,
- 0,
- Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh,
- 0,
- Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh,
- 0,
- Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh,
- 0,
- Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh,
- 0,
- Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh,
- 0,
- Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh,
- 0,
- Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh,
- 0,
- Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll,
- 0,
- Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll,
- 0,
- Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll,
- 0,
- Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll,
- 0,
- Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh,
- 0,
- Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh,
- 0,
- Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh,
- 0,
- Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh,
- 0,
- Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh,
- 0,
- Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh,
- 0,
- Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh,
- 0,
- Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh,
- 0,
- Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll,
- 0,
- Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll,
- 0,
- Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll,
- 0,
- Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll,
- 0,
- Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh,
- 0,
- Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh,
- 0,
- Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh,
- 0,
- Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh,
- 0,
- Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh,
- 0,
- Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh,
- 0,
- Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh,
- 0,
- Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh,
- 0,
- Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll,
- 0,
- Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll,
- 0,
- Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll,
- 0,
- Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll,
- 0,
- Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh,
- 0,
- Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh,
- 0,
- Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh,
- 0,
- Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh,
- 0,
- Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh,
- 0,
- Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh,
- 0,
- Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 },
- { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh,
- 0,
- Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh,
- 0,
- Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 },
- { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll,
- 0,
- Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll,
- 0,
- Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh,
- 0,
- Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh,
- 0,
- Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll,
- 0,
- Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll,
- 0,
- Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh,
- 0,
- Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh,
- 0,
- Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll,
- 0,
- Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll,
- 0,
- Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh,
- 0,
- Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh,
- 0,
- Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll,
- 0,
- Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll,
- 0,
- Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh,
- 0,
- Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh,
- 0,
- Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll,
- 0,
- Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll,
- 0,
- Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh,
- 0,
- Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh,
- 0,
- Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll,
- 0,
- Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll,
- 0,
- Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh,
- 0,
- Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh,
- 0,
- Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll,
- 0,
- Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll,
- 0,
- Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh,
- 0,
- Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh,
- 0,
- Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll,
- 0,
- Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll,
- 0,
- Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 },
- { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh,
- 0,
- Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh,
- 0,
- Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 },
- { "ae_sha32", ICLASS_ae_iclass_sha32,
- 0,
- Opcode_ae_sha32_encode_fns, 0, 0 },
- { "ae_vldl32t", ICLASS_ae_iclass_vldl32t,
- 0,
- Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses },
- { "ae_vldl16t", ICLASS_ae_iclass_vldl16t,
- 0,
- Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses },
- { "ae_vldl16c", ICLASS_ae_iclass_vldl16c,
- 0,
- Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses },
- { "ae_vldsht", ICLASS_ae_iclass_vldsht,
- 0,
- Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses },
- { "ae_lb", ICLASS_ae_iclass_lb,
- 0,
- Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses },
- { "ae_lbi", ICLASS_ae_iclass_lbi,
- 0,
- Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses },
- { "ae_lbk", ICLASS_ae_iclass_lbk,
- 0,
- Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses },
- { "ae_lbki", ICLASS_ae_iclass_lbki,
- 0,
- Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses },
- { "ae_db", ICLASS_ae_iclass_db,
- 0,
- Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses },
- { "ae_dbi", ICLASS_ae_iclass_dbi,
- 0,
- Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses },
- { "ae_vlel32t", ICLASS_ae_iclass_vlel32t,
- 0,
- Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses },
- { "ae_vlel16t", ICLASS_ae_iclass_vlel16t,
- 0,
- Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses },
- { "ae_sb", ICLASS_ae_iclass_sb,
- 0,
- Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses },
- { "ae_sbi", ICLASS_ae_iclass_sbi,
- 0,
- Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses },
- { "ae_vles16c", ICLASS_ae_iclass_vles16c,
- 0,
- Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses },
- { "ae_sbf", ICLASS_ae_iclass_sbf,
- 0,
- Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }
-};
-
-enum xtensa_opcode_id {
- OPCODE_EXCW,
- OPCODE_RFE,
- OPCODE_RFDE,
- OPCODE_SYSCALL,
- OPCODE_CALL12,
- OPCODE_CALL8,
- OPCODE_CALL4,
- OPCODE_CALLX12,
- OPCODE_CALLX8,
- OPCODE_CALLX4,
- OPCODE_ENTRY,
- OPCODE_MOVSP,
- OPCODE_ROTW,
- OPCODE_RETW,
- OPCODE_RETW_N,
- OPCODE_RFWO,
- OPCODE_RFWU,
- OPCODE_L32E,
- OPCODE_S32E,
- OPCODE_RSR_WINDOWBASE,
- OPCODE_WSR_WINDOWBASE,
- OPCODE_XSR_WINDOWBASE,
- OPCODE_RSR_WINDOWSTART,
- OPCODE_WSR_WINDOWSTART,
- OPCODE_XSR_WINDOWSTART,
- OPCODE_ADD_N,
- OPCODE_ADDI_N,
- OPCODE_BEQZ_N,
- OPCODE_BNEZ_N,
- OPCODE_ILL_N,
- OPCODE_L32I_N,
- OPCODE_MOV_N,
- OPCODE_MOVI_N,
- OPCODE_NOP_N,
- OPCODE_RET_N,
- OPCODE_S32I_N,
- OPCODE_RUR_THREADPTR,
- OPCODE_WUR_THREADPTR,
- OPCODE_ADDI,
- OPCODE_ADDMI,
- OPCODE_ADD,
- OPCODE_SUB,
- OPCODE_ADDX2,
- OPCODE_ADDX4,
- OPCODE_ADDX8,
- OPCODE_SUBX2,
- OPCODE_SUBX4,
- OPCODE_SUBX8,
- OPCODE_AND,
- OPCODE_OR,
- OPCODE_XOR,
- OPCODE_BEQI,
- OPCODE_BNEI,
- OPCODE_BGEI,
- OPCODE_BLTI,
- OPCODE_BBCI,
- OPCODE_BBSI,
- OPCODE_BGEUI,
- OPCODE_BLTUI,
- OPCODE_BEQ,
- OPCODE_BNE,
- OPCODE_BGE,
- OPCODE_BLT,
- OPCODE_BGEU,
- OPCODE_BLTU,
- OPCODE_BANY,
- OPCODE_BNONE,
- OPCODE_BALL,
- OPCODE_BNALL,
- OPCODE_BBC,
- OPCODE_BBS,
- OPCODE_BEQZ,
- OPCODE_BNEZ,
- OPCODE_BGEZ,
- OPCODE_BLTZ,
- OPCODE_CALL0,
- OPCODE_CALLX0,
- OPCODE_EXTUI,
- OPCODE_ILL,
- OPCODE_J,
- OPCODE_JX,
- OPCODE_L16UI,
- OPCODE_L16SI,
- OPCODE_L32I,
- OPCODE_L32R,
- OPCODE_L8UI,
- OPCODE_LOOP,
- OPCODE_LOOPNEZ,
- OPCODE_LOOPGTZ,
- OPCODE_MOVI,
- OPCODE_MOVEQZ,
- OPCODE_MOVNEZ,
- OPCODE_MOVLTZ,
- OPCODE_MOVGEZ,
- OPCODE_NEG,
- OPCODE_ABS,
- OPCODE_NOP,
- OPCODE_RET,
- OPCODE_SIMCALL,
- OPCODE_S16I,
- OPCODE_S32I,
- OPCODE_S8I,
- OPCODE_SSR,
- OPCODE_SSL,
- OPCODE_SSA8L,
- OPCODE_SSA8B,
- OPCODE_SSAI,
- OPCODE_SLL,
- OPCODE_SRC,
- OPCODE_SRL,
- OPCODE_SRA,
- OPCODE_SLLI,
- OPCODE_SRAI,
- OPCODE_SRLI,
- OPCODE_MEMW,
- OPCODE_EXTW,
- OPCODE_ISYNC,
- OPCODE_RSYNC,
- OPCODE_ESYNC,
- OPCODE_DSYNC,
- OPCODE_RSIL,
- OPCODE_RSR_LEND,
- OPCODE_WSR_LEND,
- OPCODE_XSR_LEND,
- OPCODE_RSR_LCOUNT,
- OPCODE_WSR_LCOUNT,
- OPCODE_XSR_LCOUNT,
- OPCODE_RSR_LBEG,
- OPCODE_WSR_LBEG,
- OPCODE_XSR_LBEG,
- OPCODE_RSR_SAR,
- OPCODE_WSR_SAR,
- OPCODE_XSR_SAR,
- OPCODE_RSR_LITBASE,
- OPCODE_WSR_LITBASE,
- OPCODE_XSR_LITBASE,
- OPCODE_RSR_CONFIGID0,
- OPCODE_WSR_CONFIGID0,
- OPCODE_RSR_CONFIGID1,
- OPCODE_RSR_PS,
- OPCODE_WSR_PS,
- OPCODE_XSR_PS,
- OPCODE_RSR_EPC1,
- OPCODE_WSR_EPC1,
- OPCODE_XSR_EPC1,
- OPCODE_RSR_EXCSAVE1,
- OPCODE_WSR_EXCSAVE1,
- OPCODE_XSR_EXCSAVE1,
- OPCODE_RSR_EPC2,
- OPCODE_WSR_EPC2,
- OPCODE_XSR_EPC2,
- OPCODE_RSR_EXCSAVE2,
- OPCODE_WSR_EXCSAVE2,
- OPCODE_XSR_EXCSAVE2,
- OPCODE_RSR_EPS2,
- OPCODE_WSR_EPS2,
- OPCODE_XSR_EPS2,
- OPCODE_RSR_EXCVADDR,
- OPCODE_WSR_EXCVADDR,
- OPCODE_XSR_EXCVADDR,
- OPCODE_RSR_DEPC,
- OPCODE_WSR_DEPC,
- OPCODE_XSR_DEPC,
- OPCODE_RSR_EXCCAUSE,
- OPCODE_WSR_EXCCAUSE,
- OPCODE_XSR_EXCCAUSE,
- OPCODE_RSR_MISC0,
- OPCODE_WSR_MISC0,
- OPCODE_XSR_MISC0,
- OPCODE_RSR_MISC1,
- OPCODE_WSR_MISC1,
- OPCODE_XSR_MISC1,
- OPCODE_RSR_PRID,
- OPCODE_RSR_VECBASE,
- OPCODE_WSR_VECBASE,
- OPCODE_XSR_VECBASE,
- OPCODE_MUL16U,
- OPCODE_MUL16S,
- OPCODE_MULL,
- OPCODE_RFI,
- OPCODE_WAITI,
- OPCODE_RSR_INTERRUPT,
- OPCODE_WSR_INTSET,
- OPCODE_WSR_INTCLEAR,
- OPCODE_RSR_INTENABLE,
- OPCODE_WSR_INTENABLE,
- OPCODE_XSR_INTENABLE,
- OPCODE_BREAK,
- OPCODE_BREAK_N,
- OPCODE_RSR_DEBUGCAUSE,
- OPCODE_WSR_DEBUGCAUSE,
- OPCODE_XSR_DEBUGCAUSE,
- OPCODE_RSR_ICOUNT,
- OPCODE_WSR_ICOUNT,
- OPCODE_XSR_ICOUNT,
- OPCODE_RSR_ICOUNTLEVEL,
- OPCODE_WSR_ICOUNTLEVEL,
- OPCODE_XSR_ICOUNTLEVEL,
- OPCODE_RSR_DDR,
- OPCODE_WSR_DDR,
- OPCODE_XSR_DDR,
- OPCODE_RFDO,
- OPCODE_RFDD,
- OPCODE_ANDB,
- OPCODE_ANDBC,
- OPCODE_ORB,
- OPCODE_ORBC,
- OPCODE_XORB,
- OPCODE_ANY4,
- OPCODE_ALL4,
- OPCODE_ANY8,
- OPCODE_ALL8,
- OPCODE_BF,
- OPCODE_BT,
- OPCODE_MOVF,
- OPCODE_MOVT,
- OPCODE_RSR_BR,
- OPCODE_WSR_BR,
- OPCODE_XSR_BR,
- OPCODE_RSR_CCOUNT,
- OPCODE_WSR_CCOUNT,
- OPCODE_XSR_CCOUNT,
- OPCODE_RSR_CCOMPARE0,
- OPCODE_WSR_CCOMPARE0,
- OPCODE_XSR_CCOMPARE0,
- OPCODE_RSR_CCOMPARE1,
- OPCODE_WSR_CCOMPARE1,
- OPCODE_XSR_CCOMPARE1,
- OPCODE_IPF,
- OPCODE_IHI,
- OPCODE_III,
- OPCODE_LICT,
- OPCODE_LICW,
- OPCODE_SICT,
- OPCODE_SICW,
- OPCODE_DHWB,
- OPCODE_DHWBI,
- OPCODE_DIWB,
- OPCODE_DIWBI,
- OPCODE_DHI,
- OPCODE_DII,
- OPCODE_DPFR,
- OPCODE_DPFW,
- OPCODE_DPFRO,
- OPCODE_DPFWO,
- OPCODE_SDCT,
- OPCODE_LDCT,
- OPCODE_WSR_PTEVADDR,
- OPCODE_RSR_PTEVADDR,
- OPCODE_XSR_PTEVADDR,
- OPCODE_RSR_RASID,
- OPCODE_WSR_RASID,
- OPCODE_XSR_RASID,
- OPCODE_RSR_ITLBCFG,
- OPCODE_WSR_ITLBCFG,
- OPCODE_XSR_ITLBCFG,
- OPCODE_RSR_DTLBCFG,
- OPCODE_WSR_DTLBCFG,
- OPCODE_XSR_DTLBCFG,
- OPCODE_IDTLB,
- OPCODE_PDTLB,
- OPCODE_RDTLB0,
- OPCODE_RDTLB1,
- OPCODE_WDTLB,
- OPCODE_IITLB,
- OPCODE_PITLB,
- OPCODE_RITLB0,
- OPCODE_RITLB1,
- OPCODE_WITLB,
- OPCODE_LDPTE,
- OPCODE_HWWITLBA,
- OPCODE_HWWDTLBA,
- OPCODE_RSR_CPENABLE,
- OPCODE_WSR_CPENABLE,
- OPCODE_XSR_CPENABLE,
- OPCODE_CLAMPS,
- OPCODE_MIN,
- OPCODE_MAX,
- OPCODE_MINU,
- OPCODE_MAXU,
- OPCODE_NSA,
- OPCODE_NSAU,
- OPCODE_SEXT,
- OPCODE_L32AI,
- OPCODE_S32RI,
- OPCODE_S32C1I,
- OPCODE_RSR_SCOMPARE1,
- OPCODE_WSR_SCOMPARE1,
- OPCODE_XSR_SCOMPARE1,
- OPCODE_RSR_ATOMCTL,
- OPCODE_WSR_ATOMCTL,
- OPCODE_XSR_ATOMCTL,
- OPCODE_RER,
- OPCODE_WER,
- OPCODE_RUR_AE_OVF_SAR,
- OPCODE_WUR_AE_OVF_SAR,
- OPCODE_RUR_AE_BITHEAD,
- OPCODE_WUR_AE_BITHEAD,
- OPCODE_RUR_AE_TS_FTS_BU_BP,
- OPCODE_WUR_AE_TS_FTS_BU_BP,
- OPCODE_RUR_AE_SD_NO,
- OPCODE_WUR_AE_SD_NO,
- OPCODE_RUR_AE_OVERFLOW,
- OPCODE_WUR_AE_OVERFLOW,
- OPCODE_RUR_AE_SAR,
- OPCODE_WUR_AE_SAR,
- OPCODE_RUR_AE_BITPTR,
- OPCODE_WUR_AE_BITPTR,
- OPCODE_RUR_AE_BITSUSED,
- OPCODE_WUR_AE_BITSUSED,
- OPCODE_RUR_AE_TABLESIZE,
- OPCODE_WUR_AE_TABLESIZE,
- OPCODE_RUR_AE_FIRST_TS,
- OPCODE_WUR_AE_FIRST_TS,
- OPCODE_RUR_AE_NEXTOFFSET,
- OPCODE_WUR_AE_NEXTOFFSET,
- OPCODE_RUR_AE_SEARCHDONE,
- OPCODE_WUR_AE_SEARCHDONE,
- OPCODE_AE_LP16F_I,
- OPCODE_AE_LP16F_IU,
- OPCODE_AE_LP16F_X,
- OPCODE_AE_LP16F_XU,
- OPCODE_AE_LP24_I,
- OPCODE_AE_LP24_IU,
- OPCODE_AE_LP24_X,
- OPCODE_AE_LP24_XU,
- OPCODE_AE_LP24F_I,
- OPCODE_AE_LP24F_IU,
- OPCODE_AE_LP24F_X,
- OPCODE_AE_LP24F_XU,
- OPCODE_AE_LP16X2F_I,
- OPCODE_AE_LP16X2F_IU,
- OPCODE_AE_LP16X2F_X,
- OPCODE_AE_LP16X2F_XU,
- OPCODE_AE_LP24X2F_I,
- OPCODE_AE_LP24X2F_IU,
- OPCODE_AE_LP24X2F_X,
- OPCODE_AE_LP24X2F_XU,
- OPCODE_AE_LP24X2_I,
- OPCODE_AE_LP24X2_IU,
- OPCODE_AE_LP24X2_X,
- OPCODE_AE_LP24X2_XU,
- OPCODE_AE_SP16X2F_I,
- OPCODE_AE_SP16X2F_IU,
- OPCODE_AE_SP16X2F_X,
- OPCODE_AE_SP16X2F_XU,
- OPCODE_AE_SP24X2S_I,
- OPCODE_AE_SP24X2S_IU,
- OPCODE_AE_SP24X2S_X,
- OPCODE_AE_SP24X2S_XU,
- OPCODE_AE_SP24X2F_I,
- OPCODE_AE_SP24X2F_IU,
- OPCODE_AE_SP24X2F_X,
- OPCODE_AE_SP24X2F_XU,
- OPCODE_AE_SP16F_L_I,
- OPCODE_AE_SP16F_L_IU,
- OPCODE_AE_SP16F_L_X,
- OPCODE_AE_SP16F_L_XU,
- OPCODE_AE_SP24S_L_I,
- OPCODE_AE_SP24S_L_IU,
- OPCODE_AE_SP24S_L_X,
- OPCODE_AE_SP24S_L_XU,
- OPCODE_AE_SP24F_L_I,
- OPCODE_AE_SP24F_L_IU,
- OPCODE_AE_SP24F_L_X,
- OPCODE_AE_SP24F_L_XU,
- OPCODE_AE_LQ56_I,
- OPCODE_AE_LQ56_IU,
- OPCODE_AE_LQ56_X,
- OPCODE_AE_LQ56_XU,
- OPCODE_AE_LQ32F_I,
- OPCODE_AE_LQ32F_IU,
- OPCODE_AE_LQ32F_X,
- OPCODE_AE_LQ32F_XU,
- OPCODE_AE_SQ56S_I,
- OPCODE_AE_SQ56S_IU,
- OPCODE_AE_SQ56S_X,
- OPCODE_AE_SQ56S_XU,
- OPCODE_AE_SQ32F_I,
- OPCODE_AE_SQ32F_IU,
- OPCODE_AE_SQ32F_X,
- OPCODE_AE_SQ32F_XU,
- OPCODE_AE_ZEROP48,
- OPCODE_AE_MOVP48,
- OPCODE_AE_SELP24_LL,
- OPCODE_AE_SELP24_LH,
- OPCODE_AE_SELP24_HL,
- OPCODE_AE_SELP24_HH,
- OPCODE_AE_MOVTP24X2,
- OPCODE_AE_MOVFP24X2,
- OPCODE_AE_MOVTP48,
- OPCODE_AE_MOVFP48,
- OPCODE_AE_MOVPA24X2,
- OPCODE_AE_TRUNCP24A32X2,
- OPCODE_AE_CVTA32P24_L,
- OPCODE_AE_CVTA32P24_H,
- OPCODE_AE_CVTP24A16X2_LL,
- OPCODE_AE_CVTP24A16X2_LH,
- OPCODE_AE_CVTP24A16X2_HL,
- OPCODE_AE_CVTP24A16X2_HH,
- OPCODE_AE_TRUNCP24Q48X2,
- OPCODE_AE_TRUNCP16,
- OPCODE_AE_ROUNDSP24Q48SYM,
- OPCODE_AE_ROUNDSP24Q48ASYM,
- OPCODE_AE_ROUNDSP16Q48SYM,
- OPCODE_AE_ROUNDSP16Q48ASYM,
- OPCODE_AE_ROUNDSP16SYM,
- OPCODE_AE_ROUNDSP16ASYM,
- OPCODE_AE_ZEROQ56,
- OPCODE_AE_MOVQ56,
- OPCODE_AE_MOVTQ56,
- OPCODE_AE_MOVFQ56,
- OPCODE_AE_CVTQ48A32S,
- OPCODE_AE_CVTQ48P24S_L,
- OPCODE_AE_CVTQ48P24S_H,
- OPCODE_AE_SATQ48S,
- OPCODE_AE_TRUNCQ32,
- OPCODE_AE_ROUNDSQ32SYM,
- OPCODE_AE_ROUNDSQ32ASYM,
- OPCODE_AE_TRUNCA32Q48,
- OPCODE_AE_MOVAP24S_L,
- OPCODE_AE_MOVAP24S_H,
- OPCODE_AE_TRUNCA16P24S_L,
- OPCODE_AE_TRUNCA16P24S_H,
- OPCODE_AE_ADDP24,
- OPCODE_AE_SUBP24,
- OPCODE_AE_NEGP24,
- OPCODE_AE_ABSP24,
- OPCODE_AE_MAXP24S,
- OPCODE_AE_MINP24S,
- OPCODE_AE_MAXBP24S,
- OPCODE_AE_MINBP24S,
- OPCODE_AE_ADDSP24S,
- OPCODE_AE_SUBSP24S,
- OPCODE_AE_NEGSP24S,
- OPCODE_AE_ABSSP24S,
- OPCODE_AE_ANDP48,
- OPCODE_AE_NANDP48,
- OPCODE_AE_ORP48,
- OPCODE_AE_XORP48,
- OPCODE_AE_LTP24S,
- OPCODE_AE_LEP24S,
- OPCODE_AE_EQP24,
- OPCODE_AE_ADDQ56,
- OPCODE_AE_SUBQ56,
- OPCODE_AE_NEGQ56,
- OPCODE_AE_ABSQ56,
- OPCODE_AE_MAXQ56S,
- OPCODE_AE_MINQ56S,
- OPCODE_AE_MAXBQ56S,
- OPCODE_AE_MINBQ56S,
- OPCODE_AE_ADDSQ56S,
- OPCODE_AE_SUBSQ56S,
- OPCODE_AE_NEGSQ56S,
- OPCODE_AE_ABSSQ56S,
- OPCODE_AE_ANDQ56,
- OPCODE_AE_NANDQ56,
- OPCODE_AE_ORQ56,
- OPCODE_AE_XORQ56,
- OPCODE_AE_SLLIP24,
- OPCODE_AE_SRLIP24,
- OPCODE_AE_SRAIP24,
- OPCODE_AE_SLLSP24,
- OPCODE_AE_SRLSP24,
- OPCODE_AE_SRASP24,
- OPCODE_AE_SLLISP24S,
- OPCODE_AE_SLLSSP24S,
- OPCODE_AE_SLLIQ56,
- OPCODE_AE_SRLIQ56,
- OPCODE_AE_SRAIQ56,
- OPCODE_AE_SLLSQ56,
- OPCODE_AE_SRLSQ56,
- OPCODE_AE_SRASQ56,
- OPCODE_AE_SLLAQ56,
- OPCODE_AE_SRLAQ56,
- OPCODE_AE_SRAAQ56,
- OPCODE_AE_SLLISQ56S,
- OPCODE_AE_SLLSSQ56S,
- OPCODE_AE_SLLASQ56S,
- OPCODE_AE_LTQ56S,
- OPCODE_AE_LEQ56S,
- OPCODE_AE_EQQ56,
- OPCODE_AE_NSAQ56S,
- OPCODE_AE_MULFS32P16S_LL,
- OPCODE_AE_MULFP24S_LL,
- OPCODE_AE_MULP24S_LL,
- OPCODE_AE_MULFS32P16S_LH,
- OPCODE_AE_MULFP24S_LH,
- OPCODE_AE_MULP24S_LH,
- OPCODE_AE_MULFS32P16S_HL,
- OPCODE_AE_MULFP24S_HL,
- OPCODE_AE_MULP24S_HL,
- OPCODE_AE_MULFS32P16S_HH,
- OPCODE_AE_MULFP24S_HH,
- OPCODE_AE_MULP24S_HH,
- OPCODE_AE_MULAFS32P16S_LL,
- OPCODE_AE_MULAFP24S_LL,
- OPCODE_AE_MULAP24S_LL,
- OPCODE_AE_MULAFS32P16S_LH,
- OPCODE_AE_MULAFP24S_LH,
- OPCODE_AE_MULAP24S_LH,
- OPCODE_AE_MULAFS32P16S_HL,
- OPCODE_AE_MULAFP24S_HL,
- OPCODE_AE_MULAP24S_HL,
- OPCODE_AE_MULAFS32P16S_HH,
- OPCODE_AE_MULAFP24S_HH,
- OPCODE_AE_MULAP24S_HH,
- OPCODE_AE_MULSFS32P16S_LL,
- OPCODE_AE_MULSFP24S_LL,
- OPCODE_AE_MULSP24S_LL,
- OPCODE_AE_MULSFS32P16S_LH,
- OPCODE_AE_MULSFP24S_LH,
- OPCODE_AE_MULSP24S_LH,
- OPCODE_AE_MULSFS32P16S_HL,
- OPCODE_AE_MULSFP24S_HL,
- OPCODE_AE_MULSP24S_HL,
- OPCODE_AE_MULSFS32P16S_HH,
- OPCODE_AE_MULSFP24S_HH,
- OPCODE_AE_MULSP24S_HH,
- OPCODE_AE_MULAFS56P24S_LL,
- OPCODE_AE_MULAS56P24S_LL,
- OPCODE_AE_MULAFS56P24S_LH,
- OPCODE_AE_MULAS56P24S_LH,
- OPCODE_AE_MULAFS56P24S_HL,
- OPCODE_AE_MULAS56P24S_HL,
- OPCODE_AE_MULAFS56P24S_HH,
- OPCODE_AE_MULAS56P24S_HH,
- OPCODE_AE_MULSFS56P24S_LL,
- OPCODE_AE_MULSS56P24S_LL,
- OPCODE_AE_MULSFS56P24S_LH,
- OPCODE_AE_MULSS56P24S_LH,
- OPCODE_AE_MULSFS56P24S_HL,
- OPCODE_AE_MULSS56P24S_HL,
- OPCODE_AE_MULSFS56P24S_HH,
- OPCODE_AE_MULSS56P24S_HH,
- OPCODE_AE_MULFQ32SP16S_L,
- OPCODE_AE_MULFQ32SP16S_H,
- OPCODE_AE_MULFQ32SP16U_L,
- OPCODE_AE_MULFQ32SP16U_H,
- OPCODE_AE_MULQ32SP16S_L,
- OPCODE_AE_MULQ32SP16S_H,
- OPCODE_AE_MULQ32SP16U_L,
- OPCODE_AE_MULQ32SP16U_H,
- OPCODE_AE_MULAFQ32SP16S_L,
- OPCODE_AE_MULAFQ32SP16S_H,
- OPCODE_AE_MULAFQ32SP16U_L,
- OPCODE_AE_MULAFQ32SP16U_H,
- OPCODE_AE_MULAQ32SP16S_L,
- OPCODE_AE_MULAQ32SP16S_H,
- OPCODE_AE_MULAQ32SP16U_L,
- OPCODE_AE_MULAQ32SP16U_H,
- OPCODE_AE_MULSFQ32SP16S_L,
- OPCODE_AE_MULSFQ32SP16S_H,
- OPCODE_AE_MULSFQ32SP16U_L,
- OPCODE_AE_MULSFQ32SP16U_H,
- OPCODE_AE_MULSQ32SP16S_L,
- OPCODE_AE_MULSQ32SP16S_H,
- OPCODE_AE_MULSQ32SP16U_L,
- OPCODE_AE_MULSQ32SP16U_H,
- OPCODE_AE_MULZAAQ32SP16S_LL,
- OPCODE_AE_MULZAAFQ32SP16S_LL,
- OPCODE_AE_MULZAAQ32SP16U_LL,
- OPCODE_AE_MULZAAFQ32SP16U_LL,
- OPCODE_AE_MULZAAQ32SP16S_HH,
- OPCODE_AE_MULZAAFQ32SP16S_HH,
- OPCODE_AE_MULZAAQ32SP16U_HH,
- OPCODE_AE_MULZAAFQ32SP16U_HH,
- OPCODE_AE_MULZAAQ32SP16S_LH,
- OPCODE_AE_MULZAAFQ32SP16S_LH,
- OPCODE_AE_MULZAAQ32SP16U_LH,
- OPCODE_AE_MULZAAFQ32SP16U_LH,
- OPCODE_AE_MULZASQ32SP16S_LL,
- OPCODE_AE_MULZASFQ32SP16S_LL,
- OPCODE_AE_MULZASQ32SP16U_LL,
- OPCODE_AE_MULZASFQ32SP16U_LL,
- OPCODE_AE_MULZASQ32SP16S_HH,
- OPCODE_AE_MULZASFQ32SP16S_HH,
- OPCODE_AE_MULZASQ32SP16U_HH,
- OPCODE_AE_MULZASFQ32SP16U_HH,
- OPCODE_AE_MULZASQ32SP16S_LH,
- OPCODE_AE_MULZASFQ32SP16S_LH,
- OPCODE_AE_MULZASQ32SP16U_LH,
- OPCODE_AE_MULZASFQ32SP16U_LH,
- OPCODE_AE_MULZSAQ32SP16S_LL,
- OPCODE_AE_MULZSAFQ32SP16S_LL,
- OPCODE_AE_MULZSAQ32SP16U_LL,
- OPCODE_AE_MULZSAFQ32SP16U_LL,
- OPCODE_AE_MULZSAQ32SP16S_HH,
- OPCODE_AE_MULZSAFQ32SP16S_HH,
- OPCODE_AE_MULZSAQ32SP16U_HH,
- OPCODE_AE_MULZSAFQ32SP16U_HH,
- OPCODE_AE_MULZSAQ32SP16S_LH,
- OPCODE_AE_MULZSAFQ32SP16S_LH,
- OPCODE_AE_MULZSAQ32SP16U_LH,
- OPCODE_AE_MULZSAFQ32SP16U_LH,
- OPCODE_AE_MULZSSQ32SP16S_LL,
- OPCODE_AE_MULZSSFQ32SP16S_LL,
- OPCODE_AE_MULZSSQ32SP16U_LL,
- OPCODE_AE_MULZSSFQ32SP16U_LL,
- OPCODE_AE_MULZSSQ32SP16S_HH,
- OPCODE_AE_MULZSSFQ32SP16S_HH,
- OPCODE_AE_MULZSSQ32SP16U_HH,
- OPCODE_AE_MULZSSFQ32SP16U_HH,
- OPCODE_AE_MULZSSQ32SP16S_LH,
- OPCODE_AE_MULZSSFQ32SP16S_LH,
- OPCODE_AE_MULZSSQ32SP16U_LH,
- OPCODE_AE_MULZSSFQ32SP16U_LH,
- OPCODE_AE_MULZAAFP24S_HH_LL,
- OPCODE_AE_MULZAAP24S_HH_LL,
- OPCODE_AE_MULZAAFP24S_HL_LH,
- OPCODE_AE_MULZAAP24S_HL_LH,
- OPCODE_AE_MULZASFP24S_HH_LL,
- OPCODE_AE_MULZASP24S_HH_LL,
- OPCODE_AE_MULZASFP24S_HL_LH,
- OPCODE_AE_MULZASP24S_HL_LH,
- OPCODE_AE_MULZSAFP24S_HH_LL,
- OPCODE_AE_MULZSAP24S_HH_LL,
- OPCODE_AE_MULZSAFP24S_HL_LH,
- OPCODE_AE_MULZSAP24S_HL_LH,
- OPCODE_AE_MULZSSFP24S_HH_LL,
- OPCODE_AE_MULZSSP24S_HH_LL,
- OPCODE_AE_MULZSSFP24S_HL_LH,
- OPCODE_AE_MULZSSP24S_HL_LH,
- OPCODE_AE_MULAAFP24S_HH_LL,
- OPCODE_AE_MULAAP24S_HH_LL,
- OPCODE_AE_MULAAFP24S_HL_LH,
- OPCODE_AE_MULAAP24S_HL_LH,
- OPCODE_AE_MULASFP24S_HH_LL,
- OPCODE_AE_MULASP24S_HH_LL,
- OPCODE_AE_MULASFP24S_HL_LH,
- OPCODE_AE_MULASP24S_HL_LH,
- OPCODE_AE_MULSAFP24S_HH_LL,
- OPCODE_AE_MULSAP24S_HH_LL,
- OPCODE_AE_MULSAFP24S_HL_LH,
- OPCODE_AE_MULSAP24S_HL_LH,
- OPCODE_AE_MULSSFP24S_HH_LL,
- OPCODE_AE_MULSSP24S_HH_LL,
- OPCODE_AE_MULSSFP24S_HL_LH,
- OPCODE_AE_MULSSP24S_HL_LH,
- OPCODE_AE_SHA32,
- OPCODE_AE_VLDL32T,
- OPCODE_AE_VLDL16T,
- OPCODE_AE_VLDL16C,
- OPCODE_AE_VLDSHT,
- OPCODE_AE_LB,
- OPCODE_AE_LBI,
- OPCODE_AE_LBK,
- OPCODE_AE_LBKI,
- OPCODE_AE_DB,
- OPCODE_AE_DBI,
- OPCODE_AE_VLEL32T,
- OPCODE_AE_VLEL16T,
- OPCODE_AE_SB,
- OPCODE_AE_SBI,
- OPCODE_AE_VLES16C,
- OPCODE_AE_SBF
-};
-
-\f
-/* Slot-specific opcode decode functions. */
-
-static int
-Slot_inst_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst_get (insn) == 0)
- {
- if (Field_op1_Slot_inst_get (insn) == 0)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- {
- if (Field_m_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_ILL;
- if (Field_m_Slot_inst_get (insn) == 2)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_RET;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_RETW;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_JX;
- }
- if (Field_m_Slot_inst_get (insn) == 3)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALLX0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALLX4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALLX8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALLX12;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_MOVSP;
- if (Field_r_Slot_inst_get (insn) == 2)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_ISYNC;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RSYNC;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_ESYNC;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DSYNC;
- if (Field_t_Slot_inst_get (insn) == 8)
- return OPCODE_EXCW;
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_MEMW;
- if (Field_t_Slot_inst_get (insn) == 13)
- return OPCODE_EXTW;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_NOP;
- }
- }
- if (Field_r_Slot_inst_get (insn) == 3)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_RFE;
- if (Field_s_Slot_inst_get (insn) == 2)
- return OPCODE_RFDE;
- if (Field_s_Slot_inst_get (insn) == 4)
- return OPCODE_RFWO;
- if (Field_s_Slot_inst_get (insn) == 5)
- return OPCODE_RFWU;
- }
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFI;
- }
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BREAK;
- if (Field_r_Slot_inst_get (insn) == 5)
- {
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SYSCALL;
- if (Field_s_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SIMCALL;
- }
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RSIL;
- if (Field_r_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_WAITI;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_ANY4;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_ALL4;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_ANY8;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_ALL8;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- return OPCODE_AND;
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_OR;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_XOR;
- if (Field_op2_Slot_inst_get (insn) == 4)
- {
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSR;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSL;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8L;
- if (Field_r_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SSA8B;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_thi3_Slot_inst_get (insn) == 0)
- return OPCODE_SSAI;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_RER;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_WER;
- if (Field_r_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_ROTW;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_NSA;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_NSAU;
- }
- if (Field_op2_Slot_inst_get (insn) == 5)
- {
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_HWWITLBA;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_RITLB0;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IITLB;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_PITLB;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_WITLB;
- if (Field_r_Slot_inst_get (insn) == 7)
- return OPCODE_RITLB1;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_HWWDTLBA;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_RDTLB0;
- if (Field_r_Slot_inst_get (insn) == 12 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_IDTLB;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_PDTLB;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_WDTLB;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_RDTLB1;
- }
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_NEG;
- if (Field_s_Slot_inst_get (insn) == 1)
- return OPCODE_ABS;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_ADD;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_ADDX2;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_ADDX4;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_ADDX8;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_SUB;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_SUBX2;
- if (Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_SUBX4;
- if (Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_SUBX8;
- }
- if (Field_op1_Slot_inst_get (insn) == 1)
- {
- if ((Field_op2_Slot_inst_get (insn) == 0 ||
- Field_op2_Slot_inst_get (insn) == 1))
- return OPCODE_SLLI;
- if ((Field_op2_Slot_inst_get (insn) == 2 ||
- Field_op2_Slot_inst_get (insn) == 3))
- return OPCODE_SRAI;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_SRLI;
- if (Field_op2_Slot_inst_get (insn) == 6)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_XSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_XSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_XSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_XSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 4)
- return OPCODE_XSR_BR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_XSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_XSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_XSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_XSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 83)
- return OPCODE_XSR_PTEVADDR;
- if (Field_sr_Slot_inst_get (insn) == 90)
- return OPCODE_XSR_RASID;
- if (Field_sr_Slot_inst_get (insn) == 91)
- return OPCODE_XSR_ITLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 92)
- return OPCODE_XSR_DTLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_XSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_XSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_XSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_XSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_XSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_XSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_XSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_XSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 224)
- return OPCODE_XSR_CPENABLE;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_XSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_XSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_XSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_XSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_XSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_XSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_XSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_XSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_XSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_XSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_XSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_XSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_XSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_SRC;
- if (Field_op2_Slot_inst_get (insn) == 9 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRL;
- if (Field_op2_Slot_inst_get (insn) == 10 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_SLL;
- if (Field_op2_Slot_inst_get (insn) == 11 &&
- Field_s_Slot_inst_get (insn) == 0)
- return OPCODE_SRA;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_MUL16U;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_MUL16S;
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_LICT;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_SICT;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_LICW;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_SICW;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_LDCT;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_SDCT;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_RFDO;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_RFDD;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_LDPTE;
- }
- }
- if (Field_op1_Slot_inst_get (insn) == 2)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_ANDB;
- if (Field_op2_Slot_inst_get (insn) == 1)
- return OPCODE_ANDBC;
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_ORB;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_ORBC;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_XORB;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MULL;
- }
- if (Field_op1_Slot_inst_get (insn) == 3)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_RSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_RSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_RSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_RSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 4)
- return OPCODE_RSR_BR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_RSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_RSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_RSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_RSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 83)
- return OPCODE_RSR_PTEVADDR;
- if (Field_sr_Slot_inst_get (insn) == 90)
- return OPCODE_RSR_RASID;
- if (Field_sr_Slot_inst_get (insn) == 91)
- return OPCODE_RSR_ITLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 92)
- return OPCODE_RSR_DTLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_RSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_RSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_RSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_RSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_RSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_RSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_RSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 208)
- return OPCODE_RSR_CONFIGID1;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_RSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_RSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 224)
- return OPCODE_RSR_CPENABLE;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_RSR_INTERRUPT;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_RSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_RSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_RSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_RSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_RSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_RSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 235)
- return OPCODE_RSR_PRID;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_RSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_RSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_RSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_RSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_RSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_RSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_RSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 1)
- {
- if (Field_sr_Slot_inst_get (insn) == 0)
- return OPCODE_WSR_LBEG;
- if (Field_sr_Slot_inst_get (insn) == 1)
- return OPCODE_WSR_LEND;
- if (Field_sr_Slot_inst_get (insn) == 2)
- return OPCODE_WSR_LCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 3)
- return OPCODE_WSR_SAR;
- if (Field_sr_Slot_inst_get (insn) == 4)
- return OPCODE_WSR_BR;
- if (Field_sr_Slot_inst_get (insn) == 5)
- return OPCODE_WSR_LITBASE;
- if (Field_sr_Slot_inst_get (insn) == 12)
- return OPCODE_WSR_SCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 72)
- return OPCODE_WSR_WINDOWBASE;
- if (Field_sr_Slot_inst_get (insn) == 73)
- return OPCODE_WSR_WINDOWSTART;
- if (Field_sr_Slot_inst_get (insn) == 83)
- return OPCODE_WSR_PTEVADDR;
- if (Field_sr_Slot_inst_get (insn) == 90)
- return OPCODE_WSR_RASID;
- if (Field_sr_Slot_inst_get (insn) == 91)
- return OPCODE_WSR_ITLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 92)
- return OPCODE_WSR_DTLBCFG;
- if (Field_sr_Slot_inst_get (insn) == 99)
- return OPCODE_WSR_ATOMCTL;
- if (Field_sr_Slot_inst_get (insn) == 104)
- return OPCODE_WSR_DDR;
- if (Field_sr_Slot_inst_get (insn) == 176)
- return OPCODE_WSR_CONFIGID0;
- if (Field_sr_Slot_inst_get (insn) == 177)
- return OPCODE_WSR_EPC1;
- if (Field_sr_Slot_inst_get (insn) == 178)
- return OPCODE_WSR_EPC2;
- if (Field_sr_Slot_inst_get (insn) == 192)
- return OPCODE_WSR_DEPC;
- if (Field_sr_Slot_inst_get (insn) == 194)
- return OPCODE_WSR_EPS2;
- if (Field_sr_Slot_inst_get (insn) == 209)
- return OPCODE_WSR_EXCSAVE1;
- if (Field_sr_Slot_inst_get (insn) == 210)
- return OPCODE_WSR_EXCSAVE2;
- if (Field_sr_Slot_inst_get (insn) == 224)
- return OPCODE_WSR_CPENABLE;
- if (Field_sr_Slot_inst_get (insn) == 226)
- return OPCODE_WSR_INTSET;
- if (Field_sr_Slot_inst_get (insn) == 227)
- return OPCODE_WSR_INTCLEAR;
- if (Field_sr_Slot_inst_get (insn) == 228)
- return OPCODE_WSR_INTENABLE;
- if (Field_sr_Slot_inst_get (insn) == 230)
- return OPCODE_WSR_PS;
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_WSR_VECBASE;
- if (Field_sr_Slot_inst_get (insn) == 232)
- return OPCODE_WSR_EXCCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 233)
- return OPCODE_WSR_DEBUGCAUSE;
- if (Field_sr_Slot_inst_get (insn) == 234)
- return OPCODE_WSR_CCOUNT;
- if (Field_sr_Slot_inst_get (insn) == 236)
- return OPCODE_WSR_ICOUNT;
- if (Field_sr_Slot_inst_get (insn) == 237)
- return OPCODE_WSR_ICOUNTLEVEL;
- if (Field_sr_Slot_inst_get (insn) == 238)
- return OPCODE_WSR_EXCVADDR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_WSR_CCOMPARE0;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_WSR_CCOMPARE1;
- if (Field_sr_Slot_inst_get (insn) == 244)
- return OPCODE_WSR_MISC0;
- if (Field_sr_Slot_inst_get (insn) == 245)
- return OPCODE_WSR_MISC1;
- }
- if (Field_op2_Slot_inst_get (insn) == 2)
- return OPCODE_SEXT;
- if (Field_op2_Slot_inst_get (insn) == 3)
- return OPCODE_CLAMPS;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_MIN;
- if (Field_op2_Slot_inst_get (insn) == 5)
- return OPCODE_MAX;
- if (Field_op2_Slot_inst_get (insn) == 6)
- return OPCODE_MINU;
- if (Field_op2_Slot_inst_get (insn) == 7)
- return OPCODE_MAXU;
- if (Field_op2_Slot_inst_get (insn) == 8)
- return OPCODE_MOVEQZ;
- if (Field_op2_Slot_inst_get (insn) == 9)
- return OPCODE_MOVNEZ;
- if (Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_MOVLTZ;
- if (Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_MOVGEZ;
- if (Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_MOVF;
- if (Field_op2_Slot_inst_get (insn) == 13)
- return OPCODE_MOVT;
- if (Field_op2_Slot_inst_get (insn) == 14)
- {
- if (Field_st_Slot_inst_get (insn) == 231)
- return OPCODE_RUR_THREADPTR;
- if (Field_st_Slot_inst_get (insn) == 240)
- return OPCODE_RUR_AE_OVF_SAR;
- if (Field_st_Slot_inst_get (insn) == 241)
- return OPCODE_RUR_AE_BITHEAD;
- if (Field_st_Slot_inst_get (insn) == 242)
- return OPCODE_RUR_AE_TS_FTS_BU_BP;
- if (Field_st_Slot_inst_get (insn) == 243)
- return OPCODE_RUR_AE_SD_NO;
- }
- if (Field_op2_Slot_inst_get (insn) == 15)
- {
- if (Field_sr_Slot_inst_get (insn) == 231)
- return OPCODE_WUR_THREADPTR;
- if (Field_sr_Slot_inst_get (insn) == 240)
- return OPCODE_WUR_AE_OVF_SAR;
- if (Field_sr_Slot_inst_get (insn) == 241)
- return OPCODE_WUR_AE_BITHEAD;
- if (Field_sr_Slot_inst_get (insn) == 242)
- return OPCODE_WUR_AE_TS_FTS_BU_BP;
- if (Field_sr_Slot_inst_get (insn) == 243)
- return OPCODE_WUR_AE_SD_NO;
- }
- }
- if ((Field_op1_Slot_inst_get (insn) == 4 ||
- Field_op1_Slot_inst_get (insn) == 5))
- return OPCODE_EXTUI;
- if (Field_op1_Slot_inst_get (insn) == 9)
- {
- if (Field_op2_Slot_inst_get (insn) == 0)
- return OPCODE_L32E;
- if (Field_op2_Slot_inst_get (insn) == 4)
- return OPCODE_S32E;
- }
- }
- if (Field_op0_Slot_inst_get (insn) == 1)
- return OPCODE_L32R;
- if (Field_op0_Slot_inst_get (insn) == 2)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_L8UI;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_L16UI;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_L32I;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_S8I;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_S16I;
- if (Field_r_Slot_inst_get (insn) == 6)
- return OPCODE_S32I;
- if (Field_r_Slot_inst_get (insn) == 7)
- {
- if (Field_t_Slot_inst_get (insn) == 0)
- return OPCODE_DPFR;
- if (Field_t_Slot_inst_get (insn) == 1)
- return OPCODE_DPFW;
- if (Field_t_Slot_inst_get (insn) == 2)
- return OPCODE_DPFRO;
- if (Field_t_Slot_inst_get (insn) == 3)
- return OPCODE_DPFWO;
- if (Field_t_Slot_inst_get (insn) == 4)
- return OPCODE_DHWB;
- if (Field_t_Slot_inst_get (insn) == 5)
- return OPCODE_DHWBI;
- if (Field_t_Slot_inst_get (insn) == 6)
- return OPCODE_DHI;
- if (Field_t_Slot_inst_get (insn) == 7)
- return OPCODE_DII;
- if (Field_t_Slot_inst_get (insn) == 8)
- {
- if (Field_op1_Slot_inst_get (insn) == 4)
- return OPCODE_DIWB;
- if (Field_op1_Slot_inst_get (insn) == 5)
- return OPCODE_DIWBI;
- }
- if (Field_t_Slot_inst_get (insn) == 12)
- return OPCODE_IPF;
- if (Field_t_Slot_inst_get (insn) == 14)
- return OPCODE_IHI;
- if (Field_t_Slot_inst_get (insn) == 15)
- return OPCODE_III;
- }
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_L16SI;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_MOVI;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_L32AI;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_ADDI;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_ADDMI;
- if (Field_r_Slot_inst_get (insn) == 14)
- return OPCODE_S32C1I;
- if (Field_r_Slot_inst_get (insn) == 15)
- return OPCODE_S32RI;
- }
- if (Field_op0_Slot_inst_get (insn) == 4)
- {
- if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_I;
- if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_X;
- if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_I;
- if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_X;
- if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_IU;
- if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ56_XU;
- if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_CVTQ48A32S;
- if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_IU;
- if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LQ32F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP24F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP24X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24S_L_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_ae_s3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVP48;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVPA24X2;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_CVTA32P24_L;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_LL;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_HL;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVAP24S_L;
- if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_TRUNCA16P24S_L;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16X2F_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16X2F_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP16X2F_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP16X2F_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LP24X2_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_LP24X2_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24X2S_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 12 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP16F_L_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_I;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_IU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_X;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 13 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_SP24F_L_XU;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_TRUNCP24A32X2;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 11 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_CVTA32P24_H;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 14 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_LH;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 15 &&
- Field_op2_Slot_inst_get (insn) == 11)
- return OPCODE_AE_CVTP24A16X2_HH;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVAP24S_H;
- if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 8 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_TRUNCA16P24S_H;
- if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_I;
- if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_X;
- if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_TRUNCA32Q48;
- if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_I;
- if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_X;
- if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_NSAQ56S;
- if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_IU;
- if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ56S_XU;
- if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_IU;
- if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SQ32F_XU;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLIQ56;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRLIQ56;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRAIQ56;
- if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
- Field_op1_Slot_inst_get (insn) == 5 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLISQ56S;
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SHA32;
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLDL32T;
- if (Field_op1_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SLLAQ56;
- if (Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLDL16T;
- if (Field_op1_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SRLAQ56;
- if (Field_op1_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_LBK;
- if (Field_op1_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SRAAQ56;
- if (Field_op1_Slot_inst_get (insn) == 3 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLEL32T;
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SLLASQ56S;
- if (Field_op1_Slot_inst_get (insn) == 4 &&
- Field_op2_Slot_inst_get (insn) == 10)
- return OPCODE_AE_VLEL16T;
- if (Field_op1_Slot_inst_get (insn) == 5 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_MOVTQ56;
- if (Field_op1_Slot_inst_get (insn) == 6 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_MOVFQ56;
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_OVERFLOW;
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_SBI;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_SAR;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_DB;
- if (Field_r_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_SB;
- if (Field_r_Slot_inst_get (insn) == 2 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_BITPTR;
- if (Field_r_Slot_inst_get (insn) == 3 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_BITSUSED;
- if (Field_r_Slot_inst_get (insn) == 4 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_TABLESIZE;
- if (Field_r_Slot_inst_get (insn) == 5 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_FIRST_TS;
- if (Field_r_Slot_inst_get (insn) == 6 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_NEXTOFFSET;
- if (Field_r_Slot_inst_get (insn) == 7 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_WUR_AE_SEARCHDONE;
- if (Field_r_Slot_inst_get (insn) == 8 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 10 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_VLDSHT;
- if (Field_r_Slot_inst_get (insn) == 12 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_VLES16C;
- if (Field_r_Slot_inst_get (insn) == 13 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_SBF;
- if (Field_r_Slot_inst_get (insn) == 14 &&
- Field_op1_Slot_inst_get (insn) == 7 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_VLDL16C;
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLSQ56;
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 6 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_LB;
- if (Field_s_Slot_inst_get (insn) == 1 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRLSQ56;
- if (Field_s_Slot_inst_get (insn) == 2 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SRASQ56;
- if (Field_s_Slot_inst_get (insn) == 3 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_SLLSSQ56S;
- if (Field_s_Slot_inst_get (insn) == 4 &&
- Field_t_Slot_inst_get (insn) == 1 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_AE_MOVQ56;
- if (Field_s_Slot_inst_get (insn) == 8 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_OVERFLOW;
- if (Field_s_Slot_inst_get (insn) == 9 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_SAR;
- if (Field_s_Slot_inst_get (insn) == 10 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_BITPTR;
- if (Field_s_Slot_inst_get (insn) == 11 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_BITSUSED;
- if (Field_s_Slot_inst_get (insn) == 12 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_TABLESIZE;
- if (Field_s_Slot_inst_get (insn) == 13 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_FIRST_TS;
- if (Field_s_Slot_inst_get (insn) == 14 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_NEXTOFFSET;
- if (Field_s_Slot_inst_get (insn) == 15 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_op1_Slot_inst_get (insn) == 9 &&
- Field_op2_Slot_inst_get (insn) == 12)
- return OPCODE_RUR_AE_SEARCHDONE;
- if (Field_t_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_LBKI;
- if (Field_t_Slot_inst_get (insn) == 0 &&
- Field_r_Slot_inst_get (insn) == 2 &&
- Field_op2_Slot_inst_get (insn) == 15)
- return OPCODE_AE_DBI;
- if (Field_t_Slot_inst_get (insn) == 2 &&
- Field_s_Slot_inst_get (insn) == 0 &&
- Field_op2_Slot_inst_get (insn) == 14)
- return OPCODE_AE_LBI;
- }
- if (Field_op0_Slot_inst_get (insn) == 5)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_CALL0;
- if (Field_n_Slot_inst_get (insn) == 1)
- return OPCODE_CALL4;
- if (Field_n_Slot_inst_get (insn) == 2)
- return OPCODE_CALL8;
- if (Field_n_Slot_inst_get (insn) == 3)
- return OPCODE_CALL12;
- }
- if (Field_op0_Slot_inst_get (insn) == 6)
- {
- if (Field_n_Slot_inst_get (insn) == 0)
- return OPCODE_J;
- if (Field_n_Slot_inst_get (insn) == 1)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQZ;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEZ;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTZ;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEZ;
- }
- if (Field_n_Slot_inst_get (insn) == 2)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_BEQI;
- if (Field_m_Slot_inst_get (insn) == 1)
- return OPCODE_BNEI;
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEI;
- }
- if (Field_n_Slot_inst_get (insn) == 3)
- {
- if (Field_m_Slot_inst_get (insn) == 0)
- return OPCODE_ENTRY;
- if (Field_m_Slot_inst_get (insn) == 1)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_BF;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_BT;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_LOOP;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_LOOPNEZ;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_LOOPGTZ;
- }
- if (Field_m_Slot_inst_get (insn) == 2)
- return OPCODE_BLTUI;
- if (Field_m_Slot_inst_get (insn) == 3)
- return OPCODE_BGEUI;
- }
- }
- if (Field_op0_Slot_inst_get (insn) == 7)
- {
- if (Field_r_Slot_inst_get (insn) == 0)
- return OPCODE_BNONE;
- if (Field_r_Slot_inst_get (insn) == 1)
- return OPCODE_BEQ;
- if (Field_r_Slot_inst_get (insn) == 2)
- return OPCODE_BLT;
- if (Field_r_Slot_inst_get (insn) == 3)
- return OPCODE_BLTU;
- if (Field_r_Slot_inst_get (insn) == 4)
- return OPCODE_BALL;
- if (Field_r_Slot_inst_get (insn) == 5)
- return OPCODE_BBC;
- if ((Field_r_Slot_inst_get (insn) == 6 ||
- Field_r_Slot_inst_get (insn) == 7))
- return OPCODE_BBCI;
- if (Field_r_Slot_inst_get (insn) == 8)
- return OPCODE_BANY;
- if (Field_r_Slot_inst_get (insn) == 9)
- return OPCODE_BNE;
- if (Field_r_Slot_inst_get (insn) == 10)
- return OPCODE_BGE;
- if (Field_r_Slot_inst_get (insn) == 11)
- return OPCODE_BGEU;
- if (Field_r_Slot_inst_get (insn) == 12)
- return OPCODE_BNALL;
- if (Field_r_Slot_inst_get (insn) == 13)
- return OPCODE_BBS;
- if ((Field_r_Slot_inst_get (insn) == 14 ||
- Field_r_Slot_inst_get (insn) == 15))
- return OPCODE_BBSI;
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16b_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16b_get (insn) == 12)
- {
- if (Field_i_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOVI_N;
- if (Field_i_Slot_inst16b_get (insn) == 1)
- {
- if (Field_z_Slot_inst16b_get (insn) == 0)
- return OPCODE_BEQZ_N;
- if (Field_z_Slot_inst16b_get (insn) == 1)
- return OPCODE_BNEZ_N;
- }
- }
- if (Field_op0_Slot_inst16b_get (insn) == 13)
- {
- if (Field_r_Slot_inst16b_get (insn) == 0)
- return OPCODE_MOV_N;
- if (Field_r_Slot_inst16b_get (insn) == 15)
- {
- if (Field_t_Slot_inst16b_get (insn) == 0)
- return OPCODE_RET_N;
- if (Field_t_Slot_inst16b_get (insn) == 1)
- return OPCODE_RETW_N;
- if (Field_t_Slot_inst16b_get (insn) == 2)
- return OPCODE_BREAK_N;
- if (Field_t_Slot_inst16b_get (insn) == 3 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_NOP_N;
- if (Field_t_Slot_inst16b_get (insn) == 6 &&
- Field_s_Slot_inst16b_get (insn) == 0)
- return OPCODE_ILL_N;
- }
- }
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_inst16a_decode (const xtensa_insnbuf insn)
-{
- if (Field_op0_Slot_inst16a_get (insn) == 8)
- return OPCODE_L32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 9)
- return OPCODE_S32I_N;
- if (Field_op0_Slot_inst16a_get (insn) == 10)
- return OPCODE_ADD_N;
- if (Field_op0_Slot_inst16a_get (insn) == 11)
- return OPCODE_ADDI_N;
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_ae_slot0_decode (const xtensa_insnbuf insn)
-{
- if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_J;
- if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_EXTUI;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BGEZ;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BLTZ;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BEQZ;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_BNEZ;
- if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVI;
- if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRAI;
- if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SLLI;
- if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVTQ56;
- if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_HH;
- if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4 &&
- Field_ae_r20_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_L32I;
- if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_I;
- if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_HL;
- if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_IU;
- if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_X;
- if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16F_XU;
- if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_LH;
- if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_I;
- if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_IU;
- if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_XU;
- if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP16X2F_X;
- if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_I;
- if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_IU;
- if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_X;
- if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTP24A16X2_LL;
- if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24_XU;
- if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_I;
- if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_XU;
- if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_IU;
- if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_I;
- if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_IU;
- if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_X;
- if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24F_X;
- if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2_XU;
- if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_I;
- if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_X;
- if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_IU;
- if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LP24X2F_XU;
- if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVPA24X2;
- if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_I;
- if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_IU;
- if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_X;
- if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_X;
- if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_XU;
- if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_I;
- if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_IU;
- if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16F_L_XU;
- if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_X;
- if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24F_L_XU;
- if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_IU;
- if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_I;
- if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_X;
- if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24S_L_XU;
- if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_I;
- if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_I;
- if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_IU;
- if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_X;
- if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_IU;
- if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2F_XU;
- if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_X;
- if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_XU;
- if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_TRUNCP24A32X2;
- if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP24X2S_I;
- if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ32F_I;
- if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ32F_IU;
- if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ32F_I;
- if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ32F_X;
- if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ32F_XU;
- if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ56_I;
- if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ32F_IU;
- if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ56_IU;
- if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_LQ56_X;
- if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTQ48A32S;
- if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_JX;
- if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SSR;
- if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_NOP;
- if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSA8B;
- if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSA8L;
- if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSL;
- if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s8_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_LQ56_XU;
- if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ALL8;
- if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBCI;
- if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBSI;
- if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_s_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ANY8;
- if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_SSAI;
- if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SP16X2F_IU;
- if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_I;
- if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_IU;
- if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLIQ56;
- if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SRAIQ56;
- if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SRLIQ56;
- if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLISQ56S;
- if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ABS;
- if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_NEG;
- if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRA;
- if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRL;
- if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVP48;
- if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ANY4;
- if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_MOVQ56;
- if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SLLSSQ56S;
- if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRASQ56;
- if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRLSQ56;
- if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SLLSQ56;
- if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_ALL4;
- if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_X;
- if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SQ56S_XU;
- if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTA32P24_H;
- if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_CVTA32P24_L;
- if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVAP24S_H;
- if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_TRUNCA16P24S_L;
- if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVAP24S_L;
- if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_NSAQ56S;
- if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_TRUNCA32Q48;
- if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
- Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_BT;
- if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_TRUNCA16P24S_H;
- if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
- Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_BLTUI;
- if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_MOVFQ56;
- if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLAQ56;
- if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AE_SLLASQ56S;
- if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SLL;
- if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf357_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRAAQ56;
- if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SRLAQ56;
- if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SQ32F_XU;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 178 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADD;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 179 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADDX8;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 180 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADDX2;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 181 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_AND;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 182 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ANDB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ANDBC;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 184 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ADDX4;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 185 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_CLAMPS;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 186 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MAX;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 187 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MIN;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 188 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MAXU;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 189 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MINU;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 190 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVEQZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 191 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVF;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 194 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVGEZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 195 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ORB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 196 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVLTZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 197 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_ORBC;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 198 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SEXT;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRC;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 200 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVNEZ;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 201 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SRLI;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 202 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 203 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUBX4;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 204 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUBX2;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 205 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_SUBX8;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 206 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_XOR;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 207 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_XORB;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 208 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_MOVT;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 224 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
- return OPCODE_OR;
- if (Field_imm8_Slot_ae_slot0_get (insn) == 244 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
- Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_AE_SQ32F_X;
- if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
- return OPCODE_L32R;
- if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_BNE;
- if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_BNONE;
- if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_L16SI;
- if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_L8UI;
- if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_ADDI;
- if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_L16UI;
- if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BALL;
- if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_S16I;
- if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BANY;
- if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_S32I;
- if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBC;
- if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
- return OPCODE_S8I;
- if (Field_r_Slot_ae_slot0_get (insn) == 8 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_ADDMI;
- if (Field_r_Slot_ae_slot0_get (insn) == 9 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BBS;
- if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BEQ;
- if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BGEU;
- if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BGE;
- if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BLT;
- if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BLTU;
- if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
- return OPCODE_BNALL;
- if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BEQI;
- if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BGEI;
- if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BGEUI;
- if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BNEI;
- if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
- return OPCODE_BLTI;
- if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
- Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
- Field_r_Slot_ae_slot0_get (insn) == 0)
- return OPCODE_BF;
- return XTENSA_UNDEFINED;
-}
-
-static int
-Slot_ae_slot1_decode (const xtensa_insnbuf insn)
-{
- if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_NEGSP24S;
- if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ABSSP24S;
- if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_NEGP24;
- if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MAXBQ56S;
- if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MINBQ56S;
- if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ae_r32_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_EQQ56;
- if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ADDSQ56S;
- if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ANDQ56;
- if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MAXQ56S;
- if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ORQ56;
- if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_MINQ56S;
- if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_SUBQ56;
- if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_SUBSQ56S;
- if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_XORQ56;
- if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_NANDQ56;
- if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_ABSQ56;
- if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5)
- return OPCODE_AE_NEGSQ56S;
- if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf338_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_SATQ48S;
- if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_LTQ56S;
- if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ABSSQ56S;
- if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_NEGQ56;
- if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_LEQ56S;
- if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_TRUNCP24Q48X2;
- if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 5 &&
- Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ADDQ56;
- if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAFP24S_HH_LL;
- if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAFP24S_HL_LH;
- if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAP24S_HH_LL;
- if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf12_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_SLLISP24S;
- if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS32P16S_HL;
- if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAAP24S_HL_LH;
- if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS32P16S_LH;
- if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS32P16S_LL;
- if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_HH;
- if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_HH;
- if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_HL;
- if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_LH;
- if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_HH;
- if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFS56P24S_LL;
- if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_HL;
- if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_LH;
- if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAP24S_LL;
- if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_HL;
- if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_HH;
- if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_HL;
- if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASFP24S_HH_LL;
- if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_LH;
- if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASFP24S_HL_LH;
- if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASP24S_HH_LL;
- if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULASP24S_HL_LH;
- if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAS56P24S_LL;
- if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_HH;
- if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_HL;
- if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_LL;
- if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFP24S_LH;
- if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_HH;
- if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_HL;
- if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_LH;
- if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_LH;
- if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULFS32P16S_LL;
- if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_HH;
- if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAFP24S_HH_LL;
- if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_HL;
- if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAFP24S_HL_LH;
- if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAP24S_HH_LL;
- if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSAP24S_HL_LH;
- if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_LH;
- if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_HH;
- if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_HL;
- if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_LL;
- if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFP24S_LH;
- if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_HH;
- if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_HL;
- if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_LH;
- if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULP24S_LL;
- if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS32P16S_LL;
- if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_HH;
- if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_LL;
- if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_HL;
- if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_HH;
- if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_HL;
- if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_LH;
- if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSFS56P24S_LH;
- if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSP24S_LL;
- if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_HH;
- if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_LH;
- if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_HL;
- if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSS56P24S_LL;
- if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSFP24S_HH_LL;
- if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSFP24S_HL_LH;
- if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULAFP24S_LL;
- if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSP24S_HH_LL;
- if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULSSP24S_HL_LH;
- if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASFP24S_HH_LL;
- if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZAAFP24S_HH_LL;
- if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASFP24S_HL_LH;
- if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASP24S_HH_LL;
- if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZASP24S_HL_LH;
- if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZAAFP24S_HL_LH;
- if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAFP24S_HH_LL;
- if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAFP24S_HL_LH;
- if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAP24S_HL_LH;
- if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSAP24S_HH_LL;
- if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSSFP24S_HH_LL;
- if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSSFP24S_HL_LH;
- if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6)
- return OPCODE_AE_MULZSSP24S_HH_LL;
- if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULZAAP24S_HH_LL;
- if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULZSSP24S_HL_LH;
- if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULZAAP24S_HL_LH;
- if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 6 &&
- Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULAFS32P16S_HH;
- if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MAXBP24S;
- if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MINBP24S;
- if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVFP48;
- if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVTP48;
- if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ADDP24;
- if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ANDP48;
- if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MAXP24S;
- if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MINP24S;
- if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ADDSP24S;
- if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_NANDP48;
- if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ORP48;
- if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_HL;
- if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_HH;
- if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_LH;
- if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SELP24_LL;
- if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SUBP24;
- if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SLLIP24;
- if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRAIP24;
- if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRLIP24;
- if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16S_L;
- if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16U_H;
- if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16U_L;
- if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16U_H;
- if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16S_H;
- if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16U_L;
- if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16S_H;
- if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16S_L;
- if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAQ32SP16S_L;
- if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16U_H;
- if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULFQ32SP16U_L;
- if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16S_L;
- if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16S_H;
- if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16U_H;
- if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULQ32SP16U_L;
- if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16S_H;
- if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULAFQ32SP16S_H;
- if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16S_L;
- if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16U_H;
- if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSQ32SP16U_L;
- if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MULSFQ32SP16U_L;
- if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_CVTQ48P24S_H;
- if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ZEROQ56;
- if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_NOP;
- if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_CVTQ48P24S_L;
- if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVQ56;
- if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSQ32ASYM;
- if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSQ32SYM;
- if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_TRUNCQ32;
- if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULSQ32SP16S_H;
- if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULSQ32SP16S_L;
- if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_MOVP48;
- if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSP16ASYM;
- if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSP16SYM;
- if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRASP24;
- if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SLLSP24;
- if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SRLSP24;
- if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_TRUNCP16;
- if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ZEROP48;
- if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r10_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_SLLSSP24S;
- if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSP16Q48ASYM;
- if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_ROUNDSP16Q48SYM;
- if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSP24Q48ASYM;
- if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf340_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ROUNDSP24Q48SYM;
- if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MULSQ32SP16U_H;
- if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_EQP24;
- if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_LEP24S;
- if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf208_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_LTP24S;
- if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ftsf347_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MOVFP24X2;
- if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_s20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_MOVTP24X2;
- if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_SUBSP24S;
- if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
- return OPCODE_AE_XORP48;
- if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
- Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
- return OPCODE_AE_ABSP24;
- if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSAQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZASQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZAAQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAFQ32SP16U_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16S_LL;
- if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAQ32SP16S_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16U_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
- return OPCODE_AE_MULZASFQ32SP16U_HH;
- if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
- return OPCODE_AE_MULZSAQ32SP16S_LH;
- if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
- Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
- return OPCODE_AE_MULZSSQ32SP16U_LL;
- return XTENSA_UNDEFINED;
-}
-
-\f
-/* Instruction slots. */
-
-static void
-Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = (insn[0] & 0xffffff);
-}
-
-static void
-Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = (insn[0] & 0xffff);
-}
-
-static void
-Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
-}
-
-static void
-Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[0] & 0x80000000) >> 31);
- slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1);
-}
-
-static void
-Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31);
- insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1);
-}
-
-static void
-Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
-{
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4);
-}
-
-static void
-Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
-{
- insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4);
-}
-
-static xtensa_get_field_fn
-Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst_get,
- Field_s2_Slot_inst_get,
- Field_r2_Slot_inst_get,
- Field_t4_Slot_inst_get,
- Field_s4_Slot_inst_get,
- Field_r4_Slot_inst_get,
- Field_t8_Slot_inst_get,
- Field_s8_Slot_inst_get,
- Field_r8_Slot_inst_get,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- Field_ae_r3_Slot_inst_get,
- Field_ae_s_non_samt_Slot_inst_get,
- Field_ae_s3_Slot_inst_get,
- Field_ae_r32_Slot_inst_get,
- Field_ae_samt_s_t_Slot_inst_get,
- Field_ae_r20_Slot_inst_get,
- Field_ae_r10_Slot_inst_get,
- Field_ae_s20_Slot_inst_get,
- Field_ae_fld_ohba_Slot_inst_get,
- Field_ae_fld_ohba2_Slot_inst_get,
- 0,
- Field_ftsf12_Slot_inst_get,
- Field_ftsf13_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst_set,
- Field_s2_Slot_inst_set,
- Field_r2_Slot_inst_set,
- Field_t4_Slot_inst_set,
- Field_s4_Slot_inst_set,
- Field_r4_Slot_inst_set,
- Field_t8_Slot_inst_set,
- Field_s8_Slot_inst_set,
- Field_r8_Slot_inst_set,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- Field_ae_r3_Slot_inst_set,
- Field_ae_s_non_samt_Slot_inst_set,
- Field_ae_s3_Slot_inst_set,
- Field_ae_r32_Slot_inst_set,
- Field_ae_samt_s_t_Slot_inst_set,
- Field_ae_r20_Slot_inst_set,
- Field_ae_r10_Slot_inst_set,
- Field_ae_s20_Slot_inst_set,
- Field_ae_fld_ohba_Slot_inst_set,
- Field_ae_fld_ohba2_Slot_inst_set,
- 0,
- Field_ftsf12_Slot_inst_set,
- Field_ftsf13_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- Field_t2_Slot_inst16a_get,
- Field_s2_Slot_inst16a_get,
- Field_r2_Slot_inst16a_get,
- Field_t4_Slot_inst16a_get,
- Field_s4_Slot_inst16a_get,
- Field_r4_Slot_inst16a_get,
- Field_t8_Slot_inst16a_get,
- Field_s8_Slot_inst16a_get,
- Field_r8_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- Field_t2_Slot_inst16a_set,
- Field_s2_Slot_inst16a_set,
- Field_r2_Slot_inst16a_set,
- Field_t4_Slot_inst16a_set,
- Field_s4_Slot_inst16a_set,
- Field_r4_Slot_inst16a_set,
- Field_t8_Slot_inst16a_set,
- Field_s8_Slot_inst16a_set,
- Field_r8_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- Field_t2_Slot_inst16b_get,
- Field_s2_Slot_inst16b_get,
- Field_r2_Slot_inst16b_get,
- Field_t4_Slot_inst16b_get,
- Field_s4_Slot_inst16b_get,
- Field_r4_Slot_inst16b_get,
- Field_t8_Slot_inst16b_get,
- Field_s8_Slot_inst16b_get,
- Field_r8_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- Field_t2_Slot_inst16b_set,
- Field_s2_Slot_inst16b_set,
- Field_r2_Slot_inst16b_set,
- Field_t4_Slot_inst16b_set,
- Field_s4_Slot_inst16b_set,
- Field_r4_Slot_inst16b_set,
- Field_t8_Slot_inst16b_set,
- Field_s8_Slot_inst16b_set,
- Field_r8_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
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- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_ae_slot1_get_field_fns[] = {
- Field_t_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot1_get,
- 0,
- Field_ae_r20_Slot_ae_slot1_get,
- Field_ae_r10_Slot_ae_slot1_get,
- Field_ae_s20_Slot_ae_slot1_get,
- 0,
- 0,
- Field_op0_s3_Slot_ae_slot1_get,
- Field_ftsf12_Slot_ae_slot1_get,
- Field_ftsf13_Slot_ae_slot1_get,
- Field_ftsf14_Slot_ae_slot1_get,
- Field_ftsf21ae_slot1_Slot_ae_slot1_get,
- Field_ftsf22ae_slot1_Slot_ae_slot1_get,
- Field_ftsf23ae_slot1_Slot_ae_slot1_get,
- Field_ftsf24ae_slot1_Slot_ae_slot1_get,
- Field_ftsf25ae_slot1_Slot_ae_slot1_get,
- Field_ftsf26ae_slot1_Slot_ae_slot1_get,
- Field_ftsf27ae_slot1_Slot_ae_slot1_get,
- Field_ftsf28ae_slot1_Slot_ae_slot1_get,
- Field_ftsf29ae_slot1_Slot_ae_slot1_get,
- Field_ftsf30ae_slot1_Slot_ae_slot1_get,
- Field_ftsf31ae_slot1_Slot_ae_slot1_get,
- Field_ftsf32ae_slot1_Slot_ae_slot1_get,
- Field_ftsf33ae_slot1_Slot_ae_slot1_get,
- Field_ftsf34ae_slot1_Slot_ae_slot1_get,
- Field_ftsf35ae_slot1_Slot_ae_slot1_get,
- Field_ftsf36ae_slot1_Slot_ae_slot1_get,
- Field_ftsf37ae_slot1_Slot_ae_slot1_get,
- Field_ftsf38ae_slot1_Slot_ae_slot1_get,
- Field_ftsf39ae_slot1_Slot_ae_slot1_get,
- Field_ftsf40ae_slot1_Slot_ae_slot1_get,
- Field_ftsf41ae_slot1_Slot_ae_slot1_get,
- Field_ftsf42ae_slot1_Slot_ae_slot1_get,
- Field_ftsf43ae_slot1_Slot_ae_slot1_get,
- Field_ftsf44ae_slot1_Slot_ae_slot1_get,
- Field_ftsf45ae_slot1_Slot_ae_slot1_get,
- Field_ftsf46ae_slot1_Slot_ae_slot1_get,
- Field_ftsf47ae_slot1_Slot_ae_slot1_get,
- Field_ftsf48ae_slot1_Slot_ae_slot1_get,
- Field_ftsf49ae_slot1_Slot_ae_slot1_get,
- Field_ftsf50ae_slot1_Slot_ae_slot1_get,
- Field_ftsf51ae_slot1_Slot_ae_slot1_get,
- Field_ftsf52ae_slot1_Slot_ae_slot1_get,
- Field_ftsf53ae_slot1_Slot_ae_slot1_get,
- Field_ftsf54ae_slot1_Slot_ae_slot1_get,
- Field_ftsf55ae_slot1_Slot_ae_slot1_get,
- Field_ftsf56ae_slot1_Slot_ae_slot1_get,
- Field_ftsf57ae_slot1_Slot_ae_slot1_get,
- Field_ftsf58ae_slot1_Slot_ae_slot1_get,
- Field_ftsf59ae_slot1_Slot_ae_slot1_get,
- Field_ftsf60ae_slot1_Slot_ae_slot1_get,
- Field_ftsf61ae_slot1_Slot_ae_slot1_get,
- Field_ftsf63ae_slot1_Slot_ae_slot1_get,
- Field_ftsf64ae_slot1_Slot_ae_slot1_get,
- Field_ftsf66ae_slot1_Slot_ae_slot1_get,
- Field_ftsf67ae_slot1_Slot_ae_slot1_get,
- Field_ftsf69ae_slot1_Slot_ae_slot1_get,
- Field_ftsf71ae_slot1_Slot_ae_slot1_get,
- Field_ftsf72ae_slot1_Slot_ae_slot1_get,
- Field_ftsf73ae_slot1_Slot_ae_slot1_get,
- Field_ftsf75ae_slot1_Slot_ae_slot1_get,
- Field_ftsf76ae_slot1_Slot_ae_slot1_get,
- Field_ftsf77ae_slot1_Slot_ae_slot1_get,
- Field_ftsf78ae_slot1_Slot_ae_slot1_get,
- Field_ftsf79ae_slot1_Slot_ae_slot1_get,
- Field_ftsf80ae_slot1_Slot_ae_slot1_get,
- Field_ftsf81ae_slot1_Slot_ae_slot1_get,
- Field_ftsf82ae_slot1_Slot_ae_slot1_get,
- Field_ftsf84ae_slot1_Slot_ae_slot1_get,
- Field_ftsf86ae_slot1_Slot_ae_slot1_get,
- Field_ftsf87ae_slot1_Slot_ae_slot1_get,
- Field_ftsf88ae_slot1_Slot_ae_slot1_get,
- Field_ftsf89ae_slot1_Slot_ae_slot1_get,
- Field_ftsf90ae_slot1_Slot_ae_slot1_get,
- Field_ftsf91ae_slot1_Slot_ae_slot1_get,
- Field_ftsf92ae_slot1_Slot_ae_slot1_get,
- Field_ftsf94ae_slot1_Slot_ae_slot1_get,
- Field_ftsf96ae_slot1_Slot_ae_slot1_get,
- Field_ftsf97ae_slot1_Slot_ae_slot1_get,
- Field_ftsf98ae_slot1_Slot_ae_slot1_get,
- Field_ftsf99ae_slot1_Slot_ae_slot1_get,
- Field_ftsf100ae_slot1_Slot_ae_slot1_get,
- Field_ftsf101ae_slot1_Slot_ae_slot1_get,
- Field_ftsf103ae_slot1_Slot_ae_slot1_get,
- Field_ftsf104ae_slot1_Slot_ae_slot1_get,
- Field_ftsf105ae_slot1_Slot_ae_slot1_get,
- Field_ftsf106ae_slot1_Slot_ae_slot1_get,
- Field_ftsf107ae_slot1_Slot_ae_slot1_get,
- Field_ftsf108ae_slot1_Slot_ae_slot1_get,
- Field_ftsf109ae_slot1_Slot_ae_slot1_get,
- Field_ftsf110ae_slot1_Slot_ae_slot1_get,
- Field_ftsf111ae_slot1_Slot_ae_slot1_get,
- Field_ftsf112ae_slot1_Slot_ae_slot1_get,
- Field_ftsf113ae_slot1_Slot_ae_slot1_get,
- Field_ftsf114ae_slot1_Slot_ae_slot1_get,
- Field_ftsf115ae_slot1_Slot_ae_slot1_get,
- Field_ftsf116ae_slot1_Slot_ae_slot1_get,
- Field_ftsf118ae_slot1_Slot_ae_slot1_get,
- Field_ftsf119ae_slot1_Slot_ae_slot1_get,
- Field_ftsf120ae_slot1_Slot_ae_slot1_get,
- Field_ftsf122ae_slot1_Slot_ae_slot1_get,
- Field_ftsf124ae_slot1_Slot_ae_slot1_get,
- Field_ftsf125ae_slot1_Slot_ae_slot1_get,
- Field_ftsf126ae_slot1_Slot_ae_slot1_get,
- Field_ftsf127ae_slot1_Slot_ae_slot1_get,
- Field_ftsf128ae_slot1_Slot_ae_slot1_get,
- Field_ftsf129ae_slot1_Slot_ae_slot1_get,
- Field_ftsf130ae_slot1_Slot_ae_slot1_get,
- Field_ftsf131ae_slot1_Slot_ae_slot1_get,
- Field_ftsf132ae_slot1_Slot_ae_slot1_get,
- Field_ftsf133ae_slot1_Slot_ae_slot1_get,
- Field_ftsf134ae_slot1_Slot_ae_slot1_get,
- Field_ftsf135ae_slot1_Slot_ae_slot1_get,
- Field_ftsf136ae_slot1_Slot_ae_slot1_get,
- Field_ftsf137ae_slot1_Slot_ae_slot1_get,
- Field_ftsf138ae_slot1_Slot_ae_slot1_get,
- Field_ftsf139ae_slot1_Slot_ae_slot1_get,
- Field_ftsf140ae_slot1_Slot_ae_slot1_get,
- Field_ftsf141ae_slot1_Slot_ae_slot1_get,
- Field_ftsf142ae_slot1_Slot_ae_slot1_get,
- Field_ftsf143ae_slot1_Slot_ae_slot1_get,
- Field_ftsf144ae_slot1_Slot_ae_slot1_get,
- Field_ftsf145ae_slot1_Slot_ae_slot1_get,
- Field_ftsf146ae_slot1_Slot_ae_slot1_get,
- Field_ftsf147ae_slot1_Slot_ae_slot1_get,
- Field_ftsf148ae_slot1_Slot_ae_slot1_get,
- Field_ftsf149ae_slot1_Slot_ae_slot1_get,
- Field_ftsf150ae_slot1_Slot_ae_slot1_get,
- Field_ftsf151ae_slot1_Slot_ae_slot1_get,
- Field_ftsf152ae_slot1_Slot_ae_slot1_get,
- Field_ftsf153ae_slot1_Slot_ae_slot1_get,
- Field_ftsf154ae_slot1_Slot_ae_slot1_get,
- Field_ftsf155ae_slot1_Slot_ae_slot1_get,
- Field_ftsf156ae_slot1_Slot_ae_slot1_get,
- Field_ftsf157ae_slot1_Slot_ae_slot1_get,
- Field_ftsf158ae_slot1_Slot_ae_slot1_get,
- Field_ftsf159ae_slot1_Slot_ae_slot1_get,
- Field_ftsf160ae_slot1_Slot_ae_slot1_get,
- Field_ftsf161ae_slot1_Slot_ae_slot1_get,
- Field_ftsf162ae_slot1_Slot_ae_slot1_get,
- Field_ftsf163ae_slot1_Slot_ae_slot1_get,
- Field_ftsf164ae_slot1_Slot_ae_slot1_get,
- Field_ftsf165ae_slot1_Slot_ae_slot1_get,
- Field_ftsf166ae_slot1_Slot_ae_slot1_get,
- Field_ftsf167ae_slot1_Slot_ae_slot1_get,
- Field_ftsf168ae_slot1_Slot_ae_slot1_get,
- Field_ftsf169ae_slot1_Slot_ae_slot1_get,
- Field_ftsf170ae_slot1_Slot_ae_slot1_get,
- Field_ftsf171ae_slot1_Slot_ae_slot1_get,
- Field_ftsf172ae_slot1_Slot_ae_slot1_get,
- Field_ftsf173ae_slot1_Slot_ae_slot1_get,
- Field_ftsf174ae_slot1_Slot_ae_slot1_get,
- Field_ftsf175ae_slot1_Slot_ae_slot1_get,
- Field_ftsf176ae_slot1_Slot_ae_slot1_get,
- Field_ftsf177ae_slot1_Slot_ae_slot1_get,
- Field_ftsf178ae_slot1_Slot_ae_slot1_get,
- Field_ftsf179ae_slot1_Slot_ae_slot1_get,
- Field_ftsf180ae_slot1_Slot_ae_slot1_get,
- Field_ftsf181ae_slot1_Slot_ae_slot1_get,
- Field_ftsf182ae_slot1_Slot_ae_slot1_get,
- Field_ftsf183ae_slot1_Slot_ae_slot1_get,
- Field_ftsf184ae_slot1_Slot_ae_slot1_get,
- Field_ftsf185ae_slot1_Slot_ae_slot1_get,
- Field_ftsf186ae_slot1_Slot_ae_slot1_get,
- Field_ftsf187ae_slot1_Slot_ae_slot1_get,
- Field_ftsf188ae_slot1_Slot_ae_slot1_get,
- Field_ftsf189ae_slot1_Slot_ae_slot1_get,
- Field_ftsf190ae_slot1_Slot_ae_slot1_get,
- Field_ftsf191ae_slot1_Slot_ae_slot1_get,
- Field_ftsf192ae_slot1_Slot_ae_slot1_get,
- Field_ftsf193ae_slot1_Slot_ae_slot1_get,
- Field_ftsf194ae_slot1_Slot_ae_slot1_get,
- Field_ftsf195ae_slot1_Slot_ae_slot1_get,
- Field_ftsf196ae_slot1_Slot_ae_slot1_get,
- Field_ftsf197ae_slot1_Slot_ae_slot1_get,
- Field_ftsf198ae_slot1_Slot_ae_slot1_get,
- Field_ftsf199ae_slot1_Slot_ae_slot1_get,
- Field_ftsf200ae_slot1_Slot_ae_slot1_get,
- Field_ftsf201ae_slot1_Slot_ae_slot1_get,
- Field_ftsf202ae_slot1_Slot_ae_slot1_get,
- Field_ftsf203ae_slot1_Slot_ae_slot1_get,
- Field_ftsf204ae_slot1_Slot_ae_slot1_get,
- Field_ftsf205ae_slot1_Slot_ae_slot1_get,
- Field_ftsf206ae_slot1_Slot_ae_slot1_get,
- Field_ftsf207ae_slot1_Slot_ae_slot1_get,
- Field_ftsf208_Slot_ae_slot1_get,
- Field_ftsf209ae_slot1_Slot_ae_slot1_get,
- Field_ftsf210ae_slot1_Slot_ae_slot1_get,
- Field_ftsf211ae_slot1_Slot_ae_slot1_get,
- Field_ftsf330ae_slot1_Slot_ae_slot1_get,
- Field_ftsf332ae_slot1_Slot_ae_slot1_get,
- Field_ftsf334ae_slot1_Slot_ae_slot1_get,
- Field_ftsf336ae_slot1_Slot_ae_slot1_get,
- Field_ftsf337ae_slot1_Slot_ae_slot1_get,
- Field_ftsf338_Slot_ae_slot1_get,
- Field_ftsf339ae_slot1_Slot_ae_slot1_get,
- Field_ftsf340_Slot_ae_slot1_get,
- Field_ftsf341ae_slot1_Slot_ae_slot1_get,
- Field_ftsf342ae_slot1_Slot_ae_slot1_get,
- Field_ftsf343ae_slot1_Slot_ae_slot1_get,
- Field_ftsf344ae_slot1_Slot_ae_slot1_get,
- Field_ftsf346ae_slot1_Slot_ae_slot1_get,
- Field_ftsf347_Slot_ae_slot1_get,
- Field_ftsf348ae_slot1_Slot_ae_slot1_get,
- Field_ftsf349ae_slot1_Slot_ae_slot1_get,
- Field_ftsf350ae_slot1_Slot_ae_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_ae_slot1_set_field_fns[] = {
- Field_t_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot1_set,
- 0,
- Field_ae_r20_Slot_ae_slot1_set,
- Field_ae_r10_Slot_ae_slot1_set,
- Field_ae_s20_Slot_ae_slot1_set,
- 0,
- 0,
- Field_op0_s3_Slot_ae_slot1_set,
- Field_ftsf12_Slot_ae_slot1_set,
- Field_ftsf13_Slot_ae_slot1_set,
- Field_ftsf14_Slot_ae_slot1_set,
- Field_ftsf21ae_slot1_Slot_ae_slot1_set,
- Field_ftsf22ae_slot1_Slot_ae_slot1_set,
- Field_ftsf23ae_slot1_Slot_ae_slot1_set,
- Field_ftsf24ae_slot1_Slot_ae_slot1_set,
- Field_ftsf25ae_slot1_Slot_ae_slot1_set,
- Field_ftsf26ae_slot1_Slot_ae_slot1_set,
- Field_ftsf27ae_slot1_Slot_ae_slot1_set,
- Field_ftsf28ae_slot1_Slot_ae_slot1_set,
- Field_ftsf29ae_slot1_Slot_ae_slot1_set,
- Field_ftsf30ae_slot1_Slot_ae_slot1_set,
- Field_ftsf31ae_slot1_Slot_ae_slot1_set,
- Field_ftsf32ae_slot1_Slot_ae_slot1_set,
- Field_ftsf33ae_slot1_Slot_ae_slot1_set,
- Field_ftsf34ae_slot1_Slot_ae_slot1_set,
- Field_ftsf35ae_slot1_Slot_ae_slot1_set,
- Field_ftsf36ae_slot1_Slot_ae_slot1_set,
- Field_ftsf37ae_slot1_Slot_ae_slot1_set,
- Field_ftsf38ae_slot1_Slot_ae_slot1_set,
- Field_ftsf39ae_slot1_Slot_ae_slot1_set,
- Field_ftsf40ae_slot1_Slot_ae_slot1_set,
- Field_ftsf41ae_slot1_Slot_ae_slot1_set,
- Field_ftsf42ae_slot1_Slot_ae_slot1_set,
- Field_ftsf43ae_slot1_Slot_ae_slot1_set,
- Field_ftsf44ae_slot1_Slot_ae_slot1_set,
- Field_ftsf45ae_slot1_Slot_ae_slot1_set,
- Field_ftsf46ae_slot1_Slot_ae_slot1_set,
- Field_ftsf47ae_slot1_Slot_ae_slot1_set,
- Field_ftsf48ae_slot1_Slot_ae_slot1_set,
- Field_ftsf49ae_slot1_Slot_ae_slot1_set,
- Field_ftsf50ae_slot1_Slot_ae_slot1_set,
- Field_ftsf51ae_slot1_Slot_ae_slot1_set,
- Field_ftsf52ae_slot1_Slot_ae_slot1_set,
- Field_ftsf53ae_slot1_Slot_ae_slot1_set,
- Field_ftsf54ae_slot1_Slot_ae_slot1_set,
- Field_ftsf55ae_slot1_Slot_ae_slot1_set,
- Field_ftsf56ae_slot1_Slot_ae_slot1_set,
- Field_ftsf57ae_slot1_Slot_ae_slot1_set,
- Field_ftsf58ae_slot1_Slot_ae_slot1_set,
- Field_ftsf59ae_slot1_Slot_ae_slot1_set,
- Field_ftsf60ae_slot1_Slot_ae_slot1_set,
- Field_ftsf61ae_slot1_Slot_ae_slot1_set,
- Field_ftsf63ae_slot1_Slot_ae_slot1_set,
- Field_ftsf64ae_slot1_Slot_ae_slot1_set,
- Field_ftsf66ae_slot1_Slot_ae_slot1_set,
- Field_ftsf67ae_slot1_Slot_ae_slot1_set,
- Field_ftsf69ae_slot1_Slot_ae_slot1_set,
- Field_ftsf71ae_slot1_Slot_ae_slot1_set,
- Field_ftsf72ae_slot1_Slot_ae_slot1_set,
- Field_ftsf73ae_slot1_Slot_ae_slot1_set,
- Field_ftsf75ae_slot1_Slot_ae_slot1_set,
- Field_ftsf76ae_slot1_Slot_ae_slot1_set,
- Field_ftsf77ae_slot1_Slot_ae_slot1_set,
- Field_ftsf78ae_slot1_Slot_ae_slot1_set,
- Field_ftsf79ae_slot1_Slot_ae_slot1_set,
- Field_ftsf80ae_slot1_Slot_ae_slot1_set,
- Field_ftsf81ae_slot1_Slot_ae_slot1_set,
- Field_ftsf82ae_slot1_Slot_ae_slot1_set,
- Field_ftsf84ae_slot1_Slot_ae_slot1_set,
- Field_ftsf86ae_slot1_Slot_ae_slot1_set,
- Field_ftsf87ae_slot1_Slot_ae_slot1_set,
- Field_ftsf88ae_slot1_Slot_ae_slot1_set,
- Field_ftsf89ae_slot1_Slot_ae_slot1_set,
- Field_ftsf90ae_slot1_Slot_ae_slot1_set,
- Field_ftsf91ae_slot1_Slot_ae_slot1_set,
- Field_ftsf92ae_slot1_Slot_ae_slot1_set,
- Field_ftsf94ae_slot1_Slot_ae_slot1_set,
- Field_ftsf96ae_slot1_Slot_ae_slot1_set,
- Field_ftsf97ae_slot1_Slot_ae_slot1_set,
- Field_ftsf98ae_slot1_Slot_ae_slot1_set,
- Field_ftsf99ae_slot1_Slot_ae_slot1_set,
- Field_ftsf100ae_slot1_Slot_ae_slot1_set,
- Field_ftsf101ae_slot1_Slot_ae_slot1_set,
- Field_ftsf103ae_slot1_Slot_ae_slot1_set,
- Field_ftsf104ae_slot1_Slot_ae_slot1_set,
- Field_ftsf105ae_slot1_Slot_ae_slot1_set,
- Field_ftsf106ae_slot1_Slot_ae_slot1_set,
- Field_ftsf107ae_slot1_Slot_ae_slot1_set,
- Field_ftsf108ae_slot1_Slot_ae_slot1_set,
- Field_ftsf109ae_slot1_Slot_ae_slot1_set,
- Field_ftsf110ae_slot1_Slot_ae_slot1_set,
- Field_ftsf111ae_slot1_Slot_ae_slot1_set,
- Field_ftsf112ae_slot1_Slot_ae_slot1_set,
- Field_ftsf113ae_slot1_Slot_ae_slot1_set,
- Field_ftsf114ae_slot1_Slot_ae_slot1_set,
- Field_ftsf115ae_slot1_Slot_ae_slot1_set,
- Field_ftsf116ae_slot1_Slot_ae_slot1_set,
- Field_ftsf118ae_slot1_Slot_ae_slot1_set,
- Field_ftsf119ae_slot1_Slot_ae_slot1_set,
- Field_ftsf120ae_slot1_Slot_ae_slot1_set,
- Field_ftsf122ae_slot1_Slot_ae_slot1_set,
- Field_ftsf124ae_slot1_Slot_ae_slot1_set,
- Field_ftsf125ae_slot1_Slot_ae_slot1_set,
- Field_ftsf126ae_slot1_Slot_ae_slot1_set,
- Field_ftsf127ae_slot1_Slot_ae_slot1_set,
- Field_ftsf128ae_slot1_Slot_ae_slot1_set,
- Field_ftsf129ae_slot1_Slot_ae_slot1_set,
- Field_ftsf130ae_slot1_Slot_ae_slot1_set,
- Field_ftsf131ae_slot1_Slot_ae_slot1_set,
- Field_ftsf132ae_slot1_Slot_ae_slot1_set,
- Field_ftsf133ae_slot1_Slot_ae_slot1_set,
- Field_ftsf134ae_slot1_Slot_ae_slot1_set,
- Field_ftsf135ae_slot1_Slot_ae_slot1_set,
- Field_ftsf136ae_slot1_Slot_ae_slot1_set,
- Field_ftsf137ae_slot1_Slot_ae_slot1_set,
- Field_ftsf138ae_slot1_Slot_ae_slot1_set,
- Field_ftsf139ae_slot1_Slot_ae_slot1_set,
- Field_ftsf140ae_slot1_Slot_ae_slot1_set,
- Field_ftsf141ae_slot1_Slot_ae_slot1_set,
- Field_ftsf142ae_slot1_Slot_ae_slot1_set,
- Field_ftsf143ae_slot1_Slot_ae_slot1_set,
- Field_ftsf144ae_slot1_Slot_ae_slot1_set,
- Field_ftsf145ae_slot1_Slot_ae_slot1_set,
- Field_ftsf146ae_slot1_Slot_ae_slot1_set,
- Field_ftsf147ae_slot1_Slot_ae_slot1_set,
- Field_ftsf148ae_slot1_Slot_ae_slot1_set,
- Field_ftsf149ae_slot1_Slot_ae_slot1_set,
- Field_ftsf150ae_slot1_Slot_ae_slot1_set,
- Field_ftsf151ae_slot1_Slot_ae_slot1_set,
- Field_ftsf152ae_slot1_Slot_ae_slot1_set,
- Field_ftsf153ae_slot1_Slot_ae_slot1_set,
- Field_ftsf154ae_slot1_Slot_ae_slot1_set,
- Field_ftsf155ae_slot1_Slot_ae_slot1_set,
- Field_ftsf156ae_slot1_Slot_ae_slot1_set,
- Field_ftsf157ae_slot1_Slot_ae_slot1_set,
- Field_ftsf158ae_slot1_Slot_ae_slot1_set,
- Field_ftsf159ae_slot1_Slot_ae_slot1_set,
- Field_ftsf160ae_slot1_Slot_ae_slot1_set,
- Field_ftsf161ae_slot1_Slot_ae_slot1_set,
- Field_ftsf162ae_slot1_Slot_ae_slot1_set,
- Field_ftsf163ae_slot1_Slot_ae_slot1_set,
- Field_ftsf164ae_slot1_Slot_ae_slot1_set,
- Field_ftsf165ae_slot1_Slot_ae_slot1_set,
- Field_ftsf166ae_slot1_Slot_ae_slot1_set,
- Field_ftsf167ae_slot1_Slot_ae_slot1_set,
- Field_ftsf168ae_slot1_Slot_ae_slot1_set,
- Field_ftsf169ae_slot1_Slot_ae_slot1_set,
- Field_ftsf170ae_slot1_Slot_ae_slot1_set,
- Field_ftsf171ae_slot1_Slot_ae_slot1_set,
- Field_ftsf172ae_slot1_Slot_ae_slot1_set,
- Field_ftsf173ae_slot1_Slot_ae_slot1_set,
- Field_ftsf174ae_slot1_Slot_ae_slot1_set,
- Field_ftsf175ae_slot1_Slot_ae_slot1_set,
- Field_ftsf176ae_slot1_Slot_ae_slot1_set,
- Field_ftsf177ae_slot1_Slot_ae_slot1_set,
- Field_ftsf178ae_slot1_Slot_ae_slot1_set,
- Field_ftsf179ae_slot1_Slot_ae_slot1_set,
- Field_ftsf180ae_slot1_Slot_ae_slot1_set,
- Field_ftsf181ae_slot1_Slot_ae_slot1_set,
- Field_ftsf182ae_slot1_Slot_ae_slot1_set,
- Field_ftsf183ae_slot1_Slot_ae_slot1_set,
- Field_ftsf184ae_slot1_Slot_ae_slot1_set,
- Field_ftsf185ae_slot1_Slot_ae_slot1_set,
- Field_ftsf186ae_slot1_Slot_ae_slot1_set,
- Field_ftsf187ae_slot1_Slot_ae_slot1_set,
- Field_ftsf188ae_slot1_Slot_ae_slot1_set,
- Field_ftsf189ae_slot1_Slot_ae_slot1_set,
- Field_ftsf190ae_slot1_Slot_ae_slot1_set,
- Field_ftsf191ae_slot1_Slot_ae_slot1_set,
- Field_ftsf192ae_slot1_Slot_ae_slot1_set,
- Field_ftsf193ae_slot1_Slot_ae_slot1_set,
- Field_ftsf194ae_slot1_Slot_ae_slot1_set,
- Field_ftsf195ae_slot1_Slot_ae_slot1_set,
- Field_ftsf196ae_slot1_Slot_ae_slot1_set,
- Field_ftsf197ae_slot1_Slot_ae_slot1_set,
- Field_ftsf198ae_slot1_Slot_ae_slot1_set,
- Field_ftsf199ae_slot1_Slot_ae_slot1_set,
- Field_ftsf200ae_slot1_Slot_ae_slot1_set,
- Field_ftsf201ae_slot1_Slot_ae_slot1_set,
- Field_ftsf202ae_slot1_Slot_ae_slot1_set,
- Field_ftsf203ae_slot1_Slot_ae_slot1_set,
- Field_ftsf204ae_slot1_Slot_ae_slot1_set,
- Field_ftsf205ae_slot1_Slot_ae_slot1_set,
- Field_ftsf206ae_slot1_Slot_ae_slot1_set,
- Field_ftsf207ae_slot1_Slot_ae_slot1_set,
- Field_ftsf208_Slot_ae_slot1_set,
- Field_ftsf209ae_slot1_Slot_ae_slot1_set,
- Field_ftsf210ae_slot1_Slot_ae_slot1_set,
- Field_ftsf211ae_slot1_Slot_ae_slot1_set,
- Field_ftsf330ae_slot1_Slot_ae_slot1_set,
- Field_ftsf332ae_slot1_Slot_ae_slot1_set,
- Field_ftsf334ae_slot1_Slot_ae_slot1_set,
- Field_ftsf336ae_slot1_Slot_ae_slot1_set,
- Field_ftsf337ae_slot1_Slot_ae_slot1_set,
- Field_ftsf338_Slot_ae_slot1_set,
- Field_ftsf339ae_slot1_Slot_ae_slot1_set,
- Field_ftsf340_Slot_ae_slot1_set,
- Field_ftsf341ae_slot1_Slot_ae_slot1_set,
- Field_ftsf342ae_slot1_Slot_ae_slot1_set,
- Field_ftsf343ae_slot1_Slot_ae_slot1_set,
- Field_ftsf344ae_slot1_Slot_ae_slot1_set,
- Field_ftsf346ae_slot1_Slot_ae_slot1_set,
- Field_ftsf347_Slot_ae_slot1_set,
- Field_ftsf348ae_slot1_Slot_ae_slot1_set,
- Field_ftsf349ae_slot1_Slot_ae_slot1_set,
- Field_ftsf350ae_slot1_Slot_ae_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_get_field_fn
-Slot_ae_slot0_get_field_fns[] = {
- Field_t_Slot_ae_slot0_get,
- 0,
- Field_bbi_Slot_ae_slot0_get,
- Field_imm12_Slot_ae_slot0_get,
- Field_imm8_Slot_ae_slot0_get,
- Field_s_Slot_ae_slot0_get,
- Field_imm12b_Slot_ae_slot0_get,
- Field_imm16_Slot_ae_slot0_get,
- 0,
- 0,
- Field_offset_Slot_ae_slot0_get,
- 0,
- 0,
- Field_op2_Slot_ae_slot0_get,
- Field_r_Slot_ae_slot0_get,
- 0,
- 0,
- Field_sae_Slot_ae_slot0_get,
- Field_sal_Slot_ae_slot0_get,
- Field_sargt_Slot_ae_slot0_get,
- 0,
- Field_sas_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_s4_Slot_ae_slot0_get,
- 0,
- 0,
- Field_s8_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot0_get,
- Field_ae_samt_s_t_Slot_ae_slot0_get,
- Field_ae_r20_Slot_ae_slot0_get,
- Field_ae_r10_Slot_ae_slot0_get,
- Field_ae_s20_Slot_ae_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s4_Slot_ae_slot0_get,
- Field_ftsf212ae_slot0_Slot_ae_slot0_get,
- Field_ftsf213ae_slot0_Slot_ae_slot0_get,
- Field_ftsf214ae_slot0_Slot_ae_slot0_get,
- Field_ftsf215ae_slot0_Slot_ae_slot0_get,
- Field_ftsf216ae_slot0_Slot_ae_slot0_get,
- Field_ftsf217_Slot_ae_slot0_get,
- Field_ftsf218ae_slot0_Slot_ae_slot0_get,
- Field_ftsf219ae_slot0_Slot_ae_slot0_get,
- Field_ftsf220ae_slot0_Slot_ae_slot0_get,
- Field_ftsf221ae_slot0_Slot_ae_slot0_get,
- Field_ftsf222ae_slot0_Slot_ae_slot0_get,
- Field_ftsf223ae_slot0_Slot_ae_slot0_get,
- Field_ftsf224ae_slot0_Slot_ae_slot0_get,
- Field_ftsf225ae_slot0_Slot_ae_slot0_get,
- Field_ftsf226ae_slot0_Slot_ae_slot0_get,
- Field_ftsf227ae_slot0_Slot_ae_slot0_get,
- Field_ftsf228ae_slot0_Slot_ae_slot0_get,
- Field_ftsf229ae_slot0_Slot_ae_slot0_get,
- Field_ftsf230ae_slot0_Slot_ae_slot0_get,
- Field_ftsf231ae_slot0_Slot_ae_slot0_get,
- Field_ftsf232ae_slot0_Slot_ae_slot0_get,
- Field_ftsf233ae_slot0_Slot_ae_slot0_get,
- Field_ftsf234ae_slot0_Slot_ae_slot0_get,
- Field_ftsf235ae_slot0_Slot_ae_slot0_get,
- Field_ftsf236ae_slot0_Slot_ae_slot0_get,
- Field_ftsf237ae_slot0_Slot_ae_slot0_get,
- Field_ftsf238ae_slot0_Slot_ae_slot0_get,
- Field_ftsf239ae_slot0_Slot_ae_slot0_get,
- Field_ftsf240ae_slot0_Slot_ae_slot0_get,
- Field_ftsf241ae_slot0_Slot_ae_slot0_get,
- Field_ftsf242ae_slot0_Slot_ae_slot0_get,
- Field_ftsf243ae_slot0_Slot_ae_slot0_get,
- Field_ftsf244ae_slot0_Slot_ae_slot0_get,
- Field_ftsf245ae_slot0_Slot_ae_slot0_get,
- Field_ftsf246ae_slot0_Slot_ae_slot0_get,
- Field_ftsf247ae_slot0_Slot_ae_slot0_get,
- Field_ftsf248ae_slot0_Slot_ae_slot0_get,
- Field_ftsf249ae_slot0_Slot_ae_slot0_get,
- Field_ftsf250ae_slot0_Slot_ae_slot0_get,
- Field_ftsf251ae_slot0_Slot_ae_slot0_get,
- Field_ftsf252ae_slot0_Slot_ae_slot0_get,
- Field_ftsf253ae_slot0_Slot_ae_slot0_get,
- Field_ftsf254ae_slot0_Slot_ae_slot0_get,
- Field_ftsf255ae_slot0_Slot_ae_slot0_get,
- Field_ftsf256ae_slot0_Slot_ae_slot0_get,
- Field_ftsf257ae_slot0_Slot_ae_slot0_get,
- Field_ftsf258ae_slot0_Slot_ae_slot0_get,
- Field_ftsf259ae_slot0_Slot_ae_slot0_get,
- Field_ftsf260ae_slot0_Slot_ae_slot0_get,
- Field_ftsf261ae_slot0_Slot_ae_slot0_get,
- Field_ftsf262ae_slot0_Slot_ae_slot0_get,
- Field_ftsf263ae_slot0_Slot_ae_slot0_get,
- Field_ftsf264ae_slot0_Slot_ae_slot0_get,
- Field_ftsf265ae_slot0_Slot_ae_slot0_get,
- Field_ftsf266ae_slot0_Slot_ae_slot0_get,
- Field_ftsf267ae_slot0_Slot_ae_slot0_get,
- Field_ftsf268ae_slot0_Slot_ae_slot0_get,
- Field_ftsf269ae_slot0_Slot_ae_slot0_get,
- Field_ftsf270ae_slot0_Slot_ae_slot0_get,
- Field_ftsf271ae_slot0_Slot_ae_slot0_get,
- Field_ftsf272ae_slot0_Slot_ae_slot0_get,
- Field_ftsf273ae_slot0_Slot_ae_slot0_get,
- Field_ftsf274ae_slot0_Slot_ae_slot0_get,
- Field_ftsf275ae_slot0_Slot_ae_slot0_get,
- Field_ftsf276ae_slot0_Slot_ae_slot0_get,
- Field_ftsf277ae_slot0_Slot_ae_slot0_get,
- Field_ftsf278ae_slot0_Slot_ae_slot0_get,
- Field_ftsf279ae_slot0_Slot_ae_slot0_get,
- Field_ftsf281ae_slot0_Slot_ae_slot0_get,
- Field_ftsf282ae_slot0_Slot_ae_slot0_get,
- Field_ftsf283ae_slot0_Slot_ae_slot0_get,
- Field_ftsf284ae_slot0_Slot_ae_slot0_get,
- Field_ftsf286ae_slot0_Slot_ae_slot0_get,
- Field_ftsf288ae_slot0_Slot_ae_slot0_get,
- Field_ftsf290ae_slot0_Slot_ae_slot0_get,
- Field_ftsf292ae_slot0_Slot_ae_slot0_get,
- Field_ftsf293_Slot_ae_slot0_get,
- Field_ftsf294ae_slot0_Slot_ae_slot0_get,
- Field_ftsf295ae_slot0_Slot_ae_slot0_get,
- Field_ftsf296ae_slot0_Slot_ae_slot0_get,
- Field_ftsf297ae_slot0_Slot_ae_slot0_get,
- Field_ftsf298ae_slot0_Slot_ae_slot0_get,
- Field_ftsf299ae_slot0_Slot_ae_slot0_get,
- Field_ftsf300ae_slot0_Slot_ae_slot0_get,
- Field_ftsf301ae_slot0_Slot_ae_slot0_get,
- Field_ftsf302ae_slot0_Slot_ae_slot0_get,
- Field_ftsf303ae_slot0_Slot_ae_slot0_get,
- Field_ftsf304ae_slot0_Slot_ae_slot0_get,
- Field_ftsf306ae_slot0_Slot_ae_slot0_get,
- Field_ftsf308ae_slot0_Slot_ae_slot0_get,
- Field_ftsf309ae_slot0_Slot_ae_slot0_get,
- Field_ftsf310ae_slot0_Slot_ae_slot0_get,
- Field_ftsf311ae_slot0_Slot_ae_slot0_get,
- Field_ftsf312ae_slot0_Slot_ae_slot0_get,
- Field_ftsf313ae_slot0_Slot_ae_slot0_get,
- Field_ftsf314ae_slot0_Slot_ae_slot0_get,
- Field_ftsf315ae_slot0_Slot_ae_slot0_get,
- Field_ftsf316ae_slot0_Slot_ae_slot0_get,
- Field_ftsf317ae_slot0_Slot_ae_slot0_get,
- Field_ftsf318ae_slot0_Slot_ae_slot0_get,
- Field_ftsf319_Slot_ae_slot0_get,
- Field_ftsf320ae_slot0_Slot_ae_slot0_get,
- Field_ftsf321_Slot_ae_slot0_get,
- Field_ftsf322ae_slot0_Slot_ae_slot0_get,
- Field_ftsf323ae_slot0_Slot_ae_slot0_get,
- Field_ftsf324ae_slot0_Slot_ae_slot0_get,
- Field_ftsf325ae_slot0_Slot_ae_slot0_get,
- Field_ftsf326ae_slot0_Slot_ae_slot0_get,
- Field_ftsf328ae_slot0_Slot_ae_slot0_get,
- Field_ftsf329ae_slot0_Slot_ae_slot0_get,
- Field_ftsf352ae_slot0_Slot_ae_slot0_get,
- Field_ftsf353_Slot_ae_slot0_get,
- Field_ftsf354ae_slot0_Slot_ae_slot0_get,
- Field_ftsf356ae_slot0_Slot_ae_slot0_get,
- Field_ftsf357_Slot_ae_slot0_get,
- Field_ftsf358ae_slot0_Slot_ae_slot0_get,
- Field_ftsf359ae_slot0_Slot_ae_slot0_get,
- Field_ftsf360ae_slot0_Slot_ae_slot0_get,
- Field_ftsf361ae_slot0_Slot_ae_slot0_get,
- Field_ftsf362ae_slot0_Slot_ae_slot0_get,
- Field_ftsf364ae_slot0_Slot_ae_slot0_get,
- Field_ftsf365ae_slot0_Slot_ae_slot0_get,
- Field_ftsf366ae_slot0_Slot_ae_slot0_get,
- Field_ftsf368ae_slot0_Slot_ae_slot0_get,
- Field_ftsf369ae_slot0_Slot_ae_slot0_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
-};
-
-static xtensa_set_field_fn
-Slot_ae_slot0_set_field_fns[] = {
- Field_t_Slot_ae_slot0_set,
- 0,
- Field_bbi_Slot_ae_slot0_set,
- Field_imm12_Slot_ae_slot0_set,
- Field_imm8_Slot_ae_slot0_set,
- Field_s_Slot_ae_slot0_set,
- Field_imm12b_Slot_ae_slot0_set,
- Field_imm16_Slot_ae_slot0_set,
- 0,
- 0,
- Field_offset_Slot_ae_slot0_set,
- 0,
- 0,
- Field_op2_Slot_ae_slot0_set,
- Field_r_Slot_ae_slot0_set,
- 0,
- 0,
- Field_sae_Slot_ae_slot0_set,
- Field_sal_Slot_ae_slot0_set,
- Field_sargt_Slot_ae_slot0_set,
- 0,
- Field_sas_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_s4_Slot_ae_slot0_set,
- 0,
- 0,
- Field_s8_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_ae_r32_Slot_ae_slot0_set,
- Field_ae_samt_s_t_Slot_ae_slot0_set,
- Field_ae_r20_Slot_ae_slot0_set,
- Field_ae_r10_Slot_ae_slot0_set,
- Field_ae_s20_Slot_ae_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s4_Slot_ae_slot0_set,
- Field_ftsf212ae_slot0_Slot_ae_slot0_set,
- Field_ftsf213ae_slot0_Slot_ae_slot0_set,
- Field_ftsf214ae_slot0_Slot_ae_slot0_set,
- Field_ftsf215ae_slot0_Slot_ae_slot0_set,
- Field_ftsf216ae_slot0_Slot_ae_slot0_set,
- Field_ftsf217_Slot_ae_slot0_set,
- Field_ftsf218ae_slot0_Slot_ae_slot0_set,
- Field_ftsf219ae_slot0_Slot_ae_slot0_set,
- Field_ftsf220ae_slot0_Slot_ae_slot0_set,
- Field_ftsf221ae_slot0_Slot_ae_slot0_set,
- Field_ftsf222ae_slot0_Slot_ae_slot0_set,
- Field_ftsf223ae_slot0_Slot_ae_slot0_set,
- Field_ftsf224ae_slot0_Slot_ae_slot0_set,
- Field_ftsf225ae_slot0_Slot_ae_slot0_set,
- Field_ftsf226ae_slot0_Slot_ae_slot0_set,
- Field_ftsf227ae_slot0_Slot_ae_slot0_set,
- Field_ftsf228ae_slot0_Slot_ae_slot0_set,
- Field_ftsf229ae_slot0_Slot_ae_slot0_set,
- Field_ftsf230ae_slot0_Slot_ae_slot0_set,
- Field_ftsf231ae_slot0_Slot_ae_slot0_set,
- Field_ftsf232ae_slot0_Slot_ae_slot0_set,
- Field_ftsf233ae_slot0_Slot_ae_slot0_set,
- Field_ftsf234ae_slot0_Slot_ae_slot0_set,
- Field_ftsf235ae_slot0_Slot_ae_slot0_set,
- Field_ftsf236ae_slot0_Slot_ae_slot0_set,
- Field_ftsf237ae_slot0_Slot_ae_slot0_set,
- Field_ftsf238ae_slot0_Slot_ae_slot0_set,
- Field_ftsf239ae_slot0_Slot_ae_slot0_set,
- Field_ftsf240ae_slot0_Slot_ae_slot0_set,
- Field_ftsf241ae_slot0_Slot_ae_slot0_set,
- Field_ftsf242ae_slot0_Slot_ae_slot0_set,
- Field_ftsf243ae_slot0_Slot_ae_slot0_set,
- Field_ftsf244ae_slot0_Slot_ae_slot0_set,
- Field_ftsf245ae_slot0_Slot_ae_slot0_set,
- Field_ftsf246ae_slot0_Slot_ae_slot0_set,
- Field_ftsf247ae_slot0_Slot_ae_slot0_set,
- Field_ftsf248ae_slot0_Slot_ae_slot0_set,
- Field_ftsf249ae_slot0_Slot_ae_slot0_set,
- Field_ftsf250ae_slot0_Slot_ae_slot0_set,
- Field_ftsf251ae_slot0_Slot_ae_slot0_set,
- Field_ftsf252ae_slot0_Slot_ae_slot0_set,
- Field_ftsf253ae_slot0_Slot_ae_slot0_set,
- Field_ftsf254ae_slot0_Slot_ae_slot0_set,
- Field_ftsf255ae_slot0_Slot_ae_slot0_set,
- Field_ftsf256ae_slot0_Slot_ae_slot0_set,
- Field_ftsf257ae_slot0_Slot_ae_slot0_set,
- Field_ftsf258ae_slot0_Slot_ae_slot0_set,
- Field_ftsf259ae_slot0_Slot_ae_slot0_set,
- Field_ftsf260ae_slot0_Slot_ae_slot0_set,
- Field_ftsf261ae_slot0_Slot_ae_slot0_set,
- Field_ftsf262ae_slot0_Slot_ae_slot0_set,
- Field_ftsf263ae_slot0_Slot_ae_slot0_set,
- Field_ftsf264ae_slot0_Slot_ae_slot0_set,
- Field_ftsf265ae_slot0_Slot_ae_slot0_set,
- Field_ftsf266ae_slot0_Slot_ae_slot0_set,
- Field_ftsf267ae_slot0_Slot_ae_slot0_set,
- Field_ftsf268ae_slot0_Slot_ae_slot0_set,
- Field_ftsf269ae_slot0_Slot_ae_slot0_set,
- Field_ftsf270ae_slot0_Slot_ae_slot0_set,
- Field_ftsf271ae_slot0_Slot_ae_slot0_set,
- Field_ftsf272ae_slot0_Slot_ae_slot0_set,
- Field_ftsf273ae_slot0_Slot_ae_slot0_set,
- Field_ftsf274ae_slot0_Slot_ae_slot0_set,
- Field_ftsf275ae_slot0_Slot_ae_slot0_set,
- Field_ftsf276ae_slot0_Slot_ae_slot0_set,
- Field_ftsf277ae_slot0_Slot_ae_slot0_set,
- Field_ftsf278ae_slot0_Slot_ae_slot0_set,
- Field_ftsf279ae_slot0_Slot_ae_slot0_set,
- Field_ftsf281ae_slot0_Slot_ae_slot0_set,
- Field_ftsf282ae_slot0_Slot_ae_slot0_set,
- Field_ftsf283ae_slot0_Slot_ae_slot0_set,
- Field_ftsf284ae_slot0_Slot_ae_slot0_set,
- Field_ftsf286ae_slot0_Slot_ae_slot0_set,
- Field_ftsf288ae_slot0_Slot_ae_slot0_set,
- Field_ftsf290ae_slot0_Slot_ae_slot0_set,
- Field_ftsf292ae_slot0_Slot_ae_slot0_set,
- Field_ftsf293_Slot_ae_slot0_set,
- Field_ftsf294ae_slot0_Slot_ae_slot0_set,
- Field_ftsf295ae_slot0_Slot_ae_slot0_set,
- Field_ftsf296ae_slot0_Slot_ae_slot0_set,
- Field_ftsf297ae_slot0_Slot_ae_slot0_set,
- Field_ftsf298ae_slot0_Slot_ae_slot0_set,
- Field_ftsf299ae_slot0_Slot_ae_slot0_set,
- Field_ftsf300ae_slot0_Slot_ae_slot0_set,
- Field_ftsf301ae_slot0_Slot_ae_slot0_set,
- Field_ftsf302ae_slot0_Slot_ae_slot0_set,
- Field_ftsf303ae_slot0_Slot_ae_slot0_set,
- Field_ftsf304ae_slot0_Slot_ae_slot0_set,
- Field_ftsf306ae_slot0_Slot_ae_slot0_set,
- Field_ftsf308ae_slot0_Slot_ae_slot0_set,
- Field_ftsf309ae_slot0_Slot_ae_slot0_set,
- Field_ftsf310ae_slot0_Slot_ae_slot0_set,
- Field_ftsf311ae_slot0_Slot_ae_slot0_set,
- Field_ftsf312ae_slot0_Slot_ae_slot0_set,
- Field_ftsf313ae_slot0_Slot_ae_slot0_set,
- Field_ftsf314ae_slot0_Slot_ae_slot0_set,
- Field_ftsf315ae_slot0_Slot_ae_slot0_set,
- Field_ftsf316ae_slot0_Slot_ae_slot0_set,
- Field_ftsf317ae_slot0_Slot_ae_slot0_set,
- Field_ftsf318ae_slot0_Slot_ae_slot0_set,
- Field_ftsf319_Slot_ae_slot0_set,
- Field_ftsf320ae_slot0_Slot_ae_slot0_set,
- Field_ftsf321_Slot_ae_slot0_set,
- Field_ftsf322ae_slot0_Slot_ae_slot0_set,
- Field_ftsf323ae_slot0_Slot_ae_slot0_set,
- Field_ftsf324ae_slot0_Slot_ae_slot0_set,
- Field_ftsf325ae_slot0_Slot_ae_slot0_set,
- Field_ftsf326ae_slot0_Slot_ae_slot0_set,
- Field_ftsf328ae_slot0_Slot_ae_slot0_set,
- Field_ftsf329ae_slot0_Slot_ae_slot0_set,
- Field_ftsf352ae_slot0_Slot_ae_slot0_set,
- Field_ftsf353_Slot_ae_slot0_set,
- Field_ftsf354ae_slot0_Slot_ae_slot0_set,
- Field_ftsf356ae_slot0_Slot_ae_slot0_set,
- Field_ftsf357_Slot_ae_slot0_set,
- Field_ftsf358ae_slot0_Slot_ae_slot0_set,
- Field_ftsf359ae_slot0_Slot_ae_slot0_set,
- Field_ftsf360ae_slot0_Slot_ae_slot0_set,
- Field_ftsf361ae_slot0_Slot_ae_slot0_set,
- Field_ftsf362ae_slot0_Slot_ae_slot0_set,
- Field_ftsf364ae_slot0_Slot_ae_slot0_set,
- Field_ftsf365ae_slot0_Slot_ae_slot0_set,
- Field_ftsf366ae_slot0_Slot_ae_slot0_set,
- Field_ftsf368ae_slot0_Slot_ae_slot0_set,
- Field_ftsf369ae_slot0_Slot_ae_slot0_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
-};
-
-static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" },
- { "ae_slot1", "ae_format", 1,
- Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set,
- Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns,
- Slot_ae_slot1_decode, "nop" },
- { "ae_slot0", "ae_format", 0,
- Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set,
- Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns,
- Slot_ae_slot0_decode, "nop" }
-};
-
-\f
-/* Instruction formats. */
-
-static void
-Format_x24_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0;
- insn[1] = 0;
-}
-
-static void
-Format_x16a_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0x8;
- insn[1] = 0;
-}
-
-static void
-Format_x16b_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xc;
- insn[1] = 0;
-}
-
-static void
-Format_ae_format_encode (xtensa_insnbuf insn)
-{
- insn[0] = 0xf;
- insn[1] = 0;
-}
-
-static int Format_x24_slots[] = { 0 };
-
-static int Format_x16a_slots[] = { 1 };
-
-static int Format_x16b_slots[] = { 2 };
-
-static int Format_ae_format_slots[] = { 4, 3 };
-
-static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
- { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots }
-};
-
-
-static int
-format_decoder (const xtensa_insnbuf insn)
-{
- if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
- return 1; /* x16a */
- if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
- return 2; /* x16b */
- if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0)
- return 3; /* ae_format */
- return -1;
-}
-
-static int length_table[256] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- 8
-};
-
-static int
-length_decoder (const unsigned char *insn)
-{
- int l = insn[0];
- return length_table[l];
-}
-
-\f
-/* Top-level ISA structure. */
-
-xtensa_isa_internal xtensa_modules = {
- 0 /* little-endian */,
- 8 /* insn_size */, 0,
- 4, formats, format_decoder, length_decoder,
- 5, slots,
- 389 /* num_fields */,
- 454, operands,
- 588, iclasses,
- 656, opcodes, 0,
- 8, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 2, interfaces, 0,
- 4, funcUnits, 0
-};
xtensa/config/core-isa.h \
xtensa/config/core-matmap.h
tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
- sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c
+ sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c.inc
#
# Fix up known issues in the xtensa-modules.c
#
-e '/^#include "ansidecl.h"/d' \
-e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^ return 0;$/ return XTENSA_UNDEFINED;/' \
-e 's/#include <xtensa-isa.h>/#include "xtensa-isa.h"/' \
- > "$TARGET"/xtensa-modules.inc.c
+ > "$TARGET"/xtensa-modules.c.inc
cat <<EOF > "${TARGET}.c"
#include "qemu/osdep.h"
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_$NAME
-#include "core-$NAME/xtensa-modules.inc.c"
+#include "core-$NAME/xtensa-modules.c.inc"
static XtensaConfig $NAME __attribute__((unused)) = {
.name = "$NAME",
.gdb_regmap = {
.reg = {
-#include "core-$NAME/gdb-config.inc.c"
+#include "core-$NAME/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
4) Backend
-tcg-target.h contains the target specific definitions. tcg-target.inc.c
+tcg-target.h contains the target specific definitions. tcg-target.c.inc
contains the target specific code; it is #included by tcg/tcg.c, rather
than being a standalone C file.
--- /dev/null
+/*
+ * Initial TCG Implementation for aarch64
+ *
+ * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
+ * Written by Claudio Fontana
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ */
+
+#include "../tcg-pool.c.inc"
+#include "qemu/bitops.h"
+
+/* We're going to re-use TCGType in setting of the SF bit, which controls
+ the size of the operation performed. If we know the values match, it
+ makes things much cleaner. */
+QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp",
+
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31",
+};
+#endif /* CONFIG_DEBUG_TCG */
+
+static const int tcg_target_reg_alloc_order[] = {
+ TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
+ TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
+ TCG_REG_X28, /* we will reserve this for guest_base if configured */
+
+ TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
+ TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
+ TCG_REG_X16, TCG_REG_X17,
+
+ TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
+ TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
+
+ /* X18 reserved by system */
+ /* X19 reserved for AREG0 */
+ /* X29 reserved as fp */
+ /* X30 reserved as temporary */
+
+ TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ /* V8 - V15 are call-saved, and skipped. */
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+};
+
+static const int tcg_target_call_iarg_regs[8] = {
+ TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
+ TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7
+};
+static const int tcg_target_call_oarg_regs[1] = {
+ TCG_REG_X0
+};
+
+#define TCG_REG_TMP TCG_REG_X30
+#define TCG_VEC_TMP TCG_REG_V31
+
+#ifndef CONFIG_SOFTMMU
+/* Note that XZR cannot be encoded in the address base register slot,
+ as that actaully encodes SP. So if we need to zero-extend the guest
+ address, via the address index register slot, we need to load even
+ a zero guest base into a register. */
+#define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32)
+#define TCG_REG_GUEST_BASE TCG_REG_X28
+#endif
+
+static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = target - code_ptr;
+ if (offset == sextract64(offset, 0, 26)) {
+ /* read instruction, mask away previous PC_REL26 parameter contents,
+ set the proper offset, then write back the instruction. */
+ *code_ptr = deposit32(*code_ptr, 0, 26, offset);
+ return true;
+ }
+ return false;
+}
+
+static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = target - code_ptr;
+ if (offset == sextract64(offset, 0, 19)) {
+ *code_ptr = deposit32(*code_ptr, 5, 19, offset);
+ return true;
+ }
+ return false;
+}
+
+static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ tcg_debug_assert(addend == 0);
+ switch (type) {
+ case R_AARCH64_JUMP26:
+ case R_AARCH64_CALL26:
+ return reloc_pc26(code_ptr, (tcg_insn_unit *)value);
+ case R_AARCH64_CONDBR19:
+ return reloc_pc19(code_ptr, (tcg_insn_unit *)value);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+#define TCG_CT_CONST_AIMM 0x100
+#define TCG_CT_CONST_LIMM 0x200
+#define TCG_CT_CONST_ZERO 0x400
+#define TCG_CT_CONST_MONE 0x800
+#define TCG_CT_CONST_ORRI 0x1000
+#define TCG_CT_CONST_ANDI 0x2000
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'r': /* general registers */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= 0xffffffffu;
+ break;
+ case 'w': /* advsimd registers */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= 0xffffffff00000000ull;
+ break;
+ case 'l': /* qemu_ld / qemu_st address, data_reg */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffffu;
+#ifdef CONFIG_SOFTMMU
+ /* x0 and x1 will be overwritten when reading the tlb entry,
+ and x2, and x3 for helper args, better to avoid using them. */
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
+#endif
+ break;
+ case 'A': /* Valid for arithmetic immediate (positive or negative). */
+ ct->ct |= TCG_CT_CONST_AIMM;
+ break;
+ case 'L': /* Valid for logical immediate. */
+ ct->ct |= TCG_CT_CONST_LIMM;
+ break;
+ case 'M': /* minus one */
+ ct->ct |= TCG_CT_CONST_MONE;
+ break;
+ case 'O': /* vector orr/bic immediate */
+ ct->ct |= TCG_CT_CONST_ORRI;
+ break;
+ case 'N': /* vector orr/bic immediate, inverted */
+ ct->ct |= TCG_CT_CONST_ANDI;
+ break;
+ case 'Z': /* zero */
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* Match a constant valid for addition (12-bit, optionally shifted). */
+static inline bool is_aimm(uint64_t val)
+{
+ return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
+}
+
+/* Match a constant valid for logical operations. */
+static inline bool is_limm(uint64_t val)
+{
+ /* Taking a simplified view of the logical immediates for now, ignoring
+ the replication that can happen across the field. Match bit patterns
+ of the forms
+ 0....01....1
+ 0..01..10..0
+ and their inverses. */
+
+ /* Make things easier below, by testing the form with msb clear. */
+ if ((int64_t)val < 0) {
+ val = ~val;
+ }
+ if (val == 0) {
+ return false;
+ }
+ val += val & -val;
+ return (val & (val - 1)) == 0;
+}
+
+/* Return true if v16 is a valid 16-bit shifted immediate. */
+static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
+{
+ if (v16 == (v16 & 0xff)) {
+ *cmode = 0x8;
+ *imm8 = v16 & 0xff;
+ return true;
+ } else if (v16 == (v16 & 0xff00)) {
+ *cmode = 0xa;
+ *imm8 = v16 >> 8;
+ return true;
+ }
+ return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifted immediate. */
+static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
+{
+ if (v32 == (v32 & 0xff)) {
+ *cmode = 0x0;
+ *imm8 = v32 & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff00)) {
+ *cmode = 0x2;
+ *imm8 = (v32 >> 8) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff0000)) {
+ *cmode = 0x4;
+ *imm8 = (v32 >> 16) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff000000)) {
+ *cmode = 0x6;
+ *imm8 = v32 >> 24;
+ return true;
+ }
+ return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifting ones immediate. */
+static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
+{
+ if ((v32 & 0xffff00ff) == 0xff) {
+ *cmode = 0xc;
+ *imm8 = (v32 >> 8) & 0xff;
+ return true;
+ } else if ((v32 & 0xff00ffff) == 0xffff) {
+ *cmode = 0xd;
+ *imm8 = (v32 >> 16) & 0xff;
+ return true;
+ }
+ return false;
+}
+
+/* Return true if v32 is a valid float32 immediate. */
+static bool is_fimm32(uint32_t v32, int *cmode, int *imm8)
+{
+ if (extract32(v32, 0, 19) == 0
+ && (extract32(v32, 25, 6) == 0x20
+ || extract32(v32, 25, 6) == 0x1f)) {
+ *cmode = 0xf;
+ *imm8 = (extract32(v32, 31, 1) << 7)
+ | (extract32(v32, 25, 1) << 6)
+ | extract32(v32, 19, 6);
+ return true;
+ }
+ return false;
+}
+
+/* Return true if v64 is a valid float64 immediate. */
+static bool is_fimm64(uint64_t v64, int *cmode, int *imm8)
+{
+ if (extract64(v64, 0, 48) == 0
+ && (extract64(v64, 54, 9) == 0x100
+ || extract64(v64, 54, 9) == 0x0ff)) {
+ *cmode = 0xf;
+ *imm8 = (extract64(v64, 63, 1) << 7)
+ | (extract64(v64, 54, 1) << 6)
+ | extract64(v64, 48, 6);
+ return true;
+ }
+ return false;
+}
+
+/*
+ * Return non-zero if v32 can be formed by MOVI+ORR.
+ * Place the parameters for MOVI in (cmode, imm8).
+ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
+ */
+static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
+{
+ int i;
+
+ for (i = 6; i > 0; i -= 2) {
+ /* Mask out one byte we can add with ORR. */
+ uint32_t tmp = v32 & ~(0xffu << (i * 4));
+ if (is_shimm32(tmp, cmode, imm8) ||
+ is_soimm32(tmp, cmode, imm8)) {
+ break;
+ }
+ }
+ return i;
+}
+
+/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+{
+ if (v32 == deposit32(v32, 16, 16, v32)) {
+ return is_shimm16(v32, cmode, imm8);
+ } else {
+ return is_shimm32(v32, cmode, imm8);
+ }
+}
+
+static int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct = arg_ct->ct;
+
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+ if (type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+ if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_MONE) && val == -1) {
+ return 1;
+ }
+
+ switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
+ case 0:
+ break;
+ case TCG_CT_CONST_ANDI:
+ val = ~val;
+ /* fallthru */
+ case TCG_CT_CONST_ORRI:
+ if (val == deposit64(val, 32, 32, val)) {
+ int cmode, imm8;
+ return is_shimm1632(val, &cmode, &imm8);
+ }
+ break;
+ default:
+ /* Both bits should not be set for the same insn. */
+ g_assert_not_reached();
+ }
+
+ return 0;
+}
+
+enum aarch64_cond_code {
+ COND_EQ = 0x0,
+ COND_NE = 0x1,
+ COND_CS = 0x2, /* Unsigned greater or equal */
+ COND_HS = COND_CS, /* ALIAS greater or equal */
+ COND_CC = 0x3, /* Unsigned less than */
+ COND_LO = COND_CC, /* ALIAS Lower */
+ COND_MI = 0x4, /* Negative */
+ COND_PL = 0x5, /* Zero or greater */
+ COND_VS = 0x6, /* Overflow */
+ COND_VC = 0x7, /* No overflow */
+ COND_HI = 0x8, /* Unsigned greater than */
+ COND_LS = 0x9, /* Unsigned less or equal */
+ COND_GE = 0xa,
+ COND_LT = 0xb,
+ COND_GT = 0xc,
+ COND_LE = 0xd,
+ COND_AL = 0xe,
+ COND_NV = 0xf, /* behaves like COND_AL here */
+};
+
+static const enum aarch64_cond_code tcg_cond_to_aarch64[] = {
+ [TCG_COND_EQ] = COND_EQ,
+ [TCG_COND_NE] = COND_NE,
+ [TCG_COND_LT] = COND_LT,
+ [TCG_COND_GE] = COND_GE,
+ [TCG_COND_LE] = COND_LE,
+ [TCG_COND_GT] = COND_GT,
+ /* unsigned */
+ [TCG_COND_LTU] = COND_LO,
+ [TCG_COND_GTU] = COND_HI,
+ [TCG_COND_GEU] = COND_HS,
+ [TCG_COND_LEU] = COND_LS,
+};
+
+typedef enum {
+ LDST_ST = 0, /* store */
+ LDST_LD = 1, /* load */
+ LDST_LD_S_X = 2, /* load and sign-extend into Xt */
+ LDST_LD_S_W = 3, /* load and sign-extend into Wt */
+} AArch64LdstType;
+
+/* We encode the format of the insn into the beginning of the name, so that
+ we can have the preprocessor help "typecheck" the insn vs the output
+ function. Arm didn't provide us with nice names for the formats, so we
+ use the section number of the architecture reference manual in which the
+ instruction group is described. */
+typedef enum {
+ /* Compare and branch (immediate). */
+ I3201_CBZ = 0x34000000,
+ I3201_CBNZ = 0x35000000,
+
+ /* Conditional branch (immediate). */
+ I3202_B_C = 0x54000000,
+
+ /* Unconditional branch (immediate). */
+ I3206_B = 0x14000000,
+ I3206_BL = 0x94000000,
+
+ /* Unconditional branch (register). */
+ I3207_BR = 0xd61f0000,
+ I3207_BLR = 0xd63f0000,
+ I3207_RET = 0xd65f0000,
+
+ /* AdvSIMD load/store single structure. */
+ I3303_LD1R = 0x0d40c000,
+
+ /* Load literal for loading the address at pc-relative offset */
+ I3305_LDR = 0x58000000,
+ I3305_LDR_v64 = 0x5c000000,
+ I3305_LDR_v128 = 0x9c000000,
+
+ /* Load/store register. Described here as 3.3.12, but the helper
+ that emits them can transform to 3.3.10 or 3.3.13. */
+ I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
+ I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,
+ I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,
+ I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,
+
+ I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,
+ I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,
+ I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,
+ I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,
+
+ I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,
+ I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,
+
+ I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,
+ I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
+ I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
+
+ I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
+ I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
+
+ I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
+ I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
+
+ I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
+ I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
+
+ I3312_TO_I3310 = 0x00200800,
+ I3312_TO_I3313 = 0x01000000,
+
+ /* Load/store register pair instructions. */
+ I3314_LDP = 0x28400000,
+ I3314_STP = 0x28000000,
+
+ /* Add/subtract immediate instructions. */
+ I3401_ADDI = 0x11000000,
+ I3401_ADDSI = 0x31000000,
+ I3401_SUBI = 0x51000000,
+ I3401_SUBSI = 0x71000000,
+
+ /* Bitfield instructions. */
+ I3402_BFM = 0x33000000,
+ I3402_SBFM = 0x13000000,
+ I3402_UBFM = 0x53000000,
+
+ /* Extract instruction. */
+ I3403_EXTR = 0x13800000,
+
+ /* Logical immediate instructions. */
+ I3404_ANDI = 0x12000000,
+ I3404_ORRI = 0x32000000,
+ I3404_EORI = 0x52000000,
+
+ /* Move wide immediate instructions. */
+ I3405_MOVN = 0x12800000,
+ I3405_MOVZ = 0x52800000,
+ I3405_MOVK = 0x72800000,
+
+ /* PC relative addressing instructions. */
+ I3406_ADR = 0x10000000,
+ I3406_ADRP = 0x90000000,
+
+ /* Add/subtract shifted register instructions (without a shift). */
+ I3502_ADD = 0x0b000000,
+ I3502_ADDS = 0x2b000000,
+ I3502_SUB = 0x4b000000,
+ I3502_SUBS = 0x6b000000,
+
+ /* Add/subtract shifted register instructions (with a shift). */
+ I3502S_ADD_LSL = I3502_ADD,
+
+ /* Add/subtract with carry instructions. */
+ I3503_ADC = 0x1a000000,
+ I3503_SBC = 0x5a000000,
+
+ /* Conditional select instructions. */
+ I3506_CSEL = 0x1a800000,
+ I3506_CSINC = 0x1a800400,
+ I3506_CSINV = 0x5a800000,
+ I3506_CSNEG = 0x5a800400,
+
+ /* Data-processing (1 source) instructions. */
+ I3507_CLZ = 0x5ac01000,
+ I3507_RBIT = 0x5ac00000,
+ I3507_REV16 = 0x5ac00400,
+ I3507_REV32 = 0x5ac00800,
+ I3507_REV64 = 0x5ac00c00,
+
+ /* Data-processing (2 source) instructions. */
+ I3508_LSLV = 0x1ac02000,
+ I3508_LSRV = 0x1ac02400,
+ I3508_ASRV = 0x1ac02800,
+ I3508_RORV = 0x1ac02c00,
+ I3508_SMULH = 0x9b407c00,
+ I3508_UMULH = 0x9bc07c00,
+ I3508_UDIV = 0x1ac00800,
+ I3508_SDIV = 0x1ac00c00,
+
+ /* Data-processing (3 source) instructions. */
+ I3509_MADD = 0x1b000000,
+ I3509_MSUB = 0x1b008000,
+
+ /* Logical shifted register instructions (without a shift). */
+ I3510_AND = 0x0a000000,
+ I3510_BIC = 0x0a200000,
+ I3510_ORR = 0x2a000000,
+ I3510_ORN = 0x2a200000,
+ I3510_EOR = 0x4a000000,
+ I3510_EON = 0x4a200000,
+ I3510_ANDS = 0x6a000000,
+
+ /* Logical shifted register instructions (with a shift). */
+ I3502S_AND_LSR = I3510_AND | (1 << 22),
+
+ /* AdvSIMD copy */
+ I3605_DUP = 0x0e000400,
+ I3605_INS = 0x4e001c00,
+ I3605_UMOV = 0x0e003c00,
+
+ /* AdvSIMD modified immediate */
+ I3606_MOVI = 0x0f000400,
+ I3606_MVNI = 0x2f000400,
+ I3606_BIC = 0x2f001400,
+ I3606_ORR = 0x0f001400,
+
+ /* AdvSIMD shift by immediate */
+ I3614_SSHR = 0x0f000400,
+ I3614_SSRA = 0x0f001400,
+ I3614_SHL = 0x0f005400,
+ I3614_SLI = 0x2f005400,
+ I3614_USHR = 0x2f000400,
+ I3614_USRA = 0x2f001400,
+
+ /* AdvSIMD three same. */
+ I3616_ADD = 0x0e208400,
+ I3616_AND = 0x0e201c00,
+ I3616_BIC = 0x0e601c00,
+ I3616_BIF = 0x2ee01c00,
+ I3616_BIT = 0x2ea01c00,
+ I3616_BSL = 0x2e601c00,
+ I3616_EOR = 0x2e201c00,
+ I3616_MUL = 0x0e209c00,
+ I3616_ORR = 0x0ea01c00,
+ I3616_ORN = 0x0ee01c00,
+ I3616_SUB = 0x2e208400,
+ I3616_CMGT = 0x0e203400,
+ I3616_CMGE = 0x0e203c00,
+ I3616_CMTST = 0x0e208c00,
+ I3616_CMHI = 0x2e203400,
+ I3616_CMHS = 0x2e203c00,
+ I3616_CMEQ = 0x2e208c00,
+ I3616_SMAX = 0x0e206400,
+ I3616_SMIN = 0x0e206c00,
+ I3616_SSHL = 0x0e204400,
+ I3616_SQADD = 0x0e200c00,
+ I3616_SQSUB = 0x0e202c00,
+ I3616_UMAX = 0x2e206400,
+ I3616_UMIN = 0x2e206c00,
+ I3616_UQADD = 0x2e200c00,
+ I3616_UQSUB = 0x2e202c00,
+ I3616_USHL = 0x2e204400,
+
+ /* AdvSIMD two-reg misc. */
+ I3617_CMGT0 = 0x0e208800,
+ I3617_CMEQ0 = 0x0e209800,
+ I3617_CMLT0 = 0x0e20a800,
+ I3617_CMGE0 = 0x2e208800,
+ I3617_CMLE0 = 0x2e20a800,
+ I3617_NOT = 0x2e205800,
+ I3617_ABS = 0x0e20b800,
+ I3617_NEG = 0x2e20b800,
+
+ /* System instructions. */
+ NOP = 0xd503201f,
+ DMB_ISH = 0xd50338bf,
+ DMB_LD = 0x00000100,
+ DMB_ST = 0x00000200,
+} AArch64Insn;
+
+static inline uint32_t tcg_in32(TCGContext *s)
+{
+ uint32_t v = *(uint32_t *)s->code_ptr;
+ return v;
+}
+
+/* Emit an opcode with "type-checking" of the format. */
+#define tcg_out_insn(S, FMT, OP, ...) \
+ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
+
+static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rt, TCGReg rn, unsigned size)
+{
+ tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
+}
+
+static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
+ int imm19, TCGReg rt)
+{
+ tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
+}
+
+static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rt, int imm19)
+{
+ tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt);
+}
+
+static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn,
+ TCGCond c, int imm19)
+{
+ tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5);
+}
+
+static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26)
+{
+ tcg_out32(s, insn | (imm26 & 0x03ffffff));
+}
+
+static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn)
+{
+ tcg_out32(s, insn | rn << 5);
+}
+
+static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,
+ TCGReg r1, TCGReg r2, TCGReg rn,
+ tcg_target_long ofs, bool pre, bool w)
+{
+ insn |= 1u << 31; /* ext */
+ insn |= pre << 24;
+ insn |= w << 23;
+
+ tcg_debug_assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0);
+ insn |= (ofs & (0x7f << 3)) << (15 - 3);
+
+ tcg_out32(s, insn | r2 << 10 | rn << 5 | r1);
+}
+
+static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, uint64_t aimm)
+{
+ if (aimm > 0xfff) {
+ tcg_debug_assert((aimm & 0xfff) == 0);
+ aimm >>= 12;
+ tcg_debug_assert(aimm <= 0xfff);
+ aimm |= 1 << 12; /* apply LSL 12 */
+ }
+ tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd);
+}
+
+/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4
+ (Logical immediate). Both insn groups have N, IMMR and IMMS fields
+ that feed the DecodeBitMasks pseudo function. */
+static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, int n, int immr, int imms)
+{
+ tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10
+ | rn << 5 | rd);
+}
+
+#define tcg_out_insn_3404 tcg_out_insn_3402
+
+static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm, int imms)
+{
+ tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10
+ | rn << 5 | rd);
+}
+
+/* This function is used for the Move (wide immediate) instruction group.
+ Note that SHIFT is a full shift count, not the 2 bit HW field. */
+static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, uint16_t half, unsigned shift)
+{
+ tcg_debug_assert((shift & ~0x30) == 0);
+ tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);
+}
+
+static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,
+ TCGReg rd, int64_t disp)
+{
+ tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
+}
+
+/* This function is for both 3.5.2 (Add/Subtract shifted register), for
+ the rare occasion when we actually want to supply a shift amount. */
+static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
+ TCGType ext, TCGReg rd, TCGReg rn,
+ TCGReg rm, int imm6)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd);
+}
+
+/* This function is for 3.5.2 (Add/subtract shifted register),
+ and 3.5.10 (Logical shifted register), for the vast majorty of cases
+ when we don't want to apply a shift. Thus it can also be used for
+ 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */
+static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd);
+}
+
+#define tcg_out_insn_3503 tcg_out_insn_3502
+#define tcg_out_insn_3508 tcg_out_insn_3502
+#define tcg_out_insn_3510 tcg_out_insn_3502
+
+static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd
+ | tcg_cond_to_aarch64[c] << 12);
+}
+
+static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn)
+{
+ tcg_out32(s, insn | ext << 31 | rn << 5 | rd);
+}
+
+static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
+}
+
+static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, TCGReg rn, int dst_idx, int src_idx)
+{
+ /* Note that bit 11 set means general register input. Therefore
+ we can handle both register sets with one function. */
+ tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11)
+ | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);
+}
+
+static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, bool op, int cmode, uint8_t imm8)
+{
+ tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)
+ | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
+}
+
+static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, TCGReg rn, unsigned immhb)
+{
+ tcg_out32(s, insn | q << 30 | immhb << 16
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22)
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
+ TCGReg rd, TCGReg base, TCGType ext,
+ TCGReg regoff)
+{
+ /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
+ tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
+ 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
+ TCGReg rd, TCGReg rn, intptr_t offset)
+{
+ tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,
+ TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
+{
+ /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
+ tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10
+ | rn << 5 | (rd & 0x1f));
+}
+
+/* Register to register move using ORR (shifted register with no shift). */
+static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
+{
+ tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
+}
+
+/* Register to register move using ADDI (move to/from SP). */
+static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
+{
+ tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
+}
+
+/* This function is used for the Logical (immediate) instruction group.
+ The value of LIMM must satisfy IS_LIMM. See the comment above about
+ only supporting simplified logical immediates. */
+static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, uint64_t limm)
+{
+ unsigned h, l, r, c;
+
+ tcg_debug_assert(is_limm(limm));
+
+ h = clz64(limm);
+ l = ctz64(limm);
+ if (l == 0) {
+ r = 0; /* form 0....01....1 */
+ c = ctz64(~limm) - 1;
+ if (h == 0) {
+ r = clz64(~limm); /* form 1..10..01..1 */
+ c += r;
+ }
+ } else {
+ r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
+ c = r - h - 1;
+ }
+ if (ext == TCG_TYPE_I32) {
+ r &= 31;
+ c &= 31;
+ }
+
+ tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg rd, tcg_target_long v64)
+{
+ bool q = type == TCG_TYPE_V128;
+ int cmode, imm8, i;
+
+ /* Test all bytes equal first. */
+ if (v64 == dup_const(MO_8, v64)) {
+ imm8 = (uint8_t)v64;
+ tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);
+ return;
+ }
+
+ /*
+ * Test all bytes 0x00 or 0xff second. This can match cases that
+ * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
+ */
+ for (i = imm8 = 0; i < 8; i++) {
+ uint8_t byte = v64 >> (i * 8);
+ if (byte == 0xff) {
+ imm8 |= 1 << i;
+ } else if (byte != 0) {
+ goto fail_bytes;
+ }
+ }
+ tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8);
+ return;
+ fail_bytes:
+
+ /*
+ * Tests for various replications. For each element width, if we
+ * cannot find an expansion there's no point checking a larger
+ * width because we already know by replication it cannot match.
+ */
+ if (v64 == dup_const(MO_16, v64)) {
+ uint16_t v16 = v64;
+
+ if (is_shimm16(v16, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
+ return;
+ }
+ if (is_shimm16(~v16, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
+ return;
+ }
+
+ /*
+ * Otherwise, all remaining constants can be loaded in two insns:
+ * rd = v16 & 0xff, rd |= v16 & 0xff00.
+ */
+ tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);
+ tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);
+ return;
+ } else if (v64 == dup_const(MO_32, v64)) {
+ uint32_t v32 = v64;
+ uint32_t n32 = ~v32;
+
+ if (is_shimm32(v32, &cmode, &imm8) ||
+ is_soimm32(v32, &cmode, &imm8) ||
+ is_fimm32(v32, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
+ return;
+ }
+ if (is_shimm32(n32, &cmode, &imm8) ||
+ is_soimm32(n32, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
+ return;
+ }
+
+ /*
+ * Restrict the set of constants to those we can load with
+ * two instructions. Others we load from the pool.
+ */
+ i = is_shimm32_pair(v32, &cmode, &imm8);
+ if (i) {
+ tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
+ tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8));
+ return;
+ }
+ i = is_shimm32_pair(n32, &cmode, &imm8);
+ if (i) {
+ tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
+ tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8));
+ return;
+ }
+ } else if (is_fimm64(v64, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8);
+ return;
+ }
+
+ /*
+ * As a last resort, load from the constant pool. Sadly there
+ * is no LD1R (literal), so store the full 16-byte vector.
+ */
+ if (type == TCG_TYPE_V128) {
+ new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
+ tcg_out_insn(s, 3305, LDR_v128, 0, rd);
+ } else {
+ new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);
+ tcg_out_insn(s, 3305, LDR_v64, 0, rd);
+ }
+}
+
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg rd, TCGReg rs)
+{
+ int is_q = type - TCG_TYPE_V64;
+ tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0);
+ return true;
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg base, intptr_t offset)
+{
+ TCGReg temp = TCG_REG_TMP;
+
+ if (offset < -0xffffff || offset > 0xffffff) {
+ tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);
+ tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);
+ base = temp;
+ } else {
+ AArch64Insn add_insn = I3401_ADDI;
+
+ if (offset < 0) {
+ add_insn = I3401_SUBI;
+ offset = -offset;
+ }
+ if (offset & 0xfff000) {
+ tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
+ base = temp;
+ }
+ if (offset & 0xfff) {
+ tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
+ base = temp;
+ }
+ }
+ tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);
+ return true;
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long value)
+{
+ tcg_target_long svalue = value;
+ tcg_target_long ivalue = ~value;
+ tcg_target_long t0, t1, t2;
+ int s0, s1;
+ AArch64Insn opc;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_debug_assert(rd < 32);
+ break;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(rd >= 32);
+ tcg_out_dupi_vec(s, type, rd, value);
+ return;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ /* For 32-bit values, discard potential garbage in value. For 64-bit
+ values within [2**31, 2**32-1], we can create smaller sequences by
+ interpreting this as a negative 32-bit number, while ensuring that
+ the high 32 bits are cleared by setting SF=0. */
+ if (type == TCG_TYPE_I32 || (value & ~0xffffffffull) == 0) {
+ svalue = (int32_t)value;
+ value = (uint32_t)value;
+ ivalue = (uint32_t)ivalue;
+ type = TCG_TYPE_I32;
+ }
+
+ /* Speed things up by handling the common case of small positive
+ and negative values specially. */
+ if ((value & ~0xffffull) == 0) {
+ tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0);
+ return;
+ } else if ((ivalue & ~0xffffull) == 0) {
+ tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0);
+ return;
+ }
+
+ /* Check for bitfield immediates. For the benefit of 32-bit quantities,
+ use the sign-extended value. That lets us match rotated values such
+ as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */
+ if (is_limm(svalue)) {
+ tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue);
+ return;
+ }
+
+ /* Look for host pointer values within 4G of the PC. This happens
+ often when loading pointers to QEMU's own data structures. */
+ if (type == TCG_TYPE_I64) {
+ tcg_target_long disp = value - (intptr_t)s->code_ptr;
+ if (disp == sextract64(disp, 0, 21)) {
+ tcg_out_insn(s, 3406, ADR, rd, disp);
+ return;
+ }
+ disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
+ if (disp == sextract64(disp, 0, 21)) {
+ tcg_out_insn(s, 3406, ADRP, rd, disp);
+ if (value & 0xfff) {
+ tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
+ }
+ return;
+ }
+ }
+
+ /* Would it take fewer insns to begin with MOVN? */
+ if (ctpop64(value) >= 32) {
+ t0 = ivalue;
+ opc = I3405_MOVN;
+ } else {
+ t0 = value;
+ opc = I3405_MOVZ;
+ }
+ s0 = ctz64(t0) & (63 & -16);
+ t1 = t0 & ~(0xffffUL << s0);
+ s1 = ctz64(t1) & (63 & -16);
+ t2 = t1 & ~(0xffffUL << s1);
+ if (t2 == 0) {
+ tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0);
+ if (t1 != 0) {
+ tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1);
+ }
+ return;
+ }
+
+ /* For more than 2 insns, dump it into the constant pool. */
+ new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0);
+ tcg_out_insn(s, 3305, LDR, 0, rd);
+}
+
+/* Define something more legible for general use. */
+#define tcg_out_ldst_r tcg_out_insn_3310
+
+static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
+ TCGReg rn, intptr_t offset, int lgsize)
+{
+ /* If the offset is naturally aligned and in range, then we can
+ use the scaled uimm12 encoding */
+ if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {
+ uintptr_t scaled_uimm = offset >> lgsize;
+ if (scaled_uimm <= 0xfff) {
+ tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);
+ return;
+ }
+ }
+
+ /* Small signed offsets can use the unscaled encoding. */
+ if (offset >= -256 && offset < 256) {
+ tcg_out_insn_3312(s, insn, rd, rn, offset);
+ return;
+ }
+
+ /* Worst-case scenario, move offset to temp register, use reg offset. */
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
+ tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
+}
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ if (ret < 32 && arg < 32) {
+ tcg_out_movr(s, type, ret, arg);
+ break;
+ } else if (ret < 32) {
+ tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
+ break;
+ } else if (arg < 32) {
+ tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
+ break;
+ }
+ /* FALLTHRU */
+
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg base, intptr_t ofs)
+{
+ AArch64Insn insn;
+ int lgsz;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS);
+ lgsz = 2;
+ break;
+ case TCG_TYPE_I64:
+ insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD);
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V64:
+ insn = I3312_LDRVD;
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V128:
+ insn = I3312_LDRVQ;
+ lgsz = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_ldst(s, insn, ret, base, ofs, lgsz);
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
+ TCGReg base, intptr_t ofs)
+{
+ AArch64Insn insn;
+ int lgsz;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ insn = (src < 32 ? I3312_STRW : I3312_STRVS);
+ lgsz = 2;
+ break;
+ case TCG_TYPE_I64:
+ insn = (src < 32 ? I3312_STRX : I3312_STRVD);
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V64:
+ insn = I3312_STRVD;
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V128:
+ insn = I3312_STRVQ;
+ lgsz = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_ldst(s, insn, src, base, ofs, lgsz);
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ if (type <= TCG_TYPE_I64 && val == 0) {
+ tcg_out_st(s, type, TCG_REG_XZR, base, ofs);
+ return true;
+ }
+ return false;
+}
+
+static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned int a, unsigned int b)
+{
+ tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b);
+}
+
+static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned int a, unsigned int b)
+{
+ tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b);
+}
+
+static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned int a, unsigned int b)
+{
+ tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b);
+}
+
+static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, TCGReg rm, unsigned int a)
+{
+ tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);
+}
+
+static inline void tcg_out_shl(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn, unsigned int m)
+{
+ int bits = ext ? 64 : 32;
+ int max = bits - 1;
+ tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max));
+}
+
+static inline void tcg_out_shr(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn, unsigned int m)
+{
+ int max = ext ? 63 : 31;
+ tcg_out_ubfm(s, ext, rd, rn, m & max, max);
+}
+
+static inline void tcg_out_sar(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn, unsigned int m)
+{
+ int max = ext ? 63 : 31;
+ tcg_out_sbfm(s, ext, rd, rn, m & max, max);
+}
+
+static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn, unsigned int m)
+{
+ int max = ext ? 63 : 31;
+ tcg_out_extr(s, ext, rd, rn, rn, m & max);
+}
+
+static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn, unsigned int m)
+{
+ int bits = ext ? 64 : 32;
+ int max = bits - 1;
+ tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
+}
+
+static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned lsb, unsigned width)
+{
+ unsigned size = ext ? 64 : 32;
+ unsigned a = (size - lsb) & (size - 1);
+ unsigned b = width - 1;
+ tcg_out_bfm(s, ext, rd, rn, a, b);
+}
+
+static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
+ tcg_target_long b, bool const_b)
+{
+ if (const_b) {
+ /* Using CMP or CMN aliases. */
+ if (b >= 0) {
+ tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b);
+ } else {
+ tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b);
+ }
+ } else {
+ /* Using CMP alias SUBS wzr, Wn, Wm */
+ tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b);
+ }
+}
+
+static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = target - s->code_ptr;
+ tcg_debug_assert(offset == sextract64(offset, 0, 26));
+ tcg_out_insn(s, 3206, B, offset);
+}
+
+static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = target - s->code_ptr;
+ if (offset == sextract64(offset, 0, 26)) {
+ tcg_out_insn(s, 3206, BL, offset);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
+ tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
+ }
+}
+
+static inline void tcg_out_callr(TCGContext *s, TCGReg reg)
+{
+ tcg_out_insn(s, 3207, BLR, reg);
+}
+
+static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = target - s->code_ptr;
+ if (offset == sextract64(offset, 0, 26)) {
+ tcg_out_insn(s, 3206, BL, offset);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
+ tcg_out_callr(s, TCG_REG_TMP);
+ }
+}
+
+void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
+ uintptr_t addr)
+{
+ tcg_insn_unit i1, i2;
+ TCGType rt = TCG_TYPE_I64;
+ TCGReg rd = TCG_REG_TMP;
+ uint64_t pair;
+
+ ptrdiff_t offset = addr - jmp_addr;
+
+ if (offset == sextract64(offset, 0, 26)) {
+ i1 = I3206_B | ((offset >> 2) & 0x3ffffff);
+ i2 = NOP;
+ } else {
+ offset = (addr >> 12) - (jmp_addr >> 12);
+
+ /* patch ADRP */
+ i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd;
+ /* patch ADDI */
+ i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd;
+ }
+ pair = (uint64_t)i2 << 32 | i1;
+ atomic_set((uint64_t *)jmp_addr, pair);
+ flush_icache_range(jmp_addr, jmp_addr + 8);
+}
+
+static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l)
+{
+ if (!l->has_value) {
+ tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0);
+ tcg_out_insn(s, 3206, B, 0);
+ } else {
+ tcg_out_goto(s, l->u.value_ptr);
+ }
+}
+
+static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
+ TCGArg b, bool b_const, TCGLabel *l)
+{
+ intptr_t offset;
+ bool need_cmp;
+
+ if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) {
+ need_cmp = false;
+ } else {
+ need_cmp = true;
+ tcg_out_cmp(s, ext, a, b, b_const);
+ }
+
+ if (!l->has_value) {
+ tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
+ offset = tcg_in32(s) >> 5;
+ } else {
+ offset = l->u.value_ptr - s->code_ptr;
+ tcg_debug_assert(offset == sextract64(offset, 0, 19));
+ }
+
+ if (need_cmp) {
+ tcg_out_insn(s, 3202, B_C, c, offset);
+ } else if (c == TCG_COND_EQ) {
+ tcg_out_insn(s, 3201, CBZ, ext, a, offset);
+ } else {
+ tcg_out_insn(s, 3201, CBNZ, ext, a, offset);
+ }
+}
+
+static inline void tcg_out_rev64(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+ tcg_out_insn(s, 3507, REV64, TCG_TYPE_I64, rd, rn);
+}
+
+static inline void tcg_out_rev32(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+ tcg_out_insn(s, 3507, REV32, TCG_TYPE_I32, rd, rn);
+}
+
+static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+ tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);
+}
+
+static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,
+ TCGReg rd, TCGReg rn)
+{
+ /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
+ int bits = (8 << s_bits) - 1;
+ tcg_out_sbfm(s, ext, rd, rn, 0, bits);
+}
+
+static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,
+ TCGReg rd, TCGReg rn)
+{
+ /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
+ int bits = (8 << s_bits) - 1;
+ tcg_out_ubfm(s, 0, rd, rn, 0, bits);
+}
+
+static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
+ TCGReg rn, int64_t aimm)
+{
+ if (aimm >= 0) {
+ tcg_out_insn(s, 3401, ADDI, ext, rd, rn, aimm);
+ } else {
+ tcg_out_insn(s, 3401, SUBI, ext, rd, rn, -aimm);
+ }
+}
+
+static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
+ TCGReg rh, TCGReg al, TCGReg ah,
+ tcg_target_long bl, tcg_target_long bh,
+ bool const_bl, bool const_bh, bool sub)
+{
+ TCGReg orig_rl = rl;
+ AArch64Insn insn;
+
+ if (rl == ah || (!const_bh && rl == bh)) {
+ rl = TCG_REG_TMP;
+ }
+
+ if (const_bl) {
+ insn = I3401_ADDSI;
+ if ((bl < 0) ^ sub) {
+ insn = I3401_SUBSI;
+ bl = -bl;
+ }
+ if (unlikely(al == TCG_REG_XZR)) {
+ /* ??? We want to allow al to be zero for the benefit of
+ negation via subtraction. However, that leaves open the
+ possibility of adding 0+const in the low part, and the
+ immediate add instructions encode XSP not XZR. Don't try
+ anything more elaborate here than loading another zero. */
+ al = TCG_REG_TMP;
+ tcg_out_movi(s, ext, al, 0);
+ }
+ tcg_out_insn_3401(s, insn, ext, rl, al, bl);
+ } else {
+ tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);
+ }
+
+ insn = I3503_ADC;
+ if (const_bh) {
+ /* Note that the only two constants we support are 0 and -1, and
+ that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */
+ if ((bh != 0) ^ sub) {
+ insn = I3503_SBC;
+ }
+ bh = TCG_REG_XZR;
+ } else if (sub) {
+ insn = I3503_SBC;
+ }
+ tcg_out_insn_3503(s, insn, ext, rh, ah, bh);
+
+ tcg_out_mov(s, ext, orig_rl, rl);
+}
+
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ static const uint32_t sync[] = {
+ [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST,
+ [TCG_MO_ST_ST] = DMB_ISH | DMB_ST,
+ [TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
+ [TCG_MO_LD_ST] = DMB_ISH | DMB_LD,
+ [TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
+ };
+ tcg_out32(s, sync[a0 & TCG_MO_ALL]);
+}
+
+static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
+ TCGReg a0, TCGArg b, bool const_b, bool is_ctz)
+{
+ TCGReg a1 = a0;
+ if (is_ctz) {
+ a1 = TCG_REG_TMP;
+ tcg_out_insn(s, 3507, RBIT, ext, a1, a0);
+ }
+ if (const_b && b == (ext ? 64 : 32)) {
+ tcg_out_insn(s, 3507, CLZ, ext, d, a1);
+ } else {
+ AArch64Insn sel = I3506_CSEL;
+
+ tcg_out_cmp(s, ext, a0, 0, 1);
+ tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1);
+
+ if (const_b) {
+ if (b == -1) {
+ b = TCG_REG_XZR;
+ sel = I3506_CSINV;
+ } else if (b == 0) {
+ b = TCG_REG_XZR;
+ } else {
+ tcg_out_movi(s, ext, d, b);
+ b = d;
+ }
+ }
+ tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE);
+ }
+}
+
+#ifdef CONFIG_SOFTMMU
+#include "../tcg-ldst.c.inc"
+
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * TCGMemOpIdx oi, uintptr_t ra)
+ */
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+};
+
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, TCGMemOpIdx oi,
+ * uintptr_t ra)
+ */
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+
+static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
+{
+ ptrdiff_t offset = tcg_pcrel_diff(s, target);
+ tcg_debug_assert(offset == sextract64(offset, 0, 21));
+ tcg_out_insn(s, 3406, ADR, rd, offset);
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+ MemOp size = opc & MO_SIZE;
+
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
+ tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi);
+ tcg_out_adr(s, TCG_REG_X3, lb->raddr);
+ tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ if (opc & MO_SIGN) {
+ tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0);
+ } else {
+ tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0);
+ }
+
+ tcg_out_goto(s, lb->raddr);
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+ MemOp size = opc & MO_SIZE;
+
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
+ tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
+ tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi);
+ tcg_out_adr(s, TCG_REG_X4, lb->raddr);
+ tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ tcg_out_goto(s, lb->raddr);
+ return true;
+}
+
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+ TCGType ext, TCGReg data_reg, TCGReg addr_reg,
+ tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->type = ext;
+ label->datalo_reg = data_reg;
+ label->addrlo_reg = addr_reg;
+ label->raddr = raddr;
+ label->label_ptr[0] = label_ptr;
+}
+
+/* We expect to use a 7-bit scaled negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512);
+
+/* These offsets are built into the LDP below. */
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);
+
+/* Load and compare a TLB entry, emitting the conditional jump to the
+ slow path for the failure case, which will be patched later when finalizing
+ the slow path. Generated code returns the host addend in X1,
+ clobbers X0,X2,X3,TMP. */
+static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
+ tcg_insn_unit **label_ptr, int mem_index,
+ bool is_read)
+{
+ unsigned a_bits = get_alignment_bits(opc);
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_mask = (1u << a_bits) - 1;
+ unsigned s_mask = (1u << s_bits) - 1;
+ TCGReg x3;
+ TCGType mask_type;
+ uint64_t compare_mask;
+
+ mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32
+ ? TCG_TYPE_I64 : TCG_TYPE_I32);
+
+ /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */
+ tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0,
+ TLB_MASK_TABLE_OFS(mem_index), 1, 0);
+
+ /* Extract the TLB index from the address into X0. */
+ tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64,
+ TCG_REG_X0, TCG_REG_X0, addr_reg,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+
+ /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1. */
+ tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0);
+
+ /* Load the tlb comparator into X0, and the fast path addend into X1. */
+ tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read
+ ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1,
+ offsetof(CPUTLBEntry, addend));
+
+ /* For aligned accesses, we check the first byte and include the alignment
+ bits within the address. For unaligned access, we check that we don't
+ cross pages using the address of the last byte of the access. */
+ if (a_bits >= s_bits) {
+ x3 = addr_reg;
+ } else {
+ tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS == 64,
+ TCG_REG_X3, addr_reg, s_mask - a_mask);
+ x3 = TCG_REG_X3;
+ }
+ compare_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
+
+ /* Store the page mask part of the address into X3. */
+ tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64,
+ TCG_REG_X3, x3, compare_mask);
+
+ /* Perform the address comparison. */
+ tcg_out_cmp(s, TARGET_LONG_BITS == 64, TCG_REG_X0, TCG_REG_X3, 0);
+
+ /* If not equal, we jump to the slow path. */
+ *label_ptr = s->code_ptr;
+ tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
+}
+
+#endif /* CONFIG_SOFTMMU */
+
+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
+ TCGReg data_r, TCGReg addr_r,
+ TCGType otype, TCGReg off_r)
+{
+ const MemOp bswap = memop & MO_BSWAP;
+
+ switch (memop & MO_SSIZE) {
+ case MO_UB:
+ tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
+ break;
+ case MO_SB:
+ tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
+ data_r, addr_r, otype, off_r);
+ break;
+ case MO_UW:
+ tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
+ if (bswap) {
+ tcg_out_rev16(s, data_r, data_r);
+ }
+ break;
+ case MO_SW:
+ if (bswap) {
+ tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
+ tcg_out_rev16(s, data_r, data_r);
+ tcg_out_sxt(s, ext, MO_16, data_r, data_r);
+ } else {
+ tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
+ data_r, addr_r, otype, off_r);
+ }
+ break;
+ case MO_UL:
+ tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
+ if (bswap) {
+ tcg_out_rev32(s, data_r, data_r);
+ }
+ break;
+ case MO_SL:
+ if (bswap) {
+ tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
+ tcg_out_rev32(s, data_r, data_r);
+ tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);
+ } else {
+ tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
+ }
+ break;
+ case MO_Q:
+ tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
+ if (bswap) {
+ tcg_out_rev64(s, data_r, data_r);
+ }
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
+ TCGReg data_r, TCGReg addr_r,
+ TCGType otype, TCGReg off_r)
+{
+ const MemOp bswap = memop & MO_BSWAP;
+
+ switch (memop & MO_SIZE) {
+ case MO_8:
+ tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
+ break;
+ case MO_16:
+ if (bswap && data_r != TCG_REG_XZR) {
+ tcg_out_rev16(s, TCG_REG_TMP, data_r);
+ data_r = TCG_REG_TMP;
+ }
+ tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
+ break;
+ case MO_32:
+ if (bswap && data_r != TCG_REG_XZR) {
+ tcg_out_rev32(s, TCG_REG_TMP, data_r);
+ data_r = TCG_REG_TMP;
+ }
+ tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
+ break;
+ case MO_64:
+ if (bswap && data_r != TCG_REG_XZR) {
+ tcg_out_rev64(s, TCG_REG_TMP, data_r);
+ data_r = TCG_REG_TMP;
+ }
+ tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+ TCGMemOpIdx oi, TCGType ext)
+{
+ MemOp memop = get_memop(oi);
+ const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
+ tcg_insn_unit *label_ptr;
+
+ tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
+ tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+ TCG_REG_X1, otype, addr_reg);
+ add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
+ s->code_ptr, label_ptr);
+#else /* !CONFIG_SOFTMMU */
+ if (USE_GUEST_BASE) {
+ tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+ TCG_REG_GUEST_BASE, otype, addr_reg);
+ } else {
+ tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+ addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
+ }
+#endif /* CONFIG_SOFTMMU */
+}
+
+static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+ TCGMemOpIdx oi)
+{
+ MemOp memop = get_memop(oi);
+ const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
+ tcg_insn_unit *label_ptr;
+
+ tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
+ tcg_out_qemu_st_direct(s, memop, data_reg,
+ TCG_REG_X1, otype, addr_reg);
+ add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
+ data_reg, addr_reg, s->code_ptr, label_ptr);
+#else /* !CONFIG_SOFTMMU */
+ if (USE_GUEST_BASE) {
+ tcg_out_qemu_st_direct(s, memop, data_reg,
+ TCG_REG_GUEST_BASE, otype, addr_reg);
+ } else {
+ tcg_out_qemu_st_direct(s, memop, data_reg,
+ addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
+ }
+#endif /* CONFIG_SOFTMMU */
+}
+
+static tcg_insn_unit *tb_ret_addr;
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
+{
+ /* 99% of the time, we can signal the use of extension registers
+ by looking to see if the opcode handles 64-bit data. */
+ TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
+
+ /* Hoist the loads of the most common arguments. */
+ TCGArg a0 = args[0];
+ TCGArg a1 = args[1];
+ TCGArg a2 = args[2];
+ int c2 = const_args[2];
+
+ /* Some operands are defined with "rZ" constraint, a register or
+ the zero register. These need not actually test args[I] == 0. */
+#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ /* Reuse the zeroing that exists for goto_ptr. */
+ if (a0 == 0) {
+ tcg_out_goto_long(s, s->code_gen_epilogue);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
+ tcg_out_goto_long(s, tb_ret_addr);
+ }
+ break;
+
+ case INDEX_op_goto_tb:
+ if (s->tb_jmp_insn_offset != NULL) {
+ /* TCG_TARGET_HAS_direct_jump */
+ /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic
+ write can be used to patch the target address. */
+ if ((uintptr_t)s->code_ptr & 7) {
+ tcg_out32(s, NOP);
+ }
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ /* actual branch destination will be patched by
+ tb_target_set_jmp_target later. */
+ tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0);
+ tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0);
+ } else {
+ /* !TCG_TARGET_HAS_direct_jump */
+ tcg_debug_assert(s->tb_jmp_target_addr != NULL);
+ intptr_t offset = tcg_pcrel_diff(s, (s->tb_jmp_target_addr + a0)) >> 2;
+ tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP);
+ }
+ tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
+ set_jmp_reset_offset(s, a0);
+ break;
+
+ case INDEX_op_goto_ptr:
+ tcg_out_insn(s, 3207, BR, a0);
+ break;
+
+ case INDEX_op_br:
+ tcg_out_goto_label(s, arg_label(a0));
+ break;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
+ break;
+ case INDEX_op_ld8s_i32:
+ tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);
+ break;
+ case INDEX_op_ld8s_i64:
+ tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);
+ break;
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1);
+ break;
+ case INDEX_op_ld16s_i32:
+ tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1);
+ break;
+ case INDEX_op_ld16s_i64:
+ tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1);
+ break;
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32u_i64:
+ tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2);
+ break;
+ case INDEX_op_ld32s_i64:
+ tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3);
+ break;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
+ break;
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
+ break;
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
+ break;
+
+ case INDEX_op_add_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_add_i64:
+ if (c2) {
+ tcg_out_addsubi(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_sub_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_sub_i64:
+ if (c2) {
+ tcg_out_addsubi(s, ext, a0, a1, -a2);
+ } else {
+ tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_neg_i64:
+ case INDEX_op_neg_i32:
+ tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
+ break;
+
+ case INDEX_op_and_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_and_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_andc_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_andc_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_or_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_or_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_orc_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_orc_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_xor_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_xor_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_eqv_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_eqv_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, EON, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_not_i64:
+ case INDEX_op_not_i32:
+ tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
+ break;
+
+ case INDEX_op_mul_i64:
+ case INDEX_op_mul_i32:
+ tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR);
+ break;
+
+ case INDEX_op_div_i64:
+ case INDEX_op_div_i32:
+ tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2);
+ break;
+ case INDEX_op_divu_i64:
+ case INDEX_op_divu_i32:
+ tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2);
+ break;
+
+ case INDEX_op_rem_i64:
+ case INDEX_op_rem_i32:
+ tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2);
+ tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
+ break;
+ case INDEX_op_remu_i64:
+ case INDEX_op_remu_i32:
+ tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2);
+ tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
+ break;
+
+ case INDEX_op_shl_i64:
+ case INDEX_op_shl_i32:
+ if (c2) {
+ tcg_out_shl(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_shr_i64:
+ case INDEX_op_shr_i32:
+ if (c2) {
+ tcg_out_shr(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_sar_i64:
+ case INDEX_op_sar_i32:
+ if (c2) {
+ tcg_out_sar(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_rotr_i64:
+ case INDEX_op_rotr_i32:
+ if (c2) {
+ tcg_out_rotr(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotl_i32:
+ if (c2) {
+ tcg_out_rotl(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2);
+ tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP);
+ }
+ break;
+
+ case INDEX_op_clz_i64:
+ case INDEX_op_clz_i32:
+ tcg_out_cltz(s, ext, a0, a1, a2, c2, false);
+ break;
+ case INDEX_op_ctz_i64:
+ case INDEX_op_ctz_i32:
+ tcg_out_cltz(s, ext, a0, a1, a2, c2, true);
+ break;
+
+ case INDEX_op_brcond_i32:
+ a1 = (int32_t)a1;
+ /* FALLTHRU */
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3]));
+ break;
+
+ case INDEX_op_setcond_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_setcond_i64:
+ tcg_out_cmp(s, ext, a1, a2, c2);
+ /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */
+ tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR,
+ TCG_REG_XZR, tcg_invert_cond(args[3]));
+ break;
+
+ case INDEX_op_movcond_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_movcond_i64:
+ tcg_out_cmp(s, ext, a1, a2, c2);
+ tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, a0, a1, a2, ext);
+ break;
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, REG0(0), a1, a2);
+ break;
+
+ case INDEX_op_bswap64_i64:
+ tcg_out_rev64(s, a0, a1);
+ break;
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap32_i32:
+ tcg_out_rev32(s, a0, a1);
+ break;
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap16_i32:
+ tcg_out_rev16(s, a0, a1);
+ break;
+
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8s_i32:
+ tcg_out_sxt(s, ext, MO_8, a0, a1);
+ break;
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext16s_i32:
+ tcg_out_sxt(s, ext, MO_16, a0, a1);
+ break;
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_ext32s_i64:
+ tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);
+ break;
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext8u_i32:
+ tcg_out_uxt(s, MO_8, a0, a1);
+ break;
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext16u_i32:
+ tcg_out_uxt(s, MO_16, a0, a1);
+ break;
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_ext32u_i64:
+ tcg_out_movr(s, TCG_TYPE_I32, a0, a1);
+ break;
+
+ case INDEX_op_deposit_i64:
+ case INDEX_op_deposit_i32:
+ tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
+ break;
+
+ case INDEX_op_extract_i64:
+ case INDEX_op_extract_i32:
+ tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
+ break;
+
+ case INDEX_op_sextract_i64:
+ case INDEX_op_sextract_i32:
+ tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
+ break;
+
+ case INDEX_op_extract2_i64:
+ case INDEX_op_extract2_i32:
+ tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
+ break;
+
+ case INDEX_op_add2_i32:
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
+ (int32_t)args[4], args[5], const_args[4],
+ const_args[5], false);
+ break;
+ case INDEX_op_add2_i64:
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
+ args[5], const_args[4], const_args[5], false);
+ break;
+ case INDEX_op_sub2_i32:
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
+ (int32_t)args[4], args[5], const_args[4],
+ const_args[5], true);
+ break;
+ case INDEX_op_sub2_i64:
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
+ args[5], const_args[4], const_args[5], true);
+ break;
+
+ case INDEX_op_muluh_i64:
+ tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ g_assert_not_reached();
+ }
+
+#undef REG0
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static const AArch64Insn cmp_insn[16] = {
+ [TCG_COND_EQ] = I3616_CMEQ,
+ [TCG_COND_GT] = I3616_CMGT,
+ [TCG_COND_GE] = I3616_CMGE,
+ [TCG_COND_GTU] = I3616_CMHI,
+ [TCG_COND_GEU] = I3616_CMHS,
+ };
+ static const AArch64Insn cmp0_insn[16] = {
+ [TCG_COND_EQ] = I3617_CMEQ0,
+ [TCG_COND_GT] = I3617_CMGT0,
+ [TCG_COND_GE] = I3617_CMGE0,
+ [TCG_COND_LT] = I3617_CMLT0,
+ [TCG_COND_LE] = I3617_CMLE0,
+ };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ unsigned is_q = vecl;
+ TCGArg a0, a1, a2, a3;
+ int cmode, imm8;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_dupm_vec:
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+ break;
+ case INDEX_op_add_vec:
+ tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_sub_vec:
+ tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_mul_vec:
+ tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_neg_vec:
+ tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
+ break;
+ case INDEX_op_abs_vec:
+ tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
+ break;
+ case INDEX_op_and_vec:
+ if (const_args[2]) {
+ is_shimm1632(~a2, &cmode, &imm8);
+ if (a0 == a1) {
+ tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
+ return;
+ }
+ tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
+ a2 = a0;
+ }
+ tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_or_vec:
+ if (const_args[2]) {
+ is_shimm1632(a2, &cmode, &imm8);
+ if (a0 == a1) {
+ tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
+ return;
+ }
+ tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
+ a2 = a0;
+ }
+ tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_andc_vec:
+ if (const_args[2]) {
+ is_shimm1632(a2, &cmode, &imm8);
+ if (a0 == a1) {
+ tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
+ return;
+ }
+ tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
+ a2 = a0;
+ }
+ tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_orc_vec:
+ if (const_args[2]) {
+ is_shimm1632(~a2, &cmode, &imm8);
+ if (a0 == a1) {
+ tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
+ return;
+ }
+ tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
+ a2 = a0;
+ }
+ tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_xor_vec:
+ tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_ssadd_vec:
+ tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_sssub_vec:
+ tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_usadd_vec:
+ tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_ussub_vec:
+ tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_smax_vec:
+ tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_smin_vec:
+ tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_umax_vec:
+ tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_umin_vec:
+ tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_not_vec:
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
+ break;
+ case INDEX_op_shli_vec:
+ tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
+ break;
+ case INDEX_op_shri_vec:
+ tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
+ break;
+ case INDEX_op_sari_vec:
+ tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
+ break;
+ case INDEX_op_aa64_sli_vec:
+ tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
+ break;
+ case INDEX_op_shlv_vec:
+ tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_aa64_sshl_vec:
+ tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_cmp_vec:
+ {
+ TCGCond cond = args[3];
+ AArch64Insn insn;
+
+ if (cond == TCG_COND_NE) {
+ if (const_args[2]) {
+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
+ } else {
+ tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
+ }
+ } else {
+ if (const_args[2]) {
+ insn = cmp0_insn[cond];
+ if (insn) {
+ tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
+ break;
+ }
+ tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0);
+ a2 = TCG_VEC_TMP;
+ }
+ insn = cmp_insn[cond];
+ if (insn == 0) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ insn = cmp_insn[cond];
+ tcg_debug_assert(insn != 0);
+ }
+ tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
+ }
+ }
+ break;
+
+ case INDEX_op_bitsel_vec:
+ a3 = args[3];
+ if (a0 == a3) {
+ tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1);
+ } else if (a0 == a2) {
+ tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1);
+ } else {
+ if (a0 != a1) {
+ tcg_out_mov(s, type, a0, a1);
+ }
+ tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3);
+ }
+ break;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
+ default:
+ g_assert_not_reached();
+ }
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_abs_vec:
+ case INDEX_op_not_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_bitsel_vec:
+ return 1;
+ case INDEX_op_rotli_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
+ return -1;
+ case INDEX_op_mul_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ return vece < MO_64;
+
+ default:
+ return 0;
+ }
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ va_list va;
+ TCGv_vec v0, v1, v2, t1, t2;
+ TCGArg a2;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ a2 = va_arg(va, TCGArg);
+ v2 = temp_tcgv_vec(arg_temp(a2));
+
+ switch (opc) {
+ case INDEX_op_rotli_vec:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
+ vec_gen_4(INDEX_op_aa64_sli_vec, type, vece,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
+ tcg_temp_free_vec(t1);
+ break;
+
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ /* Right shifts are negative left shifts for AArch64. */
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_neg_vec(vece, t1, v2);
+ opc = (opc == INDEX_op_shrv_vec
+ ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec);
+ vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+
+ case INDEX_op_rotlv_vec:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(vece, t1, 8 << vece);
+ tcg_gen_sub_vec(vece, t1, v2, t1);
+ /* Right shifts are negative left shifts for AArch64. */
+ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ tcg_gen_or_vec(vece, v0, v0, t1);
+ tcg_temp_free_vec(t1);
+ break;
+
+ case INDEX_op_rotrv_vec:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_neg_vec(vece, t1, v2);
+ tcg_gen_dupi_vec(vece, t2, 8 << vece);
+ tcg_gen_add_vec(vece, t2, t1, t2);
+ /* Right shifts are negative left shifts for AArch64. */
+ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+ tcg_gen_or_vec(vece, v0, t1, t2);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ va_end(va);
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
+ static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
+ static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
+ static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
+ static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
+ static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
+ static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
+ static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
+ static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
+ static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
+ static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
+ static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
+ static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
+ static const TCGTargetOpDef r_r_rAL
+ = { .args_ct_str = { "r", "r", "rAL" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef ext2
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
+ static const TCGTargetOpDef w_w_w_w
+ = { .args_ct_str = { "w", "w", "w", "w" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_sextract_i64:
+ return &r_r;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &rZ_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return &r_r_rA;
+
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_mulsh_i64:
+ return &r_r_r;
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ return &r_r_rL;
+
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i64:
+ return &r_r_ri;
+
+ case INDEX_op_clz_i32:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i64:
+ return &r_r_rAL;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &r_rA;
+
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ return &movc;
+
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_ld_i64:
+ return &r_l;
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st_i64:
+ return &lZ_l;
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return &dep;
+
+ case INDEX_op_extract2_i32:
+ case INDEX_op_extract2_i64:
+ return &ext2;
+
+ case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
+ return &add2;
+
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_aa64_sshl_vec:
+ return &w_w_w;
+ case INDEX_op_not_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_abs_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ return &w_w;
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ case INDEX_op_dupm_vec:
+ return &w_r;
+ case INDEX_op_dup_vec:
+ return &w_wr;
+ case INDEX_op_or_vec:
+ case INDEX_op_andc_vec:
+ return &w_w_wO;
+ case INDEX_op_and_vec:
+ case INDEX_op_orc_vec:
+ return &w_w_wN;
+ case INDEX_op_cmp_vec:
+ return &w_w_wZ;
+ case INDEX_op_bitsel_vec:
+ return &w_w_w_w;
+ case INDEX_op_aa64_sli_vec:
+ return &w_0_w;
+
+ default:
+ return NULL;
+ }
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
+
+ tcg_target_call_clobber_regs = -1ull;
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
+}
+
+/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */
+#define PUSH_SIZE ((30 - 19 + 1) * 8)
+
+#define FRAME_SIZE \
+ ((PUSH_SIZE \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_NLONGS * sizeof(long) \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & ~(TCG_TARGET_STACK_ALIGN - 1))
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+/* We're expecting to use a single ADDI insn. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff);
+
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ TCGReg r;
+
+ /* Push (FP, LR) and allocate space for all saved registers. */
+ tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR,
+ TCG_REG_SP, -PUSH_SIZE, 1, 1);
+
+ /* Set up frame pointer for canonical unwinding. */
+ tcg_out_movr_sp(s, TCG_TYPE_I64, TCG_REG_FP, TCG_REG_SP);
+
+ /* Store callee-preserved regs x19..x28. */
+ for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
+ int ofs = (r - TCG_REG_X19 + 2) * 8;
+ tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
+ }
+
+ /* Make stack space for TCG locals. */
+ tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
+ FRAME_SIZE - PUSH_SIZE);
+
+ /* Inform TCG about how to find TCG locals with register, offset, size. */
+ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE,
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
+
+#if !defined(CONFIG_SOFTMMU)
+ if (USE_GUEST_BASE) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
+ }
+#endif
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+ tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);
+
+ /*
+ * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
+ * and fall through to the rest of the epilogue.
+ */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0);
+
+ /* TB epilogue */
+ tb_ret_addr = s->code_ptr;
+
+ /* Remove TCG locals stack space. */
+ tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
+ FRAME_SIZE - PUSH_SIZE);
+
+ /* Restore registers x19..x28. */
+ for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
+ int ofs = (r - TCG_REG_X19 + 2) * 8;
+ tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
+ }
+
+ /* Pop (FP, LR), restore SP to previous frame. */
+ tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR,
+ TCG_REG_SP, PUSH_SIZE, 0, 1);
+ tcg_out_insn(s, 3207, RET, TCG_REG_LR);
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = NOP;
+ }
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[24];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_AARCH64
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = 0x78, /* sleb128 -8 */
+ .h.cie.return_column = TCG_REG_LR,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 28, 1, /* DW_CFA_offset, x28, -8 */
+ 0x80 + 27, 2, /* DW_CFA_offset, x27, -16 */
+ 0x80 + 26, 3, /* DW_CFA_offset, x26, -24 */
+ 0x80 + 25, 4, /* DW_CFA_offset, x25, -32 */
+ 0x80 + 24, 5, /* DW_CFA_offset, x24, -40 */
+ 0x80 + 23, 6, /* DW_CFA_offset, x23, -48 */
+ 0x80 + 22, 7, /* DW_CFA_offset, x22, -56 */
+ 0x80 + 21, 8, /* DW_CFA_offset, x21, -64 */
+ 0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */
+ 0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */
+ 0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */
+ 0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+++ /dev/null
-/*
- * Initial TCG Implementation for aarch64
- *
- * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
- * Written by Claudio Fontana
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * (at your option) any later version.
- *
- * See the COPYING file in the top-level directory for details.
- */
-
-#include "../tcg-pool.inc.c"
-#include "qemu/bitops.h"
-
-/* We're going to re-use TCGType in setting of the SF bit, which controls
- the size of the operation performed. If we know the values match, it
- makes things much cleaner. */
-QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
- "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
- "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
- "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp",
-
- "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
- "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
- "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
- "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31",
-};
-#endif /* CONFIG_DEBUG_TCG */
-
-static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
- TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
- TCG_REG_X28, /* we will reserve this for guest_base if configured */
-
- TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
- TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
- TCG_REG_X16, TCG_REG_X17,
-
- TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
- TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
-
- /* X18 reserved by system */
- /* X19 reserved for AREG0 */
- /* X29 reserved as fp */
- /* X30 reserved as temporary */
-
- TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
- TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
- /* V8 - V15 are call-saved, and skipped. */
- TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
- TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
- TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
- TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
-};
-
-static const int tcg_target_call_iarg_regs[8] = {
- TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
- TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7
-};
-static const int tcg_target_call_oarg_regs[1] = {
- TCG_REG_X0
-};
-
-#define TCG_REG_TMP TCG_REG_X30
-#define TCG_VEC_TMP TCG_REG_V31
-
-#ifndef CONFIG_SOFTMMU
-/* Note that XZR cannot be encoded in the address base register slot,
- as that actaully encodes SP. So if we need to zero-extend the guest
- address, via the address index register slot, we need to load even
- a zero guest base into a register. */
-#define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32)
-#define TCG_REG_GUEST_BASE TCG_REG_X28
-#endif
-
-static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- ptrdiff_t offset = target - code_ptr;
- if (offset == sextract64(offset, 0, 26)) {
- /* read instruction, mask away previous PC_REL26 parameter contents,
- set the proper offset, then write back the instruction. */
- *code_ptr = deposit32(*code_ptr, 0, 26, offset);
- return true;
- }
- return false;
-}
-
-static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- ptrdiff_t offset = target - code_ptr;
- if (offset == sextract64(offset, 0, 19)) {
- *code_ptr = deposit32(*code_ptr, 5, 19, offset);
- return true;
- }
- return false;
-}
-
-static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- tcg_debug_assert(addend == 0);
- switch (type) {
- case R_AARCH64_JUMP26:
- case R_AARCH64_CALL26:
- return reloc_pc26(code_ptr, (tcg_insn_unit *)value);
- case R_AARCH64_CONDBR19:
- return reloc_pc19(code_ptr, (tcg_insn_unit *)value);
- default:
- g_assert_not_reached();
- }
-}
-
-#define TCG_CT_CONST_AIMM 0x100
-#define TCG_CT_CONST_LIMM 0x200
-#define TCG_CT_CONST_ZERO 0x400
-#define TCG_CT_CONST_MONE 0x800
-#define TCG_CT_CONST_ORRI 0x1000
-#define TCG_CT_CONST_ANDI 0x2000
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r': /* general registers */
- ct->ct |= TCG_CT_REG;
- ct->u.regs |= 0xffffffffu;
- break;
- case 'w': /* advsimd registers */
- ct->ct |= TCG_CT_REG;
- ct->u.regs |= 0xffffffff00000000ull;
- break;
- case 'l': /* qemu_ld / qemu_st address, data_reg */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffffu;
-#ifdef CONFIG_SOFTMMU
- /* x0 and x1 will be overwritten when reading the tlb entry,
- and x2, and x3 for helper args, better to avoid using them. */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
-#endif
- break;
- case 'A': /* Valid for arithmetic immediate (positive or negative). */
- ct->ct |= TCG_CT_CONST_AIMM;
- break;
- case 'L': /* Valid for logical immediate. */
- ct->ct |= TCG_CT_CONST_LIMM;
- break;
- case 'M': /* minus one */
- ct->ct |= TCG_CT_CONST_MONE;
- break;
- case 'O': /* vector orr/bic immediate */
- ct->ct |= TCG_CT_CONST_ORRI;
- break;
- case 'N': /* vector orr/bic immediate, inverted */
- ct->ct |= TCG_CT_CONST_ANDI;
- break;
- case 'Z': /* zero */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* Match a constant valid for addition (12-bit, optionally shifted). */
-static inline bool is_aimm(uint64_t val)
-{
- return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
-}
-
-/* Match a constant valid for logical operations. */
-static inline bool is_limm(uint64_t val)
-{
- /* Taking a simplified view of the logical immediates for now, ignoring
- the replication that can happen across the field. Match bit patterns
- of the forms
- 0....01....1
- 0..01..10..0
- and their inverses. */
-
- /* Make things easier below, by testing the form with msb clear. */
- if ((int64_t)val < 0) {
- val = ~val;
- }
- if (val == 0) {
- return false;
- }
- val += val & -val;
- return (val & (val - 1)) == 0;
-}
-
-/* Return true if v16 is a valid 16-bit shifted immediate. */
-static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
-{
- if (v16 == (v16 & 0xff)) {
- *cmode = 0x8;
- *imm8 = v16 & 0xff;
- return true;
- } else if (v16 == (v16 & 0xff00)) {
- *cmode = 0xa;
- *imm8 = v16 >> 8;
- return true;
- }
- return false;
-}
-
-/* Return true if v32 is a valid 32-bit shifted immediate. */
-static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
-{
- if (v32 == (v32 & 0xff)) {
- *cmode = 0x0;
- *imm8 = v32 & 0xff;
- return true;
- } else if (v32 == (v32 & 0xff00)) {
- *cmode = 0x2;
- *imm8 = (v32 >> 8) & 0xff;
- return true;
- } else if (v32 == (v32 & 0xff0000)) {
- *cmode = 0x4;
- *imm8 = (v32 >> 16) & 0xff;
- return true;
- } else if (v32 == (v32 & 0xff000000)) {
- *cmode = 0x6;
- *imm8 = v32 >> 24;
- return true;
- }
- return false;
-}
-
-/* Return true if v32 is a valid 32-bit shifting ones immediate. */
-static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
-{
- if ((v32 & 0xffff00ff) == 0xff) {
- *cmode = 0xc;
- *imm8 = (v32 >> 8) & 0xff;
- return true;
- } else if ((v32 & 0xff00ffff) == 0xffff) {
- *cmode = 0xd;
- *imm8 = (v32 >> 16) & 0xff;
- return true;
- }
- return false;
-}
-
-/* Return true if v32 is a valid float32 immediate. */
-static bool is_fimm32(uint32_t v32, int *cmode, int *imm8)
-{
- if (extract32(v32, 0, 19) == 0
- && (extract32(v32, 25, 6) == 0x20
- || extract32(v32, 25, 6) == 0x1f)) {
- *cmode = 0xf;
- *imm8 = (extract32(v32, 31, 1) << 7)
- | (extract32(v32, 25, 1) << 6)
- | extract32(v32, 19, 6);
- return true;
- }
- return false;
-}
-
-/* Return true if v64 is a valid float64 immediate. */
-static bool is_fimm64(uint64_t v64, int *cmode, int *imm8)
-{
- if (extract64(v64, 0, 48) == 0
- && (extract64(v64, 54, 9) == 0x100
- || extract64(v64, 54, 9) == 0x0ff)) {
- *cmode = 0xf;
- *imm8 = (extract64(v64, 63, 1) << 7)
- | (extract64(v64, 54, 1) << 6)
- | extract64(v64, 48, 6);
- return true;
- }
- return false;
-}
-
-/*
- * Return non-zero if v32 can be formed by MOVI+ORR.
- * Place the parameters for MOVI in (cmode, imm8).
- * Return the cmode for ORR; the imm8 can be had via extraction from v32.
- */
-static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
-{
- int i;
-
- for (i = 6; i > 0; i -= 2) {
- /* Mask out one byte we can add with ORR. */
- uint32_t tmp = v32 & ~(0xffu << (i * 4));
- if (is_shimm32(tmp, cmode, imm8) ||
- is_soimm32(tmp, cmode, imm8)) {
- break;
- }
- }
- return i;
-}
-
-/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
-static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
-{
- if (v32 == deposit32(v32, 16, 16, v32)) {
- return is_shimm16(v32, cmode, imm8);
- } else {
- return is_shimm32(v32, cmode, imm8);
- }
-}
-
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct = arg_ct->ct;
-
- if (ct & TCG_CT_CONST) {
- return 1;
- }
- if (type == TCG_TYPE_I32) {
- val = (int32_t)val;
- }
- if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_MONE) && val == -1) {
- return 1;
- }
-
- switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
- case 0:
- break;
- case TCG_CT_CONST_ANDI:
- val = ~val;
- /* fallthru */
- case TCG_CT_CONST_ORRI:
- if (val == deposit64(val, 32, 32, val)) {
- int cmode, imm8;
- return is_shimm1632(val, &cmode, &imm8);
- }
- break;
- default:
- /* Both bits should not be set for the same insn. */
- g_assert_not_reached();
- }
-
- return 0;
-}
-
-enum aarch64_cond_code {
- COND_EQ = 0x0,
- COND_NE = 0x1,
- COND_CS = 0x2, /* Unsigned greater or equal */
- COND_HS = COND_CS, /* ALIAS greater or equal */
- COND_CC = 0x3, /* Unsigned less than */
- COND_LO = COND_CC, /* ALIAS Lower */
- COND_MI = 0x4, /* Negative */
- COND_PL = 0x5, /* Zero or greater */
- COND_VS = 0x6, /* Overflow */
- COND_VC = 0x7, /* No overflow */
- COND_HI = 0x8, /* Unsigned greater than */
- COND_LS = 0x9, /* Unsigned less or equal */
- COND_GE = 0xa,
- COND_LT = 0xb,
- COND_GT = 0xc,
- COND_LE = 0xd,
- COND_AL = 0xe,
- COND_NV = 0xf, /* behaves like COND_AL here */
-};
-
-static const enum aarch64_cond_code tcg_cond_to_aarch64[] = {
- [TCG_COND_EQ] = COND_EQ,
- [TCG_COND_NE] = COND_NE,
- [TCG_COND_LT] = COND_LT,
- [TCG_COND_GE] = COND_GE,
- [TCG_COND_LE] = COND_LE,
- [TCG_COND_GT] = COND_GT,
- /* unsigned */
- [TCG_COND_LTU] = COND_LO,
- [TCG_COND_GTU] = COND_HI,
- [TCG_COND_GEU] = COND_HS,
- [TCG_COND_LEU] = COND_LS,
-};
-
-typedef enum {
- LDST_ST = 0, /* store */
- LDST_LD = 1, /* load */
- LDST_LD_S_X = 2, /* load and sign-extend into Xt */
- LDST_LD_S_W = 3, /* load and sign-extend into Wt */
-} AArch64LdstType;
-
-/* We encode the format of the insn into the beginning of the name, so that
- we can have the preprocessor help "typecheck" the insn vs the output
- function. Arm didn't provide us with nice names for the formats, so we
- use the section number of the architecture reference manual in which the
- instruction group is described. */
-typedef enum {
- /* Compare and branch (immediate). */
- I3201_CBZ = 0x34000000,
- I3201_CBNZ = 0x35000000,
-
- /* Conditional branch (immediate). */
- I3202_B_C = 0x54000000,
-
- /* Unconditional branch (immediate). */
- I3206_B = 0x14000000,
- I3206_BL = 0x94000000,
-
- /* Unconditional branch (register). */
- I3207_BR = 0xd61f0000,
- I3207_BLR = 0xd63f0000,
- I3207_RET = 0xd65f0000,
-
- /* AdvSIMD load/store single structure. */
- I3303_LD1R = 0x0d40c000,
-
- /* Load literal for loading the address at pc-relative offset */
- I3305_LDR = 0x58000000,
- I3305_LDR_v64 = 0x5c000000,
- I3305_LDR_v128 = 0x9c000000,
-
- /* Load/store register. Described here as 3.3.12, but the helper
- that emits them can transform to 3.3.10 or 3.3.13. */
- I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
- I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,
- I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,
- I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,
-
- I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,
- I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,
- I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,
- I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,
-
- I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,
- I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,
-
- I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,
- I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
- I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
-
- I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
- I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
-
- I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
- I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
-
- I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
- I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
-
- I3312_TO_I3310 = 0x00200800,
- I3312_TO_I3313 = 0x01000000,
-
- /* Load/store register pair instructions. */
- I3314_LDP = 0x28400000,
- I3314_STP = 0x28000000,
-
- /* Add/subtract immediate instructions. */
- I3401_ADDI = 0x11000000,
- I3401_ADDSI = 0x31000000,
- I3401_SUBI = 0x51000000,
- I3401_SUBSI = 0x71000000,
-
- /* Bitfield instructions. */
- I3402_BFM = 0x33000000,
- I3402_SBFM = 0x13000000,
- I3402_UBFM = 0x53000000,
-
- /* Extract instruction. */
- I3403_EXTR = 0x13800000,
-
- /* Logical immediate instructions. */
- I3404_ANDI = 0x12000000,
- I3404_ORRI = 0x32000000,
- I3404_EORI = 0x52000000,
-
- /* Move wide immediate instructions. */
- I3405_MOVN = 0x12800000,
- I3405_MOVZ = 0x52800000,
- I3405_MOVK = 0x72800000,
-
- /* PC relative addressing instructions. */
- I3406_ADR = 0x10000000,
- I3406_ADRP = 0x90000000,
-
- /* Add/subtract shifted register instructions (without a shift). */
- I3502_ADD = 0x0b000000,
- I3502_ADDS = 0x2b000000,
- I3502_SUB = 0x4b000000,
- I3502_SUBS = 0x6b000000,
-
- /* Add/subtract shifted register instructions (with a shift). */
- I3502S_ADD_LSL = I3502_ADD,
-
- /* Add/subtract with carry instructions. */
- I3503_ADC = 0x1a000000,
- I3503_SBC = 0x5a000000,
-
- /* Conditional select instructions. */
- I3506_CSEL = 0x1a800000,
- I3506_CSINC = 0x1a800400,
- I3506_CSINV = 0x5a800000,
- I3506_CSNEG = 0x5a800400,
-
- /* Data-processing (1 source) instructions. */
- I3507_CLZ = 0x5ac01000,
- I3507_RBIT = 0x5ac00000,
- I3507_REV16 = 0x5ac00400,
- I3507_REV32 = 0x5ac00800,
- I3507_REV64 = 0x5ac00c00,
-
- /* Data-processing (2 source) instructions. */
- I3508_LSLV = 0x1ac02000,
- I3508_LSRV = 0x1ac02400,
- I3508_ASRV = 0x1ac02800,
- I3508_RORV = 0x1ac02c00,
- I3508_SMULH = 0x9b407c00,
- I3508_UMULH = 0x9bc07c00,
- I3508_UDIV = 0x1ac00800,
- I3508_SDIV = 0x1ac00c00,
-
- /* Data-processing (3 source) instructions. */
- I3509_MADD = 0x1b000000,
- I3509_MSUB = 0x1b008000,
-
- /* Logical shifted register instructions (without a shift). */
- I3510_AND = 0x0a000000,
- I3510_BIC = 0x0a200000,
- I3510_ORR = 0x2a000000,
- I3510_ORN = 0x2a200000,
- I3510_EOR = 0x4a000000,
- I3510_EON = 0x4a200000,
- I3510_ANDS = 0x6a000000,
-
- /* Logical shifted register instructions (with a shift). */
- I3502S_AND_LSR = I3510_AND | (1 << 22),
-
- /* AdvSIMD copy */
- I3605_DUP = 0x0e000400,
- I3605_INS = 0x4e001c00,
- I3605_UMOV = 0x0e003c00,
-
- /* AdvSIMD modified immediate */
- I3606_MOVI = 0x0f000400,
- I3606_MVNI = 0x2f000400,
- I3606_BIC = 0x2f001400,
- I3606_ORR = 0x0f001400,
-
- /* AdvSIMD shift by immediate */
- I3614_SSHR = 0x0f000400,
- I3614_SSRA = 0x0f001400,
- I3614_SHL = 0x0f005400,
- I3614_SLI = 0x2f005400,
- I3614_USHR = 0x2f000400,
- I3614_USRA = 0x2f001400,
-
- /* AdvSIMD three same. */
- I3616_ADD = 0x0e208400,
- I3616_AND = 0x0e201c00,
- I3616_BIC = 0x0e601c00,
- I3616_BIF = 0x2ee01c00,
- I3616_BIT = 0x2ea01c00,
- I3616_BSL = 0x2e601c00,
- I3616_EOR = 0x2e201c00,
- I3616_MUL = 0x0e209c00,
- I3616_ORR = 0x0ea01c00,
- I3616_ORN = 0x0ee01c00,
- I3616_SUB = 0x2e208400,
- I3616_CMGT = 0x0e203400,
- I3616_CMGE = 0x0e203c00,
- I3616_CMTST = 0x0e208c00,
- I3616_CMHI = 0x2e203400,
- I3616_CMHS = 0x2e203c00,
- I3616_CMEQ = 0x2e208c00,
- I3616_SMAX = 0x0e206400,
- I3616_SMIN = 0x0e206c00,
- I3616_SSHL = 0x0e204400,
- I3616_SQADD = 0x0e200c00,
- I3616_SQSUB = 0x0e202c00,
- I3616_UMAX = 0x2e206400,
- I3616_UMIN = 0x2e206c00,
- I3616_UQADD = 0x2e200c00,
- I3616_UQSUB = 0x2e202c00,
- I3616_USHL = 0x2e204400,
-
- /* AdvSIMD two-reg misc. */
- I3617_CMGT0 = 0x0e208800,
- I3617_CMEQ0 = 0x0e209800,
- I3617_CMLT0 = 0x0e20a800,
- I3617_CMGE0 = 0x2e208800,
- I3617_CMLE0 = 0x2e20a800,
- I3617_NOT = 0x2e205800,
- I3617_ABS = 0x0e20b800,
- I3617_NEG = 0x2e20b800,
-
- /* System instructions. */
- NOP = 0xd503201f,
- DMB_ISH = 0xd50338bf,
- DMB_LD = 0x00000100,
- DMB_ST = 0x00000200,
-} AArch64Insn;
-
-static inline uint32_t tcg_in32(TCGContext *s)
-{
- uint32_t v = *(uint32_t *)s->code_ptr;
- return v;
-}
-
-/* Emit an opcode with "type-checking" of the format. */
-#define tcg_out_insn(S, FMT, OP, ...) \
- glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
-
-static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,
- TCGReg rt, TCGReg rn, unsigned size)
-{
- tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
-}
-
-static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
- int imm19, TCGReg rt)
-{
- tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
-}
-
-static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rt, int imm19)
-{
- tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt);
-}
-
-static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn,
- TCGCond c, int imm19)
-{
- tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5);
-}
-
-static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26)
-{
- tcg_out32(s, insn | (imm26 & 0x03ffffff));
-}
-
-static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn)
-{
- tcg_out32(s, insn | rn << 5);
-}
-
-static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,
- TCGReg r1, TCGReg r2, TCGReg rn,
- tcg_target_long ofs, bool pre, bool w)
-{
- insn |= 1u << 31; /* ext */
- insn |= pre << 24;
- insn |= w << 23;
-
- tcg_debug_assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0);
- insn |= (ofs & (0x7f << 3)) << (15 - 3);
-
- tcg_out32(s, insn | r2 << 10 | rn << 5 | r1);
-}
-
-static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, uint64_t aimm)
-{
- if (aimm > 0xfff) {
- tcg_debug_assert((aimm & 0xfff) == 0);
- aimm >>= 12;
- tcg_debug_assert(aimm <= 0xfff);
- aimm |= 1 << 12; /* apply LSL 12 */
- }
- tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd);
-}
-
-/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4
- (Logical immediate). Both insn groups have N, IMMR and IMMS fields
- that feed the DecodeBitMasks pseudo function. */
-static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, int n, int immr, int imms)
-{
- tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10
- | rn << 5 | rd);
-}
-
-#define tcg_out_insn_3404 tcg_out_insn_3402
-
-static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm, int imms)
-{
- tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10
- | rn << 5 | rd);
-}
-
-/* This function is used for the Move (wide immediate) instruction group.
- Note that SHIFT is a full shift count, not the 2 bit HW field. */
-static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, uint16_t half, unsigned shift)
-{
- tcg_debug_assert((shift & ~0x30) == 0);
- tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);
-}
-
-static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,
- TCGReg rd, int64_t disp)
-{
- tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
-}
-
-/* This function is for both 3.5.2 (Add/Subtract shifted register), for
- the rare occasion when we actually want to supply a shift amount. */
-static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
- TCGType ext, TCGReg rd, TCGReg rn,
- TCGReg rm, int imm6)
-{
- tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd);
-}
-
-/* This function is for 3.5.2 (Add/subtract shifted register),
- and 3.5.10 (Logical shifted register), for the vast majorty of cases
- when we don't want to apply a shift. Thus it can also be used for
- 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */
-static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm)
-{
- tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd);
-}
-
-#define tcg_out_insn_3503 tcg_out_insn_3502
-#define tcg_out_insn_3508 tcg_out_insn_3502
-#define tcg_out_insn_3510 tcg_out_insn_3502
-
-static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c)
-{
- tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd
- | tcg_cond_to_aarch64[c] << 12);
-}
-
-static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn)
-{
- tcg_out32(s, insn | ext << 31 | rn << 5 | rd);
-}
-
-static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
-{
- tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
-}
-
-static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,
- TCGReg rd, TCGReg rn, int dst_idx, int src_idx)
-{
- /* Note that bit 11 set means general register input. Therefore
- we can handle both register sets with one function. */
- tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11)
- | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);
-}
-
-static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
- TCGReg rd, bool op, int cmode, uint8_t imm8)
-{
- tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)
- | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
-}
-
-static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
- TCGReg rd, TCGReg rn, unsigned immhb)
-{
- tcg_out32(s, insn | q << 30 | immhb << 16
- | (rn & 0x1f) << 5 | (rd & 0x1f));
-}
-
-static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,
- unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
-{
- tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16
- | (rn & 0x1f) << 5 | (rd & 0x1f));
-}
-
-static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
- unsigned size, TCGReg rd, TCGReg rn)
-{
- tcg_out32(s, insn | q << 30 | (size << 22)
- | (rn & 0x1f) << 5 | (rd & 0x1f));
-}
-
-static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
- TCGReg rd, TCGReg base, TCGType ext,
- TCGReg regoff)
-{
- /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
- tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
- 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
-}
-
-static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
- TCGReg rd, TCGReg rn, intptr_t offset)
-{
- tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
-}
-
-static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,
- TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
-{
- /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
- tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10
- | rn << 5 | (rd & 0x1f));
-}
-
-/* Register to register move using ORR (shifted register with no shift). */
-static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
-{
- tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
-}
-
-/* Register to register move using ADDI (move to/from SP). */
-static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
-}
-
-/* This function is used for the Logical (immediate) instruction group.
- The value of LIMM must satisfy IS_LIMM. See the comment above about
- only supporting simplified logical immediates. */
-static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, uint64_t limm)
-{
- unsigned h, l, r, c;
-
- tcg_debug_assert(is_limm(limm));
-
- h = clz64(limm);
- l = ctz64(limm);
- if (l == 0) {
- r = 0; /* form 0....01....1 */
- c = ctz64(~limm) - 1;
- if (h == 0) {
- r = clz64(~limm); /* form 1..10..01..1 */
- c += r;
- }
- } else {
- r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
- c = r - h - 1;
- }
- if (ext == TCG_TYPE_I32) {
- r &= 31;
- c &= 31;
- }
-
- tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
-}
-
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg rd, tcg_target_long v64)
-{
- bool q = type == TCG_TYPE_V128;
- int cmode, imm8, i;
-
- /* Test all bytes equal first. */
- if (v64 == dup_const(MO_8, v64)) {
- imm8 = (uint8_t)v64;
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);
- return;
- }
-
- /*
- * Test all bytes 0x00 or 0xff second. This can match cases that
- * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
- */
- for (i = imm8 = 0; i < 8; i++) {
- uint8_t byte = v64 >> (i * 8);
- if (byte == 0xff) {
- imm8 |= 1 << i;
- } else if (byte != 0) {
- goto fail_bytes;
- }
- }
- tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8);
- return;
- fail_bytes:
-
- /*
- * Tests for various replications. For each element width, if we
- * cannot find an expansion there's no point checking a larger
- * width because we already know by replication it cannot match.
- */
- if (v64 == dup_const(MO_16, v64)) {
- uint16_t v16 = v64;
-
- if (is_shimm16(v16, &cmode, &imm8)) {
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
- return;
- }
- if (is_shimm16(~v16, &cmode, &imm8)) {
- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
- return;
- }
-
- /*
- * Otherwise, all remaining constants can be loaded in two insns:
- * rd = v16 & 0xff, rd |= v16 & 0xff00.
- */
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);
- tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);
- return;
- } else if (v64 == dup_const(MO_32, v64)) {
- uint32_t v32 = v64;
- uint32_t n32 = ~v32;
-
- if (is_shimm32(v32, &cmode, &imm8) ||
- is_soimm32(v32, &cmode, &imm8) ||
- is_fimm32(v32, &cmode, &imm8)) {
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
- return;
- }
- if (is_shimm32(n32, &cmode, &imm8) ||
- is_soimm32(n32, &cmode, &imm8)) {
- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
- return;
- }
-
- /*
- * Restrict the set of constants to those we can load with
- * two instructions. Others we load from the pool.
- */
- i = is_shimm32_pair(v32, &cmode, &imm8);
- if (i) {
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
- tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8));
- return;
- }
- i = is_shimm32_pair(n32, &cmode, &imm8);
- if (i) {
- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
- tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8));
- return;
- }
- } else if (is_fimm64(v64, &cmode, &imm8)) {
- tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8);
- return;
- }
-
- /*
- * As a last resort, load from the constant pool. Sadly there
- * is no LD1R (literal), so store the full 16-byte vector.
- */
- if (type == TCG_TYPE_V128) {
- new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
- tcg_out_insn(s, 3305, LDR_v128, 0, rd);
- } else {
- new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);
- tcg_out_insn(s, 3305, LDR_v64, 0, rd);
- }
-}
-
-static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
- TCGReg rd, TCGReg rs)
-{
- int is_q = type - TCG_TYPE_V64;
- tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0);
- return true;
-}
-
-static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
- TCGReg r, TCGReg base, intptr_t offset)
-{
- TCGReg temp = TCG_REG_TMP;
-
- if (offset < -0xffffff || offset > 0xffffff) {
- tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);
- tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);
- base = temp;
- } else {
- AArch64Insn add_insn = I3401_ADDI;
-
- if (offset < 0) {
- add_insn = I3401_SUBI;
- offset = -offset;
- }
- if (offset & 0xfff000) {
- tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
- base = temp;
- }
- if (offset & 0xfff) {
- tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
- base = temp;
- }
- }
- tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);
- return true;
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
- tcg_target_long value)
-{
- tcg_target_long svalue = value;
- tcg_target_long ivalue = ~value;
- tcg_target_long t0, t1, t2;
- int s0, s1;
- AArch64Insn opc;
-
- switch (type) {
- case TCG_TYPE_I32:
- case TCG_TYPE_I64:
- tcg_debug_assert(rd < 32);
- break;
-
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- tcg_debug_assert(rd >= 32);
- tcg_out_dupi_vec(s, type, rd, value);
- return;
-
- default:
- g_assert_not_reached();
- }
-
- /* For 32-bit values, discard potential garbage in value. For 64-bit
- values within [2**31, 2**32-1], we can create smaller sequences by
- interpreting this as a negative 32-bit number, while ensuring that
- the high 32 bits are cleared by setting SF=0. */
- if (type == TCG_TYPE_I32 || (value & ~0xffffffffull) == 0) {
- svalue = (int32_t)value;
- value = (uint32_t)value;
- ivalue = (uint32_t)ivalue;
- type = TCG_TYPE_I32;
- }
-
- /* Speed things up by handling the common case of small positive
- and negative values specially. */
- if ((value & ~0xffffull) == 0) {
- tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0);
- return;
- } else if ((ivalue & ~0xffffull) == 0) {
- tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0);
- return;
- }
-
- /* Check for bitfield immediates. For the benefit of 32-bit quantities,
- use the sign-extended value. That lets us match rotated values such
- as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */
- if (is_limm(svalue)) {
- tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue);
- return;
- }
-
- /* Look for host pointer values within 4G of the PC. This happens
- often when loading pointers to QEMU's own data structures. */
- if (type == TCG_TYPE_I64) {
- tcg_target_long disp = value - (intptr_t)s->code_ptr;
- if (disp == sextract64(disp, 0, 21)) {
- tcg_out_insn(s, 3406, ADR, rd, disp);
- return;
- }
- disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
- if (disp == sextract64(disp, 0, 21)) {
- tcg_out_insn(s, 3406, ADRP, rd, disp);
- if (value & 0xfff) {
- tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
- }
- return;
- }
- }
-
- /* Would it take fewer insns to begin with MOVN? */
- if (ctpop64(value) >= 32) {
- t0 = ivalue;
- opc = I3405_MOVN;
- } else {
- t0 = value;
- opc = I3405_MOVZ;
- }
- s0 = ctz64(t0) & (63 & -16);
- t1 = t0 & ~(0xffffUL << s0);
- s1 = ctz64(t1) & (63 & -16);
- t2 = t1 & ~(0xffffUL << s1);
- if (t2 == 0) {
- tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0);
- if (t1 != 0) {
- tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1);
- }
- return;
- }
-
- /* For more than 2 insns, dump it into the constant pool. */
- new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0);
- tcg_out_insn(s, 3305, LDR, 0, rd);
-}
-
-/* Define something more legible for general use. */
-#define tcg_out_ldst_r tcg_out_insn_3310
-
-static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
- TCGReg rn, intptr_t offset, int lgsize)
-{
- /* If the offset is naturally aligned and in range, then we can
- use the scaled uimm12 encoding */
- if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {
- uintptr_t scaled_uimm = offset >> lgsize;
- if (scaled_uimm <= 0xfff) {
- tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);
- return;
- }
- }
-
- /* Small signed offsets can use the unscaled encoding. */
- if (offset >= -256 && offset < 256) {
- tcg_out_insn_3312(s, insn, rd, rn, offset);
- return;
- }
-
- /* Worst-case scenario, move offset to temp register, use reg offset. */
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
- tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
-}
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
-{
- if (ret == arg) {
- return true;
- }
- switch (type) {
- case TCG_TYPE_I32:
- case TCG_TYPE_I64:
- if (ret < 32 && arg < 32) {
- tcg_out_movr(s, type, ret, arg);
- break;
- } else if (ret < 32) {
- tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
- break;
- } else if (arg < 32) {
- tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
- break;
- }
- /* FALLTHRU */
-
- case TCG_TYPE_V64:
- tcg_debug_assert(ret >= 32 && arg >= 32);
- tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
- break;
- case TCG_TYPE_V128:
- tcg_debug_assert(ret >= 32 && arg >= 32);
- tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
- break;
-
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg base, intptr_t ofs)
-{
- AArch64Insn insn;
- int lgsz;
-
- switch (type) {
- case TCG_TYPE_I32:
- insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS);
- lgsz = 2;
- break;
- case TCG_TYPE_I64:
- insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD);
- lgsz = 3;
- break;
- case TCG_TYPE_V64:
- insn = I3312_LDRVD;
- lgsz = 3;
- break;
- case TCG_TYPE_V128:
- insn = I3312_LDRVQ;
- lgsz = 4;
- break;
- default:
- g_assert_not_reached();
- }
- tcg_out_ldst(s, insn, ret, base, ofs, lgsz);
-}
-
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
- TCGReg base, intptr_t ofs)
-{
- AArch64Insn insn;
- int lgsz;
-
- switch (type) {
- case TCG_TYPE_I32:
- insn = (src < 32 ? I3312_STRW : I3312_STRVS);
- lgsz = 2;
- break;
- case TCG_TYPE_I64:
- insn = (src < 32 ? I3312_STRX : I3312_STRVD);
- lgsz = 3;
- break;
- case TCG_TYPE_V64:
- insn = I3312_STRVD;
- lgsz = 3;
- break;
- case TCG_TYPE_V128:
- insn = I3312_STRVQ;
- lgsz = 4;
- break;
- default:
- g_assert_not_reached();
- }
- tcg_out_ldst(s, insn, src, base, ofs, lgsz);
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- if (type <= TCG_TYPE_I64 && val == 0) {
- tcg_out_st(s, type, TCG_REG_XZR, base, ofs);
- return true;
- }
- return false;
-}
-
-static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
- TCGReg rn, unsigned int a, unsigned int b)
-{
- tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b);
-}
-
-static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
- TCGReg rn, unsigned int a, unsigned int b)
-{
- tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b);
-}
-
-static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,
- TCGReg rn, unsigned int a, unsigned int b)
-{
- tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b);
-}
-
-static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,
- TCGReg rn, TCGReg rm, unsigned int a)
-{
- tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);
-}
-
-static inline void tcg_out_shl(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int m)
-{
- int bits = ext ? 64 : 32;
- int max = bits - 1;
- tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max));
-}
-
-static inline void tcg_out_shr(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int m)
-{
- int max = ext ? 63 : 31;
- tcg_out_ubfm(s, ext, rd, rn, m & max, max);
-}
-
-static inline void tcg_out_sar(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int m)
-{
- int max = ext ? 63 : 31;
- tcg_out_sbfm(s, ext, rd, rn, m & max, max);
-}
-
-static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int m)
-{
- int max = ext ? 63 : 31;
- tcg_out_extr(s, ext, rd, rn, rn, m & max);
-}
-
-static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int m)
-{
- int bits = ext ? 64 : 32;
- int max = bits - 1;
- tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
-}
-
-static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd,
- TCGReg rn, unsigned lsb, unsigned width)
-{
- unsigned size = ext ? 64 : 32;
- unsigned a = (size - lsb) & (size - 1);
- unsigned b = width - 1;
- tcg_out_bfm(s, ext, rd, rn, a, b);
-}
-
-static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
- tcg_target_long b, bool const_b)
-{
- if (const_b) {
- /* Using CMP or CMN aliases. */
- if (b >= 0) {
- tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b);
- } else {
- tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b);
- }
- } else {
- /* Using CMP alias SUBS wzr, Wn, Wm */
- tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b);
- }
-}
-
-static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
-{
- ptrdiff_t offset = target - s->code_ptr;
- tcg_debug_assert(offset == sextract64(offset, 0, 26));
- tcg_out_insn(s, 3206, B, offset);
-}
-
-static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target)
-{
- ptrdiff_t offset = target - s->code_ptr;
- if (offset == sextract64(offset, 0, 26)) {
- tcg_out_insn(s, 3206, BL, offset);
- } else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
- tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
- }
-}
-
-static inline void tcg_out_callr(TCGContext *s, TCGReg reg)
-{
- tcg_out_insn(s, 3207, BLR, reg);
-}
-
-static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
-{
- ptrdiff_t offset = target - s->code_ptr;
- if (offset == sextract64(offset, 0, 26)) {
- tcg_out_insn(s, 3206, BL, offset);
- } else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
- tcg_out_callr(s, TCG_REG_TMP);
- }
-}
-
-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
- uintptr_t addr)
-{
- tcg_insn_unit i1, i2;
- TCGType rt = TCG_TYPE_I64;
- TCGReg rd = TCG_REG_TMP;
- uint64_t pair;
-
- ptrdiff_t offset = addr - jmp_addr;
-
- if (offset == sextract64(offset, 0, 26)) {
- i1 = I3206_B | ((offset >> 2) & 0x3ffffff);
- i2 = NOP;
- } else {
- offset = (addr >> 12) - (jmp_addr >> 12);
-
- /* patch ADRP */
- i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd;
- /* patch ADDI */
- i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd;
- }
- pair = (uint64_t)i2 << 32 | i1;
- atomic_set((uint64_t *)jmp_addr, pair);
- flush_icache_range(jmp_addr, jmp_addr + 8);
-}
-
-static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l)
-{
- if (!l->has_value) {
- tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0);
- tcg_out_insn(s, 3206, B, 0);
- } else {
- tcg_out_goto(s, l->u.value_ptr);
- }
-}
-
-static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
- TCGArg b, bool b_const, TCGLabel *l)
-{
- intptr_t offset;
- bool need_cmp;
-
- if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) {
- need_cmp = false;
- } else {
- need_cmp = true;
- tcg_out_cmp(s, ext, a, b, b_const);
- }
-
- if (!l->has_value) {
- tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
- offset = tcg_in32(s) >> 5;
- } else {
- offset = l->u.value_ptr - s->code_ptr;
- tcg_debug_assert(offset == sextract64(offset, 0, 19));
- }
-
- if (need_cmp) {
- tcg_out_insn(s, 3202, B_C, c, offset);
- } else if (c == TCG_COND_EQ) {
- tcg_out_insn(s, 3201, CBZ, ext, a, offset);
- } else {
- tcg_out_insn(s, 3201, CBNZ, ext, a, offset);
- }
-}
-
-static inline void tcg_out_rev64(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV64, TCG_TYPE_I64, rd, rn);
-}
-
-static inline void tcg_out_rev32(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV32, TCG_TYPE_I32, rd, rn);
-}
-
-static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);
-}
-
-static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,
- TCGReg rd, TCGReg rn)
-{
- /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
- int bits = (8 << s_bits) - 1;
- tcg_out_sbfm(s, ext, rd, rn, 0, bits);
-}
-
-static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,
- TCGReg rd, TCGReg rn)
-{
- /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
- int bits = (8 << s_bits) - 1;
- tcg_out_ubfm(s, 0, rd, rn, 0, bits);
-}
-
-static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
- TCGReg rn, int64_t aimm)
-{
- if (aimm >= 0) {
- tcg_out_insn(s, 3401, ADDI, ext, rd, rn, aimm);
- } else {
- tcg_out_insn(s, 3401, SUBI, ext, rd, rn, -aimm);
- }
-}
-
-static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl,
- TCGReg rh, TCGReg al, TCGReg ah,
- tcg_target_long bl, tcg_target_long bh,
- bool const_bl, bool const_bh, bool sub)
-{
- TCGReg orig_rl = rl;
- AArch64Insn insn;
-
- if (rl == ah || (!const_bh && rl == bh)) {
- rl = TCG_REG_TMP;
- }
-
- if (const_bl) {
- insn = I3401_ADDSI;
- if ((bl < 0) ^ sub) {
- insn = I3401_SUBSI;
- bl = -bl;
- }
- if (unlikely(al == TCG_REG_XZR)) {
- /* ??? We want to allow al to be zero for the benefit of
- negation via subtraction. However, that leaves open the
- possibility of adding 0+const in the low part, and the
- immediate add instructions encode XSP not XZR. Don't try
- anything more elaborate here than loading another zero. */
- al = TCG_REG_TMP;
- tcg_out_movi(s, ext, al, 0);
- }
- tcg_out_insn_3401(s, insn, ext, rl, al, bl);
- } else {
- tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);
- }
-
- insn = I3503_ADC;
- if (const_bh) {
- /* Note that the only two constants we support are 0 and -1, and
- that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */
- if ((bh != 0) ^ sub) {
- insn = I3503_SBC;
- }
- bh = TCG_REG_XZR;
- } else if (sub) {
- insn = I3503_SBC;
- }
- tcg_out_insn_3503(s, insn, ext, rh, ah, bh);
-
- tcg_out_mov(s, ext, orig_rl, rl);
-}
-
-static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- static const uint32_t sync[] = {
- [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST,
- [TCG_MO_ST_ST] = DMB_ISH | DMB_ST,
- [TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
- [TCG_MO_LD_ST] = DMB_ISH | DMB_LD,
- [TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
- };
- tcg_out32(s, sync[a0 & TCG_MO_ALL]);
-}
-
-static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
- TCGReg a0, TCGArg b, bool const_b, bool is_ctz)
-{
- TCGReg a1 = a0;
- if (is_ctz) {
- a1 = TCG_REG_TMP;
- tcg_out_insn(s, 3507, RBIT, ext, a1, a0);
- }
- if (const_b && b == (ext ? 64 : 32)) {
- tcg_out_insn(s, 3507, CLZ, ext, d, a1);
- } else {
- AArch64Insn sel = I3506_CSEL;
-
- tcg_out_cmp(s, ext, a0, 0, 1);
- tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1);
-
- if (const_b) {
- if (b == -1) {
- b = TCG_REG_XZR;
- sel = I3506_CSINV;
- } else if (b == 0) {
- b = TCG_REG_XZR;
- } else {
- tcg_out_movi(s, ext, d, b);
- b = d;
- }
- }
- tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE);
- }
-}
-
-#ifdef CONFIG_SOFTMMU
-#include "../tcg-ldst.inc.c"
-
-/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * TCGMemOpIdx oi, uintptr_t ra)
- */
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
-};
-
-/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, TCGMemOpIdx oi,
- * uintptr_t ra)
- */
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-
-static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
-{
- ptrdiff_t offset = tcg_pcrel_diff(s, target);
- tcg_debug_assert(offset == sextract64(offset, 0, 21));
- tcg_out_insn(s, 3406, ADR, rd, offset);
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- MemOp size = opc & MO_SIZE;
-
- if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
- tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi);
- tcg_out_adr(s, TCG_REG_X3, lb->raddr);
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
- if (opc & MO_SIGN) {
- tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0);
- } else {
- tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0);
- }
-
- tcg_out_goto(s, lb->raddr);
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- MemOp size = opc & MO_SIZE;
-
- if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
- tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
- tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi);
- tcg_out_adr(s, TCG_REG_X4, lb->raddr);
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
- tcg_out_goto(s, lb->raddr);
- return true;
-}
-
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
- TCGType ext, TCGReg data_reg, TCGReg addr_reg,
- tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->type = ext;
- label->datalo_reg = data_reg;
- label->addrlo_reg = addr_reg;
- label->raddr = raddr;
- label->label_ptr[0] = label_ptr;
-}
-
-/* We expect to use a 7-bit scaled negative offset from ENV. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512);
-
-/* These offsets are built into the LDP below. */
-QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
-QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);
-
-/* Load and compare a TLB entry, emitting the conditional jump to the
- slow path for the failure case, which will be patched later when finalizing
- the slow path. Generated code returns the host addend in X1,
- clobbers X0,X2,X3,TMP. */
-static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
- tcg_insn_unit **label_ptr, int mem_index,
- bool is_read)
-{
- unsigned a_bits = get_alignment_bits(opc);
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_mask = (1u << a_bits) - 1;
- unsigned s_mask = (1u << s_bits) - 1;
- TCGReg x3;
- TCGType mask_type;
- uint64_t compare_mask;
-
- mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32
- ? TCG_TYPE_I64 : TCG_TYPE_I32);
-
- /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */
- tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0,
- TLB_MASK_TABLE_OFS(mem_index), 1, 0);
-
- /* Extract the TLB index from the address into X0. */
- tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64,
- TCG_REG_X0, TCG_REG_X0, addr_reg,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
-
- /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1. */
- tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0);
-
- /* Load the tlb comparator into X0, and the fast path addend into X1. */
- tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read
- ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write));
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1,
- offsetof(CPUTLBEntry, addend));
-
- /* For aligned accesses, we check the first byte and include the alignment
- bits within the address. For unaligned access, we check that we don't
- cross pages using the address of the last byte of the access. */
- if (a_bits >= s_bits) {
- x3 = addr_reg;
- } else {
- tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS == 64,
- TCG_REG_X3, addr_reg, s_mask - a_mask);
- x3 = TCG_REG_X3;
- }
- compare_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
-
- /* Store the page mask part of the address into X3. */
- tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64,
- TCG_REG_X3, x3, compare_mask);
-
- /* Perform the address comparison. */
- tcg_out_cmp(s, TARGET_LONG_BITS == 64, TCG_REG_X0, TCG_REG_X3, 0);
-
- /* If not equal, we jump to the slow path. */
- *label_ptr = s->code_ptr;
- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
-}
-
-#endif /* CONFIG_SOFTMMU */
-
-static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
- TCGReg data_r, TCGReg addr_r,
- TCGType otype, TCGReg off_r)
-{
- const MemOp bswap = memop & MO_BSWAP;
-
- switch (memop & MO_SSIZE) {
- case MO_UB:
- tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
- break;
- case MO_SB:
- tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
- data_r, addr_r, otype, off_r);
- break;
- case MO_UW:
- tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
- if (bswap) {
- tcg_out_rev16(s, data_r, data_r);
- }
- break;
- case MO_SW:
- if (bswap) {
- tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
- tcg_out_rev16(s, data_r, data_r);
- tcg_out_sxt(s, ext, MO_16, data_r, data_r);
- } else {
- tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
- data_r, addr_r, otype, off_r);
- }
- break;
- case MO_UL:
- tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
- if (bswap) {
- tcg_out_rev32(s, data_r, data_r);
- }
- break;
- case MO_SL:
- if (bswap) {
- tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
- tcg_out_rev32(s, data_r, data_r);
- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);
- } else {
- tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
- }
- break;
- case MO_Q:
- tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
- if (bswap) {
- tcg_out_rev64(s, data_r, data_r);
- }
- break;
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
- TCGReg data_r, TCGReg addr_r,
- TCGType otype, TCGReg off_r)
-{
- const MemOp bswap = memop & MO_BSWAP;
-
- switch (memop & MO_SIZE) {
- case MO_8:
- tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
- break;
- case MO_16:
- if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev16(s, TCG_REG_TMP, data_r);
- data_r = TCG_REG_TMP;
- }
- tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
- break;
- case MO_32:
- if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev32(s, TCG_REG_TMP, data_r);
- data_r = TCG_REG_TMP;
- }
- tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
- break;
- case MO_64:
- if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev64(s, TCG_REG_TMP, data_r);
- data_r = TCG_REG_TMP;
- }
- tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
- break;
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi, TCGType ext)
-{
- MemOp memop = get_memop(oi);
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
-#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
- tcg_insn_unit *label_ptr;
-
- tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- TCG_REG_X1, otype, addr_reg);
- add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
- s->code_ptr, label_ptr);
-#else /* !CONFIG_SOFTMMU */
- if (USE_GUEST_BASE) {
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- TCG_REG_GUEST_BASE, otype, addr_reg);
- } else {
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
- }
-#endif /* CONFIG_SOFTMMU */
-}
-
-static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
-{
- MemOp memop = get_memop(oi);
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
-#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
- tcg_insn_unit *label_ptr;
-
- tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
- tcg_out_qemu_st_direct(s, memop, data_reg,
- TCG_REG_X1, otype, addr_reg);
- add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
- data_reg, addr_reg, s->code_ptr, label_ptr);
-#else /* !CONFIG_SOFTMMU */
- if (USE_GUEST_BASE) {
- tcg_out_qemu_st_direct(s, memop, data_reg,
- TCG_REG_GUEST_BASE, otype, addr_reg);
- } else {
- tcg_out_qemu_st_direct(s, memop, data_reg,
- addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
- }
-#endif /* CONFIG_SOFTMMU */
-}
-
-static tcg_insn_unit *tb_ret_addr;
-
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg args[TCG_MAX_OP_ARGS],
- const int const_args[TCG_MAX_OP_ARGS])
-{
- /* 99% of the time, we can signal the use of extension registers
- by looking to see if the opcode handles 64-bit data. */
- TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
-
- /* Hoist the loads of the most common arguments. */
- TCGArg a0 = args[0];
- TCGArg a1 = args[1];
- TCGArg a2 = args[2];
- int c2 = const_args[2];
-
- /* Some operands are defined with "rZ" constraint, a register or
- the zero register. These need not actually test args[I] == 0. */
-#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
-
- switch (opc) {
- case INDEX_op_exit_tb:
- /* Reuse the zeroing that exists for goto_ptr. */
- if (a0 == 0) {
- tcg_out_goto_long(s, s->code_gen_epilogue);
- } else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
- tcg_out_goto_long(s, tb_ret_addr);
- }
- break;
-
- case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset != NULL) {
- /* TCG_TARGET_HAS_direct_jump */
- /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic
- write can be used to patch the target address. */
- if ((uintptr_t)s->code_ptr & 7) {
- tcg_out32(s, NOP);
- }
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- /* actual branch destination will be patched by
- tb_target_set_jmp_target later. */
- tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0);
- tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0);
- } else {
- /* !TCG_TARGET_HAS_direct_jump */
- tcg_debug_assert(s->tb_jmp_target_addr != NULL);
- intptr_t offset = tcg_pcrel_diff(s, (s->tb_jmp_target_addr + a0)) >> 2;
- tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP);
- }
- tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
- set_jmp_reset_offset(s, a0);
- break;
-
- case INDEX_op_goto_ptr:
- tcg_out_insn(s, 3207, BR, a0);
- break;
-
- case INDEX_op_br:
- tcg_out_goto_label(s, arg_label(a0));
- break;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
- break;
- case INDEX_op_ld8s_i32:
- tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);
- break;
- case INDEX_op_ld8s_i64:
- tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);
- break;
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1);
- break;
- case INDEX_op_ld16s_i32:
- tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1);
- break;
- case INDEX_op_ld16s_i64:
- tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1);
- break;
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2);
- break;
- case INDEX_op_ld32s_i64:
- tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2);
- break;
- case INDEX_op_ld_i64:
- tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3);
- break;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
- break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
- break;
-
- case INDEX_op_add_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_add_i64:
- if (c2) {
- tcg_out_addsubi(s, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_sub_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_sub_i64:
- if (c2) {
- tcg_out_addsubi(s, ext, a0, a1, -a2);
- } else {
- tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_neg_i64:
- case INDEX_op_neg_i32:
- tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
- break;
-
- case INDEX_op_and_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_and_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_andc_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_andc_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
- } else {
- tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_or_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_or_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_orc_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_orc_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2);
- } else {
- tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_xor_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_xor_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_eqv_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_eqv_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2);
- } else {
- tcg_out_insn(s, 3510, EON, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_not_i64:
- case INDEX_op_not_i32:
- tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
- break;
-
- case INDEX_op_mul_i64:
- case INDEX_op_mul_i32:
- tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR);
- break;
-
- case INDEX_op_div_i64:
- case INDEX_op_div_i32:
- tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2);
- break;
- case INDEX_op_divu_i64:
- case INDEX_op_divu_i32:
- tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2);
- break;
-
- case INDEX_op_rem_i64:
- case INDEX_op_rem_i32:
- tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2);
- tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
- break;
- case INDEX_op_remu_i64:
- case INDEX_op_remu_i32:
- tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2);
- tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
- break;
-
- case INDEX_op_shl_i64:
- case INDEX_op_shl_i32:
- if (c2) {
- tcg_out_shl(s, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_shr_i64:
- case INDEX_op_shr_i32:
- if (c2) {
- tcg_out_shr(s, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_sar_i64:
- case INDEX_op_sar_i32:
- if (c2) {
- tcg_out_sar(s, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_rotr_i64:
- case INDEX_op_rotr_i32:
- if (c2) {
- tcg_out_rotr(s, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2);
- }
- break;
-
- case INDEX_op_rotl_i64:
- case INDEX_op_rotl_i32:
- if (c2) {
- tcg_out_rotl(s, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2);
- tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP);
- }
- break;
-
- case INDEX_op_clz_i64:
- case INDEX_op_clz_i32:
- tcg_out_cltz(s, ext, a0, a1, a2, c2, false);
- break;
- case INDEX_op_ctz_i64:
- case INDEX_op_ctz_i32:
- tcg_out_cltz(s, ext, a0, a1, a2, c2, true);
- break;
-
- case INDEX_op_brcond_i32:
- a1 = (int32_t)a1;
- /* FALLTHRU */
- case INDEX_op_brcond_i64:
- tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3]));
- break;
-
- case INDEX_op_setcond_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_setcond_i64:
- tcg_out_cmp(s, ext, a1, a2, c2);
- /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */
- tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR,
- TCG_REG_XZR, tcg_invert_cond(args[3]));
- break;
-
- case INDEX_op_movcond_i32:
- a2 = (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_movcond_i64:
- tcg_out_cmp(s, ext, a1, a2, c2);
- tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
- break;
-
- case INDEX_op_qemu_ld_i32:
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, a0, a1, a2, ext);
- break;
- case INDEX_op_qemu_st_i32:
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, REG0(0), a1, a2);
- break;
-
- case INDEX_op_bswap64_i64:
- tcg_out_rev64(s, a0, a1);
- break;
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap32_i32:
- tcg_out_rev32(s, a0, a1);
- break;
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap16_i32:
- tcg_out_rev16(s, a0, a1);
- break;
-
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext8s_i32:
- tcg_out_sxt(s, ext, MO_8, a0, a1);
- break;
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext16s_i32:
- tcg_out_sxt(s, ext, MO_16, a0, a1);
- break;
- case INDEX_op_ext_i32_i64:
- case INDEX_op_ext32s_i64:
- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);
- break;
- case INDEX_op_ext8u_i64:
- case INDEX_op_ext8u_i32:
- tcg_out_uxt(s, MO_8, a0, a1);
- break;
- case INDEX_op_ext16u_i64:
- case INDEX_op_ext16u_i32:
- tcg_out_uxt(s, MO_16, a0, a1);
- break;
- case INDEX_op_extu_i32_i64:
- case INDEX_op_ext32u_i64:
- tcg_out_movr(s, TCG_TYPE_I32, a0, a1);
- break;
-
- case INDEX_op_deposit_i64:
- case INDEX_op_deposit_i32:
- tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
- break;
-
- case INDEX_op_extract_i64:
- case INDEX_op_extract_i32:
- tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
- break;
-
- case INDEX_op_sextract_i64:
- case INDEX_op_sextract_i32:
- tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
- break;
-
- case INDEX_op_extract2_i64:
- case INDEX_op_extract2_i32:
- tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
- break;
-
- case INDEX_op_add2_i32:
- tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
- (int32_t)args[4], args[5], const_args[4],
- const_args[5], false);
- break;
- case INDEX_op_add2_i64:
- tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
- args[5], const_args[4], const_args[5], false);
- break;
- case INDEX_op_sub2_i32:
- tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
- (int32_t)args[4], args[5], const_args[4],
- const_args[5], true);
- break;
- case INDEX_op_sub2_i64:
- tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
- args[5], const_args[4], const_args[5], true);
- break;
-
- case INDEX_op_muluh_i64:
- tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
- break;
- case INDEX_op_mulsh_i64:
- tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, a0);
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- g_assert_not_reached();
- }
-
-#undef REG0
-}
-
-static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
- unsigned vecl, unsigned vece,
- const TCGArg *args, const int *const_args)
-{
- static const AArch64Insn cmp_insn[16] = {
- [TCG_COND_EQ] = I3616_CMEQ,
- [TCG_COND_GT] = I3616_CMGT,
- [TCG_COND_GE] = I3616_CMGE,
- [TCG_COND_GTU] = I3616_CMHI,
- [TCG_COND_GEU] = I3616_CMHS,
- };
- static const AArch64Insn cmp0_insn[16] = {
- [TCG_COND_EQ] = I3617_CMEQ0,
- [TCG_COND_GT] = I3617_CMGT0,
- [TCG_COND_GE] = I3617_CMGE0,
- [TCG_COND_LT] = I3617_CMLT0,
- [TCG_COND_LE] = I3617_CMLE0,
- };
-
- TCGType type = vecl + TCG_TYPE_V64;
- unsigned is_q = vecl;
- TCGArg a0, a1, a2, a3;
- int cmode, imm8;
-
- a0 = args[0];
- a1 = args[1];
- a2 = args[2];
-
- switch (opc) {
- case INDEX_op_ld_vec:
- tcg_out_ld(s, type, a0, a1, a2);
- break;
- case INDEX_op_st_vec:
- tcg_out_st(s, type, a0, a1, a2);
- break;
- case INDEX_op_dupm_vec:
- tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
- break;
- case INDEX_op_add_vec:
- tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_sub_vec:
- tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_mul_vec:
- tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_neg_vec:
- tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
- break;
- case INDEX_op_abs_vec:
- tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
- break;
- case INDEX_op_and_vec:
- if (const_args[2]) {
- is_shimm1632(~a2, &cmode, &imm8);
- if (a0 == a1) {
- tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
- return;
- }
- tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
- a2 = a0;
- }
- tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
- break;
- case INDEX_op_or_vec:
- if (const_args[2]) {
- is_shimm1632(a2, &cmode, &imm8);
- if (a0 == a1) {
- tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
- return;
- }
- tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
- a2 = a0;
- }
- tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);
- break;
- case INDEX_op_andc_vec:
- if (const_args[2]) {
- is_shimm1632(a2, &cmode, &imm8);
- if (a0 == a1) {
- tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
- return;
- }
- tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
- a2 = a0;
- }
- tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);
- break;
- case INDEX_op_orc_vec:
- if (const_args[2]) {
- is_shimm1632(~a2, &cmode, &imm8);
- if (a0 == a1) {
- tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
- return;
- }
- tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
- a2 = a0;
- }
- tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
- break;
- case INDEX_op_xor_vec:
- tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
- break;
- case INDEX_op_ssadd_vec:
- tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_sssub_vec:
- tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_usadd_vec:
- tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_ussub_vec:
- tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_smax_vec:
- tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_smin_vec:
- tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_umax_vec:
- tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_umin_vec:
- tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_not_vec:
- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
- break;
- case INDEX_op_shli_vec:
- tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
- break;
- case INDEX_op_shri_vec:
- tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
- break;
- case INDEX_op_sari_vec:
- tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
- break;
- case INDEX_op_aa64_sli_vec:
- tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
- break;
- case INDEX_op_shlv_vec:
- tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_aa64_sshl_vec:
- tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
- break;
- case INDEX_op_cmp_vec:
- {
- TCGCond cond = args[3];
- AArch64Insn insn;
-
- if (cond == TCG_COND_NE) {
- if (const_args[2]) {
- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
- } else {
- tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
- }
- } else {
- if (const_args[2]) {
- insn = cmp0_insn[cond];
- if (insn) {
- tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
- break;
- }
- tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0);
- a2 = TCG_VEC_TMP;
- }
- insn = cmp_insn[cond];
- if (insn == 0) {
- TCGArg t;
- t = a1, a1 = a2, a2 = t;
- cond = tcg_swap_cond(cond);
- insn = cmp_insn[cond];
- tcg_debug_assert(insn != 0);
- }
- tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
- }
- }
- break;
-
- case INDEX_op_bitsel_vec:
- a3 = args[3];
- if (a0 == a3) {
- tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1);
- } else if (a0 == a2) {
- tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1);
- } else {
- if (a0 != a1) {
- tcg_out_mov(s, type, a0, a1);
- }
- tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3);
- }
- break;
-
- case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
- case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
- case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
- default:
- g_assert_not_reached();
- }
-}
-
-int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-{
- switch (opc) {
- case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
- case INDEX_op_and_vec:
- case INDEX_op_or_vec:
- case INDEX_op_xor_vec:
- case INDEX_op_andc_vec:
- case INDEX_op_orc_vec:
- case INDEX_op_neg_vec:
- case INDEX_op_abs_vec:
- case INDEX_op_not_vec:
- case INDEX_op_cmp_vec:
- case INDEX_op_shli_vec:
- case INDEX_op_shri_vec:
- case INDEX_op_sari_vec:
- case INDEX_op_ssadd_vec:
- case INDEX_op_sssub_vec:
- case INDEX_op_usadd_vec:
- case INDEX_op_ussub_vec:
- case INDEX_op_shlv_vec:
- case INDEX_op_bitsel_vec:
- return 1;
- case INDEX_op_rotli_vec:
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
- case INDEX_op_rotlv_vec:
- case INDEX_op_rotrv_vec:
- return -1;
- case INDEX_op_mul_vec:
- case INDEX_op_smax_vec:
- case INDEX_op_smin_vec:
- case INDEX_op_umax_vec:
- case INDEX_op_umin_vec:
- return vece < MO_64;
-
- default:
- return 0;
- }
-}
-
-void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
- TCGArg a0, ...)
-{
- va_list va;
- TCGv_vec v0, v1, v2, t1, t2;
- TCGArg a2;
-
- va_start(va, a0);
- v0 = temp_tcgv_vec(arg_temp(a0));
- v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
- a2 = va_arg(va, TCGArg);
- v2 = temp_tcgv_vec(arg_temp(a2));
-
- switch (opc) {
- case INDEX_op_rotli_vec:
- t1 = tcg_temp_new_vec(type);
- tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
- vec_gen_4(INDEX_op_aa64_sli_vec, type, vece,
- tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
- tcg_temp_free_vec(t1);
- break;
-
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
- /* Right shifts are negative left shifts for AArch64. */
- t1 = tcg_temp_new_vec(type);
- tcg_gen_neg_vec(vece, t1, v2);
- opc = (opc == INDEX_op_shrv_vec
- ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec);
- vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
- tcgv_vec_arg(v1), tcgv_vec_arg(t1));
- tcg_temp_free_vec(t1);
- break;
-
- case INDEX_op_rotlv_vec:
- t1 = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(vece, t1, 8 << vece);
- tcg_gen_sub_vec(vece, t1, v2, t1);
- /* Right shifts are negative left shifts for AArch64. */
- vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
- tcgv_vec_arg(v1), tcgv_vec_arg(t1));
- vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),
- tcgv_vec_arg(v1), tcgv_vec_arg(v2));
- tcg_gen_or_vec(vece, v0, v0, t1);
- tcg_temp_free_vec(t1);
- break;
-
- case INDEX_op_rotrv_vec:
- t1 = tcg_temp_new_vec(type);
- t2 = tcg_temp_new_vec(type);
- tcg_gen_neg_vec(vece, t1, v2);
- tcg_gen_dupi_vec(vece, t2, 8 << vece);
- tcg_gen_add_vec(vece, t2, t1, t2);
- /* Right shifts are negative left shifts for AArch64. */
- vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
- tcgv_vec_arg(v1), tcgv_vec_arg(t1));
- vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2),
- tcgv_vec_arg(v1), tcgv_vec_arg(t2));
- tcg_gen_or_vec(vece, v0, t1, t2);
- tcg_temp_free_vec(t1);
- tcg_temp_free_vec(t2);
- break;
-
- default:
- g_assert_not_reached();
- }
-
- va_end(va);
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
- static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
- static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
- static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
- static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
- static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
- static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
- static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
- static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
- static const TCGTargetOpDef r_r_rAL
- = { .args_ct_str = { "r", "r", "rAL" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef ext2
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
- static const TCGTargetOpDef w_w_w_w
- = { .args_ct_str = { "w", "w", "w", "w" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
- case INDEX_op_not_i32:
- case INDEX_op_not_i64:
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap32_i32:
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap64_i64:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext8u_i64:
- case INDEX_op_ext16u_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_extract_i32:
- case INDEX_op_extract_i64:
- case INDEX_op_sextract_i32:
- case INDEX_op_sextract_i64:
- return &r_r;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return &rZ_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_add_i64:
- case INDEX_op_sub_i32:
- case INDEX_op_sub_i64:
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return &r_r_rA;
-
- case INDEX_op_mul_i32:
- case INDEX_op_mul_i64:
- case INDEX_op_div_i32:
- case INDEX_op_div_i64:
- case INDEX_op_divu_i32:
- case INDEX_op_divu_i64:
- case INDEX_op_rem_i32:
- case INDEX_op_rem_i64:
- case INDEX_op_remu_i32:
- case INDEX_op_remu_i64:
- case INDEX_op_muluh_i64:
- case INDEX_op_mulsh_i64:
- return &r_r_r;
-
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
- case INDEX_op_or_i32:
- case INDEX_op_or_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
- case INDEX_op_orc_i32:
- case INDEX_op_orc_i64:
- case INDEX_op_eqv_i32:
- case INDEX_op_eqv_i64:
- return &r_r_rL;
-
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_rotl_i32:
- case INDEX_op_rotr_i32:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i64:
- return &r_r_ri;
-
- case INDEX_op_clz_i32:
- case INDEX_op_ctz_i32:
- case INDEX_op_clz_i64:
- case INDEX_op_ctz_i64:
- return &r_r_rAL;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return &r_rA;
-
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- return &movc;
-
- case INDEX_op_qemu_ld_i32:
- case INDEX_op_qemu_ld_i64:
- return &r_l;
- case INDEX_op_qemu_st_i32:
- case INDEX_op_qemu_st_i64:
- return &lZ_l;
-
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
- return &dep;
-
- case INDEX_op_extract2_i32:
- case INDEX_op_extract2_i64:
- return &ext2;
-
- case INDEX_op_add2_i32:
- case INDEX_op_add2_i64:
- case INDEX_op_sub2_i32:
- case INDEX_op_sub2_i64:
- return &add2;
-
- case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
- case INDEX_op_mul_vec:
- case INDEX_op_xor_vec:
- case INDEX_op_ssadd_vec:
- case INDEX_op_sssub_vec:
- case INDEX_op_usadd_vec:
- case INDEX_op_ussub_vec:
- case INDEX_op_smax_vec:
- case INDEX_op_smin_vec:
- case INDEX_op_umax_vec:
- case INDEX_op_umin_vec:
- case INDEX_op_shlv_vec:
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
- case INDEX_op_aa64_sshl_vec:
- return &w_w_w;
- case INDEX_op_not_vec:
- case INDEX_op_neg_vec:
- case INDEX_op_abs_vec:
- case INDEX_op_shli_vec:
- case INDEX_op_shri_vec:
- case INDEX_op_sari_vec:
- return &w_w;
- case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
- case INDEX_op_dupm_vec:
- return &w_r;
- case INDEX_op_dup_vec:
- return &w_wr;
- case INDEX_op_or_vec:
- case INDEX_op_andc_vec:
- return &w_w_wO;
- case INDEX_op_and_vec:
- case INDEX_op_orc_vec:
- return &w_w_wN;
- case INDEX_op_cmp_vec:
- return &w_w_wZ;
- case INDEX_op_bitsel_vec:
- return &w_w_w_w;
- case INDEX_op_aa64_sli_vec:
- return &w_0_w;
-
- default:
- return NULL;
- }
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
- tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
- tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
-
- tcg_target_call_clobber_regs = -1ull;
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
- tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
-}
-
-/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */
-#define PUSH_SIZE ((30 - 19 + 1) * 8)
-
-#define FRAME_SIZE \
- ((PUSH_SIZE \
- + TCG_STATIC_CALL_ARGS_SIZE \
- + CPU_TEMP_BUF_NLONGS * sizeof(long) \
- + TCG_TARGET_STACK_ALIGN - 1) \
- & ~(TCG_TARGET_STACK_ALIGN - 1))
-
-/* We're expecting a 2 byte uleb128 encoded value. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-
-/* We're expecting to use a single ADDI insn. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff);
-
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- TCGReg r;
-
- /* Push (FP, LR) and allocate space for all saved registers. */
- tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR,
- TCG_REG_SP, -PUSH_SIZE, 1, 1);
-
- /* Set up frame pointer for canonical unwinding. */
- tcg_out_movr_sp(s, TCG_TYPE_I64, TCG_REG_FP, TCG_REG_SP);
-
- /* Store callee-preserved regs x19..x28. */
- for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
- int ofs = (r - TCG_REG_X19 + 2) * 8;
- tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
- }
-
- /* Make stack space for TCG locals. */
- tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
- FRAME_SIZE - PUSH_SIZE);
-
- /* Inform TCG about how to find TCG locals with register, offset, size. */
- tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
-
-#if !defined(CONFIG_SOFTMMU)
- if (USE_GUEST_BASE) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
- }
-#endif
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);
-
- /*
- * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
- * and fall through to the rest of the epilogue.
- */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0);
-
- /* TB epilogue */
- tb_ret_addr = s->code_ptr;
-
- /* Remove TCG locals stack space. */
- tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
- FRAME_SIZE - PUSH_SIZE);
-
- /* Restore registers x19..x28. */
- for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
- int ofs = (r - TCG_REG_X19 + 2) * 8;
- tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
- }
-
- /* Pop (FP, LR), restore SP to previous frame. */
- tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR,
- TCG_REG_SP, PUSH_SIZE, 0, 1);
- tcg_out_insn(s, 3207, RET, TCG_REG_LR);
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- int i;
- for (i = 0; i < count; ++i) {
- p[i] = NOP;
- }
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[24];
-} DebugFrame;
-
-#define ELF_HOST_MACHINE EM_AARCH64
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = 0x78, /* sleb128 -8 */
- .h.cie.return_column = TCG_REG_LR,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x80 + 28, 1, /* DW_CFA_offset, x28, -8 */
- 0x80 + 27, 2, /* DW_CFA_offset, x27, -16 */
- 0x80 + 26, 3, /* DW_CFA_offset, x26, -24 */
- 0x80 + 25, 4, /* DW_CFA_offset, x25, -32 */
- 0x80 + 24, 5, /* DW_CFA_offset, x24, -40 */
- 0x80 + 23, 6, /* DW_CFA_offset, x23, -48 */
- 0x80 + 22, 7, /* DW_CFA_offset, x22, -56 */
- 0x80 + 21, 8, /* DW_CFA_offset, x21, -64 */
- 0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */
- 0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */
- 0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */
- 0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */
- }
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Andrzej Zaborowski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "elf.h"
+#include "../tcg-pool.c.inc"
+
+int arm_arch = __ARM_ARCH;
+
+#ifndef use_idiv_instructions
+bool use_idiv_instructions;
+#endif
+
+/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */
+#ifdef CONFIG_SOFTMMU
+# define USING_SOFTMMU 1
+#else
+# define USING_SOFTMMU 0
+#endif
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "%r0",
+ "%r1",
+ "%r2",
+ "%r3",
+ "%r4",
+ "%r5",
+ "%r6",
+ "%r7",
+ "%r8",
+ "%r9",
+ "%r10",
+ "%r11",
+ "%r12",
+ "%r13",
+ "%r14",
+ "%pc",
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+ TCG_REG_R4,
+ TCG_REG_R5,
+ TCG_REG_R6,
+ TCG_REG_R7,
+ TCG_REG_R8,
+ TCG_REG_R9,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R13,
+ TCG_REG_R0,
+ TCG_REG_R1,
+ TCG_REG_R2,
+ TCG_REG_R3,
+ TCG_REG_R12,
+ TCG_REG_R14,
+};
+
+static const int tcg_target_call_iarg_regs[4] = {
+ TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
+};
+static const int tcg_target_call_oarg_regs[2] = {
+ TCG_REG_R0, TCG_REG_R1
+};
+
+#define TCG_REG_TMP TCG_REG_R12
+
+enum arm_cond_code_e {
+ COND_EQ = 0x0,
+ COND_NE = 0x1,
+ COND_CS = 0x2, /* Unsigned greater or equal */
+ COND_CC = 0x3, /* Unsigned less than */
+ COND_MI = 0x4, /* Negative */
+ COND_PL = 0x5, /* Zero or greater */
+ COND_VS = 0x6, /* Overflow */
+ COND_VC = 0x7, /* No overflow */
+ COND_HI = 0x8, /* Unsigned greater than */
+ COND_LS = 0x9, /* Unsigned less or equal */
+ COND_GE = 0xa,
+ COND_LT = 0xb,
+ COND_GT = 0xc,
+ COND_LE = 0xd,
+ COND_AL = 0xe,
+};
+
+#define TO_CPSR (1 << 20)
+
+#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
+#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
+#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
+#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
+#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
+#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
+#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
+#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
+
+typedef enum {
+ ARITH_AND = 0x0 << 21,
+ ARITH_EOR = 0x1 << 21,
+ ARITH_SUB = 0x2 << 21,
+ ARITH_RSB = 0x3 << 21,
+ ARITH_ADD = 0x4 << 21,
+ ARITH_ADC = 0x5 << 21,
+ ARITH_SBC = 0x6 << 21,
+ ARITH_RSC = 0x7 << 21,
+ ARITH_TST = 0x8 << 21 | TO_CPSR,
+ ARITH_CMP = 0xa << 21 | TO_CPSR,
+ ARITH_CMN = 0xb << 21 | TO_CPSR,
+ ARITH_ORR = 0xc << 21,
+ ARITH_MOV = 0xd << 21,
+ ARITH_BIC = 0xe << 21,
+ ARITH_MVN = 0xf << 21,
+
+ INSN_CLZ = 0x016f0f10,
+ INSN_RBIT = 0x06ff0f30,
+
+ INSN_LDR_IMM = 0x04100000,
+ INSN_LDR_REG = 0x06100000,
+ INSN_STR_IMM = 0x04000000,
+ INSN_STR_REG = 0x06000000,
+
+ INSN_LDRH_IMM = 0x005000b0,
+ INSN_LDRH_REG = 0x001000b0,
+ INSN_LDRSH_IMM = 0x005000f0,
+ INSN_LDRSH_REG = 0x001000f0,
+ INSN_STRH_IMM = 0x004000b0,
+ INSN_STRH_REG = 0x000000b0,
+
+ INSN_LDRB_IMM = 0x04500000,
+ INSN_LDRB_REG = 0x06500000,
+ INSN_LDRSB_IMM = 0x005000d0,
+ INSN_LDRSB_REG = 0x001000d0,
+ INSN_STRB_IMM = 0x04400000,
+ INSN_STRB_REG = 0x06400000,
+
+ INSN_LDRD_IMM = 0x004000d0,
+ INSN_LDRD_REG = 0x000000d0,
+ INSN_STRD_IMM = 0x004000f0,
+ INSN_STRD_REG = 0x000000f0,
+
+ INSN_DMB_ISH = 0xf57ff05b,
+ INSN_DMB_MCR = 0xee070fba,
+
+ /* Architected nop introduced in v6k. */
+ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
+ also Just So Happened to do nothing on pre-v6k so that we
+ don't need to conditionalize it? */
+ INSN_NOP_v6k = 0xe320f000,
+ /* Otherwise the assembler uses mov r0,r0 */
+ INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
+} ARMInsn;
+
+#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
+
+static const uint8_t tcg_cond_to_arm_cond[] = {
+ [TCG_COND_EQ] = COND_EQ,
+ [TCG_COND_NE] = COND_NE,
+ [TCG_COND_LT] = COND_LT,
+ [TCG_COND_GE] = COND_GE,
+ [TCG_COND_LE] = COND_LE,
+ [TCG_COND_GT] = COND_GT,
+ /* unsigned */
+ [TCG_COND_LTU] = COND_CC,
+ [TCG_COND_GEU] = COND_CS,
+ [TCG_COND_LEU] = COND_LS,
+ [TCG_COND_GTU] = COND_HI,
+};
+
+static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2;
+ if (offset == sextract32(offset, 0, 24)) {
+ *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff);
+ return true;
+ }
+ return false;
+}
+
+static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
+
+ if (offset >= -0xfff && offset <= 0xfff) {
+ tcg_insn_unit insn = *code_ptr;
+ bool u = (offset >= 0);
+ if (!u) {
+ offset = -offset;
+ }
+ insn = deposit32(insn, 23, 1, u);
+ insn = deposit32(insn, 0, 12, offset);
+ *code_ptr = insn;
+ return true;
+ }
+ return false;
+}
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ tcg_debug_assert(addend == 0);
+
+ if (type == R_ARM_PC24) {
+ return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
+ } else if (type == R_ARM_PC13) {
+ return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+#define TCG_CT_CONST_ARM 0x100
+#define TCG_CT_CONST_INV 0x200
+#define TCG_CT_CONST_NEG 0x400
+#define TCG_CT_CONST_ZERO 0x800
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'I':
+ ct->ct |= TCG_CT_CONST_ARM;
+ break;
+ case 'K':
+ ct->ct |= TCG_CT_CONST_INV;
+ break;
+ case 'N': /* The gcc constraint letter is L, already used here. */
+ ct->ct |= TCG_CT_CONST_NEG;
+ break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+
+ case 'r':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffff;
+ break;
+
+ /* qemu_ld address */
+ case 'l':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffff;
+#ifdef CONFIG_SOFTMMU
+ /* r0-r2,lr will be overwritten when reading the tlb entry,
+ so don't use these. */
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+#endif
+ break;
+
+ /* qemu_st address & data */
+ case 's':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffff;
+ /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
+ and r0-r1 doing the byte swapping, so don't use these. */
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
+#if defined(CONFIG_SOFTMMU)
+ /* Avoid clashes with registers being used for helper args */
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+#if TARGET_LONG_BITS == 64
+ /* Avoid clashes with registers being used for helper args */
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+#endif
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+#endif
+ break;
+
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+static inline uint32_t rotl(uint32_t val, int n)
+{
+ return (val << n) | (val >> (32 - n));
+}
+
+/* ARM immediates for ALU instructions are made of an unsigned 8-bit
+ right-rotated by an even amount between 0 and 30. */
+static inline int encode_imm(uint32_t imm)
+{
+ int shift;
+
+ /* simple case, only lower bits */
+ if ((imm & ~0xff) == 0)
+ return 0;
+ /* then try a simple even shift */
+ shift = ctz32(imm) & ~1;
+ if (((imm >> shift) & ~0xff) == 0)
+ return 32 - shift;
+ /* now try harder with rotations */
+ if ((rotl(imm, 2) & ~0xff) == 0)
+ return 2;
+ if ((rotl(imm, 4) & ~0xff) == 0)
+ return 4;
+ if ((rotl(imm, 6) & ~0xff) == 0)
+ return 6;
+ /* imm can't be encoded */
+ return -1;
+}
+
+static inline int check_fit_imm(uint32_t imm)
+{
+ return encode_imm(imm) >= 0;
+}
+
+/* Test if a constant matches the constraint.
+ * TODO: define constraints for:
+ *
+ * ldr/str offset: between -0xfff and 0xfff
+ * ldrh/strh offset: between -0xff and 0xff
+ * mov operand2: values represented with x << (2 * y), x < 0x100
+ * add, sub, eor...: ditto
+ */
+static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct;
+ ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
+{
+ tcg_out32(s, (cond << 28) | 0x0a000000 |
+ (((offset - 8) >> 2) & 0x00ffffff));
+}
+
+static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
+{
+ tcg_out32(s, (cond << 28) | 0x0b000000 |
+ (((offset - 8) >> 2) & 0x00ffffff));
+}
+
+static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
+{
+ tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
+}
+
+static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)
+{
+ tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
+ (((offset - 8) >> 2) & 0x00ffffff));
+}
+
+static inline void tcg_out_dat_reg(TCGContext *s,
+ int cond, int opc, int rd, int rn, int rm, int shift)
+{
+ tcg_out32(s, (cond << 28) | (0 << 25) | opc |
+ (rn << 16) | (rd << 12) | shift | rm);
+}
+
+static inline void tcg_out_nop(TCGContext *s)
+{
+ tcg_out32(s, INSN_NOP);
+}
+
+static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
+{
+ /* Simple reg-reg move, optimising out the 'do nothing' case */
+ if (rd != rm) {
+ tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
+ }
+}
+
+static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn)
+{
+ /* Unless the C portion of QEMU is compiled as thumb, we don't
+ actually need true BX semantics; merely a branch to an address
+ held in a register. */
+ if (use_armv5t_instructions) {
+ tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
+ } else {
+ tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);
+ }
+}
+
+static inline void tcg_out_dat_imm(TCGContext *s,
+ int cond, int opc, int rd, int rn, int im)
+{
+ tcg_out32(s, (cond << 28) | (1 << 25) | opc |
+ (rn << 16) | (rd << 12) | im);
+}
+
+/* Note that this routine is used for both LDR and LDRH formats, so we do
+ not wish to include an immediate shift at this point. */
+static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
+ TCGReg rn, TCGReg rm, bool u, bool p, bool w)
+{
+ tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)
+ | (w << 21) | (rn << 16) | (rt << 12) | rm);
+}
+
+static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
+ TCGReg rn, int imm8, bool p, bool w)
+{
+ bool u = 1;
+ if (imm8 < 0) {
+ imm8 = -imm8;
+ u = 0;
+ }
+ tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
+ (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));
+}
+
+static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
+ TCGReg rn, int imm12, bool p, bool w)
+{
+ bool u = 1;
+ if (imm12 < 0) {
+ imm12 = -imm12;
+ u = 0;
+ }
+ tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
+ (rn << 16) | (rt << 12) | imm12);
+}
+
+static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm12)
+{
+ tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);
+}
+
+static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm12)
+{
+ tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0);
+}
+
+static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm8)
+{
+ tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0);
+}
+
+static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1);
+}
+
+static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm8)
+{
+ tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);
+}
+
+static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0);
+}
+
+/* Register pre-increment with base writeback. */
+static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1);
+}
+
+static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1);
+}
+
+static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm8)
+{
+ tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0);
+}
+
+static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm8)
+{
+ tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0);
+}
+
+static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm8)
+{
+ tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0);
+}
+
+static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm12)
+{
+ tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0);
+}
+
+static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm12)
+{
+ tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0);
+}
+
+static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, int imm8)
+{
+ tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0);
+}
+
+static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,
+ TCGReg rn, TCGReg rm)
+{
+ tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);
+}
+
+static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)
+{
+ new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
+ tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
+}
+
+static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)
+{
+ int rot, diff, opc, sh1, sh2;
+ uint32_t tt0, tt1, tt2;
+
+ /* Check a single MOV/MVN before anything else. */
+ rot = encode_imm(arg);
+ if (rot >= 0) {
+ tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0,
+ rotl(arg, rot) | (rot << 7));
+ return;
+ }
+ rot = encode_imm(~arg);
+ if (rot >= 0) {
+ tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0,
+ rotl(~arg, rot) | (rot << 7));
+ return;
+ }
+
+ /* Check for a pc-relative address. This will usually be the TB,
+ or within the TB, which is immediately before the code block. */
+ diff = arg - ((intptr_t)s->code_ptr + 8);
+ if (diff >= 0) {
+ rot = encode_imm(diff);
+ if (rot >= 0) {
+ tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC,
+ rotl(diff, rot) | (rot << 7));
+ return;
+ }
+ } else {
+ rot = encode_imm(-diff);
+ if (rot >= 0) {
+ tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC,
+ rotl(-diff, rot) | (rot << 7));
+ return;
+ }
+ }
+
+ /* Use movw + movt. */
+ if (use_armv7_instructions) {
+ /* movw */
+ tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
+ | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
+ if (arg & 0xffff0000) {
+ /* movt */
+ tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
+ | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
+ }
+ return;
+ }
+
+ /* Look for sequences of two insns. If we have lots of 1's, we can
+ shorten the sequence by beginning with mvn and then clearing
+ higher bits with eor. */
+ tt0 = arg;
+ opc = ARITH_MOV;
+ if (ctpop32(arg) > 16) {
+ tt0 = ~arg;
+ opc = ARITH_MVN;
+ }
+ sh1 = ctz32(tt0) & ~1;
+ tt1 = tt0 & ~(0xff << sh1);
+ sh2 = ctz32(tt1) & ~1;
+ tt2 = tt1 & ~(0xff << sh2);
+ if (tt2 == 0) {
+ rot = ((32 - sh1) << 7) & 0xf00;
+ tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot);
+ rot = ((32 - sh2) << 7) & 0xf00;
+ tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd,
+ ((tt0 >> sh2) & 0xff) | rot);
+ return;
+ }
+
+ /* Otherwise, drop it into the constant pool. */
+ tcg_out_movi_pool(s, cond, rd, arg);
+}
+
+static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,
+ TCGArg lhs, TCGArg rhs, int rhs_is_const)
+{
+ /* Emit either the reg,imm or reg,reg form of a data-processing insn.
+ * rhs must satisfy the "rI" constraint.
+ */
+ if (rhs_is_const) {
+ int rot = encode_imm(rhs);
+ tcg_debug_assert(rot >= 0);
+ tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
+ } else {
+ tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
+ }
+}
+
+static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv,
+ TCGReg dst, TCGReg lhs, TCGArg rhs,
+ bool rhs_is_const)
+{
+ /* Emit either the reg,imm or reg,reg form of a data-processing insn.
+ * rhs must satisfy the "rIK" constraint.
+ */
+ if (rhs_is_const) {
+ int rot = encode_imm(rhs);
+ if (rot < 0) {
+ rhs = ~rhs;
+ rot = encode_imm(rhs);
+ tcg_debug_assert(rot >= 0);
+ opc = opinv;
+ }
+ tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
+ } else {
+ tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
+ }
+}
+
+static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg,
+ TCGArg dst, TCGArg lhs, TCGArg rhs,
+ bool rhs_is_const)
+{
+ /* Emit either the reg,imm or reg,reg form of a data-processing insn.
+ * rhs must satisfy the "rIN" constraint.
+ */
+ if (rhs_is_const) {
+ int rot = encode_imm(rhs);
+ if (rot < 0) {
+ rhs = -rhs;
+ rot = encode_imm(rhs);
+ tcg_debug_assert(rot >= 0);
+ opc = opneg;
+ }
+ tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
+ } else {
+ tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
+ }
+}
+
+static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd,
+ TCGReg rn, TCGReg rm)
+{
+ /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
+ if (!use_armv6_instructions && rd == rn) {
+ if (rd == rm) {
+ /* rd == rn == rm; copy an input to tmp first. */
+ tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
+ rm = rn = TCG_REG_TMP;
+ } else {
+ rn = rm;
+ rm = rd;
+ }
+ }
+ /* mul */
+ tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn);
+}
+
+static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0,
+ TCGReg rd1, TCGReg rn, TCGReg rm)
+{
+ /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
+ if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
+ if (rd0 == rm || rd1 == rm) {
+ tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
+ rn = TCG_REG_TMP;
+ } else {
+ TCGReg t = rn;
+ rn = rm;
+ rm = t;
+ }
+ }
+ /* umull */
+ tcg_out32(s, (cond << 28) | 0x00800090 |
+ (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
+}
+
+static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0,
+ TCGReg rd1, TCGReg rn, TCGReg rm)
+{
+ /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
+ if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
+ if (rd0 == rm || rd1 == rm) {
+ tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
+ rn = TCG_REG_TMP;
+ } else {
+ TCGReg t = rn;
+ rn = rm;
+ rm = t;
+ }
+ }
+ /* smull */
+ tcg_out32(s, (cond << 28) | 0x00c00090 |
+ (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
+}
+
+static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm)
+{
+ tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
+}
+
+static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm)
+{
+ tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
+}
+
+static inline void tcg_out_ext8s(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* sxtb */
+ tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_LSL(24));
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rd, SHIFT_IMM_ASR(24));
+ }
+}
+
+static inline void tcg_out_ext8u(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
+}
+
+static inline void tcg_out_ext16s(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* sxth */
+ tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_LSL(16));
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rd, SHIFT_IMM_ASR(16));
+ }
+}
+
+static inline void tcg_out_ext16u(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* uxth */
+ tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_LSL(16));
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rd, SHIFT_IMM_LSR(16));
+ }
+}
+
+static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* revsh */
+ tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16));
+ tcg_out_dat_reg(s, cond, ARITH_ORR,
+ rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
+ }
+}
+
+static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* rev16 */
+ tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSR(16));
+ tcg_out_dat_reg(s, cond, ARITH_ORR,
+ rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
+ }
+}
+
+/* swap the two low bytes assuming that the two high input bytes and the
+ two high output bit can hold any value. */
+static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* rev16 */
+ tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8));
+ tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff);
+ tcg_out_dat_reg(s, cond, ARITH_ORR,
+ rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8));
+ }
+}
+
+static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* rev */
+ tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_EOR,
+ TCG_REG_TMP, rn, rn, SHIFT_IMM_ROR(16));
+ tcg_out_dat_imm(s, cond, ARITH_BIC,
+ TCG_REG_TMP, TCG_REG_TMP, 0xff | 0x800);
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_ROR(8));
+ tcg_out_dat_reg(s, cond, ARITH_EOR,
+ rd, rd, TCG_REG_TMP, SHIFT_IMM_LSR(8));
+ }
+}
+
+static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd,
+ TCGArg a1, int ofs, int len, bool const_a1)
+{
+ if (const_a1) {
+ /* bfi becomes bfc with rn == 15. */
+ a1 = 15;
+ }
+ /* bfi/bfc */
+ tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1
+ | (ofs << 7) | ((ofs + len - 1) << 16));
+}
+
+static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd,
+ TCGArg a1, int ofs, int len)
+{
+ /* ubfx */
+ tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1
+ | (ofs << 7) | ((len - 1) << 16));
+}
+
+static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd,
+ TCGArg a1, int ofs, int len)
+{
+ /* sbfx */
+ tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1
+ | (ofs << 7) | ((len - 1) << 16));
+}
+
+static inline void tcg_out_ld32u(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xfff || offset < -0xfff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_ld32_12(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_st32(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xfff || offset < -0xfff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_st32_12(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_ld16u(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xff || offset < -0xff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_ld16u_8(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_ld16s(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xff || offset < -0xff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_ld16s_8(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_st16(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xff || offset < -0xff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_st16_8(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_ld8u(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xfff || offset < -0xfff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_ld8_12(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_ld8s(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xff || offset < -0xff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_ld8s_8(s, cond, rd, rn, offset);
+}
+
+static inline void tcg_out_st8(TCGContext *s, int cond,
+ int rd, int rn, int32_t offset)
+{
+ if (offset > 0xfff || offset < -0xfff) {
+ tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
+ tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP);
+ } else
+ tcg_out_st8_12(s, cond, rd, rn, offset);
+}
+
+/* The _goto case is normally between TBs within the same code buffer, and
+ * with the code buffer limited to 16MB we wouldn't need the long case.
+ * But we also use it for the tail-call to the qemu_ld/st helpers, which does.
+ */
+static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr)
+{
+ intptr_t addri = (intptr_t)addr;
+ ptrdiff_t disp = tcg_pcrel_diff(s, addr);
+
+ if ((addri & 1) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) {
+ tcg_out_b(s, cond, disp);
+ return;
+ }
+ tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
+}
+
+/* The call case is mostly used for helpers - so it's not unreasonable
+ * for them to be beyond branch range */
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr)
+{
+ intptr_t addri = (intptr_t)addr;
+ ptrdiff_t disp = tcg_pcrel_diff(s, addr);
+
+ if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) {
+ if (addri & 1) {
+ /* Use BLX if the target is in Thumb mode */
+ if (!use_armv5t_instructions) {
+ tcg_abort();
+ }
+ tcg_out_blx_imm(s, disp);
+ } else {
+ tcg_out_bl(s, COND_AL, disp);
+ }
+ } else if (use_armv7_instructions) {
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
+ tcg_out_blx(s, COND_AL, TCG_REG_TMP);
+ } else {
+ /* ??? Know that movi_pool emits exactly 1 insn. */
+ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0);
+ tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
+ }
+}
+
+static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
+{
+ if (l->has_value) {
+ tcg_out_goto(s, cond, l->u.value_ptr);
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0);
+ tcg_out_b(s, cond, 0);
+ }
+}
+
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (use_armv7_instructions) {
+ tcg_out32(s, INSN_DMB_ISH);
+ } else if (use_armv6_instructions) {
+ tcg_out32(s, INSN_DMB_MCR);
+ }
+}
+
+static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ TCGReg al = args[0];
+ TCGReg ah = args[1];
+ TCGArg bl = args[2];
+ TCGArg bh = args[3];
+ TCGCond cond = args[4];
+ int const_bl = const_args[2];
+ int const_bh = const_args[3];
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ case TCG_COND_LTU:
+ case TCG_COND_LEU:
+ case TCG_COND_GTU:
+ case TCG_COND_GEU:
+ /* We perform a conditional comparision. If the high half is
+ equal, then overwrite the flags with the comparison of the
+ low half. The resulting flags cover the whole. */
+ tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh);
+ tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
+ return cond;
+
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ /* We perform a double-word subtraction and examine the result.
+ We do not actually need the result of the subtract, so the
+ low part "subtract" is a compare. For the high half we have
+ no choice but to compute into a temporary. */
+ tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl);
+ tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR,
+ TCG_REG_TMP, ah, bh, const_bh);
+ return cond;
+
+ case TCG_COND_LE:
+ case TCG_COND_GT:
+ /* Similar, but with swapped arguments, via reversed subtract. */
+ tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR,
+ TCG_REG_TMP, al, bl, const_bl);
+ tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR,
+ TCG_REG_TMP, ah, bh, const_bh);
+ return tcg_swap_cond(cond);
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+#ifdef CONFIG_SOFTMMU
+#include "../tcg-ldst.c.inc"
+
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * int mmu_idx, uintptr_t ra)
+ */
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_LESW] = helper_le_ldsw_mmu,
+ [MO_LESL] = helper_le_ldul_mmu,
+
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+ [MO_BESW] = helper_be_ldsw_mmu,
+ [MO_BESL] = helper_be_ldul_mmu,
+};
+
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, int mmu_idx, uintptr_t ra)
+ */
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+
+/* Helper routines for marshalling helper function arguments into
+ * the correct registers and stack.
+ * argreg is where we want to put this argument, arg is the argument itself.
+ * Return value is the updated argreg ready for the next call.
+ * Note that argreg 0..3 is real registers, 4+ on stack.
+ *
+ * We provide routines for arguments which are: immediate, 32 bit
+ * value in register, 16 and 8 bit values in register (which must be zero
+ * extended before use) and 64 bit value in a lo:hi register pair.
+ */
+#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
+static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
+{ \
+ if (argreg < 4) { \
+ MOV_ARG(s, COND_AL, argreg, arg); \
+ } else { \
+ int ofs = (argreg - 4) * 4; \
+ EXT_ARG; \
+ tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
+ tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
+ } \
+ return argreg + 1; \
+}
+
+DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32,
+ (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
+DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u,
+ (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
+DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u,
+ (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
+DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, )
+
+static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
+ TCGReg arglo, TCGReg arghi)
+{
+ /* 64 bit arguments must go in even/odd register pairs
+ * and in 8-aligned stack slots.
+ */
+ if (argreg & 1) {
+ argreg++;
+ }
+ if (use_armv6_instructions && argreg >= 4
+ && (arglo & 1) == 0 && arghi == arglo + 1) {
+ tcg_out_strd_8(s, COND_AL, arglo,
+ TCG_REG_CALL_STACK, (argreg - 4) * 4);
+ return argreg + 2;
+ } else {
+ argreg = tcg_out_arg_reg32(s, argreg, arglo);
+ argreg = tcg_out_arg_reg32(s, argreg, arghi);
+ return argreg;
+ }
+}
+
+#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
+
+/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
+
+/* These offsets are built into the LDRD below. */
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
+
+/* Load and compare a TLB entry, leaving the flags set. Returns the register
+ containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
+
+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
+ MemOp opc, int mem_index, bool is_load)
+{
+ int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+
+ /*
+ * We don't support inline unaligned acceses, but we can easily
+ * support overalignment checks.
+ */
+ if (a_bits < s_bits) {
+ a_bits = s_bits;
+ }
+
+ /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
+ if (use_armv6_instructions) {
+ tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
+ } else {
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off);
+ }
+
+ /* Extract the tlb index from the address into R0. */
+ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
+ SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
+
+ /*
+ * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
+ * Load the tlb comparator into R2/R3 and the fast path addend into R1.
+ */
+ if (cmp_off == 0) {
+ if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
+ tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
+ } else {
+ tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
+ }
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
+ TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
+ if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
+ tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
+ } else {
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
+ }
+ }
+ if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4);
+ }
+
+ /* Load the tlb addend. */
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
+ offsetof(CPUTLBEntry, addend));
+
+ /*
+ * Check alignment, check comparators.
+ * Do this in no more than 3 insns. Use MOVW for v7, if possible,
+ * to reduce the number of sequential conditional instructions.
+ * Almost all guests have at least 4k pages, which means that we need
+ * to clear at least 9 bits even for an 8-byte memory, which means it
+ * isn't worth checking for an immediate operand for BIC.
+ */
+ if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
+ tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
+
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
+ tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
+ addrlo, TCG_REG_TMP, 0);
+ tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
+ } else {
+ if (a_bits) {
+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,
+ (1 << a_bits) - 1);
+ }
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo,
+ SHIFT_IMM_LSR(TARGET_PAGE_BITS));
+ tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,
+ 0, TCG_REG_R2, TCG_REG_TMP,
+ SHIFT_IMM_LSL(TARGET_PAGE_BITS));
+ }
+
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
+ }
+
+ return TCG_REG_R1;
+}
+
+/* Record the context of a call to the out of line helper code for the slow
+ path for a load or store, so that we can later generate the correct
+ helper code. */
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+ TCGReg datalo, TCGReg datahi, TCGReg addrlo,
+ TCGReg addrhi, tcg_insn_unit *raddr,
+ tcg_insn_unit *label_ptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->datalo_reg = datalo;
+ label->datahi_reg = datahi;
+ label->addrlo_reg = addrlo;
+ label->addrhi_reg = addrhi;
+ label->raddr = raddr;
+ label->label_ptr[0] = label_ptr;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGReg argreg, datalo, datahi;
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+ void *func;
+
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
+ return false;
+ }
+
+ argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
+ if (TARGET_LONG_BITS == 64) {
+ argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
+ } else {
+ argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
+ }
+ argreg = tcg_out_arg_imm32(s, argreg, oi);
+ argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
+
+ /* For armv6 we can use the canonical unsigned helpers and minimize
+ icache usage. For pre-armv6, use the signed helpers since we do
+ not have a single insn sign-extend. */
+ if (use_armv6_instructions) {
+ func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)];
+ } else {
+ func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)];
+ if (opc & MO_SIGN) {
+ opc = MO_UL;
+ }
+ }
+ tcg_out_call(s, func);
+
+ datalo = lb->datalo_reg;
+ datahi = lb->datahi_reg;
+ switch (opc & MO_SSIZE) {
+ case MO_SB:
+ tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0);
+ break;
+ case MO_SW:
+ tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0);
+ break;
+ default:
+ tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
+ break;
+ case MO_Q:
+ if (datalo != TCG_REG_R1) {
+ tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
+ tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
+ } else if (datahi != TCG_REG_R0) {
+ tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
+ tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
+ } else {
+ tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0);
+ tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
+ tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP);
+ }
+ break;
+ }
+
+ tcg_out_goto(s, COND_AL, lb->raddr);
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGReg argreg, datalo, datahi;
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
+ return false;
+ }
+
+ argreg = TCG_REG_R0;
+ argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
+ if (TARGET_LONG_BITS == 64) {
+ argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
+ } else {
+ argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
+ }
+
+ datalo = lb->datalo_reg;
+ datahi = lb->datahi_reg;
+ switch (opc & MO_SIZE) {
+ case MO_8:
+ argreg = tcg_out_arg_reg8(s, argreg, datalo);
+ break;
+ case MO_16:
+ argreg = tcg_out_arg_reg16(s, argreg, datalo);
+ break;
+ case MO_32:
+ default:
+ argreg = tcg_out_arg_reg32(s, argreg, datalo);
+ break;
+ case MO_64:
+ argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi);
+ break;
+ }
+
+ argreg = tcg_out_arg_imm32(s, argreg, oi);
+ argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
+
+ /* Tail-call to the helper, which will return to the fast path. */
+ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ return true;
+}
+#endif /* SOFTMMU */
+
+static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addend)
+{
+ MemOp bswap = opc & MO_BSWAP;
+
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
+ tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend);
+ break;
+ case MO_SB:
+ tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend);
+ break;
+ case MO_UW:
+ tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
+ if (bswap) {
+ tcg_out_bswap16(s, COND_AL, datalo, datalo);
+ }
+ break;
+ case MO_SW:
+ if (bswap) {
+ tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
+ tcg_out_bswap16s(s, COND_AL, datalo, datalo);
+ } else {
+ tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
+ }
+ break;
+ case MO_UL:
+ default:
+ tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
+ if (bswap) {
+ tcg_out_bswap32(s, COND_AL, datalo, datalo);
+ }
+ break;
+ case MO_Q:
+ {
+ TCGReg dl = (bswap ? datahi : datalo);
+ TCGReg dh = (bswap ? datalo : datahi);
+
+ /* Avoid ldrd for user-only emulation, to handle unaligned. */
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (dl & 1) == 0 && dh == dl + 1) {
+ tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend);
+ } else if (dl != addend) {
+ tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo);
+ tcg_out_ld32_12(s, COND_AL, dh, addend, 4);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
+ addend, addrlo, SHIFT_IMM_LSL(0));
+ tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0);
+ tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4);
+ }
+ if (bswap) {
+ tcg_out_bswap32(s, COND_AL, dl, dl);
+ tcg_out_bswap32(s, COND_AL, dh, dh);
+ }
+ }
+ break;
+ }
+}
+
+static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo)
+{
+ MemOp bswap = opc & MO_BSWAP;
+
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
+ tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0);
+ break;
+ case MO_SB:
+ tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0);
+ break;
+ case MO_UW:
+ tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
+ if (bswap) {
+ tcg_out_bswap16(s, COND_AL, datalo, datalo);
+ }
+ break;
+ case MO_SW:
+ if (bswap) {
+ tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
+ tcg_out_bswap16s(s, COND_AL, datalo, datalo);
+ } else {
+ tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
+ }
+ break;
+ case MO_UL:
+ default:
+ tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
+ if (bswap) {
+ tcg_out_bswap32(s, COND_AL, datalo, datalo);
+ }
+ break;
+ case MO_Q:
+ {
+ TCGReg dl = (bswap ? datahi : datalo);
+ TCGReg dh = (bswap ? datalo : datahi);
+
+ /* Avoid ldrd for user-only emulation, to handle unaligned. */
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (dl & 1) == 0 && dh == dl + 1) {
+ tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0);
+ } else if (dl == addrlo) {
+ tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
+ tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
+ } else {
+ tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
+ tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
+ }
+ if (bswap) {
+ tcg_out_bswap32(s, COND_AL, dl, dl);
+ tcg_out_bswap32(s, COND_AL, dh, dh);
+ }
+ }
+ break;
+ }
+}
+
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
+{
+ TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
+ MemOp opc;
+#ifdef CONFIG_SOFTMMU
+ int mem_index;
+ TCGReg addend;
+ tcg_insn_unit *label_ptr;
+#endif
+
+ datalo = *args++;
+ datahi = (is64 ? *args++ : 0);
+ addrlo = *args++;
+ addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#ifdef CONFIG_SOFTMMU
+ mem_index = get_mmuidx(oi);
+ addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1);
+
+ /* This a conditional BL only to load a pointer within this opcode into LR
+ for the slow path. We will not be using the value for a tail call. */
+ label_ptr = s->code_ptr;
+ tcg_out_bl(s, COND_NE, 0);
+
+ tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend);
+
+ add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
+ s->code_ptr, label_ptr);
+#else /* !CONFIG_SOFTMMU */
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base);
+ tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP);
+ } else {
+ tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo);
+ }
+#endif
+}
+
+static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addend)
+{
+ MemOp bswap = opc & MO_BSWAP;
+
+ switch (opc & MO_SIZE) {
+ case MO_8:
+ tcg_out_st8_r(s, cond, datalo, addrlo, addend);
+ break;
+ case MO_16:
+ if (bswap) {
+ tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo);
+ tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);
+ } else {
+ tcg_out_st16_r(s, cond, datalo, addrlo, addend);
+ }
+ break;
+ case MO_32:
+ default:
+ if (bswap) {
+ tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
+ tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend);
+ } else {
+ tcg_out_st32_r(s, cond, datalo, addrlo, addend);
+ }
+ break;
+ case MO_64:
+ /* Avoid strd for user-only emulation, to handle unaligned. */
+ if (bswap) {
+ tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);
+ tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo);
+ tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
+ tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4);
+ } else if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
+ tcg_out_strd_r(s, cond, datalo, addrlo, addend);
+ } else {
+ tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
+ tcg_out_st32_12(s, cond, datahi, addend, 4);
+ }
+ break;
+ }
+}
+
+static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo)
+{
+ MemOp bswap = opc & MO_BSWAP;
+
+ switch (opc & MO_SIZE) {
+ case MO_8:
+ tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
+ break;
+ case MO_16:
+ if (bswap) {
+ tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo);
+ tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);
+ } else {
+ tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
+ }
+ break;
+ case MO_32:
+ default:
+ if (bswap) {
+ tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
+ tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
+ } else {
+ tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
+ }
+ break;
+ case MO_64:
+ /* Avoid strd for user-only emulation, to handle unaligned. */
+ if (bswap) {
+ tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);
+ tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
+ tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
+ tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4);
+ } else if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
+ tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
+ } else {
+ tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
+ tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
+ }
+ break;
+ }
+}
+
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
+{
+ TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
+ MemOp opc;
+#ifdef CONFIG_SOFTMMU
+ int mem_index;
+ TCGReg addend;
+ tcg_insn_unit *label_ptr;
+#endif
+
+ datalo = *args++;
+ datahi = (is64 ? *args++ : 0);
+ addrlo = *args++;
+ addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#ifdef CONFIG_SOFTMMU
+ mem_index = get_mmuidx(oi);
+ addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0);
+
+ tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend);
+
+ /* The conditional call must come last, as we're going to return here. */
+ label_ptr = s->code_ptr;
+ tcg_out_bl(s, COND_NE, 0);
+
+ add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
+ s->code_ptr, label_ptr);
+#else /* !CONFIG_SOFTMMU */
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base);
+ tcg_out_qemu_st_index(s, COND_AL, opc, datalo,
+ datahi, addrlo, TCG_REG_TMP);
+ } else {
+ tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo);
+ }
+#endif
+}
+
+static void tcg_out_epilogue(TCGContext *s);
+
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg *args, const int *const_args)
+{
+ TCGArg a0, a1, a2, a3, a4, a5;
+ int c;
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]);
+ tcg_out_epilogue(s);
+ break;
+ case INDEX_op_goto_tb:
+ {
+ /* Indirect jump method */
+ intptr_t ptr, dif, dil;
+ TCGReg base = TCG_REG_PC;
+
+ tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+ ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]);
+ dif = ptr - ((intptr_t)s->code_ptr + 8);
+ dil = sextract32(dif, 0, 12);
+ if (dif != dil) {
+ /* The TB is close, but outside the 12 bits addressable by
+ the load. We can extend this to 20 bits with a sub of a
+ shifted immediate from pc. In the vastly unlikely event
+ the code requires more than 1MB, we'll use 2 insns and
+ be no worse off. */
+ base = TCG_REG_R0;
+ tcg_out_movi32(s, COND_AL, base, ptr - dil);
+ }
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil);
+ set_jmp_reset_offset(s, args[0]);
+ }
+ break;
+ case INDEX_op_goto_ptr:
+ tcg_out_bx(s, COND_AL, args[0]);
+ break;
+ case INDEX_op_br:
+ tcg_out_goto_label(s, COND_AL, arg_label(args[0]));
+ break;
+
+ case INDEX_op_ld8u_i32:
+ tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld8s_i32:
+ tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld16u_i32:
+ tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld16s_i32:
+ tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld_i32:
+ tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st8_i32:
+ tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st16_i32:
+ tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st_i32:
+ tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_movcond_i32:
+ /* Constraints mean that v2 is always in the same register as dest,
+ * so we only need to do "if condition passed, move v1 to dest".
+ */
+ tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
+ args[1], args[2], const_args[2]);
+ tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV,
+ ARITH_MVN, args[0], 0, args[3], const_args[3]);
+ break;
+ case INDEX_op_add_i32:
+ tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
+ args[0], args[1], args[2], const_args[2]);
+ break;
+ case INDEX_op_sub_i32:
+ if (const_args[1]) {
+ if (const_args[2]) {
+ tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]);
+ } else {
+ tcg_out_dat_rI(s, COND_AL, ARITH_RSB,
+ args[0], args[2], args[1], 1);
+ }
+ } else {
+ tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD,
+ args[0], args[1], args[2], const_args[2]);
+ }
+ break;
+ case INDEX_op_and_i32:
+ tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC,
+ args[0], args[1], args[2], const_args[2]);
+ break;
+ case INDEX_op_andc_i32:
+ tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
+ args[0], args[1], args[2], const_args[2]);
+ break;
+ case INDEX_op_or_i32:
+ c = ARITH_ORR;
+ goto gen_arith;
+ case INDEX_op_xor_i32:
+ c = ARITH_EOR;
+ /* Fall through. */
+ gen_arith:
+ tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
+ break;
+ case INDEX_op_add2_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ a3 = args[3], a4 = args[4], a5 = args[5];
+ if (a0 == a3 || (a0 == a5 && !const_args[5])) {
+ a0 = TCG_REG_TMP;
+ }
+ tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR,
+ a0, a2, a4, const_args[4]);
+ tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC,
+ a1, a3, a5, const_args[5]);
+ tcg_out_mov_reg(s, COND_AL, args[0], a0);
+ break;
+ case INDEX_op_sub2_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ a3 = args[3], a4 = args[4], a5 = args[5];
+ if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) {
+ a0 = TCG_REG_TMP;
+ }
+ if (const_args[2]) {
+ if (const_args[4]) {
+ tcg_out_movi32(s, COND_AL, a0, a4);
+ a4 = a0;
+ }
+ tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1);
+ } else {
+ tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR,
+ ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]);
+ }
+ if (const_args[3]) {
+ if (const_args[5]) {
+ tcg_out_movi32(s, COND_AL, a1, a5);
+ a5 = a1;
+ }
+ tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1);
+ } else {
+ tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC,
+ a1, a3, a5, const_args[5]);
+ }
+ tcg_out_mov_reg(s, COND_AL, args[0], a0);
+ break;
+ case INDEX_op_neg_i32:
+ tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
+ break;
+ case INDEX_op_not_i32:
+ tcg_out_dat_reg(s, COND_AL,
+ ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
+ break;
+ case INDEX_op_mul_i32:
+ tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_mulu2_i32:
+ tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
+ break;
+ case INDEX_op_muls2_i32:
+ tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
+ break;
+ /* XXX: Perhaps args[2] & 0x1f is wrong */
+ case INDEX_op_shl_i32:
+ c = const_args[2] ?
+ SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
+ goto gen_shift32;
+ case INDEX_op_shr_i32:
+ c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
+ SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
+ goto gen_shift32;
+ case INDEX_op_sar_i32:
+ c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
+ SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
+ goto gen_shift32;
+ case INDEX_op_rotr_i32:
+ c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
+ SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
+ /* Fall through. */
+ gen_shift32:
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
+ break;
+
+ case INDEX_op_rotl_i32:
+ if (const_args[2]) {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
+ ((0x20 - args[2]) & 0x1f) ?
+ SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
+ SHIFT_IMM_LSL(0));
+ } else {
+ tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20);
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
+ SHIFT_REG_ROR(TCG_REG_TMP));
+ }
+ break;
+
+ case INDEX_op_ctz_i32:
+ tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0);
+ a1 = TCG_REG_TMP;
+ goto do_clz;
+
+ case INDEX_op_clz_i32:
+ a1 = args[1];
+ do_clz:
+ a0 = args[0];
+ a2 = args[2];
+ c = const_args[2];
+ if (c && a2 == 32) {
+ tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0);
+ break;
+ }
+ tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0);
+ tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0);
+ if (c || a0 != a2) {
+ tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c);
+ }
+ break;
+
+ case INDEX_op_brcond_i32:
+ tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
+ args[0], args[1], const_args[1]);
+ tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]],
+ arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i32:
+ tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
+ args[1], args[2], const_args[2]);
+ tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
+ ARITH_MOV, args[0], 0, 1);
+ tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
+ ARITH_MOV, args[0], 0, 0);
+ break;
+
+ case INDEX_op_brcond2_i32:
+ c = tcg_out_cmp2(s, args, const_args);
+ tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5]));
+ break;
+ case INDEX_op_setcond2_i32:
+ c = tcg_out_cmp2(s, args + 1, const_args + 1);
+ tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1);
+ tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)],
+ ARITH_MOV, args[0], 0, 0);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_qemu_ld(s, args, 0);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args, 1);
+ break;
+ case INDEX_op_qemu_st_i32:
+ tcg_out_qemu_st(s, args, 0);
+ break;
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args, 1);
+ break;
+
+ case INDEX_op_bswap16_i32:
+ tcg_out_bswap16(s, COND_AL, args[0], args[1]);
+ break;
+ case INDEX_op_bswap32_i32:
+ tcg_out_bswap32(s, COND_AL, args[0], args[1]);
+ break;
+
+ case INDEX_op_ext8s_i32:
+ tcg_out_ext8s(s, COND_AL, args[0], args[1]);
+ break;
+ case INDEX_op_ext16s_i32:
+ tcg_out_ext16s(s, COND_AL, args[0], args[1]);
+ break;
+ case INDEX_op_ext16u_i32:
+ tcg_out_ext16u(s, COND_AL, args[0], args[1]);
+ break;
+
+ case INDEX_op_deposit_i32:
+ tcg_out_deposit(s, COND_AL, args[0], args[2],
+ args[3], args[4], const_args[2]);
+ break;
+ case INDEX_op_extract_i32:
+ tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]);
+ break;
+ case INDEX_op_sextract_i32:
+ tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
+ break;
+ case INDEX_op_extract2_i32:
+ /* ??? These optimization vs zero should be generic. */
+ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
+ if (const_args[1]) {
+ if (const_args[2]) {
+ tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
+ }
+ } else if (const_args[2]) {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
+ args[1], SHIFT_IMM_LSR(args[3]));
+ } else {
+ /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
+ tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
+ args[1], SHIFT_IMM_LSR(args[3]));
+ }
+ break;
+
+ case INDEX_op_div_i32:
+ tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_divu_i32:
+ tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
+ static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
+ static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
+ static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
+ static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_r_rIN
+ = { .args_ct_str = { "r", "r", "rIN" } };
+ static const TCGTargetOpDef r_r_rIK
+ = { .args_ct_str = { "r", "r", "rIK" } };
+ static const TCGTargetOpDef r_r_r_r
+ = { .args_ct_str = { "r", "r", "r", "r" } };
+ static const TCGTargetOpDef r_r_l_l
+ = { .args_ct_str = { "r", "r", "l", "l" } };
+ static const TCGTargetOpDef s_s_s_s
+ = { .args_ct_str = { "s", "s", "s", "s" } };
+ static const TCGTargetOpDef br
+ = { .args_ct_str = { "r", "rIN" } };
+ static const TCGTargetOpDef ext2
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
+ static const TCGTargetOpDef sub2
+ = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
+ static const TCGTargetOpDef br2
+ = { .args_ct_str = { "r", "r", "rI", "rI" } };
+ static const TCGTargetOpDef setc2
+ = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_sextract_i32:
+ return &r_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_sub_i32:
+ case INDEX_op_setcond_i32:
+ return &r_r_rIN;
+ case INDEX_op_and_i32:
+ case INDEX_op_andc_i32:
+ case INDEX_op_clz_i32:
+ case INDEX_op_ctz_i32:
+ return &r_r_rIK;
+ case INDEX_op_mul_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ return &r_r_r;
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_muls2_i32:
+ return &r_r_r_r;
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ return &r_r_rI;
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotr_i32:
+ return &r_r_ri;
+
+ case INDEX_op_brcond_i32:
+ return &br;
+ case INDEX_op_deposit_i32:
+ return &dep;
+ case INDEX_op_extract2_i32:
+ return &ext2;
+ case INDEX_op_movcond_i32:
+ return &movc;
+ case INDEX_op_add2_i32:
+ return &add2;
+ case INDEX_op_sub2_i32:
+ return &sub2;
+ case INDEX_op_brcond2_i32:
+ return &br2;
+ case INDEX_op_setcond2_i32:
+ return &setc2;
+
+ case INDEX_op_qemu_ld_i32:
+ return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
+ case INDEX_op_qemu_ld_i64:
+ return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
+ case INDEX_op_qemu_st_i32:
+ return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
+ case INDEX_op_qemu_st_i64:
+ return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
+
+ default:
+ return NULL;
+ }
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ /* Only probe for the platform and capabilities if we havn't already
+ determined maximum values at compile time. */
+#ifndef use_idiv_instructions
+ {
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+ use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
+ }
+#endif
+ if (__ARM_ARCH < 7) {
+ const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
+ if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
+ arm_arch = pl[1] - '0';
+ }
+ }
+
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+
+ tcg_target_call_clobber_regs = 0;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
+}
+
+static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+}
+
+static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ return false;
+}
+
+static inline bool tcg_out_mov(TCGContext *s, TCGType type,
+ TCGReg ret, TCGReg arg)
+{
+ tcg_out_mov_reg(s, COND_AL, ret, arg);
+ return true;
+}
+
+static inline void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ tcg_out_movi32(s, COND_AL, ret, arg);
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = INSN_NOP;
+ }
+}
+
+/* Compute frame size via macros, to share between tcg_target_qemu_prologue
+ and tcg_register_jit. */
+
+#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
+
+#define FRAME_SIZE \
+ ((PUSH_SIZE \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_NLONGS * sizeof(long) \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & -TCG_TARGET_STACK_ALIGN)
+
+#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE)
+
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ /* Calling convention requires us to save r4-r11 and lr. */
+ /* stmdb sp!, { r4 - r11, lr } */
+ tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
+
+ /* Reserve callee argument and tcg temp space. */
+ tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
+ TCG_REG_CALL_STACK, STACK_ADDEND, 1);
+ tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+
+ tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]);
+
+ /*
+ * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
+ * and fall through to the rest of the epilogue.
+ */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0);
+ tcg_out_epilogue(s);
+}
+
+static void tcg_out_epilogue(TCGContext *s)
+{
+ /* Release local stack frame. */
+ tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
+ TCG_REG_CALL_STACK, STACK_ADDEND, 1);
+
+ /* ldmia sp!, { r4 - r11, pc } */
+ tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[18];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_ARM
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = 0x7c, /* sleb128 -4 */
+ .h.cie.return_column = 14,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, 13, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ /* The following must match the stmdb in the prologue. */
+ 0x8e, 1, /* DW_CFA_offset, lr, -4 */
+ 0x8b, 2, /* DW_CFA_offset, r11, -8 */
+ 0x8a, 3, /* DW_CFA_offset, r10, -12 */
+ 0x89, 4, /* DW_CFA_offset, r9, -16 */
+ 0x88, 5, /* DW_CFA_offset, r8, -20 */
+ 0x87, 6, /* DW_CFA_offset, r7, -24 */
+ 0x86, 7, /* DW_CFA_offset, r6, -28 */
+ 0x85, 8, /* DW_CFA_offset, r5, -32 */
+ 0x84, 9, /* DW_CFA_offset, r4, -36 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Andrzej Zaborowski
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "elf.h"
-#include "../tcg-pool.inc.c"
-
-int arm_arch = __ARM_ARCH;
-
-#ifndef use_idiv_instructions
-bool use_idiv_instructions;
-#endif
-
-/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */
-#ifdef CONFIG_SOFTMMU
-# define USING_SOFTMMU 1
-#else
-# define USING_SOFTMMU 0
-#endif
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%r0",
- "%r1",
- "%r2",
- "%r3",
- "%r4",
- "%r5",
- "%r6",
- "%r7",
- "%r8",
- "%r9",
- "%r10",
- "%r11",
- "%r12",
- "%r13",
- "%r14",
- "%pc",
-};
-#endif
-
-static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R4,
- TCG_REG_R5,
- TCG_REG_R6,
- TCG_REG_R7,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R13,
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
- TCG_REG_R12,
- TCG_REG_R14,
-};
-
-static const int tcg_target_call_iarg_regs[4] = {
- TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
-};
-static const int tcg_target_call_oarg_regs[2] = {
- TCG_REG_R0, TCG_REG_R1
-};
-
-#define TCG_REG_TMP TCG_REG_R12
-
-enum arm_cond_code_e {
- COND_EQ = 0x0,
- COND_NE = 0x1,
- COND_CS = 0x2, /* Unsigned greater or equal */
- COND_CC = 0x3, /* Unsigned less than */
- COND_MI = 0x4, /* Negative */
- COND_PL = 0x5, /* Zero or greater */
- COND_VS = 0x6, /* Overflow */
- COND_VC = 0x7, /* No overflow */
- COND_HI = 0x8, /* Unsigned greater than */
- COND_LS = 0x9, /* Unsigned less or equal */
- COND_GE = 0xa,
- COND_LT = 0xb,
- COND_GT = 0xc,
- COND_LE = 0xd,
- COND_AL = 0xe,
-};
-
-#define TO_CPSR (1 << 20)
-
-#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
-#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
-#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
-#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
-#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
-#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
-#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
-#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
-
-typedef enum {
- ARITH_AND = 0x0 << 21,
- ARITH_EOR = 0x1 << 21,
- ARITH_SUB = 0x2 << 21,
- ARITH_RSB = 0x3 << 21,
- ARITH_ADD = 0x4 << 21,
- ARITH_ADC = 0x5 << 21,
- ARITH_SBC = 0x6 << 21,
- ARITH_RSC = 0x7 << 21,
- ARITH_TST = 0x8 << 21 | TO_CPSR,
- ARITH_CMP = 0xa << 21 | TO_CPSR,
- ARITH_CMN = 0xb << 21 | TO_CPSR,
- ARITH_ORR = 0xc << 21,
- ARITH_MOV = 0xd << 21,
- ARITH_BIC = 0xe << 21,
- ARITH_MVN = 0xf << 21,
-
- INSN_CLZ = 0x016f0f10,
- INSN_RBIT = 0x06ff0f30,
-
- INSN_LDR_IMM = 0x04100000,
- INSN_LDR_REG = 0x06100000,
- INSN_STR_IMM = 0x04000000,
- INSN_STR_REG = 0x06000000,
-
- INSN_LDRH_IMM = 0x005000b0,
- INSN_LDRH_REG = 0x001000b0,
- INSN_LDRSH_IMM = 0x005000f0,
- INSN_LDRSH_REG = 0x001000f0,
- INSN_STRH_IMM = 0x004000b0,
- INSN_STRH_REG = 0x000000b0,
-
- INSN_LDRB_IMM = 0x04500000,
- INSN_LDRB_REG = 0x06500000,
- INSN_LDRSB_IMM = 0x005000d0,
- INSN_LDRSB_REG = 0x001000d0,
- INSN_STRB_IMM = 0x04400000,
- INSN_STRB_REG = 0x06400000,
-
- INSN_LDRD_IMM = 0x004000d0,
- INSN_LDRD_REG = 0x000000d0,
- INSN_STRD_IMM = 0x004000f0,
- INSN_STRD_REG = 0x000000f0,
-
- INSN_DMB_ISH = 0xf57ff05b,
- INSN_DMB_MCR = 0xee070fba,
-
- /* Architected nop introduced in v6k. */
- /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
- also Just So Happened to do nothing on pre-v6k so that we
- don't need to conditionalize it? */
- INSN_NOP_v6k = 0xe320f000,
- /* Otherwise the assembler uses mov r0,r0 */
- INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
-} ARMInsn;
-
-#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
-
-static const uint8_t tcg_cond_to_arm_cond[] = {
- [TCG_COND_EQ] = COND_EQ,
- [TCG_COND_NE] = COND_NE,
- [TCG_COND_LT] = COND_LT,
- [TCG_COND_GE] = COND_GE,
- [TCG_COND_LE] = COND_LE,
- [TCG_COND_GT] = COND_GT,
- /* unsigned */
- [TCG_COND_LTU] = COND_CC,
- [TCG_COND_GEU] = COND_CS,
- [TCG_COND_LEU] = COND_LS,
- [TCG_COND_GTU] = COND_HI,
-};
-
-static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2;
- if (offset == sextract32(offset, 0, 24)) {
- *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff);
- return true;
- }
- return false;
-}
-
-static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
-
- if (offset >= -0xfff && offset <= 0xfff) {
- tcg_insn_unit insn = *code_ptr;
- bool u = (offset >= 0);
- if (!u) {
- offset = -offset;
- }
- insn = deposit32(insn, 23, 1, u);
- insn = deposit32(insn, 0, 12, offset);
- *code_ptr = insn;
- return true;
- }
- return false;
-}
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- tcg_debug_assert(addend == 0);
-
- if (type == R_ARM_PC24) {
- return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
- } else if (type == R_ARM_PC13) {
- return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
- } else {
- g_assert_not_reached();
- }
-}
-
-#define TCG_CT_CONST_ARM 0x100
-#define TCG_CT_CONST_INV 0x200
-#define TCG_CT_CONST_NEG 0x400
-#define TCG_CT_CONST_ZERO 0x800
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'I':
- ct->ct |= TCG_CT_CONST_ARM;
- break;
- case 'K':
- ct->ct |= TCG_CT_CONST_INV;
- break;
- case 'N': /* The gcc constraint letter is L, already used here. */
- ct->ct |= TCG_CT_CONST_NEG;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
-
- case 'r':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
- break;
-
- /* qemu_ld address */
- case 'l':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
-#ifdef CONFIG_SOFTMMU
- /* r0-r2,lr will be overwritten when reading the tlb entry,
- so don't use these. */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
-#endif
- break;
-
- /* qemu_st address & data */
- case 's':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
- /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
- and r0-r1 doing the byte swapping, so don't use these. */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
-#if defined(CONFIG_SOFTMMU)
- /* Avoid clashes with registers being used for helper args */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
-#if TARGET_LONG_BITS == 64
- /* Avoid clashes with registers being used for helper args */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-#endif
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
-#endif
- break;
-
- default:
- return NULL;
- }
- return ct_str;
-}
-
-static inline uint32_t rotl(uint32_t val, int n)
-{
- return (val << n) | (val >> (32 - n));
-}
-
-/* ARM immediates for ALU instructions are made of an unsigned 8-bit
- right-rotated by an even amount between 0 and 30. */
-static inline int encode_imm(uint32_t imm)
-{
- int shift;
-
- /* simple case, only lower bits */
- if ((imm & ~0xff) == 0)
- return 0;
- /* then try a simple even shift */
- shift = ctz32(imm) & ~1;
- if (((imm >> shift) & ~0xff) == 0)
- return 32 - shift;
- /* now try harder with rotations */
- if ((rotl(imm, 2) & ~0xff) == 0)
- return 2;
- if ((rotl(imm, 4) & ~0xff) == 0)
- return 4;
- if ((rotl(imm, 6) & ~0xff) == 0)
- return 6;
- /* imm can't be encoded */
- return -1;
-}
-
-static inline int check_fit_imm(uint32_t imm)
-{
- return encode_imm(imm) >= 0;
-}
-
-/* Test if a constant matches the constraint.
- * TODO: define constraints for:
- *
- * ldr/str offset: between -0xfff and 0xfff
- * ldrh/strh offset: between -0xff and 0xff
- * mov operand2: values represented with x << (2 * y), x < 0x100
- * add, sub, eor...: ditto
- */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct;
- ct = arg_ct->ct;
- if (ct & TCG_CT_CONST) {
- return 1;
- } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
- return 1;
- } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
- return 1;
- } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) {
- return 1;
- } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
- return 1;
- } else {
- return 0;
- }
-}
-
-static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
-{
- tcg_out32(s, (cond << 28) | 0x0a000000 |
- (((offset - 8) >> 2) & 0x00ffffff));
-}
-
-static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
-{
- tcg_out32(s, (cond << 28) | 0x0b000000 |
- (((offset - 8) >> 2) & 0x00ffffff));
-}
-
-static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
-{
- tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
-}
-
-static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset)
-{
- tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
- (((offset - 8) >> 2) & 0x00ffffff));
-}
-
-static inline void tcg_out_dat_reg(TCGContext *s,
- int cond, int opc, int rd, int rn, int rm, int shift)
-{
- tcg_out32(s, (cond << 28) | (0 << 25) | opc |
- (rn << 16) | (rd << 12) | shift | rm);
-}
-
-static inline void tcg_out_nop(TCGContext *s)
-{
- tcg_out32(s, INSN_NOP);
-}
-
-static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
-{
- /* Simple reg-reg move, optimising out the 'do nothing' case */
- if (rd != rm) {
- tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
- }
-}
-
-static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn)
-{
- /* Unless the C portion of QEMU is compiled as thumb, we don't
- actually need true BX semantics; merely a branch to an address
- held in a register. */
- if (use_armv5t_instructions) {
- tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
- } else {
- tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);
- }
-}
-
-static inline void tcg_out_dat_imm(TCGContext *s,
- int cond, int opc, int rd, int rn, int im)
-{
- tcg_out32(s, (cond << 28) | (1 << 25) | opc |
- (rn << 16) | (rd << 12) | im);
-}
-
-/* Note that this routine is used for both LDR and LDRH formats, so we do
- not wish to include an immediate shift at this point. */
-static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
- TCGReg rn, TCGReg rm, bool u, bool p, bool w)
-{
- tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)
- | (w << 21) | (rn << 16) | (rt << 12) | rm);
-}
-
-static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
- TCGReg rn, int imm8, bool p, bool w)
-{
- bool u = 1;
- if (imm8 < 0) {
- imm8 = -imm8;
- u = 0;
- }
- tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
- (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));
-}
-
-static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
- TCGReg rn, int imm12, bool p, bool w)
-{
- bool u = 1;
- if (imm12 < 0) {
- imm12 = -imm12;
- u = 0;
- }
- tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
- (rn << 16) | (rt << 12) | imm12);
-}
-
-static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm12)
-{
- tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);
-}
-
-static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm12)
-{
- tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0);
-}
-
-static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm8)
-{
- tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0);
-}
-
-static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1);
-}
-
-static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm8)
-{
- tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);
-}
-
-static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0);
-}
-
-/* Register pre-increment with base writeback. */
-static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1);
-}
-
-static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1);
-}
-
-static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm8)
-{
- tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0);
-}
-
-static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm8)
-{
- tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0);
-}
-
-static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm8)
-{
- tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0);
-}
-
-static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm12)
-{
- tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0);
-}
-
-static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm12)
-{
- tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0);
-}
-
-static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, int imm8)
-{
- tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0);
-}
-
-static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,
- TCGReg rn, TCGReg rm)
-{
- tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);
-}
-
-static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)
-{
- new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
- tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
-}
-
-static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)
-{
- int rot, diff, opc, sh1, sh2;
- uint32_t tt0, tt1, tt2;
-
- /* Check a single MOV/MVN before anything else. */
- rot = encode_imm(arg);
- if (rot >= 0) {
- tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0,
- rotl(arg, rot) | (rot << 7));
- return;
- }
- rot = encode_imm(~arg);
- if (rot >= 0) {
- tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0,
- rotl(~arg, rot) | (rot << 7));
- return;
- }
-
- /* Check for a pc-relative address. This will usually be the TB,
- or within the TB, which is immediately before the code block. */
- diff = arg - ((intptr_t)s->code_ptr + 8);
- if (diff >= 0) {
- rot = encode_imm(diff);
- if (rot >= 0) {
- tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC,
- rotl(diff, rot) | (rot << 7));
- return;
- }
- } else {
- rot = encode_imm(-diff);
- if (rot >= 0) {
- tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC,
- rotl(-diff, rot) | (rot << 7));
- return;
- }
- }
-
- /* Use movw + movt. */
- if (use_armv7_instructions) {
- /* movw */
- tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
- | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
- if (arg & 0xffff0000) {
- /* movt */
- tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
- | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
- }
- return;
- }
-
- /* Look for sequences of two insns. If we have lots of 1's, we can
- shorten the sequence by beginning with mvn and then clearing
- higher bits with eor. */
- tt0 = arg;
- opc = ARITH_MOV;
- if (ctpop32(arg) > 16) {
- tt0 = ~arg;
- opc = ARITH_MVN;
- }
- sh1 = ctz32(tt0) & ~1;
- tt1 = tt0 & ~(0xff << sh1);
- sh2 = ctz32(tt1) & ~1;
- tt2 = tt1 & ~(0xff << sh2);
- if (tt2 == 0) {
- rot = ((32 - sh1) << 7) & 0xf00;
- tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot);
- rot = ((32 - sh2) << 7) & 0xf00;
- tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd,
- ((tt0 >> sh2) & 0xff) | rot);
- return;
- }
-
- /* Otherwise, drop it into the constant pool. */
- tcg_out_movi_pool(s, cond, rd, arg);
-}
-
-static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,
- TCGArg lhs, TCGArg rhs, int rhs_is_const)
-{
- /* Emit either the reg,imm or reg,reg form of a data-processing insn.
- * rhs must satisfy the "rI" constraint.
- */
- if (rhs_is_const) {
- int rot = encode_imm(rhs);
- tcg_debug_assert(rot >= 0);
- tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
- } else {
- tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
- }
-}
-
-static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv,
- TCGReg dst, TCGReg lhs, TCGArg rhs,
- bool rhs_is_const)
-{
- /* Emit either the reg,imm or reg,reg form of a data-processing insn.
- * rhs must satisfy the "rIK" constraint.
- */
- if (rhs_is_const) {
- int rot = encode_imm(rhs);
- if (rot < 0) {
- rhs = ~rhs;
- rot = encode_imm(rhs);
- tcg_debug_assert(rot >= 0);
- opc = opinv;
- }
- tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
- } else {
- tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
- }
-}
-
-static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg,
- TCGArg dst, TCGArg lhs, TCGArg rhs,
- bool rhs_is_const)
-{
- /* Emit either the reg,imm or reg,reg form of a data-processing insn.
- * rhs must satisfy the "rIN" constraint.
- */
- if (rhs_is_const) {
- int rot = encode_imm(rhs);
- if (rot < 0) {
- rhs = -rhs;
- rot = encode_imm(rhs);
- tcg_debug_assert(rot >= 0);
- opc = opneg;
- }
- tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
- } else {
- tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
- }
-}
-
-static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd,
- TCGReg rn, TCGReg rm)
-{
- /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
- if (!use_armv6_instructions && rd == rn) {
- if (rd == rm) {
- /* rd == rn == rm; copy an input to tmp first. */
- tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
- rm = rn = TCG_REG_TMP;
- } else {
- rn = rm;
- rm = rd;
- }
- }
- /* mul */
- tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn);
-}
-
-static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0,
- TCGReg rd1, TCGReg rn, TCGReg rm)
-{
- /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
- if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
- if (rd0 == rm || rd1 == rm) {
- tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
- rn = TCG_REG_TMP;
- } else {
- TCGReg t = rn;
- rn = rm;
- rm = t;
- }
- }
- /* umull */
- tcg_out32(s, (cond << 28) | 0x00800090 |
- (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
-}
-
-static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0,
- TCGReg rd1, TCGReg rn, TCGReg rm)
-{
- /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
- if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
- if (rd0 == rm || rd1 == rm) {
- tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
- rn = TCG_REG_TMP;
- } else {
- TCGReg t = rn;
- rn = rm;
- rm = t;
- }
- }
- /* smull */
- tcg_out32(s, (cond << 28) | 0x00c00090 |
- (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
-}
-
-static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm)
-{
- tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
-}
-
-static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm)
-{
- tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
-}
-
-static inline void tcg_out_ext8s(TCGContext *s, int cond,
- int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* sxtb */
- tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rn, SHIFT_IMM_LSL(24));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rd, SHIFT_IMM_ASR(24));
- }
-}
-
-static inline void tcg_out_ext8u(TCGContext *s, int cond,
- int rd, int rn)
-{
- tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
-}
-
-static inline void tcg_out_ext16s(TCGContext *s, int cond,
- int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* sxth */
- tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rn, SHIFT_IMM_LSL(16));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rd, SHIFT_IMM_ASR(16));
- }
-}
-
-static inline void tcg_out_ext16u(TCGContext *s, int cond,
- int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* uxth */
- tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rn, SHIFT_IMM_LSL(16));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rd, SHIFT_IMM_LSR(16));
- }
-}
-
-static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* revsh */
- tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16));
- tcg_out_dat_reg(s, cond, ARITH_ORR,
- rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
- }
-}
-
-static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* rev16 */
- tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSR(16));
- tcg_out_dat_reg(s, cond, ARITH_ORR,
- rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
- }
-}
-
-/* swap the two low bytes assuming that the two high input bytes and the
- two high output bit can hold any value. */
-static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* rev16 */
- tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8));
- tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff);
- tcg_out_dat_reg(s, cond, ARITH_ORR,
- rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8));
- }
-}
-
-static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* rev */
- tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_EOR,
- TCG_REG_TMP, rn, rn, SHIFT_IMM_ROR(16));
- tcg_out_dat_imm(s, cond, ARITH_BIC,
- TCG_REG_TMP, TCG_REG_TMP, 0xff | 0x800);
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, rn, SHIFT_IMM_ROR(8));
- tcg_out_dat_reg(s, cond, ARITH_EOR,
- rd, rd, TCG_REG_TMP, SHIFT_IMM_LSR(8));
- }
-}
-
-static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd,
- TCGArg a1, int ofs, int len, bool const_a1)
-{
- if (const_a1) {
- /* bfi becomes bfc with rn == 15. */
- a1 = 15;
- }
- /* bfi/bfc */
- tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1
- | (ofs << 7) | ((ofs + len - 1) << 16));
-}
-
-static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd,
- TCGArg a1, int ofs, int len)
-{
- /* ubfx */
- tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1
- | (ofs << 7) | ((len - 1) << 16));
-}
-
-static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd,
- TCGArg a1, int ofs, int len)
-{
- /* sbfx */
- tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1
- | (ofs << 7) | ((len - 1) << 16));
-}
-
-static inline void tcg_out_ld32u(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xfff || offset < -0xfff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_ld32_12(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_st32(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xfff || offset < -0xfff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_st32_12(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_ld16u(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xff || offset < -0xff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_ld16u_8(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_ld16s(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xff || offset < -0xff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_ld16s_8(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_st16(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xff || offset < -0xff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_st16_8(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_ld8u(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xfff || offset < -0xfff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_ld8_12(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_ld8s(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xff || offset < -0xff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_ld8s_8(s, cond, rd, rn, offset);
-}
-
-static inline void tcg_out_st8(TCGContext *s, int cond,
- int rd, int rn, int32_t offset)
-{
- if (offset > 0xfff || offset < -0xfff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_st8_12(s, cond, rd, rn, offset);
-}
-
-/* The _goto case is normally between TBs within the same code buffer, and
- * with the code buffer limited to 16MB we wouldn't need the long case.
- * But we also use it for the tail-call to the qemu_ld/st helpers, which does.
- */
-static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr)
-{
- intptr_t addri = (intptr_t)addr;
- ptrdiff_t disp = tcg_pcrel_diff(s, addr);
-
- if ((addri & 1) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) {
- tcg_out_b(s, cond, disp);
- return;
- }
- tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
-}
-
-/* The call case is mostly used for helpers - so it's not unreasonable
- * for them to be beyond branch range */
-static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr)
-{
- intptr_t addri = (intptr_t)addr;
- ptrdiff_t disp = tcg_pcrel_diff(s, addr);
-
- if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) {
- if (addri & 1) {
- /* Use BLX if the target is in Thumb mode */
- if (!use_armv5t_instructions) {
- tcg_abort();
- }
- tcg_out_blx_imm(s, disp);
- } else {
- tcg_out_bl(s, COND_AL, disp);
- }
- } else if (use_armv7_instructions) {
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
- tcg_out_blx(s, COND_AL, TCG_REG_TMP);
- } else {
- /* ??? Know that movi_pool emits exactly 1 insn. */
- tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0);
- tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
- }
-}
-
-static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
-{
- if (l->has_value) {
- tcg_out_goto(s, cond, l->u.value_ptr);
- } else {
- tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0);
- tcg_out_b(s, cond, 0);
- }
-}
-
-static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- if (use_armv7_instructions) {
- tcg_out32(s, INSN_DMB_ISH);
- } else if (use_armv6_instructions) {
- tcg_out32(s, INSN_DMB_MCR);
- }
-}
-
-static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
- const int *const_args)
-{
- TCGReg al = args[0];
- TCGReg ah = args[1];
- TCGArg bl = args[2];
- TCGArg bh = args[3];
- TCGCond cond = args[4];
- int const_bl = const_args[2];
- int const_bh = const_args[3];
-
- switch (cond) {
- case TCG_COND_EQ:
- case TCG_COND_NE:
- case TCG_COND_LTU:
- case TCG_COND_LEU:
- case TCG_COND_GTU:
- case TCG_COND_GEU:
- /* We perform a conditional comparision. If the high half is
- equal, then overwrite the flags with the comparison of the
- low half. The resulting flags cover the whole. */
- tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh);
- tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
- return cond;
-
- case TCG_COND_LT:
- case TCG_COND_GE:
- /* We perform a double-word subtraction and examine the result.
- We do not actually need the result of the subtract, so the
- low part "subtract" is a compare. For the high half we have
- no choice but to compute into a temporary. */
- tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl);
- tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR,
- TCG_REG_TMP, ah, bh, const_bh);
- return cond;
-
- case TCG_COND_LE:
- case TCG_COND_GT:
- /* Similar, but with swapped arguments, via reversed subtract. */
- tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR,
- TCG_REG_TMP, al, bl, const_bl);
- tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR,
- TCG_REG_TMP, ah, bh, const_bh);
- return tcg_swap_cond(cond);
-
- default:
- g_assert_not_reached();
- }
-}
-
-#ifdef CONFIG_SOFTMMU
-#include "../tcg-ldst.inc.c"
-
-/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * int mmu_idx, uintptr_t ra)
- */
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
-
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LESL] = helper_le_ldul_mmu,
-
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BESL] = helper_be_ldul_mmu,
-};
-
-/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, int mmu_idx, uintptr_t ra)
- */
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-
-/* Helper routines for marshalling helper function arguments into
- * the correct registers and stack.
- * argreg is where we want to put this argument, arg is the argument itself.
- * Return value is the updated argreg ready for the next call.
- * Note that argreg 0..3 is real registers, 4+ on stack.
- *
- * We provide routines for arguments which are: immediate, 32 bit
- * value in register, 16 and 8 bit values in register (which must be zero
- * extended before use) and 64 bit value in a lo:hi register pair.
- */
-#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
-static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
-{ \
- if (argreg < 4) { \
- MOV_ARG(s, COND_AL, argreg, arg); \
- } else { \
- int ofs = (argreg - 4) * 4; \
- EXT_ARG; \
- tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
- tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
- } \
- return argreg + 1; \
-}
-
-DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32,
- (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
-DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u,
- (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
-DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u,
- (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
-DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, )
-
-static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
- TCGReg arglo, TCGReg arghi)
-{
- /* 64 bit arguments must go in even/odd register pairs
- * and in 8-aligned stack slots.
- */
- if (argreg & 1) {
- argreg++;
- }
- if (use_armv6_instructions && argreg >= 4
- && (arglo & 1) == 0 && arghi == arglo + 1) {
- tcg_out_strd_8(s, COND_AL, arglo,
- TCG_REG_CALL_STACK, (argreg - 4) * 4);
- return argreg + 2;
- } else {
- argreg = tcg_out_arg_reg32(s, argreg, arglo);
- argreg = tcg_out_arg_reg32(s, argreg, arghi);
- return argreg;
- }
-}
-
-#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
-
-/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
-
-/* These offsets are built into the LDRD below. */
-QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
-QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
-
-/* Load and compare a TLB entry, leaving the flags set. Returns the register
- containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
-
-static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
- MemOp opc, int mem_index, bool is_load)
-{
- int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write));
- int fast_off = TLB_MASK_TABLE_OFS(mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
-
- /*
- * We don't support inline unaligned acceses, but we can easily
- * support overalignment checks.
- */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
-
- /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
- if (use_armv6_instructions) {
- tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
- } else {
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off);
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off);
- }
-
- /* Extract the tlb index from the address into R0. */
- tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
- SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
-
- /*
- * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
- * Load the tlb comparator into R2/R3 and the fast path addend into R1.
- */
- if (cmp_off == 0) {
- if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
- tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
- } else {
- tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
- }
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
- TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
- if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
- tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
- } else {
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
- }
- }
- if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4);
- }
-
- /* Load the tlb addend. */
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
- offsetof(CPUTLBEntry, addend));
-
- /*
- * Check alignment, check comparators.
- * Do this in no more than 3 insns. Use MOVW for v7, if possible,
- * to reduce the number of sequential conditional instructions.
- * Almost all guests have at least 4k pages, which means that we need
- * to clear at least 9 bits even for an 8-byte memory, which means it
- * isn't worth checking for an immediate operand for BIC.
- */
- if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
- tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
-
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
- tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
- addrlo, TCG_REG_TMP, 0);
- tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
- } else {
- if (a_bits) {
- tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,
- (1 << a_bits) - 1);
- }
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo,
- SHIFT_IMM_LSR(TARGET_PAGE_BITS));
- tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,
- 0, TCG_REG_R2, TCG_REG_TMP,
- SHIFT_IMM_LSL(TARGET_PAGE_BITS));
- }
-
- if (TARGET_LONG_BITS == 64) {
- tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
- }
-
- return TCG_REG_R1;
-}
-
-/* Record the context of a call to the out of line helper code for the slow
- path for a load or store, so that we can later generate the correct
- helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
- TCGReg datalo, TCGReg datahi, TCGReg addrlo,
- TCGReg addrhi, tcg_insn_unit *raddr,
- tcg_insn_unit *label_ptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->datalo_reg = datalo;
- label->datahi_reg = datahi;
- label->addrlo_reg = addrlo;
- label->addrhi_reg = addrhi;
- label->raddr = raddr;
- label->label_ptr[0] = label_ptr;
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGReg argreg, datalo, datahi;
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- void *func;
-
- if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
- return false;
- }
-
- argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
- if (TARGET_LONG_BITS == 64) {
- argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
- } else {
- argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
- }
- argreg = tcg_out_arg_imm32(s, argreg, oi);
- argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
-
- /* For armv6 we can use the canonical unsigned helpers and minimize
- icache usage. For pre-armv6, use the signed helpers since we do
- not have a single insn sign-extend. */
- if (use_armv6_instructions) {
- func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)];
- } else {
- func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)];
- if (opc & MO_SIGN) {
- opc = MO_UL;
- }
- }
- tcg_out_call(s, func);
-
- datalo = lb->datalo_reg;
- datahi = lb->datahi_reg;
- switch (opc & MO_SSIZE) {
- case MO_SB:
- tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0);
- break;
- case MO_SW:
- tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0);
- break;
- default:
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
- break;
- case MO_Q:
- if (datalo != TCG_REG_R1) {
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
- tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
- } else if (datahi != TCG_REG_R0) {
- tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
- } else {
- tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0);
- tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1);
- tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP);
- }
- break;
- }
-
- tcg_out_goto(s, COND_AL, lb->raddr);
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGReg argreg, datalo, datahi;
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
-
- if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
- return false;
- }
-
- argreg = TCG_REG_R0;
- argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
- if (TARGET_LONG_BITS == 64) {
- argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
- } else {
- argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
- }
-
- datalo = lb->datalo_reg;
- datahi = lb->datahi_reg;
- switch (opc & MO_SIZE) {
- case MO_8:
- argreg = tcg_out_arg_reg8(s, argreg, datalo);
- break;
- case MO_16:
- argreg = tcg_out_arg_reg16(s, argreg, datalo);
- break;
- case MO_32:
- default:
- argreg = tcg_out_arg_reg32(s, argreg, datalo);
- break;
- case MO_64:
- argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi);
- break;
- }
-
- argreg = tcg_out_arg_imm32(s, argreg, oi);
- argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
-
- /* Tail-call to the helper, which will return to the fast path. */
- tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
- return true;
-}
-#endif /* SOFTMMU */
-
-static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addend)
-{
- MemOp bswap = opc & MO_BSWAP;
-
- switch (opc & MO_SSIZE) {
- case MO_UB:
- tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend);
- break;
- case MO_SB:
- tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend);
- break;
- case MO_UW:
- tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo);
- }
- break;
- case MO_SW:
- if (bswap) {
- tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- tcg_out_bswap16s(s, COND_AL, datalo, datalo);
- } else {
- tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
- }
- break;
- case MO_UL:
- default:
- tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, datalo, datalo);
- }
- break;
- case MO_Q:
- {
- TCGReg dl = (bswap ? datahi : datalo);
- TCGReg dh = (bswap ? datalo : datahi);
-
- /* Avoid ldrd for user-only emulation, to handle unaligned. */
- if (USING_SOFTMMU && use_armv6_instructions
- && (dl & 1) == 0 && dh == dl + 1) {
- tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend);
- } else if (dl != addend) {
- tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo);
- tcg_out_ld32_12(s, COND_AL, dh, addend, 4);
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
- addend, addrlo, SHIFT_IMM_LSL(0));
- tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0);
- tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4);
- }
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, dl, dl);
- tcg_out_bswap32(s, COND_AL, dh, dh);
- }
- }
- break;
- }
-}
-
-static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo)
-{
- MemOp bswap = opc & MO_BSWAP;
-
- switch (opc & MO_SSIZE) {
- case MO_UB:
- tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0);
- break;
- case MO_SB:
- tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0);
- break;
- case MO_UW:
- tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo);
- }
- break;
- case MO_SW:
- if (bswap) {
- tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- tcg_out_bswap16s(s, COND_AL, datalo, datalo);
- } else {
- tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
- }
- break;
- case MO_UL:
- default:
- tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, datalo, datalo);
- }
- break;
- case MO_Q:
- {
- TCGReg dl = (bswap ? datahi : datalo);
- TCGReg dh = (bswap ? datalo : datahi);
-
- /* Avoid ldrd for user-only emulation, to handle unaligned. */
- if (USING_SOFTMMU && use_armv6_instructions
- && (dl & 1) == 0 && dh == dl + 1) {
- tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0);
- } else if (dl == addrlo) {
- tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
- tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
- } else {
- tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
- tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
- }
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, dl, dl);
- tcg_out_bswap32(s, COND_AL, dh, dh);
- }
- }
- break;
- }
-}
-
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
-{
- TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- TCGMemOpIdx oi;
- MemOp opc;
-#ifdef CONFIG_SOFTMMU
- int mem_index;
- TCGReg addend;
- tcg_insn_unit *label_ptr;
-#endif
-
- datalo = *args++;
- datahi = (is64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1);
-
- /* This a conditional BL only to load a pointer within this opcode into LR
- for the slow path. We will not be using the value for a tail call. */
- label_ptr = s->code_ptr;
- tcg_out_bl(s, COND_NE, 0);
-
- tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend);
-
- add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
-#else /* !CONFIG_SOFTMMU */
- if (guest_base) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base);
- tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP);
- } else {
- tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo);
- }
-#endif
-}
-
-static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addend)
-{
- MemOp bswap = opc & MO_BSWAP;
-
- switch (opc & MO_SIZE) {
- case MO_8:
- tcg_out_st8_r(s, cond, datalo, addrlo, addend);
- break;
- case MO_16:
- if (bswap) {
- tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo);
- tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);
- } else {
- tcg_out_st16_r(s, cond, datalo, addrlo, addend);
- }
- break;
- case MO_32:
- default:
- if (bswap) {
- tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
- tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend);
- } else {
- tcg_out_st32_r(s, cond, datalo, addrlo, addend);
- }
- break;
- case MO_64:
- /* Avoid strd for user-only emulation, to handle unaligned. */
- if (bswap) {
- tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);
- tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo);
- tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4);
- } else if (USING_SOFTMMU && use_armv6_instructions
- && (datalo & 1) == 0 && datahi == datalo + 1) {
- tcg_out_strd_r(s, cond, datalo, addrlo, addend);
- } else {
- tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
- tcg_out_st32_12(s, cond, datahi, addend, 4);
- }
- break;
- }
-}
-
-static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo)
-{
- MemOp bswap = opc & MO_BSWAP;
-
- switch (opc & MO_SIZE) {
- case MO_8:
- tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
- break;
- case MO_16:
- if (bswap) {
- tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);
- } else {
- tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
- }
- break;
- case MO_32:
- default:
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
- } else {
- tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
- }
- break;
- case MO_64:
- /* Avoid strd for user-only emulation, to handle unaligned. */
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4);
- } else if (USING_SOFTMMU && use_armv6_instructions
- && (datalo & 1) == 0 && datahi == datalo + 1) {
- tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
- } else {
- tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
- tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
- }
- break;
- }
-}
-
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
-{
- TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- TCGMemOpIdx oi;
- MemOp opc;
-#ifdef CONFIG_SOFTMMU
- int mem_index;
- TCGReg addend;
- tcg_insn_unit *label_ptr;
-#endif
-
- datalo = *args++;
- datahi = (is64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0);
-
- tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend);
-
- /* The conditional call must come last, as we're going to return here. */
- label_ptr = s->code_ptr;
- tcg_out_bl(s, COND_NE, 0);
-
- add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
-#else /* !CONFIG_SOFTMMU */
- if (guest_base) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base);
- tcg_out_qemu_st_index(s, COND_AL, opc, datalo,
- datahi, addrlo, TCG_REG_TMP);
- } else {
- tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo);
- }
-#endif
-}
-
-static void tcg_out_epilogue(TCGContext *s);
-
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
-{
- TCGArg a0, a1, a2, a3, a4, a5;
- int c;
-
- switch (opc) {
- case INDEX_op_exit_tb:
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]);
- tcg_out_epilogue(s);
- break;
- case INDEX_op_goto_tb:
- {
- /* Indirect jump method */
- intptr_t ptr, dif, dil;
- TCGReg base = TCG_REG_PC;
-
- tcg_debug_assert(s->tb_jmp_insn_offset == 0);
- ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]);
- dif = ptr - ((intptr_t)s->code_ptr + 8);
- dil = sextract32(dif, 0, 12);
- if (dif != dil) {
- /* The TB is close, but outside the 12 bits addressable by
- the load. We can extend this to 20 bits with a sub of a
- shifted immediate from pc. In the vastly unlikely event
- the code requires more than 1MB, we'll use 2 insns and
- be no worse off. */
- base = TCG_REG_R0;
- tcg_out_movi32(s, COND_AL, base, ptr - dil);
- }
- tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil);
- set_jmp_reset_offset(s, args[0]);
- }
- break;
- case INDEX_op_goto_ptr:
- tcg_out_bx(s, COND_AL, args[0]);
- break;
- case INDEX_op_br:
- tcg_out_goto_label(s, COND_AL, arg_label(args[0]));
- break;
-
- case INDEX_op_ld8u_i32:
- tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld8s_i32:
- tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld16u_i32:
- tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld16s_i32:
- tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld_i32:
- tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_st8_i32:
- tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_st16_i32:
- tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i32:
- tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_movcond_i32:
- /* Constraints mean that v2 is always in the same register as dest,
- * so we only need to do "if condition passed, move v1 to dest".
- */
- tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
- args[1], args[2], const_args[2]);
- tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV,
- ARITH_MVN, args[0], 0, args[3], const_args[3]);
- break;
- case INDEX_op_add_i32:
- tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
- args[0], args[1], args[2], const_args[2]);
- break;
- case INDEX_op_sub_i32:
- if (const_args[1]) {
- if (const_args[2]) {
- tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]);
- } else {
- tcg_out_dat_rI(s, COND_AL, ARITH_RSB,
- args[0], args[2], args[1], 1);
- }
- } else {
- tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD,
- args[0], args[1], args[2], const_args[2]);
- }
- break;
- case INDEX_op_and_i32:
- tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC,
- args[0], args[1], args[2], const_args[2]);
- break;
- case INDEX_op_andc_i32:
- tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
- args[0], args[1], args[2], const_args[2]);
- break;
- case INDEX_op_or_i32:
- c = ARITH_ORR;
- goto gen_arith;
- case INDEX_op_xor_i32:
- c = ARITH_EOR;
- /* Fall through. */
- gen_arith:
- tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
- break;
- case INDEX_op_add2_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- a3 = args[3], a4 = args[4], a5 = args[5];
- if (a0 == a3 || (a0 == a5 && !const_args[5])) {
- a0 = TCG_REG_TMP;
- }
- tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR,
- a0, a2, a4, const_args[4]);
- tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC,
- a1, a3, a5, const_args[5]);
- tcg_out_mov_reg(s, COND_AL, args[0], a0);
- break;
- case INDEX_op_sub2_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- a3 = args[3], a4 = args[4], a5 = args[5];
- if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) {
- a0 = TCG_REG_TMP;
- }
- if (const_args[2]) {
- if (const_args[4]) {
- tcg_out_movi32(s, COND_AL, a0, a4);
- a4 = a0;
- }
- tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1);
- } else {
- tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR,
- ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]);
- }
- if (const_args[3]) {
- if (const_args[5]) {
- tcg_out_movi32(s, COND_AL, a1, a5);
- a5 = a1;
- }
- tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1);
- } else {
- tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC,
- a1, a3, a5, const_args[5]);
- }
- tcg_out_mov_reg(s, COND_AL, args[0], a0);
- break;
- case INDEX_op_neg_i32:
- tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
- break;
- case INDEX_op_not_i32:
- tcg_out_dat_reg(s, COND_AL,
- ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
- break;
- case INDEX_op_mul_i32:
- tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_mulu2_i32:
- tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
- break;
- case INDEX_op_muls2_i32:
- tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
- break;
- /* XXX: Perhaps args[2] & 0x1f is wrong */
- case INDEX_op_shl_i32:
- c = const_args[2] ?
- SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
- goto gen_shift32;
- case INDEX_op_shr_i32:
- c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
- SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
- goto gen_shift32;
- case INDEX_op_sar_i32:
- c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
- SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
- goto gen_shift32;
- case INDEX_op_rotr_i32:
- c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
- SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
- /* Fall through. */
- gen_shift32:
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
- break;
-
- case INDEX_op_rotl_i32:
- if (const_args[2]) {
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
- ((0x20 - args[2]) & 0x1f) ?
- SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
- SHIFT_IMM_LSL(0));
- } else {
- tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20);
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
- SHIFT_REG_ROR(TCG_REG_TMP));
- }
- break;
-
- case INDEX_op_ctz_i32:
- tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0);
- a1 = TCG_REG_TMP;
- goto do_clz;
-
- case INDEX_op_clz_i32:
- a1 = args[1];
- do_clz:
- a0 = args[0];
- a2 = args[2];
- c = const_args[2];
- if (c && a2 == 32) {
- tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0);
- break;
- }
- tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0);
- tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0);
- if (c || a0 != a2) {
- tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c);
- }
- break;
-
- case INDEX_op_brcond_i32:
- tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
- args[0], args[1], const_args[1]);
- tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]],
- arg_label(args[3]));
- break;
- case INDEX_op_setcond_i32:
- tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
- args[1], args[2], const_args[2]);
- tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
- ARITH_MOV, args[0], 0, 1);
- tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
- ARITH_MOV, args[0], 0, 0);
- break;
-
- case INDEX_op_brcond2_i32:
- c = tcg_out_cmp2(s, args, const_args);
- tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5]));
- break;
- case INDEX_op_setcond2_i32:
- c = tcg_out_cmp2(s, args + 1, const_args + 1);
- tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1);
- tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)],
- ARITH_MOV, args[0], 0, 0);
- break;
-
- case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, 0);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, 1);
- break;
- case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, 0);
- break;
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, 1);
- break;
-
- case INDEX_op_bswap16_i32:
- tcg_out_bswap16(s, COND_AL, args[0], args[1]);
- break;
- case INDEX_op_bswap32_i32:
- tcg_out_bswap32(s, COND_AL, args[0], args[1]);
- break;
-
- case INDEX_op_ext8s_i32:
- tcg_out_ext8s(s, COND_AL, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i32:
- tcg_out_ext16s(s, COND_AL, args[0], args[1]);
- break;
- case INDEX_op_ext16u_i32:
- tcg_out_ext16u(s, COND_AL, args[0], args[1]);
- break;
-
- case INDEX_op_deposit_i32:
- tcg_out_deposit(s, COND_AL, args[0], args[2],
- args[3], args[4], const_args[2]);
- break;
- case INDEX_op_extract_i32:
- tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]);
- break;
- case INDEX_op_sextract_i32:
- tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
- break;
- case INDEX_op_extract2_i32:
- /* ??? These optimization vs zero should be generic. */
- /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
- if (const_args[1]) {
- if (const_args[2]) {
- tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
- args[2], SHIFT_IMM_LSL(32 - args[3]));
- }
- } else if (const_args[2]) {
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
- args[1], SHIFT_IMM_LSR(args[3]));
- } else {
- /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
- args[2], SHIFT_IMM_LSL(32 - args[3]));
- tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
- args[1], SHIFT_IMM_LSR(args[3]));
- }
- break;
-
- case INDEX_op_div_i32:
- tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_divu_i32:
- tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, args[0]);
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
- static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
- static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rIN
- = { .args_ct_str = { "r", "r", "rIN" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_l_l
- = { .args_ct_str = { "r", "r", "l", "l" } };
- static const TCGTargetOpDef s_s_s_s
- = { .args_ct_str = { "s", "s", "s", "s" } };
- static const TCGTargetOpDef br
- = { .args_ct_str = { "r", "rIN" } };
- static const TCGTargetOpDef ext2
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
- static const TCGTargetOpDef sub2
- = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "r", "r", "rI", "rI" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_neg_i32:
- case INDEX_op_not_i32:
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap32_i32:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16u_i32:
- case INDEX_op_extract_i32:
- case INDEX_op_sextract_i32:
- return &r_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_sub_i32:
- case INDEX_op_setcond_i32:
- return &r_r_rIN;
- case INDEX_op_and_i32:
- case INDEX_op_andc_i32:
- case INDEX_op_clz_i32:
- case INDEX_op_ctz_i32:
- return &r_r_rIK;
- case INDEX_op_mul_i32:
- case INDEX_op_div_i32:
- case INDEX_op_divu_i32:
- return &r_r_r;
- case INDEX_op_mulu2_i32:
- case INDEX_op_muls2_i32:
- return &r_r_r_r;
- case INDEX_op_or_i32:
- case INDEX_op_xor_i32:
- return &r_r_rI;
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_rotl_i32:
- case INDEX_op_rotr_i32:
- return &r_r_ri;
-
- case INDEX_op_brcond_i32:
- return &br;
- case INDEX_op_deposit_i32:
- return &dep;
- case INDEX_op_extract2_i32:
- return &ext2;
- case INDEX_op_movcond_i32:
- return &movc;
- case INDEX_op_add2_i32:
- return &add2;
- case INDEX_op_sub2_i32:
- return &sub2;
- case INDEX_op_brcond2_i32:
- return &br2;
- case INDEX_op_setcond2_i32:
- return &setc2;
-
- case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
- case INDEX_op_qemu_ld_i64:
- return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
- case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
- case INDEX_op_qemu_st_i64:
- return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
-
- default:
- return NULL;
- }
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- /* Only probe for the platform and capabilities if we havn't already
- determined maximum values at compile time. */
-#ifndef use_idiv_instructions
- {
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
- use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
- }
-#endif
- if (__ARM_ARCH < 7) {
- const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
- if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
- arm_arch = pl[1] - '0';
- }
- }
-
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
-
- tcg_target_call_clobber_regs = 0;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
-}
-
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
-}
-
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- tcg_out_st32(s, COND_AL, arg, arg1, arg2);
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- return false;
-}
-
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
-{
- tcg_out_mov_reg(s, COND_AL, ret, arg);
- return true;
-}
-
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
-{
- tcg_out_movi32(s, COND_AL, ret, arg);
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- int i;
- for (i = 0; i < count; ++i) {
- p[i] = INSN_NOP;
- }
-}
-
-/* Compute frame size via macros, to share between tcg_target_qemu_prologue
- and tcg_register_jit. */
-
-#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
-
-#define FRAME_SIZE \
- ((PUSH_SIZE \
- + TCG_STATIC_CALL_ARGS_SIZE \
- + CPU_TEMP_BUF_NLONGS * sizeof(long) \
- + TCG_TARGET_STACK_ALIGN - 1) \
- & -TCG_TARGET_STACK_ALIGN)
-
-#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE)
-
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- /* Calling convention requires us to save r4-r11 and lr. */
- /* stmdb sp!, { r4 - r11, lr } */
- tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
-
- /* Reserve callee argument and tcg temp space. */
- tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
- TCG_REG_CALL_STACK, STACK_ADDEND, 1);
- tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
-
- tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]);
-
- /*
- * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
- * and fall through to the rest of the epilogue.
- */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0);
- tcg_out_epilogue(s);
-}
-
-static void tcg_out_epilogue(TCGContext *s)
-{
- /* Release local stack frame. */
- tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
- TCG_REG_CALL_STACK, STACK_ADDEND, 1);
-
- /* ldmia sp!, { r4 - r11, pc } */
- tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[18];
-} DebugFrame;
-
-#define ELF_HOST_MACHINE EM_ARM
-
-/* We're expecting a 2 byte uleb128 encoded value. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = 0x7c, /* sleb128 -4 */
- .h.cie.return_column = 14,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, 13, /* DW_CFA_def_cfa sp, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- /* The following must match the stmdb in the prologue. */
- 0x8e, 1, /* DW_CFA_offset, lr, -4 */
- 0x8b, 2, /* DW_CFA_offset, r11, -8 */
- 0x8a, 3, /* DW_CFA_offset, r10, -12 */
- 0x89, 4, /* DW_CFA_offset, r9, -16 */
- 0x88, 5, /* DW_CFA_offset, r8, -20 */
- 0x87, 6, /* DW_CFA_offset, r7, -24 */
- 0x86, 7, /* DW_CFA_offset, r6, -28 */
- 0x85, 8, /* DW_CFA_offset, r5, -32 */
- 0x84, 9, /* DW_CFA_offset, r4, -36 */
- }
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "../tcg-pool.c.inc"
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+#if TCG_TARGET_REG_BITS == 64
+ "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
+#else
+ "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
+#endif
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
+ "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
+#if TCG_TARGET_REG_BITS == 64
+ "%xmm8", "%xmm9", "%xmm10", "%xmm11",
+ "%xmm12", "%xmm13", "%xmm14", "%xmm15",
+#endif
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_RBP,
+ TCG_REG_RBX,
+ TCG_REG_R12,
+ TCG_REG_R13,
+ TCG_REG_R14,
+ TCG_REG_R15,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R9,
+ TCG_REG_R8,
+ TCG_REG_RCX,
+ TCG_REG_RDX,
+ TCG_REG_RSI,
+ TCG_REG_RDI,
+ TCG_REG_RAX,
+#else
+ TCG_REG_EBX,
+ TCG_REG_ESI,
+ TCG_REG_EDI,
+ TCG_REG_EBP,
+ TCG_REG_ECX,
+ TCG_REG_EDX,
+ TCG_REG_EAX,
+#endif
+ TCG_REG_XMM0,
+ TCG_REG_XMM1,
+ TCG_REG_XMM2,
+ TCG_REG_XMM3,
+ TCG_REG_XMM4,
+ TCG_REG_XMM5,
+#ifndef _WIN64
+ /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save
+ any of them. Therefore only allow xmm0-xmm5 to be allocated. */
+ TCG_REG_XMM6,
+ TCG_REG_XMM7,
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_XMM8,
+ TCG_REG_XMM9,
+ TCG_REG_XMM10,
+ TCG_REG_XMM11,
+ TCG_REG_XMM12,
+ TCG_REG_XMM13,
+ TCG_REG_XMM14,
+ TCG_REG_XMM15,
+#endif
+#endif
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+#if TCG_TARGET_REG_BITS == 64
+#if defined(_WIN64)
+ TCG_REG_RCX,
+ TCG_REG_RDX,
+#else
+ TCG_REG_RDI,
+ TCG_REG_RSI,
+ TCG_REG_RDX,
+ TCG_REG_RCX,
+#endif
+ TCG_REG_R8,
+ TCG_REG_R9,
+#else
+ /* 32 bit mode uses stack based calling convention (GCC default). */
+#endif
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_EAX,
+#if TCG_TARGET_REG_BITS == 32
+ TCG_REG_EDX
+#endif
+};
+
+/* Constants we accept. */
+#define TCG_CT_CONST_S32 0x100
+#define TCG_CT_CONST_U32 0x200
+#define TCG_CT_CONST_I32 0x400
+#define TCG_CT_CONST_WSZ 0x800
+
+/* Registers used with L constraint, which are the first argument
+ registers on x86_64, and two random call clobbered registers on
+ i386. */
+#if TCG_TARGET_REG_BITS == 64
+# define TCG_REG_L0 tcg_target_call_iarg_regs[0]
+# define TCG_REG_L1 tcg_target_call_iarg_regs[1]
+#else
+# define TCG_REG_L0 TCG_REG_EAX
+# define TCG_REG_L1 TCG_REG_EDX
+#endif
+
+/* The host compiler should supply <cpuid.h> to enable runtime features
+ detection, as we're not going to go so far as our own inline assembly.
+ If not available, default values will be assumed. */
+#if defined(CONFIG_CPUID_H)
+#include "qemu/cpuid.h"
+#endif
+
+/* For 64-bit, we always know that CMOV is available. */
+#if TCG_TARGET_REG_BITS == 64
+# define have_cmov 1
+#elif defined(CONFIG_CPUID_H)
+static bool have_cmov;
+#else
+# define have_cmov 0
+#endif
+
+/* We need these symbols in tcg-target.h, and we can't properly conditionalize
+ it there. Therefore we always define the variable. */
+bool have_bmi1;
+bool have_popcnt;
+bool have_avx1;
+bool have_avx2;
+
+#ifdef CONFIG_CPUID_H
+static bool have_movbe;
+static bool have_bmi2;
+static bool have_lzcnt;
+#else
+# define have_movbe 0
+# define have_bmi2 0
+# define have_lzcnt 0
+#endif
+
+static tcg_insn_unit *tb_ret_addr;
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ value += addend;
+ switch(type) {
+ case R_386_PC32:
+ value -= (uintptr_t)code_ptr;
+ if (value != (int32_t)value) {
+ return false;
+ }
+ /* FALLTHRU */
+ case R_386_32:
+ tcg_patch32(code_ptr, value);
+ break;
+ case R_386_PC8:
+ value -= (uintptr_t)code_ptr;
+ if (value != (int8_t)value) {
+ return false;
+ }
+ tcg_patch8(code_ptr, value);
+ break;
+ default:
+ tcg_abort();
+ }
+ return true;
+}
+
+#if TCG_TARGET_REG_BITS == 64
+#define ALL_GENERAL_REGS 0x0000ffffu
+#define ALL_VECTOR_REGS 0xffff0000u
+#else
+#define ALL_GENERAL_REGS 0x000000ffu
+#define ALL_VECTOR_REGS 0x00ff0000u
+#endif
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch(*ct_str++) {
+ case 'a':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
+ break;
+ case 'b':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
+ break;
+ case 'c':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
+ break;
+ case 'd':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
+ break;
+ case 'S':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
+ break;
+ case 'D':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
+ break;
+ case 'q':
+ /* A register that can be used as a byte operand. */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
+ break;
+ case 'Q':
+ /* A register with an addressable second byte (e.g. %ah). */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xf;
+ break;
+ case 'r':
+ /* A general register. */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= ALL_GENERAL_REGS;
+ break;
+ case 'W':
+ /* With TZCNT/LZCNT, we can have operand-size as an input. */
+ ct->ct |= TCG_CT_CONST_WSZ;
+ break;
+ case 'x':
+ /* A vector register. */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= ALL_VECTOR_REGS;
+ break;
+
+ /* qemu_ld/st address constraint */
+ case 'L':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
+ break;
+
+ case 'e':
+ ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
+ break;
+ case 'Z':
+ ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
+ break;
+ case 'I':
+ ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
+ break;
+
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* test if a constant matches the constraint */
+static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
+ return 1;
+ }
+ return 0;
+}
+
+# define LOWREGMASK(x) ((x) & 7)
+
+#define P_EXT 0x100 /* 0x0f opcode prefix */
+#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */
+#define P_DATA16 0x400 /* 0x66 opcode prefix */
+#if TCG_TARGET_REG_BITS == 64
+# define P_REXW 0x1000 /* Set REX.W = 1 */
+# define P_REXB_R 0x2000 /* REG field as byte register */
+# define P_REXB_RM 0x4000 /* R/M field as byte register */
+# define P_GS 0x8000 /* gs segment override */
+#else
+# define P_REXW 0
+# define P_REXB_R 0
+# define P_REXB_RM 0
+# define P_GS 0
+#endif
+#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */
+#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
+#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
+#define P_VEXL 0x80000 /* Set VEX.L = 1 */
+
+#define OPC_ARITH_EvIz (0x81)
+#define OPC_ARITH_EvIb (0x83)
+#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
+#define OPC_ANDN (0xf2 | P_EXT38)
+#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
+#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3))
+#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16)
+#define OPC_BSF (0xbc | P_EXT)
+#define OPC_BSR (0xbd | P_EXT)
+#define OPC_BSWAP (0xc8 | P_EXT)
+#define OPC_CALL_Jz (0xe8)
+#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */
+#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3))
+#define OPC_DEC_r32 (0x48)
+#define OPC_IMUL_GvEv (0xaf | P_EXT)
+#define OPC_IMUL_GvEvIb (0x6b)
+#define OPC_IMUL_GvEvIz (0x69)
+#define OPC_INC_r32 (0x40)
+#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */
+#define OPC_JCC_short (0x70) /* ... plus condition code */
+#define OPC_JMP_long (0xe9)
+#define OPC_JMP_short (0xeb)
+#define OPC_LEA (0x8d)
+#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3)
+#define OPC_MOVB_EvGv (0x88) /* stores, more or less */
+#define OPC_MOVL_EvGv (0x89) /* stores, more or less */
+#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */
+#define OPC_MOVB_EvIz (0xc6)
+#define OPC_MOVL_EvIz (0xc7)
+#define OPC_MOVL_Iv (0xb8)
+#define OPC_MOVBE_GyMy (0xf0 | P_EXT38)
+#define OPC_MOVBE_MyGy (0xf1 | P_EXT38)
+#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16)
+#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16)
+#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2)
+#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16)
+#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16)
+#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3)
+#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3)
+#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3)
+#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16)
+#define OPC_MOVSBL (0xbe | P_EXT)
+#define OPC_MOVSWL (0xbf | P_EXT)
+#define OPC_MOVSLQ (0x63 | P_REXW)
+#define OPC_MOVZBL (0xb6 | P_EXT)
+#define OPC_MOVZWL (0xb7 | P_EXT)
+#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16)
+#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16)
+#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16)
+#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
+#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
+#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
+#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16)
+#define OPC_PADDB (0xfc | P_EXT | P_DATA16)
+#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
+#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
+#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
+#define OPC_PADDSB (0xec | P_EXT | P_DATA16)
+#define OPC_PADDSW (0xed | P_EXT | P_DATA16)
+#define OPC_PADDUB (0xdc | P_EXT | P_DATA16)
+#define OPC_PADDUW (0xdd | P_EXT | P_DATA16)
+#define OPC_PAND (0xdb | P_EXT | P_DATA16)
+#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
+#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16)
+#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16)
+#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16)
+#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16)
+#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16)
+#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16)
+#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16)
+#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16)
+#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16)
+#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16)
+#define OPC_PMAXSW (0xee | P_EXT | P_DATA16)
+#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16)
+#define OPC_PMAXUB (0xde | P_EXT | P_DATA16)
+#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16)
+#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16)
+#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16)
+#define OPC_PMINSW (0xea | P_EXT | P_DATA16)
+#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16)
+#define OPC_PMINUB (0xda | P_EXT | P_DATA16)
+#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16)
+#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16)
+#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16)
+#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16)
+#define OPC_POR (0xeb | P_EXT | P_DATA16)
+#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16)
+#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
+#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2)
+#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3)
+#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16)
+#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16)
+#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16)
+#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16)
+#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16)
+#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16)
+#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16)
+#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16)
+#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16)
+#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
+#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
+#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16)
+#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16)
+#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16)
+#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16)
+#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16)
+#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16)
+#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16)
+#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16)
+#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16)
+#define OPC_PXOR (0xef | P_EXT | P_DATA16)
+#define OPC_POP_r32 (0x58)
+#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3)
+#define OPC_PUSH_r32 (0x50)
+#define OPC_PUSH_Iv (0x68)
+#define OPC_PUSH_Ib (0x6a)
+#define OPC_RET (0xc3)
+#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */
+#define OPC_SHIFT_1 (0xd1)
+#define OPC_SHIFT_Ib (0xc1)
+#define OPC_SHIFT_cl (0xd3)
+#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3)
+#define OPC_SHUFPS (0xc6 | P_EXT)
+#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
+#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
+#define OPC_SHRD_Ib (0xac | P_EXT)
+#define OPC_TESTL (0x85)
+#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
+#define OPC_UD2 (0x0b | P_EXT)
+#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16)
+#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16)
+#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16)
+#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16)
+#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16)
+#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
+#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
+#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
+#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW)
+#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
+#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
+#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW)
+#define OPC_VZEROUPPER (0x77 | P_EXT)
+#define OPC_XCHG_ax_r32 (0x90)
+
+#define OPC_GRP3_Ev (0xf7)
+#define OPC_GRP5 (0xff)
+#define OPC_GRP14 (0x73 | P_EXT | P_DATA16)
+
+/* Group 1 opcode extensions for 0x80-0x83.
+ These are also used as modifiers for OPC_ARITH. */
+#define ARITH_ADD 0
+#define ARITH_OR 1
+#define ARITH_ADC 2
+#define ARITH_SBB 3
+#define ARITH_AND 4
+#define ARITH_SUB 5
+#define ARITH_XOR 6
+#define ARITH_CMP 7
+
+/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */
+#define SHIFT_ROL 0
+#define SHIFT_ROR 1
+#define SHIFT_SHL 4
+#define SHIFT_SHR 5
+#define SHIFT_SAR 7
+
+/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */
+#define EXT3_NOT 2
+#define EXT3_NEG 3
+#define EXT3_MUL 4
+#define EXT3_IMUL 5
+#define EXT3_DIV 6
+#define EXT3_IDIV 7
+
+/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */
+#define EXT5_INC_Ev 0
+#define EXT5_DEC_Ev 1
+#define EXT5_CALLN_Ev 2
+#define EXT5_JMPN_Ev 4
+
+/* Condition codes to be added to OPC_JCC_{long,short}. */
+#define JCC_JMP (-1)
+#define JCC_JO 0x0
+#define JCC_JNO 0x1
+#define JCC_JB 0x2
+#define JCC_JAE 0x3
+#define JCC_JE 0x4
+#define JCC_JNE 0x5
+#define JCC_JBE 0x6
+#define JCC_JA 0x7
+#define JCC_JS 0x8
+#define JCC_JNS 0x9
+#define JCC_JP 0xa
+#define JCC_JNP 0xb
+#define JCC_JL 0xc
+#define JCC_JGE 0xd
+#define JCC_JLE 0xe
+#define JCC_JG 0xf
+
+static const uint8_t tcg_cond_to_jcc[] = {
+ [TCG_COND_EQ] = JCC_JE,
+ [TCG_COND_NE] = JCC_JNE,
+ [TCG_COND_LT] = JCC_JL,
+ [TCG_COND_GE] = JCC_JGE,
+ [TCG_COND_LE] = JCC_JLE,
+ [TCG_COND_GT] = JCC_JG,
+ [TCG_COND_LTU] = JCC_JB,
+ [TCG_COND_GEU] = JCC_JAE,
+ [TCG_COND_LEU] = JCC_JBE,
+ [TCG_COND_GTU] = JCC_JA,
+};
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
+{
+ int rex;
+
+ if (opc & P_GS) {
+ tcg_out8(s, 0x65);
+ }
+ if (opc & P_DATA16) {
+ /* We should never be asking for both 16 and 64-bit operation. */
+ tcg_debug_assert((opc & P_REXW) == 0);
+ tcg_out8(s, 0x66);
+ }
+ if (opc & P_SIMDF3) {
+ tcg_out8(s, 0xf3);
+ } else if (opc & P_SIMDF2) {
+ tcg_out8(s, 0xf2);
+ }
+
+ rex = 0;
+ rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */
+ rex |= (r & 8) >> 1; /* REX.R */
+ rex |= (x & 8) >> 2; /* REX.X */
+ rex |= (rm & 8) >> 3; /* REX.B */
+
+ /* P_REXB_{R,RM} indicates that the given register is the low byte.
+ For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
+ as otherwise the encoding indicates %[abcd]h. Note that the values
+ that are ORed in merely indicate that the REX byte must be present;
+ those bits get discarded in output. */
+ rex |= opc & (r >= 4 ? P_REXB_R : 0);
+ rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
+
+ if (rex) {
+ tcg_out8(s, (uint8_t)(rex | 0x40));
+ }
+
+ if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
+ tcg_out8(s, 0x0f);
+ if (opc & P_EXT38) {
+ tcg_out8(s, 0x38);
+ } else if (opc & P_EXT3A) {
+ tcg_out8(s, 0x3a);
+ }
+ }
+
+ tcg_out8(s, opc);
+}
+#else
+static void tcg_out_opc(TCGContext *s, int opc)
+{
+ if (opc & P_DATA16) {
+ tcg_out8(s, 0x66);
+ }
+ if (opc & P_SIMDF3) {
+ tcg_out8(s, 0xf3);
+ } else if (opc & P_SIMDF2) {
+ tcg_out8(s, 0xf2);
+ }
+ if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
+ tcg_out8(s, 0x0f);
+ if (opc & P_EXT38) {
+ tcg_out8(s, 0x38);
+ } else if (opc & P_EXT3A) {
+ tcg_out8(s, 0x3a);
+ }
+ }
+ tcg_out8(s, opc);
+}
+/* Discard the register arguments to tcg_out_opc early, so as not to penalize
+ the 32-bit compilation paths. This method works with all versions of gcc,
+ whereas relying on optimization may not be able to exclude them. */
+#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
+#endif
+
+static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
+{
+ tcg_out_opc(s, opc, r, rm, 0);
+ tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
+}
+
+static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
+ int rm, int index)
+{
+ int tmp;
+
+ /* Use the two byte form if possible, which cannot encode
+ VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
+ if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
+ && ((rm | index) & 8) == 0) {
+ /* Two byte VEX prefix. */
+ tcg_out8(s, 0xc5);
+
+ tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
+ } else {
+ /* Three byte VEX prefix. */
+ tcg_out8(s, 0xc4);
+
+ /* VEX.m-mmmm */
+ if (opc & P_EXT3A) {
+ tmp = 3;
+ } else if (opc & P_EXT38) {
+ tmp = 2;
+ } else if (opc & P_EXT) {
+ tmp = 1;
+ } else {
+ g_assert_not_reached();
+ }
+ tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
+ tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */
+ tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
+ tcg_out8(s, tmp);
+
+ tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
+ }
+
+ tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
+ /* VEX.pp */
+ if (opc & P_DATA16) {
+ tmp |= 1; /* 0x66 */
+ } else if (opc & P_SIMDF3) {
+ tmp |= 2; /* 0xf3 */
+ } else if (opc & P_SIMDF2) {
+ tmp |= 3; /* 0xf2 */
+ }
+ tmp |= (~v & 15) << 3; /* VEX.vvvv */
+ tcg_out8(s, tmp);
+ tcg_out8(s, opc);
+}
+
+static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
+{
+ tcg_out_vex_opc(s, opc, r, v, rm, 0);
+ tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
+}
+
+/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
+ We handle either RM and INDEX missing with a negative value. In 64-bit
+ mode for absolute addresses, ~RM is the size of the immediate operand
+ that will follow the instruction. */
+
+static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index,
+ int shift, intptr_t offset)
+{
+ int mod, len;
+
+ if (index < 0 && rm < 0) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* Try for a rip-relative addressing mode. This has replaced
+ the 32-bit-mode absolute addressing encoding. */
+ intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm;
+ intptr_t disp = offset - pc;
+ if (disp == (int32_t)disp) {
+ tcg_out8(s, (LOWREGMASK(r) << 3) | 5);
+ tcg_out32(s, disp);
+ return;
+ }
+
+ /* Try for an absolute address encoding. This requires the
+ use of the MODRM+SIB encoding and is therefore larger than
+ rip-relative addressing. */
+ if (offset == (int32_t)offset) {
+ tcg_out8(s, (LOWREGMASK(r) << 3) | 4);
+ tcg_out8(s, (4 << 3) | 5);
+ tcg_out32(s, offset);
+ return;
+ }
+
+ /* ??? The memory isn't directly addressable. */
+ g_assert_not_reached();
+ } else {
+ /* Absolute address. */
+ tcg_out8(s, (r << 3) | 5);
+ tcg_out32(s, offset);
+ return;
+ }
+ }
+
+ /* Find the length of the immediate addend. Note that the encoding
+ that would be used for (%ebp) indicates absolute addressing. */
+ if (rm < 0) {
+ mod = 0, len = 4, rm = 5;
+ } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) {
+ mod = 0, len = 0;
+ } else if (offset == (int8_t)offset) {
+ mod = 0x40, len = 1;
+ } else {
+ mod = 0x80, len = 4;
+ }
+
+ /* Use a single byte MODRM format if possible. Note that the encoding
+ that would be used for %esp is the escape to the two byte form. */
+ if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) {
+ /* Single byte MODRM format. */
+ tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
+ } else {
+ /* Two byte MODRM+SIB format. */
+
+ /* Note that the encoding that would place %esp into the index
+ field indicates no index register. In 64-bit mode, the REX.X
+ bit counts, so %r12 can be used as the index. */
+ if (index < 0) {
+ index = 4;
+ } else {
+ tcg_debug_assert(index != TCG_REG_ESP);
+ }
+
+ tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4);
+ tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm));
+ }
+
+ if (len == 1) {
+ tcg_out8(s, offset);
+ } else if (len == 4) {
+ tcg_out32(s, offset);
+ }
+}
+
+static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
+ int index, int shift, intptr_t offset)
+{
+ tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
+ tcg_out_sib_offset(s, r, rm, index, shift, offset);
+}
+
+static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v,
+ int rm, int index, int shift,
+ intptr_t offset)
+{
+ tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
+ tcg_out_sib_offset(s, r, rm, index, shift, offset);
+}
+
+/* A simplification of the above with no index or shift. */
+static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
+ int rm, intptr_t offset)
+{
+ tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset);
+}
+
+static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r,
+ int v, int rm, intptr_t offset)
+{
+ tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset);
+}
+
+/* Output an opcode with an expected reference to the constant pool. */
+static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r)
+{
+ tcg_out_opc(s, opc, r, 0, 0);
+ /* Absolute for 32-bit, pc-relative for 64-bit. */
+ tcg_out8(s, LOWREGMASK(r) << 3 | 5);
+ tcg_out32(s, 0);
+}
+
+/* Output an opcode with an expected reference to the constant pool. */
+static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r)
+{
+ tcg_out_vex_opc(s, opc, r, 0, 0, 0);
+ /* Absolute for 32-bit, pc-relative for 64-bit. */
+ tcg_out8(s, LOWREGMASK(r) << 3 | 5);
+ tcg_out32(s, 0);
+}
+
+/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
+static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
+{
+ /* Propagate an opcode prefix, such as P_REXW. */
+ int ext = subop & ~0x7;
+ subop &= 0x7;
+
+ tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
+}
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ int rexw = 0;
+
+ if (arg == ret) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I64:
+ rexw = P_REXW;
+ /* fallthru */
+ case TCG_TYPE_I32:
+ if (ret < 16) {
+ if (arg < 16) {
+ tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg);
+ } else {
+ tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret);
+ }
+ } else {
+ if (arg < 16) {
+ tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg);
+ } else {
+ tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
+ }
+ }
+ break;
+
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static const int avx2_dup_insn[4] = {
+ OPC_VPBROADCASTB, OPC_VPBROADCASTW,
+ OPC_VPBROADCASTD, OPC_VPBROADCASTQ,
+};
+
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg a)
+{
+ if (have_avx2) {
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+ tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a);
+ } else {
+ switch (vece) {
+ case MO_8:
+ /* ??? With zero in a register, use PSHUFB. */
+ tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);
+ a = r;
+ /* FALLTHRU */
+ case MO_16:
+ tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);
+ a = r;
+ /* FALLTHRU */
+ case MO_32:
+ tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);
+ /* imm8 operand: all output lanes selected from input lane 0. */
+ tcg_out8(s, 0);
+ break;
+ case MO_64:
+ tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ return true;
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg base, intptr_t offset)
+{
+ if (have_avx2) {
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+ tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l,
+ r, 0, base, offset);
+ } else {
+ switch (vece) {
+ case MO_64:
+ tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset);
+ break;
+ case MO_32:
+ tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);
+ break;
+ case MO_16:
+ tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset);
+ tcg_out8(s, 0); /* imm8 */
+ tcg_out_dup_vec(s, type, vece, r, r);
+ break;
+ case MO_8:
+ tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset);
+ tcg_out8(s, 0); /* imm8 */
+ tcg_out_dup_vec(s, type, vece, r, r);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ return true;
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+
+ if (arg == 0) {
+ tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret);
+ return;
+ }
+ if (arg == -1) {
+ tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret);
+ return;
+ }
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (type == TCG_TYPE_V64) {
+ tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret);
+ } else if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
+ }
+ new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
+ } else {
+ if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
+ }
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ }
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ tcg_target_long diff;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+#endif
+ if (ret < 16) {
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_dupi_vec(s, type, ret, arg);
+ return;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (arg == 0) {
+ tgen_arithr(s, ARITH_XOR, ret, ret);
+ return;
+ }
+ if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
+ tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0);
+ tcg_out32(s, arg);
+ return;
+ }
+ if (arg == (int32_t)arg) {
+ tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret);
+ tcg_out32(s, arg);
+ return;
+ }
+
+ /* Try a 7 byte pc-relative lea before the 10 byte movq. */
+ diff = arg - ((uintptr_t)s->code_ptr + 7);
+ if (diff == (int32_t)diff) {
+ tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0);
+ tcg_out8(s, (LOWREGMASK(ret) << 3) | 5);
+ tcg_out32(s, diff);
+ return;
+ }
+
+ tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0);
+ tcg_out64(s, arg);
+}
+
+static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
+{
+ if (val == (int8_t)val) {
+ tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0);
+ tcg_out8(s, val);
+ } else if (val == (int32_t)val) {
+ tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0);
+ tcg_out32(s, val);
+ } else {
+ tcg_abort();
+ }
+}
+
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ /* Given the strength of x86 memory ordering, we only need care for
+ store-load ordering. Experimentally, "lock orl $0,0(%esp)" is
+ faster than "mfence", so don't bother with the sse insn. */
+ if (a0 & TCG_MO_ST_LD) {
+ tcg_out8(s, 0xf0);
+ tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0);
+ tcg_out8(s, 0);
+ }
+}
+
+static inline void tcg_out_push(TCGContext *s, int reg)
+{
+ tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
+}
+
+static inline void tcg_out_pop(TCGContext *s, int reg)
+{
+ tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg arg1, intptr_t arg2)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
+ } else {
+ tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (ret < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2);
+ break;
+ }
+ /* FALLTHRU */
+ case TCG_TYPE_V64:
+ /* There is no instruction that can validate 8-byte alignment. */
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V128:
+ /*
+ * The gvec infrastructure is asserts that v128 vector loads
+ * and stores use a 16-byte aligned offset. Validate that the
+ * final pointer is aligned by using an insn that will SIGSEGV.
+ */
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V256:
+ /*
+ * The gvec infrastructure only requires 16-byte alignment,
+ * so here we must use an unaligned load.
+ */
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL,
+ ret, 0, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (arg < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
+ } else {
+ tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (arg < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2);
+ break;
+ }
+ /* FALLTHRU */
+ case TCG_TYPE_V64:
+ /* There is no instruction that can validate 8-byte alignment. */
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V128:
+ /*
+ * The gvec infrastructure is asserts that v128 vector loads
+ * and stores use a 16-byte aligned offset. Validate that the
+ * final pointer is aligned by using an insn that will SIGSEGV.
+ */
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V256:
+ /*
+ * The gvec infrastructure only requires 16-byte alignment,
+ * so here we must use an unaligned store.
+ */
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL,
+ arg, 0, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ int rexw = 0;
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
+ if (val != (int32_t)val) {
+ return false;
+ }
+ rexw = P_REXW;
+ } else if (type != TCG_TYPE_I32) {
+ return false;
+ }
+ tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs);
+ tcg_out32(s, val);
+ return true;
+}
+
+static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count)
+{
+ /* Propagate an opcode prefix, such as P_DATA16. */
+ int ext = subopc & ~0x7;
+ subopc &= 0x7;
+
+ if (count == 1) {
+ tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg);
+ } else {
+ tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg);
+ tcg_out8(s, count);
+ }
+}
+
+static inline void tcg_out_bswap32(TCGContext *s, int reg)
+{
+ tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0);
+}
+
+static inline void tcg_out_rolw_8(TCGContext *s, int reg)
+{
+ tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8);
+}
+
+static inline void tcg_out_ext8u(TCGContext *s, int dest, int src)
+{
+ /* movzbl */
+ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64);
+ tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src);
+}
+
+static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw)
+{
+ /* movsbl */
+ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64);
+ tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src);
+}
+
+static inline void tcg_out_ext16u(TCGContext *s, int dest, int src)
+{
+ /* movzwl */
+ tcg_out_modrm(s, OPC_MOVZWL, dest, src);
+}
+
+static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw)
+{
+ /* movsw[lq] */
+ tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src);
+}
+
+static inline void tcg_out_ext32u(TCGContext *s, int dest, int src)
+{
+ /* 32-bit mov zero extends. */
+ tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src);
+}
+
+static inline void tcg_out_ext32s(TCGContext *s, int dest, int src)
+{
+ tcg_out_modrm(s, OPC_MOVSLQ, dest, src);
+}
+
+static inline void tcg_out_bswap64(TCGContext *s, int reg)
+{
+ tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0);
+}
+
+static void tgen_arithi(TCGContext *s, int c, int r0,
+ tcg_target_long val, int cf)
+{
+ int rexw = 0;
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ rexw = c & -8;
+ c &= 7;
+ }
+
+ /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
+ partial flags update stalls on Pentium4 and are not recommended
+ by current Intel optimization manuals. */
+ if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
+ int is_inc = (c == ARITH_ADD) ^ (val < 0);
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* The single-byte increment encodings are re-tasked as the
+ REX prefixes. Use the MODRM encoding. */
+ tcg_out_modrm(s, OPC_GRP5 + rexw,
+ (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
+ } else {
+ tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
+ }
+ return;
+ }
+
+ if (c == ARITH_AND) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (val == 0xffffffffu) {
+ tcg_out_ext32u(s, r0, r0);
+ return;
+ }
+ if (val == (uint32_t)val) {
+ /* AND with no high bits set can use a 32-bit operation. */
+ rexw = 0;
+ }
+ }
+ if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) {
+ tcg_out_ext8u(s, r0, r0);
+ return;
+ }
+ if (val == 0xffffu) {
+ tcg_out_ext16u(s, r0, r0);
+ return;
+ }
+ }
+
+ if (val == (int8_t)val) {
+ tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0);
+ tcg_out8(s, val);
+ return;
+ }
+ if (rexw == 0 || val == (int32_t)val) {
+ tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0);
+ tcg_out32(s, val);
+ return;
+ }
+
+ tcg_abort();
+}
+
+static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
+{
+ if (val != 0) {
+ tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0);
+ }
+}
+
+/* Use SMALL != 0 to force a short forward branch. */
+static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small)
+{
+ int32_t val, val1;
+
+ if (l->has_value) {
+ val = tcg_pcrel_diff(s, l->u.value_ptr);
+ val1 = val - 2;
+ if ((int8_t)val1 == val1) {
+ if (opc == -1) {
+ tcg_out8(s, OPC_JMP_short);
+ } else {
+ tcg_out8(s, OPC_JCC_short + opc);
+ }
+ tcg_out8(s, val1);
+ } else {
+ if (small) {
+ tcg_abort();
+ }
+ if (opc == -1) {
+ tcg_out8(s, OPC_JMP_long);
+ tcg_out32(s, val - 5);
+ } else {
+ tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
+ tcg_out32(s, val - 6);
+ }
+ }
+ } else if (small) {
+ if (opc == -1) {
+ tcg_out8(s, OPC_JMP_short);
+ } else {
+ tcg_out8(s, OPC_JCC_short + opc);
+ }
+ tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1);
+ s->code_ptr += 1;
+ } else {
+ if (opc == -1) {
+ tcg_out8(s, OPC_JMP_long);
+ } else {
+ tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
+ }
+ tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4);
+ s->code_ptr += 4;
+ }
+}
+
+static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
+ int const_arg2, int rexw)
+{
+ if (const_arg2) {
+ if (arg2 == 0) {
+ /* test r, r */
+ tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1);
+ } else {
+ tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0);
+ }
+ } else {
+ tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2);
+ }
+}
+
+static void tcg_out_brcond32(TCGContext *s, TCGCond cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ TCGLabel *label, int small)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
+ tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small);
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_brcond64(TCGContext *s, TCGCond cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ TCGLabel *label, int small)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
+ tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small);
+}
+#else
+/* XXX: we implement it at the target level to avoid having to
+ handle cross basic blocks temporaries */
+static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
+ const int *const_args, int small)
+{
+ TCGLabel *label_next = gen_new_label();
+ TCGLabel *label_this = arg_label(args[5]);
+
+ switch(args[4]) {
+ case TCG_COND_EQ:
+ tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
+ label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3],
+ label_this, small);
+ break;
+ case TCG_COND_NE:
+ tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
+ label_this, small);
+ tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3],
+ label_this, small);
+ break;
+ case TCG_COND_LT:
+ tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_LE:
+ tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_GT:
+ tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_GE:
+ tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_LTU:
+ tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_LEU:
+ tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ case TCG_COND_GEU:
+ tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
+ label_this, small);
+ tcg_out_jxx(s, JCC_JNE, label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
+ label_this, small);
+ break;
+ default:
+ tcg_abort();
+ }
+ tcg_out_label(s, label_next, s->code_ptr);
+}
+#endif
+
+static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
+ tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
+ tcg_out_ext8u(s, dest, dest);
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
+ tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
+ tcg_out_ext8u(s, dest, dest);
+}
+#else
+static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ TCGArg new_args[6];
+ TCGLabel *label_true, *label_over;
+
+ memcpy(new_args, args+1, 5*sizeof(TCGArg));
+
+ if (args[0] == args[1] || args[0] == args[2]
+ || (!const_args[3] && args[0] == args[3])
+ || (!const_args[4] && args[0] == args[4])) {
+ /* When the destination overlaps with one of the argument
+ registers, don't do anything tricky. */
+ label_true = gen_new_label();
+ label_over = gen_new_label();
+
+ new_args[5] = label_arg(label_true);
+ tcg_out_brcond2(s, new_args, const_args+1, 1);
+
+ tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
+ tcg_out_jxx(s, JCC_JMP, label_over, 1);
+ tcg_out_label(s, label_true, s->code_ptr);
+
+ tcg_out_movi(s, TCG_TYPE_I32, args[0], 1);
+ tcg_out_label(s, label_over, s->code_ptr);
+ } else {
+ /* When the destination does not overlap one of the arguments,
+ clear the destination first, jump if cond false, and emit an
+ increment in the true case. This results in smaller code. */
+
+ tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
+
+ label_over = gen_new_label();
+ new_args[4] = tcg_invert_cond(new_args[4]);
+ new_args[5] = label_arg(label_over);
+ tcg_out_brcond2(s, new_args, const_args+1, 1);
+
+ tgen_arithi(s, ARITH_ADD, args[0], 1, 0);
+ tcg_out_label(s, label_over, s->code_ptr);
+ }
+}
+#endif
+
+static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw,
+ TCGReg dest, TCGReg v1)
+{
+ if (have_cmov) {
+ tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, v1);
+ } else {
+ TCGLabel *over = gen_new_label();
+ tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1);
+ tcg_out_mov(s, TCG_TYPE_I32, dest, v1);
+ tcg_out_label(s, over, s->code_ptr);
+ }
+}
+
+static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest,
+ TCGReg c1, TCGArg c2, int const_c2,
+ TCGReg v1)
+{
+ tcg_out_cmp(s, c1, c2, const_c2, 0);
+ tcg_out_cmov(s, cond, 0, dest, v1);
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest,
+ TCGReg c1, TCGArg c2, int const_c2,
+ TCGReg v1)
+{
+ tcg_out_cmp(s, c1, c2, const_c2, P_REXW);
+ tcg_out_cmov(s, cond, P_REXW, dest, v1);
+}
+#endif
+
+static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1,
+ TCGArg arg2, bool const_a2)
+{
+ if (have_bmi1) {
+ tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1);
+ if (const_a2) {
+ tcg_debug_assert(arg2 == (rexw ? 64 : 32));
+ } else {
+ tcg_debug_assert(dest != arg2);
+ tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2);
+ }
+ } else {
+ tcg_debug_assert(dest != arg2);
+ tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1);
+ tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2);
+ }
+}
+
+static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1,
+ TCGArg arg2, bool const_a2)
+{
+ if (have_lzcnt) {
+ tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1);
+ if (const_a2) {
+ tcg_debug_assert(arg2 == (rexw ? 64 : 32));
+ } else {
+ tcg_debug_assert(dest != arg2);
+ tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2);
+ }
+ } else {
+ tcg_debug_assert(!const_a2);
+ tcg_debug_assert(dest != arg1);
+ tcg_debug_assert(dest != arg2);
+
+ /* Recall that the output of BSR is the index not the count. */
+ tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1);
+ tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0);
+
+ /* Since we have destroyed the flags from BSR, we have to re-test. */
+ tcg_out_cmp(s, arg1, 0, 1, rexw);
+ tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2);
+ }
+}
+
+static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest)
+{
+ intptr_t disp = tcg_pcrel_diff(s, dest) - 5;
+
+ if (disp == (int32_t)disp) {
+ tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0);
+ tcg_out32(s, disp);
+ } else {
+ /* rip-relative addressing into the constant pool.
+ This is 6 + 8 = 14 bytes, as compared to using an
+ an immediate load 10 + 6 = 16 bytes, plus we may
+ be able to re-use the pool constant for more calls. */
+ tcg_out_opc(s, OPC_GRP5, 0, 0, 0);
+ tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5);
+ new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4);
+ tcg_out32(s, 0);
+ }
+}
+
+static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
+{
+ tcg_out_branch(s, 1, dest);
+}
+
+static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest)
+{
+ tcg_out_branch(s, 0, dest);
+}
+
+static void tcg_out_nopn(TCGContext *s, int n)
+{
+ int i;
+ /* Emit 1 or 2 operand size prefixes for the standard one byte nop,
+ * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the
+ * duplicate prefix, and all of the interesting recent cores can
+ * decode and discard the duplicates in a single cycle.
+ */
+ tcg_debug_assert(n >= 1);
+ for (i = 1; i < n; ++i) {
+ tcg_out8(s, 0x66);
+ }
+ tcg_out8(s, 0x90);
+}
+
+#if defined(CONFIG_SOFTMMU)
+#include "../tcg-ldst.c.inc"
+
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * int mmu_idx, uintptr_t ra)
+ */
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+};
+
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, int mmu_idx, uintptr_t ra)
+ */
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+
+/* Perform the TLB load and compare.
+
+ Inputs:
+ ADDRLO and ADDRHI contain the low and high part of the address.
+
+ MEM_INDEX and S_BITS are the memory context and log2 size of the load.
+
+ WHICH is the offset into the CPUTLBEntry structure of the slot to read.
+ This should be offsetof addr_read or addr_write.
+
+ Outputs:
+ LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
+ positions of the displacements of forward jumps to the TLB miss case.
+
+ Second argument register is loaded with the low part of the address.
+ In the TLB hit case, it has been adjusted as indicated by the TLB
+ and so is a host address. In the TLB miss case, it continues to
+ hold a guest address.
+
+ First argument register is clobbered. */
+
+static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
+ int mem_index, MemOp opc,
+ tcg_insn_unit **label_ptr, int which)
+{
+ const TCGReg r0 = TCG_REG_L0;
+ const TCGReg r1 = TCG_REG_L1;
+ TCGType ttype = TCG_TYPE_I32;
+ TCGType tlbtype = TCG_TYPE_I32;
+ int trexw = 0, hrexw = 0, tlbrexw = 0;
+ unsigned a_bits = get_alignment_bits(opc);
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_mask = (1 << a_bits) - 1;
+ unsigned s_mask = (1 << s_bits) - 1;
+ target_ulong tlb_mask;
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (TARGET_LONG_BITS == 64) {
+ ttype = TCG_TYPE_I64;
+ trexw = P_REXW;
+ }
+ if (TCG_TYPE_PTR == TCG_TYPE_I64) {
+ hrexw = P_REXW;
+ if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) {
+ tlbtype = TCG_TYPE_I64;
+ tlbrexw = P_REXW;
+ }
+ }
+ }
+
+ tcg_out_mov(s, tlbtype, r0, addrlo);
+ tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+
+ tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
+ TLB_MASK_TABLE_OFS(mem_index) +
+ offsetof(CPUTLBDescFast, mask));
+
+ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
+ TLB_MASK_TABLE_OFS(mem_index) +
+ offsetof(CPUTLBDescFast, table));
+
+ /* If the required alignment is at least as large as the access, simply
+ copy the address and mask. For lesser alignments, check that we don't
+ cross pages for the complete access. */
+ if (a_bits >= s_bits) {
+ tcg_out_mov(s, ttype, r1, addrlo);
+ } else {
+ tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_mask);
+ }
+ tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
+ tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0);
+
+ /* cmp 0(r0), r1 */
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which);
+
+ /* Prepare for both the fast path add of the tlb addend, and the slow
+ path function argument setup. */
+ tcg_out_mov(s, ttype, r1, addrlo);
+
+ /* jne slow_path */
+ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
+ label_ptr[0] = s->code_ptr;
+ s->code_ptr += 4;
+
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ /* cmp 4(r0), addrhi */
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4);
+
+ /* jne slow_path */
+ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
+ label_ptr[1] = s->code_ptr;
+ s->code_ptr += 4;
+ }
+
+ /* TLB Hit. */
+
+ /* add addend(r0), r1 */
+ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,
+ offsetof(CPUTLBEntry, addend));
+}
+
+/*
+ * Record the context of a call to the out of line helper code for the slow path
+ * for a load or store, so that we can later generate the correct helper code
+ */
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
+ TCGMemOpIdx oi,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addrhi,
+ tcg_insn_unit *raddr,
+ tcg_insn_unit **label_ptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->type = is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+ label->datalo_reg = datalo;
+ label->datahi_reg = datahi;
+ label->addrlo_reg = addrlo;
+ label->addrhi_reg = addrhi;
+ label->raddr = raddr;
+ label->label_ptr[0] = label_ptr[0];
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ label->label_ptr[1] = label_ptr[1];
+ }
+}
+
+/*
+ * Generate code for the slow path for a load at the end of block
+ */
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ TCGMemOpIdx oi = l->oi;
+ MemOp opc = get_memop(oi);
+ TCGReg data_reg;
+ tcg_insn_unit **label_ptr = &l->label_ptr[0];
+ int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);
+
+ /* resolve label address */
+ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4);
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4);
+ }
+
+ if (TCG_TARGET_REG_BITS == 32) {
+ int ofs = 0;
+
+ tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+ }
+
+ tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
+ /* The second argument is already loaded with addrlo. */
+ tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3],
+ (uintptr_t)l->raddr);
+ }
+
+ tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+
+ data_reg = l->datalo_reg;
+ switch (opc & MO_SSIZE) {
+ case MO_SB:
+ tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw);
+ break;
+ case MO_SW:
+ tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw);
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case MO_SL:
+ tcg_out_ext32s(s, data_reg, TCG_REG_EAX);
+ break;
+#endif
+ case MO_UB:
+ case MO_UW:
+ /* Note that the helpers have zero-extended to tcg_target_long. */
+ case MO_UL:
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
+ break;
+ case MO_Q:
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
+ } else if (data_reg == TCG_REG_EDX) {
+ /* xchg %edx, %eax */
+ tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0);
+ tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
+ tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX);
+ }
+ break;
+ default:
+ tcg_abort();
+ }
+
+ /* Jump to the code corresponding to next IR of qemu_st */
+ tcg_out_jmp(s, l->raddr);
+ return true;
+}
+
+/*
+ * Generate code for the slow path for a store at the end of block
+ */
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ TCGMemOpIdx oi = l->oi;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
+ tcg_insn_unit **label_ptr = &l->label_ptr[0];
+ TCGReg retaddr;
+
+ /* resolve label address */
+ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4);
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4);
+ }
+
+ if (TCG_TARGET_REG_BITS == 32) {
+ int ofs = 0;
+
+ tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+ }
+
+ tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ if (s_bits == MO_64) {
+ tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+ }
+
+ tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ retaddr = TCG_REG_EAX;
+ tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
+ tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
+ /* The second argument is already loaded with addrlo. */
+ tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+ tcg_target_call_iarg_regs[2], l->datalo_reg);
+ tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi);
+
+ if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) {
+ retaddr = tcg_target_call_iarg_regs[4];
+ tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
+ } else {
+ retaddr = TCG_REG_RAX;
+ tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
+ tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP,
+ TCG_TARGET_CALL_STACK_OFFSET);
+ }
+ }
+
+ /* "Tail call" to the helper, with the return address back inline. */
+ tcg_out_push(s, retaddr);
+ tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ return true;
+}
+#elif TCG_TARGET_REG_BITS == 32
+# define x86_guest_base_seg 0
+# define x86_guest_base_index -1
+# define x86_guest_base_offset guest_base
+#else
+static int x86_guest_base_seg;
+static int x86_guest_base_index = -1;
+static int32_t x86_guest_base_offset;
+# if defined(__x86_64__) && defined(__linux__)
+# include <asm/prctl.h>
+# include <sys/prctl.h>
+int arch_prctl(int code, unsigned long addr);
+static inline int setup_guest_base_seg(void)
+{
+ if (arch_prctl(ARCH_SET_GS, guest_base) == 0) {
+ return P_GS;
+ }
+ return 0;
+}
+# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__)
+# include <machine/sysarch.h>
+static inline int setup_guest_base_seg(void)
+{
+ if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) {
+ return P_GS;
+ }
+ return 0;
+}
+# else
+static inline int setup_guest_base_seg(void)
+{
+ return 0;
+}
+# endif
+#endif /* SOFTMMU */
+
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
+ TCGReg base, int index, intptr_t ofs,
+ int seg, bool is64, MemOp memop)
+{
+ const MemOp real_bswap = memop & MO_BSWAP;
+ MemOp bswap = real_bswap;
+ int rexw = is64 * P_REXW;
+ int movop = OPC_MOVL_GvEv;
+
+ if (have_movbe && real_bswap) {
+ bswap = 0;
+ movop = OPC_MOVBE_GyMy;
+ }
+
+ switch (memop & MO_SSIZE) {
+ case MO_UB:
+ tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo,
+ base, index, 0, ofs);
+ break;
+ case MO_SB:
+ tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo,
+ base, index, 0, ofs);
+ break;
+ case MO_UW:
+ tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo,
+ base, index, 0, ofs);
+ if (real_bswap) {
+ tcg_out_rolw_8(s, datalo);
+ }
+ break;
+ case MO_SW:
+ if (real_bswap) {
+ if (have_movbe) {
+ tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
+ datalo, base, index, 0, ofs);
+ } else {
+ tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo,
+ base, index, 0, ofs);
+ tcg_out_rolw_8(s, datalo);
+ }
+ tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo);
+ } else {
+ tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg,
+ datalo, base, index, 0, ofs);
+ }
+ break;
+ case MO_UL:
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);
+ if (bswap) {
+ tcg_out_bswap32(s, datalo);
+ }
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case MO_SL:
+ if (real_bswap) {
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo,
+ base, index, 0, ofs);
+ if (bswap) {
+ tcg_out_bswap32(s, datalo);
+ }
+ tcg_out_ext32s(s, datalo, datalo);
+ } else {
+ tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo,
+ base, index, 0, ofs);
+ }
+ break;
+#endif
+ case MO_Q:
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
+ base, index, 0, ofs);
+ if (bswap) {
+ tcg_out_bswap64(s, datalo);
+ }
+ } else {
+ if (real_bswap) {
+ int t = datalo;
+ datalo = datahi;
+ datahi = t;
+ }
+ if (base != datalo) {
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo,
+ base, index, 0, ofs);
+ tcg_out_modrm_sib_offset(s, movop + seg, datahi,
+ base, index, 0, ofs + 4);
+ } else {
+ tcg_out_modrm_sib_offset(s, movop + seg, datahi,
+ base, index, 0, ofs + 4);
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo,
+ base, index, 0, ofs);
+ }
+ if (bswap) {
+ tcg_out_bswap32(s, datalo);
+ tcg_out_bswap32(s, datahi);
+ }
+ }
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
+/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
+ EAX. It will be useful once fixed registers globals are less
+ common. */
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
+{
+ TCGReg datalo, datahi, addrlo;
+ TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
+ MemOp opc;
+#if defined(CONFIG_SOFTMMU)
+ int mem_index;
+ tcg_insn_unit *label_ptr[2];
+#endif
+
+ datalo = *args++;
+ datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
+ addrlo = *args++;
+ addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+ mem_index = get_mmuidx(oi);
+
+ tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc,
+ label_ptr, offsetof(CPUTLBEntry, addr_read));
+
+ /* TLB Hit. */
+ tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc);
+
+ /* Record the current context of a load into ldst label */
+ add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi,
+ s->code_ptr, label_ptr);
+#else
+ tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
+ x86_guest_base_offset, x86_guest_base_seg,
+ is64, opc);
+#endif
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
+ TCGReg base, int index, intptr_t ofs,
+ int seg, MemOp memop)
+{
+ /* ??? Ideally we wouldn't need a scratch register. For user-only,
+ we could perform the bswap twice to restore the original value
+ instead of moving to the scratch. But as it is, the L constraint
+ means that TCG_REG_L0 is definitely free here. */
+ const TCGReg scratch = TCG_REG_L0;
+ const MemOp real_bswap = memop & MO_BSWAP;
+ MemOp bswap = real_bswap;
+ int movop = OPC_MOVL_EvGv;
+
+ if (have_movbe && real_bswap) {
+ bswap = 0;
+ movop = OPC_MOVBE_MyGy;
+ }
+
+ switch (memop & MO_SIZE) {
+ case MO_8:
+ /* In 32-bit mode, 8-bit stores can only happen from [abcd]x.
+ Use the scratch register if necessary. */
+ if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) {
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
+ datalo = scratch;
+ }
+ tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,
+ datalo, base, index, 0, ofs);
+ break;
+ case MO_16:
+ if (bswap) {
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
+ tcg_out_rolw_8(s, scratch);
+ datalo = scratch;
+ }
+ tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo,
+ base, index, 0, ofs);
+ break;
+ case MO_32:
+ if (bswap) {
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
+ tcg_out_bswap32(s, scratch);
+ datalo = scratch;
+ }
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);
+ break;
+ case MO_64:
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (bswap) {
+ tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
+ tcg_out_bswap64(s, scratch);
+ datalo = scratch;
+ }
+ tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
+ base, index, 0, ofs);
+ } else if (bswap) {
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
+ tcg_out_bswap32(s, scratch);
+ tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch,
+ base, index, 0, ofs);
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
+ tcg_out_bswap32(s, scratch);
+ tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch,
+ base, index, 0, ofs + 4);
+ } else {
+ if (real_bswap) {
+ int t = datalo;
+ datalo = datahi;
+ datahi = t;
+ }
+ tcg_out_modrm_sib_offset(s, movop + seg, datalo,
+ base, index, 0, ofs);
+ tcg_out_modrm_sib_offset(s, movop + seg, datahi,
+ base, index, 0, ofs + 4);
+ }
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
+{
+ TCGReg datalo, datahi, addrlo;
+ TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
+ MemOp opc;
+#if defined(CONFIG_SOFTMMU)
+ int mem_index;
+ tcg_insn_unit *label_ptr[2];
+#endif
+
+ datalo = *args++;
+ datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
+ addrlo = *args++;
+ addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+ mem_index = get_mmuidx(oi);
+
+ tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc,
+ label_ptr, offsetof(CPUTLBEntry, addr_write));
+
+ /* TLB Hit. */
+ tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc);
+
+ /* Record the current context of a store into ldst label */
+ add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi,
+ s->code_ptr, label_ptr);
+#else
+ tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
+ x86_guest_base_offset, x86_guest_base_seg, opc);
+#endif
+}
+
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg *args, const int *const_args)
+{
+ TCGArg a0, a1, a2;
+ int c, const_a2, vexop, rexw = 0;
+
+#if TCG_TARGET_REG_BITS == 64
+# define OP_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i64): \
+ rexw = P_REXW; /* FALLTHRU */ \
+ case glue(glue(INDEX_op_, x), _i32)
+#else
+# define OP_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i32)
+#endif
+
+ /* Hoist the loads of the most common arguments. */
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+ const_a2 = const_args[2];
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ /* Reuse the zeroing that exists for goto_ptr. */
+ if (a0 == 0) {
+ tcg_out_jmp(s, s->code_gen_epilogue);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0);
+ tcg_out_jmp(s, tb_ret_addr);
+ }
+ break;
+ case INDEX_op_goto_tb:
+ if (s->tb_jmp_insn_offset) {
+ /* direct jump method */
+ int gap;
+ /* jump displacement must be aligned for atomic patching;
+ * see if we need to add extra nops before jump
+ */
+ gap = tcg_pcrel_diff(s, QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4));
+ if (gap != 1) {
+ tcg_out_nopn(s, gap - 1);
+ }
+ tcg_out8(s, OPC_JMP_long); /* jmp im */
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ tcg_out32(s, 0);
+ } else {
+ /* indirect jump method */
+ tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1,
+ (intptr_t)(s->tb_jmp_target_addr + a0));
+ }
+ set_jmp_reset_offset(s, a0);
+ break;
+ case INDEX_op_goto_ptr:
+ /* jmp to the given host address (could be epilogue) */
+ tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0);
+ break;
+ case INDEX_op_br:
+ tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0);
+ break;
+ OP_32_64(ld8u):
+ /* Note that we can ignore REXW for the zero-extend to 64-bit. */
+ tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2);
+ break;
+ OP_32_64(ld8s):
+ tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2);
+ break;
+ OP_32_64(ld16u):
+ /* Note that we can ignore REXW for the zero-extend to 64-bit. */
+ tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2);
+ break;
+ OP_32_64(ld16s):
+ tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2);
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_ld32u_i64:
+#endif
+ case INDEX_op_ld_i32:
+ tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2);
+ break;
+
+ OP_32_64(st8):
+ if (const_args[0]) {
+ tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2);
+ tcg_out8(s, a0);
+ } else {
+ tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2);
+ }
+ break;
+ OP_32_64(st16):
+ if (const_args[0]) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2);
+ tcg_out16(s, a0);
+ } else {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2);
+ }
+ break;
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_st32_i64:
+#endif
+ case INDEX_op_st_i32:
+ if (const_args[0]) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2);
+ tcg_out32(s, a0);
+ } else {
+ tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2);
+ }
+ break;
+
+ OP_32_64(add):
+ /* For 3-operand addition, use LEA. */
+ if (a0 != a1) {
+ TCGArg c3 = 0;
+ if (const_a2) {
+ c3 = a2, a2 = -1;
+ } else if (a0 == a2) {
+ /* Watch out for dest = src + dest, since we've removed
+ the matching constraint on the add. */
+ tgen_arithr(s, ARITH_ADD + rexw, a0, a1);
+ break;
+ }
+
+ tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3);
+ break;
+ }
+ c = ARITH_ADD;
+ goto gen_arith;
+ OP_32_64(sub):
+ c = ARITH_SUB;
+ goto gen_arith;
+ OP_32_64(and):
+ c = ARITH_AND;
+ goto gen_arith;
+ OP_32_64(or):
+ c = ARITH_OR;
+ goto gen_arith;
+ OP_32_64(xor):
+ c = ARITH_XOR;
+ goto gen_arith;
+ gen_arith:
+ if (const_a2) {
+ tgen_arithi(s, c + rexw, a0, a2, 0);
+ } else {
+ tgen_arithr(s, c + rexw, a0, a2);
+ }
+ break;
+
+ OP_32_64(andc):
+ if (const_a2) {
+ tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
+ tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0);
+ } else {
+ tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
+ }
+ break;
+
+ OP_32_64(mul):
+ if (const_a2) {
+ int32_t val;
+ val = a2;
+ if (val == (int8_t)val) {
+ tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0);
+ tcg_out8(s, val);
+ } else {
+ tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0);
+ tcg_out32(s, val);
+ }
+ } else {
+ tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2);
+ }
+ break;
+
+ OP_32_64(div2):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]);
+ break;
+ OP_32_64(divu2):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]);
+ break;
+
+ OP_32_64(shl):
+ /* For small constant 3-operand shift, use LEA. */
+ if (const_a2 && a0 != a1 && (a2 - 1) < 3) {
+ if (a2 - 1 == 0) {
+ /* shl $1,a1,a0 -> lea (a1,a1),a0 */
+ tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0);
+ } else {
+ /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */
+ tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0);
+ }
+ break;
+ }
+ c = SHIFT_SHL;
+ vexop = OPC_SHLX;
+ goto gen_shift_maybe_vex;
+ OP_32_64(shr):
+ c = SHIFT_SHR;
+ vexop = OPC_SHRX;
+ goto gen_shift_maybe_vex;
+ OP_32_64(sar):
+ c = SHIFT_SAR;
+ vexop = OPC_SARX;
+ goto gen_shift_maybe_vex;
+ OP_32_64(rotl):
+ c = SHIFT_ROL;
+ goto gen_shift;
+ OP_32_64(rotr):
+ c = SHIFT_ROR;
+ goto gen_shift;
+ gen_shift_maybe_vex:
+ if (have_bmi2) {
+ if (!const_a2) {
+ tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1);
+ break;
+ }
+ tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
+ }
+ /* FALLTHRU */
+ gen_shift:
+ if (const_a2) {
+ tcg_out_shifti(s, c + rexw, a0, a2);
+ } else {
+ tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0);
+ }
+ break;
+
+ OP_32_64(ctz):
+ tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]);
+ break;
+ OP_32_64(clz):
+ tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]);
+ break;
+ OP_32_64(ctpop):
+ tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1);
+ break;
+
+ case INDEX_op_brcond_i32:
+ tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0);
+ break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2);
+ break;
+ case INDEX_op_movcond_i32:
+ tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]);
+ break;
+
+ OP_32_64(bswap16):
+ tcg_out_rolw_8(s, a0);
+ break;
+ OP_32_64(bswap32):
+ tcg_out_bswap32(s, a0);
+ break;
+
+ OP_32_64(neg):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0);
+ break;
+ OP_32_64(not):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
+ break;
+
+ OP_32_64(ext8s):
+ tcg_out_ext8s(s, a0, a1, rexw);
+ break;
+ OP_32_64(ext16s):
+ tcg_out_ext16s(s, a0, a1, rexw);
+ break;
+ OP_32_64(ext8u):
+ tcg_out_ext8u(s, a0, a1);
+ break;
+ OP_32_64(ext16u):
+ tcg_out_ext16u(s, a0, a1);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_qemu_ld(s, args, 0);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args, 1);
+ break;
+ case INDEX_op_qemu_st_i32:
+ tcg_out_qemu_st(s, args, 0);
+ break;
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args, 1);
+ break;
+
+ OP_32_64(mulu2):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]);
+ break;
+ OP_32_64(muls2):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]);
+ break;
+ OP_32_64(add2):
+ if (const_args[4]) {
+ tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1);
+ } else {
+ tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]);
+ }
+ if (const_args[5]) {
+ tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1);
+ } else {
+ tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]);
+ }
+ break;
+ OP_32_64(sub2):
+ if (const_args[4]) {
+ tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1);
+ } else {
+ tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]);
+ }
+ if (const_args[5]) {
+ tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1);
+ } else {
+ tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]);
+ }
+ break;
+
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_brcond2_i32:
+ tcg_out_brcond2(s, args, const_args, 0);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2(s, args, const_args);
+ break;
+#else /* TCG_TARGET_REG_BITS == 64 */
+ case INDEX_op_ld32s_i64:
+ tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2);
+ break;
+ case INDEX_op_st_i64:
+ if (const_args[0]) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2);
+ tcg_out32(s, a0);
+ } else {
+ tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0);
+ break;
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2);
+ break;
+ case INDEX_op_movcond_i64:
+ tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]);
+ break;
+
+ case INDEX_op_bswap64_i64:
+ tcg_out_bswap64(s, a0);
+ break;
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extrl_i64_i32:
+ tcg_out_ext32u(s, a0, a1);
+ break;
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_ext32s_i64:
+ tcg_out_ext32s(s, a0, a1);
+ break;
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32);
+ break;
+#endif
+
+ OP_32_64(deposit):
+ if (args[3] == 0 && args[4] == 8) {
+ /* load bits 0..7 */
+ tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0);
+ } else if (args[3] == 8 && args[4] == 8) {
+ /* load bits 8..15 */
+ tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4);
+ } else if (args[3] == 0 && args[4] == 16) {
+ /* load bits 0..15 */
+ tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0);
+ } else {
+ tcg_abort();
+ }
+ break;
+
+ case INDEX_op_extract_i64:
+ if (a2 + args[3] == 32) {
+ /* This is a 32-bit zero-extending right shift. */
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tcg_out_shifti(s, SHIFT_SHR, a0, a2);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_extract_i32:
+ /* On the off-chance that we can use the high-byte registers.
+ Otherwise we emit the same ext16 + shift pattern that we
+ would have gotten from the normal tcg-op.c expansion. */
+ tcg_debug_assert(a2 == 8 && args[3] == 8);
+ if (a1 < 4 && a0 < 8) {
+ tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
+ } else {
+ tcg_out_ext16u(s, a0, a1);
+ tcg_out_shifti(s, SHIFT_SHR, a0, 8);
+ }
+ break;
+
+ case INDEX_op_sextract_i32:
+ /* We don't implement sextract_i64, as we cannot sign-extend to
+ 64-bits without using the REX prefix that explicitly excludes
+ access to the high-byte registers. */
+ tcg_debug_assert(a2 == 8 && args[3] == 8);
+ if (a1 < 4 && a0 < 8) {
+ tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4);
+ } else {
+ tcg_out_ext16s(s, a0, a1, 0);
+ tcg_out_shifti(s, SHIFT_SAR, a0, 8);
+ }
+ break;
+
+ OP_32_64(extract2):
+ /* Note that SHRD outputs to the r/m operand. */
+ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
+ tcg_out8(s, args[3]);
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+
+#undef OP_32_64
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static int const add_insn[4] = {
+ OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
+ };
+ static int const ssadd_insn[4] = {
+ OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
+ };
+ static int const usadd_insn[4] = {
+ OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2
+ };
+ static int const sub_insn[4] = {
+ OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
+ };
+ static int const sssub_insn[4] = {
+ OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
+ };
+ static int const ussub_insn[4] = {
+ OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2
+ };
+ static int const mul_insn[4] = {
+ OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
+ };
+ static int const shift_imm_insn[4] = {
+ OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
+ };
+ static int const cmpeq_insn[4] = {
+ OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ
+ };
+ static int const cmpgt_insn[4] = {
+ OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ
+ };
+ static int const punpckl_insn[4] = {
+ OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ
+ };
+ static int const punpckh_insn[4] = {
+ OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ
+ };
+ static int const packss_insn[4] = {
+ OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2
+ };
+ static int const packus_insn[4] = {
+ OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
+ };
+ static int const smin_insn[4] = {
+ OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2
+ };
+ static int const smax_insn[4] = {
+ OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2
+ };
+ static int const umin_insn[4] = {
+ OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2
+ };
+ static int const umax_insn[4] = {
+ OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
+ };
+ static int const shlv_insn[4] = {
+ /* TODO: AVX512 adds support for MO_16. */
+ OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
+ };
+ static int const shrv_insn[4] = {
+ /* TODO: AVX512 adds support for MO_16. */
+ OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
+ };
+ static int const sarv_insn[4] = {
+ /* TODO: AVX512 adds support for MO_16, MO_64. */
+ OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
+ };
+ static int const shls_insn[4] = {
+ OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
+ };
+ static int const shrs_insn[4] = {
+ OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ
+ };
+ static int const sars_insn[4] = {
+ OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
+ };
+ static int const abs_insn[4] = {
+ /* TODO: AVX512 adds support for MO_64. */
+ OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
+ };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ int insn, sub;
+ TCGArg a0, a1, a2;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_add_vec:
+ insn = add_insn[vece];
+ goto gen_simd;
+ case INDEX_op_ssadd_vec:
+ insn = ssadd_insn[vece];
+ goto gen_simd;
+ case INDEX_op_usadd_vec:
+ insn = usadd_insn[vece];
+ goto gen_simd;
+ case INDEX_op_sub_vec:
+ insn = sub_insn[vece];
+ goto gen_simd;
+ case INDEX_op_sssub_vec:
+ insn = sssub_insn[vece];
+ goto gen_simd;
+ case INDEX_op_ussub_vec:
+ insn = ussub_insn[vece];
+ goto gen_simd;
+ case INDEX_op_mul_vec:
+ insn = mul_insn[vece];
+ goto gen_simd;
+ case INDEX_op_and_vec:
+ insn = OPC_PAND;
+ goto gen_simd;
+ case INDEX_op_or_vec:
+ insn = OPC_POR;
+ goto gen_simd;
+ case INDEX_op_xor_vec:
+ insn = OPC_PXOR;
+ goto gen_simd;
+ case INDEX_op_smin_vec:
+ insn = smin_insn[vece];
+ goto gen_simd;
+ case INDEX_op_umin_vec:
+ insn = umin_insn[vece];
+ goto gen_simd;
+ case INDEX_op_smax_vec:
+ insn = smax_insn[vece];
+ goto gen_simd;
+ case INDEX_op_umax_vec:
+ insn = umax_insn[vece];
+ goto gen_simd;
+ case INDEX_op_shlv_vec:
+ insn = shlv_insn[vece];
+ goto gen_simd;
+ case INDEX_op_shrv_vec:
+ insn = shrv_insn[vece];
+ goto gen_simd;
+ case INDEX_op_sarv_vec:
+ insn = sarv_insn[vece];
+ goto gen_simd;
+ case INDEX_op_shls_vec:
+ insn = shls_insn[vece];
+ goto gen_simd;
+ case INDEX_op_shrs_vec:
+ insn = shrs_insn[vece];
+ goto gen_simd;
+ case INDEX_op_sars_vec:
+ insn = sars_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_punpckl_vec:
+ insn = punpckl_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_punpckh_vec:
+ insn = punpckh_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_packss_vec:
+ insn = packss_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_packus_vec:
+ insn = packus_insn[vece];
+ goto gen_simd;
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_dup2_vec:
+ /* First merge the two 32-bit inputs to a single 64-bit element. */
+ tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2);
+ /* Then replicate the 64-bit elements across the rest of the vector. */
+ if (type != TCG_TYPE_V64) {
+ tcg_out_dup_vec(s, type, MO_64, a0, a0);
+ }
+ break;
+#endif
+ case INDEX_op_abs_vec:
+ insn = abs_insn[vece];
+ a2 = a1;
+ a1 = 0;
+ goto gen_simd;
+ gen_simd:
+ tcg_debug_assert(insn != OPC_UD2);
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ break;
+
+ case INDEX_op_cmp_vec:
+ sub = args[3];
+ if (sub == TCG_COND_EQ) {
+ insn = cmpeq_insn[vece];
+ } else if (sub == TCG_COND_GT) {
+ insn = cmpgt_insn[vece];
+ } else {
+ g_assert_not_reached();
+ }
+ goto gen_simd;
+
+ case INDEX_op_andc_vec:
+ insn = OPC_PANDN;
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a2, a1);
+ break;
+
+ case INDEX_op_shli_vec:
+ sub = 6;
+ goto gen_shift;
+ case INDEX_op_shri_vec:
+ sub = 2;
+ goto gen_shift;
+ case INDEX_op_sari_vec:
+ tcg_debug_assert(vece != MO_64);
+ sub = 4;
+ gen_shift:
+ tcg_debug_assert(vece != MO_8);
+ insn = shift_imm_insn[vece];
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, sub, a0, a1);
+ tcg_out8(s, a2);
+ break;
+
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_dupm_vec:
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+ break;
+
+ case INDEX_op_x86_shufps_vec:
+ insn = OPC_SHUFPS;
+ sub = args[3];
+ goto gen_simd_imm8;
+ case INDEX_op_x86_blend_vec:
+ if (vece == MO_16) {
+ insn = OPC_PBLENDW;
+ } else if (vece == MO_32) {
+ insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);
+ } else {
+ g_assert_not_reached();
+ }
+ sub = args[3];
+ goto gen_simd_imm8;
+ case INDEX_op_x86_vperm2i128_vec:
+ insn = OPC_VPERM2I128;
+ sub = args[3];
+ goto gen_simd_imm8;
+ gen_simd_imm8:
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ tcg_out8(s, sub);
+ break;
+
+ case INDEX_op_x86_vpblendvb_vec:
+ insn = OPC_VPBLENDVB;
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ tcg_out8(s, args[3] << 4);
+ break;
+
+ case INDEX_op_x86_psrldq_vec:
+ tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1);
+ tcg_out8(s, a2);
+ break;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
+ static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
+ static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
+ static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
+ static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
+ static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
+ static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
+ static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
+ static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
+ static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
+ static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
+ static const TCGTargetOpDef r_r_L_L
+ = { .args_ct_str = { "r", "r", "L", "L" } };
+ static const TCGTargetOpDef L_L_L_L
+ = { .args_ct_str = { "L", "L", "L", "L" } };
+ static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
+ static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
+ static const TCGTargetOpDef x_x_x_x
+ = { .args_ct_str = { "x", "x", "x", "x" } };
+ static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ return &r_r;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ return &qi_r;
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ return &ri_r;
+ case INDEX_op_st_i64:
+ return &re_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ return &r_r_re;
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ return &r_0_re;
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ {
+ static const TCGTargetOpDef and
+ = { .args_ct_str = { "r", "0", "reZ" } };
+ return ∧
+ }
+ break;
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ {
+ static const TCGTargetOpDef andc
+ = { .args_ct_str = { "r", "r", "rI" } };
+ return &andc;
+ }
+ break;
+
+ case INDEX_op_shl_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i32:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i32:
+ case INDEX_op_sar_i64:
+ return have_bmi2 ? &r_r_ri : &r_0_ci;
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ return &r_0_ci;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &r_re;
+
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ case INDEX_op_extrh_i64_i32:
+ return &r_0;
+
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ return &r_q;
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i32:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_ctpop_i64:
+ return &r_r;
+ case INDEX_op_extract2_i32:
+ case INDEX_op_extract2_i64:
+ return &r_0_r;
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ {
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "Q", "0", "Q" } };
+ return &dep;
+ }
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ {
+ static const TCGTargetOpDef setc
+ = { .args_ct_str = { "q", "r", "re" } };
+ return &setc;
+ }
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ {
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "re", "r", "0" } };
+ return &movc;
+ }
+ case INDEX_op_div2_i32:
+ case INDEX_op_div2_i64:
+ case INDEX_op_divu2_i32:
+ case INDEX_op_divu2_i64:
+ {
+ static const TCGTargetOpDef div2
+ = { .args_ct_str = { "a", "d", "0", "1", "r" } };
+ return &div2;
+ }
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_mulu2_i64:
+ case INDEX_op_muls2_i32:
+ case INDEX_op_muls2_i64:
+ {
+ static const TCGTargetOpDef mul2
+ = { .args_ct_str = { "a", "d", "a", "r" } };
+ return &mul2;
+ }
+ case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
+ {
+ static const TCGTargetOpDef arith2
+ = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
+ return &arith2;
+ }
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
+ {
+ static const TCGTargetOpDef ctz[2] = {
+ { .args_ct_str = { "&r", "r", "r" } },
+ { .args_ct_str = { "&r", "r", "rW" } },
+ };
+ return &ctz[have_bmi1];
+ }
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ {
+ static const TCGTargetOpDef clz[2] = {
+ { .args_ct_str = { "&r", "r", "r" } },
+ { .args_ct_str = { "&r", "r", "rW" } },
+ };
+ return &clz[have_lzcnt];
+ }
+
+ case INDEX_op_qemu_ld_i32:
+ return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ case INDEX_op_qemu_st_i32:
+ return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &r_L
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
+ : &r_r_L_L);
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &L_L
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
+ : &L_L_L_L);
+
+ case INDEX_op_brcond2_i32:
+ {
+ static const TCGTargetOpDef b2
+ = { .args_ct_str = { "r", "r", "ri", "ri" } };
+ return &b2;
+ }
+ case INDEX_op_setcond2_i32:
+ {
+ static const TCGTargetOpDef s2
+ = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
+ return &s2;
+ }
+
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ case INDEX_op_dupm_vec:
+ return &x_r;
+
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_ussub_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_shls_vec:
+ case INDEX_op_shrs_vec:
+ case INDEX_op_sars_vec:
+ case INDEX_op_rotls_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_x86_shufps_vec:
+ case INDEX_op_x86_blend_vec:
+ case INDEX_op_x86_packss_vec:
+ case INDEX_op_x86_packus_vec:
+ case INDEX_op_x86_vperm2i128_vec:
+ case INDEX_op_x86_punpckl_vec:
+ case INDEX_op_x86_punpckh_vec:
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_dup2_vec:
+#endif
+ return &x_x_x;
+ case INDEX_op_abs_vec:
+ case INDEX_op_dup_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_x86_psrldq_vec:
+ return &x_x;
+ case INDEX_op_x86_vpblendvb_vec:
+ return &x_x_x_x;
+
+ default:
+ break;
+ }
+ return NULL;
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ return 1;
+ case INDEX_op_rotli_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_cmpsel_vec:
+ return -1;
+
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ /* We must expand the operation for MO_8. */
+ return vece == MO_8 ? -1 : 1;
+
+ case INDEX_op_sari_vec:
+ /* We must expand the operation for MO_8. */
+ if (vece == MO_8) {
+ return -1;
+ }
+ /* We can emulate this for MO_64, but it does not pay off
+ unless we're producing at least 4 values. */
+ if (vece == MO_64) {
+ return type >= TCG_TYPE_V256 ? -1 : 0;
+ }
+ return 1;
+
+ case INDEX_op_shls_vec:
+ case INDEX_op_shrs_vec:
+ return vece >= MO_16;
+ case INDEX_op_sars_vec:
+ return vece >= MO_16 && vece <= MO_32;
+ case INDEX_op_rotls_vec:
+ return vece >= MO_16 ? -1 : 0;
+
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ return have_avx2 && vece >= MO_32;
+ case INDEX_op_sarv_vec:
+ return have_avx2 && vece == MO_32;
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
+ return have_avx2 && vece >= MO_32 ? -1 : 0;
+
+ case INDEX_op_mul_vec:
+ if (vece == MO_8) {
+ /* We can expand the operation for MO_8. */
+ return -1;
+ }
+ if (vece == MO_64) {
+ return 0;
+ }
+ return 1;
+
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_ussub_vec:
+ return vece <= MO_16;
+ case INDEX_op_smin_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_abs_vec:
+ return vece <= MO_32;
+
+ default:
+ return 0;
+ }
+}
+
+static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc,
+ TCGv_vec v0, TCGv_vec v1, TCGArg imm)
+{
+ TCGv_vec t1, t2;
+
+ tcg_debug_assert(vece == MO_8);
+
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+
+ /*
+ * Unpack to W, shift, and repack. Tricky bits:
+ * (1) Use punpck*bw x,x to produce DDCCBBAA,
+ * i.e. duplicate in other half of the 16-bit lane.
+ * (2) For right-shift, add 8 so that the high half of the lane
+ * becomes zero. For left-shift, and left-rotate, we must
+ * shift up and down again.
+ * (3) Step 2 leaves high half zero such that PACKUSWB
+ * (pack with unsigned saturation) does not modify
+ * the quantity.
+ */
+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+
+ if (opc != INDEX_op_rotli_vec) {
+ imm += 8;
+ }
+ if (opc == INDEX_op_shri_vec) {
+ tcg_gen_shri_vec(MO_16, t1, t1, imm);
+ tcg_gen_shri_vec(MO_16, t2, t2, imm);
+ } else {
+ tcg_gen_shli_vec(MO_16, t1, t1, imm);
+ tcg_gen_shli_vec(MO_16, t2, t2, imm);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ tcg_gen_shri_vec(MO_16, t2, t2, 8);
+ }
+
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+}
+
+static void expand_vec_sari(TCGType type, unsigned vece,
+ TCGv_vec v0, TCGv_vec v1, TCGArg imm)
+{
+ TCGv_vec t1, t2;
+
+ switch (vece) {
+ case MO_8:
+ /* Unpack to W, shift, and repack, as in expand_vec_shi. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
+ tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);
+ tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);
+ vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ case MO_64:
+ if (imm <= 32) {
+ /*
+ * We can emulate a small sign extend by performing an arithmetic
+ * 32-bit shift and overwriting the high half of a 64-bit logical
+ * shift. Note that the ISA says shift of 32 is valid, but TCG
+ * does not, so we have to bound the smaller shift -- we get the
+ * same result in the high half either way.
+ */
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
+ tcg_gen_shri_vec(MO_64, v0, v1, imm);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ tcgv_vec_arg(v0), tcgv_vec_arg(v0),
+ tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ } else {
+ /* Otherwise we will need to use a compare vs 0 to produce
+ * the sign-extend, shift and merge.
+ */
+ t1 = tcg_const_zeros_vec(type);
+ tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
+ tcg_gen_shri_vec(MO_64, v0, v1, imm);
+ tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
+ tcg_gen_or_vec(MO_64, v0, v0, t1);
+ tcg_temp_free_vec(t1);
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void expand_vec_rotli(TCGType type, unsigned vece,
+ TCGv_vec v0, TCGv_vec v1, TCGArg imm)
+{
+ TCGv_vec t;
+
+ if (vece == MO_8) {
+ expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm);
+ return;
+ }
+
+ t = tcg_temp_new_vec(type);
+ tcg_gen_shli_vec(vece, t, v1, imm);
+ tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
+ tcg_gen_or_vec(vece, v0, v0, t);
+ tcg_temp_free_vec(t);
+}
+
+static void expand_vec_rotls(TCGType type, unsigned vece,
+ TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
+{
+ TCGv_i32 rsh;
+ TCGv_vec t;
+
+ tcg_debug_assert(vece != MO_8);
+
+ t = tcg_temp_new_vec(type);
+ rsh = tcg_temp_new_i32();
+
+ tcg_gen_neg_i32(rsh, lsh);
+ tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
+ tcg_gen_shls_vec(vece, t, v1, lsh);
+ tcg_gen_shrs_vec(vece, v0, v1, rsh);
+ tcg_gen_or_vec(vece, v0, v0, t);
+ tcg_temp_free_vec(t);
+ tcg_temp_free_i32(rsh);
+}
+
+static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec sh, bool right)
+{
+ TCGv_vec t = tcg_temp_new_vec(type);
+
+ tcg_gen_dupi_vec(vece, t, 8 << vece);
+ tcg_gen_sub_vec(vece, t, t, sh);
+ if (right) {
+ tcg_gen_shlv_vec(vece, t, v1, t);
+ tcg_gen_shrv_vec(vece, v0, v1, sh);
+ } else {
+ tcg_gen_shrv_vec(vece, t, v1, t);
+ tcg_gen_shlv_vec(vece, v0, v1, sh);
+ }
+ tcg_gen_or_vec(vece, v0, v0, t);
+ tcg_temp_free_vec(t);
+}
+
+static void expand_vec_mul(TCGType type, unsigned vece,
+ TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
+{
+ TCGv_vec t1, t2, t3, t4;
+
+ tcg_debug_assert(vece == MO_8);
+
+ /*
+ * Unpack v1 bytes to words, 0 | x.
+ * Unpack v2 bytes to words, y | 0.
+ * This leaves the 8-bit result, x * y, with 8 bits of right padding.
+ * Shift logical right by 8 bits to clear the high 8 bytes before
+ * using an unsigned saturated pack.
+ *
+ * The difference between the V64, V128 and V256 cases is merely how
+ * we distribute the expansion between temporaries.
+ */
+ switch (type) {
+ case TCG_TYPE_V64:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t2, 0);
+ vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ t3 = tcg_temp_new_vec(type);
+ t4 = tcg_temp_new_vec(type);
+ tcg_gen_dup16i_vec(t4, 0);
+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
+ tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
+ tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_mul_vec(MO_16, t3, t3, t4);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ tcg_gen_shri_vec(MO_16, t3, t3, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
+{
+ enum {
+ NEED_INV = 1,
+ NEED_SWAP = 2,
+ NEED_BIAS = 4,
+ NEED_UMIN = 8,
+ NEED_UMAX = 16,
+ };
+ TCGv_vec t1, t2;
+ uint8_t fixup;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_GT:
+ fixup = 0;
+ break;
+ case TCG_COND_NE:
+ case TCG_COND_LE:
+ fixup = NEED_INV;
+ break;
+ case TCG_COND_LT:
+ fixup = NEED_SWAP;
+ break;
+ case TCG_COND_GE:
+ fixup = NEED_SWAP | NEED_INV;
+ break;
+ case TCG_COND_LEU:
+ if (vece <= MO_32) {
+ fixup = NEED_UMIN;
+ } else {
+ fixup = NEED_BIAS | NEED_INV;
+ }
+ break;
+ case TCG_COND_GTU:
+ if (vece <= MO_32) {
+ fixup = NEED_UMIN | NEED_INV;
+ } else {
+ fixup = NEED_BIAS;
+ }
+ break;
+ case TCG_COND_GEU:
+ if (vece <= MO_32) {
+ fixup = NEED_UMAX;
+ } else {
+ fixup = NEED_BIAS | NEED_SWAP | NEED_INV;
+ }
+ break;
+ case TCG_COND_LTU:
+ if (vece <= MO_32) {
+ fixup = NEED_UMAX | NEED_INV;
+ } else {
+ fixup = NEED_BIAS | NEED_SWAP;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (fixup & NEED_INV) {
+ cond = tcg_invert_cond(cond);
+ }
+ if (fixup & NEED_SWAP) {
+ t1 = v1, v1 = v2, v2 = t1;
+ cond = tcg_swap_cond(cond);
+ }
+
+ t1 = t2 = NULL;
+ if (fixup & (NEED_UMIN | NEED_UMAX)) {
+ t1 = tcg_temp_new_vec(type);
+ if (fixup & NEED_UMIN) {
+ tcg_gen_umin_vec(vece, t1, v1, v2);
+ } else {
+ tcg_gen_umax_vec(vece, t1, v1, v2);
+ }
+ v2 = t1;
+ cond = TCG_COND_EQ;
+ } else if (fixup & NEED_BIAS) {
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
+ tcg_gen_sub_vec(vece, t1, v1, t2);
+ tcg_gen_sub_vec(vece, t2, v2, t2);
+ v1 = t1;
+ v2 = t2;
+ cond = tcg_signed_cond(cond);
+ }
+
+ tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT);
+ /* Expand directly; do not recurse. */
+ vec_gen_4(INDEX_op_cmp_vec, type, vece,
+ tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
+
+ if (t1) {
+ tcg_temp_free_vec(t1);
+ if (t2) {
+ tcg_temp_free_vec(t2);
+ }
+ }
+ return fixup & NEED_INV;
+}
+
+static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
+{
+ if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) {
+ tcg_gen_not_vec(vece, v0, v0);
+ }
+}
+
+static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec c1, TCGv_vec c2,
+ TCGv_vec v3, TCGv_vec v4, TCGCond cond)
+{
+ TCGv_vec t = tcg_temp_new_vec(type);
+
+ if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
+ /* Invert the sense of the compare by swapping arguments. */
+ TCGv_vec x;
+ x = v3, v3 = v4, v4 = x;
+ }
+ vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece,
+ tcgv_vec_arg(v0), tcgv_vec_arg(v4),
+ tcgv_vec_arg(v3), tcgv_vec_arg(t));
+ tcg_temp_free_vec(t);
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ va_list va;
+ TCGArg a2;
+ TCGv_vec v0, v1, v2, v3, v4;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ a2 = va_arg(va, TCGArg);
+
+ switch (opc) {
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ expand_vec_shi(type, vece, opc, v0, v1, a2);
+ break;
+
+ case INDEX_op_sari_vec:
+ expand_vec_sari(type, vece, v0, v1, a2);
+ break;
+
+ case INDEX_op_rotli_vec:
+ expand_vec_rotli(type, vece, v0, v1, a2);
+ break;
+
+ case INDEX_op_rotls_vec:
+ expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2)));
+ break;
+
+ case INDEX_op_rotlv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_rotv(type, vece, v0, v1, v2, false);
+ break;
+ case INDEX_op_rotrv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_rotv(type, vece, v0, v1, v2, true);
+ break;
+
+ case INDEX_op_mul_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_mul(type, vece, v0, v1, v2);
+ break;
+
+ case INDEX_op_cmp_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
+ break;
+
+ case INDEX_op_cmpsel_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
+ break;
+
+ default:
+ break;
+ }
+
+ va_end(va);
+}
+
+static const int tcg_target_callee_save_regs[] = {
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_RBP,
+ TCG_REG_RBX,
+#if defined(_WIN64)
+ TCG_REG_RDI,
+ TCG_REG_RSI,
+#endif
+ TCG_REG_R12,
+ TCG_REG_R13,
+ TCG_REG_R14, /* Currently used for the global env. */
+ TCG_REG_R15,
+#else
+ TCG_REG_EBP, /* Currently used for the global env. */
+ TCG_REG_EBX,
+ TCG_REG_ESI,
+ TCG_REG_EDI,
+#endif
+};
+
+/* Compute frame size via macros, to share between tcg_target_qemu_prologue
+ and tcg_register_jit. */
+
+#define PUSH_SIZE \
+ ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \
+ * (TCG_TARGET_REG_BITS / 8))
+
+#define FRAME_SIZE \
+ ((PUSH_SIZE \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_NLONGS * sizeof(long) \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & ~(TCG_TARGET_STACK_ALIGN - 1))
+
+/* Generate global QEMU prologue and epilogue code */
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ int i, stack_addend;
+
+ /* TB prologue */
+
+ /* Reserve some stack space, also for TCG temps. */
+ stack_addend = FRAME_SIZE - PUSH_SIZE;
+ tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
+
+ /* Save all callee saved registers. */
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_push(s, tcg_target_callee_save_regs[i]);
+ }
+
+#if TCG_TARGET_REG_BITS == 32
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
+ (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
+ tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
+ /* jmp *tb. */
+ tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
+ (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ + stack_addend);
+#else
+# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64
+ if (guest_base) {
+ int seg = setup_guest_base_seg();
+ if (seg != 0) {
+ x86_guest_base_seg = seg;
+ } else if (guest_base == (int32_t)guest_base) {
+ x86_guest_base_offset = guest_base;
+ } else {
+ /* Choose R12 because, as a base, it requires a SIB byte. */
+ x86_guest_base_index = TCG_REG_R12;
+ tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index);
+ }
+ }
+# endif
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+ tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
+ /* jmp *tb. */
+ tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
+#endif
+
+ /*
+ * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
+ * and fall through to the rest of the epilogue.
+ */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0);
+
+ /* TB epilogue */
+ tb_ret_addr = s->code_ptr;
+
+ tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend);
+
+ if (have_avx2) {
+ tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0);
+ }
+ for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
+ tcg_out_pop(s, tcg_target_callee_save_regs[i]);
+ }
+ tcg_out_opc(s, OPC_RET, 0, 0, 0);
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ memset(p, 0x90, count);
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+#ifdef CONFIG_CPUID_H
+ unsigned a, b, c, d, b7 = 0;
+ int max = __get_cpuid_max(0, 0);
+
+ if (max >= 7) {
+ /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
+ __cpuid_count(7, 0, a, b7, c, d);
+ have_bmi1 = (b7 & bit_BMI) != 0;
+ have_bmi2 = (b7 & bit_BMI2) != 0;
+ }
+
+ if (max >= 1) {
+ __cpuid(1, a, b, c, d);
+#ifndef have_cmov
+ /* For 32-bit, 99% certainty that we're running on hardware that
+ supports cmov, but we still need to check. In case cmov is not
+ available, we'll use a small forward branch. */
+ have_cmov = (d & bit_CMOV) != 0;
+#endif
+
+ /* MOVBE is only available on Intel Atom and Haswell CPUs, so we
+ need to probe for it. */
+ have_movbe = (c & bit_MOVBE) != 0;
+ have_popcnt = (c & bit_POPCNT) != 0;
+
+ /* There are a number of things we must check before we can be
+ sure of not hitting invalid opcode. */
+ if (c & bit_OSXSAVE) {
+ unsigned xcrl, xcrh;
+ /* The xgetbv instruction is not available to older versions of
+ * the assembler, so we encode the instruction manually.
+ */
+ asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0));
+ if ((xcrl & 6) == 6) {
+ have_avx1 = (c & bit_AVX) != 0;
+ have_avx2 = (b7 & bit_AVX2) != 0;
+ }
+ }
+ }
+
+ max = __get_cpuid_max(0x8000000, 0);
+ if (max >= 1) {
+ __cpuid(0x80000001, a, b, c, d);
+ /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs. */
+ have_lzcnt = (c & bit_LZCNT) != 0;
+ }
+#endif /* CONFIG_CPUID_H */
+
+ tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
+ }
+ if (have_avx1) {
+ tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
+ tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
+ }
+ if (have_avx2) {
+ tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
+ }
+
+ tcg_target_call_clobber_regs = ALL_VECTOR_REGS;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
+ if (TCG_TARGET_REG_BITS == 64) {
+#if !defined(_WIN64)
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI);
+#endif
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
+ }
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[14];
+} DebugFrame;
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+#if !defined(__ELF__)
+ /* Host machine without ELF. */
+#elif TCG_TARGET_REG_BITS == 64
+#define ELF_HOST_MACHINE EM_X86_64
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = 0x78, /* sleb128 -8 */
+ .h.cie.return_column = 16,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, 7, /* DW_CFA_def_cfa %rsp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x90, 1, /* DW_CFA_offset, %rip, -8 */
+ /* The following ordering must match tcg_target_callee_save_regs. */
+ 0x86, 2, /* DW_CFA_offset, %rbp, -16 */
+ 0x83, 3, /* DW_CFA_offset, %rbx, -24 */
+ 0x8c, 4, /* DW_CFA_offset, %r12, -32 */
+ 0x8d, 5, /* DW_CFA_offset, %r13, -40 */
+ 0x8e, 6, /* DW_CFA_offset, %r14, -48 */
+ 0x8f, 7, /* DW_CFA_offset, %r15, -56 */
+ }
+};
+#else
+#define ELF_HOST_MACHINE EM_386
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = 0x7c, /* sleb128 -4 */
+ .h.cie.return_column = 8,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, 4, /* DW_CFA_def_cfa %esp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x88, 1, /* DW_CFA_offset, %eip, -4 */
+ /* The following ordering must match tcg_target_callee_save_regs. */
+ 0x85, 2, /* DW_CFA_offset, %ebp, -8 */
+ 0x83, 3, /* DW_CFA_offset, %ebx, -12 */
+ 0x86, 4, /* DW_CFA_offset, %esi, -16 */
+ 0x87, 5, /* DW_CFA_offset, %edi, -20 */
+ }
+};
+#endif
+
+#if defined(ELF_HOST_MACHINE)
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+#endif
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "../tcg-pool.inc.c"
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-#if TCG_TARGET_REG_BITS == 64
- "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
-#else
- "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
-#endif
- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
- "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
-#if TCG_TARGET_REG_BITS == 64
- "%xmm8", "%xmm9", "%xmm10", "%xmm11",
- "%xmm12", "%xmm13", "%xmm14", "%xmm15",
-#endif
-};
-#endif
-
-static const int tcg_target_reg_alloc_order[] = {
-#if TCG_TARGET_REG_BITS == 64
- TCG_REG_RBP,
- TCG_REG_RBX,
- TCG_REG_R12,
- TCG_REG_R13,
- TCG_REG_R14,
- TCG_REG_R15,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R9,
- TCG_REG_R8,
- TCG_REG_RCX,
- TCG_REG_RDX,
- TCG_REG_RSI,
- TCG_REG_RDI,
- TCG_REG_RAX,
-#else
- TCG_REG_EBX,
- TCG_REG_ESI,
- TCG_REG_EDI,
- TCG_REG_EBP,
- TCG_REG_ECX,
- TCG_REG_EDX,
- TCG_REG_EAX,
-#endif
- TCG_REG_XMM0,
- TCG_REG_XMM1,
- TCG_REG_XMM2,
- TCG_REG_XMM3,
- TCG_REG_XMM4,
- TCG_REG_XMM5,
-#ifndef _WIN64
- /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save
- any of them. Therefore only allow xmm0-xmm5 to be allocated. */
- TCG_REG_XMM6,
- TCG_REG_XMM7,
-#if TCG_TARGET_REG_BITS == 64
- TCG_REG_XMM8,
- TCG_REG_XMM9,
- TCG_REG_XMM10,
- TCG_REG_XMM11,
- TCG_REG_XMM12,
- TCG_REG_XMM13,
- TCG_REG_XMM14,
- TCG_REG_XMM15,
-#endif
-#endif
-};
-
-static const int tcg_target_call_iarg_regs[] = {
-#if TCG_TARGET_REG_BITS == 64
-#if defined(_WIN64)
- TCG_REG_RCX,
- TCG_REG_RDX,
-#else
- TCG_REG_RDI,
- TCG_REG_RSI,
- TCG_REG_RDX,
- TCG_REG_RCX,
-#endif
- TCG_REG_R8,
- TCG_REG_R9,
-#else
- /* 32 bit mode uses stack based calling convention (GCC default). */
-#endif
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_EAX,
-#if TCG_TARGET_REG_BITS == 32
- TCG_REG_EDX
-#endif
-};
-
-/* Constants we accept. */
-#define TCG_CT_CONST_S32 0x100
-#define TCG_CT_CONST_U32 0x200
-#define TCG_CT_CONST_I32 0x400
-#define TCG_CT_CONST_WSZ 0x800
-
-/* Registers used with L constraint, which are the first argument
- registers on x86_64, and two random call clobbered registers on
- i386. */
-#if TCG_TARGET_REG_BITS == 64
-# define TCG_REG_L0 tcg_target_call_iarg_regs[0]
-# define TCG_REG_L1 tcg_target_call_iarg_regs[1]
-#else
-# define TCG_REG_L0 TCG_REG_EAX
-# define TCG_REG_L1 TCG_REG_EDX
-#endif
-
-/* The host compiler should supply <cpuid.h> to enable runtime features
- detection, as we're not going to go so far as our own inline assembly.
- If not available, default values will be assumed. */
-#if defined(CONFIG_CPUID_H)
-#include "qemu/cpuid.h"
-#endif
-
-/* For 64-bit, we always know that CMOV is available. */
-#if TCG_TARGET_REG_BITS == 64
-# define have_cmov 1
-#elif defined(CONFIG_CPUID_H)
-static bool have_cmov;
-#else
-# define have_cmov 0
-#endif
-
-/* We need these symbols in tcg-target.h, and we can't properly conditionalize
- it there. Therefore we always define the variable. */
-bool have_bmi1;
-bool have_popcnt;
-bool have_avx1;
-bool have_avx2;
-
-#ifdef CONFIG_CPUID_H
-static bool have_movbe;
-static bool have_bmi2;
-static bool have_lzcnt;
-#else
-# define have_movbe 0
-# define have_bmi2 0
-# define have_lzcnt 0
-#endif
-
-static tcg_insn_unit *tb_ret_addr;
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- value += addend;
- switch(type) {
- case R_386_PC32:
- value -= (uintptr_t)code_ptr;
- if (value != (int32_t)value) {
- return false;
- }
- /* FALLTHRU */
- case R_386_32:
- tcg_patch32(code_ptr, value);
- break;
- case R_386_PC8:
- value -= (uintptr_t)code_ptr;
- if (value != (int8_t)value) {
- return false;
- }
- tcg_patch8(code_ptr, value);
- break;
- default:
- tcg_abort();
- }
- return true;
-}
-
-#if TCG_TARGET_REG_BITS == 64
-#define ALL_GENERAL_REGS 0x0000ffffu
-#define ALL_VECTOR_REGS 0xffff0000u
-#else
-#define ALL_GENERAL_REGS 0x000000ffu
-#define ALL_VECTOR_REGS 0x00ff0000u
-#endif
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch(*ct_str++) {
- case 'a':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
- break;
- case 'b':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
- break;
- case 'c':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
- break;
- case 'd':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
- break;
- case 'S':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
- break;
- case 'D':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
- break;
- case 'q':
- /* A register that can be used as a byte operand. */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
- break;
- case 'Q':
- /* A register with an addressable second byte (e.g. %ah). */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xf;
- break;
- case 'r':
- /* A general register. */
- ct->ct |= TCG_CT_REG;
- ct->u.regs |= ALL_GENERAL_REGS;
- break;
- case 'W':
- /* With TZCNT/LZCNT, we can have operand-size as an input. */
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'x':
- /* A vector register. */
- ct->ct |= TCG_CT_REG;
- ct->u.regs |= ALL_VECTOR_REGS;
- break;
-
- /* qemu_ld/st address constraint */
- case 'L':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
- break;
-
- case 'e':
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
- break;
- case 'Z':
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
- break;
- case 'I':
- ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
- break;
-
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct = arg_ct->ct;
- if (ct & TCG_CT_CONST) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
- return 1;
- }
- return 0;
-}
-
-# define LOWREGMASK(x) ((x) & 7)
-
-#define P_EXT 0x100 /* 0x0f opcode prefix */
-#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */
-#define P_DATA16 0x400 /* 0x66 opcode prefix */
-#if TCG_TARGET_REG_BITS == 64
-# define P_REXW 0x1000 /* Set REX.W = 1 */
-# define P_REXB_R 0x2000 /* REG field as byte register */
-# define P_REXB_RM 0x4000 /* R/M field as byte register */
-# define P_GS 0x8000 /* gs segment override */
-#else
-# define P_REXW 0
-# define P_REXB_R 0
-# define P_REXB_RM 0
-# define P_GS 0
-#endif
-#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */
-#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
-#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
-#define P_VEXL 0x80000 /* Set VEX.L = 1 */
-
-#define OPC_ARITH_EvIz (0x81)
-#define OPC_ARITH_EvIb (0x83)
-#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
-#define OPC_ANDN (0xf2 | P_EXT38)
-#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
-#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3))
-#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16)
-#define OPC_BSF (0xbc | P_EXT)
-#define OPC_BSR (0xbd | P_EXT)
-#define OPC_BSWAP (0xc8 | P_EXT)
-#define OPC_CALL_Jz (0xe8)
-#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */
-#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3))
-#define OPC_DEC_r32 (0x48)
-#define OPC_IMUL_GvEv (0xaf | P_EXT)
-#define OPC_IMUL_GvEvIb (0x6b)
-#define OPC_IMUL_GvEvIz (0x69)
-#define OPC_INC_r32 (0x40)
-#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */
-#define OPC_JCC_short (0x70) /* ... plus condition code */
-#define OPC_JMP_long (0xe9)
-#define OPC_JMP_short (0xeb)
-#define OPC_LEA (0x8d)
-#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3)
-#define OPC_MOVB_EvGv (0x88) /* stores, more or less */
-#define OPC_MOVL_EvGv (0x89) /* stores, more or less */
-#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */
-#define OPC_MOVB_EvIz (0xc6)
-#define OPC_MOVL_EvIz (0xc7)
-#define OPC_MOVL_Iv (0xb8)
-#define OPC_MOVBE_GyMy (0xf0 | P_EXT38)
-#define OPC_MOVBE_MyGy (0xf1 | P_EXT38)
-#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16)
-#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16)
-#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2)
-#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16)
-#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16)
-#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3)
-#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3)
-#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3)
-#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16)
-#define OPC_MOVSBL (0xbe | P_EXT)
-#define OPC_MOVSWL (0xbf | P_EXT)
-#define OPC_MOVSLQ (0x63 | P_REXW)
-#define OPC_MOVZBL (0xb6 | P_EXT)
-#define OPC_MOVZWL (0xb7 | P_EXT)
-#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16)
-#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16)
-#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16)
-#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
-#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
-#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
-#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16)
-#define OPC_PADDB (0xfc | P_EXT | P_DATA16)
-#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
-#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
-#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
-#define OPC_PADDSB (0xec | P_EXT | P_DATA16)
-#define OPC_PADDSW (0xed | P_EXT | P_DATA16)
-#define OPC_PADDUB (0xdc | P_EXT | P_DATA16)
-#define OPC_PADDUW (0xdd | P_EXT | P_DATA16)
-#define OPC_PAND (0xdb | P_EXT | P_DATA16)
-#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
-#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16)
-#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16)
-#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16)
-#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16)
-#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16)
-#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16)
-#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16)
-#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16)
-#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16)
-#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16)
-#define OPC_PMAXSW (0xee | P_EXT | P_DATA16)
-#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16)
-#define OPC_PMAXUB (0xde | P_EXT | P_DATA16)
-#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16)
-#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16)
-#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16)
-#define OPC_PMINSW (0xea | P_EXT | P_DATA16)
-#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16)
-#define OPC_PMINUB (0xda | P_EXT | P_DATA16)
-#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16)
-#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16)
-#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16)
-#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16)
-#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16)
-#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16)
-#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16)
-#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16)
-#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16)
-#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16)
-#define OPC_POR (0xeb | P_EXT | P_DATA16)
-#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16)
-#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
-#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2)
-#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3)
-#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
-#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
-#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
-#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16)
-#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16)
-#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16)
-#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16)
-#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16)
-#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16)
-#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16)
-#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16)
-#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16)
-#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
-#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
-#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16)
-#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16)
-#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16)
-#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16)
-#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16)
-#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16)
-#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
-#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
-#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16)
-#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16)
-#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16)
-#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16)
-#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16)
-#define OPC_PXOR (0xef | P_EXT | P_DATA16)
-#define OPC_POP_r32 (0x58)
-#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3)
-#define OPC_PUSH_r32 (0x50)
-#define OPC_PUSH_Iv (0x68)
-#define OPC_PUSH_Ib (0x6a)
-#define OPC_RET (0xc3)
-#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */
-#define OPC_SHIFT_1 (0xd1)
-#define OPC_SHIFT_Ib (0xc1)
-#define OPC_SHIFT_cl (0xd3)
-#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3)
-#define OPC_SHUFPS (0xc6 | P_EXT)
-#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
-#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
-#define OPC_SHRD_Ib (0xac | P_EXT)
-#define OPC_TESTL (0x85)
-#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
-#define OPC_UD2 (0x0b | P_EXT)
-#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16)
-#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16)
-#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16)
-#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16)
-#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16)
-#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16)
-#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16)
-#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
-#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
-#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
-#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
-#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
-#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
-#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW)
-#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
-#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
-#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW)
-#define OPC_VZEROUPPER (0x77 | P_EXT)
-#define OPC_XCHG_ax_r32 (0x90)
-
-#define OPC_GRP3_Ev (0xf7)
-#define OPC_GRP5 (0xff)
-#define OPC_GRP14 (0x73 | P_EXT | P_DATA16)
-
-/* Group 1 opcode extensions for 0x80-0x83.
- These are also used as modifiers for OPC_ARITH. */
-#define ARITH_ADD 0
-#define ARITH_OR 1
-#define ARITH_ADC 2
-#define ARITH_SBB 3
-#define ARITH_AND 4
-#define ARITH_SUB 5
-#define ARITH_XOR 6
-#define ARITH_CMP 7
-
-/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */
-#define SHIFT_ROL 0
-#define SHIFT_ROR 1
-#define SHIFT_SHL 4
-#define SHIFT_SHR 5
-#define SHIFT_SAR 7
-
-/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */
-#define EXT3_NOT 2
-#define EXT3_NEG 3
-#define EXT3_MUL 4
-#define EXT3_IMUL 5
-#define EXT3_DIV 6
-#define EXT3_IDIV 7
-
-/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */
-#define EXT5_INC_Ev 0
-#define EXT5_DEC_Ev 1
-#define EXT5_CALLN_Ev 2
-#define EXT5_JMPN_Ev 4
-
-/* Condition codes to be added to OPC_JCC_{long,short}. */
-#define JCC_JMP (-1)
-#define JCC_JO 0x0
-#define JCC_JNO 0x1
-#define JCC_JB 0x2
-#define JCC_JAE 0x3
-#define JCC_JE 0x4
-#define JCC_JNE 0x5
-#define JCC_JBE 0x6
-#define JCC_JA 0x7
-#define JCC_JS 0x8
-#define JCC_JNS 0x9
-#define JCC_JP 0xa
-#define JCC_JNP 0xb
-#define JCC_JL 0xc
-#define JCC_JGE 0xd
-#define JCC_JLE 0xe
-#define JCC_JG 0xf
-
-static const uint8_t tcg_cond_to_jcc[] = {
- [TCG_COND_EQ] = JCC_JE,
- [TCG_COND_NE] = JCC_JNE,
- [TCG_COND_LT] = JCC_JL,
- [TCG_COND_GE] = JCC_JGE,
- [TCG_COND_LE] = JCC_JLE,
- [TCG_COND_GT] = JCC_JG,
- [TCG_COND_LTU] = JCC_JB,
- [TCG_COND_GEU] = JCC_JAE,
- [TCG_COND_LEU] = JCC_JBE,
- [TCG_COND_GTU] = JCC_JA,
-};
-
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
-{
- int rex;
-
- if (opc & P_GS) {
- tcg_out8(s, 0x65);
- }
- if (opc & P_DATA16) {
- /* We should never be asking for both 16 and 64-bit operation. */
- tcg_debug_assert((opc & P_REXW) == 0);
- tcg_out8(s, 0x66);
- }
- if (opc & P_SIMDF3) {
- tcg_out8(s, 0xf3);
- } else if (opc & P_SIMDF2) {
- tcg_out8(s, 0xf2);
- }
-
- rex = 0;
- rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */
- rex |= (r & 8) >> 1; /* REX.R */
- rex |= (x & 8) >> 2; /* REX.X */
- rex |= (rm & 8) >> 3; /* REX.B */
-
- /* P_REXB_{R,RM} indicates that the given register is the low byte.
- For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
- as otherwise the encoding indicates %[abcd]h. Note that the values
- that are ORed in merely indicate that the REX byte must be present;
- those bits get discarded in output. */
- rex |= opc & (r >= 4 ? P_REXB_R : 0);
- rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
-
- if (rex) {
- tcg_out8(s, (uint8_t)(rex | 0x40));
- }
-
- if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
- tcg_out8(s, 0x0f);
- if (opc & P_EXT38) {
- tcg_out8(s, 0x38);
- } else if (opc & P_EXT3A) {
- tcg_out8(s, 0x3a);
- }
- }
-
- tcg_out8(s, opc);
-}
-#else
-static void tcg_out_opc(TCGContext *s, int opc)
-{
- if (opc & P_DATA16) {
- tcg_out8(s, 0x66);
- }
- if (opc & P_SIMDF3) {
- tcg_out8(s, 0xf3);
- } else if (opc & P_SIMDF2) {
- tcg_out8(s, 0xf2);
- }
- if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
- tcg_out8(s, 0x0f);
- if (opc & P_EXT38) {
- tcg_out8(s, 0x38);
- } else if (opc & P_EXT3A) {
- tcg_out8(s, 0x3a);
- }
- }
- tcg_out8(s, opc);
-}
-/* Discard the register arguments to tcg_out_opc early, so as not to penalize
- the 32-bit compilation paths. This method works with all versions of gcc,
- whereas relying on optimization may not be able to exclude them. */
-#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
-#endif
-
-static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
-{
- tcg_out_opc(s, opc, r, rm, 0);
- tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
-}
-
-static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
- int rm, int index)
-{
- int tmp;
-
- /* Use the two byte form if possible, which cannot encode
- VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
- if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
- && ((rm | index) & 8) == 0) {
- /* Two byte VEX prefix. */
- tcg_out8(s, 0xc5);
-
- tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
- } else {
- /* Three byte VEX prefix. */
- tcg_out8(s, 0xc4);
-
- /* VEX.m-mmmm */
- if (opc & P_EXT3A) {
- tmp = 3;
- } else if (opc & P_EXT38) {
- tmp = 2;
- } else if (opc & P_EXT) {
- tmp = 1;
- } else {
- g_assert_not_reached();
- }
- tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
- tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */
- tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
- tcg_out8(s, tmp);
-
- tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
- }
-
- tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
- /* VEX.pp */
- if (opc & P_DATA16) {
- tmp |= 1; /* 0x66 */
- } else if (opc & P_SIMDF3) {
- tmp |= 2; /* 0xf3 */
- } else if (opc & P_SIMDF2) {
- tmp |= 3; /* 0xf2 */
- }
- tmp |= (~v & 15) << 3; /* VEX.vvvv */
- tcg_out8(s, tmp);
- tcg_out8(s, opc);
-}
-
-static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
-{
- tcg_out_vex_opc(s, opc, r, v, rm, 0);
- tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
-}
-
-/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
- We handle either RM and INDEX missing with a negative value. In 64-bit
- mode for absolute addresses, ~RM is the size of the immediate operand
- that will follow the instruction. */
-
-static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index,
- int shift, intptr_t offset)
-{
- int mod, len;
-
- if (index < 0 && rm < 0) {
- if (TCG_TARGET_REG_BITS == 64) {
- /* Try for a rip-relative addressing mode. This has replaced
- the 32-bit-mode absolute addressing encoding. */
- intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm;
- intptr_t disp = offset - pc;
- if (disp == (int32_t)disp) {
- tcg_out8(s, (LOWREGMASK(r) << 3) | 5);
- tcg_out32(s, disp);
- return;
- }
-
- /* Try for an absolute address encoding. This requires the
- use of the MODRM+SIB encoding and is therefore larger than
- rip-relative addressing. */
- if (offset == (int32_t)offset) {
- tcg_out8(s, (LOWREGMASK(r) << 3) | 4);
- tcg_out8(s, (4 << 3) | 5);
- tcg_out32(s, offset);
- return;
- }
-
- /* ??? The memory isn't directly addressable. */
- g_assert_not_reached();
- } else {
- /* Absolute address. */
- tcg_out8(s, (r << 3) | 5);
- tcg_out32(s, offset);
- return;
- }
- }
-
- /* Find the length of the immediate addend. Note that the encoding
- that would be used for (%ebp) indicates absolute addressing. */
- if (rm < 0) {
- mod = 0, len = 4, rm = 5;
- } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) {
- mod = 0, len = 0;
- } else if (offset == (int8_t)offset) {
- mod = 0x40, len = 1;
- } else {
- mod = 0x80, len = 4;
- }
-
- /* Use a single byte MODRM format if possible. Note that the encoding
- that would be used for %esp is the escape to the two byte form. */
- if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) {
- /* Single byte MODRM format. */
- tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
- } else {
- /* Two byte MODRM+SIB format. */
-
- /* Note that the encoding that would place %esp into the index
- field indicates no index register. In 64-bit mode, the REX.X
- bit counts, so %r12 can be used as the index. */
- if (index < 0) {
- index = 4;
- } else {
- tcg_debug_assert(index != TCG_REG_ESP);
- }
-
- tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4);
- tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm));
- }
-
- if (len == 1) {
- tcg_out8(s, offset);
- } else if (len == 4) {
- tcg_out32(s, offset);
- }
-}
-
-static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
- int index, int shift, intptr_t offset)
-{
- tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
- tcg_out_sib_offset(s, r, rm, index, shift, offset);
-}
-
-static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v,
- int rm, int index, int shift,
- intptr_t offset)
-{
- tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
- tcg_out_sib_offset(s, r, rm, index, shift, offset);
-}
-
-/* A simplification of the above with no index or shift. */
-static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
- int rm, intptr_t offset)
-{
- tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset);
-}
-
-static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r,
- int v, int rm, intptr_t offset)
-{
- tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset);
-}
-
-/* Output an opcode with an expected reference to the constant pool. */
-static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r)
-{
- tcg_out_opc(s, opc, r, 0, 0);
- /* Absolute for 32-bit, pc-relative for 64-bit. */
- tcg_out8(s, LOWREGMASK(r) << 3 | 5);
- tcg_out32(s, 0);
-}
-
-/* Output an opcode with an expected reference to the constant pool. */
-static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r)
-{
- tcg_out_vex_opc(s, opc, r, 0, 0, 0);
- /* Absolute for 32-bit, pc-relative for 64-bit. */
- tcg_out8(s, LOWREGMASK(r) << 3 | 5);
- tcg_out32(s, 0);
-}
-
-/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
-static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
-{
- /* Propagate an opcode prefix, such as P_REXW. */
- int ext = subop & ~0x7;
- subop &= 0x7;
-
- tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
-}
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
-{
- int rexw = 0;
-
- if (arg == ret) {
- return true;
- }
- switch (type) {
- case TCG_TYPE_I64:
- rexw = P_REXW;
- /* fallthru */
- case TCG_TYPE_I32:
- if (ret < 16) {
- if (arg < 16) {
- tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg);
- } else {
- tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret);
- }
- } else {
- if (arg < 16) {
- tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg);
- } else {
- tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
- }
- }
- break;
-
- case TCG_TYPE_V64:
- tcg_debug_assert(ret >= 16 && arg >= 16);
- tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
- break;
- case TCG_TYPE_V128:
- tcg_debug_assert(ret >= 16 && arg >= 16);
- tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg);
- break;
- case TCG_TYPE_V256:
- tcg_debug_assert(ret >= 16 && arg >= 16);
- tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg);
- break;
-
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static const int avx2_dup_insn[4] = {
- OPC_VPBROADCASTB, OPC_VPBROADCASTW,
- OPC_VPBROADCASTD, OPC_VPBROADCASTQ,
-};
-
-static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
- TCGReg r, TCGReg a)
-{
- if (have_avx2) {
- int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
- tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a);
- } else {
- switch (vece) {
- case MO_8:
- /* ??? With zero in a register, use PSHUFB. */
- tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a);
- a = r;
- /* FALLTHRU */
- case MO_16:
- tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a);
- a = r;
- /* FALLTHRU */
- case MO_32:
- tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);
- /* imm8 operand: all output lanes selected from input lane 0. */
- tcg_out8(s, 0);
- break;
- case MO_64:
- tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a);
- break;
- default:
- g_assert_not_reached();
- }
- }
- return true;
-}
-
-static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
- TCGReg r, TCGReg base, intptr_t offset)
-{
- if (have_avx2) {
- int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
- tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l,
- r, 0, base, offset);
- } else {
- switch (vece) {
- case MO_64:
- tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset);
- break;
- case MO_32:
- tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);
- break;
- case MO_16:
- tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset);
- tcg_out8(s, 0); /* imm8 */
- tcg_out_dup_vec(s, type, vece, r, r);
- break;
- case MO_8:
- tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset);
- tcg_out8(s, 0); /* imm8 */
- tcg_out_dup_vec(s, type, vece, r, r);
- break;
- default:
- g_assert_not_reached();
- }
- }
- return true;
-}
-
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
-{
- int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
-
- if (arg == 0) {
- tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret);
- return;
- }
- if (arg == -1) {
- tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret);
- return;
- }
-
- if (TCG_TARGET_REG_BITS == 64) {
- if (type == TCG_TYPE_V64) {
- tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret);
- } else if (have_avx2) {
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret);
- } else {
- tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
- }
- new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
- } else {
- if (have_avx2) {
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
- } else {
- tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
- }
- new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
- }
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
-{
- tcg_target_long diff;
-
- switch (type) {
- case TCG_TYPE_I32:
-#if TCG_TARGET_REG_BITS == 64
- case TCG_TYPE_I64:
-#endif
- if (ret < 16) {
- break;
- }
- /* fallthru */
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- case TCG_TYPE_V256:
- tcg_debug_assert(ret >= 16);
- tcg_out_dupi_vec(s, type, ret, arg);
- return;
- default:
- g_assert_not_reached();
- }
-
- if (arg == 0) {
- tgen_arithr(s, ARITH_XOR, ret, ret);
- return;
- }
- if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
- tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0);
- tcg_out32(s, arg);
- return;
- }
- if (arg == (int32_t)arg) {
- tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret);
- tcg_out32(s, arg);
- return;
- }
-
- /* Try a 7 byte pc-relative lea before the 10 byte movq. */
- diff = arg - ((uintptr_t)s->code_ptr + 7);
- if (diff == (int32_t)diff) {
- tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0);
- tcg_out8(s, (LOWREGMASK(ret) << 3) | 5);
- tcg_out32(s, diff);
- return;
- }
-
- tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0);
- tcg_out64(s, arg);
-}
-
-static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
-{
- if (val == (int8_t)val) {
- tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0);
- tcg_out8(s, val);
- } else if (val == (int32_t)val) {
- tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0);
- tcg_out32(s, val);
- } else {
- tcg_abort();
- }
-}
-
-static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- /* Given the strength of x86 memory ordering, we only need care for
- store-load ordering. Experimentally, "lock orl $0,0(%esp)" is
- faster than "mfence", so don't bother with the sse insn. */
- if (a0 & TCG_MO_ST_LD) {
- tcg_out8(s, 0xf0);
- tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0);
- tcg_out8(s, 0);
- }
-}
-
-static inline void tcg_out_push(TCGContext *s, int reg)
-{
- tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
-}
-
-static inline void tcg_out_pop(TCGContext *s, int reg)
-{
- tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
-}
-
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg arg1, intptr_t arg2)
-{
- switch (type) {
- case TCG_TYPE_I32:
- if (ret < 16) {
- tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
- } else {
- tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2);
- }
- break;
- case TCG_TYPE_I64:
- if (ret < 16) {
- tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2);
- break;
- }
- /* FALLTHRU */
- case TCG_TYPE_V64:
- /* There is no instruction that can validate 8-byte alignment. */
- tcg_debug_assert(ret >= 16);
- tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2);
- break;
- case TCG_TYPE_V128:
- /*
- * The gvec infrastructure is asserts that v128 vector loads
- * and stores use a 16-byte aligned offset. Validate that the
- * final pointer is aligned by using an insn that will SIGSEGV.
- */
- tcg_debug_assert(ret >= 16);
- tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2);
- break;
- case TCG_TYPE_V256:
- /*
- * The gvec infrastructure only requires 16-byte alignment,
- * so here we must use an unaligned load.
- */
- tcg_debug_assert(ret >= 16);
- tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL,
- ret, 0, arg1, arg2);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- switch (type) {
- case TCG_TYPE_I32:
- if (arg < 16) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
- } else {
- tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2);
- }
- break;
- case TCG_TYPE_I64:
- if (arg < 16) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2);
- break;
- }
- /* FALLTHRU */
- case TCG_TYPE_V64:
- /* There is no instruction that can validate 8-byte alignment. */
- tcg_debug_assert(arg >= 16);
- tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2);
- break;
- case TCG_TYPE_V128:
- /*
- * The gvec infrastructure is asserts that v128 vector loads
- * and stores use a 16-byte aligned offset. Validate that the
- * final pointer is aligned by using an insn that will SIGSEGV.
- */
- tcg_debug_assert(arg >= 16);
- tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2);
- break;
- case TCG_TYPE_V256:
- /*
- * The gvec infrastructure only requires 16-byte alignment,
- * so here we must use an unaligned store.
- */
- tcg_debug_assert(arg >= 16);
- tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL,
- arg, 0, arg1, arg2);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- int rexw = 0;
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
- if (val != (int32_t)val) {
- return false;
- }
- rexw = P_REXW;
- } else if (type != TCG_TYPE_I32) {
- return false;
- }
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs);
- tcg_out32(s, val);
- return true;
-}
-
-static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count)
-{
- /* Propagate an opcode prefix, such as P_DATA16. */
- int ext = subopc & ~0x7;
- subopc &= 0x7;
-
- if (count == 1) {
- tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg);
- } else {
- tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg);
- tcg_out8(s, count);
- }
-}
-
-static inline void tcg_out_bswap32(TCGContext *s, int reg)
-{
- tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0);
-}
-
-static inline void tcg_out_rolw_8(TCGContext *s, int reg)
-{
- tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8);
-}
-
-static inline void tcg_out_ext8u(TCGContext *s, int dest, int src)
-{
- /* movzbl */
- tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64);
- tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src);
-}
-
-static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw)
-{
- /* movsbl */
- tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64);
- tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src);
-}
-
-static inline void tcg_out_ext16u(TCGContext *s, int dest, int src)
-{
- /* movzwl */
- tcg_out_modrm(s, OPC_MOVZWL, dest, src);
-}
-
-static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw)
-{
- /* movsw[lq] */
- tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src);
-}
-
-static inline void tcg_out_ext32u(TCGContext *s, int dest, int src)
-{
- /* 32-bit mov zero extends. */
- tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src);
-}
-
-static inline void tcg_out_ext32s(TCGContext *s, int dest, int src)
-{
- tcg_out_modrm(s, OPC_MOVSLQ, dest, src);
-}
-
-static inline void tcg_out_bswap64(TCGContext *s, int reg)
-{
- tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0);
-}
-
-static void tgen_arithi(TCGContext *s, int c, int r0,
- tcg_target_long val, int cf)
-{
- int rexw = 0;
-
- if (TCG_TARGET_REG_BITS == 64) {
- rexw = c & -8;
- c &= 7;
- }
-
- /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
- partial flags update stalls on Pentium4 and are not recommended
- by current Intel optimization manuals. */
- if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
- int is_inc = (c == ARITH_ADD) ^ (val < 0);
- if (TCG_TARGET_REG_BITS == 64) {
- /* The single-byte increment encodings are re-tasked as the
- REX prefixes. Use the MODRM encoding. */
- tcg_out_modrm(s, OPC_GRP5 + rexw,
- (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
- } else {
- tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
- }
- return;
- }
-
- if (c == ARITH_AND) {
- if (TCG_TARGET_REG_BITS == 64) {
- if (val == 0xffffffffu) {
- tcg_out_ext32u(s, r0, r0);
- return;
- }
- if (val == (uint32_t)val) {
- /* AND with no high bits set can use a 32-bit operation. */
- rexw = 0;
- }
- }
- if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) {
- tcg_out_ext8u(s, r0, r0);
- return;
- }
- if (val == 0xffffu) {
- tcg_out_ext16u(s, r0, r0);
- return;
- }
- }
-
- if (val == (int8_t)val) {
- tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0);
- tcg_out8(s, val);
- return;
- }
- if (rexw == 0 || val == (int32_t)val) {
- tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0);
- tcg_out32(s, val);
- return;
- }
-
- tcg_abort();
-}
-
-static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
-{
- if (val != 0) {
- tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0);
- }
-}
-
-/* Use SMALL != 0 to force a short forward branch. */
-static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small)
-{
- int32_t val, val1;
-
- if (l->has_value) {
- val = tcg_pcrel_diff(s, l->u.value_ptr);
- val1 = val - 2;
- if ((int8_t)val1 == val1) {
- if (opc == -1) {
- tcg_out8(s, OPC_JMP_short);
- } else {
- tcg_out8(s, OPC_JCC_short + opc);
- }
- tcg_out8(s, val1);
- } else {
- if (small) {
- tcg_abort();
- }
- if (opc == -1) {
- tcg_out8(s, OPC_JMP_long);
- tcg_out32(s, val - 5);
- } else {
- tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
- tcg_out32(s, val - 6);
- }
- }
- } else if (small) {
- if (opc == -1) {
- tcg_out8(s, OPC_JMP_short);
- } else {
- tcg_out8(s, OPC_JCC_short + opc);
- }
- tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1);
- s->code_ptr += 1;
- } else {
- if (opc == -1) {
- tcg_out8(s, OPC_JMP_long);
- } else {
- tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
- }
- tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4);
- s->code_ptr += 4;
- }
-}
-
-static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
- int const_arg2, int rexw)
-{
- if (const_arg2) {
- if (arg2 == 0) {
- /* test r, r */
- tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1);
- } else {
- tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0);
- }
- } else {
- tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2);
- }
-}
-
-static void tcg_out_brcond32(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- TCGLabel *label, int small)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
- tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small);
-}
-
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_brcond64(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- TCGLabel *label, int small)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
- tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small);
-}
-#else
-/* XXX: we implement it at the target level to avoid having to
- handle cross basic blocks temporaries */
-static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
- const int *const_args, int small)
-{
- TCGLabel *label_next = gen_new_label();
- TCGLabel *label_this = arg_label(args[5]);
-
- switch(args[4]) {
- case TCG_COND_EQ:
- tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
- label_next, 1);
- tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3],
- label_this, small);
- break;
- case TCG_COND_NE:
- tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
- label_this, small);
- tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3],
- label_this, small);
- break;
- case TCG_COND_LT:
- tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_LE:
- tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_GT:
- tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_GE:
- tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_LTU:
- tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_LEU:
- tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_GTU:
- tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- case TCG_COND_GEU:
- tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
- label_this, small);
- tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
- label_this, small);
- break;
- default:
- tcg_abort();
- }
- tcg_out_label(s, label_next, s->code_ptr);
-}
-#endif
-
-static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest,
- TCGArg arg1, TCGArg arg2, int const_arg2)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
- tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
- tcg_out_ext8u(s, dest, dest);
-}
-
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest,
- TCGArg arg1, TCGArg arg2, int const_arg2)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
- tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
- tcg_out_ext8u(s, dest, dest);
-}
-#else
-static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
- const int *const_args)
-{
- TCGArg new_args[6];
- TCGLabel *label_true, *label_over;
-
- memcpy(new_args, args+1, 5*sizeof(TCGArg));
-
- if (args[0] == args[1] || args[0] == args[2]
- || (!const_args[3] && args[0] == args[3])
- || (!const_args[4] && args[0] == args[4])) {
- /* When the destination overlaps with one of the argument
- registers, don't do anything tricky. */
- label_true = gen_new_label();
- label_over = gen_new_label();
-
- new_args[5] = label_arg(label_true);
- tcg_out_brcond2(s, new_args, const_args+1, 1);
-
- tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
- tcg_out_jxx(s, JCC_JMP, label_over, 1);
- tcg_out_label(s, label_true, s->code_ptr);
-
- tcg_out_movi(s, TCG_TYPE_I32, args[0], 1);
- tcg_out_label(s, label_over, s->code_ptr);
- } else {
- /* When the destination does not overlap one of the arguments,
- clear the destination first, jump if cond false, and emit an
- increment in the true case. This results in smaller code. */
-
- tcg_out_movi(s, TCG_TYPE_I32, args[0], 0);
-
- label_over = gen_new_label();
- new_args[4] = tcg_invert_cond(new_args[4]);
- new_args[5] = label_arg(label_over);
- tcg_out_brcond2(s, new_args, const_args+1, 1);
-
- tgen_arithi(s, ARITH_ADD, args[0], 1, 0);
- tcg_out_label(s, label_over, s->code_ptr);
- }
-}
-#endif
-
-static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw,
- TCGReg dest, TCGReg v1)
-{
- if (have_cmov) {
- tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, v1);
- } else {
- TCGLabel *over = gen_new_label();
- tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1);
- tcg_out_mov(s, TCG_TYPE_I32, dest, v1);
- tcg_out_label(s, over, s->code_ptr);
- }
-}
-
-static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest,
- TCGReg c1, TCGArg c2, int const_c2,
- TCGReg v1)
-{
- tcg_out_cmp(s, c1, c2, const_c2, 0);
- tcg_out_cmov(s, cond, 0, dest, v1);
-}
-
-#if TCG_TARGET_REG_BITS == 64
-static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest,
- TCGReg c1, TCGArg c2, int const_c2,
- TCGReg v1)
-{
- tcg_out_cmp(s, c1, c2, const_c2, P_REXW);
- tcg_out_cmov(s, cond, P_REXW, dest, v1);
-}
-#endif
-
-static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1,
- TCGArg arg2, bool const_a2)
-{
- if (have_bmi1) {
- tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1);
- if (const_a2) {
- tcg_debug_assert(arg2 == (rexw ? 64 : 32));
- } else {
- tcg_debug_assert(dest != arg2);
- tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2);
- }
- } else {
- tcg_debug_assert(dest != arg2);
- tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1);
- tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2);
- }
-}
-
-static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1,
- TCGArg arg2, bool const_a2)
-{
- if (have_lzcnt) {
- tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1);
- if (const_a2) {
- tcg_debug_assert(arg2 == (rexw ? 64 : 32));
- } else {
- tcg_debug_assert(dest != arg2);
- tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2);
- }
- } else {
- tcg_debug_assert(!const_a2);
- tcg_debug_assert(dest != arg1);
- tcg_debug_assert(dest != arg2);
-
- /* Recall that the output of BSR is the index not the count. */
- tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1);
- tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0);
-
- /* Since we have destroyed the flags from BSR, we have to re-test. */
- tcg_out_cmp(s, arg1, 0, 1, rexw);
- tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2);
- }
-}
-
-static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest)
-{
- intptr_t disp = tcg_pcrel_diff(s, dest) - 5;
-
- if (disp == (int32_t)disp) {
- tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0);
- tcg_out32(s, disp);
- } else {
- /* rip-relative addressing into the constant pool.
- This is 6 + 8 = 14 bytes, as compared to using an
- an immediate load 10 + 6 = 16 bytes, plus we may
- be able to re-use the pool constant for more calls. */
- tcg_out_opc(s, OPC_GRP5, 0, 0, 0);
- tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5);
- new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4);
- tcg_out32(s, 0);
- }
-}
-
-static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
-{
- tcg_out_branch(s, 1, dest);
-}
-
-static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest)
-{
- tcg_out_branch(s, 0, dest);
-}
-
-static void tcg_out_nopn(TCGContext *s, int n)
-{
- int i;
- /* Emit 1 or 2 operand size prefixes for the standard one byte nop,
- * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the
- * duplicate prefix, and all of the interesting recent cores can
- * decode and discard the duplicates in a single cycle.
- */
- tcg_debug_assert(n >= 1);
- for (i = 1; i < n; ++i) {
- tcg_out8(s, 0x66);
- }
- tcg_out8(s, 0x90);
-}
-
-#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
-
-/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * int mmu_idx, uintptr_t ra)
- */
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
-};
-
-/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, int mmu_idx, uintptr_t ra)
- */
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-
-/* Perform the TLB load and compare.
-
- Inputs:
- ADDRLO and ADDRHI contain the low and high part of the address.
-
- MEM_INDEX and S_BITS are the memory context and log2 size of the load.
-
- WHICH is the offset into the CPUTLBEntry structure of the slot to read.
- This should be offsetof addr_read or addr_write.
-
- Outputs:
- LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
- positions of the displacements of forward jumps to the TLB miss case.
-
- Second argument register is loaded with the low part of the address.
- In the TLB hit case, it has been adjusted as indicated by the TLB
- and so is a host address. In the TLB miss case, it continues to
- hold a guest address.
-
- First argument register is clobbered. */
-
-static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
- int mem_index, MemOp opc,
- tcg_insn_unit **label_ptr, int which)
-{
- const TCGReg r0 = TCG_REG_L0;
- const TCGReg r1 = TCG_REG_L1;
- TCGType ttype = TCG_TYPE_I32;
- TCGType tlbtype = TCG_TYPE_I32;
- int trexw = 0, hrexw = 0, tlbrexw = 0;
- unsigned a_bits = get_alignment_bits(opc);
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_mask = (1 << a_bits) - 1;
- unsigned s_mask = (1 << s_bits) - 1;
- target_ulong tlb_mask;
-
- if (TCG_TARGET_REG_BITS == 64) {
- if (TARGET_LONG_BITS == 64) {
- ttype = TCG_TYPE_I64;
- trexw = P_REXW;
- }
- if (TCG_TYPE_PTR == TCG_TYPE_I64) {
- hrexw = P_REXW;
- if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) {
- tlbtype = TCG_TYPE_I64;
- tlbrexw = P_REXW;
- }
- }
- }
-
- tcg_out_mov(s, tlbtype, r0, addrlo);
- tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
-
- tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
- TLB_MASK_TABLE_OFS(mem_index) +
- offsetof(CPUTLBDescFast, mask));
-
- tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
- TLB_MASK_TABLE_OFS(mem_index) +
- offsetof(CPUTLBDescFast, table));
-
- /* If the required alignment is at least as large as the access, simply
- copy the address and mask. For lesser alignments, check that we don't
- cross pages for the complete access. */
- if (a_bits >= s_bits) {
- tcg_out_mov(s, ttype, r1, addrlo);
- } else {
- tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_mask);
- }
- tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
- tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0);
-
- /* cmp 0(r0), r1 */
- tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which);
-
- /* Prepare for both the fast path add of the tlb addend, and the slow
- path function argument setup. */
- tcg_out_mov(s, ttype, r1, addrlo);
-
- /* jne slow_path */
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
- label_ptr[0] = s->code_ptr;
- s->code_ptr += 4;
-
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- /* cmp 4(r0), addrhi */
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4);
-
- /* jne slow_path */
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
- label_ptr[1] = s->code_ptr;
- s->code_ptr += 4;
- }
-
- /* TLB Hit. */
-
- /* add addend(r0), r1 */
- tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,
- offsetof(CPUTLBEntry, addend));
-}
-
-/*
- * Record the context of a call to the out of line helper code for the slow path
- * for a load or store, so that we can later generate the correct helper code
- */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
- TCGMemOpIdx oi,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- tcg_insn_unit *raddr,
- tcg_insn_unit **label_ptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->type = is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
- label->datalo_reg = datalo;
- label->datahi_reg = datahi;
- label->addrlo_reg = addrlo;
- label->addrhi_reg = addrhi;
- label->raddr = raddr;
- label->label_ptr[0] = label_ptr[0];
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- label->label_ptr[1] = label_ptr[1];
- }
-}
-
-/*
- * Generate code for the slow path for a load at the end of block
- */
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- TCGMemOpIdx oi = l->oi;
- MemOp opc = get_memop(oi);
- TCGReg data_reg;
- tcg_insn_unit **label_ptr = &l->label_ptr[0];
- int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);
-
- /* resolve label address */
- tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4);
- }
-
- if (TCG_TARGET_REG_BITS == 32) {
- int ofs = 0;
-
- tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs);
- ofs += 4;
-
- tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs);
- ofs += 4;
-
- if (TARGET_LONG_BITS == 64) {
- tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs);
- ofs += 4;
- }
-
- tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs);
- ofs += 4;
-
- tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs);
- } else {
- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
- /* The second argument is already loaded with addrlo. */
- tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi);
- tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3],
- (uintptr_t)l->raddr);
- }
-
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
-
- data_reg = l->datalo_reg;
- switch (opc & MO_SSIZE) {
- case MO_SB:
- tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw);
- break;
- case MO_SW:
- tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw);
- break;
-#if TCG_TARGET_REG_BITS == 64
- case MO_SL:
- tcg_out_ext32s(s, data_reg, TCG_REG_EAX);
- break;
-#endif
- case MO_UB:
- case MO_UW:
- /* Note that the helpers have zero-extended to tcg_target_long. */
- case MO_UL:
- tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
- break;
- case MO_Q:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
- } else if (data_reg == TCG_REG_EDX) {
- /* xchg %edx, %eax */
- tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0);
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX);
- } else {
- tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX);
- }
- break;
- default:
- tcg_abort();
- }
-
- /* Jump to the code corresponding to next IR of qemu_st */
- tcg_out_jmp(s, l->raddr);
- return true;
-}
-
-/*
- * Generate code for the slow path for a store at the end of block
- */
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- TCGMemOpIdx oi = l->oi;
- MemOp opc = get_memop(oi);
- MemOp s_bits = opc & MO_SIZE;
- tcg_insn_unit **label_ptr = &l->label_ptr[0];
- TCGReg retaddr;
-
- /* resolve label address */
- tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4);
- }
-
- if (TCG_TARGET_REG_BITS == 32) {
- int ofs = 0;
-
- tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs);
- ofs += 4;
-
- tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs);
- ofs += 4;
-
- if (TARGET_LONG_BITS == 64) {
- tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs);
- ofs += 4;
- }
-
- tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs);
- ofs += 4;
-
- if (s_bits == MO_64) {
- tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs);
- ofs += 4;
- }
-
- tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs);
- ofs += 4;
-
- retaddr = TCG_REG_EAX;
- tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
- tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs);
- } else {
- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
- /* The second argument is already loaded with addrlo. */
- tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
- tcg_target_call_iarg_regs[2], l->datalo_reg);
- tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi);
-
- if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) {
- retaddr = tcg_target_call_iarg_regs[4];
- tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
- } else {
- retaddr = TCG_REG_RAX;
- tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
- tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP,
- TCG_TARGET_CALL_STACK_OFFSET);
- }
- }
-
- /* "Tail call" to the helper, with the return address back inline. */
- tcg_out_push(s, retaddr);
- tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
- return true;
-}
-#elif TCG_TARGET_REG_BITS == 32
-# define x86_guest_base_seg 0
-# define x86_guest_base_index -1
-# define x86_guest_base_offset guest_base
-#else
-static int x86_guest_base_seg;
-static int x86_guest_base_index = -1;
-static int32_t x86_guest_base_offset;
-# if defined(__x86_64__) && defined(__linux__)
-# include <asm/prctl.h>
-# include <sys/prctl.h>
-int arch_prctl(int code, unsigned long addr);
-static inline int setup_guest_base_seg(void)
-{
- if (arch_prctl(ARCH_SET_GS, guest_base) == 0) {
- return P_GS;
- }
- return 0;
-}
-# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__)
-# include <machine/sysarch.h>
-static inline int setup_guest_base_seg(void)
-{
- if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) {
- return P_GS;
- }
- return 0;
-}
-# else
-static inline int setup_guest_base_seg(void)
-{
- return 0;
-}
-# endif
-#endif /* SOFTMMU */
-
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg base, int index, intptr_t ofs,
- int seg, bool is64, MemOp memop)
-{
- const MemOp real_bswap = memop & MO_BSWAP;
- MemOp bswap = real_bswap;
- int rexw = is64 * P_REXW;
- int movop = OPC_MOVL_GvEv;
-
- if (have_movbe && real_bswap) {
- bswap = 0;
- movop = OPC_MOVBE_GyMy;
- }
-
- switch (memop & MO_SSIZE) {
- case MO_UB:
- tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo,
- base, index, 0, ofs);
- break;
- case MO_SB:
- tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo,
- base, index, 0, ofs);
- break;
- case MO_UW:
- tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo,
- base, index, 0, ofs);
- if (real_bswap) {
- tcg_out_rolw_8(s, datalo);
- }
- break;
- case MO_SW:
- if (real_bswap) {
- if (have_movbe) {
- tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
- datalo, base, index, 0, ofs);
- } else {
- tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo,
- base, index, 0, ofs);
- tcg_out_rolw_8(s, datalo);
- }
- tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo);
- } else {
- tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg,
- datalo, base, index, 0, ofs);
- }
- break;
- case MO_UL:
- tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);
- if (bswap) {
- tcg_out_bswap32(s, datalo);
- }
- break;
-#if TCG_TARGET_REG_BITS == 64
- case MO_SL:
- if (real_bswap) {
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
- base, index, 0, ofs);
- if (bswap) {
- tcg_out_bswap32(s, datalo);
- }
- tcg_out_ext32s(s, datalo, datalo);
- } else {
- tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo,
- base, index, 0, ofs);
- }
- break;
-#endif
- case MO_Q:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
- base, index, 0, ofs);
- if (bswap) {
- tcg_out_bswap64(s, datalo);
- }
- } else {
- if (real_bswap) {
- int t = datalo;
- datalo = datahi;
- datahi = t;
- }
- if (base != datalo) {
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
- base, index, 0, ofs);
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
- base, index, 0, ofs + 4);
- } else {
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
- base, index, 0, ofs + 4);
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
- base, index, 0, ofs);
- }
- if (bswap) {
- tcg_out_bswap32(s, datalo);
- tcg_out_bswap32(s, datahi);
- }
- }
- break;
- default:
- tcg_abort();
- }
-}
-
-/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
- EAX. It will be useful once fixed registers globals are less
- common. */
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
-{
- TCGReg datalo, datahi, addrlo;
- TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
- int mem_index;
- tcg_insn_unit *label_ptr[2];
-#endif
-
- datalo = *args++;
- datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- mem_index = get_mmuidx(oi);
-
- tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc,
- label_ptr, offsetof(CPUTLBEntry, addr_read));
-
- /* TLB Hit. */
- tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc);
-
- /* Record the current context of a load into ldst label */
- add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
-#else
- tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
- x86_guest_base_offset, x86_guest_base_seg,
- is64, opc);
-#endif
-}
-
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg base, int index, intptr_t ofs,
- int seg, MemOp memop)
-{
- /* ??? Ideally we wouldn't need a scratch register. For user-only,
- we could perform the bswap twice to restore the original value
- instead of moving to the scratch. But as it is, the L constraint
- means that TCG_REG_L0 is definitely free here. */
- const TCGReg scratch = TCG_REG_L0;
- const MemOp real_bswap = memop & MO_BSWAP;
- MemOp bswap = real_bswap;
- int movop = OPC_MOVL_EvGv;
-
- if (have_movbe && real_bswap) {
- bswap = 0;
- movop = OPC_MOVBE_MyGy;
- }
-
- switch (memop & MO_SIZE) {
- case MO_8:
- /* In 32-bit mode, 8-bit stores can only happen from [abcd]x.
- Use the scratch register if necessary. */
- if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) {
- tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
- datalo = scratch;
- }
- tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,
- datalo, base, index, 0, ofs);
- break;
- case MO_16:
- if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
- tcg_out_rolw_8(s, scratch);
- datalo = scratch;
- }
- tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo,
- base, index, 0, ofs);
- break;
- case MO_32:
- if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
- tcg_out_bswap32(s, scratch);
- datalo = scratch;
- }
- tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs);
- break;
- case MO_64:
- if (TCG_TARGET_REG_BITS == 64) {
- if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
- tcg_out_bswap64(s, scratch);
- datalo = scratch;
- }
- tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo,
- base, index, 0, ofs);
- } else if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
- tcg_out_bswap32(s, scratch);
- tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch,
- base, index, 0, ofs);
- tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
- tcg_out_bswap32(s, scratch);
- tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch,
- base, index, 0, ofs + 4);
- } else {
- if (real_bswap) {
- int t = datalo;
- datalo = datahi;
- datahi = t;
- }
- tcg_out_modrm_sib_offset(s, movop + seg, datalo,
- base, index, 0, ofs);
- tcg_out_modrm_sib_offset(s, movop + seg, datahi,
- base, index, 0, ofs + 4);
- }
- break;
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
-{
- TCGReg datalo, datahi, addrlo;
- TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
- int mem_index;
- tcg_insn_unit *label_ptr[2];
-#endif
-
- datalo = *args++;
- datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- mem_index = get_mmuidx(oi);
-
- tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc,
- label_ptr, offsetof(CPUTLBEntry, addr_write));
-
- /* TLB Hit. */
- tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc);
-
- /* Record the current context of a store into ldst label */
- add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
-#else
- tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
- x86_guest_base_offset, x86_guest_base_seg, opc);
-#endif
-}
-
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
-{
- TCGArg a0, a1, a2;
- int c, const_a2, vexop, rexw = 0;
-
-#if TCG_TARGET_REG_BITS == 64
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_, x), _i64): \
- rexw = P_REXW; /* FALLTHRU */ \
- case glue(glue(INDEX_op_, x), _i32)
-#else
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_, x), _i32)
-#endif
-
- /* Hoist the loads of the most common arguments. */
- a0 = args[0];
- a1 = args[1];
- a2 = args[2];
- const_a2 = const_args[2];
-
- switch (opc) {
- case INDEX_op_exit_tb:
- /* Reuse the zeroing that exists for goto_ptr. */
- if (a0 == 0) {
- tcg_out_jmp(s, s->code_gen_epilogue);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0);
- tcg_out_jmp(s, tb_ret_addr);
- }
- break;
- case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* direct jump method */
- int gap;
- /* jump displacement must be aligned for atomic patching;
- * see if we need to add extra nops before jump
- */
- gap = tcg_pcrel_diff(s, QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4));
- if (gap != 1) {
- tcg_out_nopn(s, gap - 1);
- }
- tcg_out8(s, OPC_JMP_long); /* jmp im */
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- tcg_out32(s, 0);
- } else {
- /* indirect jump method */
- tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1,
- (intptr_t)(s->tb_jmp_target_addr + a0));
- }
- set_jmp_reset_offset(s, a0);
- break;
- case INDEX_op_goto_ptr:
- /* jmp to the given host address (could be epilogue) */
- tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0);
- break;
- case INDEX_op_br:
- tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0);
- break;
- OP_32_64(ld8u):
- /* Note that we can ignore REXW for the zero-extend to 64-bit. */
- tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2);
- break;
- OP_32_64(ld8s):
- tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2);
- break;
- OP_32_64(ld16u):
- /* Note that we can ignore REXW for the zero-extend to 64-bit. */
- tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2);
- break;
- OP_32_64(ld16s):
- tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2);
- break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_ld32u_i64:
-#endif
- case INDEX_op_ld_i32:
- tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2);
- break;
-
- OP_32_64(st8):
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2);
- tcg_out8(s, a0);
- } else {
- tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2);
- }
- break;
- OP_32_64(st16):
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2);
- tcg_out16(s, a0);
- } else {
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2);
- }
- break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_st32_i64:
-#endif
- case INDEX_op_st_i32:
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2);
- tcg_out32(s, a0);
- } else {
- tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2);
- }
- break;
-
- OP_32_64(add):
- /* For 3-operand addition, use LEA. */
- if (a0 != a1) {
- TCGArg c3 = 0;
- if (const_a2) {
- c3 = a2, a2 = -1;
- } else if (a0 == a2) {
- /* Watch out for dest = src + dest, since we've removed
- the matching constraint on the add. */
- tgen_arithr(s, ARITH_ADD + rexw, a0, a1);
- break;
- }
-
- tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3);
- break;
- }
- c = ARITH_ADD;
- goto gen_arith;
- OP_32_64(sub):
- c = ARITH_SUB;
- goto gen_arith;
- OP_32_64(and):
- c = ARITH_AND;
- goto gen_arith;
- OP_32_64(or):
- c = ARITH_OR;
- goto gen_arith;
- OP_32_64(xor):
- c = ARITH_XOR;
- goto gen_arith;
- gen_arith:
- if (const_a2) {
- tgen_arithi(s, c + rexw, a0, a2, 0);
- } else {
- tgen_arithr(s, c + rexw, a0, a2);
- }
- break;
-
- OP_32_64(andc):
- if (const_a2) {
- tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
- tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0);
- } else {
- tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
- }
- break;
-
- OP_32_64(mul):
- if (const_a2) {
- int32_t val;
- val = a2;
- if (val == (int8_t)val) {
- tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0);
- tcg_out8(s, val);
- } else {
- tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0);
- tcg_out32(s, val);
- }
- } else {
- tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2);
- }
- break;
-
- OP_32_64(div2):
- tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]);
- break;
- OP_32_64(divu2):
- tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]);
- break;
-
- OP_32_64(shl):
- /* For small constant 3-operand shift, use LEA. */
- if (const_a2 && a0 != a1 && (a2 - 1) < 3) {
- if (a2 - 1 == 0) {
- /* shl $1,a1,a0 -> lea (a1,a1),a0 */
- tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0);
- } else {
- /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */
- tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0);
- }
- break;
- }
- c = SHIFT_SHL;
- vexop = OPC_SHLX;
- goto gen_shift_maybe_vex;
- OP_32_64(shr):
- c = SHIFT_SHR;
- vexop = OPC_SHRX;
- goto gen_shift_maybe_vex;
- OP_32_64(sar):
- c = SHIFT_SAR;
- vexop = OPC_SARX;
- goto gen_shift_maybe_vex;
- OP_32_64(rotl):
- c = SHIFT_ROL;
- goto gen_shift;
- OP_32_64(rotr):
- c = SHIFT_ROR;
- goto gen_shift;
- gen_shift_maybe_vex:
- if (have_bmi2) {
- if (!const_a2) {
- tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1);
- break;
- }
- tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
- }
- /* FALLTHRU */
- gen_shift:
- if (const_a2) {
- tcg_out_shifti(s, c + rexw, a0, a2);
- } else {
- tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0);
- }
- break;
-
- OP_32_64(ctz):
- tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]);
- break;
- OP_32_64(clz):
- tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]);
- break;
- OP_32_64(ctpop):
- tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1);
- break;
-
- case INDEX_op_brcond_i32:
- tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0);
- break;
- case INDEX_op_setcond_i32:
- tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2);
- break;
- case INDEX_op_movcond_i32:
- tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]);
- break;
-
- OP_32_64(bswap16):
- tcg_out_rolw_8(s, a0);
- break;
- OP_32_64(bswap32):
- tcg_out_bswap32(s, a0);
- break;
-
- OP_32_64(neg):
- tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0);
- break;
- OP_32_64(not):
- tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0);
- break;
-
- OP_32_64(ext8s):
- tcg_out_ext8s(s, a0, a1, rexw);
- break;
- OP_32_64(ext16s):
- tcg_out_ext16s(s, a0, a1, rexw);
- break;
- OP_32_64(ext8u):
- tcg_out_ext8u(s, a0, a1);
- break;
- OP_32_64(ext16u):
- tcg_out_ext16u(s, a0, a1);
- break;
-
- case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, 0);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, 1);
- break;
- case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, 0);
- break;
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, 1);
- break;
-
- OP_32_64(mulu2):
- tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]);
- break;
- OP_32_64(muls2):
- tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]);
- break;
- OP_32_64(add2):
- if (const_args[4]) {
- tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1);
- } else {
- tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]);
- }
- if (const_args[5]) {
- tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1);
- } else {
- tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]);
- }
- break;
- OP_32_64(sub2):
- if (const_args[4]) {
- tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1);
- } else {
- tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]);
- }
- if (const_args[5]) {
- tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1);
- } else {
- tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]);
- }
- break;
-
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_brcond2_i32:
- tcg_out_brcond2(s, args, const_args, 0);
- break;
- case INDEX_op_setcond2_i32:
- tcg_out_setcond2(s, args, const_args);
- break;
-#else /* TCG_TARGET_REG_BITS == 64 */
- case INDEX_op_ld32s_i64:
- tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2);
- break;
- case INDEX_op_ld_i64:
- tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2);
- break;
- case INDEX_op_st_i64:
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2);
- tcg_out32(s, a0);
- } else {
- tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2);
- }
- break;
-
- case INDEX_op_brcond_i64:
- tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0);
- break;
- case INDEX_op_setcond_i64:
- tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2);
- break;
- case INDEX_op_movcond_i64:
- tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]);
- break;
-
- case INDEX_op_bswap64_i64:
- tcg_out_bswap64(s, a0);
- break;
- case INDEX_op_extu_i32_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_extrl_i64_i32:
- tcg_out_ext32u(s, a0, a1);
- break;
- case INDEX_op_ext_i32_i64:
- case INDEX_op_ext32s_i64:
- tcg_out_ext32s(s, a0, a1);
- break;
- case INDEX_op_extrh_i64_i32:
- tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32);
- break;
-#endif
-
- OP_32_64(deposit):
- if (args[3] == 0 && args[4] == 8) {
- /* load bits 0..7 */
- tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0);
- } else if (args[3] == 8 && args[4] == 8) {
- /* load bits 8..15 */
- tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4);
- } else if (args[3] == 0 && args[4] == 16) {
- /* load bits 0..15 */
- tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0);
- } else {
- tcg_abort();
- }
- break;
-
- case INDEX_op_extract_i64:
- if (a2 + args[3] == 32) {
- /* This is a 32-bit zero-extending right shift. */
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tcg_out_shifti(s, SHIFT_SHR, a0, a2);
- break;
- }
- /* FALLTHRU */
- case INDEX_op_extract_i32:
- /* On the off-chance that we can use the high-byte registers.
- Otherwise we emit the same ext16 + shift pattern that we
- would have gotten from the normal tcg-op.c expansion. */
- tcg_debug_assert(a2 == 8 && args[3] == 8);
- if (a1 < 4 && a0 < 8) {
- tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
- } else {
- tcg_out_ext16u(s, a0, a1);
- tcg_out_shifti(s, SHIFT_SHR, a0, 8);
- }
- break;
-
- case INDEX_op_sextract_i32:
- /* We don't implement sextract_i64, as we cannot sign-extend to
- 64-bits without using the REX prefix that explicitly excludes
- access to the high-byte registers. */
- tcg_debug_assert(a2 == 8 && args[3] == 8);
- if (a1 < 4 && a0 < 8) {
- tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4);
- } else {
- tcg_out_ext16s(s, a0, a1, 0);
- tcg_out_shifti(s, SHIFT_SAR, a0, 8);
- }
- break;
-
- OP_32_64(extract2):
- /* Note that SHRD outputs to the r/m operand. */
- tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
- tcg_out8(s, args[3]);
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, a0);
- break;
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-
-#undef OP_32_64
-}
-
-static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
- unsigned vecl, unsigned vece,
- const TCGArg *args, const int *const_args)
-{
- static int const add_insn[4] = {
- OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
- };
- static int const ssadd_insn[4] = {
- OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
- };
- static int const usadd_insn[4] = {
- OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2
- };
- static int const sub_insn[4] = {
- OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
- };
- static int const sssub_insn[4] = {
- OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
- };
- static int const ussub_insn[4] = {
- OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2
- };
- static int const mul_insn[4] = {
- OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
- };
- static int const shift_imm_insn[4] = {
- OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
- };
- static int const cmpeq_insn[4] = {
- OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ
- };
- static int const cmpgt_insn[4] = {
- OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ
- };
- static int const punpckl_insn[4] = {
- OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ
- };
- static int const punpckh_insn[4] = {
- OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ
- };
- static int const packss_insn[4] = {
- OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2
- };
- static int const packus_insn[4] = {
- OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
- };
- static int const smin_insn[4] = {
- OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2
- };
- static int const smax_insn[4] = {
- OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2
- };
- static int const umin_insn[4] = {
- OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2
- };
- static int const umax_insn[4] = {
- OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
- };
- static int const shlv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16. */
- OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
- };
- static int const shrv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16. */
- OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
- };
- static int const sarv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16, MO_64. */
- OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
- };
- static int const shls_insn[4] = {
- OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
- };
- static int const shrs_insn[4] = {
- OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ
- };
- static int const sars_insn[4] = {
- OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
- };
- static int const abs_insn[4] = {
- /* TODO: AVX512 adds support for MO_64. */
- OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
- };
-
- TCGType type = vecl + TCG_TYPE_V64;
- int insn, sub;
- TCGArg a0, a1, a2;
-
- a0 = args[0];
- a1 = args[1];
- a2 = args[2];
-
- switch (opc) {
- case INDEX_op_add_vec:
- insn = add_insn[vece];
- goto gen_simd;
- case INDEX_op_ssadd_vec:
- insn = ssadd_insn[vece];
- goto gen_simd;
- case INDEX_op_usadd_vec:
- insn = usadd_insn[vece];
- goto gen_simd;
- case INDEX_op_sub_vec:
- insn = sub_insn[vece];
- goto gen_simd;
- case INDEX_op_sssub_vec:
- insn = sssub_insn[vece];
- goto gen_simd;
- case INDEX_op_ussub_vec:
- insn = ussub_insn[vece];
- goto gen_simd;
- case INDEX_op_mul_vec:
- insn = mul_insn[vece];
- goto gen_simd;
- case INDEX_op_and_vec:
- insn = OPC_PAND;
- goto gen_simd;
- case INDEX_op_or_vec:
- insn = OPC_POR;
- goto gen_simd;
- case INDEX_op_xor_vec:
- insn = OPC_PXOR;
- goto gen_simd;
- case INDEX_op_smin_vec:
- insn = smin_insn[vece];
- goto gen_simd;
- case INDEX_op_umin_vec:
- insn = umin_insn[vece];
- goto gen_simd;
- case INDEX_op_smax_vec:
- insn = smax_insn[vece];
- goto gen_simd;
- case INDEX_op_umax_vec:
- insn = umax_insn[vece];
- goto gen_simd;
- case INDEX_op_shlv_vec:
- insn = shlv_insn[vece];
- goto gen_simd;
- case INDEX_op_shrv_vec:
- insn = shrv_insn[vece];
- goto gen_simd;
- case INDEX_op_sarv_vec:
- insn = sarv_insn[vece];
- goto gen_simd;
- case INDEX_op_shls_vec:
- insn = shls_insn[vece];
- goto gen_simd;
- case INDEX_op_shrs_vec:
- insn = shrs_insn[vece];
- goto gen_simd;
- case INDEX_op_sars_vec:
- insn = sars_insn[vece];
- goto gen_simd;
- case INDEX_op_x86_punpckl_vec:
- insn = punpckl_insn[vece];
- goto gen_simd;
- case INDEX_op_x86_punpckh_vec:
- insn = punpckh_insn[vece];
- goto gen_simd;
- case INDEX_op_x86_packss_vec:
- insn = packss_insn[vece];
- goto gen_simd;
- case INDEX_op_x86_packus_vec:
- insn = packus_insn[vece];
- goto gen_simd;
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_dup2_vec:
- /* First merge the two 32-bit inputs to a single 64-bit element. */
- tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2);
- /* Then replicate the 64-bit elements across the rest of the vector. */
- if (type != TCG_TYPE_V64) {
- tcg_out_dup_vec(s, type, MO_64, a0, a0);
- }
- break;
-#endif
- case INDEX_op_abs_vec:
- insn = abs_insn[vece];
- a2 = a1;
- a1 = 0;
- goto gen_simd;
- gen_simd:
- tcg_debug_assert(insn != OPC_UD2);
- if (type == TCG_TYPE_V256) {
- insn |= P_VEXL;
- }
- tcg_out_vex_modrm(s, insn, a0, a1, a2);
- break;
-
- case INDEX_op_cmp_vec:
- sub = args[3];
- if (sub == TCG_COND_EQ) {
- insn = cmpeq_insn[vece];
- } else if (sub == TCG_COND_GT) {
- insn = cmpgt_insn[vece];
- } else {
- g_assert_not_reached();
- }
- goto gen_simd;
-
- case INDEX_op_andc_vec:
- insn = OPC_PANDN;
- if (type == TCG_TYPE_V256) {
- insn |= P_VEXL;
- }
- tcg_out_vex_modrm(s, insn, a0, a2, a1);
- break;
-
- case INDEX_op_shli_vec:
- sub = 6;
- goto gen_shift;
- case INDEX_op_shri_vec:
- sub = 2;
- goto gen_shift;
- case INDEX_op_sari_vec:
- tcg_debug_assert(vece != MO_64);
- sub = 4;
- gen_shift:
- tcg_debug_assert(vece != MO_8);
- insn = shift_imm_insn[vece];
- if (type == TCG_TYPE_V256) {
- insn |= P_VEXL;
- }
- tcg_out_vex_modrm(s, insn, sub, a0, a1);
- tcg_out8(s, a2);
- break;
-
- case INDEX_op_ld_vec:
- tcg_out_ld(s, type, a0, a1, a2);
- break;
- case INDEX_op_st_vec:
- tcg_out_st(s, type, a0, a1, a2);
- break;
- case INDEX_op_dupm_vec:
- tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
- break;
-
- case INDEX_op_x86_shufps_vec:
- insn = OPC_SHUFPS;
- sub = args[3];
- goto gen_simd_imm8;
- case INDEX_op_x86_blend_vec:
- if (vece == MO_16) {
- insn = OPC_PBLENDW;
- } else if (vece == MO_32) {
- insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);
- } else {
- g_assert_not_reached();
- }
- sub = args[3];
- goto gen_simd_imm8;
- case INDEX_op_x86_vperm2i128_vec:
- insn = OPC_VPERM2I128;
- sub = args[3];
- goto gen_simd_imm8;
- gen_simd_imm8:
- if (type == TCG_TYPE_V256) {
- insn |= P_VEXL;
- }
- tcg_out_vex_modrm(s, insn, a0, a1, a2);
- tcg_out8(s, sub);
- break;
-
- case INDEX_op_x86_vpblendvb_vec:
- insn = OPC_VPBLENDVB;
- if (type == TCG_TYPE_V256) {
- insn |= P_VEXL;
- }
- tcg_out_vex_modrm(s, insn, a0, a1, a2);
- tcg_out8(s, args[3] << 4);
- break;
-
- case INDEX_op_x86_psrldq_vec:
- tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1);
- tcg_out8(s, a2);
- break;
-
- case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
- case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
- case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
- default:
- g_assert_not_reached();
- }
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
- static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
- static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
- static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
- static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
- static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
- static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
- static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef L_L_L_L
- = { .args_ct_str = { "L", "L", "L", "L" } };
- static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
- static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
- static const TCGTargetOpDef x_x_x_x
- = { .args_ct_str = { "x", "x", "x", "x" } };
- static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- return &r_r;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- return &qi_r;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- return &ri_r;
- case INDEX_op_st_i64:
- return &re_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_add_i64:
- return &r_r_re;
- case INDEX_op_sub_i32:
- case INDEX_op_sub_i64:
- case INDEX_op_mul_i32:
- case INDEX_op_mul_i64:
- case INDEX_op_or_i32:
- case INDEX_op_or_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- return &r_0_re;
-
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
- {
- static const TCGTargetOpDef and
- = { .args_ct_str = { "r", "0", "reZ" } };
- return ∧
- }
- break;
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
- {
- static const TCGTargetOpDef andc
- = { .args_ct_str = { "r", "r", "rI" } };
- return &andc;
- }
- break;
-
- case INDEX_op_shl_i32:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i32:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i32:
- case INDEX_op_sar_i64:
- return have_bmi2 ? &r_r_ri : &r_0_ci;
- case INDEX_op_rotl_i32:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotr_i64:
- return &r_0_ci;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return &r_re;
-
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap32_i32:
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap64_i64:
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
- case INDEX_op_not_i32:
- case INDEX_op_not_i64:
- case INDEX_op_extrh_i64_i32:
- return &r_0;
-
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext8u_i64:
- return &r_q;
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext16u_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_extrl_i64_i32:
- case INDEX_op_extract_i32:
- case INDEX_op_extract_i64:
- case INDEX_op_sextract_i32:
- case INDEX_op_ctpop_i32:
- case INDEX_op_ctpop_i64:
- return &r_r;
- case INDEX_op_extract2_i32:
- case INDEX_op_extract2_i64:
- return &r_0_r;
-
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "Q", "0", "Q" } };
- return &dep;
- }
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- {
- static const TCGTargetOpDef setc
- = { .args_ct_str = { "q", "r", "re" } };
- return &setc;
- }
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "re", "r", "0" } };
- return &movc;
- }
- case INDEX_op_div2_i32:
- case INDEX_op_div2_i64:
- case INDEX_op_divu2_i32:
- case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "a", "d", "0", "1", "r" } };
- return &div2;
- }
- case INDEX_op_mulu2_i32:
- case INDEX_op_mulu2_i64:
- case INDEX_op_muls2_i32:
- case INDEX_op_muls2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "a", "d", "a", "r" } };
- return &mul2;
- }
- case INDEX_op_add2_i32:
- case INDEX_op_add2_i64:
- case INDEX_op_sub2_i32:
- case INDEX_op_sub2_i64:
- {
- static const TCGTargetOpDef arith2
- = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
- return &arith2;
- }
- case INDEX_op_ctz_i32:
- case INDEX_op_ctz_i64:
- {
- static const TCGTargetOpDef ctz[2] = {
- { .args_ct_str = { "&r", "r", "r" } },
- { .args_ct_str = { "&r", "r", "rW" } },
- };
- return &ctz[have_bmi1];
- }
- case INDEX_op_clz_i32:
- case INDEX_op_clz_i64:
- {
- static const TCGTargetOpDef clz[2] = {
- { .args_ct_str = { "&r", "r", "r" } },
- { .args_ct_str = { "&r", "r", "rW" } },
- };
- return &clz[have_lzcnt];
- }
-
- case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
- case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
- case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L);
- case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &L_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
- : &L_L_L_L);
-
- case INDEX_op_brcond2_i32:
- {
- static const TCGTargetOpDef b2
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
- return &b2;
- }
- case INDEX_op_setcond2_i32:
- {
- static const TCGTargetOpDef s2
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
- return &s2;
- }
-
- case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
- case INDEX_op_dupm_vec:
- return &x_r;
-
- case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
- case INDEX_op_mul_vec:
- case INDEX_op_and_vec:
- case INDEX_op_or_vec:
- case INDEX_op_xor_vec:
- case INDEX_op_andc_vec:
- case INDEX_op_ssadd_vec:
- case INDEX_op_usadd_vec:
- case INDEX_op_sssub_vec:
- case INDEX_op_ussub_vec:
- case INDEX_op_smin_vec:
- case INDEX_op_umin_vec:
- case INDEX_op_smax_vec:
- case INDEX_op_umax_vec:
- case INDEX_op_shlv_vec:
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
- case INDEX_op_shls_vec:
- case INDEX_op_shrs_vec:
- case INDEX_op_sars_vec:
- case INDEX_op_rotls_vec:
- case INDEX_op_cmp_vec:
- case INDEX_op_x86_shufps_vec:
- case INDEX_op_x86_blend_vec:
- case INDEX_op_x86_packss_vec:
- case INDEX_op_x86_packus_vec:
- case INDEX_op_x86_vperm2i128_vec:
- case INDEX_op_x86_punpckl_vec:
- case INDEX_op_x86_punpckh_vec:
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_dup2_vec:
-#endif
- return &x_x_x;
- case INDEX_op_abs_vec:
- case INDEX_op_dup_vec:
- case INDEX_op_shli_vec:
- case INDEX_op_shri_vec:
- case INDEX_op_sari_vec:
- case INDEX_op_x86_psrldq_vec:
- return &x_x;
- case INDEX_op_x86_vpblendvb_vec:
- return &x_x_x_x;
-
- default:
- break;
- }
- return NULL;
-}
-
-int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-{
- switch (opc) {
- case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
- case INDEX_op_and_vec:
- case INDEX_op_or_vec:
- case INDEX_op_xor_vec:
- case INDEX_op_andc_vec:
- return 1;
- case INDEX_op_rotli_vec:
- case INDEX_op_cmp_vec:
- case INDEX_op_cmpsel_vec:
- return -1;
-
- case INDEX_op_shli_vec:
- case INDEX_op_shri_vec:
- /* We must expand the operation for MO_8. */
- return vece == MO_8 ? -1 : 1;
-
- case INDEX_op_sari_vec:
- /* We must expand the operation for MO_8. */
- if (vece == MO_8) {
- return -1;
- }
- /* We can emulate this for MO_64, but it does not pay off
- unless we're producing at least 4 values. */
- if (vece == MO_64) {
- return type >= TCG_TYPE_V256 ? -1 : 0;
- }
- return 1;
-
- case INDEX_op_shls_vec:
- case INDEX_op_shrs_vec:
- return vece >= MO_16;
- case INDEX_op_sars_vec:
- return vece >= MO_16 && vece <= MO_32;
- case INDEX_op_rotls_vec:
- return vece >= MO_16 ? -1 : 0;
-
- case INDEX_op_shlv_vec:
- case INDEX_op_shrv_vec:
- return have_avx2 && vece >= MO_32;
- case INDEX_op_sarv_vec:
- return have_avx2 && vece == MO_32;
- case INDEX_op_rotlv_vec:
- case INDEX_op_rotrv_vec:
- return have_avx2 && vece >= MO_32 ? -1 : 0;
-
- case INDEX_op_mul_vec:
- if (vece == MO_8) {
- /* We can expand the operation for MO_8. */
- return -1;
- }
- if (vece == MO_64) {
- return 0;
- }
- return 1;
-
- case INDEX_op_ssadd_vec:
- case INDEX_op_usadd_vec:
- case INDEX_op_sssub_vec:
- case INDEX_op_ussub_vec:
- return vece <= MO_16;
- case INDEX_op_smin_vec:
- case INDEX_op_smax_vec:
- case INDEX_op_umin_vec:
- case INDEX_op_umax_vec:
- case INDEX_op_abs_vec:
- return vece <= MO_32;
-
- default:
- return 0;
- }
-}
-
-static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc,
- TCGv_vec v0, TCGv_vec v1, TCGArg imm)
-{
- TCGv_vec t1, t2;
-
- tcg_debug_assert(vece == MO_8);
-
- t1 = tcg_temp_new_vec(type);
- t2 = tcg_temp_new_vec(type);
-
- /*
- * Unpack to W, shift, and repack. Tricky bits:
- * (1) Use punpck*bw x,x to produce DDCCBBAA,
- * i.e. duplicate in other half of the 16-bit lane.
- * (2) For right-shift, add 8 so that the high half of the lane
- * becomes zero. For left-shift, and left-rotate, we must
- * shift up and down again.
- * (3) Step 2 leaves high half zero such that PACKUSWB
- * (pack with unsigned saturation) does not modify
- * the quantity.
- */
- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
- tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
- tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
-
- if (opc != INDEX_op_rotli_vec) {
- imm += 8;
- }
- if (opc == INDEX_op_shri_vec) {
- tcg_gen_shri_vec(MO_16, t1, t1, imm);
- tcg_gen_shri_vec(MO_16, t2, t2, imm);
- } else {
- tcg_gen_shli_vec(MO_16, t1, t1, imm);
- tcg_gen_shli_vec(MO_16, t2, t2, imm);
- tcg_gen_shri_vec(MO_16, t1, t1, 8);
- tcg_gen_shri_vec(MO_16, t2, t2, 8);
- }
-
- vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
- tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
- tcg_temp_free_vec(t1);
- tcg_temp_free_vec(t2);
-}
-
-static void expand_vec_sari(TCGType type, unsigned vece,
- TCGv_vec v0, TCGv_vec v1, TCGArg imm)
-{
- TCGv_vec t1, t2;
-
- switch (vece) {
- case MO_8:
- /* Unpack to W, shift, and repack, as in expand_vec_shi. */
- t1 = tcg_temp_new_vec(type);
- t2 = tcg_temp_new_vec(type);
- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
- tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
- tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1));
- tcg_gen_sari_vec(MO_16, t1, t1, imm + 8);
- tcg_gen_sari_vec(MO_16, t2, t2, imm + 8);
- vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
- tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2));
- tcg_temp_free_vec(t1);
- tcg_temp_free_vec(t2);
- break;
-
- case MO_64:
- if (imm <= 32) {
- /*
- * We can emulate a small sign extend by performing an arithmetic
- * 32-bit shift and overwriting the high half of a 64-bit logical
- * shift. Note that the ISA says shift of 32 is valid, but TCG
- * does not, so we have to bound the smaller shift -- we get the
- * same result in the high half either way.
- */
- t1 = tcg_temp_new_vec(type);
- tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
- tcg_gen_shri_vec(MO_64, v0, v1, imm);
- vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
- tcgv_vec_arg(v0), tcgv_vec_arg(v0),
- tcgv_vec_arg(t1), 0xaa);
- tcg_temp_free_vec(t1);
- } else {
- /* Otherwise we will need to use a compare vs 0 to produce
- * the sign-extend, shift and merge.
- */
- t1 = tcg_const_zeros_vec(type);
- tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
- tcg_gen_shri_vec(MO_64, v0, v1, imm);
- tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
- tcg_gen_or_vec(MO_64, v0, v0, t1);
- tcg_temp_free_vec(t1);
- }
- break;
-
- default:
- g_assert_not_reached();
- }
-}
-
-static void expand_vec_rotli(TCGType type, unsigned vece,
- TCGv_vec v0, TCGv_vec v1, TCGArg imm)
-{
- TCGv_vec t;
-
- if (vece == MO_8) {
- expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm);
- return;
- }
-
- t = tcg_temp_new_vec(type);
- tcg_gen_shli_vec(vece, t, v1, imm);
- tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
- tcg_gen_or_vec(vece, v0, v0, t);
- tcg_temp_free_vec(t);
-}
-
-static void expand_vec_rotls(TCGType type, unsigned vece,
- TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
-{
- TCGv_i32 rsh;
- TCGv_vec t;
-
- tcg_debug_assert(vece != MO_8);
-
- t = tcg_temp_new_vec(type);
- rsh = tcg_temp_new_i32();
-
- tcg_gen_neg_i32(rsh, lsh);
- tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
- tcg_gen_shls_vec(vece, t, v1, lsh);
- tcg_gen_shrs_vec(vece, v0, v1, rsh);
- tcg_gen_or_vec(vece, v0, v0, t);
- tcg_temp_free_vec(t);
- tcg_temp_free_i32(rsh);
-}
-
-static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec v1, TCGv_vec sh, bool right)
-{
- TCGv_vec t = tcg_temp_new_vec(type);
-
- tcg_gen_dupi_vec(vece, t, 8 << vece);
- tcg_gen_sub_vec(vece, t, t, sh);
- if (right) {
- tcg_gen_shlv_vec(vece, t, v1, t);
- tcg_gen_shrv_vec(vece, v0, v1, sh);
- } else {
- tcg_gen_shrv_vec(vece, t, v1, t);
- tcg_gen_shlv_vec(vece, v0, v1, sh);
- }
- tcg_gen_or_vec(vece, v0, v0, t);
- tcg_temp_free_vec(t);
-}
-
-static void expand_vec_mul(TCGType type, unsigned vece,
- TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
-{
- TCGv_vec t1, t2, t3, t4;
-
- tcg_debug_assert(vece == MO_8);
-
- /*
- * Unpack v1 bytes to words, 0 | x.
- * Unpack v2 bytes to words, y | 0.
- * This leaves the 8-bit result, x * y, with 8 bits of right padding.
- * Shift logical right by 8 bits to clear the high 8 bytes before
- * using an unsigned saturated pack.
- *
- * The difference between the V64, V128 and V256 cases is merely how
- * we distribute the expansion between temporaries.
- */
- switch (type) {
- case TCG_TYPE_V64:
- t1 = tcg_temp_new_vec(TCG_TYPE_V128);
- t2 = tcg_temp_new_vec(TCG_TYPE_V128);
- tcg_gen_dup16i_vec(t2, 0);
- vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
- tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));
- vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
- tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));
- tcg_gen_mul_vec(MO_16, t1, t1, t2);
- tcg_gen_shri_vec(MO_16, t1, t1, 8);
- vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
- tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1));
- tcg_temp_free_vec(t1);
- tcg_temp_free_vec(t2);
- break;
-
- case TCG_TYPE_V128:
- case TCG_TYPE_V256:
- t1 = tcg_temp_new_vec(type);
- t2 = tcg_temp_new_vec(type);
- t3 = tcg_temp_new_vec(type);
- t4 = tcg_temp_new_vec(type);
- tcg_gen_dup16i_vec(t4, 0);
- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
- tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
- vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
- tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
- tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
- vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
- tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
- tcg_gen_mul_vec(MO_16, t1, t1, t2);
- tcg_gen_mul_vec(MO_16, t3, t3, t4);
- tcg_gen_shri_vec(MO_16, t1, t1, 8);
- tcg_gen_shri_vec(MO_16, t3, t3, 8);
- vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
- tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
- tcg_temp_free_vec(t1);
- tcg_temp_free_vec(t2);
- tcg_temp_free_vec(t3);
- tcg_temp_free_vec(t4);
- break;
-
- default:
- g_assert_not_reached();
- }
-}
-
-static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec v1, TCGv_vec v2, TCGCond cond)
-{
- enum {
- NEED_INV = 1,
- NEED_SWAP = 2,
- NEED_BIAS = 4,
- NEED_UMIN = 8,
- NEED_UMAX = 16,
- };
- TCGv_vec t1, t2;
- uint8_t fixup;
-
- switch (cond) {
- case TCG_COND_EQ:
- case TCG_COND_GT:
- fixup = 0;
- break;
- case TCG_COND_NE:
- case TCG_COND_LE:
- fixup = NEED_INV;
- break;
- case TCG_COND_LT:
- fixup = NEED_SWAP;
- break;
- case TCG_COND_GE:
- fixup = NEED_SWAP | NEED_INV;
- break;
- case TCG_COND_LEU:
- if (vece <= MO_32) {
- fixup = NEED_UMIN;
- } else {
- fixup = NEED_BIAS | NEED_INV;
- }
- break;
- case TCG_COND_GTU:
- if (vece <= MO_32) {
- fixup = NEED_UMIN | NEED_INV;
- } else {
- fixup = NEED_BIAS;
- }
- break;
- case TCG_COND_GEU:
- if (vece <= MO_32) {
- fixup = NEED_UMAX;
- } else {
- fixup = NEED_BIAS | NEED_SWAP | NEED_INV;
- }
- break;
- case TCG_COND_LTU:
- if (vece <= MO_32) {
- fixup = NEED_UMAX | NEED_INV;
- } else {
- fixup = NEED_BIAS | NEED_SWAP;
- }
- break;
- default:
- g_assert_not_reached();
- }
-
- if (fixup & NEED_INV) {
- cond = tcg_invert_cond(cond);
- }
- if (fixup & NEED_SWAP) {
- t1 = v1, v1 = v2, v2 = t1;
- cond = tcg_swap_cond(cond);
- }
-
- t1 = t2 = NULL;
- if (fixup & (NEED_UMIN | NEED_UMAX)) {
- t1 = tcg_temp_new_vec(type);
- if (fixup & NEED_UMIN) {
- tcg_gen_umin_vec(vece, t1, v1, v2);
- } else {
- tcg_gen_umax_vec(vece, t1, v1, v2);
- }
- v2 = t1;
- cond = TCG_COND_EQ;
- } else if (fixup & NEED_BIAS) {
- t1 = tcg_temp_new_vec(type);
- t2 = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
- tcg_gen_sub_vec(vece, t1, v1, t2);
- tcg_gen_sub_vec(vece, t2, v2, t2);
- v1 = t1;
- v2 = t2;
- cond = tcg_signed_cond(cond);
- }
-
- tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT);
- /* Expand directly; do not recurse. */
- vec_gen_4(INDEX_op_cmp_vec, type, vece,
- tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
-
- if (t1) {
- tcg_temp_free_vec(t1);
- if (t2) {
- tcg_temp_free_vec(t2);
- }
- }
- return fixup & NEED_INV;
-}
-
-static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec v1, TCGv_vec v2, TCGCond cond)
-{
- if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) {
- tcg_gen_not_vec(vece, v0, v0);
- }
-}
-
-static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec c1, TCGv_vec c2,
- TCGv_vec v3, TCGv_vec v4, TCGCond cond)
-{
- TCGv_vec t = tcg_temp_new_vec(type);
-
- if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
- /* Invert the sense of the compare by swapping arguments. */
- TCGv_vec x;
- x = v3, v3 = v4, v4 = x;
- }
- vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece,
- tcgv_vec_arg(v0), tcgv_vec_arg(v4),
- tcgv_vec_arg(v3), tcgv_vec_arg(t));
- tcg_temp_free_vec(t);
-}
-
-void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
- TCGArg a0, ...)
-{
- va_list va;
- TCGArg a2;
- TCGv_vec v0, v1, v2, v3, v4;
-
- va_start(va, a0);
- v0 = temp_tcgv_vec(arg_temp(a0));
- v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
- a2 = va_arg(va, TCGArg);
-
- switch (opc) {
- case INDEX_op_shli_vec:
- case INDEX_op_shri_vec:
- expand_vec_shi(type, vece, opc, v0, v1, a2);
- break;
-
- case INDEX_op_sari_vec:
- expand_vec_sari(type, vece, v0, v1, a2);
- break;
-
- case INDEX_op_rotli_vec:
- expand_vec_rotli(type, vece, v0, v1, a2);
- break;
-
- case INDEX_op_rotls_vec:
- expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2)));
- break;
-
- case INDEX_op_rotlv_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- expand_vec_rotv(type, vece, v0, v1, v2, false);
- break;
- case INDEX_op_rotrv_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- expand_vec_rotv(type, vece, v0, v1, v2, true);
- break;
-
- case INDEX_op_mul_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- expand_vec_mul(type, vece, v0, v1, v2);
- break;
-
- case INDEX_op_cmp_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
- break;
-
- case INDEX_op_cmpsel_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
- v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
- expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
- break;
-
- default:
- break;
- }
-
- va_end(va);
-}
-
-static const int tcg_target_callee_save_regs[] = {
-#if TCG_TARGET_REG_BITS == 64
- TCG_REG_RBP,
- TCG_REG_RBX,
-#if defined(_WIN64)
- TCG_REG_RDI,
- TCG_REG_RSI,
-#endif
- TCG_REG_R12,
- TCG_REG_R13,
- TCG_REG_R14, /* Currently used for the global env. */
- TCG_REG_R15,
-#else
- TCG_REG_EBP, /* Currently used for the global env. */
- TCG_REG_EBX,
- TCG_REG_ESI,
- TCG_REG_EDI,
-#endif
-};
-
-/* Compute frame size via macros, to share between tcg_target_qemu_prologue
- and tcg_register_jit. */
-
-#define PUSH_SIZE \
- ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \
- * (TCG_TARGET_REG_BITS / 8))
-
-#define FRAME_SIZE \
- ((PUSH_SIZE \
- + TCG_STATIC_CALL_ARGS_SIZE \
- + CPU_TEMP_BUF_NLONGS * sizeof(long) \
- + TCG_TARGET_STACK_ALIGN - 1) \
- & ~(TCG_TARGET_STACK_ALIGN - 1))
-
-/* Generate global QEMU prologue and epilogue code */
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- int i, stack_addend;
-
- /* TB prologue */
-
- /* Reserve some stack space, also for TCG temps. */
- stack_addend = FRAME_SIZE - PUSH_SIZE;
- tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
-
- /* Save all callee saved registers. */
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
- tcg_out_push(s, tcg_target_callee_save_regs[i]);
- }
-
-#if TCG_TARGET_REG_BITS == 32
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
- (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
- tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
- /* jmp *tb. */
- tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
- (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
- + stack_addend);
-#else
-# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64
- if (guest_base) {
- int seg = setup_guest_base_seg();
- if (seg != 0) {
- x86_guest_base_seg = seg;
- } else if (guest_base == (int32_t)guest_base) {
- x86_guest_base_offset = guest_base;
- } else {
- /* Choose R12 because, as a base, it requires a SIB byte. */
- x86_guest_base_index = TCG_REG_R12;
- tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
- tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index);
- }
- }
-# endif
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
- /* jmp *tb. */
- tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
-#endif
-
- /*
- * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
- * and fall through to the rest of the epilogue.
- */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0);
-
- /* TB epilogue */
- tb_ret_addr = s->code_ptr;
-
- tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend);
-
- if (have_avx2) {
- tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0);
- }
- for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
- tcg_out_pop(s, tcg_target_callee_save_regs[i]);
- }
- tcg_out_opc(s, OPC_RET, 0, 0, 0);
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- memset(p, 0x90, count);
-}
-
-static void tcg_target_init(TCGContext *s)
-{
-#ifdef CONFIG_CPUID_H
- unsigned a, b, c, d, b7 = 0;
- int max = __get_cpuid_max(0, 0);
-
- if (max >= 7) {
- /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
- __cpuid_count(7, 0, a, b7, c, d);
- have_bmi1 = (b7 & bit_BMI) != 0;
- have_bmi2 = (b7 & bit_BMI2) != 0;
- }
-
- if (max >= 1) {
- __cpuid(1, a, b, c, d);
-#ifndef have_cmov
- /* For 32-bit, 99% certainty that we're running on hardware that
- supports cmov, but we still need to check. In case cmov is not
- available, we'll use a small forward branch. */
- have_cmov = (d & bit_CMOV) != 0;
-#endif
-
- /* MOVBE is only available on Intel Atom and Haswell CPUs, so we
- need to probe for it. */
- have_movbe = (c & bit_MOVBE) != 0;
- have_popcnt = (c & bit_POPCNT) != 0;
-
- /* There are a number of things we must check before we can be
- sure of not hitting invalid opcode. */
- if (c & bit_OSXSAVE) {
- unsigned xcrl, xcrh;
- /* The xgetbv instruction is not available to older versions of
- * the assembler, so we encode the instruction manually.
- */
- asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0));
- if ((xcrl & 6) == 6) {
- have_avx1 = (c & bit_AVX) != 0;
- have_avx2 = (b7 & bit_AVX2) != 0;
- }
- }
- }
-
- max = __get_cpuid_max(0x8000000, 0);
- if (max >= 1) {
- __cpuid(0x80000001, a, b, c, d);
- /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs. */
- have_lzcnt = (c & bit_LZCNT) != 0;
- }
-#endif /* CONFIG_CPUID_H */
-
- tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
- }
- if (have_avx1) {
- tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
- tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
- }
- if (have_avx2) {
- tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
- }
-
- tcg_target_call_clobber_regs = ALL_VECTOR_REGS;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
- if (TCG_TARGET_REG_BITS == 64) {
-#if !defined(_WIN64)
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI);
-#endif
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
- }
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[14];
-} DebugFrame;
-
-/* We're expecting a 2 byte uleb128 encoded value. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-
-#if !defined(__ELF__)
- /* Host machine without ELF. */
-#elif TCG_TARGET_REG_BITS == 64
-#define ELF_HOST_MACHINE EM_X86_64
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = 0x78, /* sleb128 -8 */
- .h.cie.return_column = 16,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, 7, /* DW_CFA_def_cfa %rsp, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x90, 1, /* DW_CFA_offset, %rip, -8 */
- /* The following ordering must match tcg_target_callee_save_regs. */
- 0x86, 2, /* DW_CFA_offset, %rbp, -16 */
- 0x83, 3, /* DW_CFA_offset, %rbx, -24 */
- 0x8c, 4, /* DW_CFA_offset, %r12, -32 */
- 0x8d, 5, /* DW_CFA_offset, %r13, -40 */
- 0x8e, 6, /* DW_CFA_offset, %r14, -48 */
- 0x8f, 7, /* DW_CFA_offset, %r15, -56 */
- }
-};
-#else
-#define ELF_HOST_MACHINE EM_386
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = 0x7c, /* sleb128 -4 */
- .h.cie.return_column = 8,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, 4, /* DW_CFA_def_cfa %esp, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x88, 1, /* DW_CFA_offset, %eip, -4 */
- /* The following ordering must match tcg_target_callee_save_regs. */
- 0x85, 2, /* DW_CFA_offset, %ebp, -8 */
- 0x83, 3, /* DW_CFA_offset, %ebx, -12 */
- 0x86, 4, /* DW_CFA_offset, %esi, -16 */
- 0x87, 5, /* DW_CFA_offset, %edi, -20 */
- }
-};
-#endif
-
-#if defined(ELF_HOST_MACHINE)
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
-#endif
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
+ * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifdef HOST_WORDS_BIGENDIAN
+# define MIPS_BE 1
+#else
+# define MIPS_BE 0
+#endif
+
+#if TCG_TARGET_REG_BITS == 32
+# define LO_OFF (MIPS_BE * 4)
+# define HI_OFF (4 - LO_OFF)
+#else
+/* To assert at compile-time that these values are never used
+ for TCG_TARGET_REG_BITS == 64. */
+int link_error(void);
+# define LO_OFF link_error()
+# define HI_OFF link_error()
+#endif
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "zero",
+ "at",
+ "v0",
+ "v1",
+ "a0",
+ "a1",
+ "a2",
+ "a3",
+ "t0",
+ "t1",
+ "t2",
+ "t3",
+ "t4",
+ "t5",
+ "t6",
+ "t7",
+ "s0",
+ "s1",
+ "s2",
+ "s3",
+ "s4",
+ "s5",
+ "s6",
+ "s7",
+ "t8",
+ "t9",
+ "k0",
+ "k1",
+ "gp",
+ "sp",
+ "s8",
+ "ra",
+};
+#endif
+
+#define TCG_TMP0 TCG_REG_AT
+#define TCG_TMP1 TCG_REG_T9
+#define TCG_TMP2 TCG_REG_T8
+#define TCG_TMP3 TCG_REG_T7
+
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_S1
+#endif
+
+/* check if we really need so many registers :P */
+static const int tcg_target_reg_alloc_order[] = {
+ /* Call saved registers. */
+ TCG_REG_S0,
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+
+ /* Call clobbered registers. */
+ TCG_REG_T4,
+ TCG_REG_T5,
+ TCG_REG_T6,
+ TCG_REG_T7,
+ TCG_REG_T8,
+ TCG_REG_T9,
+ TCG_REG_V1,
+ TCG_REG_V0,
+
+ /* Argument registers, opposite order of allocation. */
+ TCG_REG_T3,
+ TCG_REG_T2,
+ TCG_REG_T1,
+ TCG_REG_T0,
+ TCG_REG_A3,
+ TCG_REG_A2,
+ TCG_REG_A1,
+ TCG_REG_A0,
+};
+
+static const TCGReg tcg_target_call_iarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+#endif
+};
+
+static const TCGReg tcg_target_call_oarg_regs[2] = {
+ TCG_REG_V0,
+ TCG_REG_V1
+};
+
+static tcg_insn_unit *tb_ret_addr;
+static tcg_insn_unit *bswap32_addr;
+static tcg_insn_unit *bswap32u_addr;
+static tcg_insn_unit *bswap64_addr;
+
+static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ /* Let the compiler perform the right-shift as part of the arithmetic. */
+ ptrdiff_t disp = target - (pc + 1);
+ tcg_debug_assert(disp == (int16_t)disp);
+ return disp & 0xffff;
+}
+
+static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
+}
+
+static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
+ return ((uintptr_t)target >> 2) & 0x3ffffff;
+}
+
+static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
+}
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ tcg_debug_assert(type == R_MIPS_PC16);
+ tcg_debug_assert(addend == 0);
+ reloc_pc16(code_ptr, (tcg_insn_unit *)value);
+ return true;
+}
+
+#define TCG_CT_CONST_ZERO 0x100
+#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
+#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
+#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
+#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
+#define TCG_CT_CONST_WSZ 0x2000 /* word size */
+
+static inline bool is_p2m1(tcg_target_long val)
+{
+ return val && ((val + 1) & val) == 0;
+}
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch(*ct_str++) {
+ case 'r':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ break;
+ case 'L': /* qemu_ld input arg constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+#if defined(CONFIG_SOFTMMU)
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
+ }
+#endif
+ break;
+ case 'S': /* qemu_st constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+#if defined(CONFIG_SOFTMMU)
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
+ } else {
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
+ }
+#endif
+ break;
+ case 'I':
+ ct->ct |= TCG_CT_CONST_U16;
+ break;
+ case 'J':
+ ct->ct |= TCG_CT_CONST_S16;
+ break;
+ case 'K':
+ ct->ct |= TCG_CT_CONST_P2M1;
+ break;
+ case 'N':
+ ct->ct |= TCG_CT_CONST_N16;
+ break;
+ case 'W':
+ ct->ct |= TCG_CT_CONST_WSZ;
+ break;
+ case 'Z':
+ /* We are cheating a bit here, using the fact that the register
+ ZERO is also the register number 0. Hence there is no need
+ to check for const_args in each instruction. */
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* test if a constant matches the constraint */
+static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct;
+ ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_P2M1)
+ && use_mips32r2_instructions && is_p2m1(val)) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_WSZ)
+ && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
+ return 1;
+ }
+ return 0;
+}
+
+/* instruction opcodes */
+typedef enum {
+ OPC_J = 002 << 26,
+ OPC_JAL = 003 << 26,
+ OPC_BEQ = 004 << 26,
+ OPC_BNE = 005 << 26,
+ OPC_BLEZ = 006 << 26,
+ OPC_BGTZ = 007 << 26,
+ OPC_ADDIU = 011 << 26,
+ OPC_SLTI = 012 << 26,
+ OPC_SLTIU = 013 << 26,
+ OPC_ANDI = 014 << 26,
+ OPC_ORI = 015 << 26,
+ OPC_XORI = 016 << 26,
+ OPC_LUI = 017 << 26,
+ OPC_DADDIU = 031 << 26,
+ OPC_LB = 040 << 26,
+ OPC_LH = 041 << 26,
+ OPC_LW = 043 << 26,
+ OPC_LBU = 044 << 26,
+ OPC_LHU = 045 << 26,
+ OPC_LWU = 047 << 26,
+ OPC_SB = 050 << 26,
+ OPC_SH = 051 << 26,
+ OPC_SW = 053 << 26,
+ OPC_LD = 067 << 26,
+ OPC_SD = 077 << 26,
+
+ OPC_SPECIAL = 000 << 26,
+ OPC_SLL = OPC_SPECIAL | 000,
+ OPC_SRL = OPC_SPECIAL | 002,
+ OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
+ OPC_SRA = OPC_SPECIAL | 003,
+ OPC_SLLV = OPC_SPECIAL | 004,
+ OPC_SRLV = OPC_SPECIAL | 006,
+ OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
+ OPC_SRAV = OPC_SPECIAL | 007,
+ OPC_JR_R5 = OPC_SPECIAL | 010,
+ OPC_JALR = OPC_SPECIAL | 011,
+ OPC_MOVZ = OPC_SPECIAL | 012,
+ OPC_MOVN = OPC_SPECIAL | 013,
+ OPC_SYNC = OPC_SPECIAL | 017,
+ OPC_MFHI = OPC_SPECIAL | 020,
+ OPC_MFLO = OPC_SPECIAL | 022,
+ OPC_DSLLV = OPC_SPECIAL | 024,
+ OPC_DSRLV = OPC_SPECIAL | 026,
+ OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
+ OPC_DSRAV = OPC_SPECIAL | 027,
+ OPC_MULT = OPC_SPECIAL | 030,
+ OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
+ OPC_MUH = OPC_SPECIAL | 030 | 0300,
+ OPC_MULTU = OPC_SPECIAL | 031,
+ OPC_MULU = OPC_SPECIAL | 031 | 0200,
+ OPC_MUHU = OPC_SPECIAL | 031 | 0300,
+ OPC_DIV = OPC_SPECIAL | 032,
+ OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
+ OPC_MOD = OPC_SPECIAL | 032 | 0300,
+ OPC_DIVU = OPC_SPECIAL | 033,
+ OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
+ OPC_MODU = OPC_SPECIAL | 033 | 0300,
+ OPC_DMULT = OPC_SPECIAL | 034,
+ OPC_DMUL = OPC_SPECIAL | 034 | 0200,
+ OPC_DMUH = OPC_SPECIAL | 034 | 0300,
+ OPC_DMULTU = OPC_SPECIAL | 035,
+ OPC_DMULU = OPC_SPECIAL | 035 | 0200,
+ OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
+ OPC_DDIV = OPC_SPECIAL | 036,
+ OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
+ OPC_DMOD = OPC_SPECIAL | 036 | 0300,
+ OPC_DDIVU = OPC_SPECIAL | 037,
+ OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
+ OPC_DMODU = OPC_SPECIAL | 037 | 0300,
+ OPC_ADDU = OPC_SPECIAL | 041,
+ OPC_SUBU = OPC_SPECIAL | 043,
+ OPC_AND = OPC_SPECIAL | 044,
+ OPC_OR = OPC_SPECIAL | 045,
+ OPC_XOR = OPC_SPECIAL | 046,
+ OPC_NOR = OPC_SPECIAL | 047,
+ OPC_SLT = OPC_SPECIAL | 052,
+ OPC_SLTU = OPC_SPECIAL | 053,
+ OPC_DADDU = OPC_SPECIAL | 055,
+ OPC_DSUBU = OPC_SPECIAL | 057,
+ OPC_SELEQZ = OPC_SPECIAL | 065,
+ OPC_SELNEZ = OPC_SPECIAL | 067,
+ OPC_DSLL = OPC_SPECIAL | 070,
+ OPC_DSRL = OPC_SPECIAL | 072,
+ OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
+ OPC_DSRA = OPC_SPECIAL | 073,
+ OPC_DSLL32 = OPC_SPECIAL | 074,
+ OPC_DSRL32 = OPC_SPECIAL | 076,
+ OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
+ OPC_DSRA32 = OPC_SPECIAL | 077,
+ OPC_CLZ_R6 = OPC_SPECIAL | 0120,
+ OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
+
+ OPC_REGIMM = 001 << 26,
+ OPC_BLTZ = OPC_REGIMM | (000 << 16),
+ OPC_BGEZ = OPC_REGIMM | (001 << 16),
+
+ OPC_SPECIAL2 = 034 << 26,
+ OPC_MUL_R5 = OPC_SPECIAL2 | 002,
+ OPC_CLZ = OPC_SPECIAL2 | 040,
+ OPC_DCLZ = OPC_SPECIAL2 | 044,
+
+ OPC_SPECIAL3 = 037 << 26,
+ OPC_EXT = OPC_SPECIAL3 | 000,
+ OPC_DEXTM = OPC_SPECIAL3 | 001,
+ OPC_DEXTU = OPC_SPECIAL3 | 002,
+ OPC_DEXT = OPC_SPECIAL3 | 003,
+ OPC_INS = OPC_SPECIAL3 | 004,
+ OPC_DINSM = OPC_SPECIAL3 | 005,
+ OPC_DINSU = OPC_SPECIAL3 | 006,
+ OPC_DINS = OPC_SPECIAL3 | 007,
+ OPC_WSBH = OPC_SPECIAL3 | 00240,
+ OPC_DSBH = OPC_SPECIAL3 | 00244,
+ OPC_DSHD = OPC_SPECIAL3 | 00544,
+ OPC_SEB = OPC_SPECIAL3 | 02040,
+ OPC_SEH = OPC_SPECIAL3 | 03040,
+
+ /* MIPS r6 doesn't have JR, JALR should be used instead */
+ OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
+
+ /*
+ * MIPS r6 replaces MUL with an alternative encoding which is
+ * backwards-compatible at the assembly level.
+ */
+ OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
+
+ /* MIPS r6 introduced names for weaker variants of SYNC. These are
+ backward compatible to previous architecture revisions. */
+ OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
+ OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
+ OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
+ OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
+ OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
+
+ /* Aliases for convenience. */
+ ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
+ ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
+ ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
+ ? OPC_SRL : OPC_DSRL,
+} MIPSInsn;
+
+/*
+ * Type reg
+ */
+static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
+ TCGReg rd, TCGReg rs, TCGReg rt)
+{
+ int32_t inst;
+
+ inst = opc;
+ inst |= (rs & 0x1F) << 21;
+ inst |= (rt & 0x1F) << 16;
+ inst |= (rd & 0x1F) << 11;
+ tcg_out32(s, inst);
+}
+
+/*
+ * Type immediate
+ */
+static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
+ TCGReg rt, TCGReg rs, TCGArg imm)
+{
+ int32_t inst;
+
+ inst = opc;
+ inst |= (rs & 0x1F) << 21;
+ inst |= (rt & 0x1F) << 16;
+ inst |= (imm & 0xffff);
+ tcg_out32(s, inst);
+}
+
+/*
+ * Type bitfield
+ */
+static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
+ TCGReg rs, int msb, int lsb)
+{
+ int32_t inst;
+
+ inst = opc;
+ inst |= (rs & 0x1F) << 21;
+ inst |= (rt & 0x1F) << 16;
+ inst |= (msb & 0x1F) << 11;
+ inst |= (lsb & 0x1F) << 6;
+ tcg_out32(s, inst);
+}
+
+static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
+ MIPSInsn oph, TCGReg rt, TCGReg rs,
+ int msb, int lsb)
+{
+ if (lsb >= 32) {
+ opc = oph;
+ msb -= 32;
+ lsb -= 32;
+ } else if (msb >= 32) {
+ opc = opm;
+ msb -= 32;
+ }
+ tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
+}
+
+/*
+ * Type branch
+ */
+static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
+ TCGReg rt, TCGReg rs)
+{
+ tcg_out_opc_imm(s, opc, rt, rs, 0);
+}
+
+/*
+ * Type sa
+ */
+static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
+ TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ int32_t inst;
+
+ inst = opc;
+ inst |= (rt & 0x1F) << 16;
+ inst |= (rd & 0x1F) << 11;
+ inst |= (sa & 0x1F) << 6;
+ tcg_out32(s, inst);
+
+}
+
+static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
+ TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ int32_t inst;
+
+ inst = (sa & 32 ? opc2 : opc1);
+ inst |= (rt & 0x1F) << 16;
+ inst |= (rd & 0x1F) << 11;
+ inst |= (sa & 0x1F) << 6;
+ tcg_out32(s, inst);
+}
+
+/*
+ * Type jump.
+ * Returns true if the branch was in range and the insn was emitted.
+ */
+static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
+{
+ uintptr_t dest = (uintptr_t)target;
+ uintptr_t from = (uintptr_t)s->code_ptr + 4;
+ int32_t inst;
+
+ /* The pc-region branch happens within the 256MB region of
+ the delay slot (thus the +4). */
+ if ((from ^ dest) & -(1 << 28)) {
+ return false;
+ }
+ tcg_debug_assert((dest & 3) == 0);
+
+ inst = opc;
+ inst |= (dest >> 2) & 0x3ffffff;
+ tcg_out32(s, inst);
+ return true;
+}
+
+static inline void tcg_out_nop(TCGContext *s)
+{
+ tcg_out32(s, 0);
+}
+
+static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
+}
+
+static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
+}
+
+static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
+}
+
+static inline bool tcg_out_mov(TCGContext *s, TCGType type,
+ TCGReg ret, TCGReg arg)
+{
+ /* Simple reg-reg move, optimising out the 'do nothing' case */
+ if (ret != arg) {
+ tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
+ }
+ return true;
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ arg = (int32_t)arg;
+ }
+ if (arg == (int16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (arg == (uint16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
+ } else {
+ tcg_out_dsll(s, ret, ret, 32);
+ }
+ }
+ if (arg & 0xffff) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
+ }
+}
+
+static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
+ } else {
+ /* ret and arg can't be register at */
+ if (ret == TCG_TMP0 || arg == TCG_TMP0) {
+ tcg_abort();
+ }
+
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
+ tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
+ tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
+ }
+}
+
+static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
+ tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
+ } else {
+ /* ret and arg can't be register at */
+ if (ret == TCG_TMP0 || arg == TCG_TMP0) {
+ tcg_abort();
+ }
+
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
+ tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
+ tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
+ }
+}
+
+static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
+{
+ bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
+ tcg_debug_assert(ok);
+}
+
+static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
+ tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot -- never omit the insn, like tcg_out_mov might. */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
+ }
+}
+
+static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
+ tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
+ tcg_out_dsrl(s, ret, ret, 32);
+ } else {
+ tcg_out_bswap_subr(s, bswap32u_addr);
+ /* delay slot -- never omit the insn, like tcg_out_mov might. */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
+ }
+}
+
+static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
+ tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
+ } else {
+ tcg_out_bswap_subr(s, bswap64_addr);
+ /* delay slot -- never omit the insn, like tcg_out_mov might. */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
+ }
+}
+
+static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
+ } else {
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
+ tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
+ }
+}
+
+static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
+ } else {
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
+ tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
+ }
+}
+
+static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
+ } else {
+ tcg_out_dsll(s, ret, arg, 32);
+ tcg_out_dsrl(s, ret, ret, 32);
+ }
+}
+
+static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
+ TCGReg addr, intptr_t ofs)
+{
+ int16_t lo = ofs;
+ if (ofs != lo) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
+ if (addr != TCG_REG_ZERO) {
+ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
+ }
+ addr = TCG_TMP0;
+ }
+ tcg_out_opc_imm(s, opc, data, addr, lo);
+}
+
+static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ MIPSInsn opc = OPC_LD;
+ if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
+ opc = OPC_LW;
+ }
+ tcg_out_ldst(s, opc, arg, arg1, arg2);
+}
+
+static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ MIPSInsn opc = OPC_SD;
+ if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
+ opc = OPC_SW;
+ }
+ tcg_out_ldst(s, opc, arg, arg1, arg2);
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ if (val == 0) {
+ tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
+ return true;
+ }
+ return false;
+}
+
+static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
+ TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
+ bool cbh, bool is_sub)
+{
+ TCGReg th = TCG_TMP1;
+
+ /* If we have a negative constant such that negating it would
+ make the high part zero, we can (usually) eliminate one insn. */
+ if (cbl && cbh && bh == -1 && bl != 0) {
+ bl = -bl;
+ bh = 0;
+ is_sub = !is_sub;
+ }
+
+ /* By operating on the high part first, we get to use the final
+ carry operation to move back from the temporary. */
+ if (!cbh) {
+ tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
+ } else if (bh != 0 || ah == rl) {
+ tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
+ } else {
+ th = ah;
+ }
+
+ /* Note that tcg optimization should eliminate the bl == 0 case. */
+ if (is_sub) {
+ if (cbl) {
+ tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
+ tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
+ } else {
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
+ tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
+ }
+ tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
+ } else {
+ if (cbl) {
+ tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
+ tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
+ } else if (rl == al && rl == bl) {
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
+ tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
+ } else {
+ tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
+ }
+ tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
+ }
+}
+
+/* Bit 0 set if inversion required; bit 1 set if swapping required. */
+#define MIPS_CMP_INV 1
+#define MIPS_CMP_SWAP 2
+
+static const uint8_t mips_cmp_map[16] = {
+ [TCG_COND_LT] = 0,
+ [TCG_COND_LTU] = 0,
+ [TCG_COND_GE] = MIPS_CMP_INV,
+ [TCG_COND_GEU] = MIPS_CMP_INV,
+ [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
+ [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
+ [TCG_COND_GT] = MIPS_CMP_SWAP,
+ [TCG_COND_GTU] = MIPS_CMP_SWAP,
+};
+
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg arg1, TCGReg arg2)
+{
+ MIPSInsn s_opc = OPC_SLTU;
+ int cmp_map;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ if (arg2 != 0) {
+ tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
+ arg1 = ret;
+ }
+ tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
+ break;
+
+ case TCG_COND_NE:
+ if (arg2 != 0) {
+ tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
+ arg1 = ret;
+ }
+ tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
+ break;
+
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ case TCG_COND_LE:
+ case TCG_COND_GT:
+ s_opc = OPC_SLT;
+ /* FALLTHRU */
+
+ case TCG_COND_LTU:
+ case TCG_COND_GEU:
+ case TCG_COND_LEU:
+ case TCG_COND_GTU:
+ cmp_map = mips_cmp_map[cond];
+ if (cmp_map & MIPS_CMP_SWAP) {
+ TCGReg t = arg1;
+ arg1 = arg2;
+ arg2 = t;
+ }
+ tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
+ if (cmp_map & MIPS_CMP_INV) {
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ }
+ break;
+
+ default:
+ tcg_abort();
+ break;
+ }
+}
+
+static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
+ TCGReg arg2, TCGLabel *l)
+{
+ static const MIPSInsn b_zero[16] = {
+ [TCG_COND_LT] = OPC_BLTZ,
+ [TCG_COND_GT] = OPC_BGTZ,
+ [TCG_COND_LE] = OPC_BLEZ,
+ [TCG_COND_GE] = OPC_BGEZ,
+ };
+
+ MIPSInsn s_opc = OPC_SLTU;
+ MIPSInsn b_opc;
+ int cmp_map;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ b_opc = OPC_BEQ;
+ break;
+ case TCG_COND_NE:
+ b_opc = OPC_BNE;
+ break;
+
+ case TCG_COND_LT:
+ case TCG_COND_GT:
+ case TCG_COND_LE:
+ case TCG_COND_GE:
+ if (arg2 == 0) {
+ b_opc = b_zero[cond];
+ arg2 = arg1;
+ arg1 = 0;
+ break;
+ }
+ s_opc = OPC_SLT;
+ /* FALLTHRU */
+
+ case TCG_COND_LTU:
+ case TCG_COND_GTU:
+ case TCG_COND_LEU:
+ case TCG_COND_GEU:
+ cmp_map = mips_cmp_map[cond];
+ if (cmp_map & MIPS_CMP_SWAP) {
+ TCGReg t = arg1;
+ arg1 = arg2;
+ arg2 = t;
+ }
+ tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
+ b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
+ arg1 = TCG_TMP0;
+ arg2 = TCG_REG_ZERO;
+ break;
+
+ default:
+ tcg_abort();
+ break;
+ }
+
+ tcg_out_opc_br(s, b_opc, arg1, arg2);
+ if (l->has_value) {
+ reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
+ } else {
+ tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
+ }
+ tcg_out_nop(s);
+}
+
+static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
+ TCGReg al, TCGReg ah,
+ TCGReg bl, TCGReg bh)
+{
+ /* Merge highpart comparison into AH. */
+ if (bh != 0) {
+ if (ah != 0) {
+ tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
+ ah = tmp0;
+ } else {
+ ah = bh;
+ }
+ }
+ /* Merge lowpart comparison into AL. */
+ if (bl != 0) {
+ if (al != 0) {
+ tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
+ al = tmp1;
+ } else {
+ al = bl;
+ }
+ }
+ /* Merge high and low part comparisons into AL. */
+ if (ah != 0) {
+ if (al != 0) {
+ tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
+ al = tmp0;
+ } else {
+ al = ah;
+ }
+ }
+ return al;
+}
+
+static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
+{
+ TCGReg tmp0 = TCG_TMP0;
+ TCGReg tmp1 = ret;
+
+ tcg_debug_assert(ret != TCG_TMP0);
+ if (ret == ah || ret == bh) {
+ tcg_debug_assert(ret != TCG_TMP1);
+ tmp1 = TCG_TMP1;
+ }
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
+ tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
+ break;
+
+ default:
+ tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
+ tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
+ tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
+ tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
+ tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
+ break;
+ }
+}
+
+static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
+ TCGReg bl, TCGReg bh, TCGLabel *l)
+{
+ TCGCond b_cond = TCG_COND_NE;
+ TCGReg tmp = TCG_TMP1;
+
+ /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
+ With setcond, we emit between 3 and 10 insns and only 1 branch,
+ which ought to get better branch prediction. */
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ b_cond = cond;
+ tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
+ break;
+
+ default:
+ /* Minimize code size by preferring a compare not requiring INV. */
+ if (mips_cmp_map[cond] & MIPS_CMP_INV) {
+ cond = tcg_invert_cond(cond);
+ b_cond = TCG_COND_EQ;
+ }
+ tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
+ break;
+ }
+
+ tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
+}
+
+static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
+{
+ bool eqz = false;
+
+ /* If one of the values is zero, put it last to match SEL*Z instructions */
+ if (use_mips32r6_instructions && v1 == 0) {
+ v1 = v2;
+ v2 = 0;
+ cond = tcg_invert_cond(cond);
+ }
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ eqz = true;
+ /* FALLTHRU */
+ case TCG_COND_NE:
+ if (c2 != 0) {
+ tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
+ c1 = TCG_TMP0;
+ }
+ break;
+
+ default:
+ /* Minimize code size by preferring a compare not requiring INV. */
+ if (mips_cmp_map[cond] & MIPS_CMP_INV) {
+ cond = tcg_invert_cond(cond);
+ eqz = true;
+ }
+ tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
+ c1 = TCG_TMP0;
+ break;
+ }
+
+ if (use_mips32r6_instructions) {
+ MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
+ MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
+
+ if (v2 != 0) {
+ tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
+ }
+ tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
+ if (v2 != 0) {
+ tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
+ }
+ } else {
+ MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
+
+ tcg_out_opc_reg(s, m_opc, ret, v1, c1);
+
+ /* This should be guaranteed via constraints */
+ tcg_debug_assert(v2 == ret);
+ }
+}
+
+static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
+{
+ /* Note that the ABI requires the called function's address to be
+ loaded into T9, even if a direct branch is in range. */
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
+
+ /* But do try a direct branch, allowing the cpu better insn prefetch. */
+ if (tail) {
+ if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
+ }
+ } else {
+ if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
+ tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
+ }
+ }
+}
+
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
+{
+ tcg_out_call_int(s, arg, false);
+ tcg_out_nop(s);
+}
+
+#if defined(CONFIG_SOFTMMU)
+#include "../tcg-ldst.c.inc"
+
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LESW] = helper_le_ldsw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BESW] = helper_be_ldsw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+#if TCG_TARGET_REG_BITS == 64
+ [MO_LESL] = helper_le_ldsl_mmu,
+ [MO_BESL] = helper_be_ldsl_mmu,
+#endif
+};
+
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+
+/* Helper routines for marshalling helper function arguments into
+ * the correct registers and stack.
+ * I is where we want to put this argument, and is updated and returned
+ * for the next call. ARG is the argument itself.
+ *
+ * We provide routines for arguments which are: immediate, 32 bit
+ * value in register, 16 and 8 bit values in register (which must be zero
+ * extended before use) and 64 bit value in a lo:hi register pair.
+ */
+
+static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
+{
+ if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
+ } else {
+ /* For N32 and N64, the initial offset is different. But there
+ we also have 8 argument register so we don't run out here. */
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
+ tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
+ }
+ return i + 1;
+}
+
+static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
+{
+ TCGReg tmp = TCG_TMP0;
+ if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
+ tmp = tcg_target_call_iarg_regs[i];
+ }
+ tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
+ return tcg_out_call_iarg_reg(s, i, tmp);
+}
+
+static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
+{
+ TCGReg tmp = TCG_TMP0;
+ if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
+ tmp = tcg_target_call_iarg_regs[i];
+ }
+ tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
+ return tcg_out_call_iarg_reg(s, i, tmp);
+}
+
+static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
+{
+ TCGReg tmp = TCG_TMP0;
+ if (arg == 0) {
+ tmp = TCG_REG_ZERO;
+ } else {
+ if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
+ tmp = tcg_target_call_iarg_regs[i];
+ }
+ tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
+ }
+ return tcg_out_call_iarg_reg(s, i, tmp);
+}
+
+static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
+{
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
+ i = (i + 1) & ~1;
+ i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
+ i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
+ return i;
+}
+
+/* We expect to use a 16-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
+
+/*
+ * Perform the tlb comparison operation.
+ * The complete host address is placed in BASE.
+ * Clobbers TMP0, TMP1, TMP2, TMP3.
+ */
+static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
+ TCGReg addrh, TCGMemOpIdx oi,
+ tcg_insn_unit *label_ptr[2], bool is_load)
+{
+ MemOp opc = get_memop(oi);
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+ int mem_index = get_mmuidx(oi);
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ int add_off = offsetof(CPUTLBEntry, addend);
+ int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+ target_ulong mask;
+
+ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
+
+ /* Extract the TLB index from the address into TMP3. */
+ tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
+
+ /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
+ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ /* We don't currently support unaligned accesses.
+ We could do so with mips32r6. */
+ if (a_bits < s_bits) {
+ a_bits = s_bits;
+ }
+
+ /* Mask the page bits, keeping the alignment bits to compare against. */
+ mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
+
+ /* Load the (low-half) tlb comparator. */
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
+ } else {
+ tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
+ : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
+ TCG_TMP0, TCG_TMP3, cmp_off);
+ tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
+ /* No second compare is required here;
+ load the tlb addend for the fast path. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
+ }
+ tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
+
+ /* Zero extend a 32-bit guest address for a 64-bit host. */
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addrl);
+ addrl = base;
+ }
+
+ label_ptr[0] = s->code_ptr;
+ tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
+
+ /* Load and test the high half tlb comparator. */
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ /* delay slot */
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
+
+ /* Load the tlb addend for the fast path. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
+
+ label_ptr[1] = s->code_ptr;
+ tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
+ }
+
+ /* delay slot */
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
+}
+
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
+ TCGType ext,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addrhi,
+ void *raddr, tcg_insn_unit *label_ptr[2])
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->type = ext;
+ label->datalo_reg = datalo;
+ label->datahi_reg = datahi;
+ label->addrlo_reg = addrlo;
+ label->addrhi_reg = addrhi;
+ label->raddr = raddr;
+ label->label_ptr[0] = label_ptr[0];
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ label->label_ptr[1] = label_ptr[1];
+ }
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ TCGMemOpIdx oi = l->oi;
+ MemOp opc = get_memop(oi);
+ TCGReg v0;
+ int i;
+
+ /* resolve label address */
+ reloc_pc16(l->label_ptr[0], s->code_ptr);
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ reloc_pc16(l->label_ptr[1], s->code_ptr);
+ }
+
+ i = 1;
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
+ } else {
+ i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
+ }
+ i = tcg_out_call_iarg_imm(s, i, oi);
+ i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
+ tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
+ /* delay slot */
+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
+
+ v0 = l->datalo_reg;
+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
+ /* We eliminated V0 from the possible output registers, so it
+ cannot be clobbered here. So we must move V1 first. */
+ if (MIPS_BE) {
+ tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
+ v0 = l->datahi_reg;
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
+ }
+ }
+
+ tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
+ reloc_pc16(s->code_ptr - 1, l->raddr);
+
+ /* delay slot */
+ if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
+ /* we always sign-extend 32-bit loads */
+ tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
+ } else {
+ tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
+ }
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ TCGMemOpIdx oi = l->oi;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
+ int i;
+
+ /* resolve label address */
+ reloc_pc16(l->label_ptr[0], s->code_ptr);
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ reloc_pc16(l->label_ptr[1], s->code_ptr);
+ }
+
+ i = 1;
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
+ } else {
+ i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
+ }
+ switch (s_bits) {
+ case MO_8:
+ i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
+ break;
+ case MO_16:
+ i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
+ break;
+ case MO_32:
+ i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
+ break;
+ case MO_64:
+ if (TCG_TARGET_REG_BITS == 32) {
+ i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
+ } else {
+ i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
+ }
+ break;
+ default:
+ tcg_abort();
+ }
+ i = tcg_out_call_iarg_imm(s, i, oi);
+
+ /* Tail call to the store helper. Thus force the return address
+ computation to take place in the return address register. */
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
+ i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
+ tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
+ /* delay slot */
+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
+ return true;
+}
+#endif
+
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
+ TCGReg base, MemOp opc, bool is_64)
+{
+ switch (opc & (MO_SSIZE | MO_BSWAP)) {
+ case MO_UB:
+ tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
+ break;
+ case MO_SB:
+ tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
+ break;
+ case MO_UW | MO_BSWAP:
+ tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
+ tcg_out_bswap16(s, lo, TCG_TMP1);
+ break;
+ case MO_UW:
+ tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
+ break;
+ case MO_SW | MO_BSWAP:
+ tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
+ tcg_out_bswap16s(s, lo, TCG_TMP1);
+ break;
+ case MO_SW:
+ tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
+ break;
+ case MO_UL | MO_BSWAP:
+ if (TCG_TARGET_REG_BITS == 64 && is_64) {
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
+ tcg_out_bswap32u(s, lo, lo);
+ } else {
+ tcg_out_bswap_subr(s, bswap32u_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
+ tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
+ }
+ break;
+ }
+ /* FALLTHRU */
+ case MO_SL | MO_BSWAP:
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+ tcg_out_bswap32(s, lo, lo);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
+ tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
+ }
+ break;
+ case MO_UL:
+ if (TCG_TARGET_REG_BITS == 64 && is_64) {
+ tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
+ break;
+ }
+ /* FALLTHRU */
+ case MO_SL:
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+ break;
+ case MO_Q | MO_BSWAP:
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
+ tcg_out_bswap64(s, lo, lo);
+ } else {
+ tcg_out_bswap_subr(s, bswap64_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
+ tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
+ }
+ } else if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
+ tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
+ tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot */
+ tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
+ tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
+ }
+ break;
+ case MO_Q:
+ /* Prefer to load from offset 0 first, but allow for overlap. */
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
+ } else if (MIPS_BE ? hi != base : lo == base) {
+ tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
+ tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
+ } else {
+ tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
+ tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
+ }
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
+{
+ TCGReg addr_regl, addr_regh __attribute__((unused));
+ TCGReg data_regl, data_regh;
+ TCGMemOpIdx oi;
+ MemOp opc;
+#if defined(CONFIG_SOFTMMU)
+ tcg_insn_unit *label_ptr[2];
+#endif
+ TCGReg base = TCG_REG_A0;
+
+ data_regl = *args++;
+ data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+ addr_regl = *args++;
+ addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+ tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+ add_qemu_ldst_label(s, 1, oi,
+ (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+ data_regl, data_regh, addr_regl, addr_regh,
+ s->code_ptr, label_ptr);
+#else
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addr_regl);
+ addr_regl = base;
+ }
+ if (guest_base == 0 && data_regl != addr_regl) {
+ base = addr_regl;
+ } else if (guest_base == (int16_t)guest_base) {
+ tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
+ } else {
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ }
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+#endif
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
+ TCGReg base, MemOp opc)
+{
+ /* Don't clutter the code below with checks to avoid bswapping ZERO. */
+ if ((lo | hi) == 0) {
+ opc &= ~MO_BSWAP;
+ }
+
+ switch (opc & (MO_SIZE | MO_BSWAP)) {
+ case MO_8:
+ tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
+ break;
+
+ case MO_16 | MO_BSWAP:
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
+ tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
+ lo = TCG_TMP1;
+ /* FALLTHRU */
+ case MO_16:
+ tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
+ break;
+
+ case MO_32 | MO_BSWAP:
+ tcg_out_bswap32(s, TCG_TMP3, lo);
+ lo = TCG_TMP3;
+ /* FALLTHRU */
+ case MO_32:
+ tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
+ break;
+
+ case MO_64 | MO_BSWAP:
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_bswap64(s, TCG_TMP3, lo);
+ tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
+ } else if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
+ tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
+ tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
+ } else {
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
+ }
+ break;
+ case MO_64:
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
+ } else {
+ tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
+ }
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
+{
+ TCGReg addr_regl, addr_regh __attribute__((unused));
+ TCGReg data_regl, data_regh;
+ TCGMemOpIdx oi;
+ MemOp opc;
+#if defined(CONFIG_SOFTMMU)
+ tcg_insn_unit *label_ptr[2];
+#endif
+ TCGReg base = TCG_REG_A0;
+
+ data_regl = *args++;
+ data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+ addr_regl = *args++;
+ addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+ tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
+ tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+ add_qemu_ldst_label(s, 0, oi,
+ (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+ data_regl, data_regh, addr_regl, addr_regh,
+ s->code_ptr, label_ptr);
+#else
+ base = TCG_REG_A0;
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addr_regl);
+ addr_regl = base;
+ }
+ if (guest_base == 0) {
+ base = addr_regl;
+ } else if (guest_base == (int16_t)guest_base) {
+ tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
+ } else {
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ }
+ tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+#endif
+}
+
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ static const MIPSInsn sync[] = {
+ /* Note that SYNC_MB is a slightly weaker than SYNC 0,
+ as the former is an ordering barrier and the latter
+ is a completion barrier. */
+ [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
+ [TCG_MO_LD_LD] = OPC_SYNC_RMB,
+ [TCG_MO_ST_ST] = OPC_SYNC_WMB,
+ [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
+ [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
+ [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
+ };
+ tcg_out32(s, sync[a0 & TCG_MO_ALL]);
+}
+
+static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
+ int width, TCGReg a0, TCGReg a1, TCGArg a2)
+{
+ if (use_mips32r6_instructions) {
+ if (a2 == width) {
+ tcg_out_opc_reg(s, opcv6, a0, a1, 0);
+ } else {
+ tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
+ tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
+ }
+ } else {
+ if (a2 == width) {
+ tcg_out_opc_reg(s, opcv2, a0, a1, a1);
+ } else if (a0 == a2) {
+ tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
+ tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
+ } else if (a0 != a1) {
+ tcg_out_opc_reg(s, opcv2, a0, a1, a1);
+ tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
+ } else {
+ tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
+ tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
+ tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
+ }
+ }
+}
+
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg *args, const int *const_args)
+{
+ MIPSInsn i1, i2;
+ TCGArg a0, a1, a2;
+ int c2;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+ c2 = const_args[2];
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ {
+ TCGReg b0 = TCG_REG_ZERO;
+
+ a0 = (intptr_t)a0;
+ if (a0 & ~0xffff) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
+ b0 = TCG_REG_V0;
+ }
+ if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
+ (uintptr_t)tb_ret_addr);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
+ }
+ tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
+ }
+ break;
+ case INDEX_op_goto_tb:
+ if (s->tb_jmp_insn_offset) {
+ /* direct jump method */
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ /* Avoid clobbering the address during retranslation. */
+ tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
+ } else {
+ /* indirect jump method */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
+ (uintptr_t)(s->tb_jmp_target_addr + a0));
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
+ }
+ tcg_out_nop(s);
+ set_jmp_reset_offset(s, a0);
+ break;
+ case INDEX_op_goto_ptr:
+ /* jmp to the given host address (could be epilogue) */
+ tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
+ tcg_out_nop(s);
+ break;
+ case INDEX_op_br:
+ tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
+ arg_label(a0));
+ break;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ i1 = OPC_LBU;
+ goto do_ldst;
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ i1 = OPC_LB;
+ goto do_ldst;
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ i1 = OPC_LHU;
+ goto do_ldst;
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ i1 = OPC_LH;
+ goto do_ldst;
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32s_i64:
+ i1 = OPC_LW;
+ goto do_ldst;
+ case INDEX_op_ld32u_i64:
+ i1 = OPC_LWU;
+ goto do_ldst;
+ case INDEX_op_ld_i64:
+ i1 = OPC_LD;
+ goto do_ldst;
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ i1 = OPC_SB;
+ goto do_ldst;
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ i1 = OPC_SH;
+ goto do_ldst;
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ i1 = OPC_SW;
+ goto do_ldst;
+ case INDEX_op_st_i64:
+ i1 = OPC_SD;
+ do_ldst:
+ tcg_out_ldst(s, i1, a0, a1, a2);
+ break;
+
+ case INDEX_op_add_i32:
+ i1 = OPC_ADDU, i2 = OPC_ADDIU;
+ goto do_binary;
+ case INDEX_op_add_i64:
+ i1 = OPC_DADDU, i2 = OPC_DADDIU;
+ goto do_binary;
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ i1 = OPC_OR, i2 = OPC_ORI;
+ goto do_binary;
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ i1 = OPC_XOR, i2 = OPC_XORI;
+ do_binary:
+ if (c2) {
+ tcg_out_opc_imm(s, i2, a0, a1, a2);
+ break;
+ }
+ do_binaryv:
+ tcg_out_opc_reg(s, i1, a0, a1, a2);
+ break;
+
+ case INDEX_op_sub_i32:
+ i1 = OPC_SUBU, i2 = OPC_ADDIU;
+ goto do_subtract;
+ case INDEX_op_sub_i64:
+ i1 = OPC_DSUBU, i2 = OPC_DADDIU;
+ do_subtract:
+ if (c2) {
+ tcg_out_opc_imm(s, i2, a0, a1, -a2);
+ break;
+ }
+ goto do_binaryv;
+ case INDEX_op_and_i32:
+ if (c2 && a2 != (uint16_t)a2) {
+ int msb = ctz32(~a2) - 1;
+ tcg_debug_assert(use_mips32r2_instructions);
+ tcg_debug_assert(is_p2m1(a2));
+ tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
+ break;
+ }
+ i1 = OPC_AND, i2 = OPC_ANDI;
+ goto do_binary;
+ case INDEX_op_and_i64:
+ if (c2 && a2 != (uint16_t)a2) {
+ int msb = ctz64(~a2) - 1;
+ tcg_debug_assert(use_mips32r2_instructions);
+ tcg_debug_assert(is_p2m1(a2));
+ tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
+ break;
+ }
+ i1 = OPC_AND, i2 = OPC_ANDI;
+ goto do_binary;
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ i1 = OPC_NOR;
+ goto do_binaryv;
+
+ case INDEX_op_mul_i32:
+ if (use_mips32_instructions) {
+ tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_MULT, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_mulsh_i32:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_MULT, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_muluh_i32:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_MULTU, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_div_i32:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DIV, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_divu_i32:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DIVU, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_rem_i32:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DIV, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_remu_i32:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DIVU, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_mul_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DMULT, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_mulsh_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DMULT, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_muluh_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DMULTU, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_div_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIV, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_divu_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIVU, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_rem_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIV, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_remu_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIVU, i2 = OPC_MFHI;
+ do_hilo1:
+ tcg_out_opc_reg(s, i1, 0, a1, a2);
+ tcg_out_opc_reg(s, i2, a0, 0, 0);
+ break;
+
+ case INDEX_op_muls2_i32:
+ i1 = OPC_MULT;
+ goto do_hilo2;
+ case INDEX_op_mulu2_i32:
+ i1 = OPC_MULTU;
+ goto do_hilo2;
+ case INDEX_op_muls2_i64:
+ i1 = OPC_DMULT;
+ goto do_hilo2;
+ case INDEX_op_mulu2_i64:
+ i1 = OPC_DMULTU;
+ do_hilo2:
+ tcg_out_opc_reg(s, i1, 0, a2, args[3]);
+ tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
+ tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
+ break;
+
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ i1 = OPC_NOR;
+ goto do_unary;
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ i1 = OPC_WSBH;
+ goto do_unary;
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ i1 = OPC_SEB;
+ goto do_unary;
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ i1 = OPC_SEH;
+ do_unary:
+ tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
+ break;
+
+ case INDEX_op_bswap32_i32:
+ tcg_out_bswap32(s, a0, a1);
+ break;
+ case INDEX_op_bswap32_i64:
+ tcg_out_bswap32u(s, a0, a1);
+ break;
+ case INDEX_op_bswap64_i64:
+ tcg_out_bswap64(s, a0, a1);
+ break;
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_dsra(s, a0, a1, 32);
+ break;
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
+ break;
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ tcg_out_ext32u(s, a0, a1);
+ break;
+
+ case INDEX_op_sar_i32:
+ i1 = OPC_SRAV, i2 = OPC_SRA;
+ goto do_shift;
+ case INDEX_op_shl_i32:
+ i1 = OPC_SLLV, i2 = OPC_SLL;
+ goto do_shift;
+ case INDEX_op_shr_i32:
+ i1 = OPC_SRLV, i2 = OPC_SRL;
+ goto do_shift;
+ case INDEX_op_rotr_i32:
+ i1 = OPC_ROTRV, i2 = OPC_ROTR;
+ do_shift:
+ if (c2) {
+ tcg_out_opc_sa(s, i2, a0, a1, a2);
+ break;
+ }
+ do_shiftv:
+ tcg_out_opc_reg(s, i1, a0, a2, a1);
+ break;
+ case INDEX_op_rotl_i32:
+ if (c2) {
+ tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
+ tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
+ }
+ break;
+ case INDEX_op_sar_i64:
+ if (c2) {
+ tcg_out_dsra(s, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DSRAV;
+ goto do_shiftv;
+ case INDEX_op_shl_i64:
+ if (c2) {
+ tcg_out_dsll(s, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DSLLV;
+ goto do_shiftv;
+ case INDEX_op_shr_i64:
+ if (c2) {
+ tcg_out_dsrl(s, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DSRLV;
+ goto do_shiftv;
+ case INDEX_op_rotr_i64:
+ if (c2) {
+ tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DROTRV;
+ goto do_shiftv;
+ case INDEX_op_rotl_i64:
+ if (c2) {
+ tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
+ tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
+ }
+ break;
+
+ case INDEX_op_clz_i32:
+ tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
+ break;
+ case INDEX_op_clz_i64:
+ tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
+ break;
+
+ case INDEX_op_deposit_i32:
+ tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
+ break;
+ case INDEX_op_deposit_i64:
+ tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
+ args[3] + args[4] - 1, args[3]);
+ break;
+ case INDEX_op_extract_i32:
+ tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
+ break;
+ case INDEX_op_extract_i64:
+ tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
+ args[3] - 1, a2);
+ break;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
+ break;
+ case INDEX_op_brcond2_i32:
+ tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
+ break;
+
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
+ break;
+
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond(s, args[3], a0, a1, a2);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_qemu_ld(s, args, false);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args, true);
+ break;
+ case INDEX_op_qemu_st_i32:
+ tcg_out_qemu_st(s, args, false);
+ break;
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args, true);
+ break;
+
+ case INDEX_op_add2_i32:
+ tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
+ const_args[4], const_args[5], false);
+ break;
+ case INDEX_op_sub2_i32:
+ tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
+ const_args[4], const_args[5], true);
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
+ static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
+ static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
+ static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
+ static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
+ static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
+ static const TCGTargetOpDef SZ_SZ_S
+ = { .args_ct_str = { "SZ", "SZ", "S" } };
+ static const TCGTargetOpDef SZ_SZ_S_S
+ = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
+ static const TCGTargetOpDef r_rZ_rN
+ = { .args_ct_str = { "r", "rZ", "rN" } };
+ static const TCGTargetOpDef r_rZ_rZ
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
+ static const TCGTargetOpDef r_r_rIK
+ = { .args_ct_str = { "r", "r", "rIK" } };
+ static const TCGTargetOpDef r_r_rWZ
+ = { .args_ct_str = { "r", "r", "rWZ" } };
+ static const TCGTargetOpDef r_r_r_r
+ = { .args_ct_str = { "r", "r", "r", "r" } };
+ static const TCGTargetOpDef r_r_L_L
+ = { .args_ct_str = { "r", "r", "L", "L" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
+ static const TCGTargetOpDef movc_r6
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
+ static const TCGTargetOpDef br2
+ = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
+ static const TCGTargetOpDef setc2
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ case INDEX_op_extract_i64:
+ return &r_r;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &rZ_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ return &r_r_rJ;
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ return &r_rZ_rN;
+ case INDEX_op_mul_i32:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_rem_i32:
+ case INDEX_op_remu_i32:
+ case INDEX_op_nor_i32:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i64:
+ case INDEX_op_nor_i64:
+ case INDEX_op_setcond_i64:
+ return &r_rZ_rZ;
+ case INDEX_op_muls2_i32:
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_muls2_i64:
+ case INDEX_op_mulu2_i64:
+ return &r_r_r_r;
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ return &r_r_rIK;
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i64:
+ return &r_r_rI;
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_rotl_i64:
+ return &r_r_ri;
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ return &r_r_rWZ;
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return &dep;
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &rZ_rZ;
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ return use_mips32r6_instructions ? &movc_r6 : &movc;
+
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return &add2;
+ case INDEX_op_setcond2_i32:
+ return &setc2;
+ case INDEX_op_brcond2_i32:
+ return &br2;
+
+ case INDEX_op_qemu_ld_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &r_L : &r_L_L);
+ case INDEX_op_qemu_st_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &SZ_S : &SZ_S_S);
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &r_L
+ : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
+ : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
+
+ default:
+ return NULL;
+ }
+}
+
+static const int tcg_target_callee_save_regs[] = {
+ TCG_REG_S0, /* used for the global env (TCG_AREG0) */
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+ TCG_REG_RA, /* should be last for ABI compliance */
+};
+
+/* The Linux kernel doesn't provide any information about the available
+ instruction set. Probe it using a signal handler. */
+
+
+#ifndef use_movnz_instructions
+bool use_movnz_instructions = false;
+#endif
+
+#ifndef use_mips32_instructions
+bool use_mips32_instructions = false;
+#endif
+
+#ifndef use_mips32r2_instructions
+bool use_mips32r2_instructions = false;
+#endif
+
+static volatile sig_atomic_t got_sigill;
+
+static void sigill_handler(int signo, siginfo_t *si, void *data)
+{
+ /* Skip the faulty instruction */
+ ucontext_t *uc = (ucontext_t *)data;
+ uc->uc_mcontext.pc += 4;
+
+ got_sigill = 1;
+}
+
+static void tcg_target_detect_isa(void)
+{
+ struct sigaction sa_old, sa_new;
+
+ memset(&sa_new, 0, sizeof(sa_new));
+ sa_new.sa_flags = SA_SIGINFO;
+ sa_new.sa_sigaction = sigill_handler;
+ sigaction(SIGILL, &sa_new, &sa_old);
+
+ /* Probe for movn/movz, necessary to implement movcond. */
+#ifndef use_movnz_instructions
+ got_sigill = 0;
+ asm volatile(".set push\n"
+ ".set mips32\n"
+ "movn $zero, $zero, $zero\n"
+ "movz $zero, $zero, $zero\n"
+ ".set pop\n"
+ : : : );
+ use_movnz_instructions = !got_sigill;
+#endif
+
+ /* Probe for MIPS32 instructions. As no subsetting is allowed
+ by the specification, it is only necessary to probe for one
+ of the instructions. */
+#ifndef use_mips32_instructions
+ got_sigill = 0;
+ asm volatile(".set push\n"
+ ".set mips32\n"
+ "mul $zero, $zero\n"
+ ".set pop\n"
+ : : : );
+ use_mips32_instructions = !got_sigill;
+#endif
+
+ /* Probe for MIPS32r2 instructions if MIPS32 instructions are
+ available. As no subsetting is allowed by the specification,
+ it is only necessary to probe for one of the instructions. */
+#ifndef use_mips32r2_instructions
+ if (use_mips32_instructions) {
+ got_sigill = 0;
+ asm volatile(".set push\n"
+ ".set mips32r2\n"
+ "seb $zero, $zero\n"
+ ".set pop\n"
+ : : : );
+ use_mips32r2_instructions = !got_sigill;
+ }
+#endif
+
+ sigaction(SIGILL, &sa_old, NULL);
+}
+
+static tcg_insn_unit *align_code_ptr(TCGContext *s)
+{
+ uintptr_t p = (uintptr_t)s->code_ptr;
+ if (p & 15) {
+ p = (p + 15) & -16;
+ s->code_ptr = (void *)p;
+ }
+ return s->code_ptr;
+}
+
+/* Stack frame parameters. */
+#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
+#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
+#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
+
+#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & -TCG_TARGET_STACK_ALIGN)
+#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
+
+/* We're expecting to be able to use an immediate for frame allocation. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
+
+/* Generate global QEMU prologue and epilogue code */
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ int i;
+
+ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
+
+ /* TB prologue */
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
+ }
+
+#ifndef CONFIG_SOFTMMU
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
+ /* Call generated code */
+ tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
+ /* delay slot */
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+
+ /*
+ * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
+ * and fall through to the rest of the epilogue.
+ */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
+
+ /* TB epilogue */
+ tb_ret_addr = s->code_ptr;
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
+ }
+
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* delay slot */
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
+
+ if (use_mips32r2_instructions) {
+ return;
+ }
+
+ /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
+ clobbers TCG_TMP1, TCG_TMP2. */
+
+ /*
+ * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
+ */
+ bswap32_addr = align_code_ptr(s);
+ /* t3 = (ssss)d000 */
+ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
+ /* t1 = 000a */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
+ /* t2 = 00c0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
+ /* t3 = d00a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 0abc */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
+ /* t2 = 0c00 */
+ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
+ /* t1 = 00b0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+ /* t3 = dc0a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* t3 = dcba -- delay slot */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ if (TCG_TARGET_REG_BITS == 32) {
+ return;
+ }
+
+ /*
+ * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
+ */
+ bswap32u_addr = align_code_ptr(s);
+ /* t1 = (0000)000d */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
+ /* t3 = 000a */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
+ /* t1 = (0000)d000 */
+ tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
+ /* t2 = 00c0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
+ /* t3 = d00a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 0abc */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
+ /* t2 = 0c00 */
+ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
+ /* t1 = 00b0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+ /* t3 = dc0a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* t3 = dcba -- delay slot */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ /*
+ * bswap64 -- 64-bit swap. a0 = abcdefgh
+ */
+ bswap64_addr = align_code_ptr(s);
+ /* t3 = h0000000 */
+ tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
+ /* t1 = 0000000a */
+ tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
+
+ /* t2 = 000000g0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
+ /* t3 = h000000a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 00000abc */
+ tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
+ /* t2 = 0g000000 */
+ tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
+ /* t1 = 000000b0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+
+ /* t3 = hg00000a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ /* t2 = 0000abcd */
+ tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
+ /* t3 = hg0000ba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ /* t1 = 000000c0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
+ /* t2 = 0000000d */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
+ /* t1 = 00000c00 */
+ tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
+ /* t2 = 0000d000 */
+ tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
+
+ /* t3 = hg000cba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 00abcdef */
+ tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
+ /* t3 = hg00dcba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+
+ /* t2 = 0000000f */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
+ /* t1 = 000000e0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+ /* t2 = 00f00000 */
+ tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
+ /* t1 = 000e0000 */
+ tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
+
+ /* t3 = hgf0dcba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* t3 = hgfedcba -- delay slot */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ tcg_target_detect_isa();
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
+ }
+
+ tcg_target_call_clobber_regs = 0;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
+}
+
+void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
+ uintptr_t addr)
+{
+ atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
+ flush_icache_range(jmp_addr, jmp_addr + 4);
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_MIPS
+/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
+ which is good because they're really quite complicated for MIPS. */
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.return_column = TCG_REG_RA,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
+ 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
+ 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
+ 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
+ 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
+ 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
+ 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
+ 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
+ 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
- * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
- * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifdef HOST_WORDS_BIGENDIAN
-# define MIPS_BE 1
-#else
-# define MIPS_BE 0
-#endif
-
-#if TCG_TARGET_REG_BITS == 32
-# define LO_OFF (MIPS_BE * 4)
-# define HI_OFF (4 - LO_OFF)
-#else
-/* To assert at compile-time that these values are never used
- for TCG_TARGET_REG_BITS == 64. */
-int link_error(void);
-# define LO_OFF link_error()
-# define HI_OFF link_error()
-#endif
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "zero",
- "at",
- "v0",
- "v1",
- "a0",
- "a1",
- "a2",
- "a3",
- "t0",
- "t1",
- "t2",
- "t3",
- "t4",
- "t5",
- "t6",
- "t7",
- "s0",
- "s1",
- "s2",
- "s3",
- "s4",
- "s5",
- "s6",
- "s7",
- "t8",
- "t9",
- "k0",
- "k1",
- "gp",
- "sp",
- "s8",
- "ra",
-};
-#endif
-
-#define TCG_TMP0 TCG_REG_AT
-#define TCG_TMP1 TCG_REG_T9
-#define TCG_TMP2 TCG_REG_T8
-#define TCG_TMP3 TCG_REG_T7
-
-#ifndef CONFIG_SOFTMMU
-#define TCG_GUEST_BASE_REG TCG_REG_S1
-#endif
-
-/* check if we really need so many registers :P */
-static const int tcg_target_reg_alloc_order[] = {
- /* Call saved registers. */
- TCG_REG_S0,
- TCG_REG_S1,
- TCG_REG_S2,
- TCG_REG_S3,
- TCG_REG_S4,
- TCG_REG_S5,
- TCG_REG_S6,
- TCG_REG_S7,
- TCG_REG_S8,
-
- /* Call clobbered registers. */
- TCG_REG_T4,
- TCG_REG_T5,
- TCG_REG_T6,
- TCG_REG_T7,
- TCG_REG_T8,
- TCG_REG_T9,
- TCG_REG_V1,
- TCG_REG_V0,
-
- /* Argument registers, opposite order of allocation. */
- TCG_REG_T3,
- TCG_REG_T2,
- TCG_REG_T1,
- TCG_REG_T0,
- TCG_REG_A3,
- TCG_REG_A2,
- TCG_REG_A1,
- TCG_REG_A0,
-};
-
-static const TCGReg tcg_target_call_iarg_regs[] = {
- TCG_REG_A0,
- TCG_REG_A1,
- TCG_REG_A2,
- TCG_REG_A3,
-#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
- TCG_REG_T0,
- TCG_REG_T1,
- TCG_REG_T2,
- TCG_REG_T3,
-#endif
-};
-
-static const TCGReg tcg_target_call_oarg_regs[2] = {
- TCG_REG_V0,
- TCG_REG_V1
-};
-
-static tcg_insn_unit *tb_ret_addr;
-static tcg_insn_unit *bswap32_addr;
-static tcg_insn_unit *bswap32u_addr;
-static tcg_insn_unit *bswap64_addr;
-
-static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- /* Let the compiler perform the right-shift as part of the arithmetic. */
- ptrdiff_t disp = target - (pc + 1);
- tcg_debug_assert(disp == (int16_t)disp);
- return disp & 0xffff;
-}
-
-static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
-}
-
-static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
- return ((uintptr_t)target >> 2) & 0x3ffffff;
-}
-
-static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
-}
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- tcg_debug_assert(type == R_MIPS_PC16);
- tcg_debug_assert(addend == 0);
- reloc_pc16(code_ptr, (tcg_insn_unit *)value);
- return true;
-}
-
-#define TCG_CT_CONST_ZERO 0x100
-#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
-#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
-#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
-#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
-#define TCG_CT_CONST_WSZ 0x2000 /* word size */
-
-static inline bool is_p2m1(tcg_target_long val)
-{
- return val && ((val + 1) & val) == 0;
-}
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch(*ct_str++) {
- case 'r':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- break;
- case 'L': /* qemu_ld input arg constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
- }
-#endif
- break;
- case 'S': /* qemu_st constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
- } else {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
- }
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_U16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'K':
- ct->ct |= TCG_CT_CONST_P2M1;
- break;
- case 'N':
- ct->ct |= TCG_CT_CONST_N16;
- break;
- case 'W':
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'Z':
- /* We are cheating a bit here, using the fact that the register
- ZERO is also the register number 0. Hence there is no need
- to check for const_args in each instruction. */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct;
- ct = arg_ct->ct;
- if (ct & TCG_CT_CONST) {
- return 1;
- } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
- return 1;
- } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
- return 1;
- } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
- return 1;
- } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
- return 1;
- } else if ((ct & TCG_CT_CONST_P2M1)
- && use_mips32r2_instructions && is_p2m1(val)) {
- return 1;
- } else if ((ct & TCG_CT_CONST_WSZ)
- && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
- return 1;
- }
- return 0;
-}
-
-/* instruction opcodes */
-typedef enum {
- OPC_J = 002 << 26,
- OPC_JAL = 003 << 26,
- OPC_BEQ = 004 << 26,
- OPC_BNE = 005 << 26,
- OPC_BLEZ = 006 << 26,
- OPC_BGTZ = 007 << 26,
- OPC_ADDIU = 011 << 26,
- OPC_SLTI = 012 << 26,
- OPC_SLTIU = 013 << 26,
- OPC_ANDI = 014 << 26,
- OPC_ORI = 015 << 26,
- OPC_XORI = 016 << 26,
- OPC_LUI = 017 << 26,
- OPC_DADDIU = 031 << 26,
- OPC_LB = 040 << 26,
- OPC_LH = 041 << 26,
- OPC_LW = 043 << 26,
- OPC_LBU = 044 << 26,
- OPC_LHU = 045 << 26,
- OPC_LWU = 047 << 26,
- OPC_SB = 050 << 26,
- OPC_SH = 051 << 26,
- OPC_SW = 053 << 26,
- OPC_LD = 067 << 26,
- OPC_SD = 077 << 26,
-
- OPC_SPECIAL = 000 << 26,
- OPC_SLL = OPC_SPECIAL | 000,
- OPC_SRL = OPC_SPECIAL | 002,
- OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
- OPC_SRA = OPC_SPECIAL | 003,
- OPC_SLLV = OPC_SPECIAL | 004,
- OPC_SRLV = OPC_SPECIAL | 006,
- OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
- OPC_SRAV = OPC_SPECIAL | 007,
- OPC_JR_R5 = OPC_SPECIAL | 010,
- OPC_JALR = OPC_SPECIAL | 011,
- OPC_MOVZ = OPC_SPECIAL | 012,
- OPC_MOVN = OPC_SPECIAL | 013,
- OPC_SYNC = OPC_SPECIAL | 017,
- OPC_MFHI = OPC_SPECIAL | 020,
- OPC_MFLO = OPC_SPECIAL | 022,
- OPC_DSLLV = OPC_SPECIAL | 024,
- OPC_DSRLV = OPC_SPECIAL | 026,
- OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
- OPC_DSRAV = OPC_SPECIAL | 027,
- OPC_MULT = OPC_SPECIAL | 030,
- OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
- OPC_MUH = OPC_SPECIAL | 030 | 0300,
- OPC_MULTU = OPC_SPECIAL | 031,
- OPC_MULU = OPC_SPECIAL | 031 | 0200,
- OPC_MUHU = OPC_SPECIAL | 031 | 0300,
- OPC_DIV = OPC_SPECIAL | 032,
- OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
- OPC_MOD = OPC_SPECIAL | 032 | 0300,
- OPC_DIVU = OPC_SPECIAL | 033,
- OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
- OPC_MODU = OPC_SPECIAL | 033 | 0300,
- OPC_DMULT = OPC_SPECIAL | 034,
- OPC_DMUL = OPC_SPECIAL | 034 | 0200,
- OPC_DMUH = OPC_SPECIAL | 034 | 0300,
- OPC_DMULTU = OPC_SPECIAL | 035,
- OPC_DMULU = OPC_SPECIAL | 035 | 0200,
- OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
- OPC_DDIV = OPC_SPECIAL | 036,
- OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
- OPC_DMOD = OPC_SPECIAL | 036 | 0300,
- OPC_DDIVU = OPC_SPECIAL | 037,
- OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
- OPC_DMODU = OPC_SPECIAL | 037 | 0300,
- OPC_ADDU = OPC_SPECIAL | 041,
- OPC_SUBU = OPC_SPECIAL | 043,
- OPC_AND = OPC_SPECIAL | 044,
- OPC_OR = OPC_SPECIAL | 045,
- OPC_XOR = OPC_SPECIAL | 046,
- OPC_NOR = OPC_SPECIAL | 047,
- OPC_SLT = OPC_SPECIAL | 052,
- OPC_SLTU = OPC_SPECIAL | 053,
- OPC_DADDU = OPC_SPECIAL | 055,
- OPC_DSUBU = OPC_SPECIAL | 057,
- OPC_SELEQZ = OPC_SPECIAL | 065,
- OPC_SELNEZ = OPC_SPECIAL | 067,
- OPC_DSLL = OPC_SPECIAL | 070,
- OPC_DSRL = OPC_SPECIAL | 072,
- OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
- OPC_DSRA = OPC_SPECIAL | 073,
- OPC_DSLL32 = OPC_SPECIAL | 074,
- OPC_DSRL32 = OPC_SPECIAL | 076,
- OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
- OPC_DSRA32 = OPC_SPECIAL | 077,
- OPC_CLZ_R6 = OPC_SPECIAL | 0120,
- OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
-
- OPC_REGIMM = 001 << 26,
- OPC_BLTZ = OPC_REGIMM | (000 << 16),
- OPC_BGEZ = OPC_REGIMM | (001 << 16),
-
- OPC_SPECIAL2 = 034 << 26,
- OPC_MUL_R5 = OPC_SPECIAL2 | 002,
- OPC_CLZ = OPC_SPECIAL2 | 040,
- OPC_DCLZ = OPC_SPECIAL2 | 044,
-
- OPC_SPECIAL3 = 037 << 26,
- OPC_EXT = OPC_SPECIAL3 | 000,
- OPC_DEXTM = OPC_SPECIAL3 | 001,
- OPC_DEXTU = OPC_SPECIAL3 | 002,
- OPC_DEXT = OPC_SPECIAL3 | 003,
- OPC_INS = OPC_SPECIAL3 | 004,
- OPC_DINSM = OPC_SPECIAL3 | 005,
- OPC_DINSU = OPC_SPECIAL3 | 006,
- OPC_DINS = OPC_SPECIAL3 | 007,
- OPC_WSBH = OPC_SPECIAL3 | 00240,
- OPC_DSBH = OPC_SPECIAL3 | 00244,
- OPC_DSHD = OPC_SPECIAL3 | 00544,
- OPC_SEB = OPC_SPECIAL3 | 02040,
- OPC_SEH = OPC_SPECIAL3 | 03040,
-
- /* MIPS r6 doesn't have JR, JALR should be used instead */
- OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
-
- /*
- * MIPS r6 replaces MUL with an alternative encoding which is
- * backwards-compatible at the assembly level.
- */
- OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
-
- /* MIPS r6 introduced names for weaker variants of SYNC. These are
- backward compatible to previous architecture revisions. */
- OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
- OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
- OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
- OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
- OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
-
- /* Aliases for convenience. */
- ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
- ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
- ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
- ? OPC_SRL : OPC_DSRL,
-} MIPSInsn;
-
-/*
- * Type reg
- */
-static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
- TCGReg rd, TCGReg rs, TCGReg rt)
-{
- int32_t inst;
-
- inst = opc;
- inst |= (rs & 0x1F) << 21;
- inst |= (rt & 0x1F) << 16;
- inst |= (rd & 0x1F) << 11;
- tcg_out32(s, inst);
-}
-
-/*
- * Type immediate
- */
-static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
- TCGReg rt, TCGReg rs, TCGArg imm)
-{
- int32_t inst;
-
- inst = opc;
- inst |= (rs & 0x1F) << 21;
- inst |= (rt & 0x1F) << 16;
- inst |= (imm & 0xffff);
- tcg_out32(s, inst);
-}
-
-/*
- * Type bitfield
- */
-static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
- TCGReg rs, int msb, int lsb)
-{
- int32_t inst;
-
- inst = opc;
- inst |= (rs & 0x1F) << 21;
- inst |= (rt & 0x1F) << 16;
- inst |= (msb & 0x1F) << 11;
- inst |= (lsb & 0x1F) << 6;
- tcg_out32(s, inst);
-}
-
-static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
- MIPSInsn oph, TCGReg rt, TCGReg rs,
- int msb, int lsb)
-{
- if (lsb >= 32) {
- opc = oph;
- msb -= 32;
- lsb -= 32;
- } else if (msb >= 32) {
- opc = opm;
- msb -= 32;
- }
- tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
-}
-
-/*
- * Type branch
- */
-static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
- TCGReg rt, TCGReg rs)
-{
- tcg_out_opc_imm(s, opc, rt, rs, 0);
-}
-
-/*
- * Type sa
- */
-static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
- TCGReg rd, TCGReg rt, TCGArg sa)
-{
- int32_t inst;
-
- inst = opc;
- inst |= (rt & 0x1F) << 16;
- inst |= (rd & 0x1F) << 11;
- inst |= (sa & 0x1F) << 6;
- tcg_out32(s, inst);
-
-}
-
-static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
- TCGReg rd, TCGReg rt, TCGArg sa)
-{
- int32_t inst;
-
- inst = (sa & 32 ? opc2 : opc1);
- inst |= (rt & 0x1F) << 16;
- inst |= (rd & 0x1F) << 11;
- inst |= (sa & 0x1F) << 6;
- tcg_out32(s, inst);
-}
-
-/*
- * Type jump.
- * Returns true if the branch was in range and the insn was emitted.
- */
-static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
-{
- uintptr_t dest = (uintptr_t)target;
- uintptr_t from = (uintptr_t)s->code_ptr + 4;
- int32_t inst;
-
- /* The pc-region branch happens within the 256MB region of
- the delay slot (thus the +4). */
- if ((from ^ dest) & -(1 << 28)) {
- return false;
- }
- tcg_debug_assert((dest & 3) == 0);
-
- inst = opc;
- inst |= (dest >> 2) & 0x3ffffff;
- tcg_out32(s, inst);
- return true;
-}
-
-static inline void tcg_out_nop(TCGContext *s)
-{
- tcg_out32(s, 0);
-}
-
-static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
-{
- tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
-}
-
-static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
-{
- tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
-}
-
-static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
-{
- tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
-}
-
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
-{
- /* Simple reg-reg move, optimising out the 'do nothing' case */
- if (ret != arg) {
- tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
- }
- return true;
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
-{
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
- arg = (int32_t)arg;
- }
- if (arg == (int16_t)arg) {
- tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
- return;
- }
- if (arg == (uint16_t)arg) {
- tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
- return;
- }
- if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
- tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
- } else {
- tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
- if (arg & 0xffff0000ull) {
- tcg_out_dsll(s, ret, ret, 16);
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
- tcg_out_dsll(s, ret, ret, 16);
- } else {
- tcg_out_dsll(s, ret, ret, 32);
- }
- }
- if (arg & 0xffff) {
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
- }
-}
-
-static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- } else {
- /* ret and arg can't be register at */
- if (ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
- }
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
- tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
- }
-}
-
-static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
- } else {
- /* ret and arg can't be register at */
- if (ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
- }
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
- }
-}
-
-static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
-{
- bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
- tcg_debug_assert(ok);
-}
-
-static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
- } else {
- tcg_out_bswap_subr(s, bswap32_addr);
- /* delay slot -- never omit the insn, like tcg_out_mov might. */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
- tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
- }
-}
-
-static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
- tcg_out_dsrl(s, ret, ret, 32);
- } else {
- tcg_out_bswap_subr(s, bswap32u_addr);
- /* delay slot -- never omit the insn, like tcg_out_mov might. */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
- tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
- }
-}
-
-static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
- } else {
- tcg_out_bswap_subr(s, bswap64_addr);
- /* delay slot -- never omit the insn, like tcg_out_mov might. */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
- tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
- }
-}
-
-static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
- } else {
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
- }
-}
-
-static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
- } else {
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
- }
-}
-
-static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
- } else {
- tcg_out_dsll(s, ret, arg, 32);
- tcg_out_dsrl(s, ret, ret, 32);
- }
-}
-
-static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
- TCGReg addr, intptr_t ofs)
-{
- int16_t lo = ofs;
- if (ofs != lo) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
- if (addr != TCG_REG_ZERO) {
- tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
- }
- addr = TCG_TMP0;
- }
- tcg_out_opc_imm(s, opc, data, addr, lo);
-}
-
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- MIPSInsn opc = OPC_LD;
- if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
- opc = OPC_LW;
- }
- tcg_out_ldst(s, opc, arg, arg1, arg2);
-}
-
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- MIPSInsn opc = OPC_SD;
- if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
- opc = OPC_SW;
- }
- tcg_out_ldst(s, opc, arg, arg1, arg2);
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- if (val == 0) {
- tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
- return true;
- }
- return false;
-}
-
-static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
- TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
- bool cbh, bool is_sub)
-{
- TCGReg th = TCG_TMP1;
-
- /* If we have a negative constant such that negating it would
- make the high part zero, we can (usually) eliminate one insn. */
- if (cbl && cbh && bh == -1 && bl != 0) {
- bl = -bl;
- bh = 0;
- is_sub = !is_sub;
- }
-
- /* By operating on the high part first, we get to use the final
- carry operation to move back from the temporary. */
- if (!cbh) {
- tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
- } else if (bh != 0 || ah == rl) {
- tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
- } else {
- th = ah;
- }
-
- /* Note that tcg optimization should eliminate the bl == 0 case. */
- if (is_sub) {
- if (cbl) {
- tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
- tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
- } else {
- tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
- tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
- }
- tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
- } else {
- if (cbl) {
- tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
- tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
- } else if (rl == al && rl == bl) {
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
- tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
- } else {
- tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
- tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
- }
- tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
- }
-}
-
-/* Bit 0 set if inversion required; bit 1 set if swapping required. */
-#define MIPS_CMP_INV 1
-#define MIPS_CMP_SWAP 2
-
-static const uint8_t mips_cmp_map[16] = {
- [TCG_COND_LT] = 0,
- [TCG_COND_LTU] = 0,
- [TCG_COND_GE] = MIPS_CMP_INV,
- [TCG_COND_GEU] = MIPS_CMP_INV,
- [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
- [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
- [TCG_COND_GT] = MIPS_CMP_SWAP,
- [TCG_COND_GTU] = MIPS_CMP_SWAP,
-};
-
-static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg arg1, TCGReg arg2)
-{
- MIPSInsn s_opc = OPC_SLTU;
- int cmp_map;
-
- switch (cond) {
- case TCG_COND_EQ:
- if (arg2 != 0) {
- tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
- arg1 = ret;
- }
- tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
- break;
-
- case TCG_COND_NE:
- if (arg2 != 0) {
- tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
- arg1 = ret;
- }
- tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
- break;
-
- case TCG_COND_LT:
- case TCG_COND_GE:
- case TCG_COND_LE:
- case TCG_COND_GT:
- s_opc = OPC_SLT;
- /* FALLTHRU */
-
- case TCG_COND_LTU:
- case TCG_COND_GEU:
- case TCG_COND_LEU:
- case TCG_COND_GTU:
- cmp_map = mips_cmp_map[cond];
- if (cmp_map & MIPS_CMP_SWAP) {
- TCGReg t = arg1;
- arg1 = arg2;
- arg2 = t;
- }
- tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
- if (cmp_map & MIPS_CMP_INV) {
- tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
- }
- break;
-
- default:
- tcg_abort();
- break;
- }
-}
-
-static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
- TCGReg arg2, TCGLabel *l)
-{
- static const MIPSInsn b_zero[16] = {
- [TCG_COND_LT] = OPC_BLTZ,
- [TCG_COND_GT] = OPC_BGTZ,
- [TCG_COND_LE] = OPC_BLEZ,
- [TCG_COND_GE] = OPC_BGEZ,
- };
-
- MIPSInsn s_opc = OPC_SLTU;
- MIPSInsn b_opc;
- int cmp_map;
-
- switch (cond) {
- case TCG_COND_EQ:
- b_opc = OPC_BEQ;
- break;
- case TCG_COND_NE:
- b_opc = OPC_BNE;
- break;
-
- case TCG_COND_LT:
- case TCG_COND_GT:
- case TCG_COND_LE:
- case TCG_COND_GE:
- if (arg2 == 0) {
- b_opc = b_zero[cond];
- arg2 = arg1;
- arg1 = 0;
- break;
- }
- s_opc = OPC_SLT;
- /* FALLTHRU */
-
- case TCG_COND_LTU:
- case TCG_COND_GTU:
- case TCG_COND_LEU:
- case TCG_COND_GEU:
- cmp_map = mips_cmp_map[cond];
- if (cmp_map & MIPS_CMP_SWAP) {
- TCGReg t = arg1;
- arg1 = arg2;
- arg2 = t;
- }
- tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
- b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
- arg1 = TCG_TMP0;
- arg2 = TCG_REG_ZERO;
- break;
-
- default:
- tcg_abort();
- break;
- }
-
- tcg_out_opc_br(s, b_opc, arg1, arg2);
- if (l->has_value) {
- reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
- } else {
- tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
- }
- tcg_out_nop(s);
-}
-
-static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
- TCGReg al, TCGReg ah,
- TCGReg bl, TCGReg bh)
-{
- /* Merge highpart comparison into AH. */
- if (bh != 0) {
- if (ah != 0) {
- tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
- ah = tmp0;
- } else {
- ah = bh;
- }
- }
- /* Merge lowpart comparison into AL. */
- if (bl != 0) {
- if (al != 0) {
- tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
- al = tmp1;
- } else {
- al = bl;
- }
- }
- /* Merge high and low part comparisons into AL. */
- if (ah != 0) {
- if (al != 0) {
- tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
- al = tmp0;
- } else {
- al = ah;
- }
- }
- return al;
-}
-
-static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
-{
- TCGReg tmp0 = TCG_TMP0;
- TCGReg tmp1 = ret;
-
- tcg_debug_assert(ret != TCG_TMP0);
- if (ret == ah || ret == bh) {
- tcg_debug_assert(ret != TCG_TMP1);
- tmp1 = TCG_TMP1;
- }
-
- switch (cond) {
- case TCG_COND_EQ:
- case TCG_COND_NE:
- tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
- tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
- break;
-
- default:
- tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
- tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
- tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
- tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
- tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
- break;
- }
-}
-
-static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
- TCGReg bl, TCGReg bh, TCGLabel *l)
-{
- TCGCond b_cond = TCG_COND_NE;
- TCGReg tmp = TCG_TMP1;
-
- /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
- With setcond, we emit between 3 and 10 insns and only 1 branch,
- which ought to get better branch prediction. */
- switch (cond) {
- case TCG_COND_EQ:
- case TCG_COND_NE:
- b_cond = cond;
- tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
- break;
-
- default:
- /* Minimize code size by preferring a compare not requiring INV. */
- if (mips_cmp_map[cond] & MIPS_CMP_INV) {
- cond = tcg_invert_cond(cond);
- b_cond = TCG_COND_EQ;
- }
- tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
- break;
- }
-
- tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
-}
-
-static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
-{
- bool eqz = false;
-
- /* If one of the values is zero, put it last to match SEL*Z instructions */
- if (use_mips32r6_instructions && v1 == 0) {
- v1 = v2;
- v2 = 0;
- cond = tcg_invert_cond(cond);
- }
-
- switch (cond) {
- case TCG_COND_EQ:
- eqz = true;
- /* FALLTHRU */
- case TCG_COND_NE:
- if (c2 != 0) {
- tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
- c1 = TCG_TMP0;
- }
- break;
-
- default:
- /* Minimize code size by preferring a compare not requiring INV. */
- if (mips_cmp_map[cond] & MIPS_CMP_INV) {
- cond = tcg_invert_cond(cond);
- eqz = true;
- }
- tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
- c1 = TCG_TMP0;
- break;
- }
-
- if (use_mips32r6_instructions) {
- MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
- MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
-
- if (v2 != 0) {
- tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
- }
- tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
- if (v2 != 0) {
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
- }
- } else {
- MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
-
- tcg_out_opc_reg(s, m_opc, ret, v1, c1);
-
- /* This should be guaranteed via constraints */
- tcg_debug_assert(v2 == ret);
- }
-}
-
-static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
-{
- /* Note that the ABI requires the called function's address to be
- loaded into T9, even if a direct branch is in range. */
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
-
- /* But do try a direct branch, allowing the cpu better insn prefetch. */
- if (tail) {
- if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
- }
- } else {
- if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
- tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
- }
- }
-}
-
-static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
-{
- tcg_out_call_int(s, arg, false);
- tcg_out_nop(s);
-}
-
-#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
-
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
-#if TCG_TARGET_REG_BITS == 64
- [MO_LESL] = helper_le_ldsl_mmu,
- [MO_BESL] = helper_be_ldsl_mmu,
-#endif
-};
-
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-
-/* Helper routines for marshalling helper function arguments into
- * the correct registers and stack.
- * I is where we want to put this argument, and is updated and returned
- * for the next call. ARG is the argument itself.
- *
- * We provide routines for arguments which are: immediate, 32 bit
- * value in register, 16 and 8 bit values in register (which must be zero
- * extended before use) and 64 bit value in a lo:hi register pair.
- */
-
-static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
-{
- if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
- tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
- } else {
- /* For N32 and N64, the initial offset is different. But there
- we also have 8 argument register so we don't run out here. */
- tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
- tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
- }
- return i + 1;
-}
-
-static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
-{
- TCGReg tmp = TCG_TMP0;
- if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
- tmp = tcg_target_call_iarg_regs[i];
- }
- tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
- return tcg_out_call_iarg_reg(s, i, tmp);
-}
-
-static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
-{
- TCGReg tmp = TCG_TMP0;
- if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
- tmp = tcg_target_call_iarg_regs[i];
- }
- tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
- return tcg_out_call_iarg_reg(s, i, tmp);
-}
-
-static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
-{
- TCGReg tmp = TCG_TMP0;
- if (arg == 0) {
- tmp = TCG_REG_ZERO;
- } else {
- if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
- tmp = tcg_target_call_iarg_regs[i];
- }
- tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
- }
- return tcg_out_call_iarg_reg(s, i, tmp);
-}
-
-static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
-{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
- i = (i + 1) & ~1;
- i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
- i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
- return i;
-}
-
-/* We expect to use a 16-bit negative offset from ENV. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
-
-/*
- * Perform the tlb comparison operation.
- * The complete host address is placed in BASE.
- * Clobbers TMP0, TMP1, TMP2, TMP3.
- */
-static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
- TCGReg addrh, TCGMemOpIdx oi,
- tcg_insn_unit *label_ptr[2], bool is_load)
-{
- MemOp opc = get_memop(oi);
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
- int mem_index = get_mmuidx(oi);
- int fast_off = TLB_MASK_TABLE_OFS(mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- int add_off = offsetof(CPUTLBEntry, addend);
- int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write));
- target_ulong mask;
-
- /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
-
- /* Extract the TLB index from the address into TMP3. */
- tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
-
- /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
- tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
-
- /* We don't currently support unaligned accesses.
- We could do so with mips32r6. */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
-
- /* Mask the page bits, keeping the alignment bits to compare against. */
- mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
-
- /* Load the (low-half) tlb comparator. */
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
- tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
- } else {
- tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
- : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
- TCG_TMP0, TCG_TMP3, cmp_off);
- tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
- /* No second compare is required here;
- load the tlb addend for the fast path. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
- }
- tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
-
- /* Zero extend a 32-bit guest address for a 64-bit host. */
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addrl);
- addrl = base;
- }
-
- label_ptr[0] = s->code_ptr;
- tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
-
- /* Load and test the high half tlb comparator. */
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- /* delay slot */
- tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
-
- /* Load the tlb addend for the fast path. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
-
- label_ptr[1] = s->code_ptr;
- tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
- }
-
- /* delay slot */
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
-}
-
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
- TCGType ext,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- void *raddr, tcg_insn_unit *label_ptr[2])
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->type = ext;
- label->datalo_reg = datalo;
- label->datahi_reg = datahi;
- label->addrlo_reg = addrlo;
- label->addrhi_reg = addrhi;
- label->raddr = raddr;
- label->label_ptr[0] = label_ptr[0];
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- label->label_ptr[1] = label_ptr[1];
- }
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- TCGMemOpIdx oi = l->oi;
- MemOp opc = get_memop(oi);
- TCGReg v0;
- int i;
-
- /* resolve label address */
- reloc_pc16(l->label_ptr[0], s->code_ptr);
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- reloc_pc16(l->label_ptr[1], s->code_ptr);
- }
-
- i = 1;
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
- } else {
- i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
- }
- i = tcg_out_call_iarg_imm(s, i, oi);
- i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
- tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
- /* delay slot */
- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
-
- v0 = l->datalo_reg;
- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
- /* We eliminated V0 from the possible output registers, so it
- cannot be clobbered here. So we must move V1 first. */
- if (MIPS_BE) {
- tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
- v0 = l->datahi_reg;
- } else {
- tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
- }
- }
-
- tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
- reloc_pc16(s->code_ptr - 1, l->raddr);
-
- /* delay slot */
- if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
- /* we always sign-extend 32-bit loads */
- tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
- } else {
- tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
- }
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- TCGMemOpIdx oi = l->oi;
- MemOp opc = get_memop(oi);
- MemOp s_bits = opc & MO_SIZE;
- int i;
-
- /* resolve label address */
- reloc_pc16(l->label_ptr[0], s->code_ptr);
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- reloc_pc16(l->label_ptr[1], s->code_ptr);
- }
-
- i = 1;
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
- } else {
- i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
- }
- switch (s_bits) {
- case MO_8:
- i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
- break;
- case MO_16:
- i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
- break;
- case MO_32:
- i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
- break;
- case MO_64:
- if (TCG_TARGET_REG_BITS == 32) {
- i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
- } else {
- i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
- }
- break;
- default:
- tcg_abort();
- }
- i = tcg_out_call_iarg_imm(s, i, oi);
-
- /* Tail call to the store helper. Thus force the return address
- computation to take place in the return address register. */
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
- i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
- tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
- /* delay slot */
- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
- return true;
-}
-#endif
-
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, MemOp opc, bool is_64)
-{
- switch (opc & (MO_SSIZE | MO_BSWAP)) {
- case MO_UB:
- tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
- break;
- case MO_SB:
- tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
- break;
- case MO_UW | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16(s, lo, TCG_TMP1);
- break;
- case MO_UW:
- tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
- break;
- case MO_SW | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16s(s, lo, TCG_TMP1);
- break;
- case MO_SW:
- tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
- break;
- case MO_UL | MO_BSWAP:
- if (TCG_TARGET_REG_BITS == 64 && is_64) {
- if (use_mips32r2_instructions) {
- tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
- tcg_out_bswap32u(s, lo, lo);
- } else {
- tcg_out_bswap_subr(s, bswap32u_addr);
- /* delay slot */
- tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
- tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
- }
- break;
- }
- /* FALLTHRU */
- case MO_SL | MO_BSWAP:
- if (use_mips32r2_instructions) {
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- tcg_out_bswap32(s, lo, lo);
- } else {
- tcg_out_bswap_subr(s, bswap32_addr);
- /* delay slot */
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
- tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
- }
- break;
- case MO_UL:
- if (TCG_TARGET_REG_BITS == 64 && is_64) {
- tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
- break;
- }
- /* FALLTHRU */
- case MO_SL:
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- break;
- case MO_Q | MO_BSWAP:
- if (TCG_TARGET_REG_BITS == 64) {
- if (use_mips32r2_instructions) {
- tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
- tcg_out_bswap64(s, lo, lo);
- } else {
- tcg_out_bswap_subr(s, bswap64_addr);
- /* delay slot */
- tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
- tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
- }
- } else if (use_mips32r2_instructions) {
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
- tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
- tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
- } else {
- tcg_out_bswap_subr(s, bswap32_addr);
- /* delay slot */
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
- tcg_out_bswap_subr(s, bswap32_addr);
- /* delay slot */
- tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
- tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
- }
- break;
- case MO_Q:
- /* Prefer to load from offset 0 first, but allow for overlap. */
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
- } else if (MIPS_BE ? hi != base : lo == base) {
- tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
- tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
- } else {
- tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
- tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
- }
- break;
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
-{
- TCGReg addr_regl, addr_regh __attribute__((unused));
- TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
- tcg_insn_unit *label_ptr[2];
-#endif
- TCGReg base = TCG_REG_A0;
-
- data_regl = *args++;
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addr_regl = *args++;
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
- add_qemu_ldst_label(s, 1, oi,
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
- data_regl, data_regh, addr_regl, addr_regh,
- s->code_ptr, label_ptr);
-#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
- }
- if (guest_base == 0 && data_regl != addr_regl) {
- base = addr_regl;
- } else if (guest_base == (int16_t)guest_base) {
- tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
- } else {
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
- }
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
-#endif
-}
-
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, MemOp opc)
-{
- /* Don't clutter the code below with checks to avoid bswapping ZERO. */
- if ((lo | hi) == 0) {
- opc &= ~MO_BSWAP;
- }
-
- switch (opc & (MO_SIZE | MO_BSWAP)) {
- case MO_8:
- tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
- break;
-
- case MO_16 | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
- tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
- lo = TCG_TMP1;
- /* FALLTHRU */
- case MO_16:
- tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
- break;
-
- case MO_32 | MO_BSWAP:
- tcg_out_bswap32(s, TCG_TMP3, lo);
- lo = TCG_TMP3;
- /* FALLTHRU */
- case MO_32:
- tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
- break;
-
- case MO_64 | MO_BSWAP:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_bswap64(s, TCG_TMP3, lo);
- tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
- } else if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
- tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
- tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
- tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
- tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
- tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
- } else {
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
- tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
- tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
- }
- break;
- case MO_64:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
- } else {
- tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
- tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
- }
- break;
-
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
-{
- TCGReg addr_regl, addr_regh __attribute__((unused));
- TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
- tcg_insn_unit *label_ptr[2];
-#endif
- TCGReg base = TCG_REG_A0;
-
- data_regl = *args++;
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addr_regl = *args++;
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
- add_qemu_ldst_label(s, 0, oi,
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
- data_regl, data_regh, addr_regl, addr_regh,
- s->code_ptr, label_ptr);
-#else
- base = TCG_REG_A0;
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
- }
- if (guest_base == 0) {
- base = addr_regl;
- } else if (guest_base == (int16_t)guest_base) {
- tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
- } else {
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
- }
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
-#endif
-}
-
-static void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- static const MIPSInsn sync[] = {
- /* Note that SYNC_MB is a slightly weaker than SYNC 0,
- as the former is an ordering barrier and the latter
- is a completion barrier. */
- [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
- [TCG_MO_LD_LD] = OPC_SYNC_RMB,
- [TCG_MO_ST_ST] = OPC_SYNC_WMB,
- [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
- [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
- [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
- };
- tcg_out32(s, sync[a0 & TCG_MO_ALL]);
-}
-
-static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
- int width, TCGReg a0, TCGReg a1, TCGArg a2)
-{
- if (use_mips32r6_instructions) {
- if (a2 == width) {
- tcg_out_opc_reg(s, opcv6, a0, a1, 0);
- } else {
- tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
- tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
- }
- } else {
- if (a2 == width) {
- tcg_out_opc_reg(s, opcv2, a0, a1, a1);
- } else if (a0 == a2) {
- tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
- tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
- } else if (a0 != a1) {
- tcg_out_opc_reg(s, opcv2, a0, a1, a1);
- tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
- } else {
- tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
- tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
- tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
- }
- }
-}
-
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
-{
- MIPSInsn i1, i2;
- TCGArg a0, a1, a2;
- int c2;
-
- a0 = args[0];
- a1 = args[1];
- a2 = args[2];
- c2 = const_args[2];
-
- switch (opc) {
- case INDEX_op_exit_tb:
- {
- TCGReg b0 = TCG_REG_ZERO;
-
- a0 = (intptr_t)a0;
- if (a0 & ~0xffff) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
- b0 = TCG_REG_V0;
- }
- if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
- (uintptr_t)tb_ret_addr);
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
- }
- tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
- }
- break;
- case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* direct jump method */
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- /* Avoid clobbering the address during retranslation. */
- tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
- } else {
- /* indirect jump method */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
- (uintptr_t)(s->tb_jmp_target_addr + a0));
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
- }
- tcg_out_nop(s);
- set_jmp_reset_offset(s, a0);
- break;
- case INDEX_op_goto_ptr:
- /* jmp to the given host address (could be epilogue) */
- tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
- tcg_out_nop(s);
- break;
- case INDEX_op_br:
- tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
- arg_label(a0));
- break;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- i1 = OPC_LBU;
- goto do_ldst;
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld8s_i64:
- i1 = OPC_LB;
- goto do_ldst;
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- i1 = OPC_LHU;
- goto do_ldst;
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld16s_i64:
- i1 = OPC_LH;
- goto do_ldst;
- case INDEX_op_ld_i32:
- case INDEX_op_ld32s_i64:
- i1 = OPC_LW;
- goto do_ldst;
- case INDEX_op_ld32u_i64:
- i1 = OPC_LWU;
- goto do_ldst;
- case INDEX_op_ld_i64:
- i1 = OPC_LD;
- goto do_ldst;
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- i1 = OPC_SB;
- goto do_ldst;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- i1 = OPC_SH;
- goto do_ldst;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- i1 = OPC_SW;
- goto do_ldst;
- case INDEX_op_st_i64:
- i1 = OPC_SD;
- do_ldst:
- tcg_out_ldst(s, i1, a0, a1, a2);
- break;
-
- case INDEX_op_add_i32:
- i1 = OPC_ADDU, i2 = OPC_ADDIU;
- goto do_binary;
- case INDEX_op_add_i64:
- i1 = OPC_DADDU, i2 = OPC_DADDIU;
- goto do_binary;
- case INDEX_op_or_i32:
- case INDEX_op_or_i64:
- i1 = OPC_OR, i2 = OPC_ORI;
- goto do_binary;
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- i1 = OPC_XOR, i2 = OPC_XORI;
- do_binary:
- if (c2) {
- tcg_out_opc_imm(s, i2, a0, a1, a2);
- break;
- }
- do_binaryv:
- tcg_out_opc_reg(s, i1, a0, a1, a2);
- break;
-
- case INDEX_op_sub_i32:
- i1 = OPC_SUBU, i2 = OPC_ADDIU;
- goto do_subtract;
- case INDEX_op_sub_i64:
- i1 = OPC_DSUBU, i2 = OPC_DADDIU;
- do_subtract:
- if (c2) {
- tcg_out_opc_imm(s, i2, a0, a1, -a2);
- break;
- }
- goto do_binaryv;
- case INDEX_op_and_i32:
- if (c2 && a2 != (uint16_t)a2) {
- int msb = ctz32(~a2) - 1;
- tcg_debug_assert(use_mips32r2_instructions);
- tcg_debug_assert(is_p2m1(a2));
- tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
- break;
- }
- i1 = OPC_AND, i2 = OPC_ANDI;
- goto do_binary;
- case INDEX_op_and_i64:
- if (c2 && a2 != (uint16_t)a2) {
- int msb = ctz64(~a2) - 1;
- tcg_debug_assert(use_mips32r2_instructions);
- tcg_debug_assert(is_p2m1(a2));
- tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
- break;
- }
- i1 = OPC_AND, i2 = OPC_ANDI;
- goto do_binary;
- case INDEX_op_nor_i32:
- case INDEX_op_nor_i64:
- i1 = OPC_NOR;
- goto do_binaryv;
-
- case INDEX_op_mul_i32:
- if (use_mips32_instructions) {
- tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
- break;
- }
- i1 = OPC_MULT, i2 = OPC_MFLO;
- goto do_hilo1;
- case INDEX_op_mulsh_i32:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
- break;
- }
- i1 = OPC_MULT, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_muluh_i32:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
- break;
- }
- i1 = OPC_MULTU, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_div_i32:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
- break;
- }
- i1 = OPC_DIV, i2 = OPC_MFLO;
- goto do_hilo1;
- case INDEX_op_divu_i32:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
- break;
- }
- i1 = OPC_DIVU, i2 = OPC_MFLO;
- goto do_hilo1;
- case INDEX_op_rem_i32:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
- break;
- }
- i1 = OPC_DIV, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_remu_i32:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
- break;
- }
- i1 = OPC_DIVU, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_mul_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
- break;
- }
- i1 = OPC_DMULT, i2 = OPC_MFLO;
- goto do_hilo1;
- case INDEX_op_mulsh_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
- break;
- }
- i1 = OPC_DMULT, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_muluh_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
- break;
- }
- i1 = OPC_DMULTU, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_div_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
- break;
- }
- i1 = OPC_DDIV, i2 = OPC_MFLO;
- goto do_hilo1;
- case INDEX_op_divu_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
- break;
- }
- i1 = OPC_DDIVU, i2 = OPC_MFLO;
- goto do_hilo1;
- case INDEX_op_rem_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
- break;
- }
- i1 = OPC_DDIV, i2 = OPC_MFHI;
- goto do_hilo1;
- case INDEX_op_remu_i64:
- if (use_mips32r6_instructions) {
- tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
- break;
- }
- i1 = OPC_DDIVU, i2 = OPC_MFHI;
- do_hilo1:
- tcg_out_opc_reg(s, i1, 0, a1, a2);
- tcg_out_opc_reg(s, i2, a0, 0, 0);
- break;
-
- case INDEX_op_muls2_i32:
- i1 = OPC_MULT;
- goto do_hilo2;
- case INDEX_op_mulu2_i32:
- i1 = OPC_MULTU;
- goto do_hilo2;
- case INDEX_op_muls2_i64:
- i1 = OPC_DMULT;
- goto do_hilo2;
- case INDEX_op_mulu2_i64:
- i1 = OPC_DMULTU;
- do_hilo2:
- tcg_out_opc_reg(s, i1, 0, a2, args[3]);
- tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
- tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
- break;
-
- case INDEX_op_not_i32:
- case INDEX_op_not_i64:
- i1 = OPC_NOR;
- goto do_unary;
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- i1 = OPC_WSBH;
- goto do_unary;
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- i1 = OPC_SEB;
- goto do_unary;
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- i1 = OPC_SEH;
- do_unary:
- tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
- break;
-
- case INDEX_op_bswap32_i32:
- tcg_out_bswap32(s, a0, a1);
- break;
- case INDEX_op_bswap32_i64:
- tcg_out_bswap32u(s, a0, a1);
- break;
- case INDEX_op_bswap64_i64:
- tcg_out_bswap64(s, a0, a1);
- break;
- case INDEX_op_extrh_i64_i32:
- tcg_out_dsra(s, a0, a1, 32);
- break;
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extrl_i64_i32:
- tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
- break;
- case INDEX_op_ext32u_i64:
- case INDEX_op_extu_i32_i64:
- tcg_out_ext32u(s, a0, a1);
- break;
-
- case INDEX_op_sar_i32:
- i1 = OPC_SRAV, i2 = OPC_SRA;
- goto do_shift;
- case INDEX_op_shl_i32:
- i1 = OPC_SLLV, i2 = OPC_SLL;
- goto do_shift;
- case INDEX_op_shr_i32:
- i1 = OPC_SRLV, i2 = OPC_SRL;
- goto do_shift;
- case INDEX_op_rotr_i32:
- i1 = OPC_ROTRV, i2 = OPC_ROTR;
- do_shift:
- if (c2) {
- tcg_out_opc_sa(s, i2, a0, a1, a2);
- break;
- }
- do_shiftv:
- tcg_out_opc_reg(s, i1, a0, a2, a1);
- break;
- case INDEX_op_rotl_i32:
- if (c2) {
- tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
- } else {
- tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
- tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
- }
- break;
- case INDEX_op_sar_i64:
- if (c2) {
- tcg_out_dsra(s, a0, a1, a2);
- break;
- }
- i1 = OPC_DSRAV;
- goto do_shiftv;
- case INDEX_op_shl_i64:
- if (c2) {
- tcg_out_dsll(s, a0, a1, a2);
- break;
- }
- i1 = OPC_DSLLV;
- goto do_shiftv;
- case INDEX_op_shr_i64:
- if (c2) {
- tcg_out_dsrl(s, a0, a1, a2);
- break;
- }
- i1 = OPC_DSRLV;
- goto do_shiftv;
- case INDEX_op_rotr_i64:
- if (c2) {
- tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
- break;
- }
- i1 = OPC_DROTRV;
- goto do_shiftv;
- case INDEX_op_rotl_i64:
- if (c2) {
- tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
- } else {
- tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
- tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
- }
- break;
-
- case INDEX_op_clz_i32:
- tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
- break;
- case INDEX_op_clz_i64:
- tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
- break;
-
- case INDEX_op_deposit_i32:
- tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
- break;
- case INDEX_op_deposit_i64:
- tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
- args[3] + args[4] - 1, args[3]);
- break;
- case INDEX_op_extract_i32:
- tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
- break;
- case INDEX_op_extract_i64:
- tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
- args[3] - 1, a2);
- break;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
- break;
- case INDEX_op_brcond2_i32:
- tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
- break;
-
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
- break;
-
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- tcg_out_setcond(s, args[3], a0, a1, a2);
- break;
- case INDEX_op_setcond2_i32:
- tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
- break;
-
- case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, false);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, true);
- break;
- case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, false);
- break;
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, true);
- break;
-
- case INDEX_op_add2_i32:
- tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
- const_args[4], const_args[5], false);
- break;
- case INDEX_op_sub2_i32:
- tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
- const_args[4], const_args[5], true);
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, a0);
- break;
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
- static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
- static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
- static const TCGTargetOpDef SZ_SZ_S
- = { .args_ct_str = { "SZ", "SZ", "S" } };
- static const TCGTargetOpDef SZ_SZ_S_S
- = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_rWZ
- = { .args_ct_str = { "r", "r", "rWZ" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
- static const TCGTargetOpDef movc_r6
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_not_i32:
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap32_i32:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext16s_i32:
- case INDEX_op_extract_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_not_i64:
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap64_i64:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_extrl_i64_i32:
- case INDEX_op_extrh_i64_i32:
- case INDEX_op_extract_i64:
- return &r_r;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return &rZ_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_add_i64:
- return &r_r_rJ;
- case INDEX_op_sub_i32:
- case INDEX_op_sub_i64:
- return &r_rZ_rN;
- case INDEX_op_mul_i32:
- case INDEX_op_mulsh_i32:
- case INDEX_op_muluh_i32:
- case INDEX_op_div_i32:
- case INDEX_op_divu_i32:
- case INDEX_op_rem_i32:
- case INDEX_op_remu_i32:
- case INDEX_op_nor_i32:
- case INDEX_op_setcond_i32:
- case INDEX_op_mul_i64:
- case INDEX_op_mulsh_i64:
- case INDEX_op_muluh_i64:
- case INDEX_op_div_i64:
- case INDEX_op_divu_i64:
- case INDEX_op_rem_i64:
- case INDEX_op_remu_i64:
- case INDEX_op_nor_i64:
- case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
- case INDEX_op_muls2_i32:
- case INDEX_op_mulu2_i32:
- case INDEX_op_muls2_i64:
- case INDEX_op_mulu2_i64:
- return &r_r_r_r;
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
- return &r_r_rIK;
- case INDEX_op_or_i32:
- case INDEX_op_xor_i32:
- case INDEX_op_or_i64:
- case INDEX_op_xor_i64:
- return &r_r_rI;
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotl_i32:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_rotr_i64:
- case INDEX_op_rotl_i64:
- return &r_r_ri;
- case INDEX_op_clz_i32:
- case INDEX_op_clz_i64:
- return &r_r_rWZ;
-
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
- return &dep;
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return &rZ_rZ;
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- return use_mips32r6_instructions ? &movc_r6 : &movc;
-
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
- return &add2;
- case INDEX_op_setcond2_i32:
- return &setc2;
- case INDEX_op_brcond2_i32:
- return &br2;
-
- case INDEX_op_qemu_ld_i32:
- return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
- case INDEX_op_qemu_st_i32:
- return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &SZ_S : &SZ_S_S);
- case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
- case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
- : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
-
- default:
- return NULL;
- }
-}
-
-static const int tcg_target_callee_save_regs[] = {
- TCG_REG_S0, /* used for the global env (TCG_AREG0) */
- TCG_REG_S1,
- TCG_REG_S2,
- TCG_REG_S3,
- TCG_REG_S4,
- TCG_REG_S5,
- TCG_REG_S6,
- TCG_REG_S7,
- TCG_REG_S8,
- TCG_REG_RA, /* should be last for ABI compliance */
-};
-
-/* The Linux kernel doesn't provide any information about the available
- instruction set. Probe it using a signal handler. */
-
-
-#ifndef use_movnz_instructions
-bool use_movnz_instructions = false;
-#endif
-
-#ifndef use_mips32_instructions
-bool use_mips32_instructions = false;
-#endif
-
-#ifndef use_mips32r2_instructions
-bool use_mips32r2_instructions = false;
-#endif
-
-static volatile sig_atomic_t got_sigill;
-
-static void sigill_handler(int signo, siginfo_t *si, void *data)
-{
- /* Skip the faulty instruction */
- ucontext_t *uc = (ucontext_t *)data;
- uc->uc_mcontext.pc += 4;
-
- got_sigill = 1;
-}
-
-static void tcg_target_detect_isa(void)
-{
- struct sigaction sa_old, sa_new;
-
- memset(&sa_new, 0, sizeof(sa_new));
- sa_new.sa_flags = SA_SIGINFO;
- sa_new.sa_sigaction = sigill_handler;
- sigaction(SIGILL, &sa_new, &sa_old);
-
- /* Probe for movn/movz, necessary to implement movcond. */
-#ifndef use_movnz_instructions
- got_sigill = 0;
- asm volatile(".set push\n"
- ".set mips32\n"
- "movn $zero, $zero, $zero\n"
- "movz $zero, $zero, $zero\n"
- ".set pop\n"
- : : : );
- use_movnz_instructions = !got_sigill;
-#endif
-
- /* Probe for MIPS32 instructions. As no subsetting is allowed
- by the specification, it is only necessary to probe for one
- of the instructions. */
-#ifndef use_mips32_instructions
- got_sigill = 0;
- asm volatile(".set push\n"
- ".set mips32\n"
- "mul $zero, $zero\n"
- ".set pop\n"
- : : : );
- use_mips32_instructions = !got_sigill;
-#endif
-
- /* Probe for MIPS32r2 instructions if MIPS32 instructions are
- available. As no subsetting is allowed by the specification,
- it is only necessary to probe for one of the instructions. */
-#ifndef use_mips32r2_instructions
- if (use_mips32_instructions) {
- got_sigill = 0;
- asm volatile(".set push\n"
- ".set mips32r2\n"
- "seb $zero, $zero\n"
- ".set pop\n"
- : : : );
- use_mips32r2_instructions = !got_sigill;
- }
-#endif
-
- sigaction(SIGILL, &sa_old, NULL);
-}
-
-static tcg_insn_unit *align_code_ptr(TCGContext *s)
-{
- uintptr_t p = (uintptr_t)s->code_ptr;
- if (p & 15) {
- p = (p + 15) & -16;
- s->code_ptr = (void *)p;
- }
- return s->code_ptr;
-}
-
-/* Stack frame parameters. */
-#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
-#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
-#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
-
-#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
- + TCG_TARGET_STACK_ALIGN - 1) \
- & -TCG_TARGET_STACK_ALIGN)
-#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
-
-/* We're expecting to be able to use an immediate for frame allocation. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
-
-/* Generate global QEMU prologue and epilogue code */
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- int i;
-
- tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
-
- /* TB prologue */
- tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
- tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
- TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
- }
-
-#ifndef CONFIG_SOFTMMU
- if (guest_base) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
- tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
- }
-#endif
-
- /* Call generated code */
- tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
- /* delay slot */
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
-
- /*
- * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
- * and fall through to the rest of the epilogue.
- */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
-
- /* TB epilogue */
- tb_ret_addr = s->code_ptr;
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
- tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
- TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
- }
-
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
- /* delay slot */
- tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
-
- if (use_mips32r2_instructions) {
- return;
- }
-
- /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
- clobbers TCG_TMP1, TCG_TMP2. */
-
- /*
- * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
- */
- bswap32_addr = align_code_ptr(s);
- /* t3 = (ssss)d000 */
- tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
- /* t1 = 000a */
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
- /* t2 = 00c0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
- /* t3 = d00a */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
- /* t1 = 0abc */
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
- /* t2 = 0c00 */
- tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
- /* t1 = 00b0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
- /* t3 = dc0a */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
- /* t3 = dcba -- delay slot */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
-
- if (TCG_TARGET_REG_BITS == 32) {
- return;
- }
-
- /*
- * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
- */
- bswap32u_addr = align_code_ptr(s);
- /* t1 = (0000)000d */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
- /* t3 = 000a */
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
- /* t1 = (0000)d000 */
- tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
- /* t2 = 00c0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
- /* t3 = d00a */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
- /* t1 = 0abc */
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
- /* t2 = 0c00 */
- tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
- /* t1 = 00b0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
- /* t3 = dc0a */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
- /* t3 = dcba -- delay slot */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
-
- /*
- * bswap64 -- 64-bit swap. a0 = abcdefgh
- */
- bswap64_addr = align_code_ptr(s);
- /* t3 = h0000000 */
- tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
- /* t1 = 0000000a */
- tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
-
- /* t2 = 000000g0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
- /* t3 = h000000a */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
- /* t1 = 00000abc */
- tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
- /* t2 = 0g000000 */
- tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
- /* t1 = 000000b0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
-
- /* t3 = hg00000a */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
- /* t2 = 0000abcd */
- tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
- /* t3 = hg0000ba */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
-
- /* t1 = 000000c0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
- /* t2 = 0000000d */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
- /* t1 = 00000c00 */
- tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
- /* t2 = 0000d000 */
- tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
-
- /* t3 = hg000cba */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
- /* t1 = 00abcdef */
- tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
- /* t3 = hg00dcba */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
-
- /* t2 = 0000000f */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
- /* t1 = 000000e0 */
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
- /* t2 = 00f00000 */
- tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
- /* t1 = 000e0000 */
- tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
-
- /* t3 = hgf0dcba */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
- /* t3 = hgfedcba -- delay slot */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- tcg_target_detect_isa();
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
- }
-
- tcg_target_call_clobber_regs = 0;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
- tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
- tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
- tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
- tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
-}
-
-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
- uintptr_t addr)
-{
- atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
- flush_icache_range(jmp_addr, jmp_addr + 4);
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
-} DebugFrame;
-
-#define ELF_HOST_MACHINE EM_MIPS
-/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
- which is good because they're really quite complicated for MIPS. */
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
- .h.cie.return_column = TCG_REG_RA,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
- 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
- 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
- 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
- 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
- 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
- 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
- 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
- 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
- }
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "elf.h"
+#include "../tcg-pool.c.inc"
+
+#if defined _CALL_DARWIN || defined __APPLE__
+#define TCG_TARGET_CALL_DARWIN
+#endif
+#ifdef _CALL_SYSV
+# define TCG_TARGET_CALL_ALIGN_ARGS 1
+#endif
+
+/* For some memory operations, we need a scratch that isn't R0. For the AIX
+ calling convention, we can re-use the TOC register since we'll be reloading
+ it at every call. Otherwise R12 will do nicely as neither a call-saved
+ register nor a parameter register. */
+#ifdef _CALL_AIX
+# define TCG_REG_TMP1 TCG_REG_R2
+#else
+# define TCG_REG_TMP1 TCG_REG_R12
+#endif
+
+#define TCG_VEC_TMP1 TCG_REG_V0
+#define TCG_VEC_TMP2 TCG_REG_V1
+
+#define TCG_REG_TB TCG_REG_R31
+#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
+
+/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
+#define SZP ((int)sizeof(void *))
+
+/* Shorthand for size of a register. */
+#define SZR (TCG_TARGET_REG_BITS / 8)
+
+#define TCG_CT_CONST_S16 0x100
+#define TCG_CT_CONST_U16 0x200
+#define TCG_CT_CONST_S32 0x400
+#define TCG_CT_CONST_U32 0x800
+#define TCG_CT_CONST_ZERO 0x1000
+#define TCG_CT_CONST_MONE 0x2000
+#define TCG_CT_CONST_WSZ 0x4000
+
+static tcg_insn_unit *tb_ret_addr;
+
+TCGPowerISA have_isa;
+static bool have_isel;
+bool have_altivec;
+bool have_vsx;
+
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG 30
+#endif
+
+#ifdef CONFIG_DEBUG_TCG
+static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+ TCG_REG_R14, /* call saved registers */
+ TCG_REG_R15,
+ TCG_REG_R16,
+ TCG_REG_R17,
+ TCG_REG_R18,
+ TCG_REG_R19,
+ TCG_REG_R20,
+ TCG_REG_R21,
+ TCG_REG_R22,
+ TCG_REG_R23,
+ TCG_REG_R24,
+ TCG_REG_R25,
+ TCG_REG_R26,
+ TCG_REG_R27,
+ TCG_REG_R28,
+ TCG_REG_R29,
+ TCG_REG_R30,
+ TCG_REG_R31,
+ TCG_REG_R12, /* call clobbered, non-arguments */
+ TCG_REG_R11,
+ TCG_REG_R2,
+ TCG_REG_R13,
+ TCG_REG_R10, /* call clobbered, arguments */
+ TCG_REG_R9,
+ TCG_REG_R8,
+ TCG_REG_R7,
+ TCG_REG_R6,
+ TCG_REG_R5,
+ TCG_REG_R4,
+ TCG_REG_R3,
+
+ /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
+ TCG_REG_V2, /* call clobbered, vectors */
+ TCG_REG_V3,
+ TCG_REG_V4,
+ TCG_REG_V5,
+ TCG_REG_V6,
+ TCG_REG_V7,
+ TCG_REG_V8,
+ TCG_REG_V9,
+ TCG_REG_V10,
+ TCG_REG_V11,
+ TCG_REG_V12,
+ TCG_REG_V13,
+ TCG_REG_V14,
+ TCG_REG_V15,
+ TCG_REG_V16,
+ TCG_REG_V17,
+ TCG_REG_V18,
+ TCG_REG_V19,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_R3,
+ TCG_REG_R4,
+ TCG_REG_R5,
+ TCG_REG_R6,
+ TCG_REG_R7,
+ TCG_REG_R8,
+ TCG_REG_R9,
+ TCG_REG_R10
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_R3,
+ TCG_REG_R4
+};
+
+static const int tcg_target_callee_save_regs[] = {
+#ifdef TCG_TARGET_CALL_DARWIN
+ TCG_REG_R11,
+#endif
+ TCG_REG_R14,
+ TCG_REG_R15,
+ TCG_REG_R16,
+ TCG_REG_R17,
+ TCG_REG_R18,
+ TCG_REG_R19,
+ TCG_REG_R20,
+ TCG_REG_R21,
+ TCG_REG_R22,
+ TCG_REG_R23,
+ TCG_REG_R24,
+ TCG_REG_R25,
+ TCG_REG_R26,
+ TCG_REG_R27, /* currently used for the global env */
+ TCG_REG_R28,
+ TCG_REG_R29,
+ TCG_REG_R30,
+ TCG_REG_R31
+};
+
+static inline bool in_range_b(tcg_target_long target)
+{
+ return target == sextract64(target, 0, 26);
+}
+
+static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
+ tcg_debug_assert(in_range_b(disp));
+ return disp & 0x3fffffc;
+}
+
+static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
+ if (in_range_b(disp)) {
+ *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc);
+ return true;
+ }
+ return false;
+}
+
+static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
+ tcg_debug_assert(disp == (int16_t) disp);
+ return disp & 0xfffc;
+}
+
+static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
+ if (disp == (int16_t) disp) {
+ *pc = (*pc & ~0xfffc) | (disp & 0xfffc);
+ return true;
+ }
+ return false;
+}
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'A': case 'B': case 'C': case 'D':
+ ct->ct |= TCG_CT_REG;
+ tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
+ break;
+ case 'r':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ break;
+ case 'v':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff00000000ull;
+ break;
+ case 'L': /* qemu_ld constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+#ifdef CONFIG_SOFTMMU
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+#endif
+ break;
+ case 'S': /* qemu_st constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+#ifdef CONFIG_SOFTMMU
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
+#endif
+ break;
+ case 'I':
+ ct->ct |= TCG_CT_CONST_S16;
+ break;
+ case 'J':
+ ct->ct |= TCG_CT_CONST_U16;
+ break;
+ case 'M':
+ ct->ct |= TCG_CT_CONST_MONE;
+ break;
+ case 'T':
+ ct->ct |= TCG_CT_CONST_S32;
+ break;
+ case 'U':
+ ct->ct |= TCG_CT_CONST_U32;
+ break;
+ case 'W':
+ ct->ct |= TCG_CT_CONST_WSZ;
+ break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* test if a constant matches the constraint */
+static int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+
+ /* The only 32-bit constraint we use aside from
+ TCG_CT_CONST is TCG_CT_CONST_S16. */
+ if (type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_WSZ)
+ && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
+ return 1;
+ }
+ return 0;
+}
+
+#define OPCD(opc) ((opc)<<26)
+#define XO19(opc) (OPCD(19)|((opc)<<1))
+#define MD30(opc) (OPCD(30)|((opc)<<2))
+#define MDS30(opc) (OPCD(30)|((opc)<<1))
+#define XO31(opc) (OPCD(31)|((opc)<<1))
+#define XO58(opc) (OPCD(58)|(opc))
+#define XO62(opc) (OPCD(62)|(opc))
+#define VX4(opc) (OPCD(4)|(opc))
+
+#define B OPCD( 18)
+#define BC OPCD( 16)
+#define LBZ OPCD( 34)
+#define LHZ OPCD( 40)
+#define LHA OPCD( 42)
+#define LWZ OPCD( 32)
+#define LWZUX XO31( 55)
+#define STB OPCD( 38)
+#define STH OPCD( 44)
+#define STW OPCD( 36)
+
+#define STD XO62( 0)
+#define STDU XO62( 1)
+#define STDX XO31(149)
+
+#define LD XO58( 0)
+#define LDX XO31( 21)
+#define LDU XO58( 1)
+#define LDUX XO31( 53)
+#define LWA XO58( 2)
+#define LWAX XO31(341)
+
+#define ADDIC OPCD( 12)
+#define ADDI OPCD( 14)
+#define ADDIS OPCD( 15)
+#define ORI OPCD( 24)
+#define ORIS OPCD( 25)
+#define XORI OPCD( 26)
+#define XORIS OPCD( 27)
+#define ANDI OPCD( 28)
+#define ANDIS OPCD( 29)
+#define MULLI OPCD( 7)
+#define CMPLI OPCD( 10)
+#define CMPI OPCD( 11)
+#define SUBFIC OPCD( 8)
+
+#define LWZU OPCD( 33)
+#define STWU OPCD( 37)
+
+#define RLWIMI OPCD( 20)
+#define RLWINM OPCD( 21)
+#define RLWNM OPCD( 23)
+
+#define RLDICL MD30( 0)
+#define RLDICR MD30( 1)
+#define RLDIMI MD30( 3)
+#define RLDCL MDS30( 8)
+
+#define BCLR XO19( 16)
+#define BCCTR XO19(528)
+#define CRAND XO19(257)
+#define CRANDC XO19(129)
+#define CRNAND XO19(225)
+#define CROR XO19(449)
+#define CRNOR XO19( 33)
+
+#define EXTSB XO31(954)
+#define EXTSH XO31(922)
+#define EXTSW XO31(986)
+#define ADD XO31(266)
+#define ADDE XO31(138)
+#define ADDME XO31(234)
+#define ADDZE XO31(202)
+#define ADDC XO31( 10)
+#define AND XO31( 28)
+#define SUBF XO31( 40)
+#define SUBFC XO31( 8)
+#define SUBFE XO31(136)
+#define SUBFME XO31(232)
+#define SUBFZE XO31(200)
+#define OR XO31(444)
+#define XOR XO31(316)
+#define MULLW XO31(235)
+#define MULHW XO31( 75)
+#define MULHWU XO31( 11)
+#define DIVW XO31(491)
+#define DIVWU XO31(459)
+#define CMP XO31( 0)
+#define CMPL XO31( 32)
+#define LHBRX XO31(790)
+#define LWBRX XO31(534)
+#define LDBRX XO31(532)
+#define STHBRX XO31(918)
+#define STWBRX XO31(662)
+#define STDBRX XO31(660)
+#define MFSPR XO31(339)
+#define MTSPR XO31(467)
+#define SRAWI XO31(824)
+#define NEG XO31(104)
+#define MFCR XO31( 19)
+#define MFOCRF (MFCR | (1u << 20))
+#define NOR XO31(124)
+#define CNTLZW XO31( 26)
+#define CNTLZD XO31( 58)
+#define CNTTZW XO31(538)
+#define CNTTZD XO31(570)
+#define CNTPOPW XO31(378)
+#define CNTPOPD XO31(506)
+#define ANDC XO31( 60)
+#define ORC XO31(412)
+#define EQV XO31(284)
+#define NAND XO31(476)
+#define ISEL XO31( 15)
+
+#define MULLD XO31(233)
+#define MULHD XO31( 73)
+#define MULHDU XO31( 9)
+#define DIVD XO31(489)
+#define DIVDU XO31(457)
+
+#define LBZX XO31( 87)
+#define LHZX XO31(279)
+#define LHAX XO31(343)
+#define LWZX XO31( 23)
+#define STBX XO31(215)
+#define STHX XO31(407)
+#define STWX XO31(151)
+
+#define EIEIO XO31(854)
+#define HWSYNC XO31(598)
+#define LWSYNC (HWSYNC | (1u << 21))
+
+#define SPR(a, b) ((((a)<<5)|(b))<<11)
+#define LR SPR(8, 0)
+#define CTR SPR(9, 0)
+
+#define SLW XO31( 24)
+#define SRW XO31(536)
+#define SRAW XO31(792)
+
+#define SLD XO31( 27)
+#define SRD XO31(539)
+#define SRAD XO31(794)
+#define SRADI XO31(413<<1)
+
+#define TW XO31( 4)
+#define TRAP (TW | TO(31))
+
+#define NOP ORI /* ori 0,0,0 */
+
+#define LVX XO31(103)
+#define LVEBX XO31(7)
+#define LVEHX XO31(39)
+#define LVEWX XO31(71)
+#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
+#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
+#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
+#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
+#define LXSD (OPCD(57) | 2) /* v3.00 */
+#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
+
+#define STVX XO31(231)
+#define STVEWX XO31(199)
+#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
+#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
+#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
+#define STXSD (OPCD(61) | 2) /* v3.00 */
+
+#define VADDSBS VX4(768)
+#define VADDUBS VX4(512)
+#define VADDUBM VX4(0)
+#define VADDSHS VX4(832)
+#define VADDUHS VX4(576)
+#define VADDUHM VX4(64)
+#define VADDSWS VX4(896)
+#define VADDUWS VX4(640)
+#define VADDUWM VX4(128)
+#define VADDUDM VX4(192) /* v2.07 */
+
+#define VSUBSBS VX4(1792)
+#define VSUBUBS VX4(1536)
+#define VSUBUBM VX4(1024)
+#define VSUBSHS VX4(1856)
+#define VSUBUHS VX4(1600)
+#define VSUBUHM VX4(1088)
+#define VSUBSWS VX4(1920)
+#define VSUBUWS VX4(1664)
+#define VSUBUWM VX4(1152)
+#define VSUBUDM VX4(1216) /* v2.07 */
+
+#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
+#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
+
+#define VMAXSB VX4(258)
+#define VMAXSH VX4(322)
+#define VMAXSW VX4(386)
+#define VMAXSD VX4(450) /* v2.07 */
+#define VMAXUB VX4(2)
+#define VMAXUH VX4(66)
+#define VMAXUW VX4(130)
+#define VMAXUD VX4(194) /* v2.07 */
+#define VMINSB VX4(770)
+#define VMINSH VX4(834)
+#define VMINSW VX4(898)
+#define VMINSD VX4(962) /* v2.07 */
+#define VMINUB VX4(514)
+#define VMINUH VX4(578)
+#define VMINUW VX4(642)
+#define VMINUD VX4(706) /* v2.07 */
+
+#define VCMPEQUB VX4(6)
+#define VCMPEQUH VX4(70)
+#define VCMPEQUW VX4(134)
+#define VCMPEQUD VX4(199) /* v2.07 */
+#define VCMPGTSB VX4(774)
+#define VCMPGTSH VX4(838)
+#define VCMPGTSW VX4(902)
+#define VCMPGTSD VX4(967) /* v2.07 */
+#define VCMPGTUB VX4(518)
+#define VCMPGTUH VX4(582)
+#define VCMPGTUW VX4(646)
+#define VCMPGTUD VX4(711) /* v2.07 */
+#define VCMPNEB VX4(7) /* v3.00 */
+#define VCMPNEH VX4(71) /* v3.00 */
+#define VCMPNEW VX4(135) /* v3.00 */
+
+#define VSLB VX4(260)
+#define VSLH VX4(324)
+#define VSLW VX4(388)
+#define VSLD VX4(1476) /* v2.07 */
+#define VSRB VX4(516)
+#define VSRH VX4(580)
+#define VSRW VX4(644)
+#define VSRD VX4(1732) /* v2.07 */
+#define VSRAB VX4(772)
+#define VSRAH VX4(836)
+#define VSRAW VX4(900)
+#define VSRAD VX4(964) /* v2.07 */
+#define VRLB VX4(4)
+#define VRLH VX4(68)
+#define VRLW VX4(132)
+#define VRLD VX4(196) /* v2.07 */
+
+#define VMULEUB VX4(520)
+#define VMULEUH VX4(584)
+#define VMULEUW VX4(648) /* v2.07 */
+#define VMULOUB VX4(8)
+#define VMULOUH VX4(72)
+#define VMULOUW VX4(136) /* v2.07 */
+#define VMULUWM VX4(137) /* v2.07 */
+#define VMSUMUHM VX4(38)
+
+#define VMRGHB VX4(12)
+#define VMRGHH VX4(76)
+#define VMRGHW VX4(140)
+#define VMRGLB VX4(268)
+#define VMRGLH VX4(332)
+#define VMRGLW VX4(396)
+
+#define VPKUHUM VX4(14)
+#define VPKUWUM VX4(78)
+
+#define VAND VX4(1028)
+#define VANDC VX4(1092)
+#define VNOR VX4(1284)
+#define VOR VX4(1156)
+#define VXOR VX4(1220)
+#define VEQV VX4(1668) /* v2.07 */
+#define VNAND VX4(1412) /* v2.07 */
+#define VORC VX4(1348) /* v2.07 */
+
+#define VSPLTB VX4(524)
+#define VSPLTH VX4(588)
+#define VSPLTW VX4(652)
+#define VSPLTISB VX4(780)
+#define VSPLTISH VX4(844)
+#define VSPLTISW VX4(908)
+
+#define VSLDOI VX4(44)
+
+#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
+#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
+#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
+
+#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
+#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
+#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
+#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
+#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
+#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
+
+#define RT(r) ((r)<<21)
+#define RS(r) ((r)<<21)
+#define RA(r) ((r)<<16)
+#define RB(r) ((r)<<11)
+#define TO(t) ((t)<<21)
+#define SH(s) ((s)<<11)
+#define MB(b) ((b)<<6)
+#define ME(e) ((e)<<1)
+#define BO(o) ((o)<<21)
+#define MB64(b) ((b)<<5)
+#define FXM(b) (1 << (19 - (b)))
+
+#define VRT(r) (((r) & 31) << 21)
+#define VRA(r) (((r) & 31) << 16)
+#define VRB(r) (((r) & 31) << 11)
+#define VRC(r) (((r) & 31) << 6)
+
+#define LK 1
+
+#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
+#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
+#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
+#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
+
+#define BF(n) ((n)<<23)
+#define BI(n, c) (((c)+((n)*4))<<16)
+#define BT(n, c) (((c)+((n)*4))<<21)
+#define BA(n, c) (((c)+((n)*4))<<16)
+#define BB(n, c) (((c)+((n)*4))<<11)
+#define BC_(n, c) (((c)+((n)*4))<<6)
+
+#define BO_COND_TRUE BO(12)
+#define BO_COND_FALSE BO( 4)
+#define BO_ALWAYS BO(20)
+
+enum {
+ CR_LT,
+ CR_GT,
+ CR_EQ,
+ CR_SO
+};
+
+static const uint32_t tcg_to_bc[] = {
+ [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
+ [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
+ [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
+ [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
+ [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
+ [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
+ [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
+ [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
+ [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
+ [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
+};
+
+/* The low bit here is set if the RA and RB fields must be inverted. */
+static const uint32_t tcg_to_isel[] = {
+ [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
+ [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
+ [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
+ [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
+ [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
+ [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
+ [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
+ [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
+ [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
+ [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
+};
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ tcg_insn_unit *target;
+ int16_t lo;
+ int32_t hi;
+
+ value += addend;
+ target = (tcg_insn_unit *)value;
+
+ switch (type) {
+ case R_PPC_REL14:
+ return reloc_pc14(code_ptr, target);
+ case R_PPC_REL24:
+ return reloc_pc24(code_ptr, target);
+ case R_PPC_ADDR16:
+ /*
+ * We are (slightly) abusing this relocation type. In particular,
+ * assert that the low 2 bits are zero, and do not modify them.
+ * That way we can use this with LD et al that have opcode bits
+ * in the low 2 bits of the insn.
+ */
+ if ((value & 3) || value != (int16_t)value) {
+ return false;
+ }
+ *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
+ break;
+ case R_PPC_ADDR32:
+ /*
+ * We are abusing this relocation type. Again, this points to
+ * a pair of insns, lis + load. This is an absolute address
+ * relocation for PPC32 so the lis cannot be removed.
+ */
+ lo = value;
+ hi = value - lo;
+ if (hi + lo != value) {
+ return false;
+ }
+ code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
+ code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
+ TCGReg base, tcg_target_long offset);
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I64:
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ /* fallthru */
+ case TCG_TYPE_I32:
+ if (ret < TCG_REG_V0) {
+ if (arg < TCG_REG_V0) {
+ tcg_out32(s, OR | SAB(arg, ret, arg));
+ break;
+ } else if (have_isa_2_07) {
+ tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
+ | VRT(arg) | RA(ret));
+ break;
+ } else {
+ /* Altivec does not support vector->integer moves. */
+ return false;
+ }
+ } else if (arg < TCG_REG_V0) {
+ if (have_isa_2_07) {
+ tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
+ | VRT(ret) | RA(arg));
+ break;
+ } else {
+ /* Altivec does not support integer->vector moves. */
+ return false;
+ }
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
+ tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
+ int sh, int mb)
+{
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
+ mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
+ tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
+}
+
+static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
+ int sh, int mb, int me)
+{
+ tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
+}
+
+static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ tcg_out_rld(s, RLDICL, dst, src, 0, 32);
+}
+
+static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
+{
+ tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
+}
+
+static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
+{
+ tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
+}
+
+static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
+{
+ tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
+}
+
+static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
+{
+ tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
+}
+
+/* Emit a move into ret of arg, if it can be done in one insn. */
+static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
+{
+ if (arg == (int16_t)arg) {
+ tcg_out32(s, ADDI | TAI(ret, 0, arg));
+ return true;
+ }
+ if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
+ tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
+ return true;
+ }
+ return false;
+}
+
+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long arg, bool in_prologue)
+{
+ intptr_t tb_diff;
+ tcg_target_long tmp;
+ int shift;
+
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
+
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ arg = (int32_t)arg;
+ }
+
+ /* Load 16-bit immediates with one insn. */
+ if (tcg_out_movi_one(s, ret, arg)) {
+ return;
+ }
+
+ /* Load addresses within the TB with one insn. */
+ tb_diff = arg - (intptr_t)s->code_gen_ptr;
+ if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
+ tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
+ return;
+ }
+
+ /* Load 32-bit immediates with two insns. Note that we've already
+ eliminated bare ADDIS, so we know both insns are required. */
+ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
+ tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
+ tcg_out32(s, ORI | SAI(ret, ret, arg));
+ return;
+ }
+ if (arg == (uint32_t)arg && !(arg & 0x8000)) {
+ tcg_out32(s, ADDI | TAI(ret, 0, arg));
+ tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
+ return;
+ }
+
+ /* Load masked 16-bit value. */
+ if (arg > 0 && (arg & 0x8000)) {
+ tmp = arg | 0x7fff;
+ if ((tmp & (tmp + 1)) == 0) {
+ int mb = clz64(tmp + 1) + 1;
+ tcg_out32(s, ADDI | TAI(ret, 0, arg));
+ tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
+ return;
+ }
+ }
+
+ /* Load common masks with 2 insns. */
+ shift = ctz64(arg);
+ tmp = arg >> shift;
+ if (tmp == (int16_t)tmp) {
+ tcg_out32(s, ADDI | TAI(ret, 0, tmp));
+ tcg_out_shli64(s, ret, ret, shift);
+ return;
+ }
+ shift = clz64(arg);
+ if (tcg_out_movi_one(s, ret, arg << shift)) {
+ tcg_out_shri64(s, ret, ret, shift);
+ return;
+ }
+
+ /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
+ if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
+ tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
+ return;
+ }
+
+ /* Use the constant pool, if possible. */
+ if (!in_prologue && USE_REG_TB) {
+ new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
+ -(intptr_t)s->code_gen_ptr);
+ tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
+ return;
+ }
+
+ tmp = arg >> 31 >> 1;
+ tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
+ if (tmp) {
+ tcg_out_shli64(s, ret, ret, 32);
+ }
+ if (arg & 0xffff0000) {
+ tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
+ }
+ if (arg & 0xffff) {
+ tcg_out32(s, ORI | SAI(ret, ret, arg));
+ }
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long val)
+{
+ uint32_t load_insn;
+ int rel, low;
+ intptr_t add;
+
+ low = (int8_t)val;
+ if (low >= -16 && low < 16) {
+ if (val == (tcg_target_long)dup_const(MO_8, low)) {
+ tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
+ return;
+ }
+ if (val == (tcg_target_long)dup_const(MO_16, low)) {
+ tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
+ return;
+ }
+ if (val == (tcg_target_long)dup_const(MO_32, low)) {
+ tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
+ return;
+ }
+ }
+ if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) {
+ tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
+ return;
+ }
+
+ /*
+ * Otherwise we must load the value from the constant pool.
+ */
+ if (USE_REG_TB) {
+ rel = R_PPC_ADDR16;
+ add = -(intptr_t)s->code_gen_ptr;
+ } else {
+ rel = R_PPC_ADDR32;
+ add = 0;
+ }
+
+ if (have_vsx) {
+ load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
+ load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_label(s, val, rel, s->code_ptr, add);
+ } else {
+ new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ }
+ } else {
+ load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ } else {
+ new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+ }
+ }
+
+ if (USE_REG_TB) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
+ load_insn |= RA(TCG_REG_TB);
+ } else {
+ tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
+ }
+ tcg_out32(s, load_insn);
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long arg)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_debug_assert(ret < TCG_REG_V0);
+ tcg_out_movi_int(s, type, ret, arg, false);
+ break;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= TCG_REG_V0);
+ tcg_out_dupi_vec(s, type, ret, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static bool mask_operand(uint32_t c, int *mb, int *me)
+{
+ uint32_t lsb, test;
+
+ /* Accept a bit pattern like:
+ 0....01....1
+ 1....10....0
+ 0..01..10..0
+ Keep track of the transitions. */
+ if (c == 0 || c == -1) {
+ return false;
+ }
+ test = c;
+ lsb = test & -test;
+ test += lsb;
+ if (test & (test - 1)) {
+ return false;
+ }
+
+ *me = clz32(lsb);
+ *mb = test ? clz32(test & -test) + 1 : 0;
+ return true;
+}
+
+static bool mask64_operand(uint64_t c, int *mb, int *me)
+{
+ uint64_t lsb;
+
+ if (c == 0) {
+ return false;
+ }
+
+ lsb = c & -c;
+ /* Accept 1..10..0. */
+ if (c == -lsb) {
+ *mb = 0;
+ *me = clz64(lsb);
+ return true;
+ }
+ /* Accept 0..01..1. */
+ if (lsb == 1 && (c & (c + 1)) == 0) {
+ *mb = clz64(c + 1) + 1;
+ *me = 63;
+ return true;
+ }
+ return false;
+}
+
+static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
+{
+ int mb, me;
+
+ if (mask_operand(c, &mb, &me)) {
+ tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
+ } else if ((c & 0xffff) == c) {
+ tcg_out32(s, ANDI | SAI(src, dst, c));
+ return;
+ } else if ((c & 0xffff0000) == c) {
+ tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
+ return;
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
+ tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
+ }
+}
+
+static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
+{
+ int mb, me;
+
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ if (mask64_operand(c, &mb, &me)) {
+ if (mb == 0) {
+ tcg_out_rld(s, RLDICR, dst, src, 0, me);
+ } else {
+ tcg_out_rld(s, RLDICL, dst, src, 0, mb);
+ }
+ } else if ((c & 0xffff) == c) {
+ tcg_out32(s, ANDI | SAI(src, dst, c));
+ return;
+ } else if ((c & 0xffff0000) == c) {
+ tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
+ return;
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
+ tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
+ }
+}
+
+static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
+ int op_lo, int op_hi)
+{
+ if (c >> 16) {
+ tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
+ src = dst;
+ }
+ if (c & 0xffff) {
+ tcg_out32(s, op_lo | SAI(src, dst, c));
+ src = dst;
+ }
+}
+
+static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
+{
+ tcg_out_zori32(s, dst, src, c, ORI, ORIS);
+}
+
+static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
+{
+ tcg_out_zori32(s, dst, src, c, XORI, XORIS);
+}
+
+static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
+{
+ ptrdiff_t disp = tcg_pcrel_diff(s, target);
+ if (in_range_b(disp)) {
+ tcg_out32(s, B | (disp & 0x3fffffc) | mask);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
+ tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
+ tcg_out32(s, BCCTR | BO_ALWAYS | mask);
+ }
+}
+
+static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
+ TCGReg base, tcg_target_long offset)
+{
+ tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
+ bool is_int_store = false;
+ TCGReg rs = TCG_REG_TMP1;
+
+ switch (opi) {
+ case LD: case LWA:
+ align = 3;
+ /* FALLTHRU */
+ default:
+ if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
+ rs = rt;
+ break;
+ }
+ break;
+ case LXSD:
+ case STXSD:
+ align = 3;
+ break;
+ case LXV:
+ case STXV:
+ align = 15;
+ break;
+ case STD:
+ align = 3;
+ /* FALLTHRU */
+ case STB: case STH: case STW:
+ is_int_store = true;
+ break;
+ }
+
+ /* For unaligned, or very large offsets, use the indexed form. */
+ if (offset & align || offset != (int32_t)offset || opi == 0) {
+ if (rs == base) {
+ rs = TCG_REG_R0;
+ }
+ tcg_debug_assert(!is_int_store || rs != rt);
+ tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
+ tcg_out32(s, opx | TAB(rt & 31, base, rs));
+ return;
+ }
+
+ l0 = (int16_t)offset;
+ offset = (offset - l0) >> 16;
+ l1 = (int16_t)offset;
+
+ if (l1 < 0 && orig >= 0) {
+ extra = 0x4000;
+ l1 = (int16_t)(offset - 0x4000);
+ }
+ if (l1) {
+ tcg_out32(s, ADDIS | TAI(rs, base, l1));
+ base = rs;
+ }
+ if (extra) {
+ tcg_out32(s, ADDIS | TAI(rs, base, extra));
+ base = rs;
+ }
+ if (opi != ADDI || base != rt || l0 != 0) {
+ tcg_out32(s, opi | TAI(rt & 31, base, l0));
+ }
+}
+
+static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
+ TCGReg va, TCGReg vb, int shb)
+{
+ tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg base, intptr_t offset)
+{
+ int shift;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < TCG_REG_V0) {
+ tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
+ break;
+ }
+ if (have_isa_2_07 && have_vsx) {
+ tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
+ break;
+ }
+ tcg_debug_assert((offset & 3) == 0);
+ tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
+ shift = (offset - 4) & 0xc;
+ if (shift) {
+ tcg_out_vsldoi(s, ret, ret, ret, shift);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (ret < TCG_REG_V0) {
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ tcg_out_mem_long(s, LD, LDX, ret, base, offset);
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= TCG_REG_V0);
+ if (have_vsx) {
+ tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
+ ret, base, offset);
+ break;
+ }
+ tcg_debug_assert((offset & 7) == 0);
+ tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
+ if (offset & 8) {
+ tcg_out_vsldoi(s, ret, ret, ret, 8);
+ }
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= TCG_REG_V0);
+ tcg_debug_assert((offset & 15) == 0);
+ tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
+ LVX, ret, base, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg base, intptr_t offset)
+{
+ int shift;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (arg < TCG_REG_V0) {
+ tcg_out_mem_long(s, STW, STWX, arg, base, offset);
+ break;
+ }
+ if (have_isa_2_07 && have_vsx) {
+ tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
+ break;
+ }
+ assert((offset & 3) == 0);
+ tcg_debug_assert((offset & 3) == 0);
+ shift = (offset - 4) & 0xc;
+ if (shift) {
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
+ arg = TCG_VEC_TMP1;
+ }
+ tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
+ break;
+ case TCG_TYPE_I64:
+ if (arg < TCG_REG_V0) {
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ tcg_out_mem_long(s, STD, STDX, arg, base, offset);
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(arg >= TCG_REG_V0);
+ if (have_vsx) {
+ tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
+ STXSDX, arg, base, offset);
+ break;
+ }
+ tcg_debug_assert((offset & 7) == 0);
+ if (offset & 8) {
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
+ arg = TCG_VEC_TMP1;
+ }
+ tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
+ tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(arg >= TCG_REG_V0);
+ tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
+ STVX, arg, base, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ return false;
+}
+
+static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
+ int const_arg2, int cr, TCGType type)
+{
+ int imm;
+ uint32_t op;
+
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
+
+ /* Simplify the comparisons below wrt CMPI. */
+ if (type == TCG_TYPE_I32) {
+ arg2 = (int32_t)arg2;
+ }
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ if (const_arg2) {
+ if ((int16_t) arg2 == arg2) {
+ op = CMPI;
+ imm = 1;
+ break;
+ } else if ((uint16_t) arg2 == arg2) {
+ op = CMPLI;
+ imm = 1;
+ break;
+ }
+ }
+ op = CMPL;
+ imm = 0;
+ break;
+
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ case TCG_COND_LE:
+ case TCG_COND_GT:
+ if (const_arg2) {
+ if ((int16_t) arg2 == arg2) {
+ op = CMPI;
+ imm = 1;
+ break;
+ }
+ }
+ op = CMP;
+ imm = 0;
+ break;
+
+ case TCG_COND_LTU:
+ case TCG_COND_GEU:
+ case TCG_COND_LEU:
+ case TCG_COND_GTU:
+ if (const_arg2) {
+ if ((uint16_t) arg2 == arg2) {
+ op = CMPLI;
+ imm = 1;
+ break;
+ }
+ }
+ op = CMPL;
+ imm = 0;
+ break;
+
+ default:
+ tcg_abort();
+ }
+ op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
+
+ if (imm) {
+ tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
+ } else {
+ if (const_arg2) {
+ tcg_out_movi(s, type, TCG_REG_R0, arg2);
+ arg2 = TCG_REG_R0;
+ }
+ tcg_out32(s, op | RA(arg1) | RB(arg2));
+ }
+}
+
+static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
+ TCGReg dst, TCGReg src)
+{
+ if (type == TCG_TYPE_I32) {
+ tcg_out32(s, CNTLZW | RS(src) | RA(dst));
+ tcg_out_shri32(s, dst, dst, 5);
+ } else {
+ tcg_out32(s, CNTLZD | RS(src) | RA(dst));
+ tcg_out_shri64(s, dst, dst, 6);
+ }
+}
+
+static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ /* X != 0 implies X + -1 generates a carry. Extra addition
+ trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
+ if (dst != src) {
+ tcg_out32(s, ADDIC | TAI(dst, src, -1));
+ tcg_out32(s, SUBFE | TAB(dst, dst, src));
+ } else {
+ tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
+ tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
+ }
+}
+
+static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
+ bool const_arg2)
+{
+ if (const_arg2) {
+ if ((uint32_t)arg2 == arg2) {
+ tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
+ tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
+ }
+ } else {
+ tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
+ }
+ return TCG_REG_R0;
+}
+
+static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
+ TCGArg arg0, TCGArg arg1, TCGArg arg2,
+ int const_arg2)
+{
+ int crop, sh;
+
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
+
+ /* Ignore high bits of a potential constant arg2. */
+ if (type == TCG_TYPE_I32) {
+ arg2 = (uint32_t)arg2;
+ }
+
+ /* Handle common and trivial cases before handling anything else. */
+ if (arg2 == 0) {
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_out_setcond_eq0(s, type, arg0, arg1);
+ return;
+ case TCG_COND_NE:
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ tcg_out_ext32u(s, TCG_REG_R0, arg1);
+ arg1 = TCG_REG_R0;
+ }
+ tcg_out_setcond_ne0(s, arg0, arg1);
+ return;
+ case TCG_COND_GE:
+ tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
+ arg1 = arg0;
+ /* FALLTHRU */
+ case TCG_COND_LT:
+ /* Extract the sign bit. */
+ if (type == TCG_TYPE_I32) {
+ tcg_out_shri32(s, arg0, arg1, 31);
+ } else {
+ tcg_out_shri64(s, arg0, arg1, 63);
+ }
+ return;
+ default:
+ break;
+ }
+ }
+
+ /* If we have ISEL, we can implement everything with 3 or 4 insns.
+ All other cases below are also at least 3 insns, so speed up the
+ code generator by not considering them and always using ISEL. */
+ if (have_isel) {
+ int isel, tab;
+
+ tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+
+ isel = tcg_to_isel[cond];
+
+ tcg_out_movi(s, type, arg0, 1);
+ if (isel & 1) {
+ /* arg0 = (bc ? 0 : 1) */
+ tab = TAB(arg0, 0, arg0);
+ isel &= ~1;
+ } else {
+ /* arg0 = (bc ? 1 : 0) */
+ tcg_out_movi(s, type, TCG_REG_R0, 0);
+ tab = TAB(arg0, arg0, TCG_REG_R0);
+ }
+ tcg_out32(s, isel | tab);
+ return;
+ }
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
+ tcg_out_setcond_eq0(s, type, arg0, arg1);
+ return;
+
+ case TCG_COND_NE:
+ arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
+ /* Discard the high bits only once, rather than both inputs. */
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ tcg_out_ext32u(s, TCG_REG_R0, arg1);
+ arg1 = TCG_REG_R0;
+ }
+ tcg_out_setcond_ne0(s, arg0, arg1);
+ return;
+
+ case TCG_COND_GT:
+ case TCG_COND_GTU:
+ sh = 30;
+ crop = 0;
+ goto crtest;
+
+ case TCG_COND_LT:
+ case TCG_COND_LTU:
+ sh = 29;
+ crop = 0;
+ goto crtest;
+
+ case TCG_COND_GE:
+ case TCG_COND_GEU:
+ sh = 31;
+ crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
+ goto crtest;
+
+ case TCG_COND_LE:
+ case TCG_COND_LEU:
+ sh = 31;
+ crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
+ crtest:
+ tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+ if (crop) {
+ tcg_out32(s, crop);
+ }
+ tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
+ tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
+{
+ if (l->has_value) {
+ bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr);
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
+ }
+ tcg_out32(s, bc);
+}
+
+static void tcg_out_brcond(TCGContext *s, TCGCond cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ TCGLabel *l, TCGType type)
+{
+ tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+ tcg_out_bc(s, tcg_to_bc[cond], l);
+}
+
+static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
+ TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
+ TCGArg v2, bool const_c2)
+{
+ /* If for some reason both inputs are zero, don't produce bad code. */
+ if (v1 == 0 && v2 == 0) {
+ tcg_out_movi(s, type, dest, 0);
+ return;
+ }
+
+ tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
+
+ if (have_isel) {
+ int isel = tcg_to_isel[cond];
+
+ /* Swap the V operands if the operation indicates inversion. */
+ if (isel & 1) {
+ int t = v1;
+ v1 = v2;
+ v2 = t;
+ isel &= ~1;
+ }
+ /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
+ if (v2 == 0) {
+ tcg_out_movi(s, type, TCG_REG_R0, 0);
+ }
+ tcg_out32(s, isel | TAB(dest, v1, v2));
+ } else {
+ if (dest == v2) {
+ cond = tcg_invert_cond(cond);
+ v2 = v1;
+ } else if (dest != v1) {
+ if (v1 == 0) {
+ tcg_out_movi(s, type, dest, 0);
+ } else {
+ tcg_out_mov(s, type, dest, v1);
+ }
+ }
+ /* Branch forward over one insn */
+ tcg_out32(s, tcg_to_bc[cond] | 8);
+ if (v2 == 0) {
+ tcg_out_movi(s, type, dest, 0);
+ } else {
+ tcg_out_mov(s, type, dest, v2);
+ }
+ }
+}
+
+static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
+ TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
+{
+ if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
+ tcg_out32(s, opc | RA(a0) | RS(a1));
+ } else {
+ tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
+ /* Note that the only other valid constant for a2 is 0. */
+ if (have_isel) {
+ tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
+ tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
+ } else if (!const_a2 && a0 == a2) {
+ tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
+ tcg_out32(s, opc | RA(a0) | RS(a1));
+ } else {
+ tcg_out32(s, opc | RA(a0) | RS(a1));
+ tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
+ if (const_a2) {
+ tcg_out_movi(s, type, a0, 0);
+ } else {
+ tcg_out_mov(s, type, a0, a2);
+ }
+ }
+ }
+}
+
+static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ static const struct { uint8_t bit1, bit2; } bits[] = {
+ [TCG_COND_LT ] = { CR_LT, CR_LT },
+ [TCG_COND_LE ] = { CR_LT, CR_GT },
+ [TCG_COND_GT ] = { CR_GT, CR_GT },
+ [TCG_COND_GE ] = { CR_GT, CR_LT },
+ [TCG_COND_LTU] = { CR_LT, CR_LT },
+ [TCG_COND_LEU] = { CR_LT, CR_GT },
+ [TCG_COND_GTU] = { CR_GT, CR_GT },
+ [TCG_COND_GEU] = { CR_GT, CR_LT },
+ };
+
+ TCGCond cond = args[4], cond2;
+ TCGArg al, ah, bl, bh;
+ int blconst, bhconst;
+ int op, bit1, bit2;
+
+ al = args[0];
+ ah = args[1];
+ bl = args[2];
+ bh = args[3];
+ blconst = const_args[2];
+ bhconst = const_args[3];
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ op = CRAND;
+ goto do_equality;
+ case TCG_COND_NE:
+ op = CRNAND;
+ do_equality:
+ tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
+ tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
+ tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
+ break;
+
+ case TCG_COND_LT:
+ case TCG_COND_LE:
+ case TCG_COND_GT:
+ case TCG_COND_GE:
+ case TCG_COND_LTU:
+ case TCG_COND_LEU:
+ case TCG_COND_GTU:
+ case TCG_COND_GEU:
+ bit1 = bits[cond].bit1;
+ bit2 = bits[cond].bit2;
+ op = (bit1 != bit2 ? CRANDC : CRAND);
+ cond2 = tcg_unsigned_cond(cond);
+
+ tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
+ tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
+ tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
+ tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ tcg_out_cmp2(s, args + 1, const_args + 1);
+ tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
+ tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
+}
+
+static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
+ const int *const_args)
+{
+ tcg_out_cmp2(s, args, const_args);
+ tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
+}
+
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ uint32_t insn = HWSYNC;
+ a0 &= TCG_MO_ALL;
+ if (a0 == TCG_MO_LD_LD) {
+ insn = LWSYNC;
+ } else if (a0 == TCG_MO_ST_ST) {
+ insn = EIEIO;
+ }
+ tcg_out32(s, insn);
+}
+
+void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
+ uintptr_t addr)
+{
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_insn_unit i1, i2;
+ intptr_t tb_diff = addr - tc_ptr;
+ intptr_t br_diff = addr - (jmp_addr + 4);
+ uint64_t pair;
+
+ /* This does not exercise the range of the branch, but we do
+ still need to be able to load the new value of TCG_REG_TB.
+ But this does still happen quite often. */
+ if (tb_diff == (int16_t)tb_diff) {
+ i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
+ i2 = B | (br_diff & 0x3fffffc);
+ } else {
+ intptr_t lo = (int16_t)tb_diff;
+ intptr_t hi = (int32_t)(tb_diff - lo);
+ assert(tb_diff == hi + lo);
+ i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
+ i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
+ }
+#ifdef HOST_WORDS_BIGENDIAN
+ pair = (uint64_t)i1 << 32 | i2;
+#else
+ pair = (uint64_t)i2 << 32 | i1;
+#endif
+
+ /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
+ within atomic_set that would fail to build a ppc32 host. */
+ atomic_set__nocheck((uint64_t *)jmp_addr, pair);
+ flush_icache_range(jmp_addr, jmp_addr + 8);
+ } else {
+ intptr_t diff = addr - jmp_addr;
+ tcg_debug_assert(in_range_b(diff));
+ atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
+ flush_icache_range(jmp_addr, jmp_addr + 4);
+ }
+}
+
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
+{
+#ifdef _CALL_AIX
+ /* Look through the descriptor. If the branch is in range, and we
+ don't have to spend too much effort on building the toc. */
+ void *tgt = ((void **)target)[0];
+ uintptr_t toc = ((uintptr_t *)target)[1];
+ intptr_t diff = tcg_pcrel_diff(s, tgt);
+
+ if (in_range_b(diff) && toc == (uint32_t)toc) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
+ tcg_out_b(s, LK, tgt);
+ } else {
+ /* Fold the low bits of the constant into the addresses below. */
+ intptr_t arg = (intptr_t)target;
+ int ofs = (int16_t)arg;
+
+ if (ofs + 8 < 0x8000) {
+ arg -= ofs;
+ } else {
+ ofs = 0;
+ }
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
+ tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
+ tcg_out32(s, BCCTR | BO_ALWAYS | LK);
+ }
+#elif defined(_CALL_ELF) && _CALL_ELF == 2
+ intptr_t diff;
+
+ /* In the ELFv2 ABI, we have to set up r12 to contain the destination
+ address, which the callee uses to compute its TOC address. */
+ /* FIXME: when the branch is in range, we could avoid r12 load if we
+ knew that the destination uses the same TOC, and what its local
+ entry point offset is. */
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
+
+ diff = tcg_pcrel_diff(s, target);
+ if (in_range_b(diff)) {
+ tcg_out_b(s, LK, target);
+ } else {
+ tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
+ tcg_out32(s, BCCTR | BO_ALWAYS | LK);
+ }
+#else
+ tcg_out_b(s, LK, target);
+#endif
+}
+
+static const uint32_t qemu_ldx_opc[16] = {
+ [MO_UB] = LBZX,
+ [MO_UW] = LHZX,
+ [MO_UL] = LWZX,
+ [MO_Q] = LDX,
+ [MO_SW] = LHAX,
+ [MO_SL] = LWAX,
+ [MO_BSWAP | MO_UB] = LBZX,
+ [MO_BSWAP | MO_UW] = LHBRX,
+ [MO_BSWAP | MO_UL] = LWBRX,
+ [MO_BSWAP | MO_Q] = LDBRX,
+};
+
+static const uint32_t qemu_stx_opc[16] = {
+ [MO_UB] = STBX,
+ [MO_UW] = STHX,
+ [MO_UL] = STWX,
+ [MO_Q] = STDX,
+ [MO_BSWAP | MO_UB] = STBX,
+ [MO_BSWAP | MO_UW] = STHBRX,
+ [MO_BSWAP | MO_UL] = STWBRX,
+ [MO_BSWAP | MO_Q] = STDBRX,
+};
+
+static const uint32_t qemu_exts_opc[4] = {
+ EXTSB, EXTSH, EXTSW, 0
+};
+
+#if defined (CONFIG_SOFTMMU)
+#include "../tcg-ldst.c.inc"
+
+/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
+ * int mmu_idx, uintptr_t ra)
+ */
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+};
+
+/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, int mmu_idx, uintptr_t ra)
+ */
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+
+/* We expect to use a 16-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
+
+/* Perform the TLB load and compare. Places the result of the comparison
+ in CR7, loads the addend of the TLB into R3, and returns the register
+ containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
+
+static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
+ TCGReg addrlo, TCGReg addrhi,
+ int mem_index, bool is_read)
+{
+ int cmp_off
+ = (is_read
+ ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+
+ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
+
+ /* Extract the page index, shifted into place for tlb index. */
+ if (TCG_TARGET_REG_BITS == 32) {
+ tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ } else {
+ tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ }
+ tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
+
+ /* Load the TLB comparator. */
+ if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
+ uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
+ ? LWZUX : LDUX);
+ tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
+ } else {
+ tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
+ } else {
+ tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
+ }
+ }
+
+ /* Load the TLB addend for use on the fast path. Do this asap
+ to minimize any load use delay. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
+ offsetof(CPUTLBEntry, addend));
+
+ /* Clear the non-page, non-alignment bits from the address */
+ if (TCG_TARGET_REG_BITS == 32) {
+ /* We don't support unaligned accesses on 32-bits.
+ * Preserve the bottom bits and thus trigger a comparison
+ * failure on unaligned accesses.
+ */
+ if (a_bits < s_bits) {
+ a_bits = s_bits;
+ }
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
+ (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
+ } else {
+ TCGReg t = addrlo;
+
+ /* If the access is unaligned, we need to make sure we fail if we
+ * cross a page boundary. The trick is to add the access size-1
+ * to the address before masking the low bits. That will make the
+ * address overflow to the next page if we cross a page boundary,
+ * which will then force a mismatch of the TLB compare.
+ */
+ if (a_bits < s_bits) {
+ unsigned a_mask = (1 << a_bits) - 1;
+ unsigned s_mask = (1 << s_bits) - 1;
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
+ t = TCG_REG_R0;
+ }
+
+ /* Mask the address for the requested alignment. */
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
+ (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
+ /* Zero-extend the address for use in the final address. */
+ tcg_out_ext32u(s, TCG_REG_R4, addrlo);
+ addrlo = TCG_REG_R4;
+ } else if (a_bits == 0) {
+ tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
+ } else {
+ tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
+ 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
+ tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
+ }
+ }
+
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
+ 0, 7, TCG_TYPE_I32);
+ tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
+ tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
+ } else {
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
+ 0, 7, TCG_TYPE_TL);
+ }
+
+ return addrlo;
+}
+
+/* Record the context of a call to the out of line helper code for the slow
+ path for a load or store, so that we can later generate the correct
+ helper code. */
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+ TCGReg datalo_reg, TCGReg datahi_reg,
+ TCGReg addrlo_reg, TCGReg addrhi_reg,
+ tcg_insn_unit *raddr, tcg_insn_unit *lptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->datalo_reg = datalo_reg;
+ label->datahi_reg = datahi_reg;
+ label->addrlo_reg = addrlo_reg;
+ label->addrhi_reg = addrhi_reg;
+ label->raddr = raddr;
+ label->label_ptr[0] = lptr;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+ TCGReg hi, lo, arg = TCG_REG_R3;
+
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
+
+ lo = lb->addrlo_reg;
+ hi = lb->addrhi_reg;
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+ arg |= 1;
+#endif
+ tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
+ tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
+ } else {
+ /* If the address needed to be zero-extended, we'll have already
+ placed it in R4. The only remaining case is 64-bit guest. */
+ tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
+ }
+
+ tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
+ tcg_out32(s, MFSPR | RT(arg) | LR);
+
+ tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+
+ lo = lb->datalo_reg;
+ hi = lb->datahi_reg;
+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
+ tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
+ tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
+ } else if (opc & MO_SIGN) {
+ uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
+ tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
+ } else {
+ tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
+ }
+
+ tcg_out_b(s, 0, lb->raddr);
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
+ TCGReg hi, lo, arg = TCG_REG_R3;
+
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
+
+ lo = lb->addrlo_reg;
+ hi = lb->addrhi_reg;
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+ arg |= 1;
+#endif
+ tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
+ tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
+ } else {
+ /* If the address needed to be zero-extended, we'll have already
+ placed it in R4. The only remaining case is 64-bit guest. */
+ tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
+ }
+
+ lo = lb->datalo_reg;
+ hi = lb->datahi_reg;
+ if (TCG_TARGET_REG_BITS == 32) {
+ switch (s_bits) {
+ case MO_64:
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+ arg |= 1;
+#endif
+ tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
+ /* FALLTHRU */
+ case MO_32:
+ tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
+ break;
+ default:
+ tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
+ break;
+ }
+ } else {
+ if (s_bits == MO_64) {
+ tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
+ } else {
+ tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
+ }
+ }
+
+ tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
+ tcg_out32(s, MFSPR | RT(arg) | LR);
+
+ tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+
+ tcg_out_b(s, 0, lb->raddr);
+ return true;
+}
+#endif /* SOFTMMU */
+
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
+{
+ TCGReg datalo, datahi, addrlo, rbase;
+ TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
+ MemOp opc, s_bits;
+#ifdef CONFIG_SOFTMMU
+ int mem_index;
+ tcg_insn_unit *label_ptr;
+#endif
+
+ datalo = *args++;
+ datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+ addrlo = *args++;
+ addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+ s_bits = opc & MO_SIZE;
+
+#ifdef CONFIG_SOFTMMU
+ mem_index = get_mmuidx(oi);
+ addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
+
+ /* Load a pointer into the current opcode w/conditional branch-link. */
+ label_ptr = s->code_ptr;
+ tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
+
+ rbase = TCG_REG_R3;
+#else /* !CONFIG_SOFTMMU */
+ rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
+ addrlo = TCG_REG_TMP1;
+ }
+#endif
+
+ if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
+ if (opc & MO_BSWAP) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
+ } else if (rbase != 0) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
+ tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
+ tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
+ } else if (addrlo == datahi) {
+ tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
+ tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
+ } else {
+ tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
+ tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
+ }
+ } else {
+ uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
+ if (!have_isa_2_06 && insn == LDBRX) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
+ tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
+ tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
+ } else if (insn) {
+ tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
+ } else {
+ insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
+ tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
+ insn = qemu_exts_opc[s_bits];
+ tcg_out32(s, insn | RA(datalo) | RS(datalo));
+ }
+ }
+
+#ifdef CONFIG_SOFTMMU
+ add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
+ s->code_ptr, label_ptr);
+#endif
+}
+
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
+{
+ TCGReg datalo, datahi, addrlo, rbase;
+ TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
+ MemOp opc, s_bits;
+#ifdef CONFIG_SOFTMMU
+ int mem_index;
+ tcg_insn_unit *label_ptr;
+#endif
+
+ datalo = *args++;
+ datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+ addrlo = *args++;
+ addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+ s_bits = opc & MO_SIZE;
+
+#ifdef CONFIG_SOFTMMU
+ mem_index = get_mmuidx(oi);
+ addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
+
+ /* Load a pointer into the current opcode w/conditional branch-link. */
+ label_ptr = s->code_ptr;
+ tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
+
+ rbase = TCG_REG_R3;
+#else /* !CONFIG_SOFTMMU */
+ rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
+ addrlo = TCG_REG_TMP1;
+ }
+#endif
+
+ if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
+ if (opc & MO_BSWAP) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
+ tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
+ tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
+ } else if (rbase != 0) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
+ tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
+ tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
+ } else {
+ tcg_out32(s, STW | TAI(datahi, addrlo, 0));
+ tcg_out32(s, STW | TAI(datalo, addrlo, 4));
+ }
+ } else {
+ uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
+ if (!have_isa_2_06 && insn == STDBRX) {
+ tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
+ tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
+ tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
+ } else {
+ tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
+ }
+ }
+
+#ifdef CONFIG_SOFTMMU
+ add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
+ s->code_ptr, label_ptr);
+#endif
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = NOP;
+ }
+}
+
+/* Parameters for function call generation, used in tcg.c. */
+#define TCG_TARGET_STACK_ALIGN 16
+#define TCG_TARGET_EXTEND_ARGS 1
+
+#ifdef _CALL_AIX
+# define LINK_AREA_SIZE (6 * SZR)
+# define LR_OFFSET (1 * SZR)
+# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
+#elif defined(TCG_TARGET_CALL_DARWIN)
+# define LINK_AREA_SIZE (6 * SZR)
+# define LR_OFFSET (2 * SZR)
+#elif TCG_TARGET_REG_BITS == 64
+# if defined(_CALL_ELF) && _CALL_ELF == 2
+# define LINK_AREA_SIZE (4 * SZR)
+# define LR_OFFSET (1 * SZR)
+# endif
+#else /* TCG_TARGET_REG_BITS == 32 */
+# if defined(_CALL_SYSV)
+# define LINK_AREA_SIZE (2 * SZR)
+# define LR_OFFSET (1 * SZR)
+# endif
+#endif
+#ifndef LR_OFFSET
+# error "Unhandled abi"
+#endif
+#ifndef TCG_TARGET_CALL_STACK_OFFSET
+# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
+#endif
+
+#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
+#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
+
+#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_SIZE \
+ + REG_SAVE_SIZE \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & -TCG_TARGET_STACK_ALIGN)
+
+#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
+
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ int i;
+
+#ifdef _CALL_AIX
+ void **desc = (void **)s->code_ptr;
+ desc[0] = desc + 2; /* entry point */
+ desc[1] = 0; /* environment pointer */
+ s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
+#endif
+
+ tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
+ CPU_TEMP_BUF_SIZE);
+
+ /* Prologue */
+ tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
+ tcg_out32(s, (SZR == 8 ? STDU : STWU)
+ | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
+
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
+ tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_R1, REG_SAVE_BOT + i * SZR);
+ }
+ tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
+
+#ifndef CONFIG_SOFTMMU
+ if (guest_base) {
+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+ tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
+ if (USE_REG_TB) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
+ }
+ tcg_out32(s, BCCTR | BO_ALWAYS);
+
+ /* Epilogue */
+ s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
+
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
+ tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_R1, REG_SAVE_BOT + i * SZR);
+ }
+ tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
+ tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
+ tcg_out32(s, BCLR | BO_ALWAYS);
+}
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
+ const int *const_args)
+{
+ TCGArg a0, a1, a2;
+ int c;
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
+ tcg_out_b(s, 0, tb_ret_addr);
+ break;
+ case INDEX_op_goto_tb:
+ if (s->tb_jmp_insn_offset) {
+ /* Direct jump. */
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* Ensure the next insns are 8-byte aligned. */
+ if ((uintptr_t)s->code_ptr & 7) {
+ tcg_out32(s, NOP);
+ }
+ s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
+ tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
+ } else {
+ s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
+ tcg_out32(s, B);
+ s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
+ break;
+ }
+ } else {
+ /* Indirect jump. */
+ tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
+ (intptr_t)(s->tb_jmp_insn_offset + args[0]));
+ }
+ tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
+ tcg_out32(s, BCCTR | BO_ALWAYS);
+ set_jmp_reset_offset(s, args[0]);
+ if (USE_REG_TB) {
+ /* For the unlinked case, need to reset TCG_REG_TB. */
+ c = -tcg_current_code_size(s);
+ assert(c == (int16_t)c);
+ tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
+ }
+ break;
+ case INDEX_op_goto_ptr:
+ tcg_out32(s, MTSPR | RS(args[0]) | CTR);
+ if (USE_REG_TB) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
+ }
+ tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
+ tcg_out32(s, BCCTR | BO_ALWAYS);
+ break;
+ case INDEX_op_br:
+ {
+ TCGLabel *l = arg_label(args[0]);
+ uint32_t insn = B;
+
+ if (l->has_value) {
+ insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr);
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
+ }
+ tcg_out32(s, insn);
+ }
+ break;
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
+ tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
+ break;
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32u_i64:
+ tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld32s_i64:
+ tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_add_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ do_addi_32:
+ tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
+ } else {
+ tcg_out32(s, ADD | TAB(a0, a1, a2));
+ }
+ break;
+ case INDEX_op_sub_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[1]) {
+ if (const_args[2]) {
+ tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
+ } else {
+ tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
+ }
+ } else if (const_args[2]) {
+ a2 = -a2;
+ goto do_addi_32;
+ } else {
+ tcg_out32(s, SUBF | TAB(a0, a2, a1));
+ }
+ break;
+
+ case INDEX_op_and_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_andi32(s, a0, a1, a2);
+ } else {
+ tcg_out32(s, AND | SAB(a1, a0, a2));
+ }
+ break;
+ case INDEX_op_and_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_andi64(s, a0, a1, a2);
+ } else {
+ tcg_out32(s, AND | SAB(a1, a0, a2));
+ }
+ break;
+ case INDEX_op_or_i64:
+ case INDEX_op_or_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_ori32(s, a0, a1, a2);
+ } else {
+ tcg_out32(s, OR | SAB(a1, a0, a2));
+ }
+ break;
+ case INDEX_op_xor_i64:
+ case INDEX_op_xor_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_xori32(s, a0, a1, a2);
+ } else {
+ tcg_out32(s, XOR | SAB(a1, a0, a2));
+ }
+ break;
+ case INDEX_op_andc_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_andi32(s, a0, a1, ~a2);
+ } else {
+ tcg_out32(s, ANDC | SAB(a1, a0, a2));
+ }
+ break;
+ case INDEX_op_andc_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_andi64(s, a0, a1, ~a2);
+ } else {
+ tcg_out32(s, ANDC | SAB(a1, a0, a2));
+ }
+ break;
+ case INDEX_op_orc_i32:
+ if (const_args[2]) {
+ tcg_out_ori32(s, args[0], args[1], ~args[2]);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_orc_i64:
+ tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
+ break;
+ case INDEX_op_eqv_i32:
+ if (const_args[2]) {
+ tcg_out_xori32(s, args[0], args[1], ~args[2]);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_eqv_i64:
+ tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
+ break;
+ case INDEX_op_nand_i32:
+ case INDEX_op_nand_i64:
+ tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
+ break;
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
+ break;
+
+ case INDEX_op_clz_i32:
+ tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_ctz_i32:
+ tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_ctpop_i32:
+ tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
+ break;
+
+ case INDEX_op_clz_i64:
+ tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_ctz_i64:
+ tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_ctpop_i64:
+ tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
+ break;
+
+ case INDEX_op_mul_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out32(s, MULLI | TAI(a0, a1, a2));
+ } else {
+ tcg_out32(s, MULLW | TAB(a0, a1, a2));
+ }
+ break;
+
+ case INDEX_op_div_i32:
+ tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
+ break;
+
+ case INDEX_op_divu_i32:
+ tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
+ break;
+
+ case INDEX_op_shl_i32:
+ if (const_args[2]) {
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_shli32(s, args[0], args[1], args[2] & 31);
+ } else {
+ tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
+ }
+ break;
+ case INDEX_op_shr_i32:
+ if (const_args[2]) {
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_shri32(s, args[0], args[1], args[2] & 31);
+ } else {
+ tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
+ }
+ break;
+ case INDEX_op_sar_i32:
+ if (const_args[2]) {
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31));
+ } else {
+ tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
+ }
+ break;
+ case INDEX_op_rotl_i32:
+ if (const_args[2]) {
+ tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
+ } else {
+ tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
+ | MB(0) | ME(31));
+ }
+ break;
+ case INDEX_op_rotr_i32:
+ if (const_args[2]) {
+ tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
+ } else {
+ tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
+ tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
+ | MB(0) | ME(31));
+ }
+ break;
+
+ case INDEX_op_brcond_i32:
+ tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
+ arg_label(args[3]), TCG_TYPE_I32);
+ break;
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
+ arg_label(args[3]), TCG_TYPE_I64);
+ break;
+ case INDEX_op_brcond2_i32:
+ tcg_out_brcond2(s, args, const_args);
+ break;
+
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
+ break;
+
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
+ break;
+
+ case INDEX_op_add_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ do_addi_64:
+ tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
+ } else {
+ tcg_out32(s, ADD | TAB(a0, a1, a2));
+ }
+ break;
+ case INDEX_op_sub_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[1]) {
+ if (const_args[2]) {
+ tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
+ } else {
+ tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
+ }
+ } else if (const_args[2]) {
+ a2 = -a2;
+ goto do_addi_64;
+ } else {
+ tcg_out32(s, SUBF | TAB(a0, a2, a1));
+ }
+ break;
+
+ case INDEX_op_shl_i64:
+ if (const_args[2]) {
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_shli64(s, args[0], args[1], args[2] & 63);
+ } else {
+ tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
+ }
+ break;
+ case INDEX_op_shr_i64:
+ if (const_args[2]) {
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_shri64(s, args[0], args[1], args[2] & 63);
+ } else {
+ tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
+ }
+ break;
+ case INDEX_op_sar_i64:
+ if (const_args[2]) {
+ int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
+ tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
+ } else {
+ tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
+ }
+ break;
+ case INDEX_op_rotl_i64:
+ if (const_args[2]) {
+ tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
+ } else {
+ tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
+ }
+ break;
+ case INDEX_op_rotr_i64:
+ if (const_args[2]) {
+ tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
+ } else {
+ tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
+ tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
+ }
+ break;
+
+ case INDEX_op_mul_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out32(s, MULLI | TAI(a0, a1, a2));
+ } else {
+ tcg_out32(s, MULLD | TAB(a0, a1, a2));
+ }
+ break;
+ case INDEX_op_div_i64:
+ tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
+ break;
+ case INDEX_op_divu_i64:
+ tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_qemu_ld(s, args, false);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args, true);
+ break;
+ case INDEX_op_qemu_st_i32:
+ tcg_out_qemu_st(s, args, false);
+ break;
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args, true);
+ break;
+
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ c = EXTSB;
+ goto gen_ext;
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ c = EXTSH;
+ goto gen_ext;
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_ext32s_i64:
+ c = EXTSW;
+ goto gen_ext;
+ gen_ext:
+ tcg_out32(s, c | RS(args[1]) | RA(args[0]));
+ break;
+ case INDEX_op_extu_i32_i64:
+ tcg_out_ext32u(s, args[0], args[1]);
+ break;
+
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
+ const_args[2]);
+ break;
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
+ const_args[2]);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2(s, args, const_args);
+ break;
+
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ a0 = args[0], a1 = args[1];
+ /* a1 = abcd */
+ if (a0 != a1) {
+ /* a0 = (a1 r<< 24) & 0xff # 000c */
+ tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
+ /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
+ tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
+ } else {
+ /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
+ /* a0 = (a1 r<< 24) & 0xff # 000c */
+ tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
+ /* a0 = a0 | r0 # 00dc */
+ tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
+ }
+ break;
+
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ /* Stolen from gcc's builtin_bswap32 */
+ a1 = args[1];
+ a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
+
+ /* a1 = args[1] # abcd */
+ /* a0 = rotate_left (a1, 8) # bcda */
+ tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
+ /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
+ tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
+ /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
+ tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
+
+ if (a0 == TCG_REG_R0) {
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
+ }
+ break;
+
+ case INDEX_op_bswap64_i64:
+ a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
+ if (a0 == a1) {
+ a0 = TCG_REG_R0;
+ a2 = a1;
+ }
+
+ /* a1 = # abcd efgh */
+ /* a0 = rl32(a1, 8) # 0000 fghe */
+ tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
+ /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
+ tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
+ /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
+ tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
+
+ /* a0 = rl64(a0, 32) # hgfe 0000 */
+ /* a2 = rl64(a1, 32) # efgh abcd */
+ tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
+ tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
+
+ /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
+ tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
+ /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
+ tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
+ /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
+ tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
+
+ if (a0 == 0) {
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
+ }
+ break;
+
+ case INDEX_op_deposit_i32:
+ if (const_args[2]) {
+ uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
+ tcg_out_andi32(s, args[0], args[0], ~mask);
+ } else {
+ tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
+ 32 - args[3] - args[4], 31 - args[3]);
+ }
+ break;
+ case INDEX_op_deposit_i64:
+ if (const_args[2]) {
+ uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
+ tcg_out_andi64(s, args[0], args[0], ~mask);
+ } else {
+ tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
+ 64 - args[3] - args[4]);
+ }
+ break;
+
+ case INDEX_op_extract_i32:
+ tcg_out_rlw(s, RLWINM, args[0], args[1],
+ 32 - args[2], 32 - args[3], 31);
+ break;
+ case INDEX_op_extract_i64:
+ tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
+ break;
+
+ case INDEX_op_movcond_i32:
+ tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
+ args[3], args[4], const_args[2]);
+ break;
+ case INDEX_op_movcond_i64:
+ tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
+ args[3], args[4], const_args[2]);
+ break;
+
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_add2_i64:
+#else
+ case INDEX_op_add2_i32:
+#endif
+ /* Note that the CA bit is defined based on the word size of the
+ environment. So in 64-bit mode it's always carry-out of bit 63.
+ The fallback code using deposit works just as well for 32-bit. */
+ a0 = args[0], a1 = args[1];
+ if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
+ a0 = TCG_REG_R0;
+ }
+ if (const_args[4]) {
+ tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
+ } else {
+ tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
+ }
+ if (const_args[5]) {
+ tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
+ } else {
+ tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
+ }
+ if (a0 != args[0]) {
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
+ }
+ break;
+
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_sub2_i64:
+#else
+ case INDEX_op_sub2_i32:
+#endif
+ a0 = args[0], a1 = args[1];
+ if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
+ a0 = TCG_REG_R0;
+ }
+ if (const_args[2]) {
+ tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
+ } else {
+ tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
+ }
+ if (const_args[3]) {
+ tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
+ } else {
+ tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
+ }
+ if (a0 != args[0]) {
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
+ }
+ break;
+
+ case INDEX_op_muluh_i32:
+ tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
+ break;
+ case INDEX_op_mulsh_i32:
+ tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
+ break;
+ case INDEX_op_muluh_i64:
+ tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_not_vec:
+ return 1;
+ case INDEX_op_orc_vec:
+ return have_isa_2_07;
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_rotlv_vec:
+ return vece <= MO_32 || have_isa_2_07;
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
+ return vece <= MO_32;
+ case INDEX_op_cmp_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_rotli_vec:
+ return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
+ case INDEX_op_neg_vec:
+ return vece >= MO_32 && have_isa_3_00;
+ case INDEX_op_mul_vec:
+ switch (vece) {
+ case MO_8:
+ case MO_16:
+ return -1;
+ case MO_32:
+ return have_isa_2_07 ? 1 : -1;
+ }
+ return 0;
+ case INDEX_op_bitsel_vec:
+ return have_vsx;
+ case INDEX_op_rotrv_vec:
+ return -1;
+ default:
+ return 0;
+ }
+}
+
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, TCGReg src)
+{
+ tcg_debug_assert(dst >= TCG_REG_V0);
+
+ /* Splat from integer reg allowed via constraints for v3.00. */
+ if (src < TCG_REG_V0) {
+ tcg_debug_assert(have_isa_3_00);
+ switch (vece) {
+ case MO_64:
+ tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
+ return true;
+ case MO_32:
+ tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
+ return true;
+ default:
+ /* Fail, so that we fall back on either dupm or mov+dup. */
+ return false;
+ }
+ }
+
+ /*
+ * Recall we use (or emulate) VSX integer loads, so the integer is
+ * right justified within the left (zero-index) double-word.
+ */
+ switch (vece) {
+ case MO_8:
+ tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
+ break;
+ case MO_16:
+ tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
+ break;
+ case MO_32:
+ tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
+ break;
+ case MO_64:
+ if (have_vsx) {
+ tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
+ break;
+ }
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
+ tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg out, TCGReg base, intptr_t offset)
+{
+ int elt;
+
+ tcg_debug_assert(out >= TCG_REG_V0);
+ switch (vece) {
+ case MO_8:
+ if (have_isa_3_00) {
+ tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
+ } else {
+ tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
+ }
+ elt = extract32(offset, 0, 4);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt ^= 15;
+#endif
+ tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
+ break;
+ case MO_16:
+ tcg_debug_assert((offset & 1) == 0);
+ if (have_isa_3_00) {
+ tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
+ } else {
+ tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
+ }
+ elt = extract32(offset, 1, 3);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt ^= 7;
+#endif
+ tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
+ break;
+ case MO_32:
+ if (have_isa_3_00) {
+ tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
+ break;
+ }
+ tcg_debug_assert((offset & 3) == 0);
+ tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
+ elt = extract32(offset, 2, 2);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt ^= 3;
+#endif
+ tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
+ break;
+ case MO_64:
+ if (have_vsx) {
+ tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
+ break;
+ }
+ tcg_debug_assert((offset & 7) == 0);
+ tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
+ elt = extract32(offset, 3, 1);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt = !elt;
+#endif
+ if (elt) {
+ tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
+ } else {
+ tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static const uint32_t
+ add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
+ sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
+ neg_op[4] = { 0, 0, VNEGW, VNEGD },
+ eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
+ ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
+ gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
+ gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
+ ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
+ usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
+ sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
+ ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
+ umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
+ smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
+ umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
+ smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
+ shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
+ shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
+ sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
+ mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
+ mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
+ muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
+ mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
+ pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
+ rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
+ uint32_t insn;
+
+ switch (opc) {
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ return;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ return;
+ case INDEX_op_dupm_vec:
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+ return;
+
+ case INDEX_op_add_vec:
+ insn = add_op[vece];
+ break;
+ case INDEX_op_sub_vec:
+ insn = sub_op[vece];
+ break;
+ case INDEX_op_neg_vec:
+ insn = neg_op[vece];
+ a2 = a1;
+ a1 = 0;
+ break;
+ case INDEX_op_mul_vec:
+ tcg_debug_assert(vece == MO_32 && have_isa_2_07);
+ insn = VMULUWM;
+ break;
+ case INDEX_op_ssadd_vec:
+ insn = ssadd_op[vece];
+ break;
+ case INDEX_op_sssub_vec:
+ insn = sssub_op[vece];
+ break;
+ case INDEX_op_usadd_vec:
+ insn = usadd_op[vece];
+ break;
+ case INDEX_op_ussub_vec:
+ insn = ussub_op[vece];
+ break;
+ case INDEX_op_smin_vec:
+ insn = smin_op[vece];
+ break;
+ case INDEX_op_umin_vec:
+ insn = umin_op[vece];
+ break;
+ case INDEX_op_smax_vec:
+ insn = smax_op[vece];
+ break;
+ case INDEX_op_umax_vec:
+ insn = umax_op[vece];
+ break;
+ case INDEX_op_shlv_vec:
+ insn = shlv_op[vece];
+ break;
+ case INDEX_op_shrv_vec:
+ insn = shrv_op[vece];
+ break;
+ case INDEX_op_sarv_vec:
+ insn = sarv_op[vece];
+ break;
+ case INDEX_op_and_vec:
+ insn = VAND;
+ break;
+ case INDEX_op_or_vec:
+ insn = VOR;
+ break;
+ case INDEX_op_xor_vec:
+ insn = VXOR;
+ break;
+ case INDEX_op_andc_vec:
+ insn = VANDC;
+ break;
+ case INDEX_op_not_vec:
+ insn = VNOR;
+ a2 = a1;
+ break;
+ case INDEX_op_orc_vec:
+ insn = VORC;
+ break;
+
+ case INDEX_op_cmp_vec:
+ switch (args[3]) {
+ case TCG_COND_EQ:
+ insn = eq_op[vece];
+ break;
+ case TCG_COND_NE:
+ insn = ne_op[vece];
+ break;
+ case TCG_COND_GT:
+ insn = gts_op[vece];
+ break;
+ case TCG_COND_GTU:
+ insn = gtu_op[vece];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_bitsel_vec:
+ tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
+ return;
+
+ case INDEX_op_dup2_vec:
+ assert(TCG_TARGET_REG_BITS == 32);
+ /* With inputs a1 = xLxx, a2 = xHxx */
+ tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
+ tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
+ return;
+
+ case INDEX_op_ppc_mrgh_vec:
+ insn = mrgh_op[vece];
+ break;
+ case INDEX_op_ppc_mrgl_vec:
+ insn = mrgl_op[vece];
+ break;
+ case INDEX_op_ppc_muleu_vec:
+ insn = muleu_op[vece];
+ break;
+ case INDEX_op_ppc_mulou_vec:
+ insn = mulou_op[vece];
+ break;
+ case INDEX_op_ppc_pkum_vec:
+ insn = pkum_op[vece];
+ break;
+ case INDEX_op_rotlv_vec:
+ insn = rotl_op[vece];
+ break;
+ case INDEX_op_ppc_msum_vec:
+ tcg_debug_assert(vece == MO_16);
+ tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
+ return;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
+ default:
+ g_assert_not_reached();
+ }
+
+ tcg_debug_assert(insn != 0);
+ tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
+}
+
+static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGArg imm, TCGOpcode opci)
+{
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+
+ /* Splat w/bytes for xxspltib. */
+ tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
+ vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+}
+
+static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
+{
+ bool need_swap = false, need_inv = false;
+
+ tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_GT:
+ case TCG_COND_GTU:
+ break;
+ case TCG_COND_NE:
+ if (have_isa_3_00 && vece <= MO_32) {
+ break;
+ }
+ /* fall through */
+ case TCG_COND_LE:
+ case TCG_COND_LEU:
+ need_inv = true;
+ break;
+ case TCG_COND_LT:
+ case TCG_COND_LTU:
+ need_swap = true;
+ break;
+ case TCG_COND_GE:
+ case TCG_COND_GEU:
+ need_swap = need_inv = true;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (need_inv) {
+ cond = tcg_invert_cond(cond);
+ }
+ if (need_swap) {
+ TCGv_vec t1;
+ t1 = v1, v1 = v2, v2 = t1;
+ cond = tcg_swap_cond(cond);
+ }
+
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
+
+ if (need_inv) {
+ tcg_gen_not_vec(vece, v0, v0);
+ }
+}
+
+static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2)
+{
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ TCGv_vec t3, t4;
+
+ switch (vece) {
+ case MO_8:
+ case MO_16:
+ vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1));
+ break;
+
+ case MO_32:
+ tcg_debug_assert(!have_isa_2_07);
+ t3 = tcg_temp_new_vec(type);
+ t4 = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(MO_8, t4, -16);
+ vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v2), tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ tcg_gen_dupi_vec(MO_8, t3, 0);
+ vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3),
+ tcgv_vec_arg(t3), tcgv_vec_arg(t4));
+ tcg_gen_add_vec(MO_32, v0, t2, t3);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ va_list va;
+ TCGv_vec v0, v1, v2, t0;
+ TCGArg a2;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ a2 = va_arg(va, TCGArg);
+
+ switch (opc) {
+ case INDEX_op_shli_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
+ break;
+ case INDEX_op_shri_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
+ break;
+ case INDEX_op_sari_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
+ break;
+ case INDEX_op_rotli_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
+ break;
+ case INDEX_op_cmp_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
+ break;
+ case INDEX_op_mul_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_mul(type, vece, v0, v1, v2);
+ break;
+ case INDEX_op_rotlv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ t0 = tcg_temp_new_vec(type);
+ tcg_gen_neg_vec(vece, t0, v2);
+ tcg_gen_rotlv_vec(vece, v0, v1, t0);
+ tcg_temp_free_vec(t0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ va_end(va);
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
+ static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
+ static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
+ static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
+ static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
+ static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
+ static const TCGTargetOpDef r_rI_ri
+ = { .args_ct_str = { "r", "rI", "ri" } };
+ static const TCGTargetOpDef r_rI_rT
+ = { .args_ct_str = { "r", "rI", "rT" } };
+ static const TCGTargetOpDef r_r_rZW
+ = { .args_ct_str = { "r", "r", "rZW" } };
+ static const TCGTargetOpDef L_L_L_L
+ = { .args_ct_str = { "L", "L", "L", "L" } };
+ static const TCGTargetOpDef S_S_S_S
+ = { .args_ct_str = { "S", "S", "S", "S" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef br2
+ = { .args_ct_str = { "r", "r", "ri", "ri" } };
+ static const TCGTargetOpDef setc2
+ = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
+ static const TCGTargetOpDef sub2
+ = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
+ static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
+ static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
+ static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
+ static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
+ static const TCGTargetOpDef v_v_v_v
+ = { .args_ct_str = { "v", "v", "v", "v" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ case INDEX_op_ctpop_i64:
+ case INDEX_op_neg_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_extract_i64:
+ return &r_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_and_i32:
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_andc_i32:
+ case INDEX_op_orc_i32:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i64:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_setcond_i64:
+ return &r_r_ri;
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ return &r_r_rI;
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nor_i32:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i64:
+ return &r_r_r;
+ case INDEX_op_sub_i32:
+ return &r_rI_ri;
+ case INDEX_op_add_i64:
+ return &r_r_rT;
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i64:
+ return &r_r_rU;
+ case INDEX_op_sub_i64:
+ return &r_rI_rT;
+ case INDEX_op_clz_i32:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i64:
+ return &r_r_rZW;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &r_ri;
+
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ return &movc;
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return &dep;
+ case INDEX_op_brcond2_i32:
+ return &br2;
+ case INDEX_op_setcond2_i32:
+ return &setc2;
+ case INDEX_op_add2_i64:
+ case INDEX_op_add2_i32:
+ return &add2;
+ case INDEX_op_sub2_i64:
+ case INDEX_op_sub2_i32:
+ return &sub2;
+
+ case INDEX_op_qemu_ld_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &r_L : &r_L_L);
+ case INDEX_op_qemu_st_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &S_S : &S_S_S);
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &r_L
+ : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &S_S
+ : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
+ case INDEX_op_ppc_mrgh_vec:
+ case INDEX_op_ppc_mrgl_vec:
+ case INDEX_op_ppc_muleu_vec:
+ case INDEX_op_ppc_mulou_vec:
+ case INDEX_op_ppc_pkum_vec:
+ case INDEX_op_dup2_vec:
+ return &v_v_v;
+ case INDEX_op_not_vec:
+ case INDEX_op_neg_vec:
+ return &v_v;
+ case INDEX_op_dup_vec:
+ return have_isa_3_00 ? &v_vr : &v_v;
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ case INDEX_op_dupm_vec:
+ return &v_r;
+ case INDEX_op_bitsel_vec:
+ case INDEX_op_ppc_msum_vec:
+ return &v_v_v_v;
+
+ default:
+ return NULL;
+ }
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+ unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
+
+ have_isa = tcg_isa_base;
+ if (hwcap & PPC_FEATURE_ARCH_2_06) {
+ have_isa = tcg_isa_2_06;
+ }
+#ifdef PPC_FEATURE2_ARCH_2_07
+ if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
+ have_isa = tcg_isa_2_07;
+ }
+#endif
+#ifdef PPC_FEATURE2_ARCH_3_00
+ if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
+ have_isa = tcg_isa_3_00;
+ }
+#endif
+
+#ifdef PPC_FEATURE2_HAS_ISEL
+ /* Prefer explicit instruction from the kernel. */
+ have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
+#else
+ /* Fall back to knowing Power7 (2.06) has ISEL. */
+ have_isel = have_isa_2_06;
+#endif
+
+ if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
+ have_altivec = true;
+ /* We only care about the portion of VSX that overlaps Altivec. */
+ if (hwcap & PPC_FEATURE_HAS_VSX) {
+ have_vsx = true;
+ }
+ }
+
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
+ if (have_altivec) {
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
+ }
+
+ tcg_target_call_clobber_regs = 0;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
+
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
+#if defined(_CALL_SYSV)
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
+#endif
+#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
+#endif
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
+ if (USE_REG_TB) {
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
+ }
+}
+
+#ifdef __ELF__
+typedef struct {
+ DebugFrameCIE cie;
+ DebugFrameFDEHeader fde;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
+} DebugFrame;
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+#if TCG_TARGET_REG_BITS == 64
+# define ELF_HOST_MACHINE EM_PPC64
+#else
+# define ELF_HOST_MACHINE EM_PPC
+#endif
+
+static DebugFrame debug_frame = {
+ .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .cie.id = -1,
+ .cie.version = 1,
+ .cie.code_align = 1,
+ .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
+ .cie.return_column = 65,
+
+ /* Total FDE size does not include the "len" member. */
+ .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
+ 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ uint8_t *p = &debug_frame.fde_reg_ofs[3];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
+ p[0] = 0x80 + tcg_target_callee_save_regs[i];
+ p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
+ }
+
+ debug_frame.fde.func_start = (uintptr_t)buf;
+ debug_frame.fde.func_len = buf_size;
+
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+#endif /* __ELF__ */
+
+void flush_icache_range(uintptr_t start, uintptr_t stop)
+{
+ uintptr_t p, start1, stop1;
+ size_t dsize = qemu_dcache_linesize;
+ size_t isize = qemu_icache_linesize;
+
+ start1 = start & ~(dsize - 1);
+ stop1 = (stop + dsize - 1) & ~(dsize - 1);
+ for (p = start1; p < stop1; p += dsize) {
+ asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
+ }
+ asm volatile ("sync" : : : "memory");
+
+ start &= start & ~(isize - 1);
+ stop1 = (stop + isize - 1) & ~(isize - 1);
+ for (p = start1; p < stop1; p += isize) {
+ asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
+ }
+ asm volatile ("sync" : : : "memory");
+ asm volatile ("isync" : : : "memory");
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "elf.h"
-#include "../tcg-pool.inc.c"
-
-#if defined _CALL_DARWIN || defined __APPLE__
-#define TCG_TARGET_CALL_DARWIN
-#endif
-#ifdef _CALL_SYSV
-# define TCG_TARGET_CALL_ALIGN_ARGS 1
-#endif
-
-/* For some memory operations, we need a scratch that isn't R0. For the AIX
- calling convention, we can re-use the TOC register since we'll be reloading
- it at every call. Otherwise R12 will do nicely as neither a call-saved
- register nor a parameter register. */
-#ifdef _CALL_AIX
-# define TCG_REG_TMP1 TCG_REG_R2
-#else
-# define TCG_REG_TMP1 TCG_REG_R12
-#endif
-
-#define TCG_VEC_TMP1 TCG_REG_V0
-#define TCG_VEC_TMP2 TCG_REG_V1
-
-#define TCG_REG_TB TCG_REG_R31
-#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
-
-/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
-#define SZP ((int)sizeof(void *))
-
-/* Shorthand for size of a register. */
-#define SZR (TCG_TARGET_REG_BITS / 8)
-
-#define TCG_CT_CONST_S16 0x100
-#define TCG_CT_CONST_U16 0x200
-#define TCG_CT_CONST_S32 0x400
-#define TCG_CT_CONST_U32 0x800
-#define TCG_CT_CONST_ZERO 0x1000
-#define TCG_CT_CONST_MONE 0x2000
-#define TCG_CT_CONST_WSZ 0x4000
-
-static tcg_insn_unit *tb_ret_addr;
-
-TCGPowerISA have_isa;
-static bool have_isel;
-bool have_altivec;
-bool have_vsx;
-
-#ifndef CONFIG_SOFTMMU
-#define TCG_GUEST_BASE_REG 30
-#endif
-
-#ifdef CONFIG_DEBUG_TCG
-static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
- "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
- "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
- "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
- "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
-};
-#endif
-
-static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R14, /* call saved registers */
- TCG_REG_R15,
- TCG_REG_R16,
- TCG_REG_R17,
- TCG_REG_R18,
- TCG_REG_R19,
- TCG_REG_R20,
- TCG_REG_R21,
- TCG_REG_R22,
- TCG_REG_R23,
- TCG_REG_R24,
- TCG_REG_R25,
- TCG_REG_R26,
- TCG_REG_R27,
- TCG_REG_R28,
- TCG_REG_R29,
- TCG_REG_R30,
- TCG_REG_R31,
- TCG_REG_R12, /* call clobbered, non-arguments */
- TCG_REG_R11,
- TCG_REG_R2,
- TCG_REG_R13,
- TCG_REG_R10, /* call clobbered, arguments */
- TCG_REG_R9,
- TCG_REG_R8,
- TCG_REG_R7,
- TCG_REG_R6,
- TCG_REG_R5,
- TCG_REG_R4,
- TCG_REG_R3,
-
- /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
- TCG_REG_V2, /* call clobbered, vectors */
- TCG_REG_V3,
- TCG_REG_V4,
- TCG_REG_V5,
- TCG_REG_V6,
- TCG_REG_V7,
- TCG_REG_V8,
- TCG_REG_V9,
- TCG_REG_V10,
- TCG_REG_V11,
- TCG_REG_V12,
- TCG_REG_V13,
- TCG_REG_V14,
- TCG_REG_V15,
- TCG_REG_V16,
- TCG_REG_V17,
- TCG_REG_V18,
- TCG_REG_V19,
-};
-
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_R3,
- TCG_REG_R4,
- TCG_REG_R5,
- TCG_REG_R6,
- TCG_REG_R7,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_R3,
- TCG_REG_R4
-};
-
-static const int tcg_target_callee_save_regs[] = {
-#ifdef TCG_TARGET_CALL_DARWIN
- TCG_REG_R11,
-#endif
- TCG_REG_R14,
- TCG_REG_R15,
- TCG_REG_R16,
- TCG_REG_R17,
- TCG_REG_R18,
- TCG_REG_R19,
- TCG_REG_R20,
- TCG_REG_R21,
- TCG_REG_R22,
- TCG_REG_R23,
- TCG_REG_R24,
- TCG_REG_R25,
- TCG_REG_R26,
- TCG_REG_R27, /* currently used for the global env */
- TCG_REG_R28,
- TCG_REG_R29,
- TCG_REG_R30,
- TCG_REG_R31
-};
-
-static inline bool in_range_b(tcg_target_long target)
-{
- return target == sextract64(target, 0, 26);
-}
-
-static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
- tcg_debug_assert(in_range_b(disp));
- return disp & 0x3fffffc;
-}
-
-static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
- if (in_range_b(disp)) {
- *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc);
- return true;
- }
- return false;
-}
-
-static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
- tcg_debug_assert(disp == (int16_t) disp);
- return disp & 0xfffc;
-}
-
-static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
-{
- ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
- if (disp == (int16_t) disp) {
- *pc = (*pc & ~0xfffc) | (disp & 0xfffc);
- return true;
- }
- return false;
-}
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'A': case 'B': case 'C': case 'D':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
- break;
- case 'r':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- break;
- case 'v':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff00000000ull;
- break;
- case 'L': /* qemu_ld constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
-#endif
- break;
- case 'S': /* qemu_st constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_U16;
- break;
- case 'M':
- ct->ct |= TCG_CT_CONST_MONE;
- break;
- case 'T':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'U':
- ct->ct |= TCG_CT_CONST_U32;
- break;
- case 'W':
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct = arg_ct->ct;
- if (ct & TCG_CT_CONST) {
- return 1;
- }
-
- /* The only 32-bit constraint we use aside from
- TCG_CT_CONST is TCG_CT_CONST_S16. */
- if (type == TCG_TYPE_I32) {
- val = (int32_t)val;
- }
-
- if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
- return 1;
- } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
- return 1;
- } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
- return 1;
- } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
- return 1;
- } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
- return 1;
- } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
- return 1;
- } else if ((ct & TCG_CT_CONST_WSZ)
- && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
- return 1;
- }
- return 0;
-}
-
-#define OPCD(opc) ((opc)<<26)
-#define XO19(opc) (OPCD(19)|((opc)<<1))
-#define MD30(opc) (OPCD(30)|((opc)<<2))
-#define MDS30(opc) (OPCD(30)|((opc)<<1))
-#define XO31(opc) (OPCD(31)|((opc)<<1))
-#define XO58(opc) (OPCD(58)|(opc))
-#define XO62(opc) (OPCD(62)|(opc))
-#define VX4(opc) (OPCD(4)|(opc))
-
-#define B OPCD( 18)
-#define BC OPCD( 16)
-#define LBZ OPCD( 34)
-#define LHZ OPCD( 40)
-#define LHA OPCD( 42)
-#define LWZ OPCD( 32)
-#define LWZUX XO31( 55)
-#define STB OPCD( 38)
-#define STH OPCD( 44)
-#define STW OPCD( 36)
-
-#define STD XO62( 0)
-#define STDU XO62( 1)
-#define STDX XO31(149)
-
-#define LD XO58( 0)
-#define LDX XO31( 21)
-#define LDU XO58( 1)
-#define LDUX XO31( 53)
-#define LWA XO58( 2)
-#define LWAX XO31(341)
-
-#define ADDIC OPCD( 12)
-#define ADDI OPCD( 14)
-#define ADDIS OPCD( 15)
-#define ORI OPCD( 24)
-#define ORIS OPCD( 25)
-#define XORI OPCD( 26)
-#define XORIS OPCD( 27)
-#define ANDI OPCD( 28)
-#define ANDIS OPCD( 29)
-#define MULLI OPCD( 7)
-#define CMPLI OPCD( 10)
-#define CMPI OPCD( 11)
-#define SUBFIC OPCD( 8)
-
-#define LWZU OPCD( 33)
-#define STWU OPCD( 37)
-
-#define RLWIMI OPCD( 20)
-#define RLWINM OPCD( 21)
-#define RLWNM OPCD( 23)
-
-#define RLDICL MD30( 0)
-#define RLDICR MD30( 1)
-#define RLDIMI MD30( 3)
-#define RLDCL MDS30( 8)
-
-#define BCLR XO19( 16)
-#define BCCTR XO19(528)
-#define CRAND XO19(257)
-#define CRANDC XO19(129)
-#define CRNAND XO19(225)
-#define CROR XO19(449)
-#define CRNOR XO19( 33)
-
-#define EXTSB XO31(954)
-#define EXTSH XO31(922)
-#define EXTSW XO31(986)
-#define ADD XO31(266)
-#define ADDE XO31(138)
-#define ADDME XO31(234)
-#define ADDZE XO31(202)
-#define ADDC XO31( 10)
-#define AND XO31( 28)
-#define SUBF XO31( 40)
-#define SUBFC XO31( 8)
-#define SUBFE XO31(136)
-#define SUBFME XO31(232)
-#define SUBFZE XO31(200)
-#define OR XO31(444)
-#define XOR XO31(316)
-#define MULLW XO31(235)
-#define MULHW XO31( 75)
-#define MULHWU XO31( 11)
-#define DIVW XO31(491)
-#define DIVWU XO31(459)
-#define CMP XO31( 0)
-#define CMPL XO31( 32)
-#define LHBRX XO31(790)
-#define LWBRX XO31(534)
-#define LDBRX XO31(532)
-#define STHBRX XO31(918)
-#define STWBRX XO31(662)
-#define STDBRX XO31(660)
-#define MFSPR XO31(339)
-#define MTSPR XO31(467)
-#define SRAWI XO31(824)
-#define NEG XO31(104)
-#define MFCR XO31( 19)
-#define MFOCRF (MFCR | (1u << 20))
-#define NOR XO31(124)
-#define CNTLZW XO31( 26)
-#define CNTLZD XO31( 58)
-#define CNTTZW XO31(538)
-#define CNTTZD XO31(570)
-#define CNTPOPW XO31(378)
-#define CNTPOPD XO31(506)
-#define ANDC XO31( 60)
-#define ORC XO31(412)
-#define EQV XO31(284)
-#define NAND XO31(476)
-#define ISEL XO31( 15)
-
-#define MULLD XO31(233)
-#define MULHD XO31( 73)
-#define MULHDU XO31( 9)
-#define DIVD XO31(489)
-#define DIVDU XO31(457)
-
-#define LBZX XO31( 87)
-#define LHZX XO31(279)
-#define LHAX XO31(343)
-#define LWZX XO31( 23)
-#define STBX XO31(215)
-#define STHX XO31(407)
-#define STWX XO31(151)
-
-#define EIEIO XO31(854)
-#define HWSYNC XO31(598)
-#define LWSYNC (HWSYNC | (1u << 21))
-
-#define SPR(a, b) ((((a)<<5)|(b))<<11)
-#define LR SPR(8, 0)
-#define CTR SPR(9, 0)
-
-#define SLW XO31( 24)
-#define SRW XO31(536)
-#define SRAW XO31(792)
-
-#define SLD XO31( 27)
-#define SRD XO31(539)
-#define SRAD XO31(794)
-#define SRADI XO31(413<<1)
-
-#define TW XO31( 4)
-#define TRAP (TW | TO(31))
-
-#define NOP ORI /* ori 0,0,0 */
-
-#define LVX XO31(103)
-#define LVEBX XO31(7)
-#define LVEHX XO31(39)
-#define LVEWX XO31(71)
-#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
-#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
-#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
-#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
-#define LXSD (OPCD(57) | 2) /* v3.00 */
-#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
-
-#define STVX XO31(231)
-#define STVEWX XO31(199)
-#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
-#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
-#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
-#define STXSD (OPCD(61) | 2) /* v3.00 */
-
-#define VADDSBS VX4(768)
-#define VADDUBS VX4(512)
-#define VADDUBM VX4(0)
-#define VADDSHS VX4(832)
-#define VADDUHS VX4(576)
-#define VADDUHM VX4(64)
-#define VADDSWS VX4(896)
-#define VADDUWS VX4(640)
-#define VADDUWM VX4(128)
-#define VADDUDM VX4(192) /* v2.07 */
-
-#define VSUBSBS VX4(1792)
-#define VSUBUBS VX4(1536)
-#define VSUBUBM VX4(1024)
-#define VSUBSHS VX4(1856)
-#define VSUBUHS VX4(1600)
-#define VSUBUHM VX4(1088)
-#define VSUBSWS VX4(1920)
-#define VSUBUWS VX4(1664)
-#define VSUBUWM VX4(1152)
-#define VSUBUDM VX4(1216) /* v2.07 */
-
-#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
-#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
-
-#define VMAXSB VX4(258)
-#define VMAXSH VX4(322)
-#define VMAXSW VX4(386)
-#define VMAXSD VX4(450) /* v2.07 */
-#define VMAXUB VX4(2)
-#define VMAXUH VX4(66)
-#define VMAXUW VX4(130)
-#define VMAXUD VX4(194) /* v2.07 */
-#define VMINSB VX4(770)
-#define VMINSH VX4(834)
-#define VMINSW VX4(898)
-#define VMINSD VX4(962) /* v2.07 */
-#define VMINUB VX4(514)
-#define VMINUH VX4(578)
-#define VMINUW VX4(642)
-#define VMINUD VX4(706) /* v2.07 */
-
-#define VCMPEQUB VX4(6)
-#define VCMPEQUH VX4(70)
-#define VCMPEQUW VX4(134)
-#define VCMPEQUD VX4(199) /* v2.07 */
-#define VCMPGTSB VX4(774)
-#define VCMPGTSH VX4(838)
-#define VCMPGTSW VX4(902)
-#define VCMPGTSD VX4(967) /* v2.07 */
-#define VCMPGTUB VX4(518)
-#define VCMPGTUH VX4(582)
-#define VCMPGTUW VX4(646)
-#define VCMPGTUD VX4(711) /* v2.07 */
-#define VCMPNEB VX4(7) /* v3.00 */
-#define VCMPNEH VX4(71) /* v3.00 */
-#define VCMPNEW VX4(135) /* v3.00 */
-
-#define VSLB VX4(260)
-#define VSLH VX4(324)
-#define VSLW VX4(388)
-#define VSLD VX4(1476) /* v2.07 */
-#define VSRB VX4(516)
-#define VSRH VX4(580)
-#define VSRW VX4(644)
-#define VSRD VX4(1732) /* v2.07 */
-#define VSRAB VX4(772)
-#define VSRAH VX4(836)
-#define VSRAW VX4(900)
-#define VSRAD VX4(964) /* v2.07 */
-#define VRLB VX4(4)
-#define VRLH VX4(68)
-#define VRLW VX4(132)
-#define VRLD VX4(196) /* v2.07 */
-
-#define VMULEUB VX4(520)
-#define VMULEUH VX4(584)
-#define VMULEUW VX4(648) /* v2.07 */
-#define VMULOUB VX4(8)
-#define VMULOUH VX4(72)
-#define VMULOUW VX4(136) /* v2.07 */
-#define VMULUWM VX4(137) /* v2.07 */
-#define VMSUMUHM VX4(38)
-
-#define VMRGHB VX4(12)
-#define VMRGHH VX4(76)
-#define VMRGHW VX4(140)
-#define VMRGLB VX4(268)
-#define VMRGLH VX4(332)
-#define VMRGLW VX4(396)
-
-#define VPKUHUM VX4(14)
-#define VPKUWUM VX4(78)
-
-#define VAND VX4(1028)
-#define VANDC VX4(1092)
-#define VNOR VX4(1284)
-#define VOR VX4(1156)
-#define VXOR VX4(1220)
-#define VEQV VX4(1668) /* v2.07 */
-#define VNAND VX4(1412) /* v2.07 */
-#define VORC VX4(1348) /* v2.07 */
-
-#define VSPLTB VX4(524)
-#define VSPLTH VX4(588)
-#define VSPLTW VX4(652)
-#define VSPLTISB VX4(780)
-#define VSPLTISH VX4(844)
-#define VSPLTISW VX4(908)
-
-#define VSLDOI VX4(44)
-
-#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
-#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
-#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
-
-#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
-#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
-#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
-#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
-#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
-#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
-
-#define RT(r) ((r)<<21)
-#define RS(r) ((r)<<21)
-#define RA(r) ((r)<<16)
-#define RB(r) ((r)<<11)
-#define TO(t) ((t)<<21)
-#define SH(s) ((s)<<11)
-#define MB(b) ((b)<<6)
-#define ME(e) ((e)<<1)
-#define BO(o) ((o)<<21)
-#define MB64(b) ((b)<<5)
-#define FXM(b) (1 << (19 - (b)))
-
-#define VRT(r) (((r) & 31) << 21)
-#define VRA(r) (((r) & 31) << 16)
-#define VRB(r) (((r) & 31) << 11)
-#define VRC(r) (((r) & 31) << 6)
-
-#define LK 1
-
-#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
-#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
-#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
-#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
-
-#define BF(n) ((n)<<23)
-#define BI(n, c) (((c)+((n)*4))<<16)
-#define BT(n, c) (((c)+((n)*4))<<21)
-#define BA(n, c) (((c)+((n)*4))<<16)
-#define BB(n, c) (((c)+((n)*4))<<11)
-#define BC_(n, c) (((c)+((n)*4))<<6)
-
-#define BO_COND_TRUE BO(12)
-#define BO_COND_FALSE BO( 4)
-#define BO_ALWAYS BO(20)
-
-enum {
- CR_LT,
- CR_GT,
- CR_EQ,
- CR_SO
-};
-
-static const uint32_t tcg_to_bc[] = {
- [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
- [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
- [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
- [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
- [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
- [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
- [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
- [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
- [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
- [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
-};
-
-/* The low bit here is set if the RA and RB fields must be inverted. */
-static const uint32_t tcg_to_isel[] = {
- [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
- [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
- [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
- [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
- [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
- [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
- [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
- [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
- [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
- [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
-};
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- tcg_insn_unit *target;
- int16_t lo;
- int32_t hi;
-
- value += addend;
- target = (tcg_insn_unit *)value;
-
- switch (type) {
- case R_PPC_REL14:
- return reloc_pc14(code_ptr, target);
- case R_PPC_REL24:
- return reloc_pc24(code_ptr, target);
- case R_PPC_ADDR16:
- /*
- * We are (slightly) abusing this relocation type. In particular,
- * assert that the low 2 bits are zero, and do not modify them.
- * That way we can use this with LD et al that have opcode bits
- * in the low 2 bits of the insn.
- */
- if ((value & 3) || value != (int16_t)value) {
- return false;
- }
- *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
- break;
- case R_PPC_ADDR32:
- /*
- * We are abusing this relocation type. Again, this points to
- * a pair of insns, lis + load. This is an absolute address
- * relocation for PPC32 so the lis cannot be removed.
- */
- lo = value;
- hi = value - lo;
- if (hi + lo != value) {
- return false;
- }
- code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
- code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
- break;
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
- TCGReg base, tcg_target_long offset);
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
-{
- if (ret == arg) {
- return true;
- }
- switch (type) {
- case TCG_TYPE_I64:
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- /* fallthru */
- case TCG_TYPE_I32:
- if (ret < TCG_REG_V0) {
- if (arg < TCG_REG_V0) {
- tcg_out32(s, OR | SAB(arg, ret, arg));
- break;
- } else if (have_isa_2_07) {
- tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
- | VRT(arg) | RA(ret));
- break;
- } else {
- /* Altivec does not support vector->integer moves. */
- return false;
- }
- } else if (arg < TCG_REG_V0) {
- if (have_isa_2_07) {
- tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
- | VRT(ret) | RA(arg));
- break;
- } else {
- /* Altivec does not support integer->vector moves. */
- return false;
- }
- }
- /* fallthru */
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
- tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
- break;
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
- int sh, int mb)
-{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
- mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
- tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
-}
-
-static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
- int sh, int mb, int me)
-{
- tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
-}
-
-static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
-{
- tcg_out_rld(s, RLDICL, dst, src, 0, 32);
-}
-
-static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
-{
- tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
-}
-
-static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
-{
- tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
-}
-
-static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
-{
- tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
-}
-
-static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
-{
- tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
-}
-
-/* Emit a move into ret of arg, if it can be done in one insn. */
-static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
-{
- if (arg == (int16_t)arg) {
- tcg_out32(s, ADDI | TAI(ret, 0, arg));
- return true;
- }
- if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
- tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
- return true;
- }
- return false;
-}
-
-static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long arg, bool in_prologue)
-{
- intptr_t tb_diff;
- tcg_target_long tmp;
- int shift;
-
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
- arg = (int32_t)arg;
- }
-
- /* Load 16-bit immediates with one insn. */
- if (tcg_out_movi_one(s, ret, arg)) {
- return;
- }
-
- /* Load addresses within the TB with one insn. */
- tb_diff = arg - (intptr_t)s->code_gen_ptr;
- if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
- tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
- return;
- }
-
- /* Load 32-bit immediates with two insns. Note that we've already
- eliminated bare ADDIS, so we know both insns are required. */
- if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
- tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
- tcg_out32(s, ORI | SAI(ret, ret, arg));
- return;
- }
- if (arg == (uint32_t)arg && !(arg & 0x8000)) {
- tcg_out32(s, ADDI | TAI(ret, 0, arg));
- tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
- return;
- }
-
- /* Load masked 16-bit value. */
- if (arg > 0 && (arg & 0x8000)) {
- tmp = arg | 0x7fff;
- if ((tmp & (tmp + 1)) == 0) {
- int mb = clz64(tmp + 1) + 1;
- tcg_out32(s, ADDI | TAI(ret, 0, arg));
- tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
- return;
- }
- }
-
- /* Load common masks with 2 insns. */
- shift = ctz64(arg);
- tmp = arg >> shift;
- if (tmp == (int16_t)tmp) {
- tcg_out32(s, ADDI | TAI(ret, 0, tmp));
- tcg_out_shli64(s, ret, ret, shift);
- return;
- }
- shift = clz64(arg);
- if (tcg_out_movi_one(s, ret, arg << shift)) {
- tcg_out_shri64(s, ret, ret, shift);
- return;
- }
-
- /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
- if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
- tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
- return;
- }
-
- /* Use the constant pool, if possible. */
- if (!in_prologue && USE_REG_TB) {
- new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
- -(intptr_t)s->code_gen_ptr);
- tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
- return;
- }
-
- tmp = arg >> 31 >> 1;
- tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
- if (tmp) {
- tcg_out_shli64(s, ret, ret, 32);
- }
- if (arg & 0xffff0000) {
- tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
- }
- if (arg & 0xffff) {
- tcg_out32(s, ORI | SAI(ret, ret, arg));
- }
-}
-
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long val)
-{
- uint32_t load_insn;
- int rel, low;
- intptr_t add;
-
- low = (int8_t)val;
- if (low >= -16 && low < 16) {
- if (val == (tcg_target_long)dup_const(MO_8, low)) {
- tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
- return;
- }
- if (val == (tcg_target_long)dup_const(MO_16, low)) {
- tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
- return;
- }
- if (val == (tcg_target_long)dup_const(MO_32, low)) {
- tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
- return;
- }
- }
- if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) {
- tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
- return;
- }
-
- /*
- * Otherwise we must load the value from the constant pool.
- */
- if (USE_REG_TB) {
- rel = R_PPC_ADDR16;
- add = -(intptr_t)s->code_gen_ptr;
- } else {
- rel = R_PPC_ADDR32;
- add = 0;
- }
-
- if (have_vsx) {
- load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
- load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
- if (TCG_TARGET_REG_BITS == 64) {
- new_pool_label(s, val, rel, s->code_ptr, add);
- } else {
- new_pool_l2(s, rel, s->code_ptr, add, val, val);
- }
- } else {
- load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
- if (TCG_TARGET_REG_BITS == 64) {
- new_pool_l2(s, rel, s->code_ptr, add, val, val);
- } else {
- new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
- }
- }
-
- if (USE_REG_TB) {
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
- load_insn |= RA(TCG_REG_TB);
- } else {
- tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
- }
- tcg_out32(s, load_insn);
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long arg)
-{
- switch (type) {
- case TCG_TYPE_I32:
- case TCG_TYPE_I64:
- tcg_debug_assert(ret < TCG_REG_V0);
- tcg_out_movi_int(s, type, ret, arg, false);
- break;
-
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- tcg_debug_assert(ret >= TCG_REG_V0);
- tcg_out_dupi_vec(s, type, ret, arg);
- break;
-
- default:
- g_assert_not_reached();
- }
-}
-
-static bool mask_operand(uint32_t c, int *mb, int *me)
-{
- uint32_t lsb, test;
-
- /* Accept a bit pattern like:
- 0....01....1
- 1....10....0
- 0..01..10..0
- Keep track of the transitions. */
- if (c == 0 || c == -1) {
- return false;
- }
- test = c;
- lsb = test & -test;
- test += lsb;
- if (test & (test - 1)) {
- return false;
- }
-
- *me = clz32(lsb);
- *mb = test ? clz32(test & -test) + 1 : 0;
- return true;
-}
-
-static bool mask64_operand(uint64_t c, int *mb, int *me)
-{
- uint64_t lsb;
-
- if (c == 0) {
- return false;
- }
-
- lsb = c & -c;
- /* Accept 1..10..0. */
- if (c == -lsb) {
- *mb = 0;
- *me = clz64(lsb);
- return true;
- }
- /* Accept 0..01..1. */
- if (lsb == 1 && (c & (c + 1)) == 0) {
- *mb = clz64(c + 1) + 1;
- *me = 63;
- return true;
- }
- return false;
-}
-
-static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
-{
- int mb, me;
-
- if (mask_operand(c, &mb, &me)) {
- tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
- } else if ((c & 0xffff) == c) {
- tcg_out32(s, ANDI | SAI(src, dst, c));
- return;
- } else if ((c & 0xffff0000) == c) {
- tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
- return;
- } else {
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
- tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
- }
-}
-
-static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
-{
- int mb, me;
-
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- if (mask64_operand(c, &mb, &me)) {
- if (mb == 0) {
- tcg_out_rld(s, RLDICR, dst, src, 0, me);
- } else {
- tcg_out_rld(s, RLDICL, dst, src, 0, mb);
- }
- } else if ((c & 0xffff) == c) {
- tcg_out32(s, ANDI | SAI(src, dst, c));
- return;
- } else if ((c & 0xffff0000) == c) {
- tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
- return;
- } else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
- tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
- }
-}
-
-static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
- int op_lo, int op_hi)
-{
- if (c >> 16) {
- tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
- src = dst;
- }
- if (c & 0xffff) {
- tcg_out32(s, op_lo | SAI(src, dst, c));
- src = dst;
- }
-}
-
-static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
-{
- tcg_out_zori32(s, dst, src, c, ORI, ORIS);
-}
-
-static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
-{
- tcg_out_zori32(s, dst, src, c, XORI, XORIS);
-}
-
-static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
-{
- ptrdiff_t disp = tcg_pcrel_diff(s, target);
- if (in_range_b(disp)) {
- tcg_out32(s, B | (disp & 0x3fffffc) | mask);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
- tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
- tcg_out32(s, BCCTR | BO_ALWAYS | mask);
- }
-}
-
-static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
- TCGReg base, tcg_target_long offset)
-{
- tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
- bool is_int_store = false;
- TCGReg rs = TCG_REG_TMP1;
-
- switch (opi) {
- case LD: case LWA:
- align = 3;
- /* FALLTHRU */
- default:
- if (rt > TCG_REG_R0 && rt < TCG_REG_V0) {
- rs = rt;
- break;
- }
- break;
- case LXSD:
- case STXSD:
- align = 3;
- break;
- case LXV:
- case STXV:
- align = 15;
- break;
- case STD:
- align = 3;
- /* FALLTHRU */
- case STB: case STH: case STW:
- is_int_store = true;
- break;
- }
-
- /* For unaligned, or very large offsets, use the indexed form. */
- if (offset & align || offset != (int32_t)offset || opi == 0) {
- if (rs == base) {
- rs = TCG_REG_R0;
- }
- tcg_debug_assert(!is_int_store || rs != rt);
- tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
- tcg_out32(s, opx | TAB(rt & 31, base, rs));
- return;
- }
-
- l0 = (int16_t)offset;
- offset = (offset - l0) >> 16;
- l1 = (int16_t)offset;
-
- if (l1 < 0 && orig >= 0) {
- extra = 0x4000;
- l1 = (int16_t)(offset - 0x4000);
- }
- if (l1) {
- tcg_out32(s, ADDIS | TAI(rs, base, l1));
- base = rs;
- }
- if (extra) {
- tcg_out32(s, ADDIS | TAI(rs, base, extra));
- base = rs;
- }
- if (opi != ADDI || base != rt || l0 != 0) {
- tcg_out32(s, opi | TAI(rt & 31, base, l0));
- }
-}
-
-static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
- TCGReg va, TCGReg vb, int shb)
-{
- tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
-}
-
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg base, intptr_t offset)
-{
- int shift;
-
- switch (type) {
- case TCG_TYPE_I32:
- if (ret < TCG_REG_V0) {
- tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
- break;
- }
- if (have_isa_2_07 && have_vsx) {
- tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset);
- break;
- }
- tcg_debug_assert((offset & 3) == 0);
- tcg_out_mem_long(s, 0, LVEWX, ret, base, offset);
- shift = (offset - 4) & 0xc;
- if (shift) {
- tcg_out_vsldoi(s, ret, ret, ret, shift);
- }
- break;
- case TCG_TYPE_I64:
- if (ret < TCG_REG_V0) {
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- tcg_out_mem_long(s, LD, LDX, ret, base, offset);
- break;
- }
- /* fallthru */
- case TCG_TYPE_V64:
- tcg_debug_assert(ret >= TCG_REG_V0);
- if (have_vsx) {
- tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX,
- ret, base, offset);
- break;
- }
- tcg_debug_assert((offset & 7) == 0);
- tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
- if (offset & 8) {
- tcg_out_vsldoi(s, ret, ret, ret, 8);
- }
- break;
- case TCG_TYPE_V128:
- tcg_debug_assert(ret >= TCG_REG_V0);
- tcg_debug_assert((offset & 15) == 0);
- tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0,
- LVX, ret, base, offset);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg base, intptr_t offset)
-{
- int shift;
-
- switch (type) {
- case TCG_TYPE_I32:
- if (arg < TCG_REG_V0) {
- tcg_out_mem_long(s, STW, STWX, arg, base, offset);
- break;
- }
- if (have_isa_2_07 && have_vsx) {
- tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset);
- break;
- }
- assert((offset & 3) == 0);
- tcg_debug_assert((offset & 3) == 0);
- shift = (offset - 4) & 0xc;
- if (shift) {
- tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
- arg = TCG_VEC_TMP1;
- }
- tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
- break;
- case TCG_TYPE_I64:
- if (arg < TCG_REG_V0) {
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- tcg_out_mem_long(s, STD, STDX, arg, base, offset);
- break;
- }
- /* fallthru */
- case TCG_TYPE_V64:
- tcg_debug_assert(arg >= TCG_REG_V0);
- if (have_vsx) {
- tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0,
- STXSDX, arg, base, offset);
- break;
- }
- tcg_debug_assert((offset & 7) == 0);
- if (offset & 8) {
- tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
- arg = TCG_VEC_TMP1;
- }
- tcg_out_mem_long(s, 0, STVEWX, arg, base, offset);
- tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4);
- break;
- case TCG_TYPE_V128:
- tcg_debug_assert(arg >= TCG_REG_V0);
- tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0,
- STVX, arg, base, offset);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- return false;
-}
-
-static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
- int const_arg2, int cr, TCGType type)
-{
- int imm;
- uint32_t op;
-
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-
- /* Simplify the comparisons below wrt CMPI. */
- if (type == TCG_TYPE_I32) {
- arg2 = (int32_t)arg2;
- }
-
- switch (cond) {
- case TCG_COND_EQ:
- case TCG_COND_NE:
- if (const_arg2) {
- if ((int16_t) arg2 == arg2) {
- op = CMPI;
- imm = 1;
- break;
- } else if ((uint16_t) arg2 == arg2) {
- op = CMPLI;
- imm = 1;
- break;
- }
- }
- op = CMPL;
- imm = 0;
- break;
-
- case TCG_COND_LT:
- case TCG_COND_GE:
- case TCG_COND_LE:
- case TCG_COND_GT:
- if (const_arg2) {
- if ((int16_t) arg2 == arg2) {
- op = CMPI;
- imm = 1;
- break;
- }
- }
- op = CMP;
- imm = 0;
- break;
-
- case TCG_COND_LTU:
- case TCG_COND_GEU:
- case TCG_COND_LEU:
- case TCG_COND_GTU:
- if (const_arg2) {
- if ((uint16_t) arg2 == arg2) {
- op = CMPLI;
- imm = 1;
- break;
- }
- }
- op = CMPL;
- imm = 0;
- break;
-
- default:
- tcg_abort();
- }
- op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
-
- if (imm) {
- tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
- } else {
- if (const_arg2) {
- tcg_out_movi(s, type, TCG_REG_R0, arg2);
- arg2 = TCG_REG_R0;
- }
- tcg_out32(s, op | RA(arg1) | RB(arg2));
- }
-}
-
-static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
- TCGReg dst, TCGReg src)
-{
- if (type == TCG_TYPE_I32) {
- tcg_out32(s, CNTLZW | RS(src) | RA(dst));
- tcg_out_shri32(s, dst, dst, 5);
- } else {
- tcg_out32(s, CNTLZD | RS(src) | RA(dst));
- tcg_out_shri64(s, dst, dst, 6);
- }
-}
-
-static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
-{
- /* X != 0 implies X + -1 generates a carry. Extra addition
- trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
- if (dst != src) {
- tcg_out32(s, ADDIC | TAI(dst, src, -1));
- tcg_out32(s, SUBFE | TAB(dst, dst, src));
- } else {
- tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
- tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
- }
-}
-
-static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
- bool const_arg2)
-{
- if (const_arg2) {
- if ((uint32_t)arg2 == arg2) {
- tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
- } else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
- tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
- }
- } else {
- tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
- }
- return TCG_REG_R0;
-}
-
-static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
- TCGArg arg0, TCGArg arg1, TCGArg arg2,
- int const_arg2)
-{
- int crop, sh;
-
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-
- /* Ignore high bits of a potential constant arg2. */
- if (type == TCG_TYPE_I32) {
- arg2 = (uint32_t)arg2;
- }
-
- /* Handle common and trivial cases before handling anything else. */
- if (arg2 == 0) {
- switch (cond) {
- case TCG_COND_EQ:
- tcg_out_setcond_eq0(s, type, arg0, arg1);
- return;
- case TCG_COND_NE:
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
- tcg_out_ext32u(s, TCG_REG_R0, arg1);
- arg1 = TCG_REG_R0;
- }
- tcg_out_setcond_ne0(s, arg0, arg1);
- return;
- case TCG_COND_GE:
- tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
- arg1 = arg0;
- /* FALLTHRU */
- case TCG_COND_LT:
- /* Extract the sign bit. */
- if (type == TCG_TYPE_I32) {
- tcg_out_shri32(s, arg0, arg1, 31);
- } else {
- tcg_out_shri64(s, arg0, arg1, 63);
- }
- return;
- default:
- break;
- }
- }
-
- /* If we have ISEL, we can implement everything with 3 or 4 insns.
- All other cases below are also at least 3 insns, so speed up the
- code generator by not considering them and always using ISEL. */
- if (have_isel) {
- int isel, tab;
-
- tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
-
- isel = tcg_to_isel[cond];
-
- tcg_out_movi(s, type, arg0, 1);
- if (isel & 1) {
- /* arg0 = (bc ? 0 : 1) */
- tab = TAB(arg0, 0, arg0);
- isel &= ~1;
- } else {
- /* arg0 = (bc ? 1 : 0) */
- tcg_out_movi(s, type, TCG_REG_R0, 0);
- tab = TAB(arg0, arg0, TCG_REG_R0);
- }
- tcg_out32(s, isel | tab);
- return;
- }
-
- switch (cond) {
- case TCG_COND_EQ:
- arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
- tcg_out_setcond_eq0(s, type, arg0, arg1);
- return;
-
- case TCG_COND_NE:
- arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
- /* Discard the high bits only once, rather than both inputs. */
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
- tcg_out_ext32u(s, TCG_REG_R0, arg1);
- arg1 = TCG_REG_R0;
- }
- tcg_out_setcond_ne0(s, arg0, arg1);
- return;
-
- case TCG_COND_GT:
- case TCG_COND_GTU:
- sh = 30;
- crop = 0;
- goto crtest;
-
- case TCG_COND_LT:
- case TCG_COND_LTU:
- sh = 29;
- crop = 0;
- goto crtest;
-
- case TCG_COND_GE:
- case TCG_COND_GEU:
- sh = 31;
- crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
- goto crtest;
-
- case TCG_COND_LE:
- case TCG_COND_LEU:
- sh = 31;
- crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
- crtest:
- tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
- if (crop) {
- tcg_out32(s, crop);
- }
- tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
- tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
- break;
-
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
-{
- if (l->has_value) {
- bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr);
- } else {
- tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
- }
- tcg_out32(s, bc);
-}
-
-static void tcg_out_brcond(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- TCGLabel *l, TCGType type)
-{
- tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
- tcg_out_bc(s, tcg_to_bc[cond], l);
-}
-
-static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
- TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
- TCGArg v2, bool const_c2)
-{
- /* If for some reason both inputs are zero, don't produce bad code. */
- if (v1 == 0 && v2 == 0) {
- tcg_out_movi(s, type, dest, 0);
- return;
- }
-
- tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
-
- if (have_isel) {
- int isel = tcg_to_isel[cond];
-
- /* Swap the V operands if the operation indicates inversion. */
- if (isel & 1) {
- int t = v1;
- v1 = v2;
- v2 = t;
- isel &= ~1;
- }
- /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
- if (v2 == 0) {
- tcg_out_movi(s, type, TCG_REG_R0, 0);
- }
- tcg_out32(s, isel | TAB(dest, v1, v2));
- } else {
- if (dest == v2) {
- cond = tcg_invert_cond(cond);
- v2 = v1;
- } else if (dest != v1) {
- if (v1 == 0) {
- tcg_out_movi(s, type, dest, 0);
- } else {
- tcg_out_mov(s, type, dest, v1);
- }
- }
- /* Branch forward over one insn */
- tcg_out32(s, tcg_to_bc[cond] | 8);
- if (v2 == 0) {
- tcg_out_movi(s, type, dest, 0);
- } else {
- tcg_out_mov(s, type, dest, v2);
- }
- }
-}
-
-static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
- TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
-{
- if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
- tcg_out32(s, opc | RA(a0) | RS(a1));
- } else {
- tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
- /* Note that the only other valid constant for a2 is 0. */
- if (have_isel) {
- tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
- tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
- } else if (!const_a2 && a0 == a2) {
- tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
- tcg_out32(s, opc | RA(a0) | RS(a1));
- } else {
- tcg_out32(s, opc | RA(a0) | RS(a1));
- tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
- if (const_a2) {
- tcg_out_movi(s, type, a0, 0);
- } else {
- tcg_out_mov(s, type, a0, a2);
- }
- }
- }
-}
-
-static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
- const int *const_args)
-{
- static const struct { uint8_t bit1, bit2; } bits[] = {
- [TCG_COND_LT ] = { CR_LT, CR_LT },
- [TCG_COND_LE ] = { CR_LT, CR_GT },
- [TCG_COND_GT ] = { CR_GT, CR_GT },
- [TCG_COND_GE ] = { CR_GT, CR_LT },
- [TCG_COND_LTU] = { CR_LT, CR_LT },
- [TCG_COND_LEU] = { CR_LT, CR_GT },
- [TCG_COND_GTU] = { CR_GT, CR_GT },
- [TCG_COND_GEU] = { CR_GT, CR_LT },
- };
-
- TCGCond cond = args[4], cond2;
- TCGArg al, ah, bl, bh;
- int blconst, bhconst;
- int op, bit1, bit2;
-
- al = args[0];
- ah = args[1];
- bl = args[2];
- bh = args[3];
- blconst = const_args[2];
- bhconst = const_args[3];
-
- switch (cond) {
- case TCG_COND_EQ:
- op = CRAND;
- goto do_equality;
- case TCG_COND_NE:
- op = CRNAND;
- do_equality:
- tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
- tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
- tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
- break;
-
- case TCG_COND_LT:
- case TCG_COND_LE:
- case TCG_COND_GT:
- case TCG_COND_GE:
- case TCG_COND_LTU:
- case TCG_COND_LEU:
- case TCG_COND_GTU:
- case TCG_COND_GEU:
- bit1 = bits[cond].bit1;
- bit2 = bits[cond].bit2;
- op = (bit1 != bit2 ? CRANDC : CRAND);
- cond2 = tcg_unsigned_cond(cond);
-
- tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
- tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
- tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
- tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
- break;
-
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
- const int *const_args)
-{
- tcg_out_cmp2(s, args + 1, const_args + 1);
- tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
- tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
-}
-
-static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
- const int *const_args)
-{
- tcg_out_cmp2(s, args, const_args);
- tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
-}
-
-static void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- uint32_t insn = HWSYNC;
- a0 &= TCG_MO_ALL;
- if (a0 == TCG_MO_LD_LD) {
- insn = LWSYNC;
- } else if (a0 == TCG_MO_ST_ST) {
- insn = EIEIO;
- }
- tcg_out32(s, insn);
-}
-
-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
- uintptr_t addr)
-{
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_insn_unit i1, i2;
- intptr_t tb_diff = addr - tc_ptr;
- intptr_t br_diff = addr - (jmp_addr + 4);
- uint64_t pair;
-
- /* This does not exercise the range of the branch, but we do
- still need to be able to load the new value of TCG_REG_TB.
- But this does still happen quite often. */
- if (tb_diff == (int16_t)tb_diff) {
- i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
- i2 = B | (br_diff & 0x3fffffc);
- } else {
- intptr_t lo = (int16_t)tb_diff;
- intptr_t hi = (int32_t)(tb_diff - lo);
- assert(tb_diff == hi + lo);
- i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
- i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
- }
-#ifdef HOST_WORDS_BIGENDIAN
- pair = (uint64_t)i1 << 32 | i2;
-#else
- pair = (uint64_t)i2 << 32 | i1;
-#endif
-
- /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
- within atomic_set that would fail to build a ppc32 host. */
- atomic_set__nocheck((uint64_t *)jmp_addr, pair);
- flush_icache_range(jmp_addr, jmp_addr + 8);
- } else {
- intptr_t diff = addr - jmp_addr;
- tcg_debug_assert(in_range_b(diff));
- atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
- flush_icache_range(jmp_addr, jmp_addr + 4);
- }
-}
-
-static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
-{
-#ifdef _CALL_AIX
- /* Look through the descriptor. If the branch is in range, and we
- don't have to spend too much effort on building the toc. */
- void *tgt = ((void **)target)[0];
- uintptr_t toc = ((uintptr_t *)target)[1];
- intptr_t diff = tcg_pcrel_diff(s, tgt);
-
- if (in_range_b(diff) && toc == (uint32_t)toc) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
- tcg_out_b(s, LK, tgt);
- } else {
- /* Fold the low bits of the constant into the addresses below. */
- intptr_t arg = (intptr_t)target;
- int ofs = (int16_t)arg;
-
- if (ofs + 8 < 0x8000) {
- arg -= ofs;
- } else {
- ofs = 0;
- }
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
- tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
- tcg_out32(s, BCCTR | BO_ALWAYS | LK);
- }
-#elif defined(_CALL_ELF) && _CALL_ELF == 2
- intptr_t diff;
-
- /* In the ELFv2 ABI, we have to set up r12 to contain the destination
- address, which the callee uses to compute its TOC address. */
- /* FIXME: when the branch is in range, we could avoid r12 load if we
- knew that the destination uses the same TOC, and what its local
- entry point offset is. */
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
-
- diff = tcg_pcrel_diff(s, target);
- if (in_range_b(diff)) {
- tcg_out_b(s, LK, target);
- } else {
- tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
- tcg_out32(s, BCCTR | BO_ALWAYS | LK);
- }
-#else
- tcg_out_b(s, LK, target);
-#endif
-}
-
-static const uint32_t qemu_ldx_opc[16] = {
- [MO_UB] = LBZX,
- [MO_UW] = LHZX,
- [MO_UL] = LWZX,
- [MO_Q] = LDX,
- [MO_SW] = LHAX,
- [MO_SL] = LWAX,
- [MO_BSWAP | MO_UB] = LBZX,
- [MO_BSWAP | MO_UW] = LHBRX,
- [MO_BSWAP | MO_UL] = LWBRX,
- [MO_BSWAP | MO_Q] = LDBRX,
-};
-
-static const uint32_t qemu_stx_opc[16] = {
- [MO_UB] = STBX,
- [MO_UW] = STHX,
- [MO_UL] = STWX,
- [MO_Q] = STDX,
- [MO_BSWAP | MO_UB] = STBX,
- [MO_BSWAP | MO_UW] = STHBRX,
- [MO_BSWAP | MO_UL] = STWBRX,
- [MO_BSWAP | MO_Q] = STDBRX,
-};
-
-static const uint32_t qemu_exts_opc[4] = {
- EXTSB, EXTSH, EXTSW, 0
-};
-
-#if defined (CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
-
-/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
- * int mmu_idx, uintptr_t ra)
- */
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
-};
-
-/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, int mmu_idx, uintptr_t ra)
- */
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-
-/* We expect to use a 16-bit negative offset from ENV. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
-
-/* Perform the TLB load and compare. Places the result of the comparison
- in CR7, loads the addend of the TLB into R3, and returns the register
- containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
-
-static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
- TCGReg addrlo, TCGReg addrhi,
- int mem_index, bool is_read)
-{
- int cmp_off
- = (is_read
- ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write));
- int fast_off = TLB_MASK_TABLE_OFS(mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
-
- /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
-
- /* Extract the page index, shifted into place for tlb index. */
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- } else {
- tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- }
- tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
-
- /* Load the TLB comparator. */
- if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
- uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
- ? LWZUX : LDUX);
- tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
- } else {
- tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
- } else {
- tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
- }
- }
-
- /* Load the TLB addend for use on the fast path. Do this asap
- to minimize any load use delay. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
- offsetof(CPUTLBEntry, addend));
-
- /* Clear the non-page, non-alignment bits from the address */
- if (TCG_TARGET_REG_BITS == 32) {
- /* We don't support unaligned accesses on 32-bits.
- * Preserve the bottom bits and thus trigger a comparison
- * failure on unaligned accesses.
- */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
- (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
- } else {
- TCGReg t = addrlo;
-
- /* If the access is unaligned, we need to make sure we fail if we
- * cross a page boundary. The trick is to add the access size-1
- * to the address before masking the low bits. That will make the
- * address overflow to the next page if we cross a page boundary,
- * which will then force a mismatch of the TLB compare.
- */
- if (a_bits < s_bits) {
- unsigned a_mask = (1 << a_bits) - 1;
- unsigned s_mask = (1 << s_bits) - 1;
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
- t = TCG_REG_R0;
- }
-
- /* Mask the address for the requested alignment. */
- if (TARGET_LONG_BITS == 32) {
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
- (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
- /* Zero-extend the address for use in the final address. */
- tcg_out_ext32u(s, TCG_REG_R4, addrlo);
- addrlo = TCG_REG_R4;
- } else if (a_bits == 0) {
- tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
- } else {
- tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
- 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
- tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
- }
- }
-
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
- 0, 7, TCG_TYPE_I32);
- tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
- tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
- } else {
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
- 0, 7, TCG_TYPE_TL);
- }
-
- return addrlo;
-}
-
-/* Record the context of a call to the out of line helper code for the slow
- path for a load or store, so that we can later generate the correct
- helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
- TCGReg datalo_reg, TCGReg datahi_reg,
- TCGReg addrlo_reg, TCGReg addrhi_reg,
- tcg_insn_unit *raddr, tcg_insn_unit *lptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->datalo_reg = datalo_reg;
- label->datahi_reg = datahi_reg;
- label->addrlo_reg = addrlo_reg;
- label->addrhi_reg = addrhi_reg;
- label->raddr = raddr;
- label->label_ptr[0] = lptr;
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- TCGReg hi, lo, arg = TCG_REG_R3;
-
- if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
-
- lo = lb->addrlo_reg;
- hi = lb->addrhi_reg;
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-#ifdef TCG_TARGET_CALL_ALIGN_ARGS
- arg |= 1;
-#endif
- tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
- } else {
- /* If the address needed to be zero-extended, we'll have already
- placed it in R4. The only remaining case is 64-bit guest. */
- tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
- }
-
- tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
- tcg_out32(s, MFSPR | RT(arg) | LR);
-
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
-
- lo = lb->datalo_reg;
- hi = lb->datahi_reg;
- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
- tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
- tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
- } else if (opc & MO_SIGN) {
- uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
- tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
- } else {
- tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
- }
-
- tcg_out_b(s, 0, lb->raddr);
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- MemOp s_bits = opc & MO_SIZE;
- TCGReg hi, lo, arg = TCG_REG_R3;
-
- if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
-
- lo = lb->addrlo_reg;
- hi = lb->addrhi_reg;
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-#ifdef TCG_TARGET_CALL_ALIGN_ARGS
- arg |= 1;
-#endif
- tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
- } else {
- /* If the address needed to be zero-extended, we'll have already
- placed it in R4. The only remaining case is 64-bit guest. */
- tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
- }
-
- lo = lb->datalo_reg;
- hi = lb->datahi_reg;
- if (TCG_TARGET_REG_BITS == 32) {
- switch (s_bits) {
- case MO_64:
-#ifdef TCG_TARGET_CALL_ALIGN_ARGS
- arg |= 1;
-#endif
- tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
- /* FALLTHRU */
- case MO_32:
- tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
- break;
- default:
- tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
- break;
- }
- } else {
- if (s_bits == MO_64) {
- tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
- } else {
- tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
- }
- }
-
- tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
- tcg_out32(s, MFSPR | RT(arg) | LR);
-
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
-
- tcg_out_b(s, 0, lb->raddr);
- return true;
-}
-#endif /* SOFTMMU */
-
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
-{
- TCGReg datalo, datahi, addrlo, rbase;
- TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
- MemOp opc, s_bits;
-#ifdef CONFIG_SOFTMMU
- int mem_index;
- tcg_insn_unit *label_ptr;
-#endif
-
- datalo = *args++;
- datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
- s_bits = opc & MO_SIZE;
-
-#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
-
- /* Load a pointer into the current opcode w/conditional branch-link. */
- label_ptr = s->code_ptr;
- tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
-
- rbase = TCG_REG_R3;
-#else /* !CONFIG_SOFTMMU */
- rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
- addrlo = TCG_REG_TMP1;
- }
-#endif
-
- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
- if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
- tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
- } else if (rbase != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
- tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
- } else if (addrlo == datahi) {
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
- } else {
- tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
- tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
- }
- } else {
- uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
- if (!have_isa_2_06 && insn == LDBRX) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
- tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
- tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
- } else if (insn) {
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
- } else {
- insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
- tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
- insn = qemu_exts_opc[s_bits];
- tcg_out32(s, insn | RA(datalo) | RS(datalo));
- }
- }
-
-#ifdef CONFIG_SOFTMMU
- add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
-#endif
-}
-
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
-{
- TCGReg datalo, datahi, addrlo, rbase;
- TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
- MemOp opc, s_bits;
-#ifdef CONFIG_SOFTMMU
- int mem_index;
- tcg_insn_unit *label_ptr;
-#endif
-
- datalo = *args++;
- datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
- s_bits = opc & MO_SIZE;
-
-#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
-
- /* Load a pointer into the current opcode w/conditional branch-link. */
- label_ptr = s->code_ptr;
- tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
-
- rbase = TCG_REG_R3;
-#else /* !CONFIG_SOFTMMU */
- rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
- addrlo = TCG_REG_TMP1;
- }
-#endif
-
- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
- if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
- tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
- } else if (rbase != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
- tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
- tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
- } else {
- tcg_out32(s, STW | TAI(datahi, addrlo, 0));
- tcg_out32(s, STW | TAI(datalo, addrlo, 4));
- }
- } else {
- uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
- if (!have_isa_2_06 && insn == STDBRX) {
- tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
- tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
- tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
- } else {
- tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
- }
- }
-
-#ifdef CONFIG_SOFTMMU
- add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
-#endif
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- int i;
- for (i = 0; i < count; ++i) {
- p[i] = NOP;
- }
-}
-
-/* Parameters for function call generation, used in tcg.c. */
-#define TCG_TARGET_STACK_ALIGN 16
-#define TCG_TARGET_EXTEND_ARGS 1
-
-#ifdef _CALL_AIX
-# define LINK_AREA_SIZE (6 * SZR)
-# define LR_OFFSET (1 * SZR)
-# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
-#elif defined(TCG_TARGET_CALL_DARWIN)
-# define LINK_AREA_SIZE (6 * SZR)
-# define LR_OFFSET (2 * SZR)
-#elif TCG_TARGET_REG_BITS == 64
-# if defined(_CALL_ELF) && _CALL_ELF == 2
-# define LINK_AREA_SIZE (4 * SZR)
-# define LR_OFFSET (1 * SZR)
-# endif
-#else /* TCG_TARGET_REG_BITS == 32 */
-# if defined(_CALL_SYSV)
-# define LINK_AREA_SIZE (2 * SZR)
-# define LR_OFFSET (1 * SZR)
-# endif
-#endif
-#ifndef LR_OFFSET
-# error "Unhandled abi"
-#endif
-#ifndef TCG_TARGET_CALL_STACK_OFFSET
-# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
-#endif
-
-#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
-#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
-
-#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
- + TCG_STATIC_CALL_ARGS_SIZE \
- + CPU_TEMP_BUF_SIZE \
- + REG_SAVE_SIZE \
- + TCG_TARGET_STACK_ALIGN - 1) \
- & -TCG_TARGET_STACK_ALIGN)
-
-#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
-
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- int i;
-
-#ifdef _CALL_AIX
- void **desc = (void **)s->code_ptr;
- desc[0] = desc + 2; /* entry point */
- desc[1] = 0; /* environment pointer */
- s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
-#endif
-
- tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
- CPU_TEMP_BUF_SIZE);
-
- /* Prologue */
- tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
- tcg_out32(s, (SZR == 8 ? STDU : STWU)
- | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
-
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
- tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
- TCG_REG_R1, REG_SAVE_BOT + i * SZR);
- }
- tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
-
-#ifndef CONFIG_SOFTMMU
- if (guest_base) {
- tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
- tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
- }
-#endif
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
- if (USE_REG_TB) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
- }
- tcg_out32(s, BCCTR | BO_ALWAYS);
-
- /* Epilogue */
- s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
-
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
- tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
- TCG_REG_R1, REG_SAVE_BOT + i * SZR);
- }
- tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
- tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
- tcg_out32(s, BCLR | BO_ALWAYS);
-}
-
-static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
- const int *const_args)
-{
- TCGArg a0, a1, a2;
- int c;
-
- switch (opc) {
- case INDEX_op_exit_tb:
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
- tcg_out_b(s, 0, tb_ret_addr);
- break;
- case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* Direct jump. */
- if (TCG_TARGET_REG_BITS == 64) {
- /* Ensure the next insns are 8-byte aligned. */
- if ((uintptr_t)s->code_ptr & 7) {
- tcg_out32(s, NOP);
- }
- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
- tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
- tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
- } else {
- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
- tcg_out32(s, B);
- s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
- break;
- }
- } else {
- /* Indirect jump. */
- tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
- (intptr_t)(s->tb_jmp_insn_offset + args[0]));
- }
- tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
- tcg_out32(s, BCCTR | BO_ALWAYS);
- set_jmp_reset_offset(s, args[0]);
- if (USE_REG_TB) {
- /* For the unlinked case, need to reset TCG_REG_TB. */
- c = -tcg_current_code_size(s);
- assert(c == (int16_t)c);
- tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
- }
- break;
- case INDEX_op_goto_ptr:
- tcg_out32(s, MTSPR | RS(args[0]) | CTR);
- if (USE_REG_TB) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
- }
- tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
- tcg_out32(s, BCCTR | BO_ALWAYS);
- break;
- case INDEX_op_br:
- {
- TCGLabel *l = arg_label(args[0]);
- uint32_t insn = B;
-
- if (l->has_value) {
- insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr);
- } else {
- tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
- }
- tcg_out32(s, insn);
- }
- break;
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld8s_i64:
- tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
- tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
- break;
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld16s_i64:
- tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld32s_i64:
- tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld_i64:
- tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i64:
- tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_add_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- do_addi_32:
- tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
- } else {
- tcg_out32(s, ADD | TAB(a0, a1, a2));
- }
- break;
- case INDEX_op_sub_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[1]) {
- if (const_args[2]) {
- tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
- } else {
- tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
- }
- } else if (const_args[2]) {
- a2 = -a2;
- goto do_addi_32;
- } else {
- tcg_out32(s, SUBF | TAB(a0, a2, a1));
- }
- break;
-
- case INDEX_op_and_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_andi32(s, a0, a1, a2);
- } else {
- tcg_out32(s, AND | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_and_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_andi64(s, a0, a1, a2);
- } else {
- tcg_out32(s, AND | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_or_i64:
- case INDEX_op_or_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_ori32(s, a0, a1, a2);
- } else {
- tcg_out32(s, OR | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_xor_i64:
- case INDEX_op_xor_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_xori32(s, a0, a1, a2);
- } else {
- tcg_out32(s, XOR | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_andc_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_andi32(s, a0, a1, ~a2);
- } else {
- tcg_out32(s, ANDC | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_andc_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_andi64(s, a0, a1, ~a2);
- } else {
- tcg_out32(s, ANDC | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_orc_i32:
- if (const_args[2]) {
- tcg_out_ori32(s, args[0], args[1], ~args[2]);
- break;
- }
- /* FALLTHRU */
- case INDEX_op_orc_i64:
- tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
- break;
- case INDEX_op_eqv_i32:
- if (const_args[2]) {
- tcg_out_xori32(s, args[0], args[1], ~args[2]);
- break;
- }
- /* FALLTHRU */
- case INDEX_op_eqv_i64:
- tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
- break;
- case INDEX_op_nand_i32:
- case INDEX_op_nand_i64:
- tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
- break;
- case INDEX_op_nor_i32:
- case INDEX_op_nor_i64:
- tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
- break;
-
- case INDEX_op_clz_i32:
- tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_ctz_i32:
- tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_ctpop_i32:
- tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
- break;
-
- case INDEX_op_clz_i64:
- tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_ctz_i64:
- tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_ctpop_i64:
- tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
- break;
-
- case INDEX_op_mul_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out32(s, MULLI | TAI(a0, a1, a2));
- } else {
- tcg_out32(s, MULLW | TAB(a0, a1, a2));
- }
- break;
-
- case INDEX_op_div_i32:
- tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
- break;
-
- case INDEX_op_divu_i32:
- tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
- break;
-
- case INDEX_op_shl_i32:
- if (const_args[2]) {
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out_shli32(s, args[0], args[1], args[2] & 31);
- } else {
- tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
- }
- break;
- case INDEX_op_shr_i32:
- if (const_args[2]) {
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out_shri32(s, args[0], args[1], args[2] & 31);
- } else {
- tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
- }
- break;
- case INDEX_op_sar_i32:
- if (const_args[2]) {
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31));
- } else {
- tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
- }
- break;
- case INDEX_op_rotl_i32:
- if (const_args[2]) {
- tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
- } else {
- tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
- | MB(0) | ME(31));
- }
- break;
- case INDEX_op_rotr_i32:
- if (const_args[2]) {
- tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
- } else {
- tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
- tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
- | MB(0) | ME(31));
- }
- break;
-
- case INDEX_op_brcond_i32:
- tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
- arg_label(args[3]), TCG_TYPE_I32);
- break;
- case INDEX_op_brcond_i64:
- tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
- arg_label(args[3]), TCG_TYPE_I64);
- break;
- case INDEX_op_brcond2_i32:
- tcg_out_brcond2(s, args, const_args);
- break;
-
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
- tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
- break;
-
- case INDEX_op_not_i32:
- case INDEX_op_not_i64:
- tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
- break;
-
- case INDEX_op_add_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- do_addi_64:
- tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
- } else {
- tcg_out32(s, ADD | TAB(a0, a1, a2));
- }
- break;
- case INDEX_op_sub_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[1]) {
- if (const_args[2]) {
- tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
- } else {
- tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
- }
- } else if (const_args[2]) {
- a2 = -a2;
- goto do_addi_64;
- } else {
- tcg_out32(s, SUBF | TAB(a0, a2, a1));
- }
- break;
-
- case INDEX_op_shl_i64:
- if (const_args[2]) {
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out_shli64(s, args[0], args[1], args[2] & 63);
- } else {
- tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
- }
- break;
- case INDEX_op_shr_i64:
- if (const_args[2]) {
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out_shri64(s, args[0], args[1], args[2] & 63);
- } else {
- tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
- }
- break;
- case INDEX_op_sar_i64:
- if (const_args[2]) {
- int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
- tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
- } else {
- tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
- }
- break;
- case INDEX_op_rotl_i64:
- if (const_args[2]) {
- tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
- } else {
- tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
- }
- break;
- case INDEX_op_rotr_i64:
- if (const_args[2]) {
- tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
- } else {
- tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
- tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
- }
- break;
-
- case INDEX_op_mul_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out32(s, MULLI | TAI(a0, a1, a2));
- } else {
- tcg_out32(s, MULLD | TAB(a0, a1, a2));
- }
- break;
- case INDEX_op_div_i64:
- tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
- break;
- case INDEX_op_divu_i64:
- tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
- break;
-
- case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, false);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, true);
- break;
- case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, false);
- break;
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, true);
- break;
-
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- c = EXTSB;
- goto gen_ext;
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- c = EXTSH;
- goto gen_ext;
- case INDEX_op_ext_i32_i64:
- case INDEX_op_ext32s_i64:
- c = EXTSW;
- goto gen_ext;
- gen_ext:
- tcg_out32(s, c | RS(args[1]) | RA(args[0]));
- break;
- case INDEX_op_extu_i32_i64:
- tcg_out_ext32u(s, args[0], args[1]);
- break;
-
- case INDEX_op_setcond_i32:
- tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
- const_args[2]);
- break;
- case INDEX_op_setcond_i64:
- tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
- const_args[2]);
- break;
- case INDEX_op_setcond2_i32:
- tcg_out_setcond2(s, args, const_args);
- break;
-
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- a0 = args[0], a1 = args[1];
- /* a1 = abcd */
- if (a0 != a1) {
- /* a0 = (a1 r<< 24) & 0xff # 000c */
- tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
- /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
- tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
- } else {
- /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
- /* a0 = (a1 r<< 24) & 0xff # 000c */
- tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
- /* a0 = a0 | r0 # 00dc */
- tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
- }
- break;
-
- case INDEX_op_bswap32_i32:
- case INDEX_op_bswap32_i64:
- /* Stolen from gcc's builtin_bswap32 */
- a1 = args[1];
- a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
-
- /* a1 = args[1] # abcd */
- /* a0 = rotate_left (a1, 8) # bcda */
- tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
- /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
- /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
-
- if (a0 == TCG_REG_R0) {
- tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
- }
- break;
-
- case INDEX_op_bswap64_i64:
- a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
- if (a0 == a1) {
- a0 = TCG_REG_R0;
- a2 = a1;
- }
-
- /* a1 = # abcd efgh */
- /* a0 = rl32(a1, 8) # 0000 fghe */
- tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
- /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
- /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
-
- /* a0 = rl64(a0, 32) # hgfe 0000 */
- /* a2 = rl64(a1, 32) # efgh abcd */
- tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
- tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
-
- /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
- tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
- /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
- tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
- /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
- tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
-
- if (a0 == 0) {
- tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
- }
- break;
-
- case INDEX_op_deposit_i32:
- if (const_args[2]) {
- uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
- tcg_out_andi32(s, args[0], args[0], ~mask);
- } else {
- tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
- 32 - args[3] - args[4], 31 - args[3]);
- }
- break;
- case INDEX_op_deposit_i64:
- if (const_args[2]) {
- uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
- tcg_out_andi64(s, args[0], args[0], ~mask);
- } else {
- tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
- 64 - args[3] - args[4]);
- }
- break;
-
- case INDEX_op_extract_i32:
- tcg_out_rlw(s, RLWINM, args[0], args[1],
- 32 - args[2], 32 - args[3], 31);
- break;
- case INDEX_op_extract_i64:
- tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
- break;
-
- case INDEX_op_movcond_i32:
- tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
- args[3], args[4], const_args[2]);
- break;
- case INDEX_op_movcond_i64:
- tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
- args[3], args[4], const_args[2]);
- break;
-
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_add2_i64:
-#else
- case INDEX_op_add2_i32:
-#endif
- /* Note that the CA bit is defined based on the word size of the
- environment. So in 64-bit mode it's always carry-out of bit 63.
- The fallback code using deposit works just as well for 32-bit. */
- a0 = args[0], a1 = args[1];
- if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
- a0 = TCG_REG_R0;
- }
- if (const_args[4]) {
- tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
- } else {
- tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
- }
- if (const_args[5]) {
- tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
- } else {
- tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
- }
- if (a0 != args[0]) {
- tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
- }
- break;
-
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_sub2_i64:
-#else
- case INDEX_op_sub2_i32:
-#endif
- a0 = args[0], a1 = args[1];
- if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
- a0 = TCG_REG_R0;
- }
- if (const_args[2]) {
- tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
- } else {
- tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
- }
- if (const_args[3]) {
- tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
- } else {
- tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
- }
- if (a0 != args[0]) {
- tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
- }
- break;
-
- case INDEX_op_muluh_i32:
- tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
- break;
- case INDEX_op_mulsh_i32:
- tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
- break;
- case INDEX_op_muluh_i64:
- tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
- break;
- case INDEX_op_mulsh_i64:
- tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, args[0]);
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-}
-
-int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-{
- switch (opc) {
- case INDEX_op_and_vec:
- case INDEX_op_or_vec:
- case INDEX_op_xor_vec:
- case INDEX_op_andc_vec:
- case INDEX_op_not_vec:
- return 1;
- case INDEX_op_orc_vec:
- return have_isa_2_07;
- case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
- case INDEX_op_smax_vec:
- case INDEX_op_smin_vec:
- case INDEX_op_umax_vec:
- case INDEX_op_umin_vec:
- case INDEX_op_shlv_vec:
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
- case INDEX_op_rotlv_vec:
- return vece <= MO_32 || have_isa_2_07;
- case INDEX_op_ssadd_vec:
- case INDEX_op_sssub_vec:
- case INDEX_op_usadd_vec:
- case INDEX_op_ussub_vec:
- return vece <= MO_32;
- case INDEX_op_cmp_vec:
- case INDEX_op_shli_vec:
- case INDEX_op_shri_vec:
- case INDEX_op_sari_vec:
- case INDEX_op_rotli_vec:
- return vece <= MO_32 || have_isa_2_07 ? -1 : 0;
- case INDEX_op_neg_vec:
- return vece >= MO_32 && have_isa_3_00;
- case INDEX_op_mul_vec:
- switch (vece) {
- case MO_8:
- case MO_16:
- return -1;
- case MO_32:
- return have_isa_2_07 ? 1 : -1;
- }
- return 0;
- case INDEX_op_bitsel_vec:
- return have_vsx;
- case INDEX_op_rotrv_vec:
- return -1;
- default:
- return 0;
- }
-}
-
-static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
- TCGReg dst, TCGReg src)
-{
- tcg_debug_assert(dst >= TCG_REG_V0);
-
- /* Splat from integer reg allowed via constraints for v3.00. */
- if (src < TCG_REG_V0) {
- tcg_debug_assert(have_isa_3_00);
- switch (vece) {
- case MO_64:
- tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
- return true;
- case MO_32:
- tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
- return true;
- default:
- /* Fail, so that we fall back on either dupm or mov+dup. */
- return false;
- }
- }
-
- /*
- * Recall we use (or emulate) VSX integer loads, so the integer is
- * right justified within the left (zero-index) double-word.
- */
- switch (vece) {
- case MO_8:
- tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
- break;
- case MO_16:
- tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
- break;
- case MO_32:
- tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
- break;
- case MO_64:
- if (have_vsx) {
- tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
- break;
- }
- tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
- tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
- break;
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
- TCGReg out, TCGReg base, intptr_t offset)
-{
- int elt;
-
- tcg_debug_assert(out >= TCG_REG_V0);
- switch (vece) {
- case MO_8:
- if (have_isa_3_00) {
- tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16);
- } else {
- tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
- }
- elt = extract32(offset, 0, 4);
-#ifndef HOST_WORDS_BIGENDIAN
- elt ^= 15;
-#endif
- tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
- break;
- case MO_16:
- tcg_debug_assert((offset & 1) == 0);
- if (have_isa_3_00) {
- tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
- } else {
- tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
- }
- elt = extract32(offset, 1, 3);
-#ifndef HOST_WORDS_BIGENDIAN
- elt ^= 7;
-#endif
- tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
- break;
- case MO_32:
- if (have_isa_3_00) {
- tcg_out_mem_long(s, 0, LXVWSX, out, base, offset);
- break;
- }
- tcg_debug_assert((offset & 3) == 0);
- tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
- elt = extract32(offset, 2, 2);
-#ifndef HOST_WORDS_BIGENDIAN
- elt ^= 3;
-#endif
- tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
- break;
- case MO_64:
- if (have_vsx) {
- tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
- break;
- }
- tcg_debug_assert((offset & 7) == 0);
- tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
- tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
- elt = extract32(offset, 3, 1);
-#ifndef HOST_WORDS_BIGENDIAN
- elt = !elt;
-#endif
- if (elt) {
- tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
- } else {
- tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
- }
- break;
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
- unsigned vecl, unsigned vece,
- const TCGArg *args, const int *const_args)
-{
- static const uint32_t
- add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
- sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
- neg_op[4] = { 0, 0, VNEGW, VNEGD },
- eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
- ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
- gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
- gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
- ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
- usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
- sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
- ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
- umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
- smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
- umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
- smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
- shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
- shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
- sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
- mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
- mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
- muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
- mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
- pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
- rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
-
- TCGType type = vecl + TCG_TYPE_V64;
- TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
- uint32_t insn;
-
- switch (opc) {
- case INDEX_op_ld_vec:
- tcg_out_ld(s, type, a0, a1, a2);
- return;
- case INDEX_op_st_vec:
- tcg_out_st(s, type, a0, a1, a2);
- return;
- case INDEX_op_dupm_vec:
- tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
- return;
-
- case INDEX_op_add_vec:
- insn = add_op[vece];
- break;
- case INDEX_op_sub_vec:
- insn = sub_op[vece];
- break;
- case INDEX_op_neg_vec:
- insn = neg_op[vece];
- a2 = a1;
- a1 = 0;
- break;
- case INDEX_op_mul_vec:
- tcg_debug_assert(vece == MO_32 && have_isa_2_07);
- insn = VMULUWM;
- break;
- case INDEX_op_ssadd_vec:
- insn = ssadd_op[vece];
- break;
- case INDEX_op_sssub_vec:
- insn = sssub_op[vece];
- break;
- case INDEX_op_usadd_vec:
- insn = usadd_op[vece];
- break;
- case INDEX_op_ussub_vec:
- insn = ussub_op[vece];
- break;
- case INDEX_op_smin_vec:
- insn = smin_op[vece];
- break;
- case INDEX_op_umin_vec:
- insn = umin_op[vece];
- break;
- case INDEX_op_smax_vec:
- insn = smax_op[vece];
- break;
- case INDEX_op_umax_vec:
- insn = umax_op[vece];
- break;
- case INDEX_op_shlv_vec:
- insn = shlv_op[vece];
- break;
- case INDEX_op_shrv_vec:
- insn = shrv_op[vece];
- break;
- case INDEX_op_sarv_vec:
- insn = sarv_op[vece];
- break;
- case INDEX_op_and_vec:
- insn = VAND;
- break;
- case INDEX_op_or_vec:
- insn = VOR;
- break;
- case INDEX_op_xor_vec:
- insn = VXOR;
- break;
- case INDEX_op_andc_vec:
- insn = VANDC;
- break;
- case INDEX_op_not_vec:
- insn = VNOR;
- a2 = a1;
- break;
- case INDEX_op_orc_vec:
- insn = VORC;
- break;
-
- case INDEX_op_cmp_vec:
- switch (args[3]) {
- case TCG_COND_EQ:
- insn = eq_op[vece];
- break;
- case TCG_COND_NE:
- insn = ne_op[vece];
- break;
- case TCG_COND_GT:
- insn = gts_op[vece];
- break;
- case TCG_COND_GTU:
- insn = gtu_op[vece];
- break;
- default:
- g_assert_not_reached();
- }
- break;
-
- case INDEX_op_bitsel_vec:
- tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
- return;
-
- case INDEX_op_dup2_vec:
- assert(TCG_TARGET_REG_BITS == 32);
- /* With inputs a1 = xLxx, a2 = xHxx */
- tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
- tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
- tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
- return;
-
- case INDEX_op_ppc_mrgh_vec:
- insn = mrgh_op[vece];
- break;
- case INDEX_op_ppc_mrgl_vec:
- insn = mrgl_op[vece];
- break;
- case INDEX_op_ppc_muleu_vec:
- insn = muleu_op[vece];
- break;
- case INDEX_op_ppc_mulou_vec:
- insn = mulou_op[vece];
- break;
- case INDEX_op_ppc_pkum_vec:
- insn = pkum_op[vece];
- break;
- case INDEX_op_rotlv_vec:
- insn = rotl_op[vece];
- break;
- case INDEX_op_ppc_msum_vec:
- tcg_debug_assert(vece == MO_16);
- tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
- return;
-
- case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
- case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
- case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
- default:
- g_assert_not_reached();
- }
-
- tcg_debug_assert(insn != 0);
- tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
-}
-
-static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec v1, TCGArg imm, TCGOpcode opci)
-{
- TCGv_vec t1 = tcg_temp_new_vec(type);
-
- /* Splat w/bytes for xxspltib. */
- tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
- vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
- tcgv_vec_arg(v1), tcgv_vec_arg(t1));
- tcg_temp_free_vec(t1);
-}
-
-static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec v1, TCGv_vec v2, TCGCond cond)
-{
- bool need_swap = false, need_inv = false;
-
- tcg_debug_assert(vece <= MO_32 || have_isa_2_07);
-
- switch (cond) {
- case TCG_COND_EQ:
- case TCG_COND_GT:
- case TCG_COND_GTU:
- break;
- case TCG_COND_NE:
- if (have_isa_3_00 && vece <= MO_32) {
- break;
- }
- /* fall through */
- case TCG_COND_LE:
- case TCG_COND_LEU:
- need_inv = true;
- break;
- case TCG_COND_LT:
- case TCG_COND_LTU:
- need_swap = true;
- break;
- case TCG_COND_GE:
- case TCG_COND_GEU:
- need_swap = need_inv = true;
- break;
- default:
- g_assert_not_reached();
- }
-
- if (need_inv) {
- cond = tcg_invert_cond(cond);
- }
- if (need_swap) {
- TCGv_vec t1;
- t1 = v1, v1 = v2, v2 = t1;
- cond = tcg_swap_cond(cond);
- }
-
- vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
- tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
-
- if (need_inv) {
- tcg_gen_not_vec(vece, v0, v0);
- }
-}
-
-static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
- TCGv_vec v1, TCGv_vec v2)
-{
- TCGv_vec t1 = tcg_temp_new_vec(type);
- TCGv_vec t2 = tcg_temp_new_vec(type);
- TCGv_vec t3, t4;
-
- switch (vece) {
- case MO_8:
- case MO_16:
- vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
- tcgv_vec_arg(v1), tcgv_vec_arg(v2));
- vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
- tcgv_vec_arg(v1), tcgv_vec_arg(v2));
- vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
- tcgv_vec_arg(t1), tcgv_vec_arg(t2));
- vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
- tcgv_vec_arg(t1), tcgv_vec_arg(t2));
- vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
- tcgv_vec_arg(v0), tcgv_vec_arg(t1));
- break;
-
- case MO_32:
- tcg_debug_assert(!have_isa_2_07);
- t3 = tcg_temp_new_vec(type);
- t4 = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(MO_8, t4, -16);
- vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
- tcgv_vec_arg(v2), tcgv_vec_arg(t4));
- vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
- tcgv_vec_arg(v1), tcgv_vec_arg(v2));
- tcg_gen_dupi_vec(MO_8, t3, 0);
- vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3),
- tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
- vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3),
- tcgv_vec_arg(t3), tcgv_vec_arg(t4));
- tcg_gen_add_vec(MO_32, v0, t2, t3);
- tcg_temp_free_vec(t3);
- tcg_temp_free_vec(t4);
- break;
-
- default:
- g_assert_not_reached();
- }
- tcg_temp_free_vec(t1);
- tcg_temp_free_vec(t2);
-}
-
-void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
- TCGArg a0, ...)
-{
- va_list va;
- TCGv_vec v0, v1, v2, t0;
- TCGArg a2;
-
- va_start(va, a0);
- v0 = temp_tcgv_vec(arg_temp(a0));
- v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
- a2 = va_arg(va, TCGArg);
-
- switch (opc) {
- case INDEX_op_shli_vec:
- expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
- break;
- case INDEX_op_shri_vec:
- expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
- break;
- case INDEX_op_sari_vec:
- expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
- break;
- case INDEX_op_rotli_vec:
- expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec);
- break;
- case INDEX_op_cmp_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
- break;
- case INDEX_op_mul_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- expand_vec_mul(type, vece, v0, v1, v2);
- break;
- case INDEX_op_rotlv_vec:
- v2 = temp_tcgv_vec(arg_temp(a2));
- t0 = tcg_temp_new_vec(type);
- tcg_gen_neg_vec(vece, t0, v2);
- tcg_gen_rotlv_vec(vece, v0, v1, t0);
- tcg_temp_free_vec(t0);
- break;
- default:
- g_assert_not_reached();
- }
- va_end(va);
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
- static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
- static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
- static const TCGTargetOpDef r_rI_ri
- = { .args_ct_str = { "r", "rI", "ri" } };
- static const TCGTargetOpDef r_rI_rT
- = { .args_ct_str = { "r", "rI", "rT" } };
- static const TCGTargetOpDef r_r_rZW
- = { .args_ct_str = { "r", "r", "rZW" } };
- static const TCGTargetOpDef L_L_L_L
- = { .args_ct_str = { "L", "L", "L", "L" } };
- static const TCGTargetOpDef S_S_S_S
- = { .args_ct_str = { "S", "S", "S", "S" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
- static const TCGTargetOpDef sub2
- = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
- static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
- static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
- static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
- static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
- static const TCGTargetOpDef v_v_v_v
- = { .args_ct_str = { "v", "v", "v", "v" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_ctpop_i32:
- case INDEX_op_neg_i32:
- case INDEX_op_not_i32:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext16s_i32:
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap32_i32:
- case INDEX_op_extract_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- case INDEX_op_ctpop_i64:
- case INDEX_op_neg_i64:
- case INDEX_op_not_i64:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap64_i64:
- case INDEX_op_extract_i64:
- return &r_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_and_i32:
- case INDEX_op_or_i32:
- case INDEX_op_xor_i32:
- case INDEX_op_andc_i32:
- case INDEX_op_orc_i32:
- case INDEX_op_eqv_i32:
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_rotl_i32:
- case INDEX_op_rotr_i32:
- case INDEX_op_setcond_i32:
- case INDEX_op_and_i64:
- case INDEX_op_andc_i64:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i64:
- case INDEX_op_setcond_i64:
- return &r_r_ri;
- case INDEX_op_mul_i32:
- case INDEX_op_mul_i64:
- return &r_r_rI;
- case INDEX_op_div_i32:
- case INDEX_op_divu_i32:
- case INDEX_op_nand_i32:
- case INDEX_op_nor_i32:
- case INDEX_op_muluh_i32:
- case INDEX_op_mulsh_i32:
- case INDEX_op_orc_i64:
- case INDEX_op_eqv_i64:
- case INDEX_op_nand_i64:
- case INDEX_op_nor_i64:
- case INDEX_op_div_i64:
- case INDEX_op_divu_i64:
- case INDEX_op_mulsh_i64:
- case INDEX_op_muluh_i64:
- return &r_r_r;
- case INDEX_op_sub_i32:
- return &r_rI_ri;
- case INDEX_op_add_i64:
- return &r_r_rT;
- case INDEX_op_or_i64:
- case INDEX_op_xor_i64:
- return &r_r_rU;
- case INDEX_op_sub_i64:
- return &r_rI_rT;
- case INDEX_op_clz_i32:
- case INDEX_op_ctz_i32:
- case INDEX_op_clz_i64:
- case INDEX_op_ctz_i64:
- return &r_r_rZW;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return &r_ri;
-
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- return &movc;
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
- return &dep;
- case INDEX_op_brcond2_i32:
- return &br2;
- case INDEX_op_setcond2_i32:
- return &setc2;
- case INDEX_op_add2_i64:
- case INDEX_op_add2_i32:
- return &add2;
- case INDEX_op_sub2_i64:
- case INDEX_op_sub2_i32:
- return &sub2;
-
- case INDEX_op_qemu_ld_i32:
- return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
- case INDEX_op_qemu_st_i32:
- return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &S_S : &S_S_S);
- case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
- case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &S_S
- : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
-
- case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
- case INDEX_op_mul_vec:
- case INDEX_op_and_vec:
- case INDEX_op_or_vec:
- case INDEX_op_xor_vec:
- case INDEX_op_andc_vec:
- case INDEX_op_orc_vec:
- case INDEX_op_cmp_vec:
- case INDEX_op_ssadd_vec:
- case INDEX_op_sssub_vec:
- case INDEX_op_usadd_vec:
- case INDEX_op_ussub_vec:
- case INDEX_op_smax_vec:
- case INDEX_op_smin_vec:
- case INDEX_op_umax_vec:
- case INDEX_op_umin_vec:
- case INDEX_op_shlv_vec:
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
- case INDEX_op_rotlv_vec:
- case INDEX_op_rotrv_vec:
- case INDEX_op_ppc_mrgh_vec:
- case INDEX_op_ppc_mrgl_vec:
- case INDEX_op_ppc_muleu_vec:
- case INDEX_op_ppc_mulou_vec:
- case INDEX_op_ppc_pkum_vec:
- case INDEX_op_dup2_vec:
- return &v_v_v;
- case INDEX_op_not_vec:
- case INDEX_op_neg_vec:
- return &v_v;
- case INDEX_op_dup_vec:
- return have_isa_3_00 ? &v_vr : &v_v;
- case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
- case INDEX_op_dupm_vec:
- return &v_r;
- case INDEX_op_bitsel_vec:
- case INDEX_op_ppc_msum_vec:
- return &v_v_v_v;
-
- default:
- return NULL;
- }
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
- unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
-
- have_isa = tcg_isa_base;
- if (hwcap & PPC_FEATURE_ARCH_2_06) {
- have_isa = tcg_isa_2_06;
- }
-#ifdef PPC_FEATURE2_ARCH_2_07
- if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
- have_isa = tcg_isa_2_07;
- }
-#endif
-#ifdef PPC_FEATURE2_ARCH_3_00
- if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
- have_isa = tcg_isa_3_00;
- }
-#endif
-
-#ifdef PPC_FEATURE2_HAS_ISEL
- /* Prefer explicit instruction from the kernel. */
- have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
-#else
- /* Fall back to knowing Power7 (2.06) has ISEL. */
- have_isel = have_isa_2_06;
-#endif
-
- if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
- have_altivec = true;
- /* We only care about the portion of VSX that overlaps Altivec. */
- if (hwcap & PPC_FEATURE_HAS_VSX) {
- have_vsx = true;
- }
- }
-
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
- if (have_altivec) {
- tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
- tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
- }
-
- tcg_target_call_clobber_regs = 0;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
-
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
-#if defined(_CALL_SYSV)
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
-#endif
-#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
-#endif
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
- tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
- tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
- if (USE_REG_TB) {
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
- }
-}
-
-#ifdef __ELF__
-typedef struct {
- DebugFrameCIE cie;
- DebugFrameFDEHeader fde;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
-} DebugFrame;
-
-/* We're expecting a 2 byte uleb128 encoded value. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-
-#if TCG_TARGET_REG_BITS == 64
-# define ELF_HOST_MACHINE EM_PPC64
-#else
-# define ELF_HOST_MACHINE EM_PPC
-#endif
-
-static DebugFrame debug_frame = {
- .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .cie.id = -1,
- .cie.version = 1,
- .cie.code_align = 1,
- .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
- .cie.return_column = 65,
-
- /* Total FDE size does not include the "len" member. */
- .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
-
- .fde_def_cfa = {
- 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
- 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
- }
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- uint8_t *p = &debug_frame.fde_reg_ofs[3];
- int i;
-
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
- p[0] = 0x80 + tcg_target_callee_save_regs[i];
- p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
- }
-
- debug_frame.fde.func_start = (uintptr_t)buf;
- debug_frame.fde.func_len = buf_size;
-
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
-#endif /* __ELF__ */
-
-void flush_icache_range(uintptr_t start, uintptr_t stop)
-{
- uintptr_t p, start1, stop1;
- size_t dsize = qemu_dcache_linesize;
- size_t isize = qemu_icache_linesize;
-
- start1 = start & ~(dsize - 1);
- stop1 = (stop + dsize - 1) & ~(dsize - 1);
- for (p = start1; p < stop1; p += dsize) {
- asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
- }
- asm volatile ("sync" : : : "memory");
-
- start &= start & ~(isize - 1);
- stop1 = (stop + isize - 1) & ~(isize - 1);
- for (p = start1; p < stop1; p += isize) {
- asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
- }
- asm volatile ("sync" : : : "memory");
- asm volatile ("isync" : : : "memory");
-}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2018 SiFive, Inc
+ * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Based on i386/tcg-target.c and mips/tcg-target.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "../tcg-pool.c.inc"
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "zero",
+ "ra",
+ "sp",
+ "gp",
+ "tp",
+ "t0",
+ "t1",
+ "t2",
+ "s0",
+ "s1",
+ "a0",
+ "a1",
+ "a2",
+ "a3",
+ "a4",
+ "a5",
+ "a6",
+ "a7",
+ "s2",
+ "s3",
+ "s4",
+ "s5",
+ "s6",
+ "s7",
+ "s8",
+ "s9",
+ "s10",
+ "s11",
+ "t3",
+ "t4",
+ "t5",
+ "t6"
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+ /* Call saved registers */
+ /* TCG_REG_S0 reservered for TCG_AREG0 */
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+ TCG_REG_S9,
+ TCG_REG_S10,
+ TCG_REG_S11,
+
+ /* Call clobbered registers */
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+ TCG_REG_T4,
+ TCG_REG_T5,
+ TCG_REG_T6,
+
+ /* Argument registers */
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+ TCG_REG_A4,
+ TCG_REG_A5,
+ TCG_REG_A6,
+ TCG_REG_A7,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+ TCG_REG_A4,
+ TCG_REG_A5,
+ TCG_REG_A6,
+ TCG_REG_A7,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+};
+
+#define TCG_CT_CONST_ZERO 0x100
+#define TCG_CT_CONST_S12 0x200
+#define TCG_CT_CONST_N12 0x400
+#define TCG_CT_CONST_M12 0x800
+
+static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
+{
+ if (TCG_TARGET_REG_BITS == 32) {
+ return sextract32(val, pos, len);
+ } else {
+ return sextract64(val, pos, len);
+ }
+}
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'r':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ break;
+ case 'L':
+ /* qemu_ld/qemu_st constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
+#if defined(CONFIG_SOFTMMU)
+ tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
+ tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
+ tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
+ tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
+ tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
+#endif
+ break;
+ case 'I':
+ ct->ct |= TCG_CT_CONST_S12;
+ break;
+ case 'N':
+ ct->ct |= TCG_CT_CONST_N12;
+ break;
+ case 'M':
+ ct->ct |= TCG_CT_CONST_M12;
+ break;
+ case 'Z':
+ /* we can use a zero immediate as a zero register argument. */
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* test if a constant matches the constraint */
+static int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * RISC-V Base ISA opcodes (IM)
+ */
+
+typedef enum {
+ OPC_ADD = 0x33,
+ OPC_ADDI = 0x13,
+ OPC_AND = 0x7033,
+ OPC_ANDI = 0x7013,
+ OPC_AUIPC = 0x17,
+ OPC_BEQ = 0x63,
+ OPC_BGE = 0x5063,
+ OPC_BGEU = 0x7063,
+ OPC_BLT = 0x4063,
+ OPC_BLTU = 0x6063,
+ OPC_BNE = 0x1063,
+ OPC_DIV = 0x2004033,
+ OPC_DIVU = 0x2005033,
+ OPC_JAL = 0x6f,
+ OPC_JALR = 0x67,
+ OPC_LB = 0x3,
+ OPC_LBU = 0x4003,
+ OPC_LD = 0x3003,
+ OPC_LH = 0x1003,
+ OPC_LHU = 0x5003,
+ OPC_LUI = 0x37,
+ OPC_LW = 0x2003,
+ OPC_LWU = 0x6003,
+ OPC_MUL = 0x2000033,
+ OPC_MULH = 0x2001033,
+ OPC_MULHSU = 0x2002033,
+ OPC_MULHU = 0x2003033,
+ OPC_OR = 0x6033,
+ OPC_ORI = 0x6013,
+ OPC_REM = 0x2006033,
+ OPC_REMU = 0x2007033,
+ OPC_SB = 0x23,
+ OPC_SD = 0x3023,
+ OPC_SH = 0x1023,
+ OPC_SLL = 0x1033,
+ OPC_SLLI = 0x1013,
+ OPC_SLT = 0x2033,
+ OPC_SLTI = 0x2013,
+ OPC_SLTIU = 0x3013,
+ OPC_SLTU = 0x3033,
+ OPC_SRA = 0x40005033,
+ OPC_SRAI = 0x40005013,
+ OPC_SRL = 0x5033,
+ OPC_SRLI = 0x5013,
+ OPC_SUB = 0x40000033,
+ OPC_SW = 0x2023,
+ OPC_XOR = 0x4033,
+ OPC_XORI = 0x4013,
+
+#if TCG_TARGET_REG_BITS == 64
+ OPC_ADDIW = 0x1b,
+ OPC_ADDW = 0x3b,
+ OPC_DIVUW = 0x200503b,
+ OPC_DIVW = 0x200403b,
+ OPC_MULW = 0x200003b,
+ OPC_REMUW = 0x200703b,
+ OPC_REMW = 0x200603b,
+ OPC_SLLIW = 0x101b,
+ OPC_SLLW = 0x103b,
+ OPC_SRAIW = 0x4000501b,
+ OPC_SRAW = 0x4000503b,
+ OPC_SRLIW = 0x501b,
+ OPC_SRLW = 0x503b,
+ OPC_SUBW = 0x4000003b,
+#else
+ /* Simplify code throughout by defining aliases for RV32. */
+ OPC_ADDIW = OPC_ADDI,
+ OPC_ADDW = OPC_ADD,
+ OPC_DIVUW = OPC_DIVU,
+ OPC_DIVW = OPC_DIV,
+ OPC_MULW = OPC_MUL,
+ OPC_REMUW = OPC_REMU,
+ OPC_REMW = OPC_REM,
+ OPC_SLLIW = OPC_SLLI,
+ OPC_SLLW = OPC_SLL,
+ OPC_SRAIW = OPC_SRAI,
+ OPC_SRAW = OPC_SRA,
+ OPC_SRLIW = OPC_SRLI,
+ OPC_SRLW = OPC_SRL,
+ OPC_SUBW = OPC_SUB,
+#endif
+
+ OPC_FENCE = 0x0000000f,
+} RISCVInsn;
+
+/*
+ * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
+ */
+
+/* Type-R */
+
+static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+ return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
+}
+
+/* Type-I */
+
+static int32_t encode_imm12(uint32_t imm)
+{
+ return (imm & 0xfff) << 20;
+}
+
+static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
+{
+ return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
+}
+
+/* Type-S */
+
+static int32_t encode_simm12(uint32_t imm)
+{
+ int32_t ret = 0;
+
+ ret |= (imm & 0xFE0) << 20;
+ ret |= (imm & 0x1F) << 7;
+
+ return ret;
+}
+
+static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
+}
+
+/* Type-SB */
+
+static int32_t encode_sbimm12(uint32_t imm)
+{
+ int32_t ret = 0;
+
+ ret |= (imm & 0x1000) << 19;
+ ret |= (imm & 0x7e0) << 20;
+ ret |= (imm & 0x1e) << 7;
+ ret |= (imm & 0x800) >> 4;
+
+ return ret;
+}
+
+static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
+}
+
+/* Type-U */
+
+static int32_t encode_uimm20(uint32_t imm)
+{
+ return imm & 0xfffff000;
+}
+
+static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
+{
+ return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
+}
+
+/* Type-UJ */
+
+static int32_t encode_ujimm20(uint32_t imm)
+{
+ int32_t ret = 0;
+
+ ret |= (imm & 0x0007fe) << (21 - 1);
+ ret |= (imm & 0x000800) << (20 - 11);
+ ret |= (imm & 0x0ff000) << (12 - 12);
+ ret |= (imm & 0x100000) << (31 - 20);
+
+ return ret;
+}
+
+static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
+{
+ return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
+}
+
+/*
+ * RISC-V instruction emitters
+ */
+
+static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+ tcg_out32(s, encode_r(opc, rd, rs1, rs2));
+}
+
+static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGArg imm)
+{
+ tcg_out32(s, encode_i(opc, rd, rs1, imm));
+}
+
+static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_s(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_u(opc, rd, imm));
+}
+
+static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_uj(opc, rd, imm));
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
+ }
+}
+
+/*
+ * Relocations
+ */
+
+static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+
+ if (offset == sextreg(offset, 1, 12) << 1) {
+ code_ptr[0] |= encode_sbimm12(offset);
+ return true;
+ }
+
+ return false;
+}
+
+static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+
+ if (offset == sextreg(offset, 1, 20) << 1) {
+ code_ptr[0] |= encode_ujimm20(offset);
+ return true;
+ }
+
+ return false;
+}
+
+static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+ int32_t lo = sextreg(offset, 0, 12);
+ int32_t hi = offset - lo;
+
+ if (offset == hi + lo) {
+ code_ptr[0] |= encode_uimm20(hi);
+ code_ptr[1] |= encode_imm12(lo);
+ return true;
+ }
+
+ return false;
+}
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ uint32_t insn = *code_ptr;
+ intptr_t diff;
+ bool short_jmp;
+
+ tcg_debug_assert(addend == 0);
+
+ switch (type) {
+ case R_RISCV_BRANCH:
+ diff = value - (uintptr_t)code_ptr;
+ short_jmp = diff == sextreg(diff, 0, 12);
+ if (short_jmp) {
+ return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
+ } else {
+ /* Invert the condition */
+ insn = insn ^ (1 << 12);
+ /* Clear the offset */
+ insn &= 0x01fff07f;
+ /* Set the offset to the PC + 8 */
+ insn |= encode_sbimm12(8);
+
+ /* Move forward */
+ code_ptr[0] = insn;
+
+ /* Overwrite the NOP with jal x0,value */
+ diff = value - (uintptr_t)(code_ptr + 1);
+ insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff);
+ code_ptr[1] = insn;
+
+ return true;
+ }
+ break;
+ case R_RISCV_JAL:
+ return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
+ case R_RISCV_CALL:
+ return reloc_call(code_ptr, (tcg_insn_unit *)value);
+ default:
+ tcg_abort();
+ }
+}
+
+/*
+ * TCG intrinsics
+ */
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+ tcg_target_long lo, hi, tmp;
+ int shift, ret;
+
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ lo = sextreg(val, 0, 12);
+ if (val == lo) {
+ tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
+ return;
+ }
+
+ hi = val - lo;
+ if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, hi);
+ if (lo != 0) {
+ tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
+ }
+ return;
+ }
+
+ /* We can only be here if TCG_TARGET_REG_BITS != 32 */
+ tmp = tcg_pcrel_diff(s, (void *)val);
+ if (tmp == (int32_t)tmp) {
+ tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
+ tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
+ ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
+ tcg_debug_assert(ret == true);
+ return;
+ }
+
+ /* Look for a single 20-bit section. */
+ shift = ctz64(val);
+ tmp = val >> shift;
+ if (tmp == sextreg(tmp, 0, 20)) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
+ if (shift > 12) {
+ tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
+ } else {
+ tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
+ }
+ return;
+ }
+
+ /* Look for a few high zero bits, with lots of bits set in the middle. */
+ shift = clz64(val);
+ tmp = val << shift;
+ if (tmp == sextreg(tmp, 12, 20) << 12) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
+ tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
+ return;
+ } else if (tmp == sextreg(tmp, 0, 12)) {
+ tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
+ tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
+ return;
+ }
+
+ /* Drop into the constant pool. */
+ new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
+ tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
+ tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
+}
+
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+ tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
+}
+
+static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
+ TCGReg addr, intptr_t offset)
+{
+ intptr_t imm12 = sextreg(offset, 0, 12);
+
+ if (offset != imm12) {
+ intptr_t diff = offset - (uintptr_t)s->code_ptr;
+
+ if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
+ imm12 = sextreg(diff, 0, 12);
+ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
+ if (addr != TCG_REG_ZERO) {
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
+ }
+ }
+ addr = TCG_REG_TMP2;
+ }
+
+ switch (opc) {
+ case OPC_SB:
+ case OPC_SH:
+ case OPC_SW:
+ case OPC_SD:
+ tcg_out_opc_store(s, opc, addr, data, imm12);
+ break;
+ case OPC_LB:
+ case OPC_LBU:
+ case OPC_LH:
+ case OPC_LHU:
+ case OPC_LW:
+ case OPC_LWU:
+ case OPC_LD:
+ tcg_out_opc_imm(s, opc, data, addr, imm12);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+ tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+ tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
+}
+
+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ if (val == 0) {
+ tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
+ return true;
+ }
+ return false;
+}
+
+static void tcg_out_addsub2(TCGContext *s,
+ TCGReg rl, TCGReg rh,
+ TCGReg al, TCGReg ah,
+ TCGArg bl, TCGArg bh,
+ bool cbl, bool cbh, bool is_sub, bool is32bit)
+{
+ const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
+ const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
+ const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
+ TCGReg th = TCG_REG_TMP1;
+
+ /* If we have a negative constant such that negating it would
+ make the high part zero, we can (usually) eliminate one insn. */
+ if (cbl && cbh && bh == -1 && bl != 0) {
+ bl = -bl;
+ bh = 0;
+ is_sub = !is_sub;
+ }
+
+ /* By operating on the high part first, we get to use the final
+ carry operation to move back from the temporary. */
+ if (!cbh) {
+ tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
+ } else if (bh != 0 || ah == rl) {
+ tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
+ } else {
+ th = ah;
+ }
+
+ /* Note that tcg optimization should eliminate the bl == 0 case. */
+ if (is_sub) {
+ if (cbl) {
+ tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
+ tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
+ } else {
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
+ tcg_out_opc_reg(s, opc_sub, rl, al, bl);
+ }
+ tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
+ } else {
+ if (cbl) {
+ tcg_out_opc_imm(s, opc_addi, rl, al, bl);
+ tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
+ } else if (rl == al && rl == bl) {
+ tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
+ tcg_out_opc_reg(s, opc_addi, rl, al, bl);
+ } else {
+ tcg_out_opc_reg(s, opc_add, rl, al, bl);
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
+ rl, (rl == bl ? al : bl));
+ }
+ tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
+ }
+}
+
+static const struct {
+ RISCVInsn op;
+ bool swap;
+} tcg_brcond_to_riscv[] = {
+ [TCG_COND_EQ] = { OPC_BEQ, false },
+ [TCG_COND_NE] = { OPC_BNE, false },
+ [TCG_COND_LT] = { OPC_BLT, false },
+ [TCG_COND_GE] = { OPC_BGE, false },
+ [TCG_COND_LE] = { OPC_BGE, true },
+ [TCG_COND_GT] = { OPC_BLT, true },
+ [TCG_COND_LTU] = { OPC_BLTU, false },
+ [TCG_COND_GEU] = { OPC_BGEU, false },
+ [TCG_COND_LEU] = { OPC_BGEU, true },
+ [TCG_COND_GTU] = { OPC_BLTU, true }
+};
+
+static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
+ TCGReg arg2, TCGLabel *l)
+{
+ RISCVInsn op = tcg_brcond_to_riscv[cond].op;
+
+ tcg_debug_assert(op != 0);
+
+ if (tcg_brcond_to_riscv[cond].swap) {
+ TCGReg t = arg1;
+ arg1 = arg2;
+ arg2 = t;
+ }
+
+ if (l->has_value) {
+ intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr);
+ if (diff == sextreg(diff, 0, 12)) {
+ tcg_out_opc_branch(s, op, arg1, arg2, diff);
+ } else {
+ /* Invert the conditional branch. */
+ tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8);
+ tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4);
+ }
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
+ tcg_out_opc_branch(s, op, arg1, arg2, 0);
+ /* NOP to allow patching later */
+ tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
+ }
+}
+
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg arg1, TCGReg arg2)
+{
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
+ break;
+ case TCG_COND_NE:
+ tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
+ tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
+ break;
+ case TCG_COND_LT:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+ break;
+ case TCG_COND_GE:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_LE:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_GT:
+ tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+ break;
+ case TCG_COND_LTU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+ break;
+ case TCG_COND_GEU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_LEU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+ tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
+ TCGReg bl, TCGReg bh, TCGLabel *l)
+{
+ /* todo */
+ g_assert_not_reached();
+}
+
+static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
+{
+ /* todo */
+ g_assert_not_reached();
+}
+
+static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
+{
+ ptrdiff_t offset = tcg_pcrel_diff(s, target);
+ tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1);
+ tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
+}
+
+static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
+{
+ TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
+ ptrdiff_t offset = tcg_pcrel_diff(s, arg);
+ int ret;
+
+ if (offset == sextreg(offset, 1, 20) << 1) {
+ /* short jump: -2097150 to 2097152 */
+ tcg_out_opc_jump(s, OPC_JAL, link, offset);
+ } else if (TCG_TARGET_REG_BITS == 32 ||
+ offset == sextreg(offset, 1, 31) << 1) {
+ /* long jump: -2147483646 to 2147483648 */
+ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
+ tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
+ ret = reloc_call(s->code_ptr - 2, arg);\
+ tcg_debug_assert(ret == true);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ /* far jump: 64-bit */
+ tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
+ tcg_target_long base = (tcg_target_long)arg - imm;
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
+ tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
+{
+ tcg_out_call_int(s, arg, false);
+}
+
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ tcg_insn_unit insn = OPC_FENCE;
+
+ if (a0 & TCG_MO_LD_LD) {
+ insn |= 0x02200000;
+ }
+ if (a0 & TCG_MO_ST_LD) {
+ insn |= 0x01200000;
+ }
+ if (a0 & TCG_MO_LD_ST) {
+ insn |= 0x02100000;
+ }
+ if (a0 & TCG_MO_ST_ST) {
+ insn |= 0x02200000;
+ }
+ tcg_out32(s, insn);
+}
+
+/*
+ * Load/store and TLB
+ */
+
+#if defined(CONFIG_SOFTMMU)
+#include "../tcg-ldst.c.inc"
+
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * TCGMemOpIdx oi, uintptr_t ra)
+ */
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LESW] = helper_le_ldsw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+#if TCG_TARGET_REG_BITS == 64
+ [MO_LESL] = helper_le_ldsl_mmu,
+#endif
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BESW] = helper_be_ldsw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+#if TCG_TARGET_REG_BITS == 64
+ [MO_BESL] = helper_be_ldsl_mmu,
+#endif
+ [MO_BEQ] = helper_be_ldq_mmu,
+};
+
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, TCGMemOpIdx oi,
+ * uintptr_t ra)
+ */
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+
+/* We don't support oversize guests */
+QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
+
+/* We expect to use a 12-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
+
+static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
+ TCGReg addrh, TCGMemOpIdx oi,
+ tcg_insn_unit **label_ptr, bool is_load)
+{
+ MemOp opc = get_memop(oi);
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+ tcg_target_long compare_mask;
+ int mem_index = get_mmuidx(oi);
+ int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
+ int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
+ TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
+
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);
+
+ tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
+
+ /* Load the tlb comparator and the addend. */
+ tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
+ is_load ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
+ offsetof(CPUTLBEntry, addend));
+
+ /* We don't support unaligned accesses. */
+ if (a_bits < s_bits) {
+ a_bits = s_bits;
+ }
+ /* Clear the non-page, non-alignment bits from the address. */
+ compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
+ if (compare_mask == sextreg(compare_mask, 0, 12)) {
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
+ tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
+ }
+
+ /* Compare masked address with the TLB entry. */
+ label_ptr[0] = s->code_ptr;
+ tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
+ /* NOP to allow patching later */
+ tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
+
+ /* TLB Hit - translate address using addend. */
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
+ addrl = TCG_REG_TMP0;
+ }
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
+}
+
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
+ TCGType ext,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addrhi,
+ void *raddr, tcg_insn_unit **label_ptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->type = ext;
+ label->datalo_reg = datalo;
+ label->datahi_reg = datahi;
+ label->addrlo_reg = addrlo;
+ label->addrhi_reg = addrhi;
+ label->raddr = raddr;
+ label->label_ptr[0] = label_ptr[0];
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ TCGMemOpIdx oi = l->oi;
+ MemOp opc = get_memop(oi);
+ TCGReg a0 = tcg_target_call_iarg_regs[0];
+ TCGReg a1 = tcg_target_call_iarg_regs[1];
+ TCGReg a2 = tcg_target_call_iarg_regs[2];
+ TCGReg a3 = tcg_target_call_iarg_regs[3];
+
+ /* We don't support oversize guests */
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ g_assert_not_reached();
+ }
+
+ /* resolve label address */
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
+ (intptr_t) s->code_ptr, 0)) {
+ return false;
+ }
+
+ /* call load helper */
+ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
+ tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
+ tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
+
+ tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
+ tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
+
+ tcg_out_goto(s, l->raddr);
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ TCGMemOpIdx oi = l->oi;
+ MemOp opc = get_memop(oi);
+ MemOp s_bits = opc & MO_SIZE;
+ TCGReg a0 = tcg_target_call_iarg_regs[0];
+ TCGReg a1 = tcg_target_call_iarg_regs[1];
+ TCGReg a2 = tcg_target_call_iarg_regs[2];
+ TCGReg a3 = tcg_target_call_iarg_regs[3];
+ TCGReg a4 = tcg_target_call_iarg_regs[4];
+
+ /* We don't support oversize guests */
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ g_assert_not_reached();
+ }
+
+ /* resolve label address */
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
+ (intptr_t) s->code_ptr, 0)) {
+ return false;
+ }
+
+ /* call store helper */
+ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
+ tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);
+ switch (s_bits) {
+ case MO_8:
+ tcg_out_ext8u(s, a2, a2);
+ break;
+ case MO_16:
+ tcg_out_ext16u(s, a2, a2);
+ break;
+ default:
+ break;
+ }
+ tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
+
+ tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
+
+ tcg_out_goto(s, l->raddr);
+ return true;
+}
+#endif /* CONFIG_SOFTMMU */
+
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
+ TCGReg base, MemOp opc, bool is_64)
+{
+ const MemOp bswap = opc & MO_BSWAP;
+
+ /* We don't yet handle byteswapping, assert */
+ g_assert(!bswap);
+
+ switch (opc & (MO_SSIZE)) {
+ case MO_UB:
+ tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
+ break;
+ case MO_SB:
+ tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
+ break;
+ case MO_UW:
+ tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
+ break;
+ case MO_SW:
+ tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
+ break;
+ case MO_UL:
+ if (TCG_TARGET_REG_BITS == 64 && is_64) {
+ tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
+ break;
+ }
+ /* FALLTHRU */
+ case MO_SL:
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+ break;
+ case MO_Q:
+ /* Prefer to load from offset 0 first, but allow for overlap. */
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
+ } else if (lo != base) {
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+ tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
+ } else {
+ tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
+{
+ TCGReg addr_regl, addr_regh __attribute__((unused));
+ TCGReg data_regl, data_regh;
+ TCGMemOpIdx oi;
+ MemOp opc;
+#if defined(CONFIG_SOFTMMU)
+ tcg_insn_unit *label_ptr[1];
+#endif
+ TCGReg base = TCG_REG_TMP0;
+
+ data_regl = *args++;
+ data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+ addr_regl = *args++;
+ addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+ tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+ add_qemu_ldst_label(s, 1, oi,
+ (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+ data_regl, data_regh, addr_regl, addr_regh,
+ s->code_ptr, label_ptr);
+#else
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addr_regl);
+ addr_regl = base;
+ }
+
+ if (guest_base == 0) {
+ tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
+ } else {
+ tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ }
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+#endif
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
+ TCGReg base, MemOp opc)
+{
+ const MemOp bswap = opc & MO_BSWAP;
+
+ /* We don't yet handle byteswapping, assert */
+ g_assert(!bswap);
+
+ switch (opc & (MO_SSIZE)) {
+ case MO_8:
+ tcg_out_opc_store(s, OPC_SB, base, lo, 0);
+ break;
+ case MO_16:
+ tcg_out_opc_store(s, OPC_SH, base, lo, 0);
+ break;
+ case MO_32:
+ tcg_out_opc_store(s, OPC_SW, base, lo, 0);
+ break;
+ case MO_64:
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_opc_store(s, OPC_SD, base, lo, 0);
+ } else {
+ tcg_out_opc_store(s, OPC_SW, base, lo, 0);
+ tcg_out_opc_store(s, OPC_SW, base, hi, 4);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
+{
+ TCGReg addr_regl, addr_regh __attribute__((unused));
+ TCGReg data_regl, data_regh;
+ TCGMemOpIdx oi;
+ MemOp opc;
+#if defined(CONFIG_SOFTMMU)
+ tcg_insn_unit *label_ptr[1];
+#endif
+ TCGReg base = TCG_REG_TMP0;
+
+ data_regl = *args++;
+ data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+ addr_regl = *args++;
+ addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+ oi = *args++;
+ opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+ tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
+ tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+ add_qemu_ldst_label(s, 0, oi,
+ (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+ data_regl, data_regh, addr_regl, addr_regh,
+ s->code_ptr, label_ptr);
+#else
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addr_regl);
+ addr_regl = base;
+ }
+
+ if (guest_base == 0) {
+ tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
+ } else {
+ tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ }
+ tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+#endif
+}
+
+static tcg_insn_unit *tb_ret_addr;
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg *args, const int *const_args)
+{
+ TCGArg a0 = args[0];
+ TCGArg a1 = args[1];
+ TCGArg a2 = args[2];
+ int c2 = const_args[2];
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ /* Reuse the zeroing that exists for goto_ptr. */
+ if (a0 == 0) {
+ tcg_out_call_int(s, s->code_gen_epilogue, true);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
+ tcg_out_call_int(s, tb_ret_addr, true);
+ }
+ break;
+
+ case INDEX_op_goto_tb:
+ assert(s->tb_jmp_insn_offset == 0);
+ /* indirect jump method */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
+ (uintptr_t)(s->tb_jmp_target_addr + a0));
+ tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
+ set_jmp_reset_offset(s, a0);
+ break;
+
+ case INDEX_op_goto_ptr:
+ tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
+ break;
+
+ case INDEX_op_br:
+ tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
+ tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
+ break;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
+ break;
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ tcg_out_ldst(s, OPC_LB, a0, a1, a2);
+ break;
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
+ break;
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ tcg_out_ldst(s, OPC_LH, a0, a1, a2);
+ break;
+ case INDEX_op_ld32u_i64:
+ tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
+ break;
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32s_i64:
+ tcg_out_ldst(s, OPC_LW, a0, a1, a2);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ldst(s, OPC_LD, a0, a1, a2);
+ break;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ tcg_out_ldst(s, OPC_SB, a0, a1, a2);
+ break;
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ tcg_out_ldst(s, OPC_SH, a0, a1, a2);
+ break;
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ tcg_out_ldst(s, OPC_SW, a0, a1, a2);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_ldst(s, OPC_SD, a0, a1, a2);
+ break;
+
+ case INDEX_op_add_i32:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_add_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_sub_i32:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_sub_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
+ break;
+
+ case INDEX_op_neg_i32:
+ tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
+ break;
+ case INDEX_op_neg_i64:
+ tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
+ break;
+
+ case INDEX_op_mul_i32:
+ tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
+ break;
+ case INDEX_op_mul_i64:
+ tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
+ break;
+
+ case INDEX_op_div_i32:
+ tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
+ break;
+ case INDEX_op_div_i64:
+ tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
+ break;
+
+ case INDEX_op_divu_i32:
+ tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
+ break;
+ case INDEX_op_divu_i64:
+ tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
+ break;
+
+ case INDEX_op_rem_i32:
+ tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
+ break;
+ case INDEX_op_rem_i64:
+ tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
+ break;
+
+ case INDEX_op_remu_i32:
+ tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
+ break;
+ case INDEX_op_remu_i64:
+ tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
+ break;
+
+ case INDEX_op_shl_i32:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_shl_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_shr_i32:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_shr_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_sar_i32:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_sar_i64:
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_add2_i32:
+ tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
+ const_args[4], const_args[5], false, true);
+ break;
+ case INDEX_op_add2_i64:
+ tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
+ const_args[4], const_args[5], false, false);
+ break;
+ case INDEX_op_sub2_i32:
+ tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
+ const_args[4], const_args[5], true, true);
+ break;
+ case INDEX_op_sub2_i64:
+ tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
+ const_args[4], const_args[5], true, false);
+ break;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
+ break;
+ case INDEX_op_brcond2_i32:
+ tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
+ break;
+
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond(s, args[3], a0, a1, a2);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_qemu_ld(s, args, false);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args, true);
+ break;
+ case INDEX_op_qemu_st_i32:
+ tcg_out_qemu_st(s, args, false);
+ break;
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args, true);
+ break;
+
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ tcg_out_ext8u(s, a0, a1);
+ break;
+
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ tcg_out_ext16u(s, a0, a1);
+ break;
+
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ tcg_out_ext32u(s, a0, a1);
+ break;
+
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ tcg_out_ext8s(s, a0, a1);
+ break;
+
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ tcg_out_ext16s(s, a0, a1);
+ break;
+
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_ext_i32_i64:
+ tcg_out_ext32s(s, a0, a1);
+ break;
+
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
+ break;
+
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_mulsh_i64:
+ tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
+ break;
+
+ case INDEX_op_muluh_i32:
+ case INDEX_op_muluh_i64:
+ tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r
+ = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r
+ = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef rZ_r
+ = { .args_ct_str = { "rZ", "r" } };
+ static const TCGTargetOpDef rZ_rZ
+ = { .args_ct_str = { "rZ", "rZ" } };
+ static const TCGTargetOpDef rZ_rZ_rZ_rZ
+ = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
+ static const TCGTargetOpDef r_r_ri
+ = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI
+ = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_rZ_rN
+ = { .args_ct_str = { "r", "rZ", "rN" } };
+ static const TCGTargetOpDef r_rZ_rZ
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
+ static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
+ static const TCGTargetOpDef r_L
+ = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef r_r_L
+ = { .args_ct_str = { "r", "r", "L" } };
+ static const TCGTargetOpDef r_L_L
+ = { .args_ct_str = { "r", "L", "L" } };
+ static const TCGTargetOpDef r_r_L_L
+ = { .args_ct_str = { "r", "r", "L", "L" } };
+ static const TCGTargetOpDef LZ_L
+ = { .args_ct_str = { "LZ", "L" } };
+ static const TCGTargetOpDef LZ_L_L
+ = { .args_ct_str = { "LZ", "L", "L" } };
+ static const TCGTargetOpDef LZ_LZ_L
+ = { .args_ct_str = { "LZ", "LZ", "L" } };
+ static const TCGTargetOpDef LZ_LZ_L_L
+ = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
+ static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
+ = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_neg_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ case INDEX_op_ext_i32_i64:
+ return &r_r;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &rZ_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_and_i32:
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_add_i64:
+ case INDEX_op_and_i64:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i64:
+ return &r_r_rI;
+
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ return &r_rZ_rN;
+
+ case INDEX_op_mul_i32:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_rem_i32:
+ case INDEX_op_remu_i32:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i64:
+ case INDEX_op_setcond_i64:
+ return &r_rZ_rZ;
+
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ return &r_r_ri;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &rZ_rZ;
+
+ case INDEX_op_add2_i32:
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i32:
+ case INDEX_op_sub2_i64:
+ return &r_r_rZ_rZ_rM_rM;
+
+ case INDEX_op_brcond2_i32:
+ return &rZ_rZ_rZ_rZ;
+
+ case INDEX_op_setcond2_i32:
+ return &r_rZ_rZ_rZ_rZ;
+
+ case INDEX_op_qemu_ld_i32:
+ return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ case INDEX_op_qemu_st_i32:
+ return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
+ case INDEX_op_qemu_ld_i64:
+ return TCG_TARGET_REG_BITS == 64 ? &r_L
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
+ : &r_r_L_L;
+ case INDEX_op_qemu_st_i64:
+ return TCG_TARGET_REG_BITS == 64 ? &LZ_L
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
+ : &LZ_LZ_L_L;
+
+ default:
+ return NULL;
+ }
+}
+
+static const int tcg_target_callee_save_regs[] = {
+ TCG_REG_S0, /* used for the global env (TCG_AREG0) */
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+ TCG_REG_S9,
+ TCG_REG_S10,
+ TCG_REG_S11,
+ TCG_REG_RA, /* should be last for ABI compliance */
+};
+
+/* Stack frame parameters. */
+#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
+#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
+#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
+#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & -TCG_TARGET_STACK_ALIGN)
+#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
+
+/* We're expecting to be able to use an immediate for frame allocation. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
+
+/* Generate global QEMU prologue and epilogue code */
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ int i;
+
+ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
+
+ /* TB prologue */
+ tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
+ }
+
+#if !defined(CONFIG_SOFTMMU)
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+#endif
+
+ /* Call generated code */
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+ tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
+
+ /* Return path for goto_ptr. Set return value to 0 */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
+
+ /* TB epilogue */
+ tb_ret_addr = s->code_ptr;
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
+ }
+
+ tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
+ tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
+ }
+
+ tcg_target_call_clobber_regs = -1u;
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_RISCV
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.return_column = TCG_REG_RA,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
+ 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
+ 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
+ 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
+ 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
+ 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
+ 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
+ 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
+ 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
+ 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
+ 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
+ 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2018 SiFive, Inc
- * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
- * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Based on i386/tcg-target.c and mips/tcg-target.c
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "../tcg-pool.inc.c"
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "zero",
- "ra",
- "sp",
- "gp",
- "tp",
- "t0",
- "t1",
- "t2",
- "s0",
- "s1",
- "a0",
- "a1",
- "a2",
- "a3",
- "a4",
- "a5",
- "a6",
- "a7",
- "s2",
- "s3",
- "s4",
- "s5",
- "s6",
- "s7",
- "s8",
- "s9",
- "s10",
- "s11",
- "t3",
- "t4",
- "t5",
- "t6"
-};
-#endif
-
-static const int tcg_target_reg_alloc_order[] = {
- /* Call saved registers */
- /* TCG_REG_S0 reservered for TCG_AREG0 */
- TCG_REG_S1,
- TCG_REG_S2,
- TCG_REG_S3,
- TCG_REG_S4,
- TCG_REG_S5,
- TCG_REG_S6,
- TCG_REG_S7,
- TCG_REG_S8,
- TCG_REG_S9,
- TCG_REG_S10,
- TCG_REG_S11,
-
- /* Call clobbered registers */
- TCG_REG_T0,
- TCG_REG_T1,
- TCG_REG_T2,
- TCG_REG_T3,
- TCG_REG_T4,
- TCG_REG_T5,
- TCG_REG_T6,
-
- /* Argument registers */
- TCG_REG_A0,
- TCG_REG_A1,
- TCG_REG_A2,
- TCG_REG_A3,
- TCG_REG_A4,
- TCG_REG_A5,
- TCG_REG_A6,
- TCG_REG_A7,
-};
-
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_A0,
- TCG_REG_A1,
- TCG_REG_A2,
- TCG_REG_A3,
- TCG_REG_A4,
- TCG_REG_A5,
- TCG_REG_A6,
- TCG_REG_A7,
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_A0,
- TCG_REG_A1,
-};
-
-#define TCG_CT_CONST_ZERO 0x100
-#define TCG_CT_CONST_S12 0x200
-#define TCG_CT_CONST_N12 0x400
-#define TCG_CT_CONST_M12 0x800
-
-static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
-{
- if (TCG_TARGET_REG_BITS == 32) {
- return sextract32(val, pos, len);
- } else {
- return sextract64(val, pos, len);
- }
-}
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- break;
- case 'L':
- /* qemu_ld/qemu_st constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
-#if defined(CONFIG_SOFTMMU)
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S12;
- break;
- case 'N':
- ct->ct |= TCG_CT_CONST_N12;
- break;
- case 'M':
- ct->ct |= TCG_CT_CONST_M12;
- break;
- case 'Z':
- /* we can use a zero immediate as a zero register argument. */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct = arg_ct->ct;
- if (ct & TCG_CT_CONST) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
- return 1;
- }
- if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
- return 1;
- }
- return 0;
-}
-
-/*
- * RISC-V Base ISA opcodes (IM)
- */
-
-typedef enum {
- OPC_ADD = 0x33,
- OPC_ADDI = 0x13,
- OPC_AND = 0x7033,
- OPC_ANDI = 0x7013,
- OPC_AUIPC = 0x17,
- OPC_BEQ = 0x63,
- OPC_BGE = 0x5063,
- OPC_BGEU = 0x7063,
- OPC_BLT = 0x4063,
- OPC_BLTU = 0x6063,
- OPC_BNE = 0x1063,
- OPC_DIV = 0x2004033,
- OPC_DIVU = 0x2005033,
- OPC_JAL = 0x6f,
- OPC_JALR = 0x67,
- OPC_LB = 0x3,
- OPC_LBU = 0x4003,
- OPC_LD = 0x3003,
- OPC_LH = 0x1003,
- OPC_LHU = 0x5003,
- OPC_LUI = 0x37,
- OPC_LW = 0x2003,
- OPC_LWU = 0x6003,
- OPC_MUL = 0x2000033,
- OPC_MULH = 0x2001033,
- OPC_MULHSU = 0x2002033,
- OPC_MULHU = 0x2003033,
- OPC_OR = 0x6033,
- OPC_ORI = 0x6013,
- OPC_REM = 0x2006033,
- OPC_REMU = 0x2007033,
- OPC_SB = 0x23,
- OPC_SD = 0x3023,
- OPC_SH = 0x1023,
- OPC_SLL = 0x1033,
- OPC_SLLI = 0x1013,
- OPC_SLT = 0x2033,
- OPC_SLTI = 0x2013,
- OPC_SLTIU = 0x3013,
- OPC_SLTU = 0x3033,
- OPC_SRA = 0x40005033,
- OPC_SRAI = 0x40005013,
- OPC_SRL = 0x5033,
- OPC_SRLI = 0x5013,
- OPC_SUB = 0x40000033,
- OPC_SW = 0x2023,
- OPC_XOR = 0x4033,
- OPC_XORI = 0x4013,
-
-#if TCG_TARGET_REG_BITS == 64
- OPC_ADDIW = 0x1b,
- OPC_ADDW = 0x3b,
- OPC_DIVUW = 0x200503b,
- OPC_DIVW = 0x200403b,
- OPC_MULW = 0x200003b,
- OPC_REMUW = 0x200703b,
- OPC_REMW = 0x200603b,
- OPC_SLLIW = 0x101b,
- OPC_SLLW = 0x103b,
- OPC_SRAIW = 0x4000501b,
- OPC_SRAW = 0x4000503b,
- OPC_SRLIW = 0x501b,
- OPC_SRLW = 0x503b,
- OPC_SUBW = 0x4000003b,
-#else
- /* Simplify code throughout by defining aliases for RV32. */
- OPC_ADDIW = OPC_ADDI,
- OPC_ADDW = OPC_ADD,
- OPC_DIVUW = OPC_DIVU,
- OPC_DIVW = OPC_DIV,
- OPC_MULW = OPC_MUL,
- OPC_REMUW = OPC_REMU,
- OPC_REMW = OPC_REM,
- OPC_SLLIW = OPC_SLLI,
- OPC_SLLW = OPC_SLL,
- OPC_SRAIW = OPC_SRAI,
- OPC_SRAW = OPC_SRA,
- OPC_SRLIW = OPC_SRLI,
- OPC_SRLW = OPC_SRL,
- OPC_SUBW = OPC_SUB,
-#endif
-
- OPC_FENCE = 0x0000000f,
-} RISCVInsn;
-
-/*
- * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
- */
-
-/* Type-R */
-
-static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
-{
- return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
-}
-
-/* Type-I */
-
-static int32_t encode_imm12(uint32_t imm)
-{
- return (imm & 0xfff) << 20;
-}
-
-static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
-{
- return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
-}
-
-/* Type-S */
-
-static int32_t encode_simm12(uint32_t imm)
-{
- int32_t ret = 0;
-
- ret |= (imm & 0xFE0) << 20;
- ret |= (imm & 0x1F) << 7;
-
- return ret;
-}
-
-static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
-{
- return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
-}
-
-/* Type-SB */
-
-static int32_t encode_sbimm12(uint32_t imm)
-{
- int32_t ret = 0;
-
- ret |= (imm & 0x1000) << 19;
- ret |= (imm & 0x7e0) << 20;
- ret |= (imm & 0x1e) << 7;
- ret |= (imm & 0x800) >> 4;
-
- return ret;
-}
-
-static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
-{
- return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
-}
-
-/* Type-U */
-
-static int32_t encode_uimm20(uint32_t imm)
-{
- return imm & 0xfffff000;
-}
-
-static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
-{
- return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
-}
-
-/* Type-UJ */
-
-static int32_t encode_ujimm20(uint32_t imm)
-{
- int32_t ret = 0;
-
- ret |= (imm & 0x0007fe) << (21 - 1);
- ret |= (imm & 0x000800) << (20 - 11);
- ret |= (imm & 0x0ff000) << (12 - 12);
- ret |= (imm & 0x100000) << (31 - 20);
-
- return ret;
-}
-
-static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
-{
- return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
-}
-
-/*
- * RISC-V instruction emitters
- */
-
-static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
- TCGReg rd, TCGReg rs1, TCGReg rs2)
-{
- tcg_out32(s, encode_r(opc, rd, rs1, rs2));
-}
-
-static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
- TCGReg rd, TCGReg rs1, TCGArg imm)
-{
- tcg_out32(s, encode_i(opc, rd, rs1, imm));
-}
-
-static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
- TCGReg rs1, TCGReg rs2, uint32_t imm)
-{
- tcg_out32(s, encode_s(opc, rs1, rs2, imm));
-}
-
-static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
- TCGReg rs1, TCGReg rs2, uint32_t imm)
-{
- tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
-}
-
-static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
- TCGReg rd, uint32_t imm)
-{
- tcg_out32(s, encode_u(opc, rd, imm));
-}
-
-static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
- TCGReg rd, uint32_t imm)
-{
- tcg_out32(s, encode_uj(opc, rd, imm));
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- int i;
- for (i = 0; i < count; ++i) {
- p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
- }
-}
-
-/*
- * Relocations
- */
-
-static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
-
- if (offset == sextreg(offset, 1, 12) << 1) {
- code_ptr[0] |= encode_sbimm12(offset);
- return true;
- }
-
- return false;
-}
-
-static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
-
- if (offset == sextreg(offset, 1, 20) << 1) {
- code_ptr[0] |= encode_ujimm20(offset);
- return true;
- }
-
- return false;
-}
-
-static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
-{
- intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
- int32_t lo = sextreg(offset, 0, 12);
- int32_t hi = offset - lo;
-
- if (offset == hi + lo) {
- code_ptr[0] |= encode_uimm20(hi);
- code_ptr[1] |= encode_imm12(lo);
- return true;
- }
-
- return false;
-}
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- uint32_t insn = *code_ptr;
- intptr_t diff;
- bool short_jmp;
-
- tcg_debug_assert(addend == 0);
-
- switch (type) {
- case R_RISCV_BRANCH:
- diff = value - (uintptr_t)code_ptr;
- short_jmp = diff == sextreg(diff, 0, 12);
- if (short_jmp) {
- return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
- } else {
- /* Invert the condition */
- insn = insn ^ (1 << 12);
- /* Clear the offset */
- insn &= 0x01fff07f;
- /* Set the offset to the PC + 8 */
- insn |= encode_sbimm12(8);
-
- /* Move forward */
- code_ptr[0] = insn;
-
- /* Overwrite the NOP with jal x0,value */
- diff = value - (uintptr_t)(code_ptr + 1);
- insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff);
- code_ptr[1] = insn;
-
- return true;
- }
- break;
- case R_RISCV_JAL:
- return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
- case R_RISCV_CALL:
- return reloc_call(code_ptr, (tcg_insn_unit *)value);
- default:
- tcg_abort();
- }
-}
-
-/*
- * TCG intrinsics
- */
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
-{
- if (ret == arg) {
- return true;
- }
- switch (type) {
- case TCG_TYPE_I32:
- case TCG_TYPE_I64:
- tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
- break;
- default:
- g_assert_not_reached();
- }
- return true;
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
- tcg_target_long val)
-{
- tcg_target_long lo, hi, tmp;
- int shift, ret;
-
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
- val = (int32_t)val;
- }
-
- lo = sextreg(val, 0, 12);
- if (val == lo) {
- tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
- return;
- }
-
- hi = val - lo;
- if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
- tcg_out_opc_upper(s, OPC_LUI, rd, hi);
- if (lo != 0) {
- tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
- }
- return;
- }
-
- /* We can only be here if TCG_TARGET_REG_BITS != 32 */
- tmp = tcg_pcrel_diff(s, (void *)val);
- if (tmp == (int32_t)tmp) {
- tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
- tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
- ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
- tcg_debug_assert(ret == true);
- return;
- }
-
- /* Look for a single 20-bit section. */
- shift = ctz64(val);
- tmp = val >> shift;
- if (tmp == sextreg(tmp, 0, 20)) {
- tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
- if (shift > 12) {
- tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
- } else {
- tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
- }
- return;
- }
-
- /* Look for a few high zero bits, with lots of bits set in the middle. */
- shift = clz64(val);
- tmp = val << shift;
- if (tmp == sextreg(tmp, 12, 20) << 12) {
- tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
- tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
- return;
- } else if (tmp == sextreg(tmp, 0, 12)) {
- tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
- tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
- return;
- }
-
- /* Drop into the constant pool. */
- new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
- tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
- tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
-}
-
-static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
-}
-
-static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
- tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
-}
-
-static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
- tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
-}
-
-static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
- tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
-}
-
-static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
- tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
-}
-
-static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
-}
-
-static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
- TCGReg addr, intptr_t offset)
-{
- intptr_t imm12 = sextreg(offset, 0, 12);
-
- if (offset != imm12) {
- intptr_t diff = offset - (uintptr_t)s->code_ptr;
-
- if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
- imm12 = sextreg(diff, 0, 12);
- tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
- if (addr != TCG_REG_ZERO) {
- tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
- }
- }
- addr = TCG_REG_TMP2;
- }
-
- switch (opc) {
- case OPC_SB:
- case OPC_SH:
- case OPC_SW:
- case OPC_SD:
- tcg_out_opc_store(s, opc, addr, data, imm12);
- break;
- case OPC_LB:
- case OPC_LBU:
- case OPC_LH:
- case OPC_LHU:
- case OPC_LW:
- case OPC_LWU:
- case OPC_LD:
- tcg_out_opc_imm(s, opc, data, addr, imm12);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
- tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
-}
-
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
- tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
-}
-
-static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- if (val == 0) {
- tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
- return true;
- }
- return false;
-}
-
-static void tcg_out_addsub2(TCGContext *s,
- TCGReg rl, TCGReg rh,
- TCGReg al, TCGReg ah,
- TCGArg bl, TCGArg bh,
- bool cbl, bool cbh, bool is_sub, bool is32bit)
-{
- const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
- const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
- const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
- TCGReg th = TCG_REG_TMP1;
-
- /* If we have a negative constant such that negating it would
- make the high part zero, we can (usually) eliminate one insn. */
- if (cbl && cbh && bh == -1 && bl != 0) {
- bl = -bl;
- bh = 0;
- is_sub = !is_sub;
- }
-
- /* By operating on the high part first, we get to use the final
- carry operation to move back from the temporary. */
- if (!cbh) {
- tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
- } else if (bh != 0 || ah == rl) {
- tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
- } else {
- th = ah;
- }
-
- /* Note that tcg optimization should eliminate the bl == 0 case. */
- if (is_sub) {
- if (cbl) {
- tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
- tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
- } else {
- tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
- tcg_out_opc_reg(s, opc_sub, rl, al, bl);
- }
- tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
- } else {
- if (cbl) {
- tcg_out_opc_imm(s, opc_addi, rl, al, bl);
- tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
- } else if (rl == al && rl == bl) {
- tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
- tcg_out_opc_reg(s, opc_addi, rl, al, bl);
- } else {
- tcg_out_opc_reg(s, opc_add, rl, al, bl);
- tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
- rl, (rl == bl ? al : bl));
- }
- tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
- }
-}
-
-static const struct {
- RISCVInsn op;
- bool swap;
-} tcg_brcond_to_riscv[] = {
- [TCG_COND_EQ] = { OPC_BEQ, false },
- [TCG_COND_NE] = { OPC_BNE, false },
- [TCG_COND_LT] = { OPC_BLT, false },
- [TCG_COND_GE] = { OPC_BGE, false },
- [TCG_COND_LE] = { OPC_BGE, true },
- [TCG_COND_GT] = { OPC_BLT, true },
- [TCG_COND_LTU] = { OPC_BLTU, false },
- [TCG_COND_GEU] = { OPC_BGEU, false },
- [TCG_COND_LEU] = { OPC_BGEU, true },
- [TCG_COND_GTU] = { OPC_BLTU, true }
-};
-
-static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
- TCGReg arg2, TCGLabel *l)
-{
- RISCVInsn op = tcg_brcond_to_riscv[cond].op;
-
- tcg_debug_assert(op != 0);
-
- if (tcg_brcond_to_riscv[cond].swap) {
- TCGReg t = arg1;
- arg1 = arg2;
- arg2 = t;
- }
-
- if (l->has_value) {
- intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr);
- if (diff == sextreg(diff, 0, 12)) {
- tcg_out_opc_branch(s, op, arg1, arg2, diff);
- } else {
- /* Invert the conditional branch. */
- tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8);
- tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4);
- }
- } else {
- tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
- tcg_out_opc_branch(s, op, arg1, arg2, 0);
- /* NOP to allow patching later */
- tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
- }
-}
-
-static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg arg1, TCGReg arg2)
-{
- switch (cond) {
- case TCG_COND_EQ:
- tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
- tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
- break;
- case TCG_COND_NE:
- tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
- tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
- break;
- case TCG_COND_LT:
- tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
- break;
- case TCG_COND_GE:
- tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
- tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
- break;
- case TCG_COND_LE:
- tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
- tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
- break;
- case TCG_COND_GT:
- tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
- break;
- case TCG_COND_LTU:
- tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
- break;
- case TCG_COND_GEU:
- tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
- tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
- break;
- case TCG_COND_LEU:
- tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
- tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
- break;
- case TCG_COND_GTU:
- tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
- break;
- default:
- g_assert_not_reached();
- break;
- }
-}
-
-static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
- TCGReg bl, TCGReg bh, TCGLabel *l)
-{
- /* todo */
- g_assert_not_reached();
-}
-
-static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
-{
- /* todo */
- g_assert_not_reached();
-}
-
-static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
-{
- ptrdiff_t offset = tcg_pcrel_diff(s, target);
- tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1);
- tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
-}
-
-static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
-{
- TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
- ptrdiff_t offset = tcg_pcrel_diff(s, arg);
- int ret;
-
- if (offset == sextreg(offset, 1, 20) << 1) {
- /* short jump: -2097150 to 2097152 */
- tcg_out_opc_jump(s, OPC_JAL, link, offset);
- } else if (TCG_TARGET_REG_BITS == 32 ||
- offset == sextreg(offset, 1, 31) << 1) {
- /* long jump: -2147483646 to 2147483648 */
- tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
- tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
- ret = reloc_call(s->code_ptr - 2, arg);\
- tcg_debug_assert(ret == true);
- } else if (TCG_TARGET_REG_BITS == 64) {
- /* far jump: 64-bit */
- tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
- tcg_target_long base = (tcg_target_long)arg - imm;
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
- tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
- } else {
- g_assert_not_reached();
- }
-}
-
-static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
-{
- tcg_out_call_int(s, arg, false);
-}
-
-static void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- tcg_insn_unit insn = OPC_FENCE;
-
- if (a0 & TCG_MO_LD_LD) {
- insn |= 0x02200000;
- }
- if (a0 & TCG_MO_ST_LD) {
- insn |= 0x01200000;
- }
- if (a0 & TCG_MO_LD_ST) {
- insn |= 0x02100000;
- }
- if (a0 & TCG_MO_ST_ST) {
- insn |= 0x02200000;
- }
- tcg_out32(s, insn);
-}
-
-/*
- * Load/store and TLB
- */
-
-#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
-
-/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * TCGMemOpIdx oi, uintptr_t ra)
- */
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
-#if TCG_TARGET_REG_BITS == 64
- [MO_LESL] = helper_le_ldsl_mmu,
-#endif
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
-#if TCG_TARGET_REG_BITS == 64
- [MO_BESL] = helper_be_ldsl_mmu,
-#endif
- [MO_BEQ] = helper_be_ldq_mmu,
-};
-
-/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, TCGMemOpIdx oi,
- * uintptr_t ra)
- */
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-
-/* We don't support oversize guests */
-QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
-
-/* We expect to use a 12-bit negative offset from ENV. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
-
-static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
- TCGReg addrh, TCGMemOpIdx oi,
- tcg_insn_unit **label_ptr, bool is_load)
-{
- MemOp opc = get_memop(oi);
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
- tcg_target_long compare_mask;
- int mem_index = get_mmuidx(oi);
- int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
- int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
- int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
- TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
-
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);
-
- tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
- tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
-
- /* Load the tlb comparator and the addend. */
- tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2,
- is_load ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write));
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
- offsetof(CPUTLBEntry, addend));
-
- /* We don't support unaligned accesses. */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
- /* Clear the non-page, non-alignment bits from the address. */
- compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
- if (compare_mask == sextreg(compare_mask, 0, 12)) {
- tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask);
- } else {
- tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask);
- tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
- }
-
- /* Compare masked address with the TLB entry. */
- label_ptr[0] = s->code_ptr;
- tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
- /* NOP to allow patching later */
- tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
-
- /* TLB Hit - translate address using addend. */
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
- addrl = TCG_REG_TMP0;
- }
- tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
-}
-
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
- TCGType ext,
- TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- void *raddr, tcg_insn_unit **label_ptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->type = ext;
- label->datalo_reg = datalo;
- label->datahi_reg = datahi;
- label->addrlo_reg = addrlo;
- label->addrhi_reg = addrhi;
- label->raddr = raddr;
- label->label_ptr[0] = label_ptr[0];
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- TCGMemOpIdx oi = l->oi;
- MemOp opc = get_memop(oi);
- TCGReg a0 = tcg_target_call_iarg_regs[0];
- TCGReg a1 = tcg_target_call_iarg_regs[1];
- TCGReg a2 = tcg_target_call_iarg_regs[2];
- TCGReg a3 = tcg_target_call_iarg_regs[3];
-
- /* We don't support oversize guests */
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- g_assert_not_reached();
- }
-
- /* resolve label address */
- if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
- (intptr_t) s->code_ptr, 0)) {
- return false;
- }
-
- /* call load helper */
- tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
- tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
- tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
- tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
-
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
- tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
-
- tcg_out_goto(s, l->raddr);
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
- TCGMemOpIdx oi = l->oi;
- MemOp opc = get_memop(oi);
- MemOp s_bits = opc & MO_SIZE;
- TCGReg a0 = tcg_target_call_iarg_regs[0];
- TCGReg a1 = tcg_target_call_iarg_regs[1];
- TCGReg a2 = tcg_target_call_iarg_regs[2];
- TCGReg a3 = tcg_target_call_iarg_regs[3];
- TCGReg a4 = tcg_target_call_iarg_regs[4];
-
- /* We don't support oversize guests */
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- g_assert_not_reached();
- }
-
- /* resolve label address */
- if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
- (intptr_t) s->code_ptr, 0)) {
- return false;
- }
-
- /* call store helper */
- tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
- tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
- tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);
- switch (s_bits) {
- case MO_8:
- tcg_out_ext8u(s, a2, a2);
- break;
- case MO_16:
- tcg_out_ext16u(s, a2, a2);
- break;
- default:
- break;
- }
- tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
- tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
-
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
-
- tcg_out_goto(s, l->raddr);
- return true;
-}
-#endif /* CONFIG_SOFTMMU */
-
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, MemOp opc, bool is_64)
-{
- const MemOp bswap = opc & MO_BSWAP;
-
- /* We don't yet handle byteswapping, assert */
- g_assert(!bswap);
-
- switch (opc & (MO_SSIZE)) {
- case MO_UB:
- tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
- break;
- case MO_SB:
- tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
- break;
- case MO_UW:
- tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
- break;
- case MO_SW:
- tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
- break;
- case MO_UL:
- if (TCG_TARGET_REG_BITS == 64 && is_64) {
- tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
- break;
- }
- /* FALLTHRU */
- case MO_SL:
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- break;
- case MO_Q:
- /* Prefer to load from offset 0 first, but allow for overlap. */
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
- } else if (lo != base) {
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
- } else {
- tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
- tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- }
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
-{
- TCGReg addr_regl, addr_regh __attribute__((unused));
- TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
- tcg_insn_unit *label_ptr[1];
-#endif
- TCGReg base = TCG_REG_TMP0;
-
- data_regl = *args++;
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addr_regl = *args++;
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
- add_qemu_ldst_label(s, 1, oi,
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
- data_regl, data_regh, addr_regl, addr_regh,
- s->code_ptr, label_ptr);
-#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
- }
-
- if (guest_base == 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
- } else {
- tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
- }
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
-#endif
-}
-
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, MemOp opc)
-{
- const MemOp bswap = opc & MO_BSWAP;
-
- /* We don't yet handle byteswapping, assert */
- g_assert(!bswap);
-
- switch (opc & (MO_SSIZE)) {
- case MO_8:
- tcg_out_opc_store(s, OPC_SB, base, lo, 0);
- break;
- case MO_16:
- tcg_out_opc_store(s, OPC_SH, base, lo, 0);
- break;
- case MO_32:
- tcg_out_opc_store(s, OPC_SW, base, lo, 0);
- break;
- case MO_64:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_store(s, OPC_SD, base, lo, 0);
- } else {
- tcg_out_opc_store(s, OPC_SW, base, lo, 0);
- tcg_out_opc_store(s, OPC_SW, base, hi, 4);
- }
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
-{
- TCGReg addr_regl, addr_regh __attribute__((unused));
- TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
- tcg_insn_unit *label_ptr[1];
-#endif
- TCGReg base = TCG_REG_TMP0;
-
- data_regl = *args++;
- data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- addr_regl = *args++;
- addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
- add_qemu_ldst_label(s, 0, oi,
- (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
- data_regl, data_regh, addr_regl, addr_regh,
- s->code_ptr, label_ptr);
-#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
- }
-
- if (guest_base == 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
- } else {
- tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
- }
- tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
-#endif
-}
-
-static tcg_insn_unit *tb_ret_addr;
-
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
-{
- TCGArg a0 = args[0];
- TCGArg a1 = args[1];
- TCGArg a2 = args[2];
- int c2 = const_args[2];
-
- switch (opc) {
- case INDEX_op_exit_tb:
- /* Reuse the zeroing that exists for goto_ptr. */
- if (a0 == 0) {
- tcg_out_call_int(s, s->code_gen_epilogue, true);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
- tcg_out_call_int(s, tb_ret_addr, true);
- }
- break;
-
- case INDEX_op_goto_tb:
- assert(s->tb_jmp_insn_offset == 0);
- /* indirect jump method */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
- (uintptr_t)(s->tb_jmp_target_addr + a0));
- tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
- set_jmp_reset_offset(s, a0);
- break;
-
- case INDEX_op_goto_ptr:
- tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
- break;
-
- case INDEX_op_br:
- tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
- tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
- break;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
- break;
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld8s_i64:
- tcg_out_ldst(s, OPC_LB, a0, a1, a2);
- break;
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
- break;
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld16s_i64:
- tcg_out_ldst(s, OPC_LH, a0, a1, a2);
- break;
- case INDEX_op_ld32u_i64:
- tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
- break;
- case INDEX_op_ld_i32:
- case INDEX_op_ld32s_i64:
- tcg_out_ldst(s, OPC_LW, a0, a1, a2);
- break;
- case INDEX_op_ld_i64:
- tcg_out_ldst(s, OPC_LD, a0, a1, a2);
- break;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_ldst(s, OPC_SB, a0, a1, a2);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_ldst(s, OPC_SH, a0, a1, a2);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, OPC_SW, a0, a1, a2);
- break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, OPC_SD, a0, a1, a2);
- break;
-
- case INDEX_op_add_i32:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
- }
- break;
- case INDEX_op_add_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
- }
- break;
-
- case INDEX_op_sub_i32:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
- } else {
- tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
- }
- break;
- case INDEX_op_sub_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
- } else {
- tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
- }
- break;
-
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
- }
- break;
-
- case INDEX_op_or_i32:
- case INDEX_op_or_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
- }
- break;
-
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
- }
- break;
-
- case INDEX_op_not_i32:
- case INDEX_op_not_i64:
- tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
- break;
-
- case INDEX_op_neg_i32:
- tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
- break;
- case INDEX_op_neg_i64:
- tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
- break;
-
- case INDEX_op_mul_i32:
- tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
- break;
- case INDEX_op_mul_i64:
- tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
- break;
-
- case INDEX_op_div_i32:
- tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
- break;
- case INDEX_op_div_i64:
- tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
- break;
-
- case INDEX_op_divu_i32:
- tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
- break;
- case INDEX_op_divu_i64:
- tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
- break;
-
- case INDEX_op_rem_i32:
- tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
- break;
- case INDEX_op_rem_i64:
- tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
- break;
-
- case INDEX_op_remu_i32:
- tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
- break;
- case INDEX_op_remu_i64:
- tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
- break;
-
- case INDEX_op_shl_i32:
- if (c2) {
- tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
- }
- break;
- case INDEX_op_shl_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
- }
- break;
-
- case INDEX_op_shr_i32:
- if (c2) {
- tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
- }
- break;
- case INDEX_op_shr_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
- }
- break;
-
- case INDEX_op_sar_i32:
- if (c2) {
- tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
- }
- break;
- case INDEX_op_sar_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
- }
- break;
-
- case INDEX_op_add2_i32:
- tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
- const_args[4], const_args[5], false, true);
- break;
- case INDEX_op_add2_i64:
- tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
- const_args[4], const_args[5], false, false);
- break;
- case INDEX_op_sub2_i32:
- tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
- const_args[4], const_args[5], true, true);
- break;
- case INDEX_op_sub2_i64:
- tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
- const_args[4], const_args[5], true, false);
- break;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
- break;
- case INDEX_op_brcond2_i32:
- tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
- break;
-
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- tcg_out_setcond(s, args[3], a0, a1, a2);
- break;
- case INDEX_op_setcond2_i32:
- tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
- break;
-
- case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, false);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, true);
- break;
- case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, false);
- break;
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, true);
- break;
-
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext8u_i64:
- tcg_out_ext8u(s, a0, a1);
- break;
-
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext16u_i64:
- tcg_out_ext16u(s, a0, a1);
- break;
-
- case INDEX_op_ext32u_i64:
- case INDEX_op_extu_i32_i64:
- tcg_out_ext32u(s, a0, a1);
- break;
-
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- tcg_out_ext8s(s, a0, a1);
- break;
-
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- tcg_out_ext16s(s, a0, a1);
- break;
-
- case INDEX_op_ext32s_i64:
- case INDEX_op_extrl_i64_i32:
- case INDEX_op_ext_i32_i64:
- tcg_out_ext32s(s, a0, a1);
- break;
-
- case INDEX_op_extrh_i64_i32:
- tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
- break;
-
- case INDEX_op_mulsh_i32:
- case INDEX_op_mulsh_i64:
- tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
- break;
-
- case INDEX_op_muluh_i32:
- case INDEX_op_muluh_i64:
- tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, a0);
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- g_assert_not_reached();
- }
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r
- = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r
- = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef rZ_r
- = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef rZ_rZ
- = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef rZ_rZ_rZ_rZ
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_ri
- = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI
- = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_L
- = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef r_r_L
- = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L
- = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef LZ_L
- = { .args_ct_str = { "LZ", "L" } };
- static const TCGTargetOpDef LZ_L_L
- = { .args_ct_str = { "LZ", "L", "L" } };
- static const TCGTargetOpDef LZ_LZ_L
- = { .args_ct_str = { "LZ", "LZ", "L" } };
- static const TCGTargetOpDef LZ_LZ_L_L
- = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
- static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_not_i32:
- case INDEX_op_neg_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_not_i64:
- case INDEX_op_neg_i64:
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext8u_i64:
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext16u_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_extrl_i64_i32:
- case INDEX_op_extrh_i64_i32:
- case INDEX_op_ext_i32_i64:
- return &r_r;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return &rZ_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_and_i32:
- case INDEX_op_or_i32:
- case INDEX_op_xor_i32:
- case INDEX_op_add_i64:
- case INDEX_op_and_i64:
- case INDEX_op_or_i64:
- case INDEX_op_xor_i64:
- return &r_r_rI;
-
- case INDEX_op_sub_i32:
- case INDEX_op_sub_i64:
- return &r_rZ_rN;
-
- case INDEX_op_mul_i32:
- case INDEX_op_mulsh_i32:
- case INDEX_op_muluh_i32:
- case INDEX_op_div_i32:
- case INDEX_op_divu_i32:
- case INDEX_op_rem_i32:
- case INDEX_op_remu_i32:
- case INDEX_op_setcond_i32:
- case INDEX_op_mul_i64:
- case INDEX_op_mulsh_i64:
- case INDEX_op_muluh_i64:
- case INDEX_op_div_i64:
- case INDEX_op_divu_i64:
- case INDEX_op_rem_i64:
- case INDEX_op_remu_i64:
- case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
-
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- return &r_r_ri;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return &rZ_rZ;
-
- case INDEX_op_add2_i32:
- case INDEX_op_add2_i64:
- case INDEX_op_sub2_i32:
- case INDEX_op_sub2_i64:
- return &r_r_rZ_rZ_rM_rM;
-
- case INDEX_op_brcond2_i32:
- return &rZ_rZ_rZ_rZ;
-
- case INDEX_op_setcond2_i32:
- return &r_rZ_rZ_rZ_rZ;
-
- case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
- case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
- case INDEX_op_qemu_ld_i64:
- return TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L;
- case INDEX_op_qemu_st_i64:
- return TCG_TARGET_REG_BITS == 64 ? &LZ_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
- : &LZ_LZ_L_L;
-
- default:
- return NULL;
- }
-}
-
-static const int tcg_target_callee_save_regs[] = {
- TCG_REG_S0, /* used for the global env (TCG_AREG0) */
- TCG_REG_S1,
- TCG_REG_S2,
- TCG_REG_S3,
- TCG_REG_S4,
- TCG_REG_S5,
- TCG_REG_S6,
- TCG_REG_S7,
- TCG_REG_S8,
- TCG_REG_S9,
- TCG_REG_S10,
- TCG_REG_S11,
- TCG_REG_RA, /* should be last for ABI compliance */
-};
-
-/* Stack frame parameters. */
-#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
-#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
-#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
-#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
- + TCG_TARGET_STACK_ALIGN - 1) \
- & -TCG_TARGET_STACK_ALIGN)
-#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
-
-/* We're expecting to be able to use an immediate for frame allocation. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
-
-/* Generate global QEMU prologue and epilogue code */
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- int i;
-
- tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
-
- /* TB prologue */
- tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
- tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
- TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
- }
-
-#if !defined(CONFIG_SOFTMMU)
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
- tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
-#endif
-
- /* Call generated code */
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
-
- /* Return path for goto_ptr. Set return value to 0 */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
-
- /* TB epilogue */
- tb_ret_addr = s->code_ptr;
- for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
- tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
- TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
- }
-
- tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
- tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
- }
-
- tcg_target_call_clobber_regs = -1u;
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
- tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
-} DebugFrame;
-
-#define ELF_HOST_MACHINE EM_RISCV
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
- .h.cie.return_column = TCG_REG_RA,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
- 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
- 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
- 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
- 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
- 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
- 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
- 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
- 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
- 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
- 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
- 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
- }
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
+ * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
+ * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* We only support generating code for 64-bit mode. */
+#if TCG_TARGET_REG_BITS != 64
+#error "unsupported code generation mode"
+#endif
+
+#include "../tcg-pool.c.inc"
+#include "elf.h"
+
+/* ??? The translation blocks produced by TCG are generally small enough to
+ be entirely reachable with a 16-bit displacement. Leaving the option for
+ a 32-bit displacement here Just In Case. */
+#define USE_LONG_BRANCHES 0
+
+#define TCG_CT_CONST_S16 0x100
+#define TCG_CT_CONST_S32 0x200
+#define TCG_CT_CONST_S33 0x400
+#define TCG_CT_CONST_ZERO 0x800
+
+/* Several places within the instruction set 0 means "no register"
+ rather than TCG_REG_R0. */
+#define TCG_REG_NONE 0
+
+/* A scratch register that may be be used throughout the backend. */
+#define TCG_TMP0 TCG_REG_R1
+
+/* A scratch register that holds a pointer to the beginning of the TB.
+ We don't need this when we have pc-relative loads with the general
+ instructions extension facility. */
+#define TCG_REG_TB TCG_REG_R12
+#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))
+
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_R13
+#endif
+
+/* All of the following instructions are prefixed with their instruction
+ format, and are defined as 8- or 16-bit quantities, even when the two
+ halves of the 16-bit quantity may appear 32 bits apart in the insn.
+ This makes it easy to copy the values from the tables in Appendix B. */
+typedef enum S390Opcode {
+ RIL_AFI = 0xc209,
+ RIL_AGFI = 0xc208,
+ RIL_ALFI = 0xc20b,
+ RIL_ALGFI = 0xc20a,
+ RIL_BRASL = 0xc005,
+ RIL_BRCL = 0xc004,
+ RIL_CFI = 0xc20d,
+ RIL_CGFI = 0xc20c,
+ RIL_CLFI = 0xc20f,
+ RIL_CLGFI = 0xc20e,
+ RIL_CLRL = 0xc60f,
+ RIL_CLGRL = 0xc60a,
+ RIL_CRL = 0xc60d,
+ RIL_CGRL = 0xc608,
+ RIL_IIHF = 0xc008,
+ RIL_IILF = 0xc009,
+ RIL_LARL = 0xc000,
+ RIL_LGFI = 0xc001,
+ RIL_LGRL = 0xc408,
+ RIL_LLIHF = 0xc00e,
+ RIL_LLILF = 0xc00f,
+ RIL_LRL = 0xc40d,
+ RIL_MSFI = 0xc201,
+ RIL_MSGFI = 0xc200,
+ RIL_NIHF = 0xc00a,
+ RIL_NILF = 0xc00b,
+ RIL_OIHF = 0xc00c,
+ RIL_OILF = 0xc00d,
+ RIL_SLFI = 0xc205,
+ RIL_SLGFI = 0xc204,
+ RIL_XIHF = 0xc006,
+ RIL_XILF = 0xc007,
+
+ RI_AGHI = 0xa70b,
+ RI_AHI = 0xa70a,
+ RI_BRC = 0xa704,
+ RI_CHI = 0xa70e,
+ RI_CGHI = 0xa70f,
+ RI_IIHH = 0xa500,
+ RI_IIHL = 0xa501,
+ RI_IILH = 0xa502,
+ RI_IILL = 0xa503,
+ RI_LGHI = 0xa709,
+ RI_LLIHH = 0xa50c,
+ RI_LLIHL = 0xa50d,
+ RI_LLILH = 0xa50e,
+ RI_LLILL = 0xa50f,
+ RI_MGHI = 0xa70d,
+ RI_MHI = 0xa70c,
+ RI_NIHH = 0xa504,
+ RI_NIHL = 0xa505,
+ RI_NILH = 0xa506,
+ RI_NILL = 0xa507,
+ RI_OIHH = 0xa508,
+ RI_OIHL = 0xa509,
+ RI_OILH = 0xa50a,
+ RI_OILL = 0xa50b,
+
+ RIE_CGIJ = 0xec7c,
+ RIE_CGRJ = 0xec64,
+ RIE_CIJ = 0xec7e,
+ RIE_CLGRJ = 0xec65,
+ RIE_CLIJ = 0xec7f,
+ RIE_CLGIJ = 0xec7d,
+ RIE_CLRJ = 0xec77,
+ RIE_CRJ = 0xec76,
+ RIE_LOCGHI = 0xec46,
+ RIE_RISBG = 0xec55,
+
+ RRE_AGR = 0xb908,
+ RRE_ALGR = 0xb90a,
+ RRE_ALCR = 0xb998,
+ RRE_ALCGR = 0xb988,
+ RRE_CGR = 0xb920,
+ RRE_CLGR = 0xb921,
+ RRE_DLGR = 0xb987,
+ RRE_DLR = 0xb997,
+ RRE_DSGFR = 0xb91d,
+ RRE_DSGR = 0xb90d,
+ RRE_FLOGR = 0xb983,
+ RRE_LGBR = 0xb906,
+ RRE_LCGR = 0xb903,
+ RRE_LGFR = 0xb914,
+ RRE_LGHR = 0xb907,
+ RRE_LGR = 0xb904,
+ RRE_LLGCR = 0xb984,
+ RRE_LLGFR = 0xb916,
+ RRE_LLGHR = 0xb985,
+ RRE_LRVR = 0xb91f,
+ RRE_LRVGR = 0xb90f,
+ RRE_LTGR = 0xb902,
+ RRE_MLGR = 0xb986,
+ RRE_MSGR = 0xb90c,
+ RRE_MSR = 0xb252,
+ RRE_NGR = 0xb980,
+ RRE_OGR = 0xb981,
+ RRE_SGR = 0xb909,
+ RRE_SLGR = 0xb90b,
+ RRE_SLBR = 0xb999,
+ RRE_SLBGR = 0xb989,
+ RRE_XGR = 0xb982,
+
+ RRF_LOCR = 0xb9f2,
+ RRF_LOCGR = 0xb9e2,
+ RRF_NRK = 0xb9f4,
+ RRF_NGRK = 0xb9e4,
+ RRF_ORK = 0xb9f6,
+ RRF_OGRK = 0xb9e6,
+ RRF_SRK = 0xb9f9,
+ RRF_SGRK = 0xb9e9,
+ RRF_SLRK = 0xb9fb,
+ RRF_SLGRK = 0xb9eb,
+ RRF_XRK = 0xb9f7,
+ RRF_XGRK = 0xb9e7,
+
+ RR_AR = 0x1a,
+ RR_ALR = 0x1e,
+ RR_BASR = 0x0d,
+ RR_BCR = 0x07,
+ RR_CLR = 0x15,
+ RR_CR = 0x19,
+ RR_DR = 0x1d,
+ RR_LCR = 0x13,
+ RR_LR = 0x18,
+ RR_LTR = 0x12,
+ RR_NR = 0x14,
+ RR_OR = 0x16,
+ RR_SR = 0x1b,
+ RR_SLR = 0x1f,
+ RR_XR = 0x17,
+
+ RSY_RLL = 0xeb1d,
+ RSY_RLLG = 0xeb1c,
+ RSY_SLLG = 0xeb0d,
+ RSY_SLLK = 0xebdf,
+ RSY_SRAG = 0xeb0a,
+ RSY_SRAK = 0xebdc,
+ RSY_SRLG = 0xeb0c,
+ RSY_SRLK = 0xebde,
+
+ RS_SLL = 0x89,
+ RS_SRA = 0x8a,
+ RS_SRL = 0x88,
+
+ RXY_AG = 0xe308,
+ RXY_AY = 0xe35a,
+ RXY_CG = 0xe320,
+ RXY_CLG = 0xe321,
+ RXY_CLY = 0xe355,
+ RXY_CY = 0xe359,
+ RXY_LAY = 0xe371,
+ RXY_LB = 0xe376,
+ RXY_LG = 0xe304,
+ RXY_LGB = 0xe377,
+ RXY_LGF = 0xe314,
+ RXY_LGH = 0xe315,
+ RXY_LHY = 0xe378,
+ RXY_LLGC = 0xe390,
+ RXY_LLGF = 0xe316,
+ RXY_LLGH = 0xe391,
+ RXY_LMG = 0xeb04,
+ RXY_LRV = 0xe31e,
+ RXY_LRVG = 0xe30f,
+ RXY_LRVH = 0xe31f,
+ RXY_LY = 0xe358,
+ RXY_NG = 0xe380,
+ RXY_OG = 0xe381,
+ RXY_STCY = 0xe372,
+ RXY_STG = 0xe324,
+ RXY_STHY = 0xe370,
+ RXY_STMG = 0xeb24,
+ RXY_STRV = 0xe33e,
+ RXY_STRVG = 0xe32f,
+ RXY_STRVH = 0xe33f,
+ RXY_STY = 0xe350,
+ RXY_XG = 0xe382,
+
+ RX_A = 0x5a,
+ RX_C = 0x59,
+ RX_L = 0x58,
+ RX_LA = 0x41,
+ RX_LH = 0x48,
+ RX_ST = 0x50,
+ RX_STC = 0x42,
+ RX_STH = 0x40,
+
+ NOP = 0x0707,
+} S390Opcode;
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
+ "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
+};
+#endif
+
+/* Since R6 is a potential argument register, choose it last of the
+ call-saved registers. Likewise prefer the call-clobbered registers
+ in reverse order to maximize the chance of avoiding the arguments. */
+static const int tcg_target_reg_alloc_order[] = {
+ /* Call saved registers. */
+ TCG_REG_R13,
+ TCG_REG_R12,
+ TCG_REG_R11,
+ TCG_REG_R10,
+ TCG_REG_R9,
+ TCG_REG_R8,
+ TCG_REG_R7,
+ TCG_REG_R6,
+ /* Call clobbered registers. */
+ TCG_REG_R14,
+ TCG_REG_R0,
+ TCG_REG_R1,
+ /* Argument registers, in reverse order of allocation. */
+ TCG_REG_R5,
+ TCG_REG_R4,
+ TCG_REG_R3,
+ TCG_REG_R2,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_R2,
+ TCG_REG_R3,
+ TCG_REG_R4,
+ TCG_REG_R5,
+ TCG_REG_R6,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_R2,
+};
+
+#define S390_CC_EQ 8
+#define S390_CC_LT 4
+#define S390_CC_GT 2
+#define S390_CC_OV 1
+#define S390_CC_NE (S390_CC_LT | S390_CC_GT)
+#define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
+#define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
+#define S390_CC_NEVER 0
+#define S390_CC_ALWAYS 15
+
+/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
+static const uint8_t tcg_cond_to_s390_cond[] = {
+ [TCG_COND_EQ] = S390_CC_EQ,
+ [TCG_COND_NE] = S390_CC_NE,
+ [TCG_COND_LT] = S390_CC_LT,
+ [TCG_COND_LE] = S390_CC_LE,
+ [TCG_COND_GT] = S390_CC_GT,
+ [TCG_COND_GE] = S390_CC_GE,
+ [TCG_COND_LTU] = S390_CC_LT,
+ [TCG_COND_LEU] = S390_CC_LE,
+ [TCG_COND_GTU] = S390_CC_GT,
+ [TCG_COND_GEU] = S390_CC_GE,
+};
+
+/* Condition codes that result from a LOAD AND TEST. Here, we have no
+ unsigned instruction variation, however since the test is vs zero we
+ can re-map the outcomes appropriately. */
+static const uint8_t tcg_cond_to_ltr_cond[] = {
+ [TCG_COND_EQ] = S390_CC_EQ,
+ [TCG_COND_NE] = S390_CC_NE,
+ [TCG_COND_LT] = S390_CC_LT,
+ [TCG_COND_LE] = S390_CC_LE,
+ [TCG_COND_GT] = S390_CC_GT,
+ [TCG_COND_GE] = S390_CC_GE,
+ [TCG_COND_LTU] = S390_CC_NEVER,
+ [TCG_COND_LEU] = S390_CC_EQ,
+ [TCG_COND_GTU] = S390_CC_NE,
+ [TCG_COND_GEU] = S390_CC_ALWAYS,
+};
+
+#ifdef CONFIG_SOFTMMU
+static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LESW] = helper_le_ldsw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LESL] = helper_le_ldsl_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BESW] = helper_be_ldsw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BESL] = helper_be_ldsl_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+};
+
+static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+#endif
+
+static tcg_insn_unit *tb_ret_addr;
+uint64_t s390_facilities;
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ intptr_t pcrel2;
+ uint32_t old;
+
+ value += addend;
+ pcrel2 = (tcg_insn_unit *)value - code_ptr;
+
+ switch (type) {
+ case R_390_PC16DBL:
+ if (pcrel2 == (int16_t)pcrel2) {
+ tcg_patch16(code_ptr, pcrel2);
+ return true;
+ }
+ break;
+ case R_390_PC32DBL:
+ if (pcrel2 == (int32_t)pcrel2) {
+ tcg_patch32(code_ptr, pcrel2);
+ return true;
+ }
+ break;
+ case R_390_20:
+ if (value == sextract64(value, 0, 20)) {
+ old = *(uint32_t *)code_ptr & 0xf00000ff;
+ old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
+ tcg_patch32(code_ptr, old);
+ return true;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return false;
+}
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'r': /* all registers */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffff;
+ break;
+ case 'L': /* qemu_ld/st constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+ break;
+ case 'a': /* force R2 for division */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
+ break;
+ case 'b': /* force R3 for division */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0;
+ tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
+ break;
+ case 'A':
+ ct->ct |= TCG_CT_CONST_S33;
+ break;
+ case 'I':
+ ct->ct |= TCG_CT_CONST_S16;
+ break;
+ case 'J':
+ ct->ct |= TCG_CT_CONST_S32;
+ break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* Test if a constant matches the constraint. */
+static int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct = arg_ct->ct;
+
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ /* The following are mutually exclusive. */
+ if (ct & TCG_CT_CONST_S16) {
+ return val == (int16_t)val;
+ } else if (ct & TCG_CT_CONST_S32) {
+ return val == (int32_t)val;
+ } else if (ct & TCG_CT_CONST_S33) {
+ return val >= -0xffffffffll && val <= 0xffffffffll;
+ } else if (ct & TCG_CT_CONST_ZERO) {
+ return val == 0;
+ }
+
+ return 0;
+}
+
+/* Emit instructions according to the given instruction format. */
+
+static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
+{
+ tcg_out16(s, (op << 8) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
+ TCGReg r1, TCGReg r2)
+{
+ tcg_out32(s, (op << 16) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
+ TCGReg r1, TCGReg r2, int m3)
+{
+ tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
+{
+ tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
+}
+
+static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
+ int i2, int m3)
+{
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
+ tcg_out32(s, (i2 << 16) | (op & 0xff));
+}
+
+static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
+{
+ tcg_out16(s, op | (r1 << 4));
+ tcg_out32(s, i2);
+}
+
+static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
+ TCGReg b2, TCGReg r3, int disp)
+{
+ tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
+ | (disp & 0xfff));
+}
+
+static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
+ TCGReg b2, TCGReg r3, int disp)
+{
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
+ tcg_out32(s, (op & 0xff) | (b2 << 28)
+ | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
+}
+
+#define tcg_out_insn_RX tcg_out_insn_RS
+#define tcg_out_insn_RXY tcg_out_insn_RSY
+
+/* Emit an opcode with "type-checking" of the format. */
+#define tcg_out_insn(S, FMT, OP, ...) \
+ glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
+
+
+/* emit 64-bit shifts */
+static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
+ TCGReg src, TCGReg sh_reg, int sh_imm)
+{
+ tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
+}
+
+/* emit 32-bit shifts */
+static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
+ TCGReg sh_reg, int sh_imm)
+{
+ tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
+}
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
+{
+ if (src != dst) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, LR, dst, src);
+ } else {
+ tcg_out_insn(s, RRE, LGR, dst, src);
+ }
+ }
+ return true;
+}
+
+static const S390Opcode lli_insns[4] = {
+ RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
+};
+
+static bool maybe_out_small_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long sval)
+{
+ tcg_target_ulong uval = sval;
+ int i;
+
+ if (type == TCG_TYPE_I32) {
+ uval = (uint32_t)sval;
+ sval = (int32_t)sval;
+ }
+
+ /* Try all 32-bit insns that can load it in one go. */
+ if (sval >= -0x8000 && sval < 0x8000) {
+ tcg_out_insn(s, RI, LGHI, ret, sval);
+ return true;
+ }
+
+ for (i = 0; i < 4; i++) {
+ tcg_target_long mask = 0xffffull << i*16;
+ if ((uval & mask) == uval) {
+ tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/* load a register with an immediate value */
+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long sval, bool in_prologue)
+{
+ tcg_target_ulong uval;
+
+ /* Try all 32-bit insns that can load it in one go. */
+ if (maybe_out_small_movi(s, type, ret, sval)) {
+ return;
+ }
+
+ uval = sval;
+ if (type == TCG_TYPE_I32) {
+ uval = (uint32_t)sval;
+ sval = (int32_t)sval;
+ }
+
+ /* Try all 48-bit insns that can load it in one go. */
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ if (sval == (int32_t)sval) {
+ tcg_out_insn(s, RIL, LGFI, ret, sval);
+ return;
+ }
+ if (uval <= 0xffffffff) {
+ tcg_out_insn(s, RIL, LLILF, ret, uval);
+ return;
+ }
+ if ((uval & 0xffffffff) == 0) {
+ tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);
+ return;
+ }
+ }
+
+ /* Try for PC-relative address load. For odd addresses,
+ attempt to use an offset from the start of the TB. */
+ if ((sval & 1) == 0) {
+ ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
+ if (off == (int32_t)off) {
+ tcg_out_insn(s, RIL, LARL, ret, off);
+ return;
+ }
+ } else if (USE_REG_TB && !in_prologue) {
+ ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr;
+ if (off == sextract64(off, 0, 20)) {
+ /* This is certain to be an address within TB, and therefore
+ OFF will be negative; don't try RX_LA. */
+ tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);
+ return;
+ }
+ }
+
+ /* A 32-bit unsigned value can be loaded in 2 insns. And given
+ that LLILL, LLIHL, LLILF above did not succeed, we know that
+ both insns are required. */
+ if (uval <= 0xffffffff) {
+ tcg_out_insn(s, RI, LLILL, ret, uval);
+ tcg_out_insn(s, RI, IILH, ret, uval >> 16);
+ return;
+ }
+
+ /* Otherwise, stuff it in the constant pool. */
+ if (s390_facilities & FACILITY_GEN_INST_EXT) {
+ tcg_out_insn(s, RIL, LGRL, ret, 0);
+ new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
+ } else if (USE_REG_TB && !in_prologue) {
+ tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
+ -(intptr_t)s->code_gen_ptr);
+ } else {
+ TCGReg base = ret ? ret : TCG_TMP0;
+ tcg_out_insn(s, RIL, LARL, base, 0);
+ new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
+ tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0);
+ }
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long sval)
+{
+ tcg_out_movi_int(s, type, ret, sval, false);
+}
+
+/* Emit a load/store type instruction. Inputs are:
+ DATA: The register to be loaded or stored.
+ BASE+OFS: The effective address.
+ OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
+ OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
+
+static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
+ TCGReg data, TCGReg base, TCGReg index,
+ tcg_target_long ofs)
+{
+ if (ofs < -0x80000 || ofs >= 0x80000) {
+ /* Combine the low 20 bits of the offset with the actual load insn;
+ the high 44 bits must come from an immediate load. */
+ tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
+ ofs = low;
+
+ /* If we were already given an index register, add it in. */
+ if (index != TCG_REG_NONE) {
+ tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
+ }
+ index = TCG_TMP0;
+ }
+
+ if (opc_rx && ofs >= 0 && ofs < 0x1000) {
+ tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
+ } else {
+ tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
+ }
+}
+
+
+/* load data without address translation or endianness conversion */
+static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, intptr_t ofs)
+{
+ if (type == TCG_TYPE_I32) {
+ tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
+ } else {
+ tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
+ }
+}
+
+static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, intptr_t ofs)
+{
+ if (type == TCG_TYPE_I32) {
+ tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
+ } else {
+ tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
+ }
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ return false;
+}
+
+/* load data from an absolute host address */
+static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
+{
+ intptr_t addr = (intptr_t)abs;
+
+ if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
+ ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
+ if (disp == (int32_t)disp) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RIL, LRL, dest, disp);
+ } else {
+ tcg_out_insn(s, RIL, LGRL, dest, disp);
+ }
+ return;
+ }
+ }
+ if (USE_REG_TB) {
+ ptrdiff_t disp = abs - (void *)s->code_gen_ptr;
+ if (disp == sextract64(disp, 0, 20)) {
+ tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
+ return;
+ }
+ }
+
+ tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
+ tcg_out_ld(s, type, dest, dest, addr & 0xffff);
+}
+
+static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
+ int msb, int lsb, int ofs, int z)
+{
+ /* Format RIE-f */
+ tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
+ tcg_out16(s, (msb << 8) | (z << 7) | lsb);
+ tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
+}
+
+static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ tcg_out_insn(s, RRE, LGBR, dest, src);
+ return;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ if (dest == src) {
+ tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
+ }
+ tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
+ tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
+ }
+}
+
+static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ tcg_out_insn(s, RRE, LLGCR, dest, src);
+ return;
+ }
+
+ if (dest == src) {
+ tcg_out_movi(s, type, TCG_TMP0, 0xff);
+ src = TCG_TMP0;
+ } else {
+ tcg_out_movi(s, type, dest, 0xff);
+ }
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, NR, dest, src);
+ } else {
+ tcg_out_insn(s, RRE, NGR, dest, src);
+ }
+}
+
+static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ tcg_out_insn(s, RRE, LGHR, dest, src);
+ return;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ if (dest == src) {
+ tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
+ }
+ tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
+ tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
+ }
+}
+
+static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ tcg_out_insn(s, RRE, LLGHR, dest, src);
+ return;
+ }
+
+ if (dest == src) {
+ tcg_out_movi(s, type, TCG_TMP0, 0xffff);
+ src = TCG_TMP0;
+ } else {
+ tcg_out_movi(s, type, dest, 0xffff);
+ }
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, NR, dest, src);
+ } else {
+ tcg_out_insn(s, RRE, NGR, dest, src);
+ }
+}
+
+static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
+{
+ tcg_out_insn(s, RRE, LGFR, dest, src);
+}
+
+static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
+{
+ tcg_out_insn(s, RRE, LLGFR, dest, src);
+}
+
+/* Accept bit patterns like these:
+ 0....01....1
+ 1....10....0
+ 1..10..01..1
+ 0..01..10..0
+ Copied from gcc sources. */
+static inline bool risbg_mask(uint64_t c)
+{
+ uint64_t lsb;
+ /* We don't change the number of transitions by inverting,
+ so make sure we start with the LSB zero. */
+ if (c & 1) {
+ c = ~c;
+ }
+ /* Reject all zeros or all ones. */
+ if (c == 0) {
+ return false;
+ }
+ /* Find the first transition. */
+ lsb = c & -c;
+ /* Invert to look for a second transition. */
+ c = ~c;
+ /* Erase the first transition. */
+ c &= -lsb;
+ /* Find the second transition, if any. */
+ lsb = c & -c;
+ /* Match if all the bits are 1's, or if c is zero. */
+ return c == -lsb;
+}
+
+static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
+{
+ int msb, lsb;
+ if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
+ /* Achieve wraparound by swapping msb and lsb. */
+ msb = 64 - ctz64(~val);
+ lsb = clz64(~val) - 1;
+ } else {
+ msb = clz64(val);
+ lsb = 63 - ctz64(val);
+ }
+ tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
+}
+
+static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
+{
+ static const S390Opcode ni_insns[4] = {
+ RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
+ };
+ static const S390Opcode nif_insns[2] = {
+ RIL_NILF, RIL_NIHF
+ };
+ uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
+ int i;
+
+ /* Look for the zero-extensions. */
+ if ((val & valid) == 0xffffffff) {
+ tgen_ext32u(s, dest, dest);
+ return;
+ }
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ if ((val & valid) == 0xff) {
+ tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
+ return;
+ }
+ if ((val & valid) == 0xffff) {
+ tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
+ return;
+ }
+ }
+
+ /* Try all 32-bit insns that can perform it in one go. */
+ for (i = 0; i < 4; i++) {
+ tcg_target_ulong mask = ~(0xffffull << i*16);
+ if (((val | ~valid) & mask) == mask) {
+ tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
+ return;
+ }
+ }
+
+ /* Try all 48-bit insns that can perform it in one go. */
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ for (i = 0; i < 2; i++) {
+ tcg_target_ulong mask = ~(0xffffffffull << i*32);
+ if (((val | ~valid) & mask) == mask) {
+ tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
+ return;
+ }
+ }
+ }
+ if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
+ tgen_andi_risbg(s, dest, dest, val);
+ return;
+ }
+
+ /* Use the constant pool if USE_REG_TB, but not for small constants. */
+ if (USE_REG_TB) {
+ if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) {
+ tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2,
+ -(intptr_t)s->code_gen_ptr);
+ return;
+ }
+ } else {
+ tcg_out_movi(s, type, TCG_TMP0, val);
+ }
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
+ } else {
+ tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
+ }
+}
+
+static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
+{
+ static const S390Opcode oi_insns[4] = {
+ RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
+ };
+ static const S390Opcode oif_insns[2] = {
+ RIL_OILF, RIL_OIHF
+ };
+
+ int i;
+
+ /* Look for no-op. */
+ if (unlikely(val == 0)) {
+ return;
+ }
+
+ /* Try all 32-bit insns that can perform it in one go. */
+ for (i = 0; i < 4; i++) {
+ tcg_target_ulong mask = (0xffffull << i*16);
+ if ((val & mask) != 0 && (val & ~mask) == 0) {
+ tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
+ return;
+ }
+ }
+
+ /* Try all 48-bit insns that can perform it in one go. */
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ for (i = 0; i < 2; i++) {
+ tcg_target_ulong mask = (0xffffffffull << i*32);
+ if ((val & mask) != 0 && (val & ~mask) == 0) {
+ tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
+ return;
+ }
+ }
+ }
+
+ /* Use the constant pool if USE_REG_TB, but not for small constants. */
+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, OR, dest, TCG_TMP0);
+ } else {
+ tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);
+ }
+ } else if (USE_REG_TB) {
+ tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,
+ -(intptr_t)s->code_gen_ptr);
+ } else {
+ /* Perform the OR via sequential modifications to the high and
+ low parts. Do this via recursion to handle 16-bit vs 32-bit
+ masks in each half. */
+ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
+ tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
+ tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
+ }
+}
+
+static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
+{
+ /* Try all 48-bit insns that can perform it in one go. */
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ if ((val & 0xffffffff00000000ull) == 0) {
+ tcg_out_insn(s, RIL, XILF, dest, val);
+ return;
+ }
+ if ((val & 0x00000000ffffffffull) == 0) {
+ tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
+ return;
+ }
+ }
+
+ /* Use the constant pool if USE_REG_TB, but not for small constants. */
+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, XR, dest, TCG_TMP0);
+ } else {
+ tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);
+ }
+ } else if (USE_REG_TB) {
+ tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,
+ -(intptr_t)s->code_gen_ptr);
+ } else {
+ /* Perform the xor by parts. */
+ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
+ if (val & 0xffffffff) {
+ tcg_out_insn(s, RIL, XILF, dest, val);
+ }
+ if (val > 0xffffffff) {
+ tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
+ }
+ }
+}
+
+static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
+ TCGArg c2, bool c2const, bool need_carry)
+{
+ bool is_unsigned = is_unsigned_cond(c);
+ S390Opcode op;
+
+ if (c2const) {
+ if (c2 == 0) {
+ if (!(is_unsigned && need_carry)) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, LTR, r1, r1);
+ } else {
+ tcg_out_insn(s, RRE, LTGR, r1, r1);
+ }
+ return tcg_cond_to_ltr_cond[c];
+ }
+ }
+
+ if (!is_unsigned && c2 == (int16_t)c2) {
+ op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI);
+ tcg_out_insn_RI(s, op, r1, c2);
+ goto exit;
+ }
+
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RIL_CLFI : RIL_CFI);
+ tcg_out_insn_RIL(s, op, r1, c2);
+ goto exit;
+ } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) {
+ op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
+ tcg_out_insn_RIL(s, op, r1, c2);
+ goto exit;
+ }
+ }
+
+ /* Use the constant pool, but not for small constants. */
+ if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) {
+ c2 = TCG_TMP0;
+ /* fall through to reg-reg */
+ } else if (USE_REG_TB) {
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RXY_CLY : RXY_CY);
+ tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2,
+ 4 - (intptr_t)s->code_gen_ptr);
+ } else {
+ op = (is_unsigned ? RXY_CLG : RXY_CG);
+ tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, c2, R_390_20, s->code_ptr - 2,
+ -(intptr_t)s->code_gen_ptr);
+ }
+ goto exit;
+ } else {
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RIL_CLRL : RIL_CRL);
+ tcg_out_insn_RIL(s, op, r1, 0);
+ new_pool_label(s, (uint32_t)c2, R_390_PC32DBL,
+ s->code_ptr - 2, 2 + 4);
+ } else {
+ op = (is_unsigned ? RIL_CLGRL : RIL_CGRL);
+ tcg_out_insn_RIL(s, op, r1, 0);
+ new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2);
+ }
+ goto exit;
+ }
+ }
+
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RR_CLR : RR_CR);
+ tcg_out_insn_RR(s, op, r1, c2);
+ } else {
+ op = (is_unsigned ? RRE_CLGR : RRE_CGR);
+ tcg_out_insn_RRE(s, op, r1, c2);
+ }
+
+ exit:
+ return tcg_cond_to_s390_cond[c];
+}
+
+static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
+ TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
+{
+ int cc;
+ bool have_loc;
+
+ /* With LOC2, we can always emit the minimum 3 insns. */
+ if (s390_facilities & FACILITY_LOAD_ON_COND2) {
+ /* Emit: d = 0, d = (cc ? 1 : d). */
+ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
+ tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+ tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
+ return;
+ }
+
+ have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
+
+ /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
+ restart:
+ switch (cond) {
+ case TCG_COND_NE:
+ /* X != 0 is X > 0. */
+ if (c2const && c2 == 0) {
+ cond = TCG_COND_GTU;
+ } else {
+ break;
+ }
+ /* fallthru */
+
+ case TCG_COND_GTU:
+ case TCG_COND_GT:
+ /* The result of a compare has CC=2 for GT and CC=3 unused.
+ ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
+ tgen_cmp(s, type, cond, c1, c2, c2const, true);
+ tcg_out_movi(s, type, dest, 0);
+ tcg_out_insn(s, RRE, ALCGR, dest, dest);
+ return;
+
+ case TCG_COND_EQ:
+ /* X == 0 is X <= 0. */
+ if (c2const && c2 == 0) {
+ cond = TCG_COND_LEU;
+ } else {
+ break;
+ }
+ /* fallthru */
+
+ case TCG_COND_LEU:
+ case TCG_COND_LE:
+ /* As above, but we're looking for borrow, or !carry.
+ The second insn computes d - d - borrow, or -1 for true
+ and 0 for false. So we must mask to 1 bit afterward. */
+ tgen_cmp(s, type, cond, c1, c2, c2const, true);
+ tcg_out_insn(s, RRE, SLBGR, dest, dest);
+ tgen_andi(s, type, dest, 1);
+ return;
+
+ case TCG_COND_GEU:
+ case TCG_COND_LTU:
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ /* Swap operands so that we can use LEU/GTU/GT/LE. */
+ if (c2const) {
+ if (have_loc) {
+ break;
+ }
+ tcg_out_movi(s, type, TCG_TMP0, c2);
+ c2 = c1;
+ c2const = 0;
+ c1 = TCG_TMP0;
+ } else {
+ TCGReg t = c1;
+ c1 = c2;
+ c2 = t;
+ }
+ cond = tcg_swap_cond(cond);
+ goto restart;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
+ if (have_loc) {
+ /* Emit: d = 0, t = 1, d = (cc ? t : d). */
+ tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
+ tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
+ } else {
+ /* Emit: d = 1; if (cc) goto over; d = 0; over: */
+ tcg_out_movi(s, type, dest, 1);
+ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
+ tcg_out_movi(s, type, dest, 0);
+ }
+}
+
+static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
+ TCGReg c1, TCGArg c2, int c2const,
+ TCGArg v3, int v3const)
+{
+ int cc;
+ if (s390_facilities & FACILITY_LOAD_ON_COND) {
+ cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
+ if (v3const) {
+ tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
+ } else {
+ tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
+ }
+ } else {
+ c = tcg_invert_cond(c);
+ cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
+
+ /* Emit: if (cc) goto over; dest = r3; over: */
+ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
+ tcg_out_insn(s, RRE, LGR, dest, v3);
+ }
+}
+
+static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
+ TCGArg a2, int a2const)
+{
+ /* Since this sets both R and R+1, we have no choice but to store the
+ result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
+ QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
+ tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
+
+ if (a2const && a2 == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
+ } else {
+ if (a2const) {
+ tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
+ }
+ if (s390_facilities & FACILITY_LOAD_ON_COND) {
+ /* Emit: if (one bit found) dest = r0. */
+ tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
+ } else {
+ /* Emit: if (no one bit found) goto over; dest = r0; over: */
+ tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
+ tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
+ }
+ }
+}
+
+static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
+ int ofs, int len, int z)
+{
+ int lsb = (63 - ofs);
+ int msb = lsb - (len - 1);
+ tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
+}
+
+static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
+ int ofs, int len)
+{
+ tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
+}
+
+static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
+{
+ ptrdiff_t off = dest - s->code_ptr;
+ if (off == (int16_t)off) {
+ tcg_out_insn(s, RI, BRC, cc, off);
+ } else if (off == (int32_t)off) {
+ tcg_out_insn(s, RIL, BRCL, cc, off);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
+ tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
+ }
+}
+
+static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
+{
+ if (l->has_value) {
+ tgen_gotoi(s, cc, l->u.value_ptr);
+ } else if (USE_LONG_BRANCHES) {
+ tcg_out16(s, RIL_BRCL | (cc << 4));
+ tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2);
+ s->code_ptr += 2;
+ } else {
+ tcg_out16(s, RI_BRC | (cc << 4));
+ tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2);
+ s->code_ptr += 1;
+ }
+}
+
+static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
+ TCGReg r1, TCGReg r2, TCGLabel *l)
+{
+ intptr_t off = 0;
+
+ if (l->has_value) {
+ off = l->u.value_ptr - s->code_ptr;
+ tcg_debug_assert(off == (int16_t)off);
+ } else {
+ tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
+ }
+
+ tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
+ tcg_out16(s, off);
+ tcg_out16(s, cc << 12 | (opc & 0xff));
+}
+
+static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
+ TCGReg r1, int i2, TCGLabel *l)
+{
+ tcg_target_long off = 0;
+
+ if (l->has_value) {
+ off = l->u.value_ptr - s->code_ptr;
+ tcg_debug_assert(off == (int16_t)off);
+ } else {
+ tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
+ }
+
+ tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
+ tcg_out16(s, off);
+ tcg_out16(s, (i2 << 8) | (opc & 0xff));
+}
+
+static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
+ TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
+{
+ int cc;
+
+ if (s390_facilities & FACILITY_GEN_INST_EXT) {
+ bool is_unsigned = is_unsigned_cond(c);
+ bool in_range;
+ S390Opcode opc;
+
+ cc = tcg_cond_to_s390_cond[c];
+
+ if (!c2const) {
+ opc = (type == TCG_TYPE_I32
+ ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
+ : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
+ tgen_compare_branch(s, opc, cc, r1, c2, l);
+ return;
+ }
+
+ /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
+ If the immediate we've been given does not fit that range, we'll
+ fall back to separate compare and branch instructions using the
+ larger comparison range afforded by COMPARE IMMEDIATE. */
+ if (type == TCG_TYPE_I32) {
+ if (is_unsigned) {
+ opc = RIE_CLIJ;
+ in_range = (uint32_t)c2 == (uint8_t)c2;
+ } else {
+ opc = RIE_CIJ;
+ in_range = (int32_t)c2 == (int8_t)c2;
+ }
+ } else {
+ if (is_unsigned) {
+ opc = RIE_CLGIJ;
+ in_range = (uint64_t)c2 == (uint8_t)c2;
+ } else {
+ opc = RIE_CGIJ;
+ in_range = (int64_t)c2 == (int8_t)c2;
+ }
+ }
+ if (in_range) {
+ tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
+ return;
+ }
+ }
+
+ cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
+ tgen_branch(s, cc, l);
+}
+
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
+{
+ ptrdiff_t off = dest - s->code_ptr;
+ if (off == (int32_t)off) {
+ tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
+ tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
+ }
+}
+
+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
+ TCGReg base, TCGReg index, int disp)
+{
+ switch (opc & (MO_SSIZE | MO_BSWAP)) {
+ case MO_UB:
+ tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
+ break;
+ case MO_SB:
+ tcg_out_insn(s, RXY, LGB, data, base, index, disp);
+ break;
+
+ case MO_UW | MO_BSWAP:
+ /* swapped unsigned halfword load with upper bits zeroed */
+ tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
+ tgen_ext16u(s, TCG_TYPE_I64, data, data);
+ break;
+ case MO_UW:
+ tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
+ break;
+
+ case MO_SW | MO_BSWAP:
+ /* swapped sign-extended halfword load */
+ tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
+ tgen_ext16s(s, TCG_TYPE_I64, data, data);
+ break;
+ case MO_SW:
+ tcg_out_insn(s, RXY, LGH, data, base, index, disp);
+ break;
+
+ case MO_UL | MO_BSWAP:
+ /* swapped unsigned int load with upper bits zeroed */
+ tcg_out_insn(s, RXY, LRV, data, base, index, disp);
+ tgen_ext32u(s, data, data);
+ break;
+ case MO_UL:
+ tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
+ break;
+
+ case MO_SL | MO_BSWAP:
+ /* swapped sign-extended int load */
+ tcg_out_insn(s, RXY, LRV, data, base, index, disp);
+ tgen_ext32s(s, data, data);
+ break;
+ case MO_SL:
+ tcg_out_insn(s, RXY, LGF, data, base, index, disp);
+ break;
+
+ case MO_Q | MO_BSWAP:
+ tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
+ break;
+ case MO_Q:
+ tcg_out_insn(s, RXY, LG, data, base, index, disp);
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
+ TCGReg base, TCGReg index, int disp)
+{
+ switch (opc & (MO_SIZE | MO_BSWAP)) {
+ case MO_UB:
+ if (disp >= 0 && disp < 0x1000) {
+ tcg_out_insn(s, RX, STC, data, base, index, disp);
+ } else {
+ tcg_out_insn(s, RXY, STCY, data, base, index, disp);
+ }
+ break;
+
+ case MO_UW | MO_BSWAP:
+ tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
+ break;
+ case MO_UW:
+ if (disp >= 0 && disp < 0x1000) {
+ tcg_out_insn(s, RX, STH, data, base, index, disp);
+ } else {
+ tcg_out_insn(s, RXY, STHY, data, base, index, disp);
+ }
+ break;
+
+ case MO_UL | MO_BSWAP:
+ tcg_out_insn(s, RXY, STRV, data, base, index, disp);
+ break;
+ case MO_UL:
+ if (disp >= 0 && disp < 0x1000) {
+ tcg_out_insn(s, RX, ST, data, base, index, disp);
+ } else {
+ tcg_out_insn(s, RXY, STY, data, base, index, disp);
+ }
+ break;
+
+ case MO_Q | MO_BSWAP:
+ tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
+ break;
+ case MO_Q:
+ tcg_out_insn(s, RXY, STG, data, base, index, disp);
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+#if defined(CONFIG_SOFTMMU)
+#include "../tcg-ldst.c.inc"
+
+/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
+
+/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
+ addend into R2. Returns a register with the santitized guest address. */
+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
+ int mem_index, bool is_ld)
+{
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+ unsigned s_mask = (1 << s_bits) - 1;
+ unsigned a_mask = (1 << a_bits) - 1;
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ int ofs, a_off;
+ uint64_t tlb_mask;
+
+ tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off);
+ tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_off);
+
+ /* For aligned accesses, we check the first byte and include the alignment
+ bits within the address. For unaligned access, we check that we don't
+ cross pages using the address of the last byte of the access. */
+ a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
+ tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
+ if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) {
+ tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
+ } else {
+ tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
+ tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
+ }
+
+ if (is_ld) {
+ ofs = offsetof(CPUTLBEntry, addr_read);
+ } else {
+ ofs = offsetof(CPUTLBEntry, addr_write);
+ }
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
+ } else {
+ tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
+ }
+
+ tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE,
+ offsetof(CPUTLBEntry, addend));
+
+ if (TARGET_LONG_BITS == 32) {
+ tgen_ext32u(s, TCG_REG_R3, addr_reg);
+ return TCG_REG_R3;
+ }
+ return addr_reg;
+}
+
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+ TCGReg data, TCGReg addr,
+ tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->datalo_reg = data;
+ label->addrlo_reg = addr;
+ label->raddr = raddr;
+ label->label_ptr[0] = label_ptr;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGReg addr_reg = lb->addrlo_reg;
+ TCGReg data_reg = lb->datalo_reg;
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
+ (intptr_t)s->code_ptr, 2)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
+ }
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr);
+ tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
+ tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
+
+ tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGReg addr_reg = lb->addrlo_reg;
+ TCGReg data_reg = lb->datalo_reg;
+ TCGMemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
+ (intptr_t)s->code_ptr, 2)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
+ }
+ switch (opc & MO_SIZE) {
+ case MO_UB:
+ tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
+ break;
+ case MO_UW:
+ tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
+ break;
+ case MO_UL:
+ tgen_ext32u(s, TCG_REG_R4, data_reg);
+ break;
+ case MO_Q:
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
+ break;
+ default:
+ tcg_abort();
+ }
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
+ tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+
+ tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
+ return true;
+}
+#else
+static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
+ TCGReg *index_reg, tcg_target_long *disp)
+{
+ if (TARGET_LONG_BITS == 32) {
+ tgen_ext32u(s, TCG_TMP0, *addr_reg);
+ *addr_reg = TCG_TMP0;
+ }
+ if (guest_base < 0x80000) {
+ *index_reg = TCG_REG_NONE;
+ *disp = guest_base;
+ } else {
+ *index_reg = TCG_GUEST_BASE_REG;
+ *disp = 0;
+ }
+}
+#endif /* CONFIG_SOFTMMU */
+
+static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
+ TCGMemOpIdx oi)
+{
+ MemOp opc = get_memop(oi);
+#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
+ tcg_insn_unit *label_ptr;
+ TCGReg base_reg;
+
+ base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
+
+ tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
+ label_ptr = s->code_ptr;
+ s->code_ptr += 1;
+
+ tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
+
+ add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
+#else
+ TCGReg index_reg;
+ tcg_target_long disp;
+
+ tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
+ tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
+#endif
+}
+
+static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
+ TCGMemOpIdx oi)
+{
+ MemOp opc = get_memop(oi);
+#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
+ tcg_insn_unit *label_ptr;
+ TCGReg base_reg;
+
+ base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
+
+ tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
+ label_ptr = s->code_ptr;
+ s->code_ptr += 1;
+
+ tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
+
+ add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
+#else
+ TCGReg index_reg;
+ tcg_target_long disp;
+
+ tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
+ tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
+#endif
+}
+
+# define OP_32_64(x) \
+ case glue(glue(INDEX_op_,x),_i32): \
+ case glue(glue(INDEX_op_,x),_i64)
+
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg *args, const int *const_args)
+{
+ S390Opcode op, op2;
+ TCGArg a0, a1, a2;
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ /* Reuse the zeroing that exists for goto_ptr. */
+ a0 = args[0];
+ if (a0 == 0) {
+ tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
+ tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
+ }
+ break;
+
+ case INDEX_op_goto_tb:
+ a0 = args[0];
+ if (s->tb_jmp_insn_offset) {
+ /* branch displacement must be aligned for atomic patching;
+ * see if we need to add extra nop before branch
+ */
+ if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
+ tcg_out16(s, NOP);
+ }
+ tcg_debug_assert(!USE_REG_TB);
+ tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ s->code_ptr += 2;
+ } else {
+ /* load address stored at s->tb_jmp_target_addr + a0 */
+ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
+ s->tb_jmp_target_addr + a0);
+ /* and go there */
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
+ }
+ set_jmp_reset_offset(s, a0);
+
+ /* For the unlinked path of goto_tb, we need to reset
+ TCG_REG_TB to the beginning of this TB. */
+ if (USE_REG_TB) {
+ int ofs = -tcg_current_code_size(s);
+ assert(ofs == (int16_t)ofs);
+ tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs);
+ }
+ break;
+
+ case INDEX_op_goto_ptr:
+ a0 = args[0];
+ if (USE_REG_TB) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
+ }
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
+ break;
+
+ OP_32_64(ld8u):
+ /* ??? LLC (RXY format) is only present with the extended-immediate
+ facility, whereas LLGC is always present. */
+ tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ OP_32_64(ld8s):
+ /* ??? LB is no smaller than LGB, so no point to using it. */
+ tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ OP_32_64(ld16u):
+ /* ??? LLH (RXY format) is only present with the extended-immediate
+ facility, whereas LLGH is always present. */
+ tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ case INDEX_op_ld16s_i32:
+ tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ case INDEX_op_ld_i32:
+ tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
+ break;
+
+ OP_32_64(st8):
+ tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
+ TCG_REG_NONE, args[2]);
+ break;
+
+ OP_32_64(st16):
+ tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
+ TCG_REG_NONE, args[2]);
+ break;
+
+ case INDEX_op_st_i32:
+ tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_add_i32:
+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
+ if (const_args[2]) {
+ do_addi_32:
+ if (a0 == a1) {
+ if (a2 == (int16_t)a2) {
+ tcg_out_insn(s, RI, AHI, a0, a2);
+ break;
+ }
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ tcg_out_insn(s, RIL, AFI, a0, a2);
+ break;
+ }
+ }
+ tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, AR, a0, a2);
+ } else {
+ tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
+ }
+ break;
+ case INDEX_op_sub_i32:
+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
+ if (const_args[2]) {
+ a2 = -a2;
+ goto do_addi_32;
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, SR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, SRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_and_i32:
+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tgen_andi(s, TCG_TYPE_I32, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, NR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, NRK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_or_i32:
+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tgen_ori(s, TCG_TYPE_I32, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, OR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, ORK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_xor_i32:
+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tgen_xori(s, TCG_TYPE_I32, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, XR, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RRF, XRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_neg_i32:
+ tcg_out_insn(s, RR, LCR, args[0], args[1]);
+ break;
+
+ case INDEX_op_mul_i32:
+ if (const_args[2]) {
+ if ((int32_t)args[2] == (int16_t)args[2]) {
+ tcg_out_insn(s, RI, MHI, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, MSR, args[0], args[2]);
+ }
+ break;
+
+ case INDEX_op_div2_i32:
+ tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
+ break;
+ case INDEX_op_divu2_i32:
+ tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
+ break;
+
+ case INDEX_op_shl_i32:
+ op = RS_SLL;
+ op2 = RSY_SLLK;
+ do_shift32:
+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
+ if (a0 == a1) {
+ if (const_args[2]) {
+ tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
+ } else {
+ tcg_out_sh32(s, op, a0, a2, 0);
+ }
+ } else {
+ /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
+ if (const_args[2]) {
+ tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
+ } else {
+ tcg_out_sh64(s, op2, a0, a1, a2, 0);
+ }
+ }
+ break;
+ case INDEX_op_shr_i32:
+ op = RS_SRL;
+ op2 = RSY_SRLK;
+ goto do_shift32;
+ case INDEX_op_sar_i32:
+ op = RS_SRA;
+ op2 = RSY_SRAK;
+ goto do_shift32;
+
+ case INDEX_op_rotl_i32:
+ /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
+ } else {
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
+ }
+ break;
+ case INDEX_op_rotr_i32:
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1],
+ TCG_REG_NONE, (32 - args[2]) & 31);
+ } else {
+ tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
+ }
+ break;
+
+ case INDEX_op_ext8s_i32:
+ tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+ case INDEX_op_ext16s_i32:
+ tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+ case INDEX_op_ext8u_i32:
+ tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+ case INDEX_op_ext16u_i32:
+ tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+
+ OP_32_64(bswap16):
+ /* The TCG bswap definition requires bits 0-47 already be zero.
+ Thus we don't need the G-type insns to implement bswap16_i64. */
+ tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+ tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
+ break;
+ OP_32_64(bswap32):
+ tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+ break;
+
+ case INDEX_op_add2_i32:
+ if (const_args[4]) {
+ tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RR, ALR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
+ break;
+ case INDEX_op_sub2_i32:
+ if (const_args[4]) {
+ tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RR, SLR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
+ break;
+
+ case INDEX_op_br:
+ tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
+ break;
+
+ case INDEX_op_brcond_i32:
+ tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
+ args[1], const_args[1], arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i32:
+ tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_movcond_i32:
+ tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
+ args[2], const_args[2], args[3], const_args[3]);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ /* ??? Technically we can use a non-extending instruction. */
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_ld16s_i64:
+ tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+ case INDEX_op_ld32u_i64:
+ tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+ case INDEX_op_ld32s_i64:
+ tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_st32_i64:
+ tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_add_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ do_addi_64:
+ if (a0 == a1) {
+ if (a2 == (int16_t)a2) {
+ tcg_out_insn(s, RI, AGHI, a0, a2);
+ break;
+ }
+ if (s390_facilities & FACILITY_EXT_IMM) {
+ if (a2 == (int32_t)a2) {
+ tcg_out_insn(s, RIL, AGFI, a0, a2);
+ break;
+ } else if (a2 == (uint32_t)a2) {
+ tcg_out_insn(s, RIL, ALGFI, a0, a2);
+ break;
+ } else if (-a2 == (uint32_t)-a2) {
+ tcg_out_insn(s, RIL, SLGFI, a0, -a2);
+ break;
+ }
+ }
+ }
+ tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, AGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
+ }
+ break;
+ case INDEX_op_sub_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ a2 = -a2;
+ goto do_addi_64;
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, SGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_and_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
+ tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, NGR, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_or_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
+ tgen_ori(s, TCG_TYPE_I64, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, OGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_xor_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
+ tgen_xori(s, TCG_TYPE_I64, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, XGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_neg_i64:
+ tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
+ break;
+ case INDEX_op_bswap64_i64:
+ tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
+ break;
+
+ case INDEX_op_mul_i64:
+ if (const_args[2]) {
+ if (args[2] == (int16_t)args[2]) {
+ tcg_out_insn(s, RI, MGHI, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
+ }
+ break;
+
+ case INDEX_op_div2_i64:
+ /* ??? We get an unnecessary sign-extension of the dividend
+ into R3 with this definition, but as we do in fact always
+ produce both quotient and remainder using INDEX_op_div_i64
+ instead requires jumping through even more hoops. */
+ tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
+ break;
+ case INDEX_op_divu2_i64:
+ tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
+ break;
+ case INDEX_op_mulu2_i64:
+ tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
+ break;
+
+ case INDEX_op_shl_i64:
+ op = RSY_SLLG;
+ do_shift64:
+ if (const_args[2]) {
+ tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
+ } else {
+ tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
+ }
+ break;
+ case INDEX_op_shr_i64:
+ op = RSY_SRLG;
+ goto do_shift64;
+ case INDEX_op_sar_i64:
+ op = RSY_SRAG;
+ goto do_shift64;
+
+ case INDEX_op_rotl_i64:
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
+ TCG_REG_NONE, args[2]);
+ } else {
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
+ }
+ break;
+ case INDEX_op_rotr_i64:
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
+ TCG_REG_NONE, (64 - args[2]) & 63);
+ } else {
+ /* We can use the smaller 32-bit negate because only the
+ low 6 bits are examined for the rotate. */
+ tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
+ }
+ break;
+
+ case INDEX_op_ext8s_i64:
+ tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ext16s_i64:
+ tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_ext32s_i64:
+ tgen_ext32s(s, args[0], args[1]);
+ break;
+ case INDEX_op_ext8u_i64:
+ tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ext16u_i64:
+ tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_ext32u_i64:
+ tgen_ext32u(s, args[0], args[1]);
+ break;
+
+ case INDEX_op_add2_i64:
+ if (const_args[4]) {
+ if ((int64_t)args[4] >= 0) {
+ tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
+ break;
+ case INDEX_op_sub2_i64:
+ if (const_args[4]) {
+ if ((int64_t)args[4] >= 0) {
+ tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
+ break;
+
+ case INDEX_op_brcond_i64:
+ tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
+ args[1], const_args[1], arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i64:
+ tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_movcond_i64:
+ tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
+ args[2], const_args[2], args[3], const_args[3]);
+ break;
+
+ OP_32_64(deposit):
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[1]) {
+ tgen_deposit(s, a0, a2, args[3], args[4], 1);
+ } else {
+ /* Since we can't support "0Z" as a constraint, we allow a1 in
+ any register. Fix things up as if a matching constraint. */
+ if (a0 != a1) {
+ TCGType type = (opc == INDEX_op_deposit_i64);
+ if (a0 == a2) {
+ tcg_out_mov(s, type, TCG_TMP0, a2);
+ a2 = TCG_TMP0;
+ }
+ tcg_out_mov(s, type, a0, a1);
+ }
+ tgen_deposit(s, a0, a2, args[3], args[4], 0);
+ }
+ break;
+
+ OP_32_64(extract):
+ tgen_extract(s, args[0], args[1], args[2], args[3]);
+ break;
+
+ case INDEX_op_clz_i64:
+ tgen_clz(s, args[0], args[1], args[2], const_args[2]);
+ break;
+
+ case INDEX_op_mb:
+ /* The host memory model is quite strong, we simply need to
+ serialize the instruction stream. */
+ if (args[0] & TCG_MO_ST_LD) {
+ tcg_out_insn(s, RR, BCR,
+ s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
+ }
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
+ static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
+ static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
+ static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
+ static const TCGTargetOpDef a2_r
+ = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
+ static const TCGTargetOpDef a2_ri
+ = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
+ static const TCGTargetOpDef a2_rA
+ = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &r_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ return &r_r_ri;
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
+
+ case INDEX_op_mul_i32:
+ /* If we have the general-instruction-extensions, then we have
+ MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
+ have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
+ return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
+ case INDEX_op_mul_i64:
+ return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
+
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
+
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ return &r_r_ri;
+
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ return &r_r_ri;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &r_ri;
+
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ return &r_r;
+
+ case INDEX_op_clz_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return &r_r_ri;
+
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_ld_i64:
+ return &r_L;
+ case INDEX_op_qemu_st_i64:
+ case INDEX_op_qemu_st_i32:
+ return &L_L;
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ {
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "rZ", "r" } };
+ return &dep;
+ }
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ {
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
+ static const TCGTargetOpDef movc_l
+ = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
+ return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
+ }
+ case INDEX_op_div2_i32:
+ case INDEX_op_div2_i64:
+ case INDEX_op_divu2_i32:
+ case INDEX_op_divu2_i64:
+ {
+ static const TCGTargetOpDef div2
+ = { .args_ct_str = { "b", "a", "0", "1", "r" } };
+ return &div2;
+ }
+ case INDEX_op_mulu2_i64:
+ {
+ static const TCGTargetOpDef mul2
+ = { .args_ct_str = { "b", "a", "0", "r" } };
+ return &mul2;
+ }
+
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i64:
+ return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
+
+ default:
+ break;
+ }
+ return NULL;
+}
+
+static void query_s390_facilities(void)
+{
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+
+ /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
+ is present on all 64-bit systems, but let's check for it anyway. */
+ if (hwcap & HWCAP_S390_STFLE) {
+ register int r0 __asm__("0");
+ register void *r1 __asm__("1");
+
+ /* stfle 0(%r1) */
+ r1 = &s390_facilities;
+ asm volatile(".word 0xb2b0,0x1000"
+ : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
+ }
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ query_s390_facilities();
+
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
+
+ tcg_target_call_clobber_regs = 0;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
+ /* The r6 register is technically call-saved, but it's also a parameter
+ register, so it can get killed by setup for the qemu_st helper. */
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
+ /* The return register can be considered call-clobbered. */
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
+ /* XXX many insns can't be used with R0, so we better avoid it for now */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+ if (USE_REG_TB) {
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
+ }
+}
+
+#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_NLONGS * sizeof(long)))
+
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ /* stmg %r6,%r15,48(%r15) (save registers) */
+ tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
+
+ /* aghi %r15,-frame_size */
+ tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
+
+ tcg_set_frame(s, TCG_REG_CALL_STACK,
+ TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
+
+#ifndef CONFIG_SOFTMMU
+ if (guest_base >= 0x80000) {
+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+ if (USE_REG_TB) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,
+ tcg_target_call_iarg_regs[1]);
+ }
+
+ /* br %r3 (go to TB) */
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
+
+ /*
+ * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
+ * and fall through to the rest of the epilogue.
+ */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
+
+ /* TB epilogue */
+ tb_ret_addr = s->code_ptr;
+
+ /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
+ tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
+ FRAME_SIZE + 48);
+
+ /* br %r14 (return) */
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ memset(p, 0x07, count * sizeof(tcg_insn_unit));
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[18];
+} DebugFrame;
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+#define ELF_HOST_MACHINE EM_S390
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = 8, /* sleb128 8 */
+ .h.cie.return_column = TCG_REG_R14,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x86, 6, /* DW_CFA_offset, %r6, 48 */
+ 0x87, 7, /* DW_CFA_offset, %r7, 56 */
+ 0x88, 8, /* DW_CFA_offset, %r8, 64 */
+ 0x89, 9, /* DW_CFA_offset, %r92, 72 */
+ 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
+ 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
+ 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
+ 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
+ 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
- * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
- * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/* We only support generating code for 64-bit mode. */
-#if TCG_TARGET_REG_BITS != 64
-#error "unsupported code generation mode"
-#endif
-
-#include "../tcg-pool.inc.c"
-#include "elf.h"
-
-/* ??? The translation blocks produced by TCG are generally small enough to
- be entirely reachable with a 16-bit displacement. Leaving the option for
- a 32-bit displacement here Just In Case. */
-#define USE_LONG_BRANCHES 0
-
-#define TCG_CT_CONST_S16 0x100
-#define TCG_CT_CONST_S32 0x200
-#define TCG_CT_CONST_S33 0x400
-#define TCG_CT_CONST_ZERO 0x800
-
-/* Several places within the instruction set 0 means "no register"
- rather than TCG_REG_R0. */
-#define TCG_REG_NONE 0
-
-/* A scratch register that may be be used throughout the backend. */
-#define TCG_TMP0 TCG_REG_R1
-
-/* A scratch register that holds a pointer to the beginning of the TB.
- We don't need this when we have pc-relative loads with the general
- instructions extension facility. */
-#define TCG_REG_TB TCG_REG_R12
-#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))
-
-#ifndef CONFIG_SOFTMMU
-#define TCG_GUEST_BASE_REG TCG_REG_R13
-#endif
-
-/* All of the following instructions are prefixed with their instruction
- format, and are defined as 8- or 16-bit quantities, even when the two
- halves of the 16-bit quantity may appear 32 bits apart in the insn.
- This makes it easy to copy the values from the tables in Appendix B. */
-typedef enum S390Opcode {
- RIL_AFI = 0xc209,
- RIL_AGFI = 0xc208,
- RIL_ALFI = 0xc20b,
- RIL_ALGFI = 0xc20a,
- RIL_BRASL = 0xc005,
- RIL_BRCL = 0xc004,
- RIL_CFI = 0xc20d,
- RIL_CGFI = 0xc20c,
- RIL_CLFI = 0xc20f,
- RIL_CLGFI = 0xc20e,
- RIL_CLRL = 0xc60f,
- RIL_CLGRL = 0xc60a,
- RIL_CRL = 0xc60d,
- RIL_CGRL = 0xc608,
- RIL_IIHF = 0xc008,
- RIL_IILF = 0xc009,
- RIL_LARL = 0xc000,
- RIL_LGFI = 0xc001,
- RIL_LGRL = 0xc408,
- RIL_LLIHF = 0xc00e,
- RIL_LLILF = 0xc00f,
- RIL_LRL = 0xc40d,
- RIL_MSFI = 0xc201,
- RIL_MSGFI = 0xc200,
- RIL_NIHF = 0xc00a,
- RIL_NILF = 0xc00b,
- RIL_OIHF = 0xc00c,
- RIL_OILF = 0xc00d,
- RIL_SLFI = 0xc205,
- RIL_SLGFI = 0xc204,
- RIL_XIHF = 0xc006,
- RIL_XILF = 0xc007,
-
- RI_AGHI = 0xa70b,
- RI_AHI = 0xa70a,
- RI_BRC = 0xa704,
- RI_CHI = 0xa70e,
- RI_CGHI = 0xa70f,
- RI_IIHH = 0xa500,
- RI_IIHL = 0xa501,
- RI_IILH = 0xa502,
- RI_IILL = 0xa503,
- RI_LGHI = 0xa709,
- RI_LLIHH = 0xa50c,
- RI_LLIHL = 0xa50d,
- RI_LLILH = 0xa50e,
- RI_LLILL = 0xa50f,
- RI_MGHI = 0xa70d,
- RI_MHI = 0xa70c,
- RI_NIHH = 0xa504,
- RI_NIHL = 0xa505,
- RI_NILH = 0xa506,
- RI_NILL = 0xa507,
- RI_OIHH = 0xa508,
- RI_OIHL = 0xa509,
- RI_OILH = 0xa50a,
- RI_OILL = 0xa50b,
-
- RIE_CGIJ = 0xec7c,
- RIE_CGRJ = 0xec64,
- RIE_CIJ = 0xec7e,
- RIE_CLGRJ = 0xec65,
- RIE_CLIJ = 0xec7f,
- RIE_CLGIJ = 0xec7d,
- RIE_CLRJ = 0xec77,
- RIE_CRJ = 0xec76,
- RIE_LOCGHI = 0xec46,
- RIE_RISBG = 0xec55,
-
- RRE_AGR = 0xb908,
- RRE_ALGR = 0xb90a,
- RRE_ALCR = 0xb998,
- RRE_ALCGR = 0xb988,
- RRE_CGR = 0xb920,
- RRE_CLGR = 0xb921,
- RRE_DLGR = 0xb987,
- RRE_DLR = 0xb997,
- RRE_DSGFR = 0xb91d,
- RRE_DSGR = 0xb90d,
- RRE_FLOGR = 0xb983,
- RRE_LGBR = 0xb906,
- RRE_LCGR = 0xb903,
- RRE_LGFR = 0xb914,
- RRE_LGHR = 0xb907,
- RRE_LGR = 0xb904,
- RRE_LLGCR = 0xb984,
- RRE_LLGFR = 0xb916,
- RRE_LLGHR = 0xb985,
- RRE_LRVR = 0xb91f,
- RRE_LRVGR = 0xb90f,
- RRE_LTGR = 0xb902,
- RRE_MLGR = 0xb986,
- RRE_MSGR = 0xb90c,
- RRE_MSR = 0xb252,
- RRE_NGR = 0xb980,
- RRE_OGR = 0xb981,
- RRE_SGR = 0xb909,
- RRE_SLGR = 0xb90b,
- RRE_SLBR = 0xb999,
- RRE_SLBGR = 0xb989,
- RRE_XGR = 0xb982,
-
- RRF_LOCR = 0xb9f2,
- RRF_LOCGR = 0xb9e2,
- RRF_NRK = 0xb9f4,
- RRF_NGRK = 0xb9e4,
- RRF_ORK = 0xb9f6,
- RRF_OGRK = 0xb9e6,
- RRF_SRK = 0xb9f9,
- RRF_SGRK = 0xb9e9,
- RRF_SLRK = 0xb9fb,
- RRF_SLGRK = 0xb9eb,
- RRF_XRK = 0xb9f7,
- RRF_XGRK = 0xb9e7,
-
- RR_AR = 0x1a,
- RR_ALR = 0x1e,
- RR_BASR = 0x0d,
- RR_BCR = 0x07,
- RR_CLR = 0x15,
- RR_CR = 0x19,
- RR_DR = 0x1d,
- RR_LCR = 0x13,
- RR_LR = 0x18,
- RR_LTR = 0x12,
- RR_NR = 0x14,
- RR_OR = 0x16,
- RR_SR = 0x1b,
- RR_SLR = 0x1f,
- RR_XR = 0x17,
-
- RSY_RLL = 0xeb1d,
- RSY_RLLG = 0xeb1c,
- RSY_SLLG = 0xeb0d,
- RSY_SLLK = 0xebdf,
- RSY_SRAG = 0xeb0a,
- RSY_SRAK = 0xebdc,
- RSY_SRLG = 0xeb0c,
- RSY_SRLK = 0xebde,
-
- RS_SLL = 0x89,
- RS_SRA = 0x8a,
- RS_SRL = 0x88,
-
- RXY_AG = 0xe308,
- RXY_AY = 0xe35a,
- RXY_CG = 0xe320,
- RXY_CLG = 0xe321,
- RXY_CLY = 0xe355,
- RXY_CY = 0xe359,
- RXY_LAY = 0xe371,
- RXY_LB = 0xe376,
- RXY_LG = 0xe304,
- RXY_LGB = 0xe377,
- RXY_LGF = 0xe314,
- RXY_LGH = 0xe315,
- RXY_LHY = 0xe378,
- RXY_LLGC = 0xe390,
- RXY_LLGF = 0xe316,
- RXY_LLGH = 0xe391,
- RXY_LMG = 0xeb04,
- RXY_LRV = 0xe31e,
- RXY_LRVG = 0xe30f,
- RXY_LRVH = 0xe31f,
- RXY_LY = 0xe358,
- RXY_NG = 0xe380,
- RXY_OG = 0xe381,
- RXY_STCY = 0xe372,
- RXY_STG = 0xe324,
- RXY_STHY = 0xe370,
- RXY_STMG = 0xeb24,
- RXY_STRV = 0xe33e,
- RXY_STRVG = 0xe32f,
- RXY_STRVH = 0xe33f,
- RXY_STY = 0xe350,
- RXY_XG = 0xe382,
-
- RX_A = 0x5a,
- RX_C = 0x59,
- RX_L = 0x58,
- RX_LA = 0x41,
- RX_LH = 0x48,
- RX_ST = 0x50,
- RX_STC = 0x42,
- RX_STH = 0x40,
-
- NOP = 0x0707,
-} S390Opcode;
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
- "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
-};
-#endif
-
-/* Since R6 is a potential argument register, choose it last of the
- call-saved registers. Likewise prefer the call-clobbered registers
- in reverse order to maximize the chance of avoiding the arguments. */
-static const int tcg_target_reg_alloc_order[] = {
- /* Call saved registers. */
- TCG_REG_R13,
- TCG_REG_R12,
- TCG_REG_R11,
- TCG_REG_R10,
- TCG_REG_R9,
- TCG_REG_R8,
- TCG_REG_R7,
- TCG_REG_R6,
- /* Call clobbered registers. */
- TCG_REG_R14,
- TCG_REG_R0,
- TCG_REG_R1,
- /* Argument registers, in reverse order of allocation. */
- TCG_REG_R5,
- TCG_REG_R4,
- TCG_REG_R3,
- TCG_REG_R2,
-};
-
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_R2,
- TCG_REG_R3,
- TCG_REG_R4,
- TCG_REG_R5,
- TCG_REG_R6,
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_R2,
-};
-
-#define S390_CC_EQ 8
-#define S390_CC_LT 4
-#define S390_CC_GT 2
-#define S390_CC_OV 1
-#define S390_CC_NE (S390_CC_LT | S390_CC_GT)
-#define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
-#define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
-#define S390_CC_NEVER 0
-#define S390_CC_ALWAYS 15
-
-/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
-static const uint8_t tcg_cond_to_s390_cond[] = {
- [TCG_COND_EQ] = S390_CC_EQ,
- [TCG_COND_NE] = S390_CC_NE,
- [TCG_COND_LT] = S390_CC_LT,
- [TCG_COND_LE] = S390_CC_LE,
- [TCG_COND_GT] = S390_CC_GT,
- [TCG_COND_GE] = S390_CC_GE,
- [TCG_COND_LTU] = S390_CC_LT,
- [TCG_COND_LEU] = S390_CC_LE,
- [TCG_COND_GTU] = S390_CC_GT,
- [TCG_COND_GEU] = S390_CC_GE,
-};
-
-/* Condition codes that result from a LOAD AND TEST. Here, we have no
- unsigned instruction variation, however since the test is vs zero we
- can re-map the outcomes appropriately. */
-static const uint8_t tcg_cond_to_ltr_cond[] = {
- [TCG_COND_EQ] = S390_CC_EQ,
- [TCG_COND_NE] = S390_CC_NE,
- [TCG_COND_LT] = S390_CC_LT,
- [TCG_COND_LE] = S390_CC_LE,
- [TCG_COND_GT] = S390_CC_GT,
- [TCG_COND_GE] = S390_CC_GE,
- [TCG_COND_LTU] = S390_CC_NEVER,
- [TCG_COND_LEU] = S390_CC_EQ,
- [TCG_COND_GTU] = S390_CC_NE,
- [TCG_COND_GEU] = S390_CC_ALWAYS,
-};
-
-#ifdef CONFIG_SOFTMMU
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LESL] = helper_le_ldsl_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BESL] = helper_be_ldsl_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
-};
-
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-#endif
-
-static tcg_insn_unit *tb_ret_addr;
-uint64_t s390_facilities;
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- intptr_t pcrel2;
- uint32_t old;
-
- value += addend;
- pcrel2 = (tcg_insn_unit *)value - code_ptr;
-
- switch (type) {
- case R_390_PC16DBL:
- if (pcrel2 == (int16_t)pcrel2) {
- tcg_patch16(code_ptr, pcrel2);
- return true;
- }
- break;
- case R_390_PC32DBL:
- if (pcrel2 == (int32_t)pcrel2) {
- tcg_patch32(code_ptr, pcrel2);
- return true;
- }
- break;
- case R_390_20:
- if (value == sextract64(value, 0, 20)) {
- old = *(uint32_t *)code_ptr & 0xf00000ff;
- old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
- tcg_patch32(code_ptr, old);
- return true;
- }
- break;
- default:
- g_assert_not_reached();
- }
- return false;
-}
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r': /* all registers */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
- break;
- case 'L': /* qemu_ld/st constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
- break;
- case 'a': /* force R2 for division */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
- break;
- case 'b': /* force R3 for division */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
- break;
- case 'A':
- ct->ct |= TCG_CT_CONST_S33;
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct = arg_ct->ct;
-
- if (ct & TCG_CT_CONST) {
- return 1;
- }
-
- if (type == TCG_TYPE_I32) {
- val = (int32_t)val;
- }
-
- /* The following are mutually exclusive. */
- if (ct & TCG_CT_CONST_S16) {
- return val == (int16_t)val;
- } else if (ct & TCG_CT_CONST_S32) {
- return val == (int32_t)val;
- } else if (ct & TCG_CT_CONST_S33) {
- return val >= -0xffffffffll && val <= 0xffffffffll;
- } else if (ct & TCG_CT_CONST_ZERO) {
- return val == 0;
- }
-
- return 0;
-}
-
-/* Emit instructions according to the given instruction format. */
-
-static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
-{
- tcg_out16(s, (op << 8) | (r1 << 4) | r2);
-}
-
-static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
- TCGReg r1, TCGReg r2)
-{
- tcg_out32(s, (op << 16) | (r1 << 4) | r2);
-}
-
-static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
- TCGReg r1, TCGReg r2, int m3)
-{
- tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
-}
-
-static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
-{
- tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
-}
-
-static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
- int i2, int m3)
-{
- tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
- tcg_out32(s, (i2 << 16) | (op & 0xff));
-}
-
-static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
-{
- tcg_out16(s, op | (r1 << 4));
- tcg_out32(s, i2);
-}
-
-static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
- TCGReg b2, TCGReg r3, int disp)
-{
- tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
- | (disp & 0xfff));
-}
-
-static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
- TCGReg b2, TCGReg r3, int disp)
-{
- tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
- tcg_out32(s, (op & 0xff) | (b2 << 28)
- | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
-}
-
-#define tcg_out_insn_RX tcg_out_insn_RS
-#define tcg_out_insn_RXY tcg_out_insn_RSY
-
-/* Emit an opcode with "type-checking" of the format. */
-#define tcg_out_insn(S, FMT, OP, ...) \
- glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
-
-
-/* emit 64-bit shifts */
-static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
- TCGReg src, TCGReg sh_reg, int sh_imm)
-{
- tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
-}
-
-/* emit 32-bit shifts */
-static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
- TCGReg sh_reg, int sh_imm)
-{
- tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
-}
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
-{
- if (src != dst) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, LR, dst, src);
- } else {
- tcg_out_insn(s, RRE, LGR, dst, src);
- }
- }
- return true;
-}
-
-static const S390Opcode lli_insns[4] = {
- RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
-};
-
-static bool maybe_out_small_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long sval)
-{
- tcg_target_ulong uval = sval;
- int i;
-
- if (type == TCG_TYPE_I32) {
- uval = (uint32_t)sval;
- sval = (int32_t)sval;
- }
-
- /* Try all 32-bit insns that can load it in one go. */
- if (sval >= -0x8000 && sval < 0x8000) {
- tcg_out_insn(s, RI, LGHI, ret, sval);
- return true;
- }
-
- for (i = 0; i < 4; i++) {
- tcg_target_long mask = 0xffffull << i*16;
- if ((uval & mask) == uval) {
- tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
- return true;
- }
- }
-
- return false;
-}
-
-/* load a register with an immediate value */
-static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long sval, bool in_prologue)
-{
- tcg_target_ulong uval;
-
- /* Try all 32-bit insns that can load it in one go. */
- if (maybe_out_small_movi(s, type, ret, sval)) {
- return;
- }
-
- uval = sval;
- if (type == TCG_TYPE_I32) {
- uval = (uint32_t)sval;
- sval = (int32_t)sval;
- }
-
- /* Try all 48-bit insns that can load it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- if (sval == (int32_t)sval) {
- tcg_out_insn(s, RIL, LGFI, ret, sval);
- return;
- }
- if (uval <= 0xffffffff) {
- tcg_out_insn(s, RIL, LLILF, ret, uval);
- return;
- }
- if ((uval & 0xffffffff) == 0) {
- tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);
- return;
- }
- }
-
- /* Try for PC-relative address load. For odd addresses,
- attempt to use an offset from the start of the TB. */
- if ((sval & 1) == 0) {
- ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
- if (off == (int32_t)off) {
- tcg_out_insn(s, RIL, LARL, ret, off);
- return;
- }
- } else if (USE_REG_TB && !in_prologue) {
- ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr;
- if (off == sextract64(off, 0, 20)) {
- /* This is certain to be an address within TB, and therefore
- OFF will be negative; don't try RX_LA. */
- tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);
- return;
- }
- }
-
- /* A 32-bit unsigned value can be loaded in 2 insns. And given
- that LLILL, LLIHL, LLILF above did not succeed, we know that
- both insns are required. */
- if (uval <= 0xffffffff) {
- tcg_out_insn(s, RI, LLILL, ret, uval);
- tcg_out_insn(s, RI, IILH, ret, uval >> 16);
- return;
- }
-
- /* Otherwise, stuff it in the constant pool. */
- if (s390_facilities & FACILITY_GEN_INST_EXT) {
- tcg_out_insn(s, RIL, LGRL, ret, 0);
- new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
- } else if (USE_REG_TB && !in_prologue) {
- tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
- -(intptr_t)s->code_gen_ptr);
- } else {
- TCGReg base = ret ? ret : TCG_TMP0;
- tcg_out_insn(s, RIL, LARL, base, 0);
- new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
- tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0);
- }
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long sval)
-{
- tcg_out_movi_int(s, type, ret, sval, false);
-}
-
-/* Emit a load/store type instruction. Inputs are:
- DATA: The register to be loaded or stored.
- BASE+OFS: The effective address.
- OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
- OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
-
-static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
- TCGReg data, TCGReg base, TCGReg index,
- tcg_target_long ofs)
-{
- if (ofs < -0x80000 || ofs >= 0x80000) {
- /* Combine the low 20 bits of the offset with the actual load insn;
- the high 44 bits must come from an immediate load. */
- tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
- ofs = low;
-
- /* If we were already given an index register, add it in. */
- if (index != TCG_REG_NONE) {
- tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
- }
- index = TCG_TMP0;
- }
-
- if (opc_rx && ofs >= 0 && ofs < 0x1000) {
- tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
- } else {
- tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
- }
-}
-
-
-/* load data without address translation or endianness conversion */
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
- TCGReg base, intptr_t ofs)
-{
- if (type == TCG_TYPE_I32) {
- tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
- } else {
- tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
- }
-}
-
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
- TCGReg base, intptr_t ofs)
-{
- if (type == TCG_TYPE_I32) {
- tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
- } else {
- tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
- }
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- return false;
-}
-
-/* load data from an absolute host address */
-static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
-{
- intptr_t addr = (intptr_t)abs;
-
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
- ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
- if (disp == (int32_t)disp) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RIL, LRL, dest, disp);
- } else {
- tcg_out_insn(s, RIL, LGRL, dest, disp);
- }
- return;
- }
- }
- if (USE_REG_TB) {
- ptrdiff_t disp = abs - (void *)s->code_gen_ptr;
- if (disp == sextract64(disp, 0, 20)) {
- tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
- return;
- }
- }
-
- tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
- tcg_out_ld(s, type, dest, dest, addr & 0xffff);
-}
-
-static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
- int msb, int lsb, int ofs, int z)
-{
- /* Format RIE-f */
- tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
- tcg_out16(s, (msb << 8) | (z << 7) | lsb);
- tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
-}
-
-static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LGBR, dest, src);
- return;
- }
-
- if (type == TCG_TYPE_I32) {
- if (dest == src) {
- tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
- }
- tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
- tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
- }
-}
-
-static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LLGCR, dest, src);
- return;
- }
-
- if (dest == src) {
- tcg_out_movi(s, type, TCG_TMP0, 0xff);
- src = TCG_TMP0;
- } else {
- tcg_out_movi(s, type, dest, 0xff);
- }
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, NR, dest, src);
- } else {
- tcg_out_insn(s, RRE, NGR, dest, src);
- }
-}
-
-static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LGHR, dest, src);
- return;
- }
-
- if (type == TCG_TYPE_I32) {
- if (dest == src) {
- tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
- }
- tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
- tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
- }
-}
-
-static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LLGHR, dest, src);
- return;
- }
-
- if (dest == src) {
- tcg_out_movi(s, type, TCG_TMP0, 0xffff);
- src = TCG_TMP0;
- } else {
- tcg_out_movi(s, type, dest, 0xffff);
- }
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, NR, dest, src);
- } else {
- tcg_out_insn(s, RRE, NGR, dest, src);
- }
-}
-
-static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
-{
- tcg_out_insn(s, RRE, LGFR, dest, src);
-}
-
-static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
-{
- tcg_out_insn(s, RRE, LLGFR, dest, src);
-}
-
-/* Accept bit patterns like these:
- 0....01....1
- 1....10....0
- 1..10..01..1
- 0..01..10..0
- Copied from gcc sources. */
-static inline bool risbg_mask(uint64_t c)
-{
- uint64_t lsb;
- /* We don't change the number of transitions by inverting,
- so make sure we start with the LSB zero. */
- if (c & 1) {
- c = ~c;
- }
- /* Reject all zeros or all ones. */
- if (c == 0) {
- return false;
- }
- /* Find the first transition. */
- lsb = c & -c;
- /* Invert to look for a second transition. */
- c = ~c;
- /* Erase the first transition. */
- c &= -lsb;
- /* Find the second transition, if any. */
- lsb = c & -c;
- /* Match if all the bits are 1's, or if c is zero. */
- return c == -lsb;
-}
-
-static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
-{
- int msb, lsb;
- if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
- /* Achieve wraparound by swapping msb and lsb. */
- msb = 64 - ctz64(~val);
- lsb = clz64(~val) - 1;
- } else {
- msb = clz64(val);
- lsb = 63 - ctz64(val);
- }
- tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
-}
-
-static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
-{
- static const S390Opcode ni_insns[4] = {
- RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
- };
- static const S390Opcode nif_insns[2] = {
- RIL_NILF, RIL_NIHF
- };
- uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
- int i;
-
- /* Look for the zero-extensions. */
- if ((val & valid) == 0xffffffff) {
- tgen_ext32u(s, dest, dest);
- return;
- }
- if (s390_facilities & FACILITY_EXT_IMM) {
- if ((val & valid) == 0xff) {
- tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
- return;
- }
- if ((val & valid) == 0xffff) {
- tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
- return;
- }
- }
-
- /* Try all 32-bit insns that can perform it in one go. */
- for (i = 0; i < 4; i++) {
- tcg_target_ulong mask = ~(0xffffull << i*16);
- if (((val | ~valid) & mask) == mask) {
- tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
- return;
- }
- }
-
- /* Try all 48-bit insns that can perform it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- for (i = 0; i < 2; i++) {
- tcg_target_ulong mask = ~(0xffffffffull << i*32);
- if (((val | ~valid) & mask) == mask) {
- tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
- return;
- }
- }
- }
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
- tgen_andi_risbg(s, dest, dest, val);
- return;
- }
-
- /* Use the constant pool if USE_REG_TB, but not for small constants. */
- if (USE_REG_TB) {
- if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) {
- tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2,
- -(intptr_t)s->code_gen_ptr);
- return;
- }
- } else {
- tcg_out_movi(s, type, TCG_TMP0, val);
- }
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
- } else {
- tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
- }
-}
-
-static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
-{
- static const S390Opcode oi_insns[4] = {
- RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
- };
- static const S390Opcode oif_insns[2] = {
- RIL_OILF, RIL_OIHF
- };
-
- int i;
-
- /* Look for no-op. */
- if (unlikely(val == 0)) {
- return;
- }
-
- /* Try all 32-bit insns that can perform it in one go. */
- for (i = 0; i < 4; i++) {
- tcg_target_ulong mask = (0xffffull << i*16);
- if ((val & mask) != 0 && (val & ~mask) == 0) {
- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
- return;
- }
- }
-
- /* Try all 48-bit insns that can perform it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- for (i = 0; i < 2; i++) {
- tcg_target_ulong mask = (0xffffffffull << i*32);
- if ((val & mask) != 0 && (val & ~mask) == 0) {
- tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
- return;
- }
- }
- }
-
- /* Use the constant pool if USE_REG_TB, but not for small constants. */
- if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, OR, dest, TCG_TMP0);
- } else {
- tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);
- }
- } else if (USE_REG_TB) {
- tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, val, R_390_20, s->code_ptr - 2,
- -(intptr_t)s->code_gen_ptr);
- } else {
- /* Perform the OR via sequential modifications to the high and
- low parts. Do this via recursion to handle 16-bit vs 32-bit
- masks in each half. */
- tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
- tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
- tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
- }
-}
-
-static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
-{
- /* Try all 48-bit insns that can perform it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- if ((val & 0xffffffff00000000ull) == 0) {
- tcg_out_insn(s, RIL, XILF, dest, val);
- return;
- }
- if ((val & 0x00000000ffffffffull) == 0) {
- tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
- return;
- }
- }
-
- /* Use the constant pool if USE_REG_TB, but not for small constants. */
- if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, XR, dest, TCG_TMP0);
- } else {
- tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);
- }
- } else if (USE_REG_TB) {
- tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, val, R_390_20, s->code_ptr - 2,
- -(intptr_t)s->code_gen_ptr);
- } else {
- /* Perform the xor by parts. */
- tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
- if (val & 0xffffffff) {
- tcg_out_insn(s, RIL, XILF, dest, val);
- }
- if (val > 0xffffffff) {
- tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
- }
- }
-}
-
-static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
- TCGArg c2, bool c2const, bool need_carry)
-{
- bool is_unsigned = is_unsigned_cond(c);
- S390Opcode op;
-
- if (c2const) {
- if (c2 == 0) {
- if (!(is_unsigned && need_carry)) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, LTR, r1, r1);
- } else {
- tcg_out_insn(s, RRE, LTGR, r1, r1);
- }
- return tcg_cond_to_ltr_cond[c];
- }
- }
-
- if (!is_unsigned && c2 == (int16_t)c2) {
- op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI);
- tcg_out_insn_RI(s, op, r1, c2);
- goto exit;
- }
-
- if (s390_facilities & FACILITY_EXT_IMM) {
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RIL_CLFI : RIL_CFI);
- tcg_out_insn_RIL(s, op, r1, c2);
- goto exit;
- } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) {
- op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
- tcg_out_insn_RIL(s, op, r1, c2);
- goto exit;
- }
- }
-
- /* Use the constant pool, but not for small constants. */
- if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) {
- c2 = TCG_TMP0;
- /* fall through to reg-reg */
- } else if (USE_REG_TB) {
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RXY_CLY : RXY_CY);
- tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2,
- 4 - (intptr_t)s->code_gen_ptr);
- } else {
- op = (is_unsigned ? RXY_CLG : RXY_CG);
- tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, c2, R_390_20, s->code_ptr - 2,
- -(intptr_t)s->code_gen_ptr);
- }
- goto exit;
- } else {
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RIL_CLRL : RIL_CRL);
- tcg_out_insn_RIL(s, op, r1, 0);
- new_pool_label(s, (uint32_t)c2, R_390_PC32DBL,
- s->code_ptr - 2, 2 + 4);
- } else {
- op = (is_unsigned ? RIL_CLGRL : RIL_CGRL);
- tcg_out_insn_RIL(s, op, r1, 0);
- new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2);
- }
- goto exit;
- }
- }
-
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RR_CLR : RR_CR);
- tcg_out_insn_RR(s, op, r1, c2);
- } else {
- op = (is_unsigned ? RRE_CLGR : RRE_CGR);
- tcg_out_insn_RRE(s, op, r1, c2);
- }
-
- exit:
- return tcg_cond_to_s390_cond[c];
-}
-
-static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
- TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
-{
- int cc;
- bool have_loc;
-
- /* With LOC2, we can always emit the minimum 3 insns. */
- if (s390_facilities & FACILITY_LOAD_ON_COND2) {
- /* Emit: d = 0, d = (cc ? 1 : d). */
- cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
- tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
- return;
- }
-
- have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
-
- /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
- restart:
- switch (cond) {
- case TCG_COND_NE:
- /* X != 0 is X > 0. */
- if (c2const && c2 == 0) {
- cond = TCG_COND_GTU;
- } else {
- break;
- }
- /* fallthru */
-
- case TCG_COND_GTU:
- case TCG_COND_GT:
- /* The result of a compare has CC=2 for GT and CC=3 unused.
- ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
- tgen_cmp(s, type, cond, c1, c2, c2const, true);
- tcg_out_movi(s, type, dest, 0);
- tcg_out_insn(s, RRE, ALCGR, dest, dest);
- return;
-
- case TCG_COND_EQ:
- /* X == 0 is X <= 0. */
- if (c2const && c2 == 0) {
- cond = TCG_COND_LEU;
- } else {
- break;
- }
- /* fallthru */
-
- case TCG_COND_LEU:
- case TCG_COND_LE:
- /* As above, but we're looking for borrow, or !carry.
- The second insn computes d - d - borrow, or -1 for true
- and 0 for false. So we must mask to 1 bit afterward. */
- tgen_cmp(s, type, cond, c1, c2, c2const, true);
- tcg_out_insn(s, RRE, SLBGR, dest, dest);
- tgen_andi(s, type, dest, 1);
- return;
-
- case TCG_COND_GEU:
- case TCG_COND_LTU:
- case TCG_COND_LT:
- case TCG_COND_GE:
- /* Swap operands so that we can use LEU/GTU/GT/LE. */
- if (c2const) {
- if (have_loc) {
- break;
- }
- tcg_out_movi(s, type, TCG_TMP0, c2);
- c2 = c1;
- c2const = 0;
- c1 = TCG_TMP0;
- } else {
- TCGReg t = c1;
- c1 = c2;
- c2 = t;
- }
- cond = tcg_swap_cond(cond);
- goto restart;
-
- default:
- g_assert_not_reached();
- }
-
- cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
- if (have_loc) {
- /* Emit: d = 0, t = 1, d = (cc ? t : d). */
- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
- tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
- tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
- } else {
- /* Emit: d = 1; if (cc) goto over; d = 0; over: */
- tcg_out_movi(s, type, dest, 1);
- tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
- tcg_out_movi(s, type, dest, 0);
- }
-}
-
-static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
- TCGReg c1, TCGArg c2, int c2const,
- TCGArg v3, int v3const)
-{
- int cc;
- if (s390_facilities & FACILITY_LOAD_ON_COND) {
- cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
- if (v3const) {
- tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
- } else {
- tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
- }
- } else {
- c = tcg_invert_cond(c);
- cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
-
- /* Emit: if (cc) goto over; dest = r3; over: */
- tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
- tcg_out_insn(s, RRE, LGR, dest, v3);
- }
-}
-
-static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
- TCGArg a2, int a2const)
-{
- /* Since this sets both R and R+1, we have no choice but to store the
- result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
- QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
- tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
-
- if (a2const && a2 == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
- } else {
- if (a2const) {
- tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
- } else {
- tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
- }
- if (s390_facilities & FACILITY_LOAD_ON_COND) {
- /* Emit: if (one bit found) dest = r0. */
- tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
- } else {
- /* Emit: if (no one bit found) goto over; dest = r0; over: */
- tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
- tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
- }
- }
-}
-
-static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
- int ofs, int len, int z)
-{
- int lsb = (63 - ofs);
- int msb = lsb - (len - 1);
- tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
-}
-
-static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
- int ofs, int len)
-{
- tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
-}
-
-static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
-{
- ptrdiff_t off = dest - s->code_ptr;
- if (off == (int16_t)off) {
- tcg_out_insn(s, RI, BRC, cc, off);
- } else if (off == (int32_t)off) {
- tcg_out_insn(s, RIL, BRCL, cc, off);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
- tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
- }
-}
-
-static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
-{
- if (l->has_value) {
- tgen_gotoi(s, cc, l->u.value_ptr);
- } else if (USE_LONG_BRANCHES) {
- tcg_out16(s, RIL_BRCL | (cc << 4));
- tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2);
- s->code_ptr += 2;
- } else {
- tcg_out16(s, RI_BRC | (cc << 4));
- tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2);
- s->code_ptr += 1;
- }
-}
-
-static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
- TCGReg r1, TCGReg r2, TCGLabel *l)
-{
- intptr_t off = 0;
-
- if (l->has_value) {
- off = l->u.value_ptr - s->code_ptr;
- tcg_debug_assert(off == (int16_t)off);
- } else {
- tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
- }
-
- tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
- tcg_out16(s, off);
- tcg_out16(s, cc << 12 | (opc & 0xff));
-}
-
-static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
- TCGReg r1, int i2, TCGLabel *l)
-{
- tcg_target_long off = 0;
-
- if (l->has_value) {
- off = l->u.value_ptr - s->code_ptr;
- tcg_debug_assert(off == (int16_t)off);
- } else {
- tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
- }
-
- tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
- tcg_out16(s, off);
- tcg_out16(s, (i2 << 8) | (opc & 0xff));
-}
-
-static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
- TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
-{
- int cc;
-
- if (s390_facilities & FACILITY_GEN_INST_EXT) {
- bool is_unsigned = is_unsigned_cond(c);
- bool in_range;
- S390Opcode opc;
-
- cc = tcg_cond_to_s390_cond[c];
-
- if (!c2const) {
- opc = (type == TCG_TYPE_I32
- ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
- : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
- tgen_compare_branch(s, opc, cc, r1, c2, l);
- return;
- }
-
- /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
- If the immediate we've been given does not fit that range, we'll
- fall back to separate compare and branch instructions using the
- larger comparison range afforded by COMPARE IMMEDIATE. */
- if (type == TCG_TYPE_I32) {
- if (is_unsigned) {
- opc = RIE_CLIJ;
- in_range = (uint32_t)c2 == (uint8_t)c2;
- } else {
- opc = RIE_CIJ;
- in_range = (int32_t)c2 == (int8_t)c2;
- }
- } else {
- if (is_unsigned) {
- opc = RIE_CLGIJ;
- in_range = (uint64_t)c2 == (uint8_t)c2;
- } else {
- opc = RIE_CGIJ;
- in_range = (int64_t)c2 == (int8_t)c2;
- }
- }
- if (in_range) {
- tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
- return;
- }
- }
-
- cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
- tgen_branch(s, cc, l);
-}
-
-static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
-{
- ptrdiff_t off = dest - s->code_ptr;
- if (off == (int32_t)off) {
- tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
- tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
- }
-}
-
-static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
- TCGReg base, TCGReg index, int disp)
-{
- switch (opc & (MO_SSIZE | MO_BSWAP)) {
- case MO_UB:
- tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
- break;
- case MO_SB:
- tcg_out_insn(s, RXY, LGB, data, base, index, disp);
- break;
-
- case MO_UW | MO_BSWAP:
- /* swapped unsigned halfword load with upper bits zeroed */
- tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
- tgen_ext16u(s, TCG_TYPE_I64, data, data);
- break;
- case MO_UW:
- tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
- break;
-
- case MO_SW | MO_BSWAP:
- /* swapped sign-extended halfword load */
- tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
- tgen_ext16s(s, TCG_TYPE_I64, data, data);
- break;
- case MO_SW:
- tcg_out_insn(s, RXY, LGH, data, base, index, disp);
- break;
-
- case MO_UL | MO_BSWAP:
- /* swapped unsigned int load with upper bits zeroed */
- tcg_out_insn(s, RXY, LRV, data, base, index, disp);
- tgen_ext32u(s, data, data);
- break;
- case MO_UL:
- tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
- break;
-
- case MO_SL | MO_BSWAP:
- /* swapped sign-extended int load */
- tcg_out_insn(s, RXY, LRV, data, base, index, disp);
- tgen_ext32s(s, data, data);
- break;
- case MO_SL:
- tcg_out_insn(s, RXY, LGF, data, base, index, disp);
- break;
-
- case MO_Q | MO_BSWAP:
- tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
- break;
- case MO_Q:
- tcg_out_insn(s, RXY, LG, data, base, index, disp);
- break;
-
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
- TCGReg base, TCGReg index, int disp)
-{
- switch (opc & (MO_SIZE | MO_BSWAP)) {
- case MO_UB:
- if (disp >= 0 && disp < 0x1000) {
- tcg_out_insn(s, RX, STC, data, base, index, disp);
- } else {
- tcg_out_insn(s, RXY, STCY, data, base, index, disp);
- }
- break;
-
- case MO_UW | MO_BSWAP:
- tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
- break;
- case MO_UW:
- if (disp >= 0 && disp < 0x1000) {
- tcg_out_insn(s, RX, STH, data, base, index, disp);
- } else {
- tcg_out_insn(s, RXY, STHY, data, base, index, disp);
- }
- break;
-
- case MO_UL | MO_BSWAP:
- tcg_out_insn(s, RXY, STRV, data, base, index, disp);
- break;
- case MO_UL:
- if (disp >= 0 && disp < 0x1000) {
- tcg_out_insn(s, RX, ST, data, base, index, disp);
- } else {
- tcg_out_insn(s, RXY, STY, data, base, index, disp);
- }
- break;
-
- case MO_Q | MO_BSWAP:
- tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
- break;
- case MO_Q:
- tcg_out_insn(s, RXY, STG, data, base, index, disp);
- break;
-
- default:
- tcg_abort();
- }
-}
-
-#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
-
-/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
-
-/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
- addend into R2. Returns a register with the santitized guest address. */
-static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
- int mem_index, bool is_ld)
-{
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
- unsigned s_mask = (1 << s_bits) - 1;
- unsigned a_mask = (1 << a_bits) - 1;
- int fast_off = TLB_MASK_TABLE_OFS(mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- int ofs, a_off;
- uint64_t tlb_mask;
-
- tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off);
- tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_off);
-
- /* For aligned accesses, we check the first byte and include the alignment
- bits within the address. For unaligned access, we check that we don't
- cross pages using the address of the last byte of the access. */
- a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
- tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) {
- tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
- } else {
- tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
- tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
- }
-
- if (is_ld) {
- ofs = offsetof(CPUTLBEntry, addr_read);
- } else {
- ofs = offsetof(CPUTLBEntry, addr_write);
- }
- if (TARGET_LONG_BITS == 32) {
- tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
- } else {
- tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
- }
-
- tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE,
- offsetof(CPUTLBEntry, addend));
-
- if (TARGET_LONG_BITS == 32) {
- tgen_ext32u(s, TCG_REG_R3, addr_reg);
- return TCG_REG_R3;
- }
- return addr_reg;
-}
-
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
- TCGReg data, TCGReg addr,
- tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->datalo_reg = data;
- label->addrlo_reg = addr;
- label->raddr = raddr;
- label->label_ptr[0] = label_ptr;
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGReg addr_reg = lb->addrlo_reg;
- TCGReg data_reg = lb->datalo_reg;
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
-
- if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
- (intptr_t)s->code_ptr, 2)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
- if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
- }
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi);
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr);
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
- tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
-
- tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGReg addr_reg = lb->addrlo_reg;
- TCGReg data_reg = lb->datalo_reg;
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
-
- if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
- (intptr_t)s->code_ptr, 2)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
- if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
- }
- switch (opc & MO_SIZE) {
- case MO_UB:
- tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
- break;
- case MO_UW:
- tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
- break;
- case MO_UL:
- tgen_ext32u(s, TCG_REG_R4, data_reg);
- break;
- case MO_Q:
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
- break;
- default:
- tcg_abort();
- }
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
-
- tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
- return true;
-}
-#else
-static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
- TCGReg *index_reg, tcg_target_long *disp)
-{
- if (TARGET_LONG_BITS == 32) {
- tgen_ext32u(s, TCG_TMP0, *addr_reg);
- *addr_reg = TCG_TMP0;
- }
- if (guest_base < 0x80000) {
- *index_reg = TCG_REG_NONE;
- *disp = guest_base;
- } else {
- *index_reg = TCG_GUEST_BASE_REG;
- *disp = 0;
- }
-}
-#endif /* CONFIG_SOFTMMU */
-
-static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
-{
- MemOp opc = get_memop(oi);
-#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
- tcg_insn_unit *label_ptr;
- TCGReg base_reg;
-
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
-
- tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
- label_ptr = s->code_ptr;
- s->code_ptr += 1;
-
- tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
-
- add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
-#else
- TCGReg index_reg;
- tcg_target_long disp;
-
- tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
- tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
-#endif
-}
-
-static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
-{
- MemOp opc = get_memop(oi);
-#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
- tcg_insn_unit *label_ptr;
- TCGReg base_reg;
-
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
-
- tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
- label_ptr = s->code_ptr;
- s->code_ptr += 1;
-
- tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
-
- add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
-#else
- TCGReg index_reg;
- tcg_target_long disp;
-
- tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
- tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
-#endif
-}
-
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_,x),_i32): \
- case glue(glue(INDEX_op_,x),_i64)
-
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
-{
- S390Opcode op, op2;
- TCGArg a0, a1, a2;
-
- switch (opc) {
- case INDEX_op_exit_tb:
- /* Reuse the zeroing that exists for goto_ptr. */
- a0 = args[0];
- if (a0 == 0) {
- tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
- tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
- }
- break;
-
- case INDEX_op_goto_tb:
- a0 = args[0];
- if (s->tb_jmp_insn_offset) {
- /* branch displacement must be aligned for atomic patching;
- * see if we need to add extra nop before branch
- */
- if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
- tcg_out16(s, NOP);
- }
- tcg_debug_assert(!USE_REG_TB);
- tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- s->code_ptr += 2;
- } else {
- /* load address stored at s->tb_jmp_target_addr + a0 */
- tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
- s->tb_jmp_target_addr + a0);
- /* and go there */
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
- }
- set_jmp_reset_offset(s, a0);
-
- /* For the unlinked path of goto_tb, we need to reset
- TCG_REG_TB to the beginning of this TB. */
- if (USE_REG_TB) {
- int ofs = -tcg_current_code_size(s);
- assert(ofs == (int16_t)ofs);
- tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs);
- }
- break;
-
- case INDEX_op_goto_ptr:
- a0 = args[0];
- if (USE_REG_TB) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
- }
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
- break;
-
- OP_32_64(ld8u):
- /* ??? LLC (RXY format) is only present with the extended-immediate
- facility, whereas LLGC is always present. */
- tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(ld8s):
- /* ??? LB is no smaller than LGB, so no point to using it. */
- tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(ld16u):
- /* ??? LLH (RXY format) is only present with the extended-immediate
- facility, whereas LLGH is always present. */
- tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_ld16s_i32:
- tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_ld_i32:
- tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
-
- OP_32_64(st8):
- tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
- TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(st16):
- tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
- TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_st_i32:
- tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_add_i32:
- a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
- if (const_args[2]) {
- do_addi_32:
- if (a0 == a1) {
- if (a2 == (int16_t)a2) {
- tcg_out_insn(s, RI, AHI, a0, a2);
- break;
- }
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RIL, AFI, a0, a2);
- break;
- }
- }
- tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, AR, a0, a2);
- } else {
- tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
- }
- break;
- case INDEX_op_sub_i32:
- a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
- if (const_args[2]) {
- a2 = -a2;
- goto do_addi_32;
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, SR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, SRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_and_i32:
- a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_andi(s, TCG_TYPE_I32, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, NR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, NRK, a0, a1, a2);
- }
- break;
- case INDEX_op_or_i32:
- a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_ori(s, TCG_TYPE_I32, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, OR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, ORK, a0, a1, a2);
- }
- break;
- case INDEX_op_xor_i32:
- a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_xori(s, TCG_TYPE_I32, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, XR, args[0], args[2]);
- } else {
- tcg_out_insn(s, RRF, XRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_neg_i32:
- tcg_out_insn(s, RR, LCR, args[0], args[1]);
- break;
-
- case INDEX_op_mul_i32:
- if (const_args[2]) {
- if ((int32_t)args[2] == (int16_t)args[2]) {
- tcg_out_insn(s, RI, MHI, args[0], args[2]);
- } else {
- tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
- }
- } else {
- tcg_out_insn(s, RRE, MSR, args[0], args[2]);
- }
- break;
-
- case INDEX_op_div2_i32:
- tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
- break;
- case INDEX_op_divu2_i32:
- tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
- break;
-
- case INDEX_op_shl_i32:
- op = RS_SLL;
- op2 = RSY_SLLK;
- do_shift32:
- a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
- if (a0 == a1) {
- if (const_args[2]) {
- tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
- } else {
- tcg_out_sh32(s, op, a0, a2, 0);
- }
- } else {
- /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
- if (const_args[2]) {
- tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
- } else {
- tcg_out_sh64(s, op2, a0, a1, a2, 0);
- }
- }
- break;
- case INDEX_op_shr_i32:
- op = RS_SRL;
- op2 = RSY_SRLK;
- goto do_shift32;
- case INDEX_op_sar_i32:
- op = RS_SRA;
- op2 = RSY_SRAK;
- goto do_shift32;
-
- case INDEX_op_rotl_i32:
- /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
- } else {
- tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
- }
- break;
- case INDEX_op_rotr_i32:
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLL, args[0], args[1],
- TCG_REG_NONE, (32 - args[2]) & 31);
- } else {
- tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
- tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
- }
- break;
-
- case INDEX_op_ext8s_i32:
- tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i32:
- tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
- break;
- case INDEX_op_ext8u_i32:
- tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
- break;
- case INDEX_op_ext16u_i32:
- tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
- break;
-
- OP_32_64(bswap16):
- /* The TCG bswap definition requires bits 0-47 already be zero.
- Thus we don't need the G-type insns to implement bswap16_i64. */
- tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
- tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
- break;
- OP_32_64(bswap32):
- tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
- break;
-
- case INDEX_op_add2_i32:
- if (const_args[4]) {
- tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RR, ALR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
- break;
- case INDEX_op_sub2_i32:
- if (const_args[4]) {
- tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RR, SLR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
- break;
-
- case INDEX_op_br:
- tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
- break;
-
- case INDEX_op_brcond_i32:
- tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
- args[1], const_args[1], arg_label(args[3]));
- break;
- case INDEX_op_setcond_i32:
- tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_movcond_i32:
- tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
- args[2], const_args[2], args[3], const_args[3]);
- break;
-
- case INDEX_op_qemu_ld_i32:
- /* ??? Technically we can use a non-extending instruction. */
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args[0], args[1], args[2]);
- break;
- case INDEX_op_qemu_st_i32:
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_ld16s_i64:
- tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
- case INDEX_op_ld32u_i64:
- tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
- case INDEX_op_ld32s_i64:
- tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
- case INDEX_op_ld_i64:
- tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_st32_i64:
- tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i64:
- tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_add_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- do_addi_64:
- if (a0 == a1) {
- if (a2 == (int16_t)a2) {
- tcg_out_insn(s, RI, AGHI, a0, a2);
- break;
- }
- if (s390_facilities & FACILITY_EXT_IMM) {
- if (a2 == (int32_t)a2) {
- tcg_out_insn(s, RIL, AGFI, a0, a2);
- break;
- } else if (a2 == (uint32_t)a2) {
- tcg_out_insn(s, RIL, ALGFI, a0, a2);
- break;
- } else if (-a2 == (uint32_t)-a2) {
- tcg_out_insn(s, RIL, SLGFI, a0, -a2);
- break;
- }
- }
- }
- tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, AGR, a0, a2);
- } else {
- tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
- }
- break;
- case INDEX_op_sub_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- a2 = -a2;
- goto do_addi_64;
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, SGR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_and_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, NGR, args[0], args[2]);
- } else {
- tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
- }
- break;
- case INDEX_op_or_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_ori(s, TCG_TYPE_I64, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, OGR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
- }
- break;
- case INDEX_op_xor_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_xori(s, TCG_TYPE_I64, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, XGR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_neg_i64:
- tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
- break;
- case INDEX_op_bswap64_i64:
- tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
- break;
-
- case INDEX_op_mul_i64:
- if (const_args[2]) {
- if (args[2] == (int16_t)args[2]) {
- tcg_out_insn(s, RI, MGHI, args[0], args[2]);
- } else {
- tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
- }
- } else {
- tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
- }
- break;
-
- case INDEX_op_div2_i64:
- /* ??? We get an unnecessary sign-extension of the dividend
- into R3 with this definition, but as we do in fact always
- produce both quotient and remainder using INDEX_op_div_i64
- instead requires jumping through even more hoops. */
- tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
- break;
- case INDEX_op_divu2_i64:
- tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
- break;
- case INDEX_op_mulu2_i64:
- tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
- break;
-
- case INDEX_op_shl_i64:
- op = RSY_SLLG;
- do_shift64:
- if (const_args[2]) {
- tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
- } else {
- tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
- }
- break;
- case INDEX_op_shr_i64:
- op = RSY_SRLG;
- goto do_shift64;
- case INDEX_op_sar_i64:
- op = RSY_SRAG;
- goto do_shift64;
-
- case INDEX_op_rotl_i64:
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
- TCG_REG_NONE, args[2]);
- } else {
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
- }
- break;
- case INDEX_op_rotr_i64:
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
- TCG_REG_NONE, (64 - args[2]) & 63);
- } else {
- /* We can use the smaller 32-bit negate because only the
- low 6 bits are examined for the rotate. */
- tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
- }
- break;
-
- case INDEX_op_ext8s_i64:
- tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i64:
- tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ext_i32_i64:
- case INDEX_op_ext32s_i64:
- tgen_ext32s(s, args[0], args[1]);
- break;
- case INDEX_op_ext8u_i64:
- tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ext16u_i64:
- tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_extu_i32_i64:
- case INDEX_op_ext32u_i64:
- tgen_ext32u(s, args[0], args[1]);
- break;
-
- case INDEX_op_add2_i64:
- if (const_args[4]) {
- if ((int64_t)args[4] >= 0) {
- tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
- }
- } else {
- tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
- break;
- case INDEX_op_sub2_i64:
- if (const_args[4]) {
- if ((int64_t)args[4] >= 0) {
- tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
- }
- } else {
- tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
- break;
-
- case INDEX_op_brcond_i64:
- tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
- args[1], const_args[1], arg_label(args[3]));
- break;
- case INDEX_op_setcond_i64:
- tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_movcond_i64:
- tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
- args[2], const_args[2], args[3], const_args[3]);
- break;
-
- OP_32_64(deposit):
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[1]) {
- tgen_deposit(s, a0, a2, args[3], args[4], 1);
- } else {
- /* Since we can't support "0Z" as a constraint, we allow a1 in
- any register. Fix things up as if a matching constraint. */
- if (a0 != a1) {
- TCGType type = (opc == INDEX_op_deposit_i64);
- if (a0 == a2) {
- tcg_out_mov(s, type, TCG_TMP0, a2);
- a2 = TCG_TMP0;
- }
- tcg_out_mov(s, type, a0, a1);
- }
- tgen_deposit(s, a0, a2, args[3], args[4], 0);
- }
- break;
-
- OP_32_64(extract):
- tgen_extract(s, args[0], args[1], args[2], args[3]);
- break;
-
- case INDEX_op_clz_i64:
- tgen_clz(s, args[0], args[1], args[2], const_args[2]);
- break;
-
- case INDEX_op_mb:
- /* The host memory model is quite strong, we simply need to
- serialize the instruction stream. */
- if (args[0] & TCG_MO_ST_LD) {
- tcg_out_insn(s, RR, BCR,
- s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
- }
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
- static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
- static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
- static const TCGTargetOpDef a2_r
- = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
- static const TCGTargetOpDef a2_ri
- = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
- static const TCGTargetOpDef a2_rA
- = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return &r_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_add_i64:
- return &r_r_ri;
- case INDEX_op_sub_i32:
- case INDEX_op_sub_i64:
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
- case INDEX_op_or_i32:
- case INDEX_op_or_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-
- case INDEX_op_mul_i32:
- /* If we have the general-instruction-extensions, then we have
- MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
- have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
- case INDEX_op_mul_i64:
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
-
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- return &r_r_ri;
-
- case INDEX_op_rotl_i32:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotr_i64:
- return &r_r_ri;
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return &r_ri;
-
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap32_i32:
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap64_i64:
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext8u_i64:
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext16u_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_extract_i32:
- case INDEX_op_extract_i64:
- return &r_r;
-
- case INDEX_op_clz_i64:
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return &r_r_ri;
-
- case INDEX_op_qemu_ld_i32:
- case INDEX_op_qemu_ld_i64:
- return &r_L;
- case INDEX_op_qemu_st_i64:
- case INDEX_op_qemu_st_i32:
- return &L_L;
-
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "rZ", "r" } };
- return &dep;
- }
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
- static const TCGTargetOpDef movc_l
- = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
- return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
- }
- case INDEX_op_div2_i32:
- case INDEX_op_div2_i64:
- case INDEX_op_divu2_i32:
- case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "b", "a", "0", "1", "r" } };
- return &div2;
- }
- case INDEX_op_mulu2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "b", "a", "0", "r" } };
- return &mul2;
- }
-
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
- case INDEX_op_add2_i64:
- case INDEX_op_sub2_i64:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
-
- default:
- break;
- }
- return NULL;
-}
-
-static void query_s390_facilities(void)
-{
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
-
- /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
- is present on all 64-bit systems, but let's check for it anyway. */
- if (hwcap & HWCAP_S390_STFLE) {
- register int r0 __asm__("0");
- register void *r1 __asm__("1");
-
- /* stfle 0(%r1) */
- r1 = &s390_facilities;
- asm volatile(".word 0xb2b0,0x1000"
- : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
- }
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- query_s390_facilities();
-
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
-
- tcg_target_call_clobber_regs = 0;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
- /* The r6 register is technically call-saved, but it's also a parameter
- register, so it can get killed by setup for the qemu_st helper. */
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
- /* The return register can be considered call-clobbered. */
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
- /* XXX many insns can't be used with R0, so we better avoid it for now */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
- if (USE_REG_TB) {
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
- }
-}
-
-#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
- + TCG_STATIC_CALL_ARGS_SIZE \
- + CPU_TEMP_BUF_NLONGS * sizeof(long)))
-
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- /* stmg %r6,%r15,48(%r15) (save registers) */
- tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
-
- /* aghi %r15,-frame_size */
- tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
-
- tcg_set_frame(s, TCG_REG_CALL_STACK,
- TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
-
-#ifndef CONFIG_SOFTMMU
- if (guest_base >= 0x80000) {
- tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
- tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
- }
-#endif
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- if (USE_REG_TB) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,
- tcg_target_call_iarg_regs[1]);
- }
-
- /* br %r3 (go to TB) */
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
-
- /*
- * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
- * and fall through to the rest of the epilogue.
- */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
-
- /* TB epilogue */
- tb_ret_addr = s->code_ptr;
-
- /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
- tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
- FRAME_SIZE + 48);
-
- /* br %r14 (return) */
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- memset(p, 0x07, count * sizeof(tcg_insn_unit));
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[18];
-} DebugFrame;
-
-/* We're expecting a 2 byte uleb128 encoded value. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-
-#define ELF_HOST_MACHINE EM_S390
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = 8, /* sleb128 8 */
- .h.cie.return_column = TCG_REG_R14,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x86, 6, /* DW_CFA_offset, %r6, 48 */
- 0x87, 7, /* DW_CFA_offset, %r7, 56 */
- 0x88, 8, /* DW_CFA_offset, %r8, 64 */
- 0x89, 9, /* DW_CFA_offset, %r92, 72 */
- 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
- 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
- 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
- 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
- 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
- }
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "../tcg-pool.c.inc"
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "%g0",
+ "%g1",
+ "%g2",
+ "%g3",
+ "%g4",
+ "%g5",
+ "%g6",
+ "%g7",
+ "%o0",
+ "%o1",
+ "%o2",
+ "%o3",
+ "%o4",
+ "%o5",
+ "%o6",
+ "%o7",
+ "%l0",
+ "%l1",
+ "%l2",
+ "%l3",
+ "%l4",
+ "%l5",
+ "%l6",
+ "%l7",
+ "%i0",
+ "%i1",
+ "%i2",
+ "%i3",
+ "%i4",
+ "%i5",
+ "%i6",
+ "%i7",
+};
+#endif
+
+#ifdef __arch64__
+# define SPARC64 1
+#else
+# define SPARC64 0
+#endif
+
+/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
+ registers. These are saved manually by the kernel in full 64-bit
+ slots. The %i and %l registers are saved by the register window
+ mechanism, which only allocates space for 32 bits. Given that this
+ window spill/fill can happen on any signal, we must consider the
+ high bits of the %i and %l registers garbage at all times. */
+#if SPARC64
+# define ALL_64 0xffffffffu
+#else
+# define ALL_64 0xffffu
+#endif
+
+/* Define some temporary registers. T2 is used for constant generation. */
+#define TCG_REG_T1 TCG_REG_G1
+#define TCG_REG_T2 TCG_REG_O7
+
+#ifndef CONFIG_SOFTMMU
+# define TCG_GUEST_BASE_REG TCG_REG_I5
+#endif
+
+#define TCG_REG_TB TCG_REG_I1
+#define USE_REG_TB (sizeof(void *) > 4)
+
+static const int tcg_target_reg_alloc_order[] = {
+ TCG_REG_L0,
+ TCG_REG_L1,
+ TCG_REG_L2,
+ TCG_REG_L3,
+ TCG_REG_L4,
+ TCG_REG_L5,
+ TCG_REG_L6,
+ TCG_REG_L7,
+
+ TCG_REG_I0,
+ TCG_REG_I1,
+ TCG_REG_I2,
+ TCG_REG_I3,
+ TCG_REG_I4,
+ TCG_REG_I5,
+
+ TCG_REG_G2,
+ TCG_REG_G3,
+ TCG_REG_G4,
+ TCG_REG_G5,
+
+ TCG_REG_O0,
+ TCG_REG_O1,
+ TCG_REG_O2,
+ TCG_REG_O3,
+ TCG_REG_O4,
+ TCG_REG_O5,
+};
+
+static const int tcg_target_call_iarg_regs[6] = {
+ TCG_REG_O0,
+ TCG_REG_O1,
+ TCG_REG_O2,
+ TCG_REG_O3,
+ TCG_REG_O4,
+ TCG_REG_O5,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_O0,
+ TCG_REG_O1,
+ TCG_REG_O2,
+ TCG_REG_O3,
+};
+
+#define INSN_OP(x) ((x) << 30)
+#define INSN_OP2(x) ((x) << 22)
+#define INSN_OP3(x) ((x) << 19)
+#define INSN_OPF(x) ((x) << 5)
+#define INSN_RD(x) ((x) << 25)
+#define INSN_RS1(x) ((x) << 14)
+#define INSN_RS2(x) (x)
+#define INSN_ASI(x) ((x) << 5)
+
+#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
+#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
+#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
+#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
+#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
+#define INSN_COND(x) ((x) << 25)
+
+#define COND_N 0x0
+#define COND_E 0x1
+#define COND_LE 0x2
+#define COND_L 0x3
+#define COND_LEU 0x4
+#define COND_CS 0x5
+#define COND_NEG 0x6
+#define COND_VS 0x7
+#define COND_A 0x8
+#define COND_NE 0x9
+#define COND_G 0xa
+#define COND_GE 0xb
+#define COND_GU 0xc
+#define COND_CC 0xd
+#define COND_POS 0xe
+#define COND_VC 0xf
+#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
+
+#define RCOND_Z 1
+#define RCOND_LEZ 2
+#define RCOND_LZ 3
+#define RCOND_NZ 5
+#define RCOND_GZ 6
+#define RCOND_GEZ 7
+
+#define MOVCC_ICC (1 << 18)
+#define MOVCC_XCC (1 << 18 | 1 << 12)
+
+#define BPCC_ICC 0
+#define BPCC_XCC (2 << 20)
+#define BPCC_PT (1 << 19)
+#define BPCC_PN 0
+#define BPCC_A (1 << 29)
+
+#define BPR_PT BPCC_PT
+
+#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
+#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
+#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
+#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
+#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
+#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
+#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
+#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
+#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
+#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
+#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08))
+#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c))
+#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
+#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
+#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
+#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
+#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
+#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
+#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
+#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
+#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
+
+#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
+#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
+
+#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
+#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
+#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
+
+#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
+#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
+#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
+
+#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
+#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
+#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
+#define RETURN (INSN_OP(2) | INSN_OP3(0x39))
+#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
+#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
+#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
+#define CALL INSN_OP(1)
+#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
+#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
+#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
+#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
+#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
+#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
+#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
+#define STB (INSN_OP(3) | INSN_OP3(0x05))
+#define STH (INSN_OP(3) | INSN_OP3(0x06))
+#define STW (INSN_OP(3) | INSN_OP3(0x04))
+#define STX (INSN_OP(3) | INSN_OP3(0x0e))
+#define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
+#define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
+#define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
+#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
+#define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
+#define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
+#define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
+#define STBA (INSN_OP(3) | INSN_OP3(0x15))
+#define STHA (INSN_OP(3) | INSN_OP3(0x16))
+#define STWA (INSN_OP(3) | INSN_OP3(0x14))
+#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
+
+#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
+
+#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0)
+
+#ifndef ASI_PRIMARY_LITTLE
+#define ASI_PRIMARY_LITTLE 0x88
+#endif
+
+#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
+#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
+#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
+#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
+#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
+
+#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
+#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
+#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
+
+#ifndef use_vis3_instructions
+bool use_vis3_instructions;
+#endif
+
+static inline int check_fit_i64(int64_t val, unsigned int bits)
+{
+ return val == sextract64(val, 0, bits);
+}
+
+static inline int check_fit_i32(int32_t val, unsigned int bits)
+{
+ return val == sextract32(val, 0, bits);
+}
+
+#define check_fit_tl check_fit_i64
+#if SPARC64
+# define check_fit_ptr check_fit_i64
+#else
+# define check_fit_ptr check_fit_i32
+#endif
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ uint32_t insn = *code_ptr;
+ intptr_t pcrel;
+
+ value += addend;
+ pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr);
+
+ switch (type) {
+ case R_SPARC_WDISP16:
+ assert(check_fit_ptr(pcrel >> 2, 16));
+ insn &= ~INSN_OFF16(-1);
+ insn |= INSN_OFF16(pcrel);
+ break;
+ case R_SPARC_WDISP19:
+ assert(check_fit_ptr(pcrel >> 2, 19));
+ insn &= ~INSN_OFF19(-1);
+ insn |= INSN_OFF19(pcrel);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ *code_ptr = insn;
+ return true;
+}
+
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'r':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ break;
+ case 'R':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = ALL_64;
+ break;
+ case 'A': /* qemu_ld/st address constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
+ reserve_helpers:
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
+ break;
+ case 's': /* qemu_st data 32-bit constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff;
+ goto reserve_helpers;
+ case 'S': /* qemu_st data 64-bit constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = ALL_64;
+ goto reserve_helpers;
+ case 'I':
+ ct->ct |= TCG_CT_CONST_S11;
+ break;
+ case 'J':
+ ct->ct |= TCG_CT_CONST_S13;
+ break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+/* test if a constant matches the constraint */
+static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ int ct = arg_ct->ct;
+
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
+ return 1;
+ } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1,
+ TCGReg rs2, int op)
+{
+ tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2));
+}
+
+static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
+ int32_t offset, int op)
+{
+ tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset));
+}
+
+static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
+ int32_t val2, int val2const, int op)
+{
+ tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
+ | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
+}
+
+static inline bool tcg_out_mov(TCGContext *s, TCGType type,
+ TCGReg ret, TCGReg arg)
+{
+ if (ret != arg) {
+ tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
+ }
+ return true;
+}
+
+static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
+{
+ tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
+}
+
+static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)
+{
+ tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
+}
+
+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long arg, bool in_prologue)
+{
+ tcg_target_long hi, lo = (int32_t)arg;
+ tcg_target_long test, lsb;
+
+ /* Make sure we test 32-bit constants for imm13 properly. */
+ if (type == TCG_TYPE_I32) {
+ arg = lo;
+ }
+
+ /* A 13-bit constant sign-extended to 64-bits. */
+ if (check_fit_tl(arg, 13)) {
+ tcg_out_movi_imm13(s, ret, arg);
+ return;
+ }
+
+ /* A 13-bit constant relative to the TB. */
+ if (!in_prologue && USE_REG_TB) {
+ test = arg - (uintptr_t)s->code_gen_ptr;
+ if (check_fit_ptr(test, 13)) {
+ tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD);
+ return;
+ }
+ }
+
+ /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
+ if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
+ tcg_out_sethi(s, ret, arg);
+ if (arg & 0x3ff) {
+ tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
+ }
+ return;
+ }
+
+ /* A 32-bit constant sign-extended to 64-bits. */
+ if (arg == lo) {
+ tcg_out_sethi(s, ret, ~arg);
+ tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
+ return;
+ }
+
+ /* A 21-bit constant, shifted. */
+ lsb = ctz64(arg);
+ test = (tcg_target_long)arg >> lsb;
+ if (check_fit_tl(test, 13)) {
+ tcg_out_movi_imm13(s, ret, test);
+ tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
+ return;
+ } else if (lsb > 10 && test == extract64(test, 0, 21)) {
+ tcg_out_sethi(s, ret, test << 10);
+ tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);
+ return;
+ }
+
+ /* A 64-bit constant decomposed into 2 32-bit pieces. */
+ if (check_fit_i32(lo, 13)) {
+ hi = (arg - lo) >> 32;
+ tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
+ tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
+ tcg_out_arithi(s, ret, ret, lo, ARITH_ADD);
+ } else {
+ hi = arg >> 32;
+ tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo);
+ tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
+ tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR);
+ }
+}
+
+static inline void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ tcg_out_movi_int(s, type, ret, arg, false);
+}
+
+static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
+ TCGReg a2, int op)
+{
+ tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
+}
+
+static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
+ intptr_t offset, int op)
+{
+ if (check_fit_ptr(offset, 13)) {
+ tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
+ INSN_IMM13(offset));
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
+ tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
+ }
+}
+
+static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg arg1, intptr_t arg2)
+{
+ tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
+}
+
+static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
+{
+ tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ if (val == 0) {
+ tcg_out_st(s, type, TCG_REG_G0, base, ofs);
+ return true;
+ }
+ return false;
+}
+
+static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg)
+{
+ intptr_t diff = arg - (uintptr_t)s->code_gen_ptr;
+ if (USE_REG_TB && check_fit_ptr(diff, 13)) {
+ tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
+ return;
+ }
+ tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);
+ tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);
+}
+
+static inline void tcg_out_sety(TCGContext *s, TCGReg rs)
+{
+ tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
+}
+
+static inline void tcg_out_rdy(TCGContext *s, TCGReg rd)
+{
+ tcg_out32(s, RDY | INSN_RD(rd));
+}
+
+static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
+ int32_t val2, int val2const, int uns)
+{
+ /* Load Y with the sign/zero extension of RS1 to 64-bits. */
+ if (uns) {
+ tcg_out_sety(s, TCG_REG_G0);
+ } else {
+ tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
+ tcg_out_sety(s, TCG_REG_T1);
+ }
+
+ tcg_out_arithc(s, rd, rs1, val2, val2const,
+ uns ? ARITH_UDIV : ARITH_SDIV);
+}
+
+static inline void tcg_out_nop(TCGContext *s)
+{
+ tcg_out32(s, NOP);
+}
+
+static const uint8_t tcg_cond_to_bcond[] = {
+ [TCG_COND_EQ] = COND_E,
+ [TCG_COND_NE] = COND_NE,
+ [TCG_COND_LT] = COND_L,
+ [TCG_COND_GE] = COND_GE,
+ [TCG_COND_LE] = COND_LE,
+ [TCG_COND_GT] = COND_G,
+ [TCG_COND_LTU] = COND_CS,
+ [TCG_COND_GEU] = COND_CC,
+ [TCG_COND_LEU] = COND_LEU,
+ [TCG_COND_GTU] = COND_GU,
+};
+
+static const uint8_t tcg_cond_to_rcond[] = {
+ [TCG_COND_EQ] = RCOND_Z,
+ [TCG_COND_NE] = RCOND_NZ,
+ [TCG_COND_LT] = RCOND_LZ,
+ [TCG_COND_GT] = RCOND_GZ,
+ [TCG_COND_LE] = RCOND_LEZ,
+ [TCG_COND_GE] = RCOND_GEZ
+};
+
+static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
+{
+ tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
+}
+
+static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
+{
+ int off19 = 0;
+
+ if (l->has_value) {
+ off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr));
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0);
+ }
+ tcg_out_bpcc0(s, scond, flags, off19);
+}
+
+static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const)
+{
+ tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
+}
+
+static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
+ int32_t arg2, int const_arg2, TCGLabel *l)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2);
+ tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l);
+ tcg_out_nop(s);
+}
+
+static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret,
+ int32_t v1, int v1const)
+{
+ tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
+}
+
+static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg c1, int32_t c2, int c2const,
+ int32_t v1, int v1const)
+{
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
+}
+
+static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1,
+ int32_t arg2, int const_arg2, TCGLabel *l)
+{
+ /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
+ if (arg2 == 0 && !is_unsigned_cond(cond)) {
+ int off16 = 0;
+
+ if (l->has_value) {
+ off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr));
+ } else {
+ tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0);
+ }
+ tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
+ | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
+ } else {
+ tcg_out_cmp(s, arg1, arg2, const_arg2);
+ tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l);
+ }
+ tcg_out_nop(s);
+}
+
+static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1,
+ int32_t v1, int v1const)
+{
+ tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
+ | (tcg_cond_to_rcond[cond] << 10)
+ | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
+}
+
+static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg c1, int32_t c2, int c2const,
+ int32_t v1, int v1const)
+{
+ /* For 64-bit signed comparisons vs zero, we can avoid the compare.
+ Note that the immediate range is one bit smaller, so we must check
+ for that as well. */
+ if (c2 == 0 && !is_unsigned_cond(cond)
+ && (!v1const || check_fit_i32(v1, 10))) {
+ tcg_out_movr(s, cond, ret, c1, v1, v1const);
+ } else {
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
+ }
+}
+
+static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg c1, int32_t c2, int c2const)
+{
+ /* For 32-bit comparisons, we can play games with ADDC/SUBC. */
+ switch (cond) {
+ case TCG_COND_LTU:
+ case TCG_COND_GEU:
+ /* The result of the comparison is in the carry bit. */
+ break;
+
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ /* For equality, we can transform to inequality vs zero. */
+ if (c2 != 0) {
+ tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR);
+ c2 = TCG_REG_T1;
+ } else {
+ c2 = c1;
+ }
+ c1 = TCG_REG_G0, c2const = 0;
+ cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
+ break;
+
+ case TCG_COND_GTU:
+ case TCG_COND_LEU:
+ /* If we don't need to load a constant into a register, we can
+ swap the operands on GTU/LEU. There's no benefit to loading
+ the constant into a temporary register. */
+ if (!c2const || c2 == 0) {
+ TCGReg t = c1;
+ c1 = c2;
+ c2 = t;
+ c2const = 0;
+ cond = tcg_swap_cond(cond);
+ break;
+ }
+ /* FALLTHRU */
+
+ default:
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
+ return;
+ }
+
+ tcg_out_cmp(s, c1, c2, c2const);
+ if (cond == TCG_COND_LTU) {
+ tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
+ } else {
+ tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
+ }
+}
+
+static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg c1, int32_t c2, int c2const)
+{
+ if (use_vis3_instructions) {
+ switch (cond) {
+ case TCG_COND_NE:
+ if (c2 != 0) {
+ break;
+ }
+ c2 = c1, c2const = 0, c1 = TCG_REG_G0;
+ /* FALLTHRU */
+ case TCG_COND_LTU:
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC);
+ return;
+ default:
+ break;
+ }
+ }
+
+ /* For 64-bit signed comparisons vs zero, we can avoid the compare
+ if the input does not overlap the output. */
+ if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out_movr(s, cond, ret, c1, 1, 1);
+ } else {
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
+ }
+}
+
+static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh,
+ TCGReg al, TCGReg ah, int32_t bl, int blconst,
+ int32_t bh, int bhconst, int opl, int oph)
+{
+ TCGReg tmp = TCG_REG_T1;
+
+ /* Note that the low parts are fully consumed before tmp is set. */
+ if (rl != ah && (bhconst || rl != bh)) {
+ tmp = rl;
+ }
+
+ tcg_out_arithc(s, tmp, al, bl, blconst, opl);
+ tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
+ tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
+}
+
+static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
+ TCGReg al, TCGReg ah, int32_t bl, int blconst,
+ int32_t bh, int bhconst, bool is_sub)
+{
+ TCGReg tmp = TCG_REG_T1;
+
+ /* Note that the low parts are fully consumed before tmp is set. */
+ if (rl != ah && (bhconst || rl != bh)) {
+ tmp = rl;
+ }
+
+ tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC);
+
+ if (use_vis3_instructions && !is_sub) {
+ /* Note that ADDXC doesn't accept immediates. */
+ if (bhconst && bh != 0) {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh);
+ bh = TCG_REG_T2;
+ }
+ tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
+ } else if (bh == TCG_REG_G0) {
+ /* If we have a zero, we can perform the operation in two insns,
+ with the arithmetic first, and a conditional move into place. */
+ if (rh == ah) {
+ tcg_out_arithi(s, TCG_REG_T2, ah, 1,
+ is_sub ? ARITH_SUB : ARITH_ADD);
+ tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
+ } else {
+ tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
+ tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
+ }
+ } else {
+ /* Otherwise adjust BH as if there is carry into T2 ... */
+ if (bhconst) {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1));
+ } else {
+ tcg_out_arithi(s, TCG_REG_T2, bh, 1,
+ is_sub ? ARITH_SUB : ARITH_ADD);
+ }
+ /* ... smoosh T2 back to original BH if carry is clear ... */
+ tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
+ /* ... and finally perform the arithmetic with the new operand. */
+ tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
+ }
+
+ tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
+}
+
+static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest,
+ bool in_prologue)
+{
+ ptrdiff_t disp = tcg_pcrel_diff(s, dest);
+
+ if (disp == (int32_t)disp) {
+ tcg_out32(s, CALL | (uint32_t)disp >> 2);
+ } else {
+ uintptr_t desti = (uintptr_t)dest;
+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1,
+ desti & ~0xfff, in_prologue);
+ tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL);
+ }
+}
+
+static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
+{
+ tcg_out_call_nodelay(s, dest, false);
+ tcg_out_nop(s);
+}
+
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
+ tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
+}
+
+#ifdef CONFIG_SOFTMMU
+static tcg_insn_unit *qemu_ld_trampoline[16];
+static tcg_insn_unit *qemu_st_trampoline[16];
+
+static void emit_extend(TCGContext *s, TCGReg r, int op)
+{
+ /* Emit zero extend of 8, 16 or 32 bit data as
+ * required by the MO_* value op; do nothing for 64 bit.
+ */
+ switch (op & MO_SIZE) {
+ case MO_8:
+ tcg_out_arithi(s, r, r, 0xff, ARITH_AND);
+ break;
+ case MO_16:
+ tcg_out_arithi(s, r, r, 16, SHIFT_SLL);
+ tcg_out_arithi(s, r, r, 16, SHIFT_SRL);
+ break;
+ case MO_32:
+ if (SPARC64) {
+ tcg_out_arith(s, r, r, 0, SHIFT_SRL);
+ }
+ break;
+ case MO_64:
+ break;
+ }
+}
+
+static void build_trampolines(TCGContext *s)
+{
+ static void * const qemu_ld_helpers[16] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LESW] = helper_le_ldsw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BESW] = helper_be_ldsw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+ };
+ static void * const qemu_st_helpers[16] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+ };
+
+ int i;
+ TCGReg ra;
+
+ for (i = 0; i < 16; ++i) {
+ if (qemu_ld_helpers[i] == NULL) {
+ continue;
+ }
+
+ /* May as well align the trampoline. */
+ while ((uintptr_t)s->code_ptr & 15) {
+ tcg_out_nop(s);
+ }
+ qemu_ld_trampoline[i] = s->code_ptr;
+
+ if (SPARC64 || TARGET_LONG_BITS == 32) {
+ ra = TCG_REG_O3;
+ } else {
+ /* Install the high part of the address. */
+ tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
+ ra = TCG_REG_O4;
+ }
+
+ /* Set the retaddr operand. */
+ tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
+ /* Set the env operand. */
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
+ /* Tail call. */
+ tcg_out_call_nodelay(s, qemu_ld_helpers[i], true);
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
+ }
+
+ for (i = 0; i < 16; ++i) {
+ if (qemu_st_helpers[i] == NULL) {
+ continue;
+ }
+
+ /* May as well align the trampoline. */
+ while ((uintptr_t)s->code_ptr & 15) {
+ tcg_out_nop(s);
+ }
+ qemu_st_trampoline[i] = s->code_ptr;
+
+ if (SPARC64) {
+ emit_extend(s, TCG_REG_O2, i);
+ ra = TCG_REG_O4;
+ } else {
+ ra = TCG_REG_O1;
+ if (TARGET_LONG_BITS == 64) {
+ /* Install the high part of the address. */
+ tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
+ ra += 2;
+ } else {
+ ra += 1;
+ }
+ if ((i & MO_SIZE) == MO_64) {
+ /* Install the high part of the data. */
+ tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
+ ra += 2;
+ } else {
+ emit_extend(s, ra, i);
+ ra += 1;
+ }
+ /* Skip the oi argument. */
+ ra += 1;
+ }
+
+ /* Set the retaddr operand. */
+ if (ra >= TCG_REG_O6) {
+ tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK,
+ TCG_TARGET_CALL_STACK_OFFSET);
+ ra = TCG_REG_G1;
+ }
+ tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
+ /* Set the env operand. */
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
+ /* Tail call. */
+ tcg_out_call_nodelay(s, qemu_st_helpers[i], true);
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
+ }
+}
+#endif
+
+/* Generate global QEMU prologue and epilogue code */
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ int tmp_buf_size, frame_size;
+
+ /* The TCG temp buffer is at the top of the frame, immediately
+ below the frame pointer. */
+ tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long);
+ tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size,
+ tmp_buf_size);
+
+ /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is
+ otherwise the minimal frame usable by callees. */
+ frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS;
+ frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size;
+ frame_size += TCG_TARGET_STACK_ALIGN - 1;
+ frame_size &= -TCG_TARGET_STACK_ALIGN;
+ tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
+ INSN_IMM13(-frame_size));
+
+#ifndef CONFIG_SOFTMMU
+ if (guest_base != 0) {
+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
+ /* We choose TCG_REG_TB such that no move is required. */
+ if (USE_REG_TB) {
+ QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
+ }
+
+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);
+ /* delay slot */
+ tcg_out_nop(s);
+
+ /* Epilogue for goto_ptr. */
+ s->code_gen_epilogue = s->code_ptr;
+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
+ /* delay slot */
+ tcg_out_movi_imm13(s, TCG_REG_O0, 0);
+
+#ifdef CONFIG_SOFTMMU
+ build_trampolines(s);
+#endif
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ int i;
+ for (i = 0; i < count; ++i) {
+ p[i] = NOP;
+ }
+}
+
+#if defined(CONFIG_SOFTMMU)
+
+/* We expect to use a 13-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));
+
+/* Perform the TLB load and compare.
+
+ Inputs:
+ ADDRLO and ADDRHI contain the possible two parts of the address.
+
+ MEM_INDEX and S_BITS are the memory context and log2 size of the load.
+
+ WHICH is the offset into the CPUTLBEntry structure of the slot to read.
+ This should be offsetof addr_read or addr_write.
+
+ The result of the TLB comparison is in %[ix]cc. The sanitized address
+ is in the returned register, maybe %o0. The TLB addend is in %o1. */
+
+static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
+ MemOp opc, int which)
+{
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ const TCGReg r0 = TCG_REG_O0;
+ const TCGReg r1 = TCG_REG_O1;
+ const TCGReg r2 = TCG_REG_O2;
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+ tcg_target_long compare_mask;
+
+ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
+ tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off);
+
+ /* Extract the page index, shifted into place for tlb index. */
+ tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
+ SHIFT_SRL);
+ tcg_out_arith(s, r2, r2, r0, ARITH_AND);
+
+ /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */
+ tcg_out_arith(s, r2, r2, r1, ARITH_ADD);
+
+ /* Load the tlb comparator and the addend. */
+ tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which);
+ tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend));
+
+ /* Mask out the page offset, except for the required alignment.
+ We don't support unaligned accesses. */
+ if (a_bits < s_bits) {
+ a_bits = s_bits;
+ }
+ compare_mask = (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
+ if (check_fit_tl(compare_mask, 13)) {
+ tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask);
+ tcg_out_arith(s, r2, addr, r2, ARITH_AND);
+ }
+ tcg_out_cmp(s, r0, r2, 0);
+
+ /* If the guest address must be zero-extended, do so now. */
+ if (SPARC64 && TARGET_LONG_BITS == 32) {
+ tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
+ return r0;
+ }
+ return addr;
+}
+#endif /* CONFIG_SOFTMMU */
+
+static const int qemu_ld_opc[16] = {
+ [MO_UB] = LDUB,
+ [MO_SB] = LDSB,
+
+ [MO_BEUW] = LDUH,
+ [MO_BESW] = LDSH,
+ [MO_BEUL] = LDUW,
+ [MO_BESL] = LDSW,
+ [MO_BEQ] = LDX,
+
+ [MO_LEUW] = LDUH_LE,
+ [MO_LESW] = LDSH_LE,
+ [MO_LEUL] = LDUW_LE,
+ [MO_LESL] = LDSW_LE,
+ [MO_LEQ] = LDX_LE,
+};
+
+static const int qemu_st_opc[16] = {
+ [MO_UB] = STB,
+
+ [MO_BEUW] = STH,
+ [MO_BEUL] = STW,
+ [MO_BEQ] = STX,
+
+ [MO_LEUW] = STH_LE,
+ [MO_LEUL] = STW_LE,
+ [MO_LEQ] = STX_LE,
+};
+
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
+ TCGMemOpIdx oi, bool is_64)
+{
+ MemOp memop = get_memop(oi);
+#ifdef CONFIG_SOFTMMU
+ unsigned memi = get_mmuidx(oi);
+ TCGReg addrz, param;
+ tcg_insn_unit *func;
+ tcg_insn_unit *label_ptr;
+
+ addrz = tcg_out_tlb_load(s, addr, memi, memop,
+ offsetof(CPUTLBEntry, addr_read));
+
+ /* The fast path is exactly one insn. Thus we can perform the
+ entire TLB Hit in the (annulled) delay slot of the branch
+ over the TLB Miss case. */
+
+ /* beq,a,pt %[xi]cc, label0 */
+ label_ptr = s->code_ptr;
+ tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
+ | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
+ /* delay slot */
+ tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
+ qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
+
+ /* TLB Miss. */
+
+ param = TCG_REG_O1;
+ if (!SPARC64 && TARGET_LONG_BITS == 64) {
+ /* Skip the high-part; we'll perform the extract in the trampoline. */
+ param++;
+ }
+ tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
+
+ /* We use the helpers to extend SB and SW data, leaving the case
+ of SL needing explicit extending below. */
+ if ((memop & MO_SSIZE) == MO_SL) {
+ func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)];
+ } else {
+ func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];
+ }
+ tcg_debug_assert(func != NULL);
+ tcg_out_call_nodelay(s, func, false);
+ /* delay slot */
+ tcg_out_movi(s, TCG_TYPE_I32, param, oi);
+
+ /* Recall that all of the helpers return 64-bit results.
+ Which complicates things for sparcv8plus. */
+ if (SPARC64) {
+ /* We let the helper sign-extend SB and SW, but leave SL for here. */
+ if (is_64 && (memop & MO_SSIZE) == MO_SL) {
+ tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
+ }
+ } else {
+ if ((memop & MO_SIZE) == MO_64) {
+ tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);
+ tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);
+ tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);
+ } else if (is_64) {
+ /* Re-extend from 32-bit rather than reassembling when we
+ know the high register must be an extension. */
+ tcg_out_arithi(s, data, TCG_REG_O1, 0,
+ memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1);
+ }
+ }
+
+ *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
+#else
+ if (SPARC64 && TARGET_LONG_BITS == 32) {
+ tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
+ addr = TCG_REG_T1;
+ }
+ tcg_out_ldst_rr(s, data, addr,
+ (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
+ qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
+#endif /* CONFIG_SOFTMMU */
+}
+
+static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
+ TCGMemOpIdx oi)
+{
+ MemOp memop = get_memop(oi);
+#ifdef CONFIG_SOFTMMU
+ unsigned memi = get_mmuidx(oi);
+ TCGReg addrz, param;
+ tcg_insn_unit *func;
+ tcg_insn_unit *label_ptr;
+
+ addrz = tcg_out_tlb_load(s, addr, memi, memop,
+ offsetof(CPUTLBEntry, addr_write));
+
+ /* The fast path is exactly one insn. Thus we can perform the entire
+ TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
+ /* beq,a,pt %[xi]cc, label0 */
+ label_ptr = s->code_ptr;
+ tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
+ | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
+ /* delay slot */
+ tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
+ qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
+
+ /* TLB Miss. */
+
+ param = TCG_REG_O1;
+ if (!SPARC64 && TARGET_LONG_BITS == 64) {
+ /* Skip the high-part; we'll perform the extract in the trampoline. */
+ param++;
+ }
+ tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
+ if (!SPARC64 && (memop & MO_SIZE) == MO_64) {
+ /* Skip the high-part; we'll perform the extract in the trampoline. */
+ param++;
+ }
+ tcg_out_mov(s, TCG_TYPE_REG, param++, data);
+
+ func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
+ tcg_debug_assert(func != NULL);
+ tcg_out_call_nodelay(s, func, false);
+ /* delay slot */
+ tcg_out_movi(s, TCG_TYPE_I32, param, oi);
+
+ *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
+#else
+ if (SPARC64 && TARGET_LONG_BITS == 32) {
+ tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
+ addr = TCG_REG_T1;
+ }
+ tcg_out_ldst_rr(s, data, addr,
+ (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
+ qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
+#endif /* CONFIG_SOFTMMU */
+}
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
+{
+ TCGArg a0, a1, a2;
+ int c, c2;
+
+ /* Hoist the loads of the most common arguments. */
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+ c2 = const_args[2];
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ if (check_fit_ptr(a0, 13)) {
+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
+ tcg_out_movi_imm13(s, TCG_REG_O0, a0);
+ break;
+ } else if (USE_REG_TB) {
+ intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr;
+ if (check_fit_ptr(tb_diff, 13)) {
+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
+ /* Note that TCG_REG_TB has been unwound to O1. */
+ tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD);
+ break;
+ }
+ }
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);
+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
+ tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);
+ break;
+ case INDEX_op_goto_tb:
+ if (s->tb_jmp_insn_offset) {
+ /* direct jump method */
+ if (USE_REG_TB) {
+ /* make sure the patch is 8-byte aligned. */
+ if ((intptr_t)s->code_ptr & 4) {
+ tcg_out_nop(s);
+ }
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ tcg_out_sethi(s, TCG_REG_T1, 0);
+ tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR);
+ tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL);
+ tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
+ } else {
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ tcg_out32(s, CALL);
+ tcg_out_nop(s);
+ }
+ } else {
+ /* indirect jump method */
+ tcg_out_ld_ptr(s, TCG_REG_TB,
+ (uintptr_t)(s->tb_jmp_target_addr + a0));
+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL);
+ tcg_out_nop(s);
+ }
+ set_jmp_reset_offset(s, a0);
+
+ /* For the unlinked path of goto_tb, we need to reset
+ TCG_REG_TB to the beginning of this TB. */
+ if (USE_REG_TB) {
+ c = -tcg_current_code_size(s);
+ if (check_fit_i32(c, 13)) {
+ tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c);
+ tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
+ TCG_REG_T1, ARITH_ADD);
+ }
+ }
+ break;
+ case INDEX_op_goto_ptr:
+ tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);
+ if (USE_REG_TB) {
+ tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR);
+ } else {
+ tcg_out_nop(s);
+ }
+ break;
+ case INDEX_op_br:
+ tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));
+ tcg_out_nop(s);
+ break;
+
+#define OP_32_64(x) \
+ glue(glue(case INDEX_op_, x), _i32): \
+ glue(glue(case INDEX_op_, x), _i64)
+
+ OP_32_64(ld8u):
+ tcg_out_ldst(s, a0, a1, a2, LDUB);
+ break;
+ OP_32_64(ld8s):
+ tcg_out_ldst(s, a0, a1, a2, LDSB);
+ break;
+ OP_32_64(ld16u):
+ tcg_out_ldst(s, a0, a1, a2, LDUH);
+ break;
+ OP_32_64(ld16s):
+ tcg_out_ldst(s, a0, a1, a2, LDSH);
+ break;
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32u_i64:
+ tcg_out_ldst(s, a0, a1, a2, LDUW);
+ break;
+ OP_32_64(st8):
+ tcg_out_ldst(s, a0, a1, a2, STB);
+ break;
+ OP_32_64(st16):
+ tcg_out_ldst(s, a0, a1, a2, STH);
+ break;
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ tcg_out_ldst(s, a0, a1, a2, STW);
+ break;
+ OP_32_64(add):
+ c = ARITH_ADD;
+ goto gen_arith;
+ OP_32_64(sub):
+ c = ARITH_SUB;
+ goto gen_arith;
+ OP_32_64(and):
+ c = ARITH_AND;
+ goto gen_arith;
+ OP_32_64(andc):
+ c = ARITH_ANDN;
+ goto gen_arith;
+ OP_32_64(or):
+ c = ARITH_OR;
+ goto gen_arith;
+ OP_32_64(orc):
+ c = ARITH_ORN;
+ goto gen_arith;
+ OP_32_64(xor):
+ c = ARITH_XOR;
+ goto gen_arith;
+ case INDEX_op_shl_i32:
+ c = SHIFT_SLL;
+ do_shift32:
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_arithc(s, a0, a1, a2 & 31, c2, c);
+ break;
+ case INDEX_op_shr_i32:
+ c = SHIFT_SRL;
+ goto do_shift32;
+ case INDEX_op_sar_i32:
+ c = SHIFT_SRA;
+ goto do_shift32;
+ case INDEX_op_mul_i32:
+ c = ARITH_UMUL;
+ goto gen_arith;
+
+ OP_32_64(neg):
+ c = ARITH_SUB;
+ goto gen_arith1;
+ OP_32_64(not):
+ c = ARITH_ORN;
+ goto gen_arith1;
+
+ case INDEX_op_div_i32:
+ tcg_out_div32(s, a0, a1, a2, c2, 0);
+ break;
+ case INDEX_op_divu_i32:
+ tcg_out_div32(s, a0, a1, a2, c2, 1);
+ break;
+
+ case INDEX_op_brcond_i32:
+ tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
+ break;
+ case INDEX_op_movcond_i32:
+ tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
+ break;
+
+ case INDEX_op_add2_i32:
+ tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
+ args[4], const_args[4], args[5], const_args[5],
+ ARITH_ADDCC, ARITH_ADDC);
+ break;
+ case INDEX_op_sub2_i32:
+ tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
+ args[4], const_args[4], args[5], const_args[5],
+ ARITH_SUBCC, ARITH_SUBC);
+ break;
+ case INDEX_op_mulu2_i32:
+ c = ARITH_UMUL;
+ goto do_mul2;
+ case INDEX_op_muls2_i32:
+ c = ARITH_SMUL;
+ do_mul2:
+ /* The 32-bit multiply insns produce a full 64-bit result. If the
+ destination register can hold it, we can avoid the slower RDY. */
+ tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
+ if (SPARC64 || a0 <= TCG_REG_O7) {
+ tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
+ } else {
+ tcg_out_rdy(s, a1);
+ }
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_qemu_ld(s, a0, a1, a2, false);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, a0, a1, a2, true);
+ break;
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_ld32s_i64:
+ tcg_out_ldst(s, a0, a1, a2, LDSW);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ldst(s, a0, a1, a2, LDX);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_ldst(s, a0, a1, a2, STX);
+ break;
+ case INDEX_op_shl_i64:
+ c = SHIFT_SLLX;
+ do_shift64:
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out_arithc(s, a0, a1, a2 & 63, c2, c);
+ break;
+ case INDEX_op_shr_i64:
+ c = SHIFT_SRLX;
+ goto do_shift64;
+ case INDEX_op_sar_i64:
+ c = SHIFT_SRAX;
+ goto do_shift64;
+ case INDEX_op_mul_i64:
+ c = ARITH_MULX;
+ goto gen_arith;
+ case INDEX_op_div_i64:
+ c = ARITH_SDIVX;
+ goto gen_arith;
+ case INDEX_op_divu_i64:
+ c = ARITH_UDIVX;
+ goto gen_arith;
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_ext32s_i64:
+ tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA);
+ break;
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_ext32u_i64:
+ tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
+ break;
+ case INDEX_op_extrl_i64_i32:
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ break;
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
+ break;
+
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
+ break;
+ case INDEX_op_movcond_i64:
+ tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
+ break;
+ case INDEX_op_add2_i64:
+ tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
+ const_args[4], args[5], const_args[5], false);
+ break;
+ case INDEX_op_sub2_i64:
+ tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
+ const_args[4], args[5], const_args[5], true);
+ break;
+ case INDEX_op_muluh_i64:
+ tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
+ break;
+
+ gen_arith:
+ tcg_out_arithc(s, a0, a1, a2, c2, c);
+ break;
+
+ gen_arith1:
+ tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
+ break;
+
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+}
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
+ static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
+ static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
+ static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
+ static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
+ static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
+ static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
+ static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
+ static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
+ static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
+ static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
+ static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
+ static const TCGTargetOpDef r_rZ_rJ
+ = { .args_ct_str = { "r", "rZ", "rJ" } };
+ static const TCGTargetOpDef R_RZ_RJ
+ = { .args_ct_str = { "R", "RZ", "RJ" } };
+ static const TCGTargetOpDef r_r_rZ_rJ
+ = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
+ static const TCGTargetOpDef movc_32
+ = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
+ static const TCGTargetOpDef movc_64
+ = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
+ static const TCGTargetOpDef add2_32
+ = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
+ static const TCGTargetOpDef add2_64
+ = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_not_i32:
+ return &r_r;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ return &rZ_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_mul_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_sub_i32:
+ case INDEX_op_and_i32:
+ case INDEX_op_andc_i32:
+ case INDEX_op_or_i32:
+ case INDEX_op_orc_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_setcond_i32:
+ return &r_rZ_rJ;
+
+ case INDEX_op_brcond_i32:
+ return &rZ_rJ;
+ case INDEX_op_movcond_i32:
+ return &movc_32;
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return &add2_32;
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_muls2_i32:
+ return &r_r_rZ_rJ;
+
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ return &R_r;
+
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &RZ_r;
+
+ case INDEX_op_add_i64:
+ case INDEX_op_mul_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_sub_i64:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i64:
+ case INDEX_op_or_i64:
+ case INDEX_op_orc_i64:
+ case INDEX_op_xor_i64:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_setcond_i64:
+ return &R_RZ_RJ;
+
+ case INDEX_op_neg_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ return &R_R;
+
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ return &r_R;
+
+ case INDEX_op_brcond_i64:
+ return &RZ_RJ;
+ case INDEX_op_movcond_i64:
+ return &movc_64;
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i64:
+ return &add2_64;
+ case INDEX_op_muluh_i64:
+ return &R_R_R;
+
+ case INDEX_op_qemu_ld_i32:
+ return &r_A;
+ case INDEX_op_qemu_ld_i64:
+ return &R_A;
+ case INDEX_op_qemu_st_i32:
+ return &sZ_A;
+ case INDEX_op_qemu_st_i64:
+ return &SZ_A;
+
+ default:
+ return NULL;
+ }
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ /* Only probe for the platform and capabilities if we havn't already
+ determined maximum values at compile time. */
+#ifndef use_vis3_instructions
+ {
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+ use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
+ }
+#endif
+
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
+
+ tcg_target_call_clobber_regs = 0;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
+}
+
+#if SPARC64
+# define ELF_HOST_MACHINE EM_SPARCV9
+#else
+# define ELF_HOST_MACHINE EM_SPARC32PLUS
+# define ELF_HOST_FLAGS EF_SPARC_32PLUS
+#endif
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
+ uint8_t fde_win_save;
+ uint8_t fde_ret_save[3];
+} DebugFrame;
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -sizeof(void *) & 0x7f,
+ .h.cie.return_column = 15, /* o7 */
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+#if SPARC64
+ 12, 30, /* DW_CFA_def_cfa i6, 2047 */
+ (2047 & 0x7f) | 0x80, (2047 >> 7)
+#else
+ 13, 30 /* DW_CFA_def_cfa_register i6 */
+#endif
+ },
+ .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */
+ .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
+
+void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
+ uintptr_t addr)
+{
+ intptr_t tb_disp = addr - tc_ptr;
+ intptr_t br_disp = addr - jmp_addr;
+ tcg_insn_unit i1, i2;
+
+ /* We can reach the entire address space for ILP32.
+ For LP64, the code_gen_buffer can't be larger than 2GB. */
+ tcg_debug_assert(tb_disp == (int32_t)tb_disp);
+ tcg_debug_assert(br_disp == (int32_t)br_disp);
+
+ if (!USE_REG_TB) {
+ atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2));
+ flush_icache_range(jmp_addr, jmp_addr + 4);
+ return;
+ }
+
+ /* This does not exercise the range of the branch, but we do
+ still need to be able to load the new value of TCG_REG_TB.
+ But this does still happen quite often. */
+ if (check_fit_ptr(tb_disp, 13)) {
+ /* ba,pt %icc, addr */
+ i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A)
+ | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp));
+ i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB)
+ | INSN_IMM13(tb_disp));
+ } else if (tb_disp >= 0) {
+ i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10);
+ i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)
+ | INSN_IMM13(tb_disp & 0x3ff));
+ } else {
+ i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10);
+ i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)
+ | INSN_IMM13((tb_disp & 0x3ff) | -0x400));
+ }
+
+ atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1));
+ flush_icache_range(jmp_addr, jmp_addr + 8);
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "../tcg-pool.inc.c"
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%g0",
- "%g1",
- "%g2",
- "%g3",
- "%g4",
- "%g5",
- "%g6",
- "%g7",
- "%o0",
- "%o1",
- "%o2",
- "%o3",
- "%o4",
- "%o5",
- "%o6",
- "%o7",
- "%l0",
- "%l1",
- "%l2",
- "%l3",
- "%l4",
- "%l5",
- "%l6",
- "%l7",
- "%i0",
- "%i1",
- "%i2",
- "%i3",
- "%i4",
- "%i5",
- "%i6",
- "%i7",
-};
-#endif
-
-#ifdef __arch64__
-# define SPARC64 1
-#else
-# define SPARC64 0
-#endif
-
-/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
- registers. These are saved manually by the kernel in full 64-bit
- slots. The %i and %l registers are saved by the register window
- mechanism, which only allocates space for 32 bits. Given that this
- window spill/fill can happen on any signal, we must consider the
- high bits of the %i and %l registers garbage at all times. */
-#if SPARC64
-# define ALL_64 0xffffffffu
-#else
-# define ALL_64 0xffffu
-#endif
-
-/* Define some temporary registers. T2 is used for constant generation. */
-#define TCG_REG_T1 TCG_REG_G1
-#define TCG_REG_T2 TCG_REG_O7
-
-#ifndef CONFIG_SOFTMMU
-# define TCG_GUEST_BASE_REG TCG_REG_I5
-#endif
-
-#define TCG_REG_TB TCG_REG_I1
-#define USE_REG_TB (sizeof(void *) > 4)
-
-static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_L0,
- TCG_REG_L1,
- TCG_REG_L2,
- TCG_REG_L3,
- TCG_REG_L4,
- TCG_REG_L5,
- TCG_REG_L6,
- TCG_REG_L7,
-
- TCG_REG_I0,
- TCG_REG_I1,
- TCG_REG_I2,
- TCG_REG_I3,
- TCG_REG_I4,
- TCG_REG_I5,
-
- TCG_REG_G2,
- TCG_REG_G3,
- TCG_REG_G4,
- TCG_REG_G5,
-
- TCG_REG_O0,
- TCG_REG_O1,
- TCG_REG_O2,
- TCG_REG_O3,
- TCG_REG_O4,
- TCG_REG_O5,
-};
-
-static const int tcg_target_call_iarg_regs[6] = {
- TCG_REG_O0,
- TCG_REG_O1,
- TCG_REG_O2,
- TCG_REG_O3,
- TCG_REG_O4,
- TCG_REG_O5,
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_O0,
- TCG_REG_O1,
- TCG_REG_O2,
- TCG_REG_O3,
-};
-
-#define INSN_OP(x) ((x) << 30)
-#define INSN_OP2(x) ((x) << 22)
-#define INSN_OP3(x) ((x) << 19)
-#define INSN_OPF(x) ((x) << 5)
-#define INSN_RD(x) ((x) << 25)
-#define INSN_RS1(x) ((x) << 14)
-#define INSN_RS2(x) (x)
-#define INSN_ASI(x) ((x) << 5)
-
-#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
-#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
-#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
-#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
-#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
-#define INSN_COND(x) ((x) << 25)
-
-#define COND_N 0x0
-#define COND_E 0x1
-#define COND_LE 0x2
-#define COND_L 0x3
-#define COND_LEU 0x4
-#define COND_CS 0x5
-#define COND_NEG 0x6
-#define COND_VS 0x7
-#define COND_A 0x8
-#define COND_NE 0x9
-#define COND_G 0xa
-#define COND_GE 0xb
-#define COND_GU 0xc
-#define COND_CC 0xd
-#define COND_POS 0xe
-#define COND_VC 0xf
-#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
-
-#define RCOND_Z 1
-#define RCOND_LEZ 2
-#define RCOND_LZ 3
-#define RCOND_NZ 5
-#define RCOND_GZ 6
-#define RCOND_GEZ 7
-
-#define MOVCC_ICC (1 << 18)
-#define MOVCC_XCC (1 << 18 | 1 << 12)
-
-#define BPCC_ICC 0
-#define BPCC_XCC (2 << 20)
-#define BPCC_PT (1 << 19)
-#define BPCC_PN 0
-#define BPCC_A (1 << 29)
-
-#define BPR_PT BPCC_PT
-
-#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
-#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
-#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
-#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
-#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
-#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
-#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
-#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
-#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
-#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
-#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08))
-#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c))
-#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
-#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
-#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
-#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
-#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
-#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
-#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
-#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
-#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
-
-#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
-#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
-
-#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
-#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
-#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
-
-#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
-#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
-#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
-
-#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
-#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
-#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
-#define RETURN (INSN_OP(2) | INSN_OP3(0x39))
-#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
-#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
-#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
-#define CALL INSN_OP(1)
-#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
-#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
-#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
-#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
-#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
-#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
-#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
-#define STB (INSN_OP(3) | INSN_OP3(0x05))
-#define STH (INSN_OP(3) | INSN_OP3(0x06))
-#define STW (INSN_OP(3) | INSN_OP3(0x04))
-#define STX (INSN_OP(3) | INSN_OP3(0x0e))
-#define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
-#define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
-#define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
-#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
-#define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
-#define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
-#define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
-#define STBA (INSN_OP(3) | INSN_OP3(0x15))
-#define STHA (INSN_OP(3) | INSN_OP3(0x16))
-#define STWA (INSN_OP(3) | INSN_OP3(0x14))
-#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
-
-#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
-
-#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0)
-
-#ifndef ASI_PRIMARY_LITTLE
-#define ASI_PRIMARY_LITTLE 0x88
-#endif
-
-#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
-
-#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
-
-#ifndef use_vis3_instructions
-bool use_vis3_instructions;
-#endif
-
-static inline int check_fit_i64(int64_t val, unsigned int bits)
-{
- return val == sextract64(val, 0, bits);
-}
-
-static inline int check_fit_i32(int32_t val, unsigned int bits)
-{
- return val == sextract32(val, 0, bits);
-}
-
-#define check_fit_tl check_fit_i64
-#if SPARC64
-# define check_fit_ptr check_fit_i64
-#else
-# define check_fit_ptr check_fit_i32
-#endif
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- uint32_t insn = *code_ptr;
- intptr_t pcrel;
-
- value += addend;
- pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr);
-
- switch (type) {
- case R_SPARC_WDISP16:
- assert(check_fit_ptr(pcrel >> 2, 16));
- insn &= ~INSN_OFF16(-1);
- insn |= INSN_OFF16(pcrel);
- break;
- case R_SPARC_WDISP19:
- assert(check_fit_ptr(pcrel >> 2, 19));
- insn &= ~INSN_OFF19(-1);
- insn |= INSN_OFF19(pcrel);
- break;
- default:
- g_assert_not_reached();
- }
-
- *code_ptr = insn;
- return true;
-}
-
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- break;
- case 'R':
- ct->ct |= TCG_CT_REG;
- ct->u.regs = ALL_64;
- break;
- case 'A': /* qemu_ld/st address constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
- reserve_helpers:
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
- break;
- case 's': /* qemu_st data 32-bit constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- goto reserve_helpers;
- case 'S': /* qemu_st data 64-bit constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = ALL_64;
- goto reserve_helpers;
- case 'I':
- ct->ct |= TCG_CT_CONST_S11;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S13;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- int ct = arg_ct->ct;
-
- if (ct & TCG_CT_CONST) {
- return 1;
- }
-
- if (type == TCG_TYPE_I32) {
- val = (int32_t)val;
- }
-
- if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
- return 1;
- } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
- return 1;
- } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
- return 1;
- } else {
- return 0;
- }
-}
-
-static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1,
- TCGReg rs2, int op)
-{
- tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2));
-}
-
-static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
- int32_t offset, int op)
-{
- tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset));
-}
-
-static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
- int32_t val2, int val2const, int op)
-{
- tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
- | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
-}
-
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
-{
- if (ret != arg) {
- tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
- }
- return true;
-}
-
-static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
-{
- tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
-}
-
-static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)
-{
- tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
-}
-
-static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long arg, bool in_prologue)
-{
- tcg_target_long hi, lo = (int32_t)arg;
- tcg_target_long test, lsb;
-
- /* Make sure we test 32-bit constants for imm13 properly. */
- if (type == TCG_TYPE_I32) {
- arg = lo;
- }
-
- /* A 13-bit constant sign-extended to 64-bits. */
- if (check_fit_tl(arg, 13)) {
- tcg_out_movi_imm13(s, ret, arg);
- return;
- }
-
- /* A 13-bit constant relative to the TB. */
- if (!in_prologue && USE_REG_TB) {
- test = arg - (uintptr_t)s->code_gen_ptr;
- if (check_fit_ptr(test, 13)) {
- tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD);
- return;
- }
- }
-
- /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
- if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
- tcg_out_sethi(s, ret, arg);
- if (arg & 0x3ff) {
- tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
- }
- return;
- }
-
- /* A 32-bit constant sign-extended to 64-bits. */
- if (arg == lo) {
- tcg_out_sethi(s, ret, ~arg);
- tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
- return;
- }
-
- /* A 21-bit constant, shifted. */
- lsb = ctz64(arg);
- test = (tcg_target_long)arg >> lsb;
- if (check_fit_tl(test, 13)) {
- tcg_out_movi_imm13(s, ret, test);
- tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
- return;
- } else if (lsb > 10 && test == extract64(test, 0, 21)) {
- tcg_out_sethi(s, ret, test << 10);
- tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);
- return;
- }
-
- /* A 64-bit constant decomposed into 2 32-bit pieces. */
- if (check_fit_i32(lo, 13)) {
- hi = (arg - lo) >> 32;
- tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
- tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
- tcg_out_arithi(s, ret, ret, lo, ARITH_ADD);
- } else {
- hi = arg >> 32;
- tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo);
- tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
- tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR);
- }
-}
-
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
-{
- tcg_out_movi_int(s, type, ret, arg, false);
-}
-
-static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
- TCGReg a2, int op)
-{
- tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
-}
-
-static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
- intptr_t offset, int op)
-{
- if (check_fit_ptr(offset, 13)) {
- tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
- INSN_IMM13(offset));
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
- tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
- }
-}
-
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg arg1, intptr_t arg2)
-{
- tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
-}
-
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
-{
- tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- if (val == 0) {
- tcg_out_st(s, type, TCG_REG_G0, base, ofs);
- return true;
- }
- return false;
-}
-
-static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg)
-{
- intptr_t diff = arg - (uintptr_t)s->code_gen_ptr;
- if (USE_REG_TB && check_fit_ptr(diff, 13)) {
- tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
- return;
- }
- tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);
- tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);
-}
-
-static inline void tcg_out_sety(TCGContext *s, TCGReg rs)
-{
- tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
-}
-
-static inline void tcg_out_rdy(TCGContext *s, TCGReg rd)
-{
- tcg_out32(s, RDY | INSN_RD(rd));
-}
-
-static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
- int32_t val2, int val2const, int uns)
-{
- /* Load Y with the sign/zero extension of RS1 to 64-bits. */
- if (uns) {
- tcg_out_sety(s, TCG_REG_G0);
- } else {
- tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
- tcg_out_sety(s, TCG_REG_T1);
- }
-
- tcg_out_arithc(s, rd, rs1, val2, val2const,
- uns ? ARITH_UDIV : ARITH_SDIV);
-}
-
-static inline void tcg_out_nop(TCGContext *s)
-{
- tcg_out32(s, NOP);
-}
-
-static const uint8_t tcg_cond_to_bcond[] = {
- [TCG_COND_EQ] = COND_E,
- [TCG_COND_NE] = COND_NE,
- [TCG_COND_LT] = COND_L,
- [TCG_COND_GE] = COND_GE,
- [TCG_COND_LE] = COND_LE,
- [TCG_COND_GT] = COND_G,
- [TCG_COND_LTU] = COND_CS,
- [TCG_COND_GEU] = COND_CC,
- [TCG_COND_LEU] = COND_LEU,
- [TCG_COND_GTU] = COND_GU,
-};
-
-static const uint8_t tcg_cond_to_rcond[] = {
- [TCG_COND_EQ] = RCOND_Z,
- [TCG_COND_NE] = RCOND_NZ,
- [TCG_COND_LT] = RCOND_LZ,
- [TCG_COND_GT] = RCOND_GZ,
- [TCG_COND_LE] = RCOND_LEZ,
- [TCG_COND_GE] = RCOND_GEZ
-};
-
-static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
-{
- tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
-}
-
-static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
-{
- int off19 = 0;
-
- if (l->has_value) {
- off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr));
- } else {
- tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0);
- }
- tcg_out_bpcc0(s, scond, flags, off19);
-}
-
-static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const)
-{
- tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
-}
-
-static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
- int32_t arg2, int const_arg2, TCGLabel *l)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2);
- tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l);
- tcg_out_nop(s);
-}
-
-static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret,
- int32_t v1, int v1const)
-{
- tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
- | INSN_RS1(tcg_cond_to_bcond[cond])
- | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
-}
-
-static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, int32_t c2, int c2const,
- int32_t v1, int v1const)
-{
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
-}
-
-static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1,
- int32_t arg2, int const_arg2, TCGLabel *l)
-{
- /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
- if (arg2 == 0 && !is_unsigned_cond(cond)) {
- int off16 = 0;
-
- if (l->has_value) {
- off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr));
- } else {
- tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0);
- }
- tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
- | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
- } else {
- tcg_out_cmp(s, arg1, arg2, const_arg2);
- tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l);
- }
- tcg_out_nop(s);
-}
-
-static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1,
- int32_t v1, int v1const)
-{
- tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
- | (tcg_cond_to_rcond[cond] << 10)
- | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
-}
-
-static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, int32_t c2, int c2const,
- int32_t v1, int v1const)
-{
- /* For 64-bit signed comparisons vs zero, we can avoid the compare.
- Note that the immediate range is one bit smaller, so we must check
- for that as well. */
- if (c2 == 0 && !is_unsigned_cond(cond)
- && (!v1const || check_fit_i32(v1, 10))) {
- tcg_out_movr(s, cond, ret, c1, v1, v1const);
- } else {
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
- }
-}
-
-static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, int32_t c2, int c2const)
-{
- /* For 32-bit comparisons, we can play games with ADDC/SUBC. */
- switch (cond) {
- case TCG_COND_LTU:
- case TCG_COND_GEU:
- /* The result of the comparison is in the carry bit. */
- break;
-
- case TCG_COND_EQ:
- case TCG_COND_NE:
- /* For equality, we can transform to inequality vs zero. */
- if (c2 != 0) {
- tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR);
- c2 = TCG_REG_T1;
- } else {
- c2 = c1;
- }
- c1 = TCG_REG_G0, c2const = 0;
- cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
- break;
-
- case TCG_COND_GTU:
- case TCG_COND_LEU:
- /* If we don't need to load a constant into a register, we can
- swap the operands on GTU/LEU. There's no benefit to loading
- the constant into a temporary register. */
- if (!c2const || c2 == 0) {
- TCGReg t = c1;
- c1 = c2;
- c2 = t;
- c2const = 0;
- cond = tcg_swap_cond(cond);
- break;
- }
- /* FALLTHRU */
-
- default:
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_movi_imm13(s, ret, 0);
- tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
- return;
- }
-
- tcg_out_cmp(s, c1, c2, c2const);
- if (cond == TCG_COND_LTU) {
- tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
- } else {
- tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
- }
-}
-
-static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg c1, int32_t c2, int c2const)
-{
- if (use_vis3_instructions) {
- switch (cond) {
- case TCG_COND_NE:
- if (c2 != 0) {
- break;
- }
- c2 = c1, c2const = 0, c1 = TCG_REG_G0;
- /* FALLTHRU */
- case TCG_COND_LTU:
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC);
- return;
- default:
- break;
- }
- }
-
- /* For 64-bit signed comparisons vs zero, we can avoid the compare
- if the input does not overlap the output. */
- if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
- tcg_out_movi_imm13(s, ret, 0);
- tcg_out_movr(s, cond, ret, c1, 1, 1);
- } else {
- tcg_out_cmp(s, c1, c2, c2const);
- tcg_out_movi_imm13(s, ret, 0);
- tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
- }
-}
-
-static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh,
- TCGReg al, TCGReg ah, int32_t bl, int blconst,
- int32_t bh, int bhconst, int opl, int oph)
-{
- TCGReg tmp = TCG_REG_T1;
-
- /* Note that the low parts are fully consumed before tmp is set. */
- if (rl != ah && (bhconst || rl != bh)) {
- tmp = rl;
- }
-
- tcg_out_arithc(s, tmp, al, bl, blconst, opl);
- tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
- tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
-}
-
-static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
- TCGReg al, TCGReg ah, int32_t bl, int blconst,
- int32_t bh, int bhconst, bool is_sub)
-{
- TCGReg tmp = TCG_REG_T1;
-
- /* Note that the low parts are fully consumed before tmp is set. */
- if (rl != ah && (bhconst || rl != bh)) {
- tmp = rl;
- }
-
- tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC);
-
- if (use_vis3_instructions && !is_sub) {
- /* Note that ADDXC doesn't accept immediates. */
- if (bhconst && bh != 0) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh);
- bh = TCG_REG_T2;
- }
- tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
- } else if (bh == TCG_REG_G0) {
- /* If we have a zero, we can perform the operation in two insns,
- with the arithmetic first, and a conditional move into place. */
- if (rh == ah) {
- tcg_out_arithi(s, TCG_REG_T2, ah, 1,
- is_sub ? ARITH_SUB : ARITH_ADD);
- tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
- } else {
- tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
- tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
- }
- } else {
- /* Otherwise adjust BH as if there is carry into T2 ... */
- if (bhconst) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1));
- } else {
- tcg_out_arithi(s, TCG_REG_T2, bh, 1,
- is_sub ? ARITH_SUB : ARITH_ADD);
- }
- /* ... smoosh T2 back to original BH if carry is clear ... */
- tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
- /* ... and finally perform the arithmetic with the new operand. */
- tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
- }
-
- tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
-}
-
-static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest,
- bool in_prologue)
-{
- ptrdiff_t disp = tcg_pcrel_diff(s, dest);
-
- if (disp == (int32_t)disp) {
- tcg_out32(s, CALL | (uint32_t)disp >> 2);
- } else {
- uintptr_t desti = (uintptr_t)dest;
- tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1,
- desti & ~0xfff, in_prologue);
- tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL);
- }
-}
-
-static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
-{
- tcg_out_call_nodelay(s, dest, false);
- tcg_out_nop(s);
-}
-
-static void tcg_out_mb(TCGContext *s, TCGArg a0)
-{
- /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
- tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
-}
-
-#ifdef CONFIG_SOFTMMU
-static tcg_insn_unit *qemu_ld_trampoline[16];
-static tcg_insn_unit *qemu_st_trampoline[16];
-
-static void emit_extend(TCGContext *s, TCGReg r, int op)
-{
- /* Emit zero extend of 8, 16 or 32 bit data as
- * required by the MO_* value op; do nothing for 64 bit.
- */
- switch (op & MO_SIZE) {
- case MO_8:
- tcg_out_arithi(s, r, r, 0xff, ARITH_AND);
- break;
- case MO_16:
- tcg_out_arithi(s, r, r, 16, SHIFT_SLL);
- tcg_out_arithi(s, r, r, 16, SHIFT_SRL);
- break;
- case MO_32:
- if (SPARC64) {
- tcg_out_arith(s, r, r, 0, SHIFT_SRL);
- }
- break;
- case MO_64:
- break;
- }
-}
-
-static void build_trampolines(TCGContext *s)
-{
- static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
- };
- static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
- };
-
- int i;
- TCGReg ra;
-
- for (i = 0; i < 16; ++i) {
- if (qemu_ld_helpers[i] == NULL) {
- continue;
- }
-
- /* May as well align the trampoline. */
- while ((uintptr_t)s->code_ptr & 15) {
- tcg_out_nop(s);
- }
- qemu_ld_trampoline[i] = s->code_ptr;
-
- if (SPARC64 || TARGET_LONG_BITS == 32) {
- ra = TCG_REG_O3;
- } else {
- /* Install the high part of the address. */
- tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
- ra = TCG_REG_O4;
- }
-
- /* Set the retaddr operand. */
- tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
- /* Set the env operand. */
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
- /* Tail call. */
- tcg_out_call_nodelay(s, qemu_ld_helpers[i], true);
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
- }
-
- for (i = 0; i < 16; ++i) {
- if (qemu_st_helpers[i] == NULL) {
- continue;
- }
-
- /* May as well align the trampoline. */
- while ((uintptr_t)s->code_ptr & 15) {
- tcg_out_nop(s);
- }
- qemu_st_trampoline[i] = s->code_ptr;
-
- if (SPARC64) {
- emit_extend(s, TCG_REG_O2, i);
- ra = TCG_REG_O4;
- } else {
- ra = TCG_REG_O1;
- if (TARGET_LONG_BITS == 64) {
- /* Install the high part of the address. */
- tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
- ra += 2;
- } else {
- ra += 1;
- }
- if ((i & MO_SIZE) == MO_64) {
- /* Install the high part of the data. */
- tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
- ra += 2;
- } else {
- emit_extend(s, ra, i);
- ra += 1;
- }
- /* Skip the oi argument. */
- ra += 1;
- }
-
- /* Set the retaddr operand. */
- if (ra >= TCG_REG_O6) {
- tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK,
- TCG_TARGET_CALL_STACK_OFFSET);
- ra = TCG_REG_G1;
- }
- tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
- /* Set the env operand. */
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
- /* Tail call. */
- tcg_out_call_nodelay(s, qemu_st_helpers[i], true);
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
- }
-}
-#endif
-
-/* Generate global QEMU prologue and epilogue code */
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- int tmp_buf_size, frame_size;
-
- /* The TCG temp buffer is at the top of the frame, immediately
- below the frame pointer. */
- tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long);
- tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size,
- tmp_buf_size);
-
- /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is
- otherwise the minimal frame usable by callees. */
- frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS;
- frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size;
- frame_size += TCG_TARGET_STACK_ALIGN - 1;
- frame_size &= -TCG_TARGET_STACK_ALIGN;
- tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
- INSN_IMM13(-frame_size));
-
-#ifndef CONFIG_SOFTMMU
- if (guest_base != 0) {
- tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
- tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
- }
-#endif
-
- /* We choose TCG_REG_TB such that no move is required. */
- if (USE_REG_TB) {
- QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
- }
-
- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);
- /* delay slot */
- tcg_out_nop(s);
-
- /* Epilogue for goto_ptr. */
- s->code_gen_epilogue = s->code_ptr;
- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
- /* delay slot */
- tcg_out_movi_imm13(s, TCG_REG_O0, 0);
-
-#ifdef CONFIG_SOFTMMU
- build_trampolines(s);
-#endif
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- int i;
- for (i = 0; i < count; ++i) {
- p[i] = NOP;
- }
-}
-
-#if defined(CONFIG_SOFTMMU)
-
-/* We expect to use a 13-bit negative offset from ENV. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));
-
-/* Perform the TLB load and compare.
-
- Inputs:
- ADDRLO and ADDRHI contain the possible two parts of the address.
-
- MEM_INDEX and S_BITS are the memory context and log2 size of the load.
-
- WHICH is the offset into the CPUTLBEntry structure of the slot to read.
- This should be offsetof addr_read or addr_write.
-
- The result of the TLB comparison is in %[ix]cc. The sanitized address
- is in the returned register, maybe %o0. The TLB addend is in %o1. */
-
-static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
- MemOp opc, int which)
-{
- int fast_off = TLB_MASK_TABLE_OFS(mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- const TCGReg r0 = TCG_REG_O0;
- const TCGReg r1 = TCG_REG_O1;
- const TCGReg r2 = TCG_REG_O2;
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
- tcg_target_long compare_mask;
-
- /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off);
-
- /* Extract the page index, shifted into place for tlb index. */
- tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
- SHIFT_SRL);
- tcg_out_arith(s, r2, r2, r0, ARITH_AND);
-
- /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */
- tcg_out_arith(s, r2, r2, r1, ARITH_ADD);
-
- /* Load the tlb comparator and the addend. */
- tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which);
- tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend));
-
- /* Mask out the page offset, except for the required alignment.
- We don't support unaligned accesses. */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
- compare_mask = (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
- if (check_fit_tl(compare_mask, 13)) {
- tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND);
- } else {
- tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask);
- tcg_out_arith(s, r2, addr, r2, ARITH_AND);
- }
- tcg_out_cmp(s, r0, r2, 0);
-
- /* If the guest address must be zero-extended, do so now. */
- if (SPARC64 && TARGET_LONG_BITS == 32) {
- tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
- return r0;
- }
- return addr;
-}
-#endif /* CONFIG_SOFTMMU */
-
-static const int qemu_ld_opc[16] = {
- [MO_UB] = LDUB,
- [MO_SB] = LDSB,
-
- [MO_BEUW] = LDUH,
- [MO_BESW] = LDSH,
- [MO_BEUL] = LDUW,
- [MO_BESL] = LDSW,
- [MO_BEQ] = LDX,
-
- [MO_LEUW] = LDUH_LE,
- [MO_LESW] = LDSH_LE,
- [MO_LEUL] = LDUW_LE,
- [MO_LESL] = LDSW_LE,
- [MO_LEQ] = LDX_LE,
-};
-
-static const int qemu_st_opc[16] = {
- [MO_UB] = STB,
-
- [MO_BEUW] = STH,
- [MO_BEUL] = STW,
- [MO_BEQ] = STX,
-
- [MO_LEUW] = STH_LE,
- [MO_LEUL] = STW_LE,
- [MO_LEQ] = STX_LE,
-};
-
-static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOpIdx oi, bool is_64)
-{
- MemOp memop = get_memop(oi);
-#ifdef CONFIG_SOFTMMU
- unsigned memi = get_mmuidx(oi);
- TCGReg addrz, param;
- tcg_insn_unit *func;
- tcg_insn_unit *label_ptr;
-
- addrz = tcg_out_tlb_load(s, addr, memi, memop,
- offsetof(CPUTLBEntry, addr_read));
-
- /* The fast path is exactly one insn. Thus we can perform the
- entire TLB Hit in the (annulled) delay slot of the branch
- over the TLB Miss case. */
-
- /* beq,a,pt %[xi]cc, label0 */
- label_ptr = s->code_ptr;
- tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
- | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
- /* delay slot */
- tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
- qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
-
- /* TLB Miss. */
-
- param = TCG_REG_O1;
- if (!SPARC64 && TARGET_LONG_BITS == 64) {
- /* Skip the high-part; we'll perform the extract in the trampoline. */
- param++;
- }
- tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
-
- /* We use the helpers to extend SB and SW data, leaving the case
- of SL needing explicit extending below. */
- if ((memop & MO_SSIZE) == MO_SL) {
- func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)];
- } else {
- func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];
- }
- tcg_debug_assert(func != NULL);
- tcg_out_call_nodelay(s, func, false);
- /* delay slot */
- tcg_out_movi(s, TCG_TYPE_I32, param, oi);
-
- /* Recall that all of the helpers return 64-bit results.
- Which complicates things for sparcv8plus. */
- if (SPARC64) {
- /* We let the helper sign-extend SB and SW, but leave SL for here. */
- if (is_64 && (memop & MO_SSIZE) == MO_SL) {
- tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
- } else {
- tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
- }
- } else {
- if ((memop & MO_SIZE) == MO_64) {
- tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);
- tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);
- tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);
- } else if (is_64) {
- /* Re-extend from 32-bit rather than reassembling when we
- know the high register must be an extension. */
- tcg_out_arithi(s, data, TCG_REG_O1, 0,
- memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL);
- } else {
- tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1);
- }
- }
-
- *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
-#else
- if (SPARC64 && TARGET_LONG_BITS == 32) {
- tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
- addr = TCG_REG_T1;
- }
- tcg_out_ldst_rr(s, data, addr,
- (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
- qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
-#endif /* CONFIG_SOFTMMU */
-}
-
-static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOpIdx oi)
-{
- MemOp memop = get_memop(oi);
-#ifdef CONFIG_SOFTMMU
- unsigned memi = get_mmuidx(oi);
- TCGReg addrz, param;
- tcg_insn_unit *func;
- tcg_insn_unit *label_ptr;
-
- addrz = tcg_out_tlb_load(s, addr, memi, memop,
- offsetof(CPUTLBEntry, addr_write));
-
- /* The fast path is exactly one insn. Thus we can perform the entire
- TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
- /* beq,a,pt %[xi]cc, label0 */
- label_ptr = s->code_ptr;
- tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
- | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
- /* delay slot */
- tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
- qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
-
- /* TLB Miss. */
-
- param = TCG_REG_O1;
- if (!SPARC64 && TARGET_LONG_BITS == 64) {
- /* Skip the high-part; we'll perform the extract in the trampoline. */
- param++;
- }
- tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
- if (!SPARC64 && (memop & MO_SIZE) == MO_64) {
- /* Skip the high-part; we'll perform the extract in the trampoline. */
- param++;
- }
- tcg_out_mov(s, TCG_TYPE_REG, param++, data);
-
- func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
- tcg_debug_assert(func != NULL);
- tcg_out_call_nodelay(s, func, false);
- /* delay slot */
- tcg_out_movi(s, TCG_TYPE_I32, param, oi);
-
- *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
-#else
- if (SPARC64 && TARGET_LONG_BITS == 32) {
- tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
- addr = TCG_REG_T1;
- }
- tcg_out_ldst_rr(s, data, addr,
- (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
- qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
-#endif /* CONFIG_SOFTMMU */
-}
-
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg args[TCG_MAX_OP_ARGS],
- const int const_args[TCG_MAX_OP_ARGS])
-{
- TCGArg a0, a1, a2;
- int c, c2;
-
- /* Hoist the loads of the most common arguments. */
- a0 = args[0];
- a1 = args[1];
- a2 = args[2];
- c2 = const_args[2];
-
- switch (opc) {
- case INDEX_op_exit_tb:
- if (check_fit_ptr(a0, 13)) {
- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
- tcg_out_movi_imm13(s, TCG_REG_O0, a0);
- break;
- } else if (USE_REG_TB) {
- intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr;
- if (check_fit_ptr(tb_diff, 13)) {
- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
- /* Note that TCG_REG_TB has been unwound to O1. */
- tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD);
- break;
- }
- }
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);
- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
- tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);
- break;
- case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* direct jump method */
- if (USE_REG_TB) {
- /* make sure the patch is 8-byte aligned. */
- if ((intptr_t)s->code_ptr & 4) {
- tcg_out_nop(s);
- }
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- tcg_out_sethi(s, TCG_REG_T1, 0);
- tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR);
- tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL);
- tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
- } else {
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- tcg_out32(s, CALL);
- tcg_out_nop(s);
- }
- } else {
- /* indirect jump method */
- tcg_out_ld_ptr(s, TCG_REG_TB,
- (uintptr_t)(s->tb_jmp_target_addr + a0));
- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL);
- tcg_out_nop(s);
- }
- set_jmp_reset_offset(s, a0);
-
- /* For the unlinked path of goto_tb, we need to reset
- TCG_REG_TB to the beginning of this TB. */
- if (USE_REG_TB) {
- c = -tcg_current_code_size(s);
- if (check_fit_i32(c, 13)) {
- tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c);
- tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
- TCG_REG_T1, ARITH_ADD);
- }
- }
- break;
- case INDEX_op_goto_ptr:
- tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);
- if (USE_REG_TB) {
- tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR);
- } else {
- tcg_out_nop(s);
- }
- break;
- case INDEX_op_br:
- tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));
- tcg_out_nop(s);
- break;
-
-#define OP_32_64(x) \
- glue(glue(case INDEX_op_, x), _i32): \
- glue(glue(case INDEX_op_, x), _i64)
-
- OP_32_64(ld8u):
- tcg_out_ldst(s, a0, a1, a2, LDUB);
- break;
- OP_32_64(ld8s):
- tcg_out_ldst(s, a0, a1, a2, LDSB);
- break;
- OP_32_64(ld16u):
- tcg_out_ldst(s, a0, a1, a2, LDUH);
- break;
- OP_32_64(ld16s):
- tcg_out_ldst(s, a0, a1, a2, LDSH);
- break;
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- tcg_out_ldst(s, a0, a1, a2, LDUW);
- break;
- OP_32_64(st8):
- tcg_out_ldst(s, a0, a1, a2, STB);
- break;
- OP_32_64(st16):
- tcg_out_ldst(s, a0, a1, a2, STH);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, a0, a1, a2, STW);
- break;
- OP_32_64(add):
- c = ARITH_ADD;
- goto gen_arith;
- OP_32_64(sub):
- c = ARITH_SUB;
- goto gen_arith;
- OP_32_64(and):
- c = ARITH_AND;
- goto gen_arith;
- OP_32_64(andc):
- c = ARITH_ANDN;
- goto gen_arith;
- OP_32_64(or):
- c = ARITH_OR;
- goto gen_arith;
- OP_32_64(orc):
- c = ARITH_ORN;
- goto gen_arith;
- OP_32_64(xor):
- c = ARITH_XOR;
- goto gen_arith;
- case INDEX_op_shl_i32:
- c = SHIFT_SLL;
- do_shift32:
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out_arithc(s, a0, a1, a2 & 31, c2, c);
- break;
- case INDEX_op_shr_i32:
- c = SHIFT_SRL;
- goto do_shift32;
- case INDEX_op_sar_i32:
- c = SHIFT_SRA;
- goto do_shift32;
- case INDEX_op_mul_i32:
- c = ARITH_UMUL;
- goto gen_arith;
-
- OP_32_64(neg):
- c = ARITH_SUB;
- goto gen_arith1;
- OP_32_64(not):
- c = ARITH_ORN;
- goto gen_arith1;
-
- case INDEX_op_div_i32:
- tcg_out_div32(s, a0, a1, a2, c2, 0);
- break;
- case INDEX_op_divu_i32:
- tcg_out_div32(s, a0, a1, a2, c2, 1);
- break;
-
- case INDEX_op_brcond_i32:
- tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
- break;
- case INDEX_op_setcond_i32:
- tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
- break;
- case INDEX_op_movcond_i32:
- tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
- break;
-
- case INDEX_op_add2_i32:
- tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
- args[4], const_args[4], args[5], const_args[5],
- ARITH_ADDCC, ARITH_ADDC);
- break;
- case INDEX_op_sub2_i32:
- tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
- args[4], const_args[4], args[5], const_args[5],
- ARITH_SUBCC, ARITH_SUBC);
- break;
- case INDEX_op_mulu2_i32:
- c = ARITH_UMUL;
- goto do_mul2;
- case INDEX_op_muls2_i32:
- c = ARITH_SMUL;
- do_mul2:
- /* The 32-bit multiply insns produce a full 64-bit result. If the
- destination register can hold it, we can avoid the slower RDY. */
- tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
- if (SPARC64 || a0 <= TCG_REG_O7) {
- tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
- } else {
- tcg_out_rdy(s, a1);
- }
- break;
-
- case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, a0, a1, a2, false);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, a0, a1, a2, true);
- break;
- case INDEX_op_qemu_st_i32:
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, a0, a1, a2);
- break;
-
- case INDEX_op_ld32s_i64:
- tcg_out_ldst(s, a0, a1, a2, LDSW);
- break;
- case INDEX_op_ld_i64:
- tcg_out_ldst(s, a0, a1, a2, LDX);
- break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, a0, a1, a2, STX);
- break;
- case INDEX_op_shl_i64:
- c = SHIFT_SLLX;
- do_shift64:
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out_arithc(s, a0, a1, a2 & 63, c2, c);
- break;
- case INDEX_op_shr_i64:
- c = SHIFT_SRLX;
- goto do_shift64;
- case INDEX_op_sar_i64:
- c = SHIFT_SRAX;
- goto do_shift64;
- case INDEX_op_mul_i64:
- c = ARITH_MULX;
- goto gen_arith;
- case INDEX_op_div_i64:
- c = ARITH_SDIVX;
- goto gen_arith;
- case INDEX_op_divu_i64:
- c = ARITH_UDIVX;
- goto gen_arith;
- case INDEX_op_ext_i32_i64:
- case INDEX_op_ext32s_i64:
- tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA);
- break;
- case INDEX_op_extu_i32_i64:
- case INDEX_op_ext32u_i64:
- tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
- break;
- case INDEX_op_extrl_i64_i32:
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- break;
- case INDEX_op_extrh_i64_i32:
- tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
- break;
-
- case INDEX_op_brcond_i64:
- tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
- break;
- case INDEX_op_setcond_i64:
- tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
- break;
- case INDEX_op_movcond_i64:
- tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
- break;
- case INDEX_op_add2_i64:
- tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
- const_args[4], args[5], const_args[5], false);
- break;
- case INDEX_op_sub2_i64:
- tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
- const_args[4], args[5], const_args[5], true);
- break;
- case INDEX_op_muluh_i64:
- tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
- break;
-
- gen_arith:
- tcg_out_arithc(s, a0, a1, a2, c2, c);
- break;
-
- gen_arith1:
- tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
- break;
-
- case INDEX_op_mb:
- tcg_out_mb(s, a0);
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-}
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
- static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
- static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
- static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
- static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
- static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
- static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
- static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
- static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
- static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
- static const TCGTargetOpDef r_rZ_rJ
- = { .args_ct_str = { "r", "rZ", "rJ" } };
- static const TCGTargetOpDef R_RZ_RJ
- = { .args_ct_str = { "R", "RZ", "RJ" } };
- static const TCGTargetOpDef r_r_rZ_rJ
- = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
- static const TCGTargetOpDef movc_32
- = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
- static const TCGTargetOpDef movc_64
- = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
- static const TCGTargetOpDef add2_32
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
- static const TCGTargetOpDef add2_64
- = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
-
- switch (op) {
- case INDEX_op_goto_ptr:
- return &r;
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_neg_i32:
- case INDEX_op_not_i32:
- return &r_r;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- return &rZ_r;
-
- case INDEX_op_add_i32:
- case INDEX_op_mul_i32:
- case INDEX_op_div_i32:
- case INDEX_op_divu_i32:
- case INDEX_op_sub_i32:
- case INDEX_op_and_i32:
- case INDEX_op_andc_i32:
- case INDEX_op_or_i32:
- case INDEX_op_orc_i32:
- case INDEX_op_xor_i32:
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_setcond_i32:
- return &r_rZ_rJ;
-
- case INDEX_op_brcond_i32:
- return &rZ_rJ;
- case INDEX_op_movcond_i32:
- return &movc_32;
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
- return &add2_32;
- case INDEX_op_mulu2_i32:
- case INDEX_op_muls2_i32:
- return &r_r_rZ_rJ;
-
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- return &R_r;
-
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return &RZ_r;
-
- case INDEX_op_add_i64:
- case INDEX_op_mul_i64:
- case INDEX_op_div_i64:
- case INDEX_op_divu_i64:
- case INDEX_op_sub_i64:
- case INDEX_op_and_i64:
- case INDEX_op_andc_i64:
- case INDEX_op_or_i64:
- case INDEX_op_orc_i64:
- case INDEX_op_xor_i64:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_setcond_i64:
- return &R_RZ_RJ;
-
- case INDEX_op_neg_i64:
- case INDEX_op_not_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext32u_i64:
- return &R_R;
-
- case INDEX_op_extrl_i64_i32:
- case INDEX_op_extrh_i64_i32:
- return &r_R;
-
- case INDEX_op_brcond_i64:
- return &RZ_RJ;
- case INDEX_op_movcond_i64:
- return &movc_64;
- case INDEX_op_add2_i64:
- case INDEX_op_sub2_i64:
- return &add2_64;
- case INDEX_op_muluh_i64:
- return &R_R_R;
-
- case INDEX_op_qemu_ld_i32:
- return &r_A;
- case INDEX_op_qemu_ld_i64:
- return &R_A;
- case INDEX_op_qemu_st_i32:
- return &sZ_A;
- case INDEX_op_qemu_st_i64:
- return &SZ_A;
-
- default:
- return NULL;
- }
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- /* Only probe for the platform and capabilities if we havn't already
- determined maximum values at compile time. */
-#ifndef use_vis3_instructions
- {
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
- use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
- }
-#endif
-
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
- tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;
-
- tcg_target_call_clobber_regs = 0;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
-}
-
-#if SPARC64
-# define ELF_HOST_MACHINE EM_SPARCV9
-#else
-# define ELF_HOST_MACHINE EM_SPARC32PLUS
-# define ELF_HOST_FLAGS EF_SPARC_32PLUS
-#endif
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
- uint8_t fde_win_save;
- uint8_t fde_ret_save[3];
-} DebugFrame;
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = -sizeof(void *) & 0x7f,
- .h.cie.return_column = 15, /* o7 */
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
-#if SPARC64
- 12, 30, /* DW_CFA_def_cfa i6, 2047 */
- (2047 & 0x7f) | 0x80, (2047 >> 7)
-#else
- 13, 30 /* DW_CFA_def_cfa_register i6 */
-#endif
- },
- .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */
- .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
-};
-
-void tcg_register_jit(void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
-
-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
- uintptr_t addr)
-{
- intptr_t tb_disp = addr - tc_ptr;
- intptr_t br_disp = addr - jmp_addr;
- tcg_insn_unit i1, i2;
-
- /* We can reach the entire address space for ILP32.
- For LP64, the code_gen_buffer can't be larger than 2GB. */
- tcg_debug_assert(tb_disp == (int32_t)tb_disp);
- tcg_debug_assert(br_disp == (int32_t)br_disp);
-
- if (!USE_REG_TB) {
- atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2));
- flush_icache_range(jmp_addr, jmp_addr + 4);
- return;
- }
-
- /* This does not exercise the range of the branch, but we do
- still need to be able to load the new value of TCG_REG_TB.
- But this does still happen quite often. */
- if (check_fit_ptr(tb_disp, 13)) {
- /* ba,pt %icc, addr */
- i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A)
- | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp));
- i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB)
- | INSN_IMM13(tb_disp));
- } else if (tb_disp >= 0) {
- i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10);
- i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)
- | INSN_IMM13(tb_disp & 0x3ff));
- } else {
- i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10);
- i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)
- | INSN_IMM13((tb_disp & 0x3ff) | -0x400));
- }
-
- atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1));
- flush_icache_range(jmp_addr, jmp_addr + 8);
-}
--- /dev/null
+/*
+ * TCG Backend Data: load-store optimization only.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef struct TCGLabelQemuLdst {
+ bool is_ld; /* qemu_ld: true, qemu_st: false */
+ TCGMemOpIdx oi;
+ TCGType type; /* result type of a load */
+ TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
+ TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
+ TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
+ TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
+ tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */
+ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */
+ QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next;
+} TCGLabelQemuLdst;
+
+
+/*
+ * Generate TB finalization at the end of block
+ */
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
+
+static int tcg_out_ldst_finalize(TCGContext *s)
+{
+ TCGLabelQemuLdst *lb;
+
+ /* qemu_ld/st slow paths */
+ QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) {
+ if (lb->is_ld
+ ? !tcg_out_qemu_ld_slow_path(s, lb)
+ : !tcg_out_qemu_st_slow_path(s, lb)) {
+ return -2;
+ }
+
+ /* Test for (pending) buffer overflow. The assumption is that any
+ one operation beginning below the high water mark cannot overrun
+ the buffer completely. Thus we can test for overflow after
+ generating code without having to check during generation. */
+ if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
+ return -1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Allocate a new TCGLabelQemuLdst entry.
+ */
+
+static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s)
+{
+ TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l));
+
+ QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next);
+
+ return l;
+}
+++ /dev/null
-/*
- * TCG Backend Data: load-store optimization only.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-typedef struct TCGLabelQemuLdst {
- bool is_ld; /* qemu_ld: true, qemu_st: false */
- TCGMemOpIdx oi;
- TCGType type; /* result type of a load */
- TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
- TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
- TCGReg datalo_reg; /* reg index for low word to be loaded or stored */
- TCGReg datahi_reg; /* reg index for high word to be loaded or stored */
- tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */
- tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */
- QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next;
-} TCGLabelQemuLdst;
-
-
-/*
- * Generate TB finalization at the end of block
- */
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
-
-static int tcg_out_ldst_finalize(TCGContext *s)
-{
- TCGLabelQemuLdst *lb;
-
- /* qemu_ld/st slow paths */
- QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) {
- if (lb->is_ld
- ? !tcg_out_qemu_ld_slow_path(s, lb)
- : !tcg_out_qemu_st_slow_path(s, lb)) {
- return -2;
- }
-
- /* Test for (pending) buffer overflow. The assumption is that any
- one operation beginning below the high water mark cannot overrun
- the buffer completely. Thus we can test for overflow after
- generating code without having to check during generation. */
- if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
- return -1;
- }
- }
- return 0;
-}
-
-/*
- * Allocate a new TCGLabelQemuLdst entry.
- */
-
-static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s)
-{
- TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l));
-
- QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next);
-
- return l;
-}
--- /dev/null
+/*
+ * TCG Backend Data: constant pool.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef struct TCGLabelPoolData {
+ struct TCGLabelPoolData *next;
+ tcg_insn_unit *label;
+ intptr_t addend;
+ int rtype;
+ unsigned nlong;
+ tcg_target_ulong data[];
+} TCGLabelPoolData;
+
+
+static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype,
+ tcg_insn_unit *label, intptr_t addend)
+{
+ TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData)
+ + sizeof(tcg_target_ulong) * nlong);
+
+ n->label = label;
+ n->addend = addend;
+ n->rtype = rtype;
+ n->nlong = nlong;
+ return n;
+}
+
+static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n)
+{
+ TCGLabelPoolData *i, **pp;
+ int nlong = n->nlong;
+
+ /* Insertion sort on the pool. */
+ for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) {
+ if (nlong > i->nlong) {
+ break;
+ }
+ if (nlong < i->nlong) {
+ continue;
+ }
+ if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) {
+ break;
+ }
+ }
+ n->next = *pp;
+ *pp = n;
+}
+
+/* The "usual" for generic integer code. */
+static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype,
+ tcg_insn_unit *label, intptr_t addend)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend);
+ n->data[0] = d;
+ new_pool_insert(s, n);
+}
+
+/* For v64 or v128, depending on the host. */
+static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label,
+ intptr_t addend, tcg_target_ulong d0,
+ tcg_target_ulong d1)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ new_pool_insert(s, n);
+}
+
+/* For v128 or v256, depending on the host. */
+static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label,
+ intptr_t addend, tcg_target_ulong d0,
+ tcg_target_ulong d1, tcg_target_ulong d2,
+ tcg_target_ulong d3)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ n->data[2] = d2;
+ n->data[3] = d3;
+ new_pool_insert(s, n);
+}
+
+/* For v256, for 32-bit host. */
+static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
+ intptr_t addend, tcg_target_ulong d0,
+ tcg_target_ulong d1, tcg_target_ulong d2,
+ tcg_target_ulong d3, tcg_target_ulong d4,
+ tcg_target_ulong d5, tcg_target_ulong d6,
+ tcg_target_ulong d7)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ n->data[2] = d2;
+ n->data[3] = d3;
+ n->data[4] = d4;
+ n->data[5] = d5;
+ n->data[6] = d6;
+ n->data[7] = d7;
+ new_pool_insert(s, n);
+}
+
+/* To be provided by cpu/tcg-target.c.inc. */
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
+
+static int tcg_out_pool_finalize(TCGContext *s)
+{
+ TCGLabelPoolData *p = s->pool_labels;
+ TCGLabelPoolData *l = NULL;
+ void *a;
+
+ if (p == NULL) {
+ return 0;
+ }
+
+ /* ??? Round up to qemu_icache_linesize, but then do not round
+ again when allocating the next TranslationBlock structure. */
+ a = (void *)ROUND_UP((uintptr_t)s->code_ptr,
+ sizeof(tcg_target_ulong) * p->nlong);
+ tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr);
+ s->data_gen_ptr = a;
+
+ for (; p != NULL; p = p->next) {
+ size_t size = sizeof(tcg_target_ulong) * p->nlong;
+ if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
+ if (unlikely(a > s->code_gen_highwater)) {
+ return -1;
+ }
+ memcpy(a, p->data, size);
+ a += size;
+ l = p;
+ }
+ if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) {
+ return -2;
+ }
+ }
+
+ s->code_ptr = a;
+ return 0;
+}
+++ /dev/null
-/*
- * TCG Backend Data: constant pool.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-typedef struct TCGLabelPoolData {
- struct TCGLabelPoolData *next;
- tcg_insn_unit *label;
- intptr_t addend;
- int rtype;
- unsigned nlong;
- tcg_target_ulong data[];
-} TCGLabelPoolData;
-
-
-static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype,
- tcg_insn_unit *label, intptr_t addend)
-{
- TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData)
- + sizeof(tcg_target_ulong) * nlong);
-
- n->label = label;
- n->addend = addend;
- n->rtype = rtype;
- n->nlong = nlong;
- return n;
-}
-
-static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n)
-{
- TCGLabelPoolData *i, **pp;
- int nlong = n->nlong;
-
- /* Insertion sort on the pool. */
- for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) {
- if (nlong > i->nlong) {
- break;
- }
- if (nlong < i->nlong) {
- continue;
- }
- if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) {
- break;
- }
- }
- n->next = *pp;
- *pp = n;
-}
-
-/* The "usual" for generic integer code. */
-static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype,
- tcg_insn_unit *label, intptr_t addend)
-{
- TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend);
- n->data[0] = d;
- new_pool_insert(s, n);
-}
-
-/* For v64 or v128, depending on the host. */
-static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label,
- intptr_t addend, tcg_target_ulong d0,
- tcg_target_ulong d1)
-{
- TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend);
- n->data[0] = d0;
- n->data[1] = d1;
- new_pool_insert(s, n);
-}
-
-/* For v128 or v256, depending on the host. */
-static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label,
- intptr_t addend, tcg_target_ulong d0,
- tcg_target_ulong d1, tcg_target_ulong d2,
- tcg_target_ulong d3)
-{
- TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend);
- n->data[0] = d0;
- n->data[1] = d1;
- n->data[2] = d2;
- n->data[3] = d3;
- new_pool_insert(s, n);
-}
-
-/* For v256, for 32-bit host. */
-static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
- intptr_t addend, tcg_target_ulong d0,
- tcg_target_ulong d1, tcg_target_ulong d2,
- tcg_target_ulong d3, tcg_target_ulong d4,
- tcg_target_ulong d5, tcg_target_ulong d6,
- tcg_target_ulong d7)
-{
- TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend);
- n->data[0] = d0;
- n->data[1] = d1;
- n->data[2] = d2;
- n->data[3] = d3;
- n->data[4] = d4;
- n->data[5] = d5;
- n->data[6] = d6;
- n->data[7] = d7;
- new_pool_insert(s, n);
-}
-
-/* To be provided by cpu/tcg-target.inc.c. */
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
-
-static int tcg_out_pool_finalize(TCGContext *s)
-{
- TCGLabelPoolData *p = s->pool_labels;
- TCGLabelPoolData *l = NULL;
- void *a;
-
- if (p == NULL) {
- return 0;
- }
-
- /* ??? Round up to qemu_icache_linesize, but then do not round
- again when allocating the next TranslationBlock structure. */
- a = (void *)ROUND_UP((uintptr_t)s->code_ptr,
- sizeof(tcg_target_ulong) * p->nlong);
- tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr);
- s->data_gen_ptr = a;
-
- for (; p != NULL; p = p->next) {
- size_t size = sizeof(tcg_target_ulong) * p->nlong;
- if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
- if (unlikely(a > s->code_gen_highwater)) {
- return -1;
- }
- memcpy(a, p->data, size);
- a += size;
- l = p;
- }
- if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) {
- return -2;
- }
- }
-
- s->code_ptr = a;
- return 0;
-}
#include "exec/log.h"
#include "sysemu/sysemu.h"
-/* Forward declarations for functions declared in tcg-target.inc.c and
+/* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
static void tcg_target_init(TCGContext *s);
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
size_t debug_frame_size)
__attribute__((unused));
-/* Forward declarations for functions declared and used in tcg-target.inc.c. */
+/* Forward declarations for functions declared and used in tcg-target.c.inc. */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type);
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
assert(s->tb_jmp_reset_offset[which] == off);
}
-#include "tcg-target.inc.c"
+#include "tcg-target.c.inc"
/* compare a pointer @ptr and a tb_tc @s */
static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s)
2) Implementation
Like each TCG host frontend, TCI implements the code generator in
-tcg-target.inc.c, tcg-target.h. Both files are in directory tcg/tci.
+tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci.
The additional file tcg/tci.c adds the interpreter.
would also improve speed for hosts which support byte alignment).
* A better disassembler for the pseudo code would be nice (a very primitive
- disassembler is included in tcg-target.inc.c).
+ disassembler is included in tcg-target.c.inc).
* It might be useful to have a runtime option which selects the native TCG
or TCI, so QEMU would have to include two TCGs. Today, selecting TCI
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2009, 2011 Stefan Weil
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* TODO list:
+ * - See TODO comments in code.
+ */
+
+/* Marker for missing code. */
+#define TODO() \
+ do { \
+ fprintf(stderr, "TODO %s:%u: %s()\n", \
+ __FILE__, __LINE__, __func__); \
+ tcg_abort(); \
+ } while (0)
+
+/* Bitfield n...m (in 32 bit value). */
+#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
+
+/* Macros used in tcg_target_op_defs. */
+#define R "r"
+#define RI "ri"
+#if TCG_TARGET_REG_BITS == 32
+# define R64 "r", "r"
+#else
+# define R64 "r"
+#endif
+#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
+# define L "L", "L"
+# define S "S", "S"
+#else
+# define L "L"
+# define S "S"
+#endif
+
+/* TODO: documentation. */
+static const TCGTargetOpDef tcg_target_op_defs[] = {
+ { INDEX_op_exit_tb, { NULL } },
+ { INDEX_op_goto_tb, { NULL } },
+ { INDEX_op_br, { NULL } },
+
+ { INDEX_op_ld8u_i32, { R, R } },
+ { INDEX_op_ld8s_i32, { R, R } },
+ { INDEX_op_ld16u_i32, { R, R } },
+ { INDEX_op_ld16s_i32, { R, R } },
+ { INDEX_op_ld_i32, { R, R } },
+ { INDEX_op_st8_i32, { R, R } },
+ { INDEX_op_st16_i32, { R, R } },
+ { INDEX_op_st_i32, { R, R } },
+
+ { INDEX_op_add_i32, { R, RI, RI } },
+ { INDEX_op_sub_i32, { R, RI, RI } },
+ { INDEX_op_mul_i32, { R, RI, RI } },
+#if TCG_TARGET_HAS_div_i32
+ { INDEX_op_div_i32, { R, R, R } },
+ { INDEX_op_divu_i32, { R, R, R } },
+ { INDEX_op_rem_i32, { R, R, R } },
+ { INDEX_op_remu_i32, { R, R, R } },
+#elif TCG_TARGET_HAS_div2_i32
+ { INDEX_op_div2_i32, { R, R, "0", "1", R } },
+ { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
+#endif
+ /* TODO: Does R, RI, RI result in faster code than R, R, RI?
+ If both operands are constants, we can optimize. */
+ { INDEX_op_and_i32, { R, RI, RI } },
+#if TCG_TARGET_HAS_andc_i32
+ { INDEX_op_andc_i32, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_eqv_i32
+ { INDEX_op_eqv_i32, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_nand_i32
+ { INDEX_op_nand_i32, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_nor_i32
+ { INDEX_op_nor_i32, { R, RI, RI } },
+#endif
+ { INDEX_op_or_i32, { R, RI, RI } },
+#if TCG_TARGET_HAS_orc_i32
+ { INDEX_op_orc_i32, { R, RI, RI } },
+#endif
+ { INDEX_op_xor_i32, { R, RI, RI } },
+ { INDEX_op_shl_i32, { R, RI, RI } },
+ { INDEX_op_shr_i32, { R, RI, RI } },
+ { INDEX_op_sar_i32, { R, RI, RI } },
+#if TCG_TARGET_HAS_rot_i32
+ { INDEX_op_rotl_i32, { R, RI, RI } },
+ { INDEX_op_rotr_i32, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_deposit_i32
+ { INDEX_op_deposit_i32, { R, "0", R } },
+#endif
+
+ { INDEX_op_brcond_i32, { R, RI } },
+
+ { INDEX_op_setcond_i32, { R, R, RI } },
+#if TCG_TARGET_REG_BITS == 64
+ { INDEX_op_setcond_i64, { R, R, RI } },
+#endif /* TCG_TARGET_REG_BITS == 64 */
+
+#if TCG_TARGET_REG_BITS == 32
+ /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
+ { INDEX_op_add2_i32, { R, R, R, R, R, R } },
+ { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
+ { INDEX_op_brcond2_i32, { R, R, RI, RI } },
+ { INDEX_op_mulu2_i32, { R, R, R, R } },
+ { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
+#endif
+
+#if TCG_TARGET_HAS_not_i32
+ { INDEX_op_not_i32, { R, R } },
+#endif
+#if TCG_TARGET_HAS_neg_i32
+ { INDEX_op_neg_i32, { R, R } },
+#endif
+
+#if TCG_TARGET_REG_BITS == 64
+ { INDEX_op_ld8u_i64, { R, R } },
+ { INDEX_op_ld8s_i64, { R, R } },
+ { INDEX_op_ld16u_i64, { R, R } },
+ { INDEX_op_ld16s_i64, { R, R } },
+ { INDEX_op_ld32u_i64, { R, R } },
+ { INDEX_op_ld32s_i64, { R, R } },
+ { INDEX_op_ld_i64, { R, R } },
+
+ { INDEX_op_st8_i64, { R, R } },
+ { INDEX_op_st16_i64, { R, R } },
+ { INDEX_op_st32_i64, { R, R } },
+ { INDEX_op_st_i64, { R, R } },
+
+ { INDEX_op_add_i64, { R, RI, RI } },
+ { INDEX_op_sub_i64, { R, RI, RI } },
+ { INDEX_op_mul_i64, { R, RI, RI } },
+#if TCG_TARGET_HAS_div_i64
+ { INDEX_op_div_i64, { R, R, R } },
+ { INDEX_op_divu_i64, { R, R, R } },
+ { INDEX_op_rem_i64, { R, R, R } },
+ { INDEX_op_remu_i64, { R, R, R } },
+#elif TCG_TARGET_HAS_div2_i64
+ { INDEX_op_div2_i64, { R, R, "0", "1", R } },
+ { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
+#endif
+ { INDEX_op_and_i64, { R, RI, RI } },
+#if TCG_TARGET_HAS_andc_i64
+ { INDEX_op_andc_i64, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_eqv_i64
+ { INDEX_op_eqv_i64, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_nand_i64
+ { INDEX_op_nand_i64, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_nor_i64
+ { INDEX_op_nor_i64, { R, RI, RI } },
+#endif
+ { INDEX_op_or_i64, { R, RI, RI } },
+#if TCG_TARGET_HAS_orc_i64
+ { INDEX_op_orc_i64, { R, RI, RI } },
+#endif
+ { INDEX_op_xor_i64, { R, RI, RI } },
+ { INDEX_op_shl_i64, { R, RI, RI } },
+ { INDEX_op_shr_i64, { R, RI, RI } },
+ { INDEX_op_sar_i64, { R, RI, RI } },
+#if TCG_TARGET_HAS_rot_i64
+ { INDEX_op_rotl_i64, { R, RI, RI } },
+ { INDEX_op_rotr_i64, { R, RI, RI } },
+#endif
+#if TCG_TARGET_HAS_deposit_i64
+ { INDEX_op_deposit_i64, { R, "0", R } },
+#endif
+ { INDEX_op_brcond_i64, { R, RI } },
+
+#if TCG_TARGET_HAS_ext8s_i64
+ { INDEX_op_ext8s_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext16s_i64
+ { INDEX_op_ext16s_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext32s_i64
+ { INDEX_op_ext32s_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext8u_i64
+ { INDEX_op_ext8u_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext16u_i64
+ { INDEX_op_ext16u_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext32u_i64
+ { INDEX_op_ext32u_i64, { R, R } },
+#endif
+ { INDEX_op_ext_i32_i64, { R, R } },
+ { INDEX_op_extu_i32_i64, { R, R } },
+#if TCG_TARGET_HAS_bswap16_i64
+ { INDEX_op_bswap16_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_bswap32_i64
+ { INDEX_op_bswap32_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_bswap64_i64
+ { INDEX_op_bswap64_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_not_i64
+ { INDEX_op_not_i64, { R, R } },
+#endif
+#if TCG_TARGET_HAS_neg_i64
+ { INDEX_op_neg_i64, { R, R } },
+#endif
+#endif /* TCG_TARGET_REG_BITS == 64 */
+
+ { INDEX_op_qemu_ld_i32, { R, L } },
+ { INDEX_op_qemu_ld_i64, { R64, L } },
+
+ { INDEX_op_qemu_st_i32, { R, S } },
+ { INDEX_op_qemu_st_i64, { R64, S } },
+
+#if TCG_TARGET_HAS_ext8s_i32
+ { INDEX_op_ext8s_i32, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext16s_i32
+ { INDEX_op_ext16s_i32, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext8u_i32
+ { INDEX_op_ext8u_i32, { R, R } },
+#endif
+#if TCG_TARGET_HAS_ext16u_i32
+ { INDEX_op_ext16u_i32, { R, R } },
+#endif
+
+#if TCG_TARGET_HAS_bswap16_i32
+ { INDEX_op_bswap16_i32, { R, R } },
+#endif
+#if TCG_TARGET_HAS_bswap32_i32
+ { INDEX_op_bswap32_i32, { R, R } },
+#endif
+
+ { INDEX_op_mb, { } },
+ { -1 },
+};
+
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ int i, n = ARRAY_SIZE(tcg_target_op_defs);
+
+ for (i = 0; i < n; ++i) {
+ if (tcg_target_op_defs[i].op == op) {
+ return &tcg_target_op_defs[i];
+ }
+ }
+ return NULL;
+}
+
+static const int tcg_target_reg_alloc_order[] = {
+ TCG_REG_R0,
+ TCG_REG_R1,
+ TCG_REG_R2,
+ TCG_REG_R3,
+#if 0 /* used for TCG_REG_CALL_STACK */
+ TCG_REG_R4,
+#endif
+ TCG_REG_R5,
+ TCG_REG_R6,
+ TCG_REG_R7,
+#if TCG_TARGET_NB_REGS >= 16
+ TCG_REG_R8,
+ TCG_REG_R9,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R12,
+ TCG_REG_R13,
+ TCG_REG_R14,
+ TCG_REG_R15,
+#endif
+};
+
+#if MAX_OPC_PARAM_IARGS != 6
+# error Fix needed, number of supported input arguments changed!
+#endif
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_R0,
+ TCG_REG_R1,
+ TCG_REG_R2,
+ TCG_REG_R3,
+#if 0 /* used for TCG_REG_CALL_STACK */
+ TCG_REG_R4,
+#endif
+ TCG_REG_R5,
+ TCG_REG_R6,
+#if TCG_TARGET_REG_BITS == 32
+ /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
+ TCG_REG_R7,
+#if TCG_TARGET_NB_REGS >= 16
+ TCG_REG_R8,
+ TCG_REG_R9,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R12,
+#else
+# error Too few input registers available
+#endif
+#endif
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_R0,
+#if TCG_TARGET_REG_BITS == 32
+ TCG_REG_R1
+#endif
+};
+
+#ifdef CONFIG_DEBUG_TCG
+static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "r00",
+ "r01",
+ "r02",
+ "r03",
+ "r04",
+ "r05",
+ "r06",
+ "r07",
+#if TCG_TARGET_NB_REGS >= 16
+ "r08",
+ "r09",
+ "r10",
+ "r11",
+ "r12",
+ "r13",
+ "r14",
+ "r15",
+#if TCG_TARGET_NB_REGS >= 32
+ "r16",
+ "r17",
+ "r18",
+ "r19",
+ "r20",
+ "r21",
+ "r22",
+ "r23",
+ "r24",
+ "r25",
+ "r26",
+ "r27",
+ "r28",
+ "r29",
+ "r30",
+ "r31"
+#endif
+#endif
+};
+#endif
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ /* tcg_out_reloc always uses the same type, addend. */
+ tcg_debug_assert(type == sizeof(tcg_target_long));
+ tcg_debug_assert(addend == 0);
+ tcg_debug_assert(value != 0);
+ if (TCG_TARGET_REG_BITS == 32) {
+ tcg_patch32(code_ptr, value);
+ } else {
+ tcg_patch64(code_ptr, value);
+ }
+ return true;
+}
+
+/* Parse target specific constraints. */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+ const char *ct_str, TCGType type)
+{
+ switch (*ct_str++) {
+ case 'r':
+ case 'L': /* qemu_ld constraint */
+ case 'S': /* qemu_st constraint */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
+ break;
+ default:
+ return NULL;
+ }
+ return ct_str;
+}
+
+#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
+/* Show current bytecode. Used by tcg interpreter. */
+void tci_disas(uint8_t opc)
+{
+ const TCGOpDef *def = &tcg_op_defs[opc];
+ fprintf(stderr, "TCG %s %u, %u, %u\n",
+ def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
+}
+#endif
+
+/* Write value (native size). */
+static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
+{
+ if (TCG_TARGET_REG_BITS == 32) {
+ tcg_out32(s, v);
+ } else {
+ tcg_out64(s, v);
+ }
+}
+
+/* Write opcode. */
+static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
+{
+ tcg_out8(s, op);
+ tcg_out8(s, 0);
+}
+
+/* Write register. */
+static void tcg_out_r(TCGContext *s, TCGArg t0)
+{
+ tcg_debug_assert(t0 < TCG_TARGET_NB_REGS);
+ tcg_out8(s, t0);
+}
+
+/* Write register or constant (native size). */
+static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
+{
+ if (const_arg) {
+ tcg_debug_assert(const_arg == 1);
+ tcg_out8(s, TCG_CONST);
+ tcg_out_i(s, arg);
+ } else {
+ tcg_out_r(s, arg);
+ }
+}
+
+/* Write register or constant (32 bit). */
+static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
+{
+ if (const_arg) {
+ tcg_debug_assert(const_arg == 1);
+ tcg_out8(s, TCG_CONST);
+ tcg_out32(s, arg);
+ } else {
+ tcg_out_r(s, arg);
+ }
+}
+
+#if TCG_TARGET_REG_BITS == 64
+/* Write register or constant (64 bit). */
+static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
+{
+ if (const_arg) {
+ tcg_debug_assert(const_arg == 1);
+ tcg_out8(s, TCG_CONST);
+ tcg_out64(s, arg);
+ } else {
+ tcg_out_r(s, arg);
+ }
+}
+#endif
+
+/* Write label. */
+static void tci_out_label(TCGContext *s, TCGLabel *label)
+{
+ if (label->has_value) {
+ tcg_out_i(s, label->u.value);
+ tcg_debug_assert(label->u.value);
+ } else {
+ tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
+ s->code_ptr += sizeof(tcg_target_ulong);
+ }
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
+ intptr_t arg2)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+ if (type == TCG_TYPE_I32) {
+ tcg_out_op_t(s, INDEX_op_ld_i32);
+ tcg_out_r(s, ret);
+ tcg_out_r(s, arg1);
+ tcg_out32(s, arg2);
+ } else {
+ tcg_debug_assert(type == TCG_TYPE_I64);
+#if TCG_TARGET_REG_BITS == 64
+ tcg_out_op_t(s, INDEX_op_ld_i64);
+ tcg_out_r(s, ret);
+ tcg_out_r(s, arg1);
+ tcg_debug_assert(arg2 == (int32_t)arg2);
+ tcg_out32(s, arg2);
+#else
+ TODO();
+#endif
+ }
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+ tcg_debug_assert(ret != arg);
+#if TCG_TARGET_REG_BITS == 32
+ tcg_out_op_t(s, INDEX_op_mov_i32);
+#else
+ tcg_out_op_t(s, INDEX_op_mov_i64);
+#endif
+ tcg_out_r(s, ret);
+ tcg_out_r(s, arg);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+ return true;
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg t0, tcg_target_long arg)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+ uint32_t arg32 = arg;
+ if (type == TCG_TYPE_I32 || arg == arg32) {
+ tcg_out_op_t(s, INDEX_op_movi_i32);
+ tcg_out_r(s, t0);
+ tcg_out32(s, arg32);
+ } else {
+ tcg_debug_assert(type == TCG_TYPE_I64);
+#if TCG_TARGET_REG_BITS == 64
+ tcg_out_op_t(s, INDEX_op_movi_i64);
+ tcg_out_r(s, t0);
+ tcg_out64(s, arg);
+#else
+ TODO();
+#endif
+ }
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
+static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+ tcg_out_op_t(s, INDEX_op_call);
+ tcg_out_ri(s, 1, (uintptr_t)arg);
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
+ const int *const_args)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+
+ tcg_out_op_t(s, opc);
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ tcg_out64(s, args[0]);
+ break;
+ case INDEX_op_goto_tb:
+ if (s->tb_jmp_insn_offset) {
+ /* Direct jump method. */
+ /* Align for atomic patching and thread safety */
+ s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4);
+ s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
+ tcg_out32(s, 0);
+ } else {
+ /* Indirect jump method. */
+ TODO();
+ }
+ set_jmp_reset_offset(s, args[0]);
+ break;
+ case INDEX_op_br:
+ tci_out_label(s, arg_label(args[0]));
+ break;
+ case INDEX_op_setcond_i32:
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_ri32(s, const_args[2], args[2]);
+ tcg_out8(s, args[3]); /* condition */
+ break;
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_setcond2_i32:
+ /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
+ tcg_out_ri32(s, const_args[3], args[3]);
+ tcg_out_ri32(s, const_args[4], args[4]);
+ tcg_out8(s, args[5]); /* condition */
+ break;
+#elif TCG_TARGET_REG_BITS == 64
+ case INDEX_op_setcond_i64:
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_ri64(s, const_args[2], args[2]);
+ tcg_out8(s, args[3]); /* condition */
+ break;
+#endif
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_debug_assert(args[2] == (int32_t)args[2]);
+ tcg_out32(s, args[2]);
+ break;
+ case INDEX_op_add_i32:
+ case INDEX_op_sub_i32:
+ case INDEX_op_mul_i32:
+ case INDEX_op_and_i32:
+ case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
+ case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
+ case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
+ case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
+ case INDEX_op_or_i32:
+ case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
+ case INDEX_op_xor_i32:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
+ case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
+ tcg_out_r(s, args[0]);
+ tcg_out_ri32(s, const_args[1], args[1]);
+ tcg_out_ri32(s, const_args[2], args[2]);
+ break;
+ case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
+ tcg_debug_assert(args[3] <= UINT8_MAX);
+ tcg_out8(s, args[3]);
+ tcg_debug_assert(args[4] <= UINT8_MAX);
+ tcg_out8(s, args[4]);
+ break;
+
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_add_i64:
+ case INDEX_op_sub_i64:
+ case INDEX_op_mul_i64:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
+ case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
+ case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
+ case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
+ case INDEX_op_or_i64:
+ case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
+ case INDEX_op_xor_i64:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
+ case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
+ tcg_out_r(s, args[0]);
+ tcg_out_ri64(s, const_args[1], args[1]);
+ tcg_out_ri64(s, const_args[2], args[2]);
+ break;
+ case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
+ tcg_debug_assert(args[3] <= UINT8_MAX);
+ tcg_out8(s, args[3]);
+ tcg_debug_assert(args[4] <= UINT8_MAX);
+ tcg_out8(s, args[4]);
+ break;
+ case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ TODO();
+ break;
+ case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
+ case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
+ TODO();
+ break;
+ case INDEX_op_brcond_i64:
+ tcg_out_r(s, args[0]);
+ tcg_out_ri64(s, const_args[1], args[1]);
+ tcg_out8(s, args[2]); /* condition */
+ tci_out_label(s, arg_label(args[3]));
+ break;
+ case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
+ case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
+ case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
+ case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
+ case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
+ case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
+ case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
+ case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
+ case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
+ case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
+ case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+#endif /* TCG_TARGET_REG_BITS == 64 */
+ case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
+ case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
+ case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
+ case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
+ case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
+ case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
+ case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
+ case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ break;
+ case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
+ case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
+ case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
+ case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
+ tcg_out_r(s, args[0]);
+ tcg_out_ri32(s, const_args[1], args[1]);
+ tcg_out_ri32(s, const_args[2], args[2]);
+ break;
+ case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
+ case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
+ TODO();
+ break;
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
+ tcg_out_r(s, args[3]);
+ tcg_out_r(s, args[4]);
+ tcg_out_r(s, args[5]);
+ break;
+ case INDEX_op_brcond2_i32:
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_ri32(s, const_args[2], args[2]);
+ tcg_out_ri32(s, const_args[3], args[3]);
+ tcg_out8(s, args[4]); /* condition */
+ tci_out_label(s, arg_label(args[5]));
+ break;
+ case INDEX_op_mulu2_i32:
+ tcg_out_r(s, args[0]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
+ tcg_out_r(s, args[3]);
+ break;
+#endif
+ case INDEX_op_brcond_i32:
+ tcg_out_r(s, args[0]);
+ tcg_out_ri32(s, const_args[1], args[1]);
+ tcg_out8(s, args[2]); /* condition */
+ tci_out_label(s, arg_label(args[3]));
+ break;
+ case INDEX_op_qemu_ld_i32:
+ tcg_out_r(s, *args++);
+ tcg_out_r(s, *args++);
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ tcg_out_r(s, *args++);
+ }
+ tcg_out_i(s, *args++);
+ break;
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_r(s, *args++);
+ if (TCG_TARGET_REG_BITS == 32) {
+ tcg_out_r(s, *args++);
+ }
+ tcg_out_r(s, *args++);
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ tcg_out_r(s, *args++);
+ }
+ tcg_out_i(s, *args++);
+ break;
+ case INDEX_op_qemu_st_i32:
+ tcg_out_r(s, *args++);
+ tcg_out_r(s, *args++);
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ tcg_out_r(s, *args++);
+ }
+ tcg_out_i(s, *args++);
+ break;
+ case INDEX_op_qemu_st_i64:
+ tcg_out_r(s, *args++);
+ if (TCG_TARGET_REG_BITS == 32) {
+ tcg_out_r(s, *args++);
+ }
+ tcg_out_r(s, *args++);
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+ tcg_out_r(s, *args++);
+ }
+ tcg_out_i(s, *args++);
+ break;
+ case INDEX_op_mb:
+ break;
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
+ intptr_t arg2)
+{
+ uint8_t *old_code_ptr = s->code_ptr;
+ if (type == TCG_TYPE_I32) {
+ tcg_out_op_t(s, INDEX_op_st_i32);
+ tcg_out_r(s, arg);
+ tcg_out_r(s, arg1);
+ tcg_out32(s, arg2);
+ } else {
+ tcg_debug_assert(type == TCG_TYPE_I64);
+#if TCG_TARGET_REG_BITS == 64
+ tcg_out_op_t(s, INDEX_op_st_i64);
+ tcg_out_r(s, arg);
+ tcg_out_r(s, arg1);
+ tcg_out32(s, arg2);
+#else
+ TODO();
+#endif
+ }
+ old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ return false;
+}
+
+/* Test if a constant matches the constraint. */
+static int tcg_target_const_match(tcg_target_long val, TCGType type,
+ const TCGArgConstraint *arg_ct)
+{
+ /* No need to return 0 or 1, 0 or != 0 is good enough. */
+ return arg_ct->ct & TCG_CT_CONST;
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
+ const char *envval = getenv("DEBUG_TCG");
+ if (envval) {
+ qemu_set_log(strtol(envval, NULL, 0));
+ }
+#endif
+
+ /* The current code uses uint8_t for tcg operations. */
+ tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX);
+
+ /* Registers available for 32 bit operations. */
+ tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
+ /* Registers available for 64 bit operations. */
+ tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
+ /* TODO: Which registers should be set here? */
+ tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+
+ /* We use negative offsets from "sp" so that we can distinguish
+ stores that might pretend to be call arguments. */
+ tcg_set_frame(s, TCG_REG_CALL_STACK,
+ -CPU_TEMP_BUF_NLONGS * sizeof(long),
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
+}
+
+/* Generate global QEMU prologue and epilogue code. */
+static inline void tcg_target_qemu_prologue(TCGContext *s)
+{
+}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2009, 2011 Stefan Weil
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/* TODO list:
- * - See TODO comments in code.
- */
-
-/* Marker for missing code. */
-#define TODO() \
- do { \
- fprintf(stderr, "TODO %s:%u: %s()\n", \
- __FILE__, __LINE__, __func__); \
- tcg_abort(); \
- } while (0)
-
-/* Bitfield n...m (in 32 bit value). */
-#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
-
-/* Macros used in tcg_target_op_defs. */
-#define R "r"
-#define RI "ri"
-#if TCG_TARGET_REG_BITS == 32
-# define R64 "r", "r"
-#else
-# define R64 "r"
-#endif
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L "L", "L"
-# define S "S", "S"
-#else
-# define L "L"
-# define S "S"
-#endif
-
-/* TODO: documentation. */
-static const TCGTargetOpDef tcg_target_op_defs[] = {
- { INDEX_op_exit_tb, { NULL } },
- { INDEX_op_goto_tb, { NULL } },
- { INDEX_op_br, { NULL } },
-
- { INDEX_op_ld8u_i32, { R, R } },
- { INDEX_op_ld8s_i32, { R, R } },
- { INDEX_op_ld16u_i32, { R, R } },
- { INDEX_op_ld16s_i32, { R, R } },
- { INDEX_op_ld_i32, { R, R } },
- { INDEX_op_st8_i32, { R, R } },
- { INDEX_op_st16_i32, { R, R } },
- { INDEX_op_st_i32, { R, R } },
-
- { INDEX_op_add_i32, { R, RI, RI } },
- { INDEX_op_sub_i32, { R, RI, RI } },
- { INDEX_op_mul_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i32
- { INDEX_op_div_i32, { R, R, R } },
- { INDEX_op_divu_i32, { R, R, R } },
- { INDEX_op_rem_i32, { R, R, R } },
- { INDEX_op_remu_i32, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i32
- { INDEX_op_div2_i32, { R, R, "0", "1", R } },
- { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
-#endif
- /* TODO: Does R, RI, RI result in faster code than R, R, RI?
- If both operands are constants, we can optimize. */
- { INDEX_op_and_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i32
- { INDEX_op_andc_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i32
- { INDEX_op_eqv_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i32
- { INDEX_op_nand_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i32
- { INDEX_op_nor_i32, { R, RI, RI } },
-#endif
- { INDEX_op_or_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i32
- { INDEX_op_orc_i32, { R, RI, RI } },
-#endif
- { INDEX_op_xor_i32, { R, RI, RI } },
- { INDEX_op_shl_i32, { R, RI, RI } },
- { INDEX_op_shr_i32, { R, RI, RI } },
- { INDEX_op_sar_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i32
- { INDEX_op_rotl_i32, { R, RI, RI } },
- { INDEX_op_rotr_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i32
- { INDEX_op_deposit_i32, { R, "0", R } },
-#endif
-
- { INDEX_op_brcond_i32, { R, RI } },
-
- { INDEX_op_setcond_i32, { R, R, RI } },
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_setcond_i64, { R, R, RI } },
-#endif /* TCG_TARGET_REG_BITS == 64 */
-
-#if TCG_TARGET_REG_BITS == 32
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
- { INDEX_op_add2_i32, { R, R, R, R, R, R } },
- { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
- { INDEX_op_brcond2_i32, { R, R, RI, RI } },
- { INDEX_op_mulu2_i32, { R, R, R, R } },
- { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
-#endif
-
-#if TCG_TARGET_HAS_not_i32
- { INDEX_op_not_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i32
- { INDEX_op_neg_i32, { R, R } },
-#endif
-
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_ld8u_i64, { R, R } },
- { INDEX_op_ld8s_i64, { R, R } },
- { INDEX_op_ld16u_i64, { R, R } },
- { INDEX_op_ld16s_i64, { R, R } },
- { INDEX_op_ld32u_i64, { R, R } },
- { INDEX_op_ld32s_i64, { R, R } },
- { INDEX_op_ld_i64, { R, R } },
-
- { INDEX_op_st8_i64, { R, R } },
- { INDEX_op_st16_i64, { R, R } },
- { INDEX_op_st32_i64, { R, R } },
- { INDEX_op_st_i64, { R, R } },
-
- { INDEX_op_add_i64, { R, RI, RI } },
- { INDEX_op_sub_i64, { R, RI, RI } },
- { INDEX_op_mul_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i64
- { INDEX_op_div_i64, { R, R, R } },
- { INDEX_op_divu_i64, { R, R, R } },
- { INDEX_op_rem_i64, { R, R, R } },
- { INDEX_op_remu_i64, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i64
- { INDEX_op_div2_i64, { R, R, "0", "1", R } },
- { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
-#endif
- { INDEX_op_and_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i64
- { INDEX_op_andc_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i64
- { INDEX_op_eqv_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i64
- { INDEX_op_nand_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i64
- { INDEX_op_nor_i64, { R, RI, RI } },
-#endif
- { INDEX_op_or_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i64
- { INDEX_op_orc_i64, { R, RI, RI } },
-#endif
- { INDEX_op_xor_i64, { R, RI, RI } },
- { INDEX_op_shl_i64, { R, RI, RI } },
- { INDEX_op_shr_i64, { R, RI, RI } },
- { INDEX_op_sar_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i64
- { INDEX_op_rotl_i64, { R, RI, RI } },
- { INDEX_op_rotr_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i64
- { INDEX_op_deposit_i64, { R, "0", R } },
-#endif
- { INDEX_op_brcond_i64, { R, RI } },
-
-#if TCG_TARGET_HAS_ext8s_i64
- { INDEX_op_ext8s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
- { INDEX_op_ext16s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32s_i64
- { INDEX_op_ext32s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i64
- { INDEX_op_ext8u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
- { INDEX_op_ext16u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32u_i64
- { INDEX_op_ext32u_i64, { R, R } },
-#endif
- { INDEX_op_ext_i32_i64, { R, R } },
- { INDEX_op_extu_i32_i64, { R, R } },
-#if TCG_TARGET_HAS_bswap16_i64
- { INDEX_op_bswap16_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i64
- { INDEX_op_bswap32_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap64_i64
- { INDEX_op_bswap64_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_not_i64
- { INDEX_op_not_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i64
- { INDEX_op_neg_i64, { R, R } },
-#endif
-#endif /* TCG_TARGET_REG_BITS == 64 */
-
- { INDEX_op_qemu_ld_i32, { R, L } },
- { INDEX_op_qemu_ld_i64, { R64, L } },
-
- { INDEX_op_qemu_st_i32, { R, S } },
- { INDEX_op_qemu_st_i64, { R64, S } },
-
-#if TCG_TARGET_HAS_ext8s_i32
- { INDEX_op_ext8s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i32
- { INDEX_op_ext16s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i32
- { INDEX_op_ext8u_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i32
- { INDEX_op_ext16u_i32, { R, R } },
-#endif
-
-#if TCG_TARGET_HAS_bswap16_i32
- { INDEX_op_bswap16_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i32
- { INDEX_op_bswap32_i32, { R, R } },
-#endif
-
- { INDEX_op_mb, { } },
- { -1 },
-};
-
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- int i, n = ARRAY_SIZE(tcg_target_op_defs);
-
- for (i = 0; i < n; ++i) {
- if (tcg_target_op_defs[i].op == op) {
- return &tcg_target_op_defs[i];
- }
- }
- return NULL;
-}
-
-static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
-#if 0 /* used for TCG_REG_CALL_STACK */
- TCG_REG_R4,
-#endif
- TCG_REG_R5,
- TCG_REG_R6,
- TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R12,
- TCG_REG_R13,
- TCG_REG_R14,
- TCG_REG_R15,
-#endif
-};
-
-#if MAX_OPC_PARAM_IARGS != 6
-# error Fix needed, number of supported input arguments changed!
-#endif
-
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
-#if 0 /* used for TCG_REG_CALL_STACK */
- TCG_REG_R4,
-#endif
- TCG_REG_R5,
- TCG_REG_R6,
-#if TCG_TARGET_REG_BITS == 32
- /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
- TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R12,
-#else
-# error Too few input registers available
-#endif
-#endif
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_R0,
-#if TCG_TARGET_REG_BITS == 32
- TCG_REG_R1
-#endif
-};
-
-#ifdef CONFIG_DEBUG_TCG
-static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "r00",
- "r01",
- "r02",
- "r03",
- "r04",
- "r05",
- "r06",
- "r07",
-#if TCG_TARGET_NB_REGS >= 16
- "r08",
- "r09",
- "r10",
- "r11",
- "r12",
- "r13",
- "r14",
- "r15",
-#if TCG_TARGET_NB_REGS >= 32
- "r16",
- "r17",
- "r18",
- "r19",
- "r20",
- "r21",
- "r22",
- "r23",
- "r24",
- "r25",
- "r26",
- "r27",
- "r28",
- "r29",
- "r30",
- "r31"
-#endif
-#endif
-};
-#endif
-
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
-{
- /* tcg_out_reloc always uses the same type, addend. */
- tcg_debug_assert(type == sizeof(tcg_target_long));
- tcg_debug_assert(addend == 0);
- tcg_debug_assert(value != 0);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_patch32(code_ptr, value);
- } else {
- tcg_patch64(code_ptr, value);
- }
- return true;
-}
-
-/* Parse target specific constraints. */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch (*ct_str++) {
- case 'r':
- case 'L': /* qemu_ld constraint */
- case 'S': /* qemu_st constraint */
- ct->ct |= TCG_CT_REG;
- ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
-#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
-/* Show current bytecode. Used by tcg interpreter. */
-void tci_disas(uint8_t opc)
-{
- const TCGOpDef *def = &tcg_op_defs[opc];
- fprintf(stderr, "TCG %s %u, %u, %u\n",
- def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
-}
-#endif
-
-/* Write value (native size). */
-static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
-{
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out32(s, v);
- } else {
- tcg_out64(s, v);
- }
-}
-
-/* Write opcode. */
-static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
-{
- tcg_out8(s, op);
- tcg_out8(s, 0);
-}
-
-/* Write register. */
-static void tcg_out_r(TCGContext *s, TCGArg t0)
-{
- tcg_debug_assert(t0 < TCG_TARGET_NB_REGS);
- tcg_out8(s, t0);
-}
-
-/* Write register or constant (native size). */
-static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
-{
- if (const_arg) {
- tcg_debug_assert(const_arg == 1);
- tcg_out8(s, TCG_CONST);
- tcg_out_i(s, arg);
- } else {
- tcg_out_r(s, arg);
- }
-}
-
-/* Write register or constant (32 bit). */
-static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
-{
- if (const_arg) {
- tcg_debug_assert(const_arg == 1);
- tcg_out8(s, TCG_CONST);
- tcg_out32(s, arg);
- } else {
- tcg_out_r(s, arg);
- }
-}
-
-#if TCG_TARGET_REG_BITS == 64
-/* Write register or constant (64 bit). */
-static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
-{
- if (const_arg) {
- tcg_debug_assert(const_arg == 1);
- tcg_out8(s, TCG_CONST);
- tcg_out64(s, arg);
- } else {
- tcg_out_r(s, arg);
- }
-}
-#endif
-
-/* Write label. */
-static void tci_out_label(TCGContext *s, TCGLabel *label)
-{
- if (label->has_value) {
- tcg_out_i(s, label->u.value);
- tcg_debug_assert(label->u.value);
- } else {
- tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
- s->code_ptr += sizeof(tcg_target_ulong);
- }
-}
-
-static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
- intptr_t arg2)
-{
- uint8_t *old_code_ptr = s->code_ptr;
- if (type == TCG_TYPE_I32) {
- tcg_out_op_t(s, INDEX_op_ld_i32);
- tcg_out_r(s, ret);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
-#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_ld_i64);
- tcg_out_r(s, ret);
- tcg_out_r(s, arg1);
- tcg_debug_assert(arg2 == (int32_t)arg2);
- tcg_out32(s, arg2);
-#else
- TODO();
-#endif
- }
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
-{
- uint8_t *old_code_ptr = s->code_ptr;
- tcg_debug_assert(ret != arg);
-#if TCG_TARGET_REG_BITS == 32
- tcg_out_op_t(s, INDEX_op_mov_i32);
-#else
- tcg_out_op_t(s, INDEX_op_mov_i64);
-#endif
- tcg_out_r(s, ret);
- tcg_out_r(s, arg);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
- return true;
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg t0, tcg_target_long arg)
-{
- uint8_t *old_code_ptr = s->code_ptr;
- uint32_t arg32 = arg;
- if (type == TCG_TYPE_I32 || arg == arg32) {
- tcg_out_op_t(s, INDEX_op_movi_i32);
- tcg_out_r(s, t0);
- tcg_out32(s, arg32);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
-#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_movi_i64);
- tcg_out_r(s, t0);
- tcg_out64(s, arg);
-#else
- TODO();
-#endif
- }
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
-static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
-{
- uint8_t *old_code_ptr = s->code_ptr;
- tcg_out_op_t(s, INDEX_op_call);
- tcg_out_ri(s, 1, (uintptr_t)arg);
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
-static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
- const int *const_args)
-{
- uint8_t *old_code_ptr = s->code_ptr;
-
- tcg_out_op_t(s, opc);
-
- switch (opc) {
- case INDEX_op_exit_tb:
- tcg_out64(s, args[0]);
- break;
- case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* Direct jump method. */
- /* Align for atomic patching and thread safety */
- s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4);
- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
- tcg_out32(s, 0);
- } else {
- /* Indirect jump method. */
- TODO();
- }
- set_jmp_reset_offset(s, args[0]);
- break;
- case INDEX_op_br:
- tci_out_label(s, arg_label(args[0]));
- break;
- case INDEX_op_setcond_i32:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
- tcg_out8(s, args[3]); /* condition */
- break;
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_setcond2_i32:
- /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_ri32(s, const_args[3], args[3]);
- tcg_out_ri32(s, const_args[4], args[4]);
- tcg_out8(s, args[5]); /* condition */
- break;
-#elif TCG_TARGET_REG_BITS == 64
- case INDEX_op_setcond_i64:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_ri64(s, const_args[2], args[2]);
- tcg_out8(s, args[3]); /* condition */
- break;
-#endif
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_debug_assert(args[2] == (int32_t)args[2]);
- tcg_out32(s, args[2]);
- break;
- case INDEX_op_add_i32:
- case INDEX_op_sub_i32:
- case INDEX_op_mul_i32:
- case INDEX_op_and_i32:
- case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
- case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
- case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
- case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
- case INDEX_op_or_i32:
- case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
- case INDEX_op_xor_i32:
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
- case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
- tcg_out_r(s, args[0]);
- tcg_out_ri32(s, const_args[1], args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
- break;
- case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_debug_assert(args[3] <= UINT8_MAX);
- tcg_out8(s, args[3]);
- tcg_debug_assert(args[4] <= UINT8_MAX);
- tcg_out8(s, args[4]);
- break;
-
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_add_i64:
- case INDEX_op_sub_i64:
- case INDEX_op_mul_i64:
- case INDEX_op_and_i64:
- case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
- case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
- case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
- case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
- case INDEX_op_or_i64:
- case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
- case INDEX_op_xor_i64:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
- case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
- tcg_out_r(s, args[0]);
- tcg_out_ri64(s, const_args[1], args[1]);
- tcg_out_ri64(s, const_args[2], args[2]);
- break;
- case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_debug_assert(args[3] <= UINT8_MAX);
- tcg_out8(s, args[3]);
- tcg_debug_assert(args[4] <= UINT8_MAX);
- tcg_out8(s, args[4]);
- break;
- case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- TODO();
- break;
- case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
- case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
- TODO();
- break;
- case INDEX_op_brcond_i64:
- tcg_out_r(s, args[0]);
- tcg_out_ri64(s, const_args[1], args[1]);
- tcg_out8(s, args[2]); /* condition */
- tci_out_label(s, arg_label(args[3]));
- break;
- case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
- case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
- case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
- case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
- case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
- case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
- case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
- case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
- case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
- case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
- case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
-#endif /* TCG_TARGET_REG_BITS == 64 */
- case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
- case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
- case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
- case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
- case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
- case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
- case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
- case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- break;
- case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
- tcg_out_r(s, args[0]);
- tcg_out_ri32(s, const_args[1], args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
- break;
- case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
- case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
- TODO();
- break;
-#if TCG_TARGET_REG_BITS == 32
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_r(s, args[3]);
- tcg_out_r(s, args[4]);
- tcg_out_r(s, args[5]);
- break;
- case INDEX_op_brcond2_i32:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
- tcg_out_ri32(s, const_args[3], args[3]);
- tcg_out8(s, args[4]); /* condition */
- tci_out_label(s, arg_label(args[5]));
- break;
- case INDEX_op_mulu2_i32:
- tcg_out_r(s, args[0]);
- tcg_out_r(s, args[1]);
- tcg_out_r(s, args[2]);
- tcg_out_r(s, args[3]);
- break;
-#endif
- case INDEX_op_brcond_i32:
- tcg_out_r(s, args[0]);
- tcg_out_ri32(s, const_args[1], args[1]);
- tcg_out8(s, args[2]); /* condition */
- tci_out_label(s, arg_label(args[3]));
- break;
- case INDEX_op_qemu_ld_i32:
- tcg_out_r(s, *args++);
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_r(s, *args++);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_r(s, *args++);
- }
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
- case INDEX_op_qemu_st_i32:
- tcg_out_r(s, *args++);
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
- case INDEX_op_qemu_st_i64:
- tcg_out_r(s, *args++);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_r(s, *args++);
- }
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
- case INDEX_op_mb:
- break;
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
-static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
- intptr_t arg2)
-{
- uint8_t *old_code_ptr = s->code_ptr;
- if (type == TCG_TYPE_I32) {
- tcg_out_op_t(s, INDEX_op_st_i32);
- tcg_out_r(s, arg);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
- } else {
- tcg_debug_assert(type == TCG_TYPE_I64);
-#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_st_i64);
- tcg_out_r(s, arg);
- tcg_out_r(s, arg1);
- tcg_out32(s, arg2);
-#else
- TODO();
-#endif
- }
- old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- return false;
-}
-
-/* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
- const TCGArgConstraint *arg_ct)
-{
- /* No need to return 0 or 1, 0 or != 0 is good enough. */
- return arg_ct->ct & TCG_CT_CONST;
-}
-
-static void tcg_target_init(TCGContext *s)
-{
-#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
- const char *envval = getenv("DEBUG_TCG");
- if (envval) {
- qemu_set_log(strtol(envval, NULL, 0));
- }
-#endif
-
- /* The current code uses uint8_t for tcg operations. */
- tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX);
-
- /* Registers available for 32 bit operations. */
- tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
- /* Registers available for 64 bit operations. */
- tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
- /* TODO: Which registers should be set here? */
- tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
-
- /* We use negative offsets from "sp" so that we can distinguish
- stores that might pretend to be call arguments. */
- tcg_set_frame(s, TCG_REG_CALL_STACK,
- -CPU_TEMP_BUF_NLONGS * sizeof(long),
- CPU_TEMP_BUF_NLONGS * sizeof(long));
-}
-
-/* Generate global QEMU prologue and epilogue code. */
-static inline void tcg_target_qemu_prologue(TCGContext *s)
-{
-}
}
/* keep wrappers separate but do not bother defining headers for all of them */
-#include "wrap.inc.c"
+#include "wrap.c.inc"
static void not_implemented(void)
{
--- /dev/null
+/*
+ * In this file we wrap QEMU FP functions to look like softfloat/testfloat's,
+ * so that we can use the testfloat infrastructure as-is.
+ *
+ * This file must be included directly from fp-test.c. We could compile it
+ * separately, but it would be tedious to add declarations for all the wrappers.
+ */
+
+static signed char sf_tininess_to_qemu(uint_fast8_t mode)
+{
+ switch (mode) {
+ case softfloat_tininess_beforeRounding:
+ return float_tininess_before_rounding;
+ case softfloat_tininess_afterRounding:
+ return float_tininess_after_rounding;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static signed char sf_rounding_to_qemu(uint_fast8_t mode)
+{
+ switch (mode) {
+ case softfloat_round_near_even:
+ return float_round_nearest_even;
+ case softfloat_round_minMag:
+ return float_round_to_zero;
+ case softfloat_round_min:
+ return float_round_down;
+ case softfloat_round_max:
+ return float_round_up;
+ case softfloat_round_near_maxMag:
+ return float_round_ties_away;
+ case softfloat_round_odd:
+ return float_round_to_odd;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static uint_fast8_t qemu_flags_to_sf(uint8_t qflags)
+{
+ uint_fast8_t ret = 0;
+
+ if (qflags & float_flag_invalid) {
+ ret |= softfloat_flag_invalid;
+ }
+ if (qflags & float_flag_divbyzero) {
+ ret |= softfloat_flag_infinite;
+ }
+ if (qflags & float_flag_overflow) {
+ ret |= softfloat_flag_overflow;
+ }
+ if (qflags & float_flag_underflow) {
+ ret |= softfloat_flag_underflow;
+ }
+ if (qflags & float_flag_inexact) {
+ ret |= softfloat_flag_inexact;
+ }
+ return ret;
+}
+
+/*
+ * floatx80 and float128 cannot be cast between qemu and softfloat, because
+ * in softfloat the order of the fields depends on the host's endianness.
+ */
+static extFloat80_t qemu_to_soft80(floatx80 a)
+{
+ extFloat80_t ret;
+
+ ret.signif = a.low;
+ ret.signExp = a.high;
+ return ret;
+}
+
+static floatx80 soft_to_qemu80(extFloat80_t a)
+{
+ floatx80 ret;
+
+ ret.low = a.signif;
+ ret.high = a.signExp;
+ return ret;
+}
+
+static float128_t qemu_to_soft128(float128 a)
+{
+ float128_t ret;
+ struct uint128 *to = (struct uint128 *)&ret;
+
+ to->v0 = a.low;
+ to->v64 = a.high;
+ return ret;
+}
+
+static float128 soft_to_qemu128(float128_t a)
+{
+ struct uint128 *from = (struct uint128 *)&a;
+ float128 ret;
+
+ ret.low = from->v0;
+ ret.high = from->v64;
+ return ret;
+}
+
+/* conversions */
+#define WRAP_SF_TO_SF_IEEE(name, func, a_type, b_type) \
+ static b_type##_t name(a_type##_t a) \
+ { \
+ a_type *ap = (a_type *)&a; \
+ b_type ret; \
+ \
+ ret = func(*ap, true, &qsf); \
+ return *(b_type##_t *)&ret; \
+ }
+
+WRAP_SF_TO_SF_IEEE(qemu_f16_to_f32, float16_to_float32, float16, float32)
+WRAP_SF_TO_SF_IEEE(qemu_f16_to_f64, float16_to_float64, float16, float64)
+
+WRAP_SF_TO_SF_IEEE(qemu_f32_to_f16, float32_to_float16, float32, float16)
+WRAP_SF_TO_SF_IEEE(qemu_f64_to_f16, float64_to_float16, float64, float16)
+#undef WRAP_SF_TO_SF_IEEE
+
+#define WRAP_SF_TO_SF(name, func, a_type, b_type) \
+ static b_type##_t name(a_type##_t a) \
+ { \
+ a_type *ap = (a_type *)&a; \
+ b_type ret; \
+ \
+ ret = func(*ap, &qsf); \
+ return *(b_type##_t *)&ret; \
+ }
+
+WRAP_SF_TO_SF(qemu_f32_to_f64, float32_to_float64, float32, float64)
+WRAP_SF_TO_SF(qemu_f64_to_f32, float64_to_float32, float64, float32)
+#undef WRAP_SF_TO_SF
+
+#define WRAP_SF_TO_80(name, func, type) \
+ static void name(type##_t a, extFloat80_t *res) \
+ { \
+ floatx80 ret; \
+ type *ap = (type *)&a; \
+ \
+ ret = func(*ap, &qsf); \
+ *res = qemu_to_soft80(ret); \
+ }
+
+WRAP_SF_TO_80(qemu_f32_to_extF80M, float32_to_floatx80, float32)
+WRAP_SF_TO_80(qemu_f64_to_extF80M, float64_to_floatx80, float64)
+#undef WRAP_SF_TO_80
+
+#define WRAP_SF_TO_128(name, func, type) \
+ static void name(type##_t a, float128_t *res) \
+ { \
+ float128 ret; \
+ type *ap = (type *)&a; \
+ \
+ ret = func(*ap, &qsf); \
+ *res = qemu_to_soft128(ret); \
+ }
+
+WRAP_SF_TO_128(qemu_f32_to_f128M, float32_to_float128, float32)
+WRAP_SF_TO_128(qemu_f64_to_f128M, float64_to_float128, float64)
+#undef WRAP_SF_TO_128
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_SF_TO_INT(name, func, type, fast_type) \
+ static fast_type name(type##_t a, uint_fast8_t round, bool exact) \
+ { \
+ type *ap = (type *)&a; \
+ \
+ qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
+ return func(*ap, &qsf); \
+ }
+
+WRAP_SF_TO_INT(qemu_f16_to_ui32, float16_to_uint32, float16, uint_fast32_t)
+WRAP_SF_TO_INT(qemu_f16_to_ui64, float16_to_uint64, float16, uint_fast64_t)
+
+WRAP_SF_TO_INT(qemu_f32_to_ui32, float32_to_uint32, float32, uint_fast32_t)
+WRAP_SF_TO_INT(qemu_f32_to_ui64, float32_to_uint64, float32, uint_fast64_t)
+
+WRAP_SF_TO_INT(qemu_f64_to_ui32, float64_to_uint32, float64, uint_fast32_t)
+WRAP_SF_TO_INT(qemu_f64_to_ui64, float64_to_uint64, float64, uint_fast64_t)
+
+WRAP_SF_TO_INT(qemu_f16_to_i32, float16_to_int32, float16, int_fast32_t)
+WRAP_SF_TO_INT(qemu_f16_to_i64, float16_to_int64, float16, int_fast64_t)
+
+WRAP_SF_TO_INT(qemu_f32_to_i32, float32_to_int32, float32, int_fast32_t)
+WRAP_SF_TO_INT(qemu_f32_to_i64, float32_to_int64, float32, int_fast64_t)
+
+WRAP_SF_TO_INT(qemu_f64_to_i32, float64_to_int32, float64, int_fast32_t)
+WRAP_SF_TO_INT(qemu_f64_to_i64, float64_to_int64, float64, int_fast64_t)
+#undef WRAP_SF_TO_INT
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_SF_TO_INT_MINMAG(name, func, type, fast_type) \
+ static fast_type name(type##_t a, bool exact) \
+ { \
+ type *ap = (type *)&a; \
+ \
+ return func(*ap, &qsf); \
+ }
+
+WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui32_r_minMag,
+ float16_to_uint32_round_to_zero, float16, uint_fast32_t)
+WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui64_r_minMag,
+ float16_to_uint64_round_to_zero, float16, uint_fast64_t)
+
+WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i32_r_minMag,
+ float16_to_int32_round_to_zero, float16, int_fast32_t)
+WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i64_r_minMag,
+ float16_to_int64_round_to_zero, float16, int_fast64_t)
+
+WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui32_r_minMag,
+ float32_to_uint32_round_to_zero, float32, uint_fast32_t)
+WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui64_r_minMag,
+ float32_to_uint64_round_to_zero, float32, uint_fast64_t)
+
+WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i32_r_minMag,
+ float32_to_int32_round_to_zero, float32, int_fast32_t)
+WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i64_r_minMag,
+ float32_to_int64_round_to_zero, float32, int_fast64_t)
+
+WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui32_r_minMag,
+ float64_to_uint32_round_to_zero, float64, uint_fast32_t)
+WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui64_r_minMag,
+ float64_to_uint64_round_to_zero, float64, uint_fast64_t)
+
+WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i32_r_minMag,
+ float64_to_int32_round_to_zero, float64, int_fast32_t)
+WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i64_r_minMag,
+ float64_to_int64_round_to_zero, float64, int_fast64_t)
+#undef WRAP_SF_TO_INT_MINMAG
+
+#define WRAP_80_TO_SF(name, func, type) \
+ static type##_t name(const extFloat80_t *ap) \
+ { \
+ floatx80 a; \
+ type ret; \
+ \
+ a = soft_to_qemu80(*ap); \
+ ret = func(a, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+WRAP_80_TO_SF(qemu_extF80M_to_f32, floatx80_to_float32, float32)
+WRAP_80_TO_SF(qemu_extF80M_to_f64, floatx80_to_float64, float64)
+#undef WRAP_80_TO_SF
+
+#define WRAP_128_TO_SF(name, func, type) \
+ static type##_t name(const float128_t *ap) \
+ { \
+ float128 a; \
+ type ret; \
+ \
+ a = soft_to_qemu128(*ap); \
+ ret = func(a, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+WRAP_128_TO_SF(qemu_f128M_to_f32, float128_to_float32, float32)
+WRAP_128_TO_SF(qemu_f128M_to_f64, float128_to_float64, float64)
+#undef WRAP_128_TO_SF
+
+static void qemu_extF80M_to_f128M(const extFloat80_t *from, float128_t *to)
+{
+ floatx80 qfrom;
+ float128 qto;
+
+ qfrom = soft_to_qemu80(*from);
+ qto = floatx80_to_float128(qfrom, &qsf);
+ *to = qemu_to_soft128(qto);
+}
+
+static void qemu_f128M_to_extF80M(const float128_t *from, extFloat80_t *to)
+{
+ float128 qfrom;
+ floatx80 qto;
+
+ qfrom = soft_to_qemu128(*from);
+ qto = float128_to_floatx80(qfrom, &qsf);
+ *to = qemu_to_soft80(qto);
+}
+
+#define WRAP_INT_TO_SF(name, func, int_type, type) \
+ static type##_t name(int_type a) \
+ { \
+ type ret; \
+ \
+ ret = func(a, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+WRAP_INT_TO_SF(qemu_ui32_to_f16, uint32_to_float16, uint32_t, float16)
+WRAP_INT_TO_SF(qemu_ui32_to_f32, uint32_to_float32, uint32_t, float32)
+WRAP_INT_TO_SF(qemu_ui32_to_f64, uint32_to_float64, uint32_t, float64)
+
+WRAP_INT_TO_SF(qemu_ui64_to_f16, uint64_to_float16, uint64_t, float16)
+WRAP_INT_TO_SF(qemu_ui64_to_f32, uint64_to_float32, uint64_t, float32)
+WRAP_INT_TO_SF(qemu_ui64_to_f64, uint64_to_float64, uint64_t, float64)
+
+WRAP_INT_TO_SF(qemu_i32_to_f16, int32_to_float16, int32_t, float16)
+WRAP_INT_TO_SF(qemu_i32_to_f32, int32_to_float32, int32_t, float32)
+WRAP_INT_TO_SF(qemu_i32_to_f64, int32_to_float64, int32_t, float64)
+
+WRAP_INT_TO_SF(qemu_i64_to_f16, int64_to_float16, int64_t, float16)
+WRAP_INT_TO_SF(qemu_i64_to_f32, int64_to_float32, int64_t, float32)
+WRAP_INT_TO_SF(qemu_i64_to_f64, int64_to_float64, int64_t, float64)
+#undef WRAP_INT_TO_SF
+
+#define WRAP_INT_TO_80(name, func, int_type) \
+ static void name(int_type a, extFloat80_t *res) \
+ { \
+ floatx80 ret; \
+ \
+ ret = func(a, &qsf); \
+ *res = qemu_to_soft80(ret); \
+ }
+
+WRAP_INT_TO_80(qemu_i32_to_extF80M, int32_to_floatx80, int32_t)
+WRAP_INT_TO_80(qemu_i64_to_extF80M, int64_to_floatx80, int64_t)
+#undef WRAP_INT_TO_80
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_80_TO_INT(name, func, fast_type) \
+ static fast_type name(const extFloat80_t *ap, uint_fast8_t round, \
+ bool exact) \
+ { \
+ floatx80 a; \
+ \
+ a = soft_to_qemu80(*ap); \
+ qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
+ return func(a, &qsf); \
+ }
+
+WRAP_80_TO_INT(qemu_extF80M_to_i32, floatx80_to_int32, int_fast32_t)
+WRAP_80_TO_INT(qemu_extF80M_to_i64, floatx80_to_int64, int_fast64_t)
+#undef WRAP_80_TO_INT
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_80_TO_INT_MINMAG(name, func, fast_type) \
+ static fast_type name(const extFloat80_t *ap, bool exact) \
+ { \
+ floatx80 a; \
+ \
+ a = soft_to_qemu80(*ap); \
+ return func(a, &qsf); \
+ }
+
+WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i32_r_minMag,
+ floatx80_to_int32_round_to_zero, int_fast32_t)
+WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i64_r_minMag,
+ floatx80_to_int64_round_to_zero, int_fast64_t)
+#undef WRAP_80_TO_INT_MINMAG
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_128_TO_INT(name, func, fast_type) \
+ static fast_type name(const float128_t *ap, uint_fast8_t round, \
+ bool exact) \
+ { \
+ float128 a; \
+ \
+ a = soft_to_qemu128(*ap); \
+ qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
+ return func(a, &qsf); \
+ }
+
+WRAP_128_TO_INT(qemu_f128M_to_i32, float128_to_int32, int_fast32_t)
+WRAP_128_TO_INT(qemu_f128M_to_i64, float128_to_int64, int_fast64_t)
+
+WRAP_128_TO_INT(qemu_f128M_to_ui32, float128_to_uint32, uint_fast32_t)
+WRAP_128_TO_INT(qemu_f128M_to_ui64, float128_to_uint64, uint_fast64_t)
+#undef WRAP_128_TO_INT
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_128_TO_INT_MINMAG(name, func, fast_type) \
+ static fast_type name(const float128_t *ap, bool exact) \
+ { \
+ float128 a; \
+ \
+ a = soft_to_qemu128(*ap); \
+ return func(a, &qsf); \
+ }
+
+WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i32_r_minMag,
+ float128_to_int32_round_to_zero, int_fast32_t)
+WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i64_r_minMag,
+ float128_to_int64_round_to_zero, int_fast64_t)
+
+WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui32_r_minMag,
+ float128_to_uint32_round_to_zero, uint_fast32_t)
+WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui64_r_minMag,
+ float128_to_uint64_round_to_zero, uint_fast64_t)
+#undef WRAP_128_TO_INT_MINMAG
+
+#define WRAP_INT_TO_128(name, func, int_type) \
+ static void name(int_type a, float128_t *res) \
+ { \
+ float128 ret; \
+ \
+ ret = func(a, &qsf); \
+ *res = qemu_to_soft128(ret); \
+ }
+
+WRAP_INT_TO_128(qemu_ui64_to_f128M, uint64_to_float128, uint64_t)
+
+WRAP_INT_TO_128(qemu_i32_to_f128M, int32_to_float128, int32_t)
+WRAP_INT_TO_128(qemu_i64_to_f128M, int64_to_float128, int64_t)
+#undef WRAP_INT_TO_128
+
+/* Note: exact is ignored since qemu's softfloat assumes it is set */
+#define WRAP_ROUND_TO_INT(name, func, type) \
+ static type##_t name(type##_t a, uint_fast8_t round, bool exact) \
+ { \
+ type *ap = (type *)&a; \
+ type ret; \
+ \
+ qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
+ ret = func(*ap, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+WRAP_ROUND_TO_INT(qemu_f16_roundToInt, float16_round_to_int, float16)
+WRAP_ROUND_TO_INT(qemu_f32_roundToInt, float32_round_to_int, float32)
+WRAP_ROUND_TO_INT(qemu_f64_roundToInt, float64_round_to_int, float64)
+#undef WRAP_ROUND_TO_INT
+
+static void qemu_extF80M_roundToInt(const extFloat80_t *ap, uint_fast8_t round,
+ bool exact, extFloat80_t *res)
+{
+ floatx80 a;
+ floatx80 ret;
+
+ a = soft_to_qemu80(*ap);
+ qsf.float_rounding_mode = sf_rounding_to_qemu(round);
+ ret = floatx80_round_to_int(a, &qsf);
+ *res = qemu_to_soft80(ret);
+}
+
+static void qemu_f128M_roundToInt(const float128_t *ap, uint_fast8_t round,
+ bool exact, float128_t *res)
+{
+ float128 a;
+ float128 ret;
+
+ a = soft_to_qemu128(*ap);
+ qsf.float_rounding_mode = sf_rounding_to_qemu(round);
+ ret = float128_round_to_int(a, &qsf);
+ *res = qemu_to_soft128(ret);
+}
+
+/* operations */
+#define WRAP1(name, func, type) \
+ static type##_t name(type##_t a) \
+ { \
+ type *ap = (type *)&a; \
+ type ret; \
+ \
+ ret = func(*ap, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+#define WRAP2(name, func, type) \
+ static type##_t name(type##_t a, type##_t b) \
+ { \
+ type *ap = (type *)&a; \
+ type *bp = (type *)&b; \
+ type ret; \
+ \
+ ret = func(*ap, *bp, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+#define WRAP_COMMON_OPS(b) \
+ WRAP1(qemu_f##b##_sqrt, float##b##_sqrt, float##b) \
+ WRAP2(qemu_f##b##_add, float##b##_add, float##b) \
+ WRAP2(qemu_f##b##_sub, float##b##_sub, float##b) \
+ WRAP2(qemu_f##b##_mul, float##b##_mul, float##b) \
+ WRAP2(qemu_f##b##_div, float##b##_div, float##b)
+
+WRAP_COMMON_OPS(16)
+WRAP_COMMON_OPS(32)
+WRAP_COMMON_OPS(64)
+#undef WRAP_COMMON
+
+WRAP2(qemu_f32_rem, float32_rem, float32)
+WRAP2(qemu_f64_rem, float64_rem, float64)
+#undef WRAP2
+#undef WRAP1
+
+#define WRAP1_80(name, func) \
+ static void name(const extFloat80_t *ap, extFloat80_t *res) \
+ { \
+ floatx80 a; \
+ floatx80 ret; \
+ \
+ a = soft_to_qemu80(*ap); \
+ ret = func(a, &qsf); \
+ *res = qemu_to_soft80(ret); \
+ }
+
+WRAP1_80(qemu_extF80M_sqrt, floatx80_sqrt)
+#undef WRAP1_80
+
+#define WRAP1_128(name, func) \
+ static void name(const float128_t *ap, float128_t *res) \
+ { \
+ float128 a; \
+ float128 ret; \
+ \
+ a = soft_to_qemu128(*ap); \
+ ret = func(a, &qsf); \
+ *res = qemu_to_soft128(ret); \
+ }
+
+WRAP1_128(qemu_f128M_sqrt, float128_sqrt)
+#undef WRAP1_128
+
+#define WRAP2_80(name, func) \
+ static void name(const extFloat80_t *ap, const extFloat80_t *bp, \
+ extFloat80_t *res) \
+ { \
+ floatx80 a; \
+ floatx80 b; \
+ floatx80 ret; \
+ \
+ a = soft_to_qemu80(*ap); \
+ b = soft_to_qemu80(*bp); \
+ ret = func(a, b, &qsf); \
+ *res = qemu_to_soft80(ret); \
+ }
+
+WRAP2_80(qemu_extF80M_add, floatx80_add)
+WRAP2_80(qemu_extF80M_sub, floatx80_sub)
+WRAP2_80(qemu_extF80M_mul, floatx80_mul)
+WRAP2_80(qemu_extF80M_div, floatx80_div)
+WRAP2_80(qemu_extF80M_rem, floatx80_rem)
+#undef WRAP2_80
+
+#define WRAP2_128(name, func) \
+ static void name(const float128_t *ap, const float128_t *bp, \
+ float128_t *res) \
+ { \
+ float128 a; \
+ float128 b; \
+ float128 ret; \
+ \
+ a = soft_to_qemu128(*ap); \
+ b = soft_to_qemu128(*bp); \
+ ret = func(a, b, &qsf); \
+ *res = qemu_to_soft128(ret); \
+ }
+
+WRAP2_128(qemu_f128M_add, float128_add)
+WRAP2_128(qemu_f128M_sub, float128_sub)
+WRAP2_128(qemu_f128M_mul, float128_mul)
+WRAP2_128(qemu_f128M_div, float128_div)
+WRAP2_128(qemu_f128M_rem, float128_rem)
+#undef WRAP2_128
+
+#define WRAP_MULADD(name, func, type) \
+ static type##_t name(type##_t a, type##_t b, type##_t c) \
+ { \
+ type *ap = (type *)&a; \
+ type *bp = (type *)&b; \
+ type *cp = (type *)&c; \
+ type ret; \
+ \
+ ret = func(*ap, *bp, *cp, 0, &qsf); \
+ return *(type##_t *)&ret; \
+ }
+
+WRAP_MULADD(qemu_f16_mulAdd, float16_muladd, float16)
+WRAP_MULADD(qemu_f32_mulAdd, float32_muladd, float32)
+WRAP_MULADD(qemu_f64_mulAdd, float64_muladd, float64)
+#undef WRAP_MULADD
+
+#define WRAP_CMP16(name, func, retcond) \
+ static bool name(float16_t a, float16_t b) \
+ { \
+ float16 *ap = (float16 *)&a; \
+ float16 *bp = (float16 *)&b; \
+ int ret; \
+ \
+ ret = func(*ap, *bp, &qsf); \
+ return retcond; \
+ }
+
+WRAP_CMP16(qemu_f16_eq_signaling, float16_compare, ret == 0)
+WRAP_CMP16(qemu_f16_eq, float16_compare_quiet, ret == 0)
+WRAP_CMP16(qemu_f16_le, float16_compare, ret <= 0)
+WRAP_CMP16(qemu_f16_lt, float16_compare, ret < 0)
+WRAP_CMP16(qemu_f16_le_quiet, float16_compare_quiet, ret <= 0)
+WRAP_CMP16(qemu_f16_lt_quiet, float16_compare_quiet, ret < 0)
+#undef WRAP_CMP16
+
+#define WRAP_CMP(name, func, type) \
+ static bool name(type##_t a, type##_t b) \
+ { \
+ type *ap = (type *)&a; \
+ type *bp = (type *)&b; \
+ \
+ return !!func(*ap, *bp, &qsf); \
+ }
+
+#define GEN_WRAP_CMP(b) \
+ WRAP_CMP(qemu_f##b##_eq_signaling, float##b##_eq, float##b) \
+ WRAP_CMP(qemu_f##b##_eq, float##b##_eq_quiet, float##b) \
+ WRAP_CMP(qemu_f##b##_le, float##b##_le, float##b) \
+ WRAP_CMP(qemu_f##b##_lt, float##b##_lt, float##b) \
+ WRAP_CMP(qemu_f##b##_le_quiet, float##b##_le_quiet, float##b) \
+ WRAP_CMP(qemu_f##b##_lt_quiet, float##b##_lt_quiet, float##b)
+
+GEN_WRAP_CMP(32)
+GEN_WRAP_CMP(64)
+#undef GEN_WRAP_CMP
+#undef WRAP_CMP
+
+#define WRAP_CMP80(name, func) \
+ static bool name(const extFloat80_t *ap, const extFloat80_t *bp) \
+ { \
+ floatx80 a; \
+ floatx80 b; \
+ \
+ a = soft_to_qemu80(*ap); \
+ b = soft_to_qemu80(*bp); \
+ return !!func(a, b, &qsf); \
+ }
+
+WRAP_CMP80(qemu_extF80M_eq_signaling, floatx80_eq)
+WRAP_CMP80(qemu_extF80M_eq, floatx80_eq_quiet)
+WRAP_CMP80(qemu_extF80M_le, floatx80_le)
+WRAP_CMP80(qemu_extF80M_lt, floatx80_lt)
+WRAP_CMP80(qemu_extF80M_le_quiet, floatx80_le_quiet)
+WRAP_CMP80(qemu_extF80M_lt_quiet, floatx80_le_quiet)
+#undef WRAP_CMP80
+
+#define WRAP_CMP128(name, func) \
+ static bool name(const float128_t *ap, const float128_t *bp) \
+ { \
+ float128 a; \
+ float128 b; \
+ \
+ a = soft_to_qemu128(*ap); \
+ b = soft_to_qemu128(*bp); \
+ return !!func(a, b, &qsf); \
+ }
+
+WRAP_CMP128(qemu_f128M_eq_signaling, float128_eq)
+WRAP_CMP128(qemu_f128M_eq, float128_eq_quiet)
+WRAP_CMP128(qemu_f128M_le, float128_le)
+WRAP_CMP128(qemu_f128M_lt, float128_lt)
+WRAP_CMP128(qemu_f128M_le_quiet, float128_le_quiet)
+WRAP_CMP128(qemu_f128M_lt_quiet, float128_lt_quiet)
+#undef WRAP_CMP128
+++ /dev/null
-/*
- * In this file we wrap QEMU FP functions to look like softfloat/testfloat's,
- * so that we can use the testfloat infrastructure as-is.
- *
- * This file must be included directly from fp-test.c. We could compile it
- * separately, but it would be tedious to add declarations for all the wrappers.
- */
-
-static signed char sf_tininess_to_qemu(uint_fast8_t mode)
-{
- switch (mode) {
- case softfloat_tininess_beforeRounding:
- return float_tininess_before_rounding;
- case softfloat_tininess_afterRounding:
- return float_tininess_after_rounding;
- default:
- g_assert_not_reached();
- }
-}
-
-static signed char sf_rounding_to_qemu(uint_fast8_t mode)
-{
- switch (mode) {
- case softfloat_round_near_even:
- return float_round_nearest_even;
- case softfloat_round_minMag:
- return float_round_to_zero;
- case softfloat_round_min:
- return float_round_down;
- case softfloat_round_max:
- return float_round_up;
- case softfloat_round_near_maxMag:
- return float_round_ties_away;
- case softfloat_round_odd:
- return float_round_to_odd;
- default:
- g_assert_not_reached();
- }
-}
-
-static uint_fast8_t qemu_flags_to_sf(uint8_t qflags)
-{
- uint_fast8_t ret = 0;
-
- if (qflags & float_flag_invalid) {
- ret |= softfloat_flag_invalid;
- }
- if (qflags & float_flag_divbyzero) {
- ret |= softfloat_flag_infinite;
- }
- if (qflags & float_flag_overflow) {
- ret |= softfloat_flag_overflow;
- }
- if (qflags & float_flag_underflow) {
- ret |= softfloat_flag_underflow;
- }
- if (qflags & float_flag_inexact) {
- ret |= softfloat_flag_inexact;
- }
- return ret;
-}
-
-/*
- * floatx80 and float128 cannot be cast between qemu and softfloat, because
- * in softfloat the order of the fields depends on the host's endianness.
- */
-static extFloat80_t qemu_to_soft80(floatx80 a)
-{
- extFloat80_t ret;
-
- ret.signif = a.low;
- ret.signExp = a.high;
- return ret;
-}
-
-static floatx80 soft_to_qemu80(extFloat80_t a)
-{
- floatx80 ret;
-
- ret.low = a.signif;
- ret.high = a.signExp;
- return ret;
-}
-
-static float128_t qemu_to_soft128(float128 a)
-{
- float128_t ret;
- struct uint128 *to = (struct uint128 *)&ret;
-
- to->v0 = a.low;
- to->v64 = a.high;
- return ret;
-}
-
-static float128 soft_to_qemu128(float128_t a)
-{
- struct uint128 *from = (struct uint128 *)&a;
- float128 ret;
-
- ret.low = from->v0;
- ret.high = from->v64;
- return ret;
-}
-
-/* conversions */
-#define WRAP_SF_TO_SF_IEEE(name, func, a_type, b_type) \
- static b_type##_t name(a_type##_t a) \
- { \
- a_type *ap = (a_type *)&a; \
- b_type ret; \
- \
- ret = func(*ap, true, &qsf); \
- return *(b_type##_t *)&ret; \
- }
-
-WRAP_SF_TO_SF_IEEE(qemu_f16_to_f32, float16_to_float32, float16, float32)
-WRAP_SF_TO_SF_IEEE(qemu_f16_to_f64, float16_to_float64, float16, float64)
-
-WRAP_SF_TO_SF_IEEE(qemu_f32_to_f16, float32_to_float16, float32, float16)
-WRAP_SF_TO_SF_IEEE(qemu_f64_to_f16, float64_to_float16, float64, float16)
-#undef WRAP_SF_TO_SF_IEEE
-
-#define WRAP_SF_TO_SF(name, func, a_type, b_type) \
- static b_type##_t name(a_type##_t a) \
- { \
- a_type *ap = (a_type *)&a; \
- b_type ret; \
- \
- ret = func(*ap, &qsf); \
- return *(b_type##_t *)&ret; \
- }
-
-WRAP_SF_TO_SF(qemu_f32_to_f64, float32_to_float64, float32, float64)
-WRAP_SF_TO_SF(qemu_f64_to_f32, float64_to_float32, float64, float32)
-#undef WRAP_SF_TO_SF
-
-#define WRAP_SF_TO_80(name, func, type) \
- static void name(type##_t a, extFloat80_t *res) \
- { \
- floatx80 ret; \
- type *ap = (type *)&a; \
- \
- ret = func(*ap, &qsf); \
- *res = qemu_to_soft80(ret); \
- }
-
-WRAP_SF_TO_80(qemu_f32_to_extF80M, float32_to_floatx80, float32)
-WRAP_SF_TO_80(qemu_f64_to_extF80M, float64_to_floatx80, float64)
-#undef WRAP_SF_TO_80
-
-#define WRAP_SF_TO_128(name, func, type) \
- static void name(type##_t a, float128_t *res) \
- { \
- float128 ret; \
- type *ap = (type *)&a; \
- \
- ret = func(*ap, &qsf); \
- *res = qemu_to_soft128(ret); \
- }
-
-WRAP_SF_TO_128(qemu_f32_to_f128M, float32_to_float128, float32)
-WRAP_SF_TO_128(qemu_f64_to_f128M, float64_to_float128, float64)
-#undef WRAP_SF_TO_128
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_SF_TO_INT(name, func, type, fast_type) \
- static fast_type name(type##_t a, uint_fast8_t round, bool exact) \
- { \
- type *ap = (type *)&a; \
- \
- qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
- return func(*ap, &qsf); \
- }
-
-WRAP_SF_TO_INT(qemu_f16_to_ui32, float16_to_uint32, float16, uint_fast32_t)
-WRAP_SF_TO_INT(qemu_f16_to_ui64, float16_to_uint64, float16, uint_fast64_t)
-
-WRAP_SF_TO_INT(qemu_f32_to_ui32, float32_to_uint32, float32, uint_fast32_t)
-WRAP_SF_TO_INT(qemu_f32_to_ui64, float32_to_uint64, float32, uint_fast64_t)
-
-WRAP_SF_TO_INT(qemu_f64_to_ui32, float64_to_uint32, float64, uint_fast32_t)
-WRAP_SF_TO_INT(qemu_f64_to_ui64, float64_to_uint64, float64, uint_fast64_t)
-
-WRAP_SF_TO_INT(qemu_f16_to_i32, float16_to_int32, float16, int_fast32_t)
-WRAP_SF_TO_INT(qemu_f16_to_i64, float16_to_int64, float16, int_fast64_t)
-
-WRAP_SF_TO_INT(qemu_f32_to_i32, float32_to_int32, float32, int_fast32_t)
-WRAP_SF_TO_INT(qemu_f32_to_i64, float32_to_int64, float32, int_fast64_t)
-
-WRAP_SF_TO_INT(qemu_f64_to_i32, float64_to_int32, float64, int_fast32_t)
-WRAP_SF_TO_INT(qemu_f64_to_i64, float64_to_int64, float64, int_fast64_t)
-#undef WRAP_SF_TO_INT
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_SF_TO_INT_MINMAG(name, func, type, fast_type) \
- static fast_type name(type##_t a, bool exact) \
- { \
- type *ap = (type *)&a; \
- \
- return func(*ap, &qsf); \
- }
-
-WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui32_r_minMag,
- float16_to_uint32_round_to_zero, float16, uint_fast32_t)
-WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui64_r_minMag,
- float16_to_uint64_round_to_zero, float16, uint_fast64_t)
-
-WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i32_r_minMag,
- float16_to_int32_round_to_zero, float16, int_fast32_t)
-WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i64_r_minMag,
- float16_to_int64_round_to_zero, float16, int_fast64_t)
-
-WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui32_r_minMag,
- float32_to_uint32_round_to_zero, float32, uint_fast32_t)
-WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui64_r_minMag,
- float32_to_uint64_round_to_zero, float32, uint_fast64_t)
-
-WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i32_r_minMag,
- float32_to_int32_round_to_zero, float32, int_fast32_t)
-WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i64_r_minMag,
- float32_to_int64_round_to_zero, float32, int_fast64_t)
-
-WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui32_r_minMag,
- float64_to_uint32_round_to_zero, float64, uint_fast32_t)
-WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui64_r_minMag,
- float64_to_uint64_round_to_zero, float64, uint_fast64_t)
-
-WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i32_r_minMag,
- float64_to_int32_round_to_zero, float64, int_fast32_t)
-WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i64_r_minMag,
- float64_to_int64_round_to_zero, float64, int_fast64_t)
-#undef WRAP_SF_TO_INT_MINMAG
-
-#define WRAP_80_TO_SF(name, func, type) \
- static type##_t name(const extFloat80_t *ap) \
- { \
- floatx80 a; \
- type ret; \
- \
- a = soft_to_qemu80(*ap); \
- ret = func(a, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-WRAP_80_TO_SF(qemu_extF80M_to_f32, floatx80_to_float32, float32)
-WRAP_80_TO_SF(qemu_extF80M_to_f64, floatx80_to_float64, float64)
-#undef WRAP_80_TO_SF
-
-#define WRAP_128_TO_SF(name, func, type) \
- static type##_t name(const float128_t *ap) \
- { \
- float128 a; \
- type ret; \
- \
- a = soft_to_qemu128(*ap); \
- ret = func(a, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-WRAP_128_TO_SF(qemu_f128M_to_f32, float128_to_float32, float32)
-WRAP_128_TO_SF(qemu_f128M_to_f64, float128_to_float64, float64)
-#undef WRAP_128_TO_SF
-
-static void qemu_extF80M_to_f128M(const extFloat80_t *from, float128_t *to)
-{
- floatx80 qfrom;
- float128 qto;
-
- qfrom = soft_to_qemu80(*from);
- qto = floatx80_to_float128(qfrom, &qsf);
- *to = qemu_to_soft128(qto);
-}
-
-static void qemu_f128M_to_extF80M(const float128_t *from, extFloat80_t *to)
-{
- float128 qfrom;
- floatx80 qto;
-
- qfrom = soft_to_qemu128(*from);
- qto = float128_to_floatx80(qfrom, &qsf);
- *to = qemu_to_soft80(qto);
-}
-
-#define WRAP_INT_TO_SF(name, func, int_type, type) \
- static type##_t name(int_type a) \
- { \
- type ret; \
- \
- ret = func(a, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-WRAP_INT_TO_SF(qemu_ui32_to_f16, uint32_to_float16, uint32_t, float16)
-WRAP_INT_TO_SF(qemu_ui32_to_f32, uint32_to_float32, uint32_t, float32)
-WRAP_INT_TO_SF(qemu_ui32_to_f64, uint32_to_float64, uint32_t, float64)
-
-WRAP_INT_TO_SF(qemu_ui64_to_f16, uint64_to_float16, uint64_t, float16)
-WRAP_INT_TO_SF(qemu_ui64_to_f32, uint64_to_float32, uint64_t, float32)
-WRAP_INT_TO_SF(qemu_ui64_to_f64, uint64_to_float64, uint64_t, float64)
-
-WRAP_INT_TO_SF(qemu_i32_to_f16, int32_to_float16, int32_t, float16)
-WRAP_INT_TO_SF(qemu_i32_to_f32, int32_to_float32, int32_t, float32)
-WRAP_INT_TO_SF(qemu_i32_to_f64, int32_to_float64, int32_t, float64)
-
-WRAP_INT_TO_SF(qemu_i64_to_f16, int64_to_float16, int64_t, float16)
-WRAP_INT_TO_SF(qemu_i64_to_f32, int64_to_float32, int64_t, float32)
-WRAP_INT_TO_SF(qemu_i64_to_f64, int64_to_float64, int64_t, float64)
-#undef WRAP_INT_TO_SF
-
-#define WRAP_INT_TO_80(name, func, int_type) \
- static void name(int_type a, extFloat80_t *res) \
- { \
- floatx80 ret; \
- \
- ret = func(a, &qsf); \
- *res = qemu_to_soft80(ret); \
- }
-
-WRAP_INT_TO_80(qemu_i32_to_extF80M, int32_to_floatx80, int32_t)
-WRAP_INT_TO_80(qemu_i64_to_extF80M, int64_to_floatx80, int64_t)
-#undef WRAP_INT_TO_80
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_80_TO_INT(name, func, fast_type) \
- static fast_type name(const extFloat80_t *ap, uint_fast8_t round, \
- bool exact) \
- { \
- floatx80 a; \
- \
- a = soft_to_qemu80(*ap); \
- qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
- return func(a, &qsf); \
- }
-
-WRAP_80_TO_INT(qemu_extF80M_to_i32, floatx80_to_int32, int_fast32_t)
-WRAP_80_TO_INT(qemu_extF80M_to_i64, floatx80_to_int64, int_fast64_t)
-#undef WRAP_80_TO_INT
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_80_TO_INT_MINMAG(name, func, fast_type) \
- static fast_type name(const extFloat80_t *ap, bool exact) \
- { \
- floatx80 a; \
- \
- a = soft_to_qemu80(*ap); \
- return func(a, &qsf); \
- }
-
-WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i32_r_minMag,
- floatx80_to_int32_round_to_zero, int_fast32_t)
-WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i64_r_minMag,
- floatx80_to_int64_round_to_zero, int_fast64_t)
-#undef WRAP_80_TO_INT_MINMAG
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_128_TO_INT(name, func, fast_type) \
- static fast_type name(const float128_t *ap, uint_fast8_t round, \
- bool exact) \
- { \
- float128 a; \
- \
- a = soft_to_qemu128(*ap); \
- qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
- return func(a, &qsf); \
- }
-
-WRAP_128_TO_INT(qemu_f128M_to_i32, float128_to_int32, int_fast32_t)
-WRAP_128_TO_INT(qemu_f128M_to_i64, float128_to_int64, int_fast64_t)
-
-WRAP_128_TO_INT(qemu_f128M_to_ui32, float128_to_uint32, uint_fast32_t)
-WRAP_128_TO_INT(qemu_f128M_to_ui64, float128_to_uint64, uint_fast64_t)
-#undef WRAP_128_TO_INT
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_128_TO_INT_MINMAG(name, func, fast_type) \
- static fast_type name(const float128_t *ap, bool exact) \
- { \
- float128 a; \
- \
- a = soft_to_qemu128(*ap); \
- return func(a, &qsf); \
- }
-
-WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i32_r_minMag,
- float128_to_int32_round_to_zero, int_fast32_t)
-WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i64_r_minMag,
- float128_to_int64_round_to_zero, int_fast64_t)
-
-WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui32_r_minMag,
- float128_to_uint32_round_to_zero, uint_fast32_t)
-WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui64_r_minMag,
- float128_to_uint64_round_to_zero, uint_fast64_t)
-#undef WRAP_128_TO_INT_MINMAG
-
-#define WRAP_INT_TO_128(name, func, int_type) \
- static void name(int_type a, float128_t *res) \
- { \
- float128 ret; \
- \
- ret = func(a, &qsf); \
- *res = qemu_to_soft128(ret); \
- }
-
-WRAP_INT_TO_128(qemu_ui64_to_f128M, uint64_to_float128, uint64_t)
-
-WRAP_INT_TO_128(qemu_i32_to_f128M, int32_to_float128, int32_t)
-WRAP_INT_TO_128(qemu_i64_to_f128M, int64_to_float128, int64_t)
-#undef WRAP_INT_TO_128
-
-/* Note: exact is ignored since qemu's softfloat assumes it is set */
-#define WRAP_ROUND_TO_INT(name, func, type) \
- static type##_t name(type##_t a, uint_fast8_t round, bool exact) \
- { \
- type *ap = (type *)&a; \
- type ret; \
- \
- qsf.float_rounding_mode = sf_rounding_to_qemu(round); \
- ret = func(*ap, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-WRAP_ROUND_TO_INT(qemu_f16_roundToInt, float16_round_to_int, float16)
-WRAP_ROUND_TO_INT(qemu_f32_roundToInt, float32_round_to_int, float32)
-WRAP_ROUND_TO_INT(qemu_f64_roundToInt, float64_round_to_int, float64)
-#undef WRAP_ROUND_TO_INT
-
-static void qemu_extF80M_roundToInt(const extFloat80_t *ap, uint_fast8_t round,
- bool exact, extFloat80_t *res)
-{
- floatx80 a;
- floatx80 ret;
-
- a = soft_to_qemu80(*ap);
- qsf.float_rounding_mode = sf_rounding_to_qemu(round);
- ret = floatx80_round_to_int(a, &qsf);
- *res = qemu_to_soft80(ret);
-}
-
-static void qemu_f128M_roundToInt(const float128_t *ap, uint_fast8_t round,
- bool exact, float128_t *res)
-{
- float128 a;
- float128 ret;
-
- a = soft_to_qemu128(*ap);
- qsf.float_rounding_mode = sf_rounding_to_qemu(round);
- ret = float128_round_to_int(a, &qsf);
- *res = qemu_to_soft128(ret);
-}
-
-/* operations */
-#define WRAP1(name, func, type) \
- static type##_t name(type##_t a) \
- { \
- type *ap = (type *)&a; \
- type ret; \
- \
- ret = func(*ap, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-#define WRAP2(name, func, type) \
- static type##_t name(type##_t a, type##_t b) \
- { \
- type *ap = (type *)&a; \
- type *bp = (type *)&b; \
- type ret; \
- \
- ret = func(*ap, *bp, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-#define WRAP_COMMON_OPS(b) \
- WRAP1(qemu_f##b##_sqrt, float##b##_sqrt, float##b) \
- WRAP2(qemu_f##b##_add, float##b##_add, float##b) \
- WRAP2(qemu_f##b##_sub, float##b##_sub, float##b) \
- WRAP2(qemu_f##b##_mul, float##b##_mul, float##b) \
- WRAP2(qemu_f##b##_div, float##b##_div, float##b)
-
-WRAP_COMMON_OPS(16)
-WRAP_COMMON_OPS(32)
-WRAP_COMMON_OPS(64)
-#undef WRAP_COMMON
-
-WRAP2(qemu_f32_rem, float32_rem, float32)
-WRAP2(qemu_f64_rem, float64_rem, float64)
-#undef WRAP2
-#undef WRAP1
-
-#define WRAP1_80(name, func) \
- static void name(const extFloat80_t *ap, extFloat80_t *res) \
- { \
- floatx80 a; \
- floatx80 ret; \
- \
- a = soft_to_qemu80(*ap); \
- ret = func(a, &qsf); \
- *res = qemu_to_soft80(ret); \
- }
-
-WRAP1_80(qemu_extF80M_sqrt, floatx80_sqrt)
-#undef WRAP1_80
-
-#define WRAP1_128(name, func) \
- static void name(const float128_t *ap, float128_t *res) \
- { \
- float128 a; \
- float128 ret; \
- \
- a = soft_to_qemu128(*ap); \
- ret = func(a, &qsf); \
- *res = qemu_to_soft128(ret); \
- }
-
-WRAP1_128(qemu_f128M_sqrt, float128_sqrt)
-#undef WRAP1_128
-
-#define WRAP2_80(name, func) \
- static void name(const extFloat80_t *ap, const extFloat80_t *bp, \
- extFloat80_t *res) \
- { \
- floatx80 a; \
- floatx80 b; \
- floatx80 ret; \
- \
- a = soft_to_qemu80(*ap); \
- b = soft_to_qemu80(*bp); \
- ret = func(a, b, &qsf); \
- *res = qemu_to_soft80(ret); \
- }
-
-WRAP2_80(qemu_extF80M_add, floatx80_add)
-WRAP2_80(qemu_extF80M_sub, floatx80_sub)
-WRAP2_80(qemu_extF80M_mul, floatx80_mul)
-WRAP2_80(qemu_extF80M_div, floatx80_div)
-WRAP2_80(qemu_extF80M_rem, floatx80_rem)
-#undef WRAP2_80
-
-#define WRAP2_128(name, func) \
- static void name(const float128_t *ap, const float128_t *bp, \
- float128_t *res) \
- { \
- float128 a; \
- float128 b; \
- float128 ret; \
- \
- a = soft_to_qemu128(*ap); \
- b = soft_to_qemu128(*bp); \
- ret = func(a, b, &qsf); \
- *res = qemu_to_soft128(ret); \
- }
-
-WRAP2_128(qemu_f128M_add, float128_add)
-WRAP2_128(qemu_f128M_sub, float128_sub)
-WRAP2_128(qemu_f128M_mul, float128_mul)
-WRAP2_128(qemu_f128M_div, float128_div)
-WRAP2_128(qemu_f128M_rem, float128_rem)
-#undef WRAP2_128
-
-#define WRAP_MULADD(name, func, type) \
- static type##_t name(type##_t a, type##_t b, type##_t c) \
- { \
- type *ap = (type *)&a; \
- type *bp = (type *)&b; \
- type *cp = (type *)&c; \
- type ret; \
- \
- ret = func(*ap, *bp, *cp, 0, &qsf); \
- return *(type##_t *)&ret; \
- }
-
-WRAP_MULADD(qemu_f16_mulAdd, float16_muladd, float16)
-WRAP_MULADD(qemu_f32_mulAdd, float32_muladd, float32)
-WRAP_MULADD(qemu_f64_mulAdd, float64_muladd, float64)
-#undef WRAP_MULADD
-
-#define WRAP_CMP16(name, func, retcond) \
- static bool name(float16_t a, float16_t b) \
- { \
- float16 *ap = (float16 *)&a; \
- float16 *bp = (float16 *)&b; \
- int ret; \
- \
- ret = func(*ap, *bp, &qsf); \
- return retcond; \
- }
-
-WRAP_CMP16(qemu_f16_eq_signaling, float16_compare, ret == 0)
-WRAP_CMP16(qemu_f16_eq, float16_compare_quiet, ret == 0)
-WRAP_CMP16(qemu_f16_le, float16_compare, ret <= 0)
-WRAP_CMP16(qemu_f16_lt, float16_compare, ret < 0)
-WRAP_CMP16(qemu_f16_le_quiet, float16_compare_quiet, ret <= 0)
-WRAP_CMP16(qemu_f16_lt_quiet, float16_compare_quiet, ret < 0)
-#undef WRAP_CMP16
-
-#define WRAP_CMP(name, func, type) \
- static bool name(type##_t a, type##_t b) \
- { \
- type *ap = (type *)&a; \
- type *bp = (type *)&b; \
- \
- return !!func(*ap, *bp, &qsf); \
- }
-
-#define GEN_WRAP_CMP(b) \
- WRAP_CMP(qemu_f##b##_eq_signaling, float##b##_eq, float##b) \
- WRAP_CMP(qemu_f##b##_eq, float##b##_eq_quiet, float##b) \
- WRAP_CMP(qemu_f##b##_le, float##b##_le, float##b) \
- WRAP_CMP(qemu_f##b##_lt, float##b##_lt, float##b) \
- WRAP_CMP(qemu_f##b##_le_quiet, float##b##_le_quiet, float##b) \
- WRAP_CMP(qemu_f##b##_lt_quiet, float##b##_lt_quiet, float##b)
-
-GEN_WRAP_CMP(32)
-GEN_WRAP_CMP(64)
-#undef GEN_WRAP_CMP
-#undef WRAP_CMP
-
-#define WRAP_CMP80(name, func) \
- static bool name(const extFloat80_t *ap, const extFloat80_t *bp) \
- { \
- floatx80 a; \
- floatx80 b; \
- \
- a = soft_to_qemu80(*ap); \
- b = soft_to_qemu80(*bp); \
- return !!func(a, b, &qsf); \
- }
-
-WRAP_CMP80(qemu_extF80M_eq_signaling, floatx80_eq)
-WRAP_CMP80(qemu_extF80M_eq, floatx80_eq_quiet)
-WRAP_CMP80(qemu_extF80M_le, floatx80_le)
-WRAP_CMP80(qemu_extF80M_lt, floatx80_lt)
-WRAP_CMP80(qemu_extF80M_le_quiet, floatx80_le_quiet)
-WRAP_CMP80(qemu_extF80M_lt_quiet, floatx80_le_quiet)
-#undef WRAP_CMP80
-
-#define WRAP_CMP128(name, func) \
- static bool name(const float128_t *ap, const float128_t *bp) \
- { \
- float128 a; \
- float128 b; \
- \
- a = soft_to_qemu128(*ap); \
- b = soft_to_qemu128(*bp); \
- return !!func(a, b, &qsf); \
- }
-
-WRAP_CMP128(qemu_f128M_eq_signaling, float128_eq)
-WRAP_CMP128(qemu_f128M_eq, float128_eq_quiet)
-WRAP_CMP128(qemu_f128M_le, float128_le)
-WRAP_CMP128(qemu_f128M_lt, float128_lt)
-WRAP_CMP128(qemu_f128M_le_quiet, float128_le_quiet)
-WRAP_CMP128(qemu_f128M_lt_quiet, float128_lt_quiet)
-#undef WRAP_CMP128
#include "standard-headers/linux/input.h"
-#include "ui/input-keymap-atset1-to-qcode.c"
-#include "ui/input-keymap-linux-to-qcode.c"
-#include "ui/input-keymap-qcode-to-atset1.c"
-#include "ui/input-keymap-qcode-to-atset2.c"
-#include "ui/input-keymap-qcode-to-atset3.c"
-#include "ui/input-keymap-qcode-to-linux.c"
-#include "ui/input-keymap-qcode-to-qnum.c"
-#include "ui/input-keymap-qcode-to-sun.c"
-#include "ui/input-keymap-qnum-to-qcode.c"
-#include "ui/input-keymap-usb-to-qcode.c"
-#include "ui/input-keymap-win32-to-qcode.c"
-#include "ui/input-keymap-x11-to-qcode.c"
-#include "ui/input-keymap-xorgevdev-to-qcode.c"
-#include "ui/input-keymap-xorgkbd-to-qcode.c"
-#include "ui/input-keymap-xorgxquartz-to-qcode.c"
-#include "ui/input-keymap-xorgxwin-to-qcode.c"
-#include "ui/input-keymap-osx-to-qcode.c"
+#include "ui/input-keymap-atset1-to-qcode.c.inc"
+#include "ui/input-keymap-linux-to-qcode.c.inc"
+#include "ui/input-keymap-qcode-to-atset1.c.inc"
+#include "ui/input-keymap-qcode-to-atset2.c.inc"
+#include "ui/input-keymap-qcode-to-atset3.c.inc"
+#include "ui/input-keymap-qcode-to-linux.c.inc"
+#include "ui/input-keymap-qcode-to-qnum.c.inc"
+#include "ui/input-keymap-qcode-to-sun.c.inc"
+#include "ui/input-keymap-qnum-to-qcode.c.inc"
+#include "ui/input-keymap-usb-to-qcode.c.inc"
+#include "ui/input-keymap-win32-to-qcode.c.inc"
+#include "ui/input-keymap-x11-to-qcode.c.inc"
+#include "ui/input-keymap-xorgevdev-to-qcode.c.inc"
+#include "ui/input-keymap-xorgkbd-to-qcode.c.inc"
+#include "ui/input-keymap-xorgxquartz-to-qcode.c.inc"
+#include "ui/input-keymap-xorgxwin-to-qcode.c.inc"
+#include "ui/input-keymap-osx-to-qcode.c.inc"
int qemu_input_linux_to_qcode(unsigned int lnx)
{
#define ZRLE_BPP 8
#define ZYWRLE_ENDIAN ENDIAN_NO
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZRLE_BPP
#define ZRLE_BPP 15
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZRLE_BPP
#define ZRLE_BPP 16
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZRLE_BPP
#define ZRLE_BPP 32
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#define ZRLE_COMPACT_PIXEL 24a
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZRLE_COMPACT_PIXEL
#define ZRLE_COMPACT_PIXEL 24b
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
#undef ZRLE_COMPACT_PIXEL
#undef ZRLE_BPP
--- /dev/null
+/*
+ * QEMU VNC display driver: Zlib Run-length Encoding (ZRLE)
+ *
+ * From libvncserver/libvncserver/zrleencodetemplate.c
+ * Copyright (C) 2002 RealVNC Ltd. All Rights Reserved.
+ * Copyright (C) 2003 Sun Microsystems, Inc.
+ *
+ * Copyright (C) 2010 Corentin Chary <corentin.chary@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * Before including this file, you must define a number of CPP macros.
+ *
+ * ZRLE_BPP should be 8, 16 or 32 depending on the bits per pixel.
+ *
+ * Note that the buf argument to ZRLE_ENCODE needs to be at least one pixel
+ * bigger than the largest tile of pixel data, since the ZRLE encoding
+ * algorithm writes to the position one past the end of the pixel data.
+ */
+
+
+#include "qemu/osdep.h"
+
+#undef ZRLE_ENDIAN_SUFFIX
+
+#if ZYWRLE_ENDIAN == ENDIAN_LITTLE
+#define ZRLE_ENDIAN_SUFFIX le
+#elif ZYWRLE_ENDIAN == ENDIAN_BIG
+#define ZRLE_ENDIAN_SUFFIX be
+#else
+#define ZRLE_ENDIAN_SUFFIX ne
+#endif
+
+#ifndef ZRLE_CONCAT
+#define ZRLE_CONCAT_I(a, b) a##b
+#define ZRLE_CONCAT2(a, b) ZRLE_CONCAT_I(a, b)
+#define ZRLE_CONCAT3(a, b, c) ZRLE_CONCAT2(a, ZRLE_CONCAT2(b, c))
+#endif
+
+#ifdef ZRLE_COMPACT_PIXEL
+#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_COMPACT_PIXEL,ZRLE_ENDIAN_SUFFIX)
+#define ZRLE_WRITE_SUFFIX ZRLE_COMPACT_PIXEL
+#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t)
+#define ZRLE_BPP_OUT 24
+#elif ZRLE_BPP == 15
+#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX)
+#define ZRLE_WRITE_SUFFIX 16
+#define ZRLE_PIXEL uint16_t
+#define ZRLE_BPP_OUT 16
+#else
+#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX)
+#define ZRLE_WRITE_SUFFIX ZRLE_BPP
+#define ZRLE_BPP_OUT ZRLE_BPP
+#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t)
+#endif
+
+#define ZRLE_WRITE_PIXEL ZRLE_CONCAT2(zrle_write_u, ZRLE_WRITE_SUFFIX)
+#define ZRLE_ENCODE ZRLE_CONCAT2(zrle_encode_, ZRLE_ENCODE_SUFFIX)
+#define ZRLE_ENCODE_TILE ZRLE_CONCAT2(zrle_encode_tile, ZRLE_ENCODE_SUFFIX)
+#define ZRLE_WRITE_PALETTE ZRLE_CONCAT2(zrle_write_palette,ZRLE_ENCODE_SUFFIX)
+
+static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h,
+ int zywrle_level);
+
+#if ZRLE_BPP != 8
+#include "vnc-enc-zywrle-template.c"
+#endif
+
+
+static void ZRLE_ENCODE(VncState *vs, int x, int y, int w, int h,
+ int zywrle_level)
+{
+ int ty;
+
+ for (ty = y; ty < y + h; ty += VNC_ZRLE_TILE_HEIGHT) {
+
+ int tx, th;
+
+ th = MIN(VNC_ZRLE_TILE_HEIGHT, y + h - ty);
+
+ for (tx = x; tx < x + w; tx += VNC_ZRLE_TILE_WIDTH) {
+ int tw;
+ ZRLE_PIXEL *buf;
+
+ tw = MIN(VNC_ZRLE_TILE_WIDTH, x + w - tx);
+
+ buf = zrle_convert_fb(vs, tx, ty, tw, th, ZRLE_BPP);
+ ZRLE_ENCODE_TILE(vs, buf, tw, th, zywrle_level);
+ }
+ }
+}
+
+static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h,
+ int zywrle_level)
+{
+ VncPalette *palette = &vs->zrle->palette;
+
+ int runs = 0;
+ int single_pixels = 0;
+
+ bool use_rle;
+ bool use_palette;
+
+ int i;
+
+ ZRLE_PIXEL *ptr = data;
+ ZRLE_PIXEL *end = ptr + h * w;
+ *end = ~*(end-1); /* one past the end is different so the while loop ends */
+
+ /* Real limit is 127 but we wan't a way to know if there is more than 127 */
+ palette_init(palette, 256, ZRLE_BPP);
+
+ while (ptr < end) {
+ ZRLE_PIXEL pix = *ptr;
+ if (*++ptr != pix) { /* FIXME */
+ single_pixels++;
+ } else {
+ while (*++ptr == pix) ;
+ runs++;
+ }
+ palette_put(palette, pix);
+ }
+
+ /* Solid tile is a special case */
+
+ if (palette_size(palette) == 1) {
+ bool found;
+
+ vnc_write_u8(vs, 1);
+ ZRLE_WRITE_PIXEL(vs, palette_color(palette, 0, &found));
+ return;
+ }
+
+ zrle_choose_palette_rle(vs, w, h, palette, ZRLE_BPP_OUT,
+ runs, single_pixels, zywrle_level,
+ &use_rle, &use_palette);
+
+ if (!use_palette) {
+ vnc_write_u8(vs, (use_rle ? 128 : 0));
+ } else {
+ uint32_t colors[VNC_PALETTE_MAX_SIZE];
+ size_t size = palette_size(palette);
+
+ vnc_write_u8(vs, (use_rle ? 128 : 0) | size);
+ palette_fill(palette, colors);
+
+ for (i = 0; i < size; i++) {
+ ZRLE_WRITE_PIXEL(vs, colors[i]);
+ }
+ }
+
+ if (use_rle) {
+ ZRLE_PIXEL *ptr = data;
+ ZRLE_PIXEL *end = ptr + w * h;
+ ZRLE_PIXEL *run_start;
+ ZRLE_PIXEL pix;
+
+ while (ptr < end) {
+ int len;
+ int index = 0;
+
+ run_start = ptr;
+ pix = *ptr++;
+
+ while (*ptr == pix && ptr < end) {
+ ptr++;
+ }
+
+ len = ptr - run_start;
+
+ if (use_palette)
+ index = palette_idx(palette, pix);
+
+ if (len <= 2 && use_palette) {
+ if (len == 2) {
+ vnc_write_u8(vs, index);
+ }
+ vnc_write_u8(vs, index);
+ continue;
+ }
+ if (use_palette) {
+ vnc_write_u8(vs, index | 128);
+ } else {
+ ZRLE_WRITE_PIXEL(vs, pix);
+ }
+
+ len -= 1;
+
+ while (len >= 255) {
+ vnc_write_u8(vs, 255);
+ len -= 255;
+ }
+
+ vnc_write_u8(vs, len);
+ }
+ } else if (use_palette) { /* no RLE */
+ int bppp;
+ ZRLE_PIXEL *ptr = data;
+
+ /* packed pixels */
+
+ assert (palette_size(palette) < 17);
+
+ bppp = bits_per_packed_pixel[palette_size(palette)-1];
+
+ for (i = 0; i < h; i++) {
+ uint8_t nbits = 0;
+ uint8_t byte = 0;
+
+ ZRLE_PIXEL *eol = ptr + w;
+
+ while (ptr < eol) {
+ ZRLE_PIXEL pix = *ptr++;
+ uint8_t index = palette_idx(palette, pix);
+
+ byte = (byte << bppp) | index;
+ nbits += bppp;
+ if (nbits >= 8) {
+ vnc_write_u8(vs, byte);
+ nbits = 0;
+ }
+ }
+ if (nbits > 0) {
+ byte <<= 8 - nbits;
+ vnc_write_u8(vs, byte);
+ }
+ }
+ } else {
+
+ /* raw */
+
+#if ZRLE_BPP != 8
+ if (zywrle_level > 0 && !(zywrle_level & 0x80)) {
+ ZYWRLE_ANALYZE(data, data, w, h, w, zywrle_level, vs->zywrle.buf);
+ ZRLE_ENCODE_TILE(vs, data, w, h, zywrle_level | 0x80);
+ }
+ else
+#endif
+ {
+#ifdef ZRLE_COMPACT_PIXEL
+ ZRLE_PIXEL *ptr;
+
+ for (ptr = data; ptr < data + w * h; ptr++) {
+ ZRLE_WRITE_PIXEL(vs, *ptr);
+ }
+#else
+ vnc_write(vs, data, w * h * (ZRLE_BPP / 8));
+#endif
+ }
+ }
+}
+
+#undef ZRLE_PIXEL
+#undef ZRLE_WRITE_PIXEL
+#undef ZRLE_ENCODE
+#undef ZRLE_ENCODE_TILE
+#undef ZYWRLE_ENCODE_TILE
+#undef ZRLE_BPP_OUT
+#undef ZRLE_WRITE_SUFFIX
+#undef ZRLE_ENCODE_SUFFIX
+++ /dev/null
-/*
- * QEMU VNC display driver: Zlib Run-length Encoding (ZRLE)
- *
- * From libvncserver/libvncserver/zrleencodetemplate.c
- * Copyright (C) 2002 RealVNC Ltd. All Rights Reserved.
- * Copyright (C) 2003 Sun Microsystems, Inc.
- *
- * Copyright (C) 2010 Corentin Chary <corentin.chary@gmail.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-/*
- * Before including this file, you must define a number of CPP macros.
- *
- * ZRLE_BPP should be 8, 16 or 32 depending on the bits per pixel.
- *
- * Note that the buf argument to ZRLE_ENCODE needs to be at least one pixel
- * bigger than the largest tile of pixel data, since the ZRLE encoding
- * algorithm writes to the position one past the end of the pixel data.
- */
-
-
-#include "qemu/osdep.h"
-
-#undef ZRLE_ENDIAN_SUFFIX
-
-#if ZYWRLE_ENDIAN == ENDIAN_LITTLE
-#define ZRLE_ENDIAN_SUFFIX le
-#elif ZYWRLE_ENDIAN == ENDIAN_BIG
-#define ZRLE_ENDIAN_SUFFIX be
-#else
-#define ZRLE_ENDIAN_SUFFIX ne
-#endif
-
-#ifndef ZRLE_CONCAT
-#define ZRLE_CONCAT_I(a, b) a##b
-#define ZRLE_CONCAT2(a, b) ZRLE_CONCAT_I(a, b)
-#define ZRLE_CONCAT3(a, b, c) ZRLE_CONCAT2(a, ZRLE_CONCAT2(b, c))
-#endif
-
-#ifdef ZRLE_COMPACT_PIXEL
-#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_COMPACT_PIXEL,ZRLE_ENDIAN_SUFFIX)
-#define ZRLE_WRITE_SUFFIX ZRLE_COMPACT_PIXEL
-#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t)
-#define ZRLE_BPP_OUT 24
-#elif ZRLE_BPP == 15
-#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX)
-#define ZRLE_WRITE_SUFFIX 16
-#define ZRLE_PIXEL uint16_t
-#define ZRLE_BPP_OUT 16
-#else
-#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX)
-#define ZRLE_WRITE_SUFFIX ZRLE_BPP
-#define ZRLE_BPP_OUT ZRLE_BPP
-#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t)
-#endif
-
-#define ZRLE_WRITE_PIXEL ZRLE_CONCAT2(zrle_write_u, ZRLE_WRITE_SUFFIX)
-#define ZRLE_ENCODE ZRLE_CONCAT2(zrle_encode_, ZRLE_ENCODE_SUFFIX)
-#define ZRLE_ENCODE_TILE ZRLE_CONCAT2(zrle_encode_tile, ZRLE_ENCODE_SUFFIX)
-#define ZRLE_WRITE_PALETTE ZRLE_CONCAT2(zrle_write_palette,ZRLE_ENCODE_SUFFIX)
-
-static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h,
- int zywrle_level);
-
-#if ZRLE_BPP != 8
-#include "vnc-enc-zywrle-template.c"
-#endif
-
-
-static void ZRLE_ENCODE(VncState *vs, int x, int y, int w, int h,
- int zywrle_level)
-{
- int ty;
-
- for (ty = y; ty < y + h; ty += VNC_ZRLE_TILE_HEIGHT) {
-
- int tx, th;
-
- th = MIN(VNC_ZRLE_TILE_HEIGHT, y + h - ty);
-
- for (tx = x; tx < x + w; tx += VNC_ZRLE_TILE_WIDTH) {
- int tw;
- ZRLE_PIXEL *buf;
-
- tw = MIN(VNC_ZRLE_TILE_WIDTH, x + w - tx);
-
- buf = zrle_convert_fb(vs, tx, ty, tw, th, ZRLE_BPP);
- ZRLE_ENCODE_TILE(vs, buf, tw, th, zywrle_level);
- }
- }
-}
-
-static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h,
- int zywrle_level)
-{
- VncPalette *palette = &vs->zrle->palette;
-
- int runs = 0;
- int single_pixels = 0;
-
- bool use_rle;
- bool use_palette;
-
- int i;
-
- ZRLE_PIXEL *ptr = data;
- ZRLE_PIXEL *end = ptr + h * w;
- *end = ~*(end-1); /* one past the end is different so the while loop ends */
-
- /* Real limit is 127 but we wan't a way to know if there is more than 127 */
- palette_init(palette, 256, ZRLE_BPP);
-
- while (ptr < end) {
- ZRLE_PIXEL pix = *ptr;
- if (*++ptr != pix) { /* FIXME */
- single_pixels++;
- } else {
- while (*++ptr == pix) ;
- runs++;
- }
- palette_put(palette, pix);
- }
-
- /* Solid tile is a special case */
-
- if (palette_size(palette) == 1) {
- bool found;
-
- vnc_write_u8(vs, 1);
- ZRLE_WRITE_PIXEL(vs, palette_color(palette, 0, &found));
- return;
- }
-
- zrle_choose_palette_rle(vs, w, h, palette, ZRLE_BPP_OUT,
- runs, single_pixels, zywrle_level,
- &use_rle, &use_palette);
-
- if (!use_palette) {
- vnc_write_u8(vs, (use_rle ? 128 : 0));
- } else {
- uint32_t colors[VNC_PALETTE_MAX_SIZE];
- size_t size = palette_size(palette);
-
- vnc_write_u8(vs, (use_rle ? 128 : 0) | size);
- palette_fill(palette, colors);
-
- for (i = 0; i < size; i++) {
- ZRLE_WRITE_PIXEL(vs, colors[i]);
- }
- }
-
- if (use_rle) {
- ZRLE_PIXEL *ptr = data;
- ZRLE_PIXEL *end = ptr + w * h;
- ZRLE_PIXEL *run_start;
- ZRLE_PIXEL pix;
-
- while (ptr < end) {
- int len;
- int index = 0;
-
- run_start = ptr;
- pix = *ptr++;
-
- while (*ptr == pix && ptr < end) {
- ptr++;
- }
-
- len = ptr - run_start;
-
- if (use_palette)
- index = palette_idx(palette, pix);
-
- if (len <= 2 && use_palette) {
- if (len == 2) {
- vnc_write_u8(vs, index);
- }
- vnc_write_u8(vs, index);
- continue;
- }
- if (use_palette) {
- vnc_write_u8(vs, index | 128);
- } else {
- ZRLE_WRITE_PIXEL(vs, pix);
- }
-
- len -= 1;
-
- while (len >= 255) {
- vnc_write_u8(vs, 255);
- len -= 255;
- }
-
- vnc_write_u8(vs, len);
- }
- } else if (use_palette) { /* no RLE */
- int bppp;
- ZRLE_PIXEL *ptr = data;
-
- /* packed pixels */
-
- assert (palette_size(palette) < 17);
-
- bppp = bits_per_packed_pixel[palette_size(palette)-1];
-
- for (i = 0; i < h; i++) {
- uint8_t nbits = 0;
- uint8_t byte = 0;
-
- ZRLE_PIXEL *eol = ptr + w;
-
- while (ptr < eol) {
- ZRLE_PIXEL pix = *ptr++;
- uint8_t index = palette_idx(palette, pix);
-
- byte = (byte << bppp) | index;
- nbits += bppp;
- if (nbits >= 8) {
- vnc_write_u8(vs, byte);
- nbits = 0;
- }
- }
- if (nbits > 0) {
- byte <<= 8 - nbits;
- vnc_write_u8(vs, byte);
- }
- }
- } else {
-
- /* raw */
-
-#if ZRLE_BPP != 8
- if (zywrle_level > 0 && !(zywrle_level & 0x80)) {
- ZYWRLE_ANALYZE(data, data, w, h, w, zywrle_level, vs->zywrle.buf);
- ZRLE_ENCODE_TILE(vs, data, w, h, zywrle_level | 0x80);
- }
- else
-#endif
- {
-#ifdef ZRLE_COMPACT_PIXEL
- ZRLE_PIXEL *ptr;
-
- for (ptr = data; ptr < data + w * h; ptr++) {
- ZRLE_WRITE_PIXEL(vs, *ptr);
- }
-#else
- vnc_write(vs, data, w * h * (ZRLE_BPP / 8));
-#endif
- }
- }
-}
-
-#undef ZRLE_PIXEL
-#undef ZRLE_WRITE_PIXEL
-#undef ZRLE_ENCODE
-#undef ZRLE_ENCODE_TILE
-#undef ZYWRLE_ENCODE_TILE
-#undef ZRLE_BPP_OUT
-#undef ZRLE_WRITE_SUFFIX
-#undef ZRLE_ENCODE_SUFFIX
projects / qemu.git / commitdiff